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gerrit-public.fairphone.software / toolchain / llvm-project / af318f7073eb1d0dc575bc74e39c78bbe8e9e05d / . / llvm / lib / Target / X86 / X86InstrAVX512.td
blob: 3ff37d4537673e60dfb6307e2766191ff8b3fde1 [file] [log] [blame]
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]1// Group template arguments that can be derived from the vector type (EltNum x
2// EltVT). These are things like the register class for the writemask, etc.
3// The idea is to pass one of these as the template argument rather than the
4// individual arguments.
Adam Nemet449b3f02014-10-15 23:42:09 +0000[diff] [blame]5class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc,
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]6 string suffix = ""> {
7 RegisterClass RC = rc;
Adam Nemet449b3f02014-10-15 23:42:09 +0000[diff] [blame]8 int NumElts = numelts;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]9
10 // Corresponding mask register class.
11 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
12
13 // Corresponding write-mask register class.
14 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
15
16 // The GPR register class that can hold the write mask. Use GR8 for fewer
17 // than 8 elements. Use shift-right and equal to work around the lack of
18 // !lt in tablegen.
19 RegisterClass MRC =
20 !cast<RegisterClass>("GR" #
21 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
22
23 // Suffix used in the instruction mnemonic.
24 string Suffix = suffix;
25
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]26 string VTName = "v" # NumElts # EltVT;
27
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]28 // The vector VT.
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]29 ValueType VT = !cast<ValueType>(VTName);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]30
31 string EltTypeName = !cast<string>(EltVT);
32 // Size of the element type in bits, e.g. 32 for v16i32.
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]33 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
34 int EltSize = EltVT.Size;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]35
36 // "i" for integer types and "f" for floating-point types
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]37 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]38
39 // Size of RC in bits, e.g. 512 for VR512.
40 int Size = VT.Size;
41
42 // The corresponding memory operand, e.g. i512mem for VR512.
43 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]44 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
45
46 // Load patterns
47 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
48 // due to load promotion during legalization
49 PatFrag LdFrag = !cast<PatFrag>("load" #
50 !if (!eq (TypeVariantName, "i"),
51 !if (!eq (Size, 128), "v2i64",
52 !if (!eq (Size, 256), "v4i64",
53 VTName)), VTName));
54 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]55
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]56 // Load patterns used for memory operands. We only have this defined in
57 // case of i64 element types for sub-512 integer vectors. For now, keep
58 // MemOpFrag undefined in these cases.
59 PatFrag MemOpFrag =
60 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
61 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
62 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
63
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]64 // The corresponding float type, e.g. v16f32 for v16i32
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]65 // Note: For EltSize < 32, FloatVT is illegal and TableGen
66 // fails to compile, so we choose FloatVT = VT
67 ValueType FloatVT = !cast<ValueType>(
68 !if (!eq (!srl(EltSize,5),0),
69 VTName,
70 !if (!eq(TypeVariantName, "i"),
71 "v" # NumElts # "f" # EltSize,
72 VTName)));
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]73
74 // The string to specify embedded broadcast in assembly.
75 string BroadcastStr = "{1to" # NumElts # "}";
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]76
Adam Nemet449b3f02014-10-15 23:42:09 +0000[diff] [blame]77 // 8-bit compressed displacement tuple/subvector format. This is only
78 // defined for NumElts <= 8.
79 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
80 !cast<CD8VForm>("CD8VT" # NumElts), ?);
81
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]82 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
83 !if (!eq (Size, 256), sub_ymm, ?));
84
85 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
86 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
87 SSEPackedInt));
Adam Nemet09377232014-10-08 23:25:31 +0000[diff] [blame]88
89 // A vector type of the same width with element type i32. This is used to
90 // create the canonical constant zero node ImmAllZerosV.
91 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
92 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]93}
94
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]95def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
96def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]97def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
98def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]99def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
100def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]101
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]102// "x" in v32i8x_info means RC = VR256X
103def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
104def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
105def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
106def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
Robert Khasanov3e534c92014-10-28 16:37:13 +0000[diff] [blame]107def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
108def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]109
110def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
111def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
112def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
113def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
Robert Khasanov3e534c92014-10-28 16:37:13 +0000[diff] [blame]114def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
115def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]116
117class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
118 X86VectorVTInfo i128> {
119 X86VectorVTInfo info512 = i512;
120 X86VectorVTInfo info256 = i256;
121 X86VectorVTInfo info128 = i128;
122}
123
124def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
125 v16i8x_info>;
126def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
127 v8i16x_info>;
128def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
129 v4i32x_info>;
130def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
131 v2i64x_info>;
Robert Khasanovaf318f72014-10-30 14:21:47 +0000[diff] [blame^]132def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
133 v4f32x_info>;
134def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
135 v2f64x_info>;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]136
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000[diff] [blame]137// This multiclass generates the masking variants from the non-masking
138// variant. It only provides the assembly pieces for the masking variants.
139// It assumes custom ISel patterns for masking which can be provided as
140// template arguments.
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]141multiclass AVX512_maskable_custom<bits<8> O, Format F,
142 dag Outs,
143 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
144 string OpcodeStr,
145 string AttSrcAsm, string IntelSrcAsm,
146 list<dag> Pattern,
147 list<dag> MaskingPattern,
148 list<dag> ZeroMaskingPattern,
149 string MaskingConstraint = "",
150 InstrItinClass itin = NoItinerary,
151 bit IsCommutable = 0> {
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000[diff] [blame]152 let isCommutable = IsCommutable in
153 def NAME: AVX512<O, F, Outs, Ins,
154 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
155 "$dst, "#IntelSrcAsm#"}",
156 Pattern, itin>;
157
158 // Prefer over VMOV*rrk Pat<>
159 let AddedComplexity = 20 in
160 def NAME#k: AVX512<O, F, Outs, MaskingIns,
161 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
162 "$dst {${mask}}, "#IntelSrcAsm#"}",
163 MaskingPattern, itin>,
164 EVEX_K {
165 // In case of the 3src subclass this is overridden with a let.
166 string Constraints = MaskingConstraint;
167 }
168 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
169 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
170 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
171 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
172 ZeroMaskingPattern,
173 itin>,
174 EVEX_KZ;
175}
176
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]177
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]178// Common base class of AVX512_maskable and AVX512_maskable_3src.
179multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
180 dag Outs,
181 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
182 string OpcodeStr,
183 string AttSrcAsm, string IntelSrcAsm,
184 dag RHS, dag MaskingRHS,
185 string MaskingConstraint = "",
186 InstrItinClass itin = NoItinerary,
187 bit IsCommutable = 0> :
188 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
189 AttSrcAsm, IntelSrcAsm,
190 [(set _.RC:$dst, RHS)],
191 [(set _.RC:$dst, MaskingRHS)],
192 [(set _.RC:$dst,
193 (vselect _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
194 MaskingConstraint, NoItinerary, IsCommutable>;
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]195
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]196// This multiclass generates the unconditional/non-masking, the masking and
197// the zero-masking variant of the instruction. In the masking case, the
198// perserved vector elements come from a new dummy input operand tied to $dst.
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]199multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
200 dag Outs, dag Ins, string OpcodeStr,
201 string AttSrcAsm, string IntelSrcAsm,
202 dag RHS, InstrItinClass itin = NoItinerary,
203 bit IsCommutable = 0> :
204 AVX512_maskable_common<O, F, _, Outs, Ins,
205 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
206 !con((ins _.KRCWM:$mask), Ins),
207 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
208 (vselect _.KRCWM:$mask, RHS, _.RC:$src0),
209 "$src0 = $dst", itin, IsCommutable>;
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]210
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]211// Similar to AVX512_maskable but in this case one of the source operands
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]212// ($src1) is already tied to $dst so we just use that for the preserved
213// vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
214// $src1.
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]215multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
216 dag Outs, dag NonTiedIns, string OpcodeStr,
217 string AttSrcAsm, string IntelSrcAsm,
218 dag RHS> :
219 AVX512_maskable_common<O, F, _, Outs,
220 !con((ins _.RC:$src1), NonTiedIns),
221 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
222 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
223 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
224 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]225
Adam Nemet2b5cdbb2014-10-08 23:25:33 +0000[diff] [blame]226
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]227multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
228 dag Outs, dag Ins,
229 string OpcodeStr,
230 string AttSrcAsm, string IntelSrcAsm,
231 list<dag> Pattern> :
232 AVX512_maskable_custom<O, F, Outs, Ins,
233 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
234 !con((ins _.KRCWM:$mask), Ins),
235 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
236 "$src0 = $dst">;
Adam Nemet2b5cdbb2014-10-08 23:25:33 +0000[diff] [blame]237
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]238// Bitcasts between 512-bit vector types. Return the original type since
239// no instruction is needed for the conversion
240let Predicates = [HasAVX512] in {
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]241 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]242 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]243 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
244 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
245 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]246 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]247 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
248 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
249 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]250 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]251 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]252 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
253 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]254 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]255 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
256 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovsky40a77142014-08-11 09:59:08 +0000[diff] [blame]257 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]258 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
259 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]260 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]261 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
262 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
263 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
264 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
265 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
266 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
267 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
268 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
269 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
270 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
271 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]272
273 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
274 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
275 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
276 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
277 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
278 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
279 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
280 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
281 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
282 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
283 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
284 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
285 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
286 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
287 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
288 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
289 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
290 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
291 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
292 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
293 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
294 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
295 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
296 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
297 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
298 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
299 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
300 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
301 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
302 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
303
304// Bitcasts between 256-bit vector types. Return the original type since
305// no instruction is needed for the conversion
306 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
307 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
308 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
309 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
310 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
311 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
312 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
313 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
314 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
315 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
316 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
317 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
318 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
319 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
320 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
321 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
322 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
323 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
324 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
325 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
326 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
327 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
328 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
329 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
330 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
331 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
332 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
333 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
334 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
335 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
336}
337
338//
339// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
340//
341
342let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
343 isPseudo = 1, Predicates = [HasAVX512] in {
344def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
345 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
346}
347
Craig Topperfb1746b2014-01-30 06:03:19 +0000[diff] [blame]348let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]349def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
350def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
351def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
Craig Topperfb1746b2014-01-30 06:03:19 +0000[diff] [blame]352}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]353
354//===----------------------------------------------------------------------===//
355// AVX-512 - VECTOR INSERT
356//
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]357
Adam Nemet4285c1f2014-10-15 23:42:17 +0000[diff] [blame]358multiclass vinsert_for_size_no_alt<int Opcode,
359 X86VectorVTInfo From, X86VectorVTInfo To,
360 PatFrag vinsert_insert,
361 SDNodeXForm INSERT_get_vinsert_imm> {
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]362 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
363 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
364 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
Adam Nemet449b3f02014-10-15 23:42:09 +0000[diff] [blame]365 "vinsert" # From.EltTypeName # "x" # From.NumElts #
366 "\t{$src3, $src2, $src1, $dst|"
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]367 "$dst, $src1, $src2, $src3}",
Adam Nemet4dca3ce2014-10-02 23:18:30 +0000[diff] [blame]368 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
369 (From.VT From.RC:$src2),
370 (iPTR imm)))]>,
371 EVEX_4V, EVEX_V512;
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]372
373 let mayLoad = 1 in
374 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
375 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
Adam Nemet449b3f02014-10-15 23:42:09 +0000[diff] [blame]376 "vinsert" # From.EltTypeName # "x" # From.NumElts #
377 "\t{$src3, $src2, $src1, $dst|"
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]378 "$dst, $src1, $src2, $src3}",
Adam Nemet449b3f02014-10-15 23:42:09 +0000[diff] [blame]379 []>,
380 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]381 }
Adam Nemet4285c1f2014-10-15 23:42:17 +0000[diff] [blame]382}
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]383
Adam Nemet4285c1f2014-10-15 23:42:17 +0000[diff] [blame]384multiclass vinsert_for_size<int Opcode,
385 X86VectorVTInfo From, X86VectorVTInfo To,
386 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
387 PatFrag vinsert_insert,
388 SDNodeXForm INSERT_get_vinsert_imm> :
389 vinsert_for_size_no_alt<Opcode, From, To,
390 vinsert_insert, INSERT_get_vinsert_imm> {
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]391 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
Adam Nemet4285c1f2014-10-15 23:42:17 +0000[diff] [blame]392 // vinserti32x4. Only add this if 64x2 and friends are not supported
393 // natively via AVX512DQ.
394 let Predicates = [NoDQI] in
395 def : Pat<(vinsert_insert:$ins
396 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
397 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
398 VR512:$src1, From.RC:$src2,
399 (INSERT_get_vinsert_imm VR512:$ins)))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]400}
401
Adam Nemetb1c3ef42014-10-15 23:42:04 +0000[diff] [blame]402multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
403 ValueType EltVT64, int Opcode256> {
404 defm NAME # "32x4" : vinsert_for_size<Opcode128,
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]405 X86VectorVTInfo< 4, EltVT32, VR128X>,
406 X86VectorVTInfo<16, EltVT32, VR512>,
407 X86VectorVTInfo< 2, EltVT64, VR128X>,
408 X86VectorVTInfo< 8, EltVT64, VR512>,
409 vinsert128_insert,
410 INSERT_get_vinsert128_imm>;
Adam Nemet4285c1f2014-10-15 23:42:17 +0000[diff] [blame]411 let Predicates = [HasDQI] in
412 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
413 X86VectorVTInfo< 2, EltVT64, VR128X>,
414 X86VectorVTInfo< 8, EltVT64, VR512>,
415 vinsert128_insert,
416 INSERT_get_vinsert128_imm>, VEX_W;
Adam Nemetb1c3ef42014-10-15 23:42:04 +0000[diff] [blame]417 defm NAME # "64x4" : vinsert_for_size<Opcode256,
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]418 X86VectorVTInfo< 4, EltVT64, VR256X>,
419 X86VectorVTInfo< 8, EltVT64, VR512>,
420 X86VectorVTInfo< 8, EltVT32, VR256>,
421 X86VectorVTInfo<16, EltVT32, VR512>,
422 vinsert256_insert,
423 INSERT_get_vinsert256_imm>, VEX_W;
Adam Nemet4285c1f2014-10-15 23:42:17 +0000[diff] [blame]424 let Predicates = [HasDQI] in
425 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
426 X86VectorVTInfo< 8, EltVT32, VR256X>,
427 X86VectorVTInfo<16, EltVT32, VR512>,
428 vinsert256_insert,
429 INSERT_get_vinsert256_imm>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]430}
431
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]432defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
433defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]434
435// vinsertps - insert f32 to XMM
436def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]437 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]438 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]439 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]440 EVEX_4V;
441def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]442 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]443 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]444 [(set VR128X:$dst, (X86insertps VR128X:$src1,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]445 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
446 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
447
448//===----------------------------------------------------------------------===//
449// AVX-512 VECTOR EXTRACT
450//---
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]451
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]452multiclass vextract_for_size<int Opcode,
453 X86VectorVTInfo From, X86VectorVTInfo To,
454 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
455 PatFrag vextract_extract,
456 SDNodeXForm EXTRACT_get_vextract_imm> {
457 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]458 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
Adam Nemet2b5cdbb2014-10-08 23:25:33 +0000[diff] [blame]459 (ins VR512:$src1, i8imm:$idx),
460 "vextract" # To.EltTypeName # "x4",
461 "$idx, $src1", "$src1, $idx",
462 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
463 (iPTR imm)))]>,
464 AVX512AIi8Base, EVEX, EVEX_V512;
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]465 let mayStore = 1 in
466 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
467 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
468 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
469 "$dst, $src1, $src2}",
470 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
471 }
472
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]473 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
474 // vextracti32x4
475 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
476 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
477 VR512:$src1,
478 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
479
480 // A 128/256-bit subvector extract from the first 512-bit vector position is
481 // a subregister copy that needs no instruction.
482 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
483 (To.VT
484 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
485
486 // And for the alternative types.
487 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
488 (AltTo.VT
489 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
Adam Nemet47b2d5f2014-10-08 23:25:37 +0000[diff] [blame]490
491 // Intrinsic call with masking.
492 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
493 "x4_512")
494 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
495 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
496 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
497 VR512:$src1, imm:$idx)>;
498
499 // Intrinsic call with zero-masking.
500 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
501 "x4_512")
502 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
503 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
504 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
505 VR512:$src1, imm:$idx)>;
506
507 // Intrinsic call without masking.
508 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
509 "x4_512")
510 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
511 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
512 VR512:$src1, imm:$idx)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]513}
514
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]515multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
516 ValueType EltVT64, int Opcode64> {
517 defm NAME # "32x4" : vextract_for_size<Opcode32,
518 X86VectorVTInfo<16, EltVT32, VR512>,
519 X86VectorVTInfo< 4, EltVT32, VR128X>,
520 X86VectorVTInfo< 8, EltVT64, VR512>,
521 X86VectorVTInfo< 2, EltVT64, VR128X>,
522 vextract128_extract,
523 EXTRACT_get_vextract128_imm>;
524 defm NAME # "64x4" : vextract_for_size<Opcode64,
525 X86VectorVTInfo< 8, EltVT64, VR512>,
526 X86VectorVTInfo< 4, EltVT64, VR256X>,
527 X86VectorVTInfo<16, EltVT32, VR512>,
528 X86VectorVTInfo< 8, EltVT32, VR256>,
529 vextract256_extract,
530 EXTRACT_get_vextract256_imm>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]531}
532
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]533defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
534defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]535
536// A 128-bit subvector insert to the first 512-bit vector position
537// is a subregister copy that needs no instruction.
538def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
539 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
540 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
541 sub_ymm)>;
542def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
543 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
544 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
545 sub_ymm)>;
546def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
547 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
548 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
549 sub_ymm)>;
550def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
551 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
552 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
553 sub_ymm)>;
554
555def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
556 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
557def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
558 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
559def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
560 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
561def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
562 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
563
564// vextractps - extract 32 bits from XMM
565def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]566 (ins VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]567 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]568 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
569 EVEX;
570
571def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]572 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]573 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]574 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
Elena Demikhovsky2aafc222014-02-11 07:25:59 +0000[diff] [blame]575 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]576
577//===---------------------------------------------------------------------===//
578// AVX-512 BROADCAST
579//---
Robert Khasanovaf318f72014-10-30 14:21:47 +0000[diff] [blame^]580multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
581 ValueType svt, X86VectorVTInfo _> {
582 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
583 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
584 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
585 T8PD, EVEX;
586
587 let mayLoad = 1 in {
588 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
589 (ins _.ScalarMemOp:$src),
590 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
591 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
592 T8PD, EVEX;
593 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]594}
Robert Khasanovaf318f72014-10-30 14:21:47 +0000[diff] [blame^]595
596multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
597 AVX512VLVectorVTInfo _> {
598 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
599 EVEX_V512;
600
601 let Predicates = [HasVLX] in {
602 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
603 EVEX_V256;
604 }
605}
606
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]607let ExeDomain = SSEPackedSingle in {
Robert Khasanovaf318f72014-10-30 14:21:47 +0000[diff] [blame^]608 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
609 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
610 let Predicates = [HasVLX] in {
611 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
612 v4f32, v4f32x_info>, EVEX_V128,
613 EVEX_CD8<32, CD8VT1>;
614 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]615}
616
617let ExeDomain = SSEPackedDouble in {
Robert Khasanovaf318f72014-10-30 14:21:47 +0000[diff] [blame^]618 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
619 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]620}
621
622def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000[diff] [blame^]623 (VBROADCASTSSZm addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]624def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000[diff] [blame^]625 (VBROADCASTSDZm addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]626
Quentin Colombet4bf1c282013-10-25 17:47:18 +0000[diff] [blame]627def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000[diff] [blame^]628 (VBROADCASTSSZm addr:$src)>;
Quentin Colombet4bf1c282013-10-25 17:47:18 +0000[diff] [blame]629def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000[diff] [blame^]630 (VBROADCASTSDZm addr:$src)>;
Quentin Colombet4bf1c282013-10-25 17:47:18 +0000[diff] [blame]631
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]632multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
633 RegisterClass SrcRC, RegisterClass KRC> {
634 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]635 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]636 []>, EVEX, EVEX_V512;
637 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
638 (ins KRC:$mask, SrcRC:$src),
639 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]640 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]641 []>, EVEX, EVEX_V512, EVEX_KZ;
642}
643
644defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
645defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
646 VEX_W;
647
648def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
649 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
650
651def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
652 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
653
654def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
655 (VPBROADCASTDrZrr GR32:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +0000[diff] [blame]656def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
657 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]658def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
659 (VPBROADCASTQrZrr GR64:$src)>;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]660def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
661 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]662
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]663def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
664 (VPBROADCASTDrZrr GR32:$src)>;
665def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
666 (VPBROADCASTQrZrr GR64:$src)>;
667
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]668def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
669 (v16i32 immAllZerosV), (i16 GR16:$mask))),
670 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
671def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
672 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
673 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
674
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]675multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
676 X86MemOperand x86memop, PatFrag ld_frag,
677 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
678 RegisterClass KRC> {
679 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]680 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]681 [(set DstRC:$dst,
682 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
683 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
684 VR128X:$src),
685 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]686 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]687 [(set DstRC:$dst,
688 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
689 EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]690 let mayLoad = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]691 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]692 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]693 [(set DstRC:$dst,
694 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
695 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
696 x86memop:$src),
697 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]698 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]699 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
700 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]701 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]702}
703
704defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
705 loadi32, VR512, v16i32, v4i32, VK16WM>,
706 EVEX_V512, EVEX_CD8<32, CD8VT1>;
707defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
708 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
709 EVEX_CD8<64, CD8VT1>;
710
Adam Nemet73f72e12014-06-27 00:43:38 +0000[diff] [blame]711multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
712 X86MemOperand x86memop, PatFrag ld_frag,
713 RegisterClass KRC> {
714 let mayLoad = 1 in {
715 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
716 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
717 []>, EVEX;
718 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
719 x86memop:$src),
720 !strconcat(OpcodeStr,
721 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
722 []>, EVEX, EVEX_KZ;
723 }
724}
725
726defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
727 i128mem, loadv2i64, VK16WM>,
728 EVEX_V512, EVEX_CD8<32, CD8VT4>;
729defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
730 i256mem, loadv4i64, VK16WM>, VEX_W,
731 EVEX_V512, EVEX_CD8<64, CD8VT4>;
732
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]733def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
734 (VPBROADCASTDZrr VR128X:$src)>;
735def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
736 (VPBROADCASTQZrr VR128X:$src)>;
737
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]738def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000[diff] [blame^]739 (VBROADCASTSSZr VR128X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]740def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000[diff] [blame^]741 (VBROADCASTSDZr VR128X:$src)>;
Quentin Colombet8761a8f2013-10-25 18:04:12 +0000[diff] [blame]742
Robert Khasanovdd09a8f2014-10-28 12:28:51 +0000[diff] [blame]743def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000[diff] [blame^]744 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
Robert Khasanovdd09a8f2014-10-28 12:28:51 +0000[diff] [blame]745def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000[diff] [blame^]746 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
Robert Khasanovdd09a8f2014-10-28 12:28:51 +0000[diff] [blame]747
748def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
749 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
750def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
751 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
752
Quentin Colombet8761a8f2013-10-25 18:04:12 +0000[diff] [blame]753def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000[diff] [blame^]754 (VBROADCASTSSZr VR128X:$src)>;
Quentin Colombet8761a8f2013-10-25 18:04:12 +0000[diff] [blame]755def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000[diff] [blame^]756 (VBROADCASTSDZr VR128X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]757
758// Provide fallback in case the load node that is used in the patterns above
759// is used by additional users, which prevents the pattern selection.
760def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000[diff] [blame^]761 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]762def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000[diff] [blame^]763 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]764
765
766let Predicates = [HasAVX512] in {
767def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
768 (EXTRACT_SUBREG
769 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
770 addr:$src)), sub_ymm)>;
771}
772//===----------------------------------------------------------------------===//
773// AVX-512 BROADCAST MASK TO VECTOR REGISTER
774//---
775
776multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
Elena Demikhovsky4b01b732014-10-26 09:52:24 +0000[diff] [blame]777 RegisterClass KRC> {
778let Predicates = [HasCDI] in
779def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]780 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky4b01b732014-10-26 09:52:24 +0000[diff] [blame]781 []>, EVEX, EVEX_V512;
782
783let Predicates = [HasCDI, HasVLX] in {
784def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
785 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
786 []>, EVEX, EVEX_V128;
787def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
788 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
789 []>, EVEX, EVEX_V256;
790}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]791}
792
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000[diff] [blame]793let Predicates = [HasCDI] in {
Elena Demikhovsky4b01b732014-10-26 09:52:24 +0000[diff] [blame]794defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
795 VK16>;
796defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
797 VK8>, VEX_W;
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000[diff] [blame]798}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]799
800//===----------------------------------------------------------------------===//
801// AVX-512 - VPERM
802//
803// -- immediate form --
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]804multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
805 X86VectorVTInfo _> {
806 let ExeDomain = _.ExeDomain in {
807 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
808 (ins _.RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]809 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]810 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]811 [(set _.RC:$dst,
812 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]813 EVEX;
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]814 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
815 (ins _.MemOp:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]816 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]817 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]818 [(set _.RC:$dst,
819 (_.VT (OpNode (_.MemOpFrag addr:$src1),
820 (i8 imm:$src2))))]>,
821 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
822}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]823}
824
Adam Nemetcf7a4a22014-10-27 23:08:40 +0000[diff] [blame]825multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
826 X86VectorVTInfo Ctrl> :
827 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
828 let ExeDomain = _.ExeDomain in {
829 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
830 (ins _.RC:$src1, _.RC:$src2),
831 !strconcat("vpermil" # _.Suffix,
832 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
833 [(set _.RC:$dst,
834 (_.VT (X86VPermilpv _.RC:$src1,
835 (Ctrl.VT Ctrl.RC:$src2))))]>,
836 EVEX_4V;
837 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
838 (ins _.RC:$src1, Ctrl.MemOp:$src2),
839 !strconcat("vpermil" # _.Suffix,
840 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
841 [(set _.RC:$dst,
842 (_.VT (X86VPermilpv _.RC:$src1,
843 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>,
844 EVEX_4V;
845 }
846}
847
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]848defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
849 EVEX_V512, VEX_W;
850defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
851 EVEX_V512, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]852
Adam Nemetcf7a4a22014-10-27 23:08:40 +0000[diff] [blame]853defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]854 EVEX_V512;
Adam Nemetcf7a4a22014-10-27 23:08:40 +0000[diff] [blame]855defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]856 EVEX_V512, VEX_W;
Adam Nemet9aad1312014-10-27 23:08:34 +0000[diff] [blame]857
858def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
859 (VPERMILPSZri VR512:$src1, imm:$imm)>;
860def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
861 (VPERMILPDZri VR512:$src1, imm:$imm)>;
862
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]863// -- VPERM - register form --
864multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
865 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
866
867 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
868 (ins RC:$src1, RC:$src2),
869 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]870 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]871 [(set RC:$dst,
872 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
873
874 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
875 (ins RC:$src1, x86memop:$src2),
876 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]877 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]878 [(set RC:$dst,
879 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
880 EVEX_4V;
881}
882
883defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
884 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
885defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
886 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
887let ExeDomain = SSEPackedSingle in
888defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
889 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
890let ExeDomain = SSEPackedDouble in
891defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
892 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
893
894// -- VPERM2I - 3 source operands form --
895multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
896 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]897 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]898let Constraints = "$src1 = $dst" in {
899 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
900 (ins RC:$src1, RC:$src2, RC:$src3),
901 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]902 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]903 [(set RC:$dst,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]904 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]905 EVEX_4V;
906
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]907 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
908 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
909 !strconcat(OpcodeStr,
910 " \t{$src3, $src2, $dst {${mask}}|"
911 "$dst {${mask}}, $src2, $src3}"),
912 [(set RC:$dst, (OpVT (vselect KRC:$mask,
913 (OpNode RC:$src1, RC:$src2,
914 RC:$src3),
915 RC:$src1)))]>,
916 EVEX_4V, EVEX_K;
917
918 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
919 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
920 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
921 !strconcat(OpcodeStr,
922 " \t{$src3, $src2, $dst {${mask}} {z} |",
923 "$dst {${mask}} {z}, $src2, $src3}"),
924 [(set RC:$dst, (OpVT (vselect KRC:$mask,
925 (OpNode RC:$src1, RC:$src2,
926 RC:$src3),
927 (OpVT (bitconvert
928 (v16i32 immAllZerosV))))))]>,
929 EVEX_4V, EVEX_KZ;
930
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]931 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
932 (ins RC:$src1, RC:$src2, x86memop:$src3),
933 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]934 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]935 [(set RC:$dst,
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]936 (OpVT (OpNode RC:$src1, RC:$src2,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]937 (mem_frag addr:$src3))))]>, EVEX_4V;
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]938
939 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
940 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
941 !strconcat(OpcodeStr,
942 " \t{$src3, $src2, $dst {${mask}}|"
943 "$dst {${mask}}, $src2, $src3}"),
944 [(set RC:$dst,
945 (OpVT (vselect KRC:$mask,
946 (OpNode RC:$src1, RC:$src2,
947 (mem_frag addr:$src3)),
948 RC:$src1)))]>,
949 EVEX_4V, EVEX_K;
950
951 let AddedComplexity = 10 in // Prefer over the rrkz variant
952 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
953 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
954 !strconcat(OpcodeStr,
955 " \t{$src3, $src2, $dst {${mask}} {z}|"
956 "$dst {${mask}} {z}, $src2, $src3}"),
957 [(set RC:$dst,
958 (OpVT (vselect KRC:$mask,
959 (OpNode RC:$src1, RC:$src2,
960 (mem_frag addr:$src3)),
961 (OpVT (bitconvert
962 (v16i32 immAllZerosV))))))]>,
963 EVEX_4V, EVEX_KZ;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]964 }
965}
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]966defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
967 i512mem, X86VPermiv3, v16i32, VK16WM>,
968 EVEX_V512, EVEX_CD8<32, CD8VF>;
969defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
970 i512mem, X86VPermiv3, v8i64, VK8WM>,
971 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
972defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
973 i512mem, X86VPermiv3, v16f32, VK16WM>,
974 EVEX_V512, EVEX_CD8<32, CD8VF>;
975defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
976 i512mem, X86VPermiv3, v8f64, VK8WM>,
977 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]978
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]979multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
980 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]981 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
982 ValueType MaskVT, RegisterClass MRC> :
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]983 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
984 OpVT, KRC> {
985 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
986 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
987 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]988
989 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
990 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
991 (!cast<Instruction>(NAME#rrk) VR512:$src1,
992 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]993}
994
995defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]996 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
997 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]998defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]999 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1000 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]1001defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]1002 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1003 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]1004defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]1005 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1006 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky299cf5112014-04-29 09:09:15 +0000[diff] [blame]1007
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1008//===----------------------------------------------------------------------===//
1009// AVX-512 - BLEND using mask
1010//
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1011multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1012 RegisterClass KRC, RegisterClass RC,
1013 X86MemOperand x86memop, PatFrag mem_frag,
1014 SDNode OpNode, ValueType vt> {
1015 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1016 (ins KRC:$mask, RC:$src1, RC:$src2),
1017 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1018 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1019 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1020 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1021 let mayLoad = 1 in
1022 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1023 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1024 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1025 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1026 []>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1027}
1028
1029let ExeDomain = SSEPackedSingle in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1030defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1031 VK16WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1032 memopv16f32, vselect, v16f32>,
1033 EVEX_CD8<32, CD8VF>, EVEX_V512;
1034let ExeDomain = SSEPackedDouble in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1035defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1036 VK8WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1037 memopv8f64, vselect, v8f64>,
1038 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1039
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1040def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
1041 (v16f32 VR512:$src2), (i16 GR16:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1042 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1043 VR512:$src1, VR512:$src2)>;
1044
1045def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
1046 (v8f64 VR512:$src2), (i8 GR8:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1047 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1048 VR512:$src1, VR512:$src2)>;
1049
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1050defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1051 VK16WM, VR512, f512mem,
1052 memopv16i32, vselect, v16i32>,
1053 EVEX_CD8<32, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1054
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1055defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1056 VK8WM, VR512, f512mem,
1057 memopv8i64, vselect, v8i64>,
1058 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1059
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1060def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
1061 (v16i32 VR512:$src2), (i16 GR16:$mask))),
1062 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
1063 VR512:$src1, VR512:$src2)>;
1064
1065def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
1066 (v8i64 VR512:$src2), (i8 GR8:$mask))),
1067 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
1068 VR512:$src1, VR512:$src2)>;
1069
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1070let Predicates = [HasAVX512] in {
1071def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1072 (v8f32 VR256X:$src2))),
1073 (EXTRACT_SUBREG
1074 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1075 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1076 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1077
1078def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1079 (v8i32 VR256X:$src2))),
1080 (EXTRACT_SUBREG
1081 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1082 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1083 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1084}
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1085//===----------------------------------------------------------------------===//
1086// Compare Instructions
1087//===----------------------------------------------------------------------===//
1088
1089// avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1090multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1091 Operand CC, SDNode OpNode, ValueType VT,
1092 PatFrag ld_frag, string asm, string asm_alt> {
1093 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1094 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
1095 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1096 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1097 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1098 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
1099 [(set VK1:$dst, (OpNode (VT RC:$src1),
1100 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1101 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1102 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1103 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1104 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1105 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1106 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1107 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1108 }
1109}
1110
1111let Predicates = [HasAVX512] in {
1112defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1113 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1114 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1115 XS;
1116defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1117 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1118 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1119 XD, VEX_W;
1120}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1121
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1122multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1123 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1124 def rr : AVX512BI<opc, MRMSrcReg,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1125 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1126 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1127 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1128 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1129 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1130 def rm : AVX512BI<opc, MRMSrcMem,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1131 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1132 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1133 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1134 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1135 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1136 def rrk : AVX512BI<opc, MRMSrcReg,
1137 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1138 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1139 "$dst {${mask}}, $src1, $src2}"),
1140 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1141 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1142 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1143 let mayLoad = 1 in
1144 def rmk : AVX512BI<opc, MRMSrcMem,
1145 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1146 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1147 "$dst {${mask}}, $src1, $src2}"),
1148 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1149 (OpNode (_.VT _.RC:$src1),
1150 (_.VT (bitconvert
1151 (_.LdFrag addr:$src2))))))],
1152 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1153}
1154
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1155multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1156 X86VectorVTInfo _> :
1157 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1158 let mayLoad = 1 in {
1159 def rmb : AVX512BI<opc, MRMSrcMem,
1160 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1161 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1162 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1163 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1164 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1165 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1166 def rmbk : AVX512BI<opc, MRMSrcMem,
1167 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1168 _.ScalarMemOp:$src2),
1169 !strconcat(OpcodeStr,
1170 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1171 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1172 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1173 (OpNode (_.VT _.RC:$src1),
1174 (X86VBroadcast
1175 (_.ScalarLdFrag addr:$src2)))))],
1176 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1177 }
1178}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1179
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1180multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1181 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1182 let Predicates = [prd] in
1183 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1184 EVEX_V512;
1185
1186 let Predicates = [prd, HasVLX] in {
1187 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1188 EVEX_V256;
1189 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1190 EVEX_V128;
1191 }
1192}
1193
1194multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1195 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1196 Predicate prd> {
1197 let Predicates = [prd] in
1198 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1199 EVEX_V512;
1200
1201 let Predicates = [prd, HasVLX] in {
1202 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1203 EVEX_V256;
1204 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1205 EVEX_V128;
1206 }
1207}
1208
1209defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1210 avx512vl_i8_info, HasBWI>,
1211 EVEX_CD8<8, CD8VF>;
1212
1213defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1214 avx512vl_i16_info, HasBWI>,
1215 EVEX_CD8<16, CD8VF>;
1216
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1217defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1218 avx512vl_i32_info, HasAVX512>,
1219 EVEX_CD8<32, CD8VF>;
1220
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1221defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1222 avx512vl_i64_info, HasAVX512>,
1223 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1224
1225defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1226 avx512vl_i8_info, HasBWI>,
1227 EVEX_CD8<8, CD8VF>;
1228
1229defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1230 avx512vl_i16_info, HasBWI>,
1231 EVEX_CD8<16, CD8VF>;
1232
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1233defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1234 avx512vl_i32_info, HasAVX512>,
1235 EVEX_CD8<32, CD8VF>;
1236
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1237defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1238 avx512vl_i64_info, HasAVX512>,
1239 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1240
1241def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1242 (COPY_TO_REGCLASS (VPCMPGTDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1243 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1244 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1245
1246def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1247 (COPY_TO_REGCLASS (VPCMPEQDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1248 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1249 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1250
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1251multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1252 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1253 def rri : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1254 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1255 !strconcat("vpcmp${cc}", Suffix,
1256 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1257 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1258 imm:$cc))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1259 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1260 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1261 def rmi : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1262 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1263 !strconcat("vpcmp${cc}", Suffix,
1264 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1265 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1266 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1267 imm:$cc))],
1268 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1269 def rrik : AVX512AIi8<opc, MRMSrcReg,
1270 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1271 AVXCC:$cc),
1272 !strconcat("vpcmp${cc}", Suffix,
1273 "\t{$src2, $src1, $dst {${mask}}|",
1274 "$dst {${mask}}, $src1, $src2}"),
1275 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1276 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1277 imm:$cc)))],
1278 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1279 let mayLoad = 1 in
1280 def rmik : AVX512AIi8<opc, MRMSrcMem,
1281 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1282 AVXCC:$cc),
1283 !strconcat("vpcmp${cc}", Suffix,
1284 "\t{$src2, $src1, $dst {${mask}}|",
1285 "$dst {${mask}}, $src1, $src2}"),
1286 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1287 (OpNode (_.VT _.RC:$src1),
1288 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1289 imm:$cc)))],
1290 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1291
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1292 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1293 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1294 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1295 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1296 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1297 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1298 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1299 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1300 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1301 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1302 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1303 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1304 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1305 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1306 i8imm:$cc),
Adam Nemet16de2482014-07-01 18:03:45 +0000[diff] [blame]1307 !strconcat("vpcmp", Suffix,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1308 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1309 "$dst {${mask}}, $src1, $src2, $cc}"),
1310 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1311 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1312 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1313 i8imm:$cc),
1314 !strconcat("vpcmp", Suffix,
1315 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1316 "$dst {${mask}}, $src1, $src2, $cc}"),
Adam Nemet16de2482014-07-01 18:03:45 +0000[diff] [blame]1317 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1318 }
1319}
1320
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1321multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1322 X86VectorVTInfo _> :
1323 avx512_icmp_cc<opc, Suffix, OpNode, _> {
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1324 let mayLoad = 1 in {
1325 def rmib : AVX512AIi8<opc, MRMSrcMem,
1326 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1327 AVXCC:$cc),
1328 !strconcat("vpcmp${cc}", Suffix,
1329 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1330 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1331 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1332 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1333 imm:$cc))],
1334 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1335 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1336 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1337 _.ScalarMemOp:$src2, AVXCC:$cc),
1338 !strconcat("vpcmp${cc}", Suffix,
1339 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1340 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1341 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1342 (OpNode (_.VT _.RC:$src1),
1343 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1344 imm:$cc)))],
1345 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1346 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1347
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1348 // Accept explicit immediate argument form instead of comparison code.
1349 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1350 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1351 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1352 i8imm:$cc),
1353 !strconcat("vpcmp", Suffix,
1354 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1355 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1356 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1357 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1358 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1359 _.ScalarMemOp:$src2, i8imm:$cc),
1360 !strconcat("vpcmp", Suffix,
1361 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1362 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1363 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1364 }
1365}
1366
1367multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1368 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1369 let Predicates = [prd] in
1370 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1371
1372 let Predicates = [prd, HasVLX] in {
1373 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1374 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1375 }
1376}
1377
1378multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1379 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1380 let Predicates = [prd] in
1381 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1382 EVEX_V512;
1383
1384 let Predicates = [prd, HasVLX] in {
1385 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1386 EVEX_V256;
1387 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1388 EVEX_V128;
1389 }
1390}
1391
1392defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1393 HasBWI>, EVEX_CD8<8, CD8VF>;
1394defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1395 HasBWI>, EVEX_CD8<8, CD8VF>;
1396
1397defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1398 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1399defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1400 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1401
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1402defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1403 HasAVX512>, EVEX_CD8<32, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1404defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1405 HasAVX512>, EVEX_CD8<32, CD8VF>;
1406
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1407defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1408 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1409defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1410 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1411
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1412// avx512_cmp_packed - compare packed instructions
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1413multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1414 X86MemOperand x86memop, ValueType vt,
1415 string suffix, Domain d> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1416 def rri : AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1417 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1418 !strconcat("vcmp${cc}", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1419 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1420 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1421 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1422 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1423 !strconcat("vcmp${cc}", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1424 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1425 [], d>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1426 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1427 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1428 !strconcat("vcmp${cc}", suffix,
1429 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1430 [(set KRC:$dst,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1431 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1432
1433 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1434 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]1435 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1436 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1437 !strconcat("vcmp", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1438 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]1439 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1440 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1441 !strconcat("vcmp", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1442 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1443 }
1444}
1445
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1446defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1447 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]1448 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1449defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1450 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1451 EVEX_CD8<64, CD8VF>;
1452
1453def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1454 (COPY_TO_REGCLASS (VCMPPSZrri
1455 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1456 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1457 imm:$cc), VK8)>;
1458def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1459 (COPY_TO_REGCLASS (VPCMPDZrri
1460 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1461 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1462 imm:$cc), VK8)>;
1463def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1464 (COPY_TO_REGCLASS (VPCMPUDZrri
1465 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1466 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1467 imm:$cc), VK8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1468
1469def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1470 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1471 FROUND_NO_EXC)),
1472 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1473 (I8Imm imm:$cc)), GR16)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1474
1475def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1476 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1477 FROUND_NO_EXC)),
1478 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1479 (I8Imm imm:$cc)), GR8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1480
1481def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1482 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1483 FROUND_CURRENT)),
1484 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1485 (I8Imm imm:$cc)), GR16)>;
1486
1487def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1488 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1489 FROUND_CURRENT)),
1490 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1491 (I8Imm imm:$cc)), GR8)>;
1492
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1493// Mask register copy, including
1494// - copy between mask registers
1495// - load/store mask registers
1496// - copy from GPR to mask register and vice versa
1497//
1498multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1499 string OpcodeStr, RegisterClass KRC,
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1500 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]1501 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1502 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1503 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1504 let mayLoad = 1 in
1505 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1506 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1507 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1508 let mayStore = 1 in
1509 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1510 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1511 }
1512}
1513
1514multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1515 string OpcodeStr,
1516 RegisterClass KRC, RegisterClass GRC> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]1517 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1518 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1519 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1520 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1521 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1522 }
1523}
1524
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1525let Predicates = [HasDQI] in
1526 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1527 i8mem>,
1528 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1529 VEX, PD;
1530
1531let Predicates = [HasAVX512] in
1532 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1533 i16mem>,
1534 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1535 VEX, PS;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1536
1537let Predicates = [HasBWI] in {
1538 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1539 i32mem>, VEX, PD, VEX_W;
1540 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1541 VEX, XD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1542}
1543
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1544let Predicates = [HasBWI] in {
1545 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1546 i64mem>, VEX, PS, VEX_W;
1547 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1548 VEX, XD, VEX_W;
1549}
1550
1551// GR from/to mask register
1552let Predicates = [HasDQI] in {
1553 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1554 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1555 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1556 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1557}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1558let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1559 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1560 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1561 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1562 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1563}
1564let Predicates = [HasBWI] in {
1565 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1566 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1567}
1568let Predicates = [HasBWI] in {
1569 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1570 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1571}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1572
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1573// Load/store kreg
1574let Predicates = [HasDQI] in {
1575 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1576 (KMOVBmk addr:$dst, VK8:$src)>;
1577}
1578let Predicates = [HasAVX512] in {
1579 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1580 (KMOVWmk addr:$dst, VK16:$src)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1581 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1582 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1583 def : Pat<(i1 (load addr:$src)),
1584 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1585 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1586 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1587}
1588let Predicates = [HasBWI] in {
1589 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1590 (KMOVDmk addr:$dst, VK32:$src)>;
1591}
1592let Predicates = [HasBWI] in {
1593 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1594 (KMOVQmk addr:$dst, VK64:$src)>;
1595}
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]1596
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1597let Predicates = [HasAVX512] in {
Elena Demikhovsky34d2d762014-08-18 11:59:06 +0000[diff] [blame]1598 def : Pat<(i1 (trunc (i64 GR64:$src))),
1599 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1600 (i32 1))), VK1)>;
1601
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1602 def : Pat<(i1 (trunc (i32 GR32:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000[diff] [blame]1603 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1604
1605 def : Pat<(i1 (trunc (i8 GR8:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000[diff] [blame]1606 (COPY_TO_REGCLASS
1607 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1608 VK1)>;
1609 def : Pat<(i1 (trunc (i16 GR16:$src))),
1610 (COPY_TO_REGCLASS
1611 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1612 VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1613
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1614 def : Pat<(i32 (zext VK1:$src)),
1615 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1616 def : Pat<(i8 (zext VK1:$src)),
1617 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1618 (AND32ri (KMOVWrk
1619 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1620 def : Pat<(i64 (zext VK1:$src)),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1621 (AND64ri8 (SUBREG_TO_REG (i64 0),
1622 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
Elena Demikhovsky750498c2014-02-17 07:29:33 +0000[diff] [blame]1623 def : Pat<(i16 (zext VK1:$src)),
1624 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1625 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1626 sub_16bit)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]1627 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1628 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1629 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1630 (COPY_TO_REGCLASS VK1:$src, VK8)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1631}
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1632let Predicates = [HasBWI] in {
1633 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1634 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1635 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1636 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1637}
1638
1639
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1640// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1641let Predicates = [HasAVX512] in {
1642 // GR from/to 8-bit mask without native support
1643 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1644 (COPY_TO_REGCLASS
1645 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1646 VK8)>;
1647 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1648 (EXTRACT_SUBREG
1649 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1650 sub_8bit)>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1651
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]1652 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1653 (COPY_TO_REGCLASS VK16:$src, VK1)>;
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]1654 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1655 (COPY_TO_REGCLASS VK8:$src, VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1656}
1657let Predicates = [HasBWI] in {
1658 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1659 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1660 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1661 (COPY_TO_REGCLASS VK64:$src, VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1662}
1663
1664// Mask unary operation
1665// - KNOT
1666multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1667 RegisterClass KRC, SDPatternOperator OpNode,
1668 Predicate prd> {
1669 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1670 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1671 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1672 [(set KRC:$dst, (OpNode KRC:$src))]>;
1673}
1674
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1675multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1676 SDPatternOperator OpNode> {
1677 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1678 HasDQI>, VEX, PD;
1679 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1680 HasAVX512>, VEX, PS;
1681 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1682 HasBWI>, VEX, PD, VEX_W;
1683 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1684 HasBWI>, VEX, PS, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1685}
1686
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1687defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1688
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1689multiclass avx512_mask_unop_int<string IntName, string InstName> {
1690 let Predicates = [HasAVX512] in
1691 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1692 (i16 GR16:$src)),
1693 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1694 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1695}
1696defm : avx512_mask_unop_int<"knot", "KNOT">;
1697
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1698let Predicates = [HasDQI] in
1699def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1700let Predicates = [HasAVX512] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1701def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1702let Predicates = [HasBWI] in
1703def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1704let Predicates = [HasBWI] in
1705def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1706
1707// KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1708let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1709def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1710 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1711
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1712def : Pat<(not VK8:$src),
1713 (COPY_TO_REGCLASS
1714 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1715}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1716
1717// Mask binary operation
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1718// - KAND, KANDN, KOR, KXNOR, KXOR
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1719multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1720 RegisterClass KRC, SDPatternOperator OpNode,
1721 Predicate prd> {
1722 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1723 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1724 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1725 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1726 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1727}
1728
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1729multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1730 SDPatternOperator OpNode> {
1731 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1732 HasDQI>, VEX_4V, VEX_L, PD;
1733 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1734 HasAVX512>, VEX_4V, VEX_L, PS;
1735 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1736 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1737 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1738 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1739}
1740
1741def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1742def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1743
1744let isCommutable = 1 in {
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1745 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1746 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1747 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1748 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1749}
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1750let isCommutable = 0 in
1751 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1752
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1753def : Pat<(xor VK1:$src1, VK1:$src2),
1754 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1755 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1756
1757def : Pat<(or VK1:$src1, VK1:$src2),
1758 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1759 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1760
Elena Demikhovskyb64d7e82013-12-25 10:06:40 +0000[diff] [blame]1761def : Pat<(and VK1:$src1, VK1:$src2),
1762 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1763 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1764
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1765multiclass avx512_mask_binop_int<string IntName, string InstName> {
1766 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1767 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1768 (i16 GR16:$src1), (i16 GR16:$src2)),
1769 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1770 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1771 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1772}
1773
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1774defm : avx512_mask_binop_int<"kand", "KAND">;
1775defm : avx512_mask_binop_int<"kandn", "KANDN">;
1776defm : avx512_mask_binop_int<"kor", "KOR">;
1777defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1778defm : avx512_mask_binop_int<"kxor", "KXOR">;
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1779
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1780// With AVX-512, 8-bit mask is promoted to 16-bit mask.
1781multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1782 let Predicates = [HasAVX512] in
1783 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1784 (COPY_TO_REGCLASS
1785 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1786 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1787}
1788
1789defm : avx512_binop_pat<and, KANDWrr>;
1790defm : avx512_binop_pat<andn, KANDNWrr>;
1791defm : avx512_binop_pat<or, KORWrr>;
1792defm : avx512_binop_pat<xnor, KXNORWrr>;
1793defm : avx512_binop_pat<xor, KXORWrr>;
1794
1795// Mask unpacking
1796multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1797 RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1798 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1799 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1800 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1801 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1802}
1803
1804multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1805 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1806 VEX_4V, VEX_L, PD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1807}
1808
1809defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]1810def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1811 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1812 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1813
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1814
1815multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1816 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1817 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1818 (i16 GR16:$src1), (i16 GR16:$src2)),
1819 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1820 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1821 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1822}
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1823defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1824
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1825// Mask bit testing
1826multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1827 SDNode OpNode> {
1828 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1829 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1830 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1831 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1832}
1833
1834multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1835 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1836 VEX, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1837}
1838
1839defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1840
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1841def : Pat<(X86cmp VK1:$src1, (i1 0)),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1842 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1843 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1844
1845// Mask shift
1846multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1847 SDNode OpNode> {
1848 let Predicates = [HasAVX512] in
1849 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1850 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1851 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1852 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1853}
1854
1855multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1856 SDNode OpNode> {
1857 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1858 VEX, TAPD, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1859}
1860
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1861defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1862defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1863
1864// Mask setting all 0s or 1s
1865multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1866 let Predicates = [HasAVX512] in
1867 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1868 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1869 [(set KRC:$dst, (VT Val))]>;
1870}
1871
1872multiclass avx512_mask_setop_w<PatFrag Val> {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1873 defm B : avx512_mask_setop<VK8, v8i1, Val>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1874 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1875}
1876
1877defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1878defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1879
1880// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1881let Predicates = [HasAVX512] in {
1882 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1883 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1884 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1885 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1886 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1887}
1888def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1889 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1890
1891def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1892 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1893
1894def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1895 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1896
Robert Khasanov5aa44452014-09-30 11:41:54 +0000[diff] [blame]1897let Predicates = [HasVLX] in {
1898 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1899 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1900 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1901 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1902 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1903 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1904 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1905 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1906}
1907
Elena Demikhovsky9737e382014-03-02 09:19:44 +0000[diff] [blame]1908def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1909 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1910
1911def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1912 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1913//===----------------------------------------------------------------------===//
1914// AVX-512 - Aligned and unaligned load and store
1915//
1916
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1917multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1918 RegisterClass KRC, RegisterClass RC,
1919 ValueType vt, ValueType zvt, X86MemOperand memop,
1920 Domain d, bit IsReMaterializable = 1> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1921let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1922 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1923 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1924 d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1925 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1926 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1927 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1928 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1929 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1930 SchedRW = [WriteLoad] in
1931 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1932 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1933 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1934 d>, EVEX;
1935
1936 let AddedComplexity = 20 in {
1937 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1938 let hasSideEffects = 0 in
1939 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1940 (ins RC:$src0, KRC:$mask, RC:$src1),
1941 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1942 "${dst} {${mask}}, $src1}"),
1943 [(set RC:$dst, (vt (vselect KRC:$mask,
1944 (vt RC:$src1),
1945 (vt RC:$src0))))],
1946 d>, EVEX, EVEX_K;
1947 let mayLoad = 1, SchedRW = [WriteLoad] in
1948 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1949 (ins RC:$src0, KRC:$mask, memop:$src1),
1950 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1951 "${dst} {${mask}}, $src1}"),
1952 [(set RC:$dst, (vt
1953 (vselect KRC:$mask,
1954 (vt (bitconvert (ld_frag addr:$src1))),
1955 (vt RC:$src0))))],
1956 d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1957 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1958 let mayLoad = 1, SchedRW = [WriteLoad] in
1959 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1960 (ins KRC:$mask, memop:$src),
1961 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1962 "${dst} {${mask}} {z}, $src}"),
1963 [(set RC:$dst, (vt
1964 (vselect KRC:$mask,
1965 (vt (bitconvert (ld_frag addr:$src))),
1966 (vt (bitconvert (zvt immAllZerosV))))))],
1967 d>, EVEX, EVEX_KZ;
1968 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1969}
1970
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1971multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1972 string elty, string elsz, string vsz512,
1973 string vsz256, string vsz128, Domain d,
1974 Predicate prd, bit IsReMaterializable = 1> {
1975 let Predicates = [prd] in
1976 defm Z : avx512_load<opc, OpcodeStr,
1977 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1978 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1979 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1980 !cast<X86MemOperand>(elty##"512mem"), d,
1981 IsReMaterializable>, EVEX_V512;
1982
1983 let Predicates = [prd, HasVLX] in {
1984 defm Z256 : avx512_load<opc, OpcodeStr,
1985 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1986 "v"##vsz256##elty##elsz, "v4i64")),
1987 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1988 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1989 !cast<X86MemOperand>(elty##"256mem"), d,
1990 IsReMaterializable>, EVEX_V256;
1991
1992 defm Z128 : avx512_load<opc, OpcodeStr,
1993 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1994 "v"##vsz128##elty##elsz, "v2i64")),
1995 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1996 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1997 !cast<X86MemOperand>(elty##"128mem"), d,
1998 IsReMaterializable>, EVEX_V128;
1999 }
2000}
2001
2002
2003multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2004 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2005 X86MemOperand memop, Domain d> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2006 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2007 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2008 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2009 EVEX;
2010 let Constraints = "$src1 = $dst" in
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2011 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2012 (ins RC:$src1, KRC:$mask, RC:$src2),
2013 !strconcat(OpcodeStr,
2014 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2015 EVEX, EVEX_K;
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2016 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2017 (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2018 !strconcat(OpcodeStr,
2019 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2020 [], d>, EVEX, EVEX_KZ;
2021 }
2022 let mayStore = 1 in {
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2023 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2024 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2025 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2026 def mrk : AVX512PI<opc, MRMDestMem, (outs),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2027 (ins memop:$dst, KRC:$mask, RC:$src),
2028 !strconcat(OpcodeStr,
2029 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2030 [], d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2031 }
2032}
2033
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2034
2035multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2036 string st_suff_512, string st_suff_256,
2037 string st_suff_128, string elty, string elsz,
2038 string vsz512, string vsz256, string vsz128,
2039 Domain d, Predicate prd> {
2040 let Predicates = [prd] in
2041 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2042 !cast<ValueType>("v"##vsz512##elty##elsz),
2043 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2044 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2045
2046 let Predicates = [prd, HasVLX] in {
2047 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2048 !cast<ValueType>("v"##vsz256##elty##elsz),
2049 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2050 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2051
2052 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2053 !cast<ValueType>("v"##vsz128##elty##elsz),
2054 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2055 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2056 }
2057}
2058
2059defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2060 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2061 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2062 "512", "256", "", "f", "32", "16", "8", "4",
2063 SSEPackedSingle, HasAVX512>,
2064 PS, EVEX_CD8<32, CD8VF>;
2065
2066defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2067 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2068 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2069 "512", "256", "", "f", "64", "8", "4", "2",
2070 SSEPackedDouble, HasAVX512>,
2071 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2072
2073defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2074 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2075 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2076 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2077 PS, EVEX_CD8<32, CD8VF>;
2078
2079defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2080 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2081 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2082 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2083 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2084
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2085def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2086 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2087 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2088
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2089def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2090 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2091 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2092
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2093def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2094 GR16:$mask),
2095 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2096 VR512:$src)>;
2097def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2098 GR8:$mask),
2099 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2100 VR512:$src)>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]2101
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2102defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2103 "16", "8", "4", SSEPackedInt, HasAVX512>,
2104 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2105 "512", "256", "", "i", "32", "16", "8", "4",
2106 SSEPackedInt, HasAVX512>,
2107 PD, EVEX_CD8<32, CD8VF>;
2108
2109defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2110 "8", "4", "2", SSEPackedInt, HasAVX512>,
2111 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2112 "512", "256", "", "i", "64", "8", "4", "2",
2113 SSEPackedInt, HasAVX512>,
2114 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2115
2116defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2117 "64", "32", "16", SSEPackedInt, HasBWI>,
2118 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2119 "i", "8", "64", "32", "16", SSEPackedInt,
2120 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2121
2122defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2123 "32", "16", "8", SSEPackedInt, HasBWI>,
2124 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2125 "i", "16", "32", "16", "8", SSEPackedInt,
2126 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2127
2128defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2129 "16", "8", "4", SSEPackedInt, HasAVX512>,
2130 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2131 "i", "32", "16", "8", "4", SSEPackedInt,
2132 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2133
2134defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2135 "8", "4", "2", SSEPackedInt, HasAVX512>,
2136 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2137 "i", "64", "8", "4", "2", SSEPackedInt,
2138 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]2139
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]2140def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2141 (v16i32 immAllZerosV), GR16:$mask)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2142 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]2143
2144def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2145 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2146 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]2147
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2148def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2149 GR16:$mask),
2150 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2151 VR512:$src)>;
2152def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2153 GR8:$mask),
2154 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2155 VR512:$src)>;
2156
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2157let AddedComplexity = 20 in {
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2158def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2159 (bc_v8i64 (v16i32 immAllZerosV)))),
2160 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2161
2162def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2163 (v8i64 VR512:$src))),
2164 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2165 VK8), VR512:$src)>;
2166
2167def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2168 (v16i32 immAllZerosV))),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2169 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2170
2171def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2172 (v16i32 VR512:$src))),
2173 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2174}
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2175
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2176// Move Int Doubleword to Packed Double Int
2177//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2178def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2179 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2180 [(set VR128X:$dst,
2181 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2182 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2183def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2184 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2185 [(set VR128X:$dst,
2186 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2187 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2188def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2189 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2190 [(set VR128X:$dst,
2191 (v2i64 (scalar_to_vector GR64:$src)))],
2192 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2193let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2194def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2195 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2196 [(set FR64:$dst, (bitconvert GR64:$src))],
2197 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2198def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2199 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2200 [(set GR64:$dst, (bitconvert FR64:$src))],
2201 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2202}
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2203def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2204 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2205 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2206 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2207 EVEX_CD8<64, CD8VT1>;
2208
2209// Move Int Doubleword to Single Scalar
2210//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2211let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2212def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2213 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2214 [(set FR32X:$dst, (bitconvert GR32:$src))],
2215 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2216
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2217def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2218 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2219 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2220 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2221}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2222
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2223// Move doubleword from xmm register to r/m32
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2224//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2225def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2226 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2227 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2228 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2229 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2230def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2231 (ins i32mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2232 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2233 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2234 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2235 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2236
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2237// Move quadword from xmm1 register to r/m64
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2238//
2239def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2240 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2241 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2242 (iPTR 0)))],
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2243 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2244 Requires<[HasAVX512, In64BitMode]>;
2245
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]2246def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2247 (ins i64mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2248 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2249 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2250 addr:$dst)], IIC_SSE_MOVDQ>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2251 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2252 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2253
2254// Move Scalar Single to Double Int
2255//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2256let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2257def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2258 (ins FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2259 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2260 [(set GR32:$dst, (bitconvert FR32X:$src))],
2261 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2262def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2263 (ins i32mem:$dst, FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2264 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2265 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2266 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2267}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2268
2269// Move Quadword Int to Packed Quadword Int
2270//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2271def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2272 (ins i64mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2273 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2274 [(set VR128X:$dst,
2275 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2276 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2277
2278//===----------------------------------------------------------------------===//
2279// AVX-512 MOVSS, MOVSD
2280//===----------------------------------------------------------------------===//
2281
2282multiclass avx512_move_scalar <string asm, RegisterClass RC,
2283 SDNode OpNode, ValueType vt,
2284 X86MemOperand x86memop, PatFrag mem_pat> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]2285 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2286 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2287 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2288 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2289 (scalar_to_vector RC:$src2))))],
2290 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2291 let Constraints = "$src1 = $dst" in
2292 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2293 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2294 !strconcat(asm,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2295 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2296 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2297 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2298 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2299 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2300 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2301 let mayStore = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2302 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2303 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2304 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2305 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2306 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2307 !strconcat(asm, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2308 [], IIC_SSE_MOV_S_MR>,
2309 EVEX, VEX_LIG, EVEX_K;
2310 } // mayStore
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]2311 } //hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2312}
2313
2314let ExeDomain = SSEPackedSingle in
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2315defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2316 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2317
2318let ExeDomain = SSEPackedDouble in
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2319defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2320 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2321
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2322def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2323 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2324 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2325
2326def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2327 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2328 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2329
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2330def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2331 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2332 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2333
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2334// For the disassembler
Craig Topper3484fc22014-01-05 04:17:28 +0000[diff] [blame]2335let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2336 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2337 (ins VR128X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2338 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2339 IIC_SSE_MOV_S_RR>,
2340 XS, EVEX_4V, VEX_LIG;
2341 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2342 (ins VR128X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2343 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2344 IIC_SSE_MOV_S_RR>,
2345 XD, EVEX_4V, VEX_LIG, VEX_W;
2346}
2347
2348let Predicates = [HasAVX512] in {
2349 let AddedComplexity = 15 in {
2350 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2351 // MOVS{S,D} to the lower bits.
2352 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2353 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2354 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2355 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2356 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2357 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2358 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2359 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2360
2361 // Move low f32 and clear high bits.
2362 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2363 (SUBREG_TO_REG (i32 0),
2364 (VMOVSSZrr (v4f32 (V_SET0)),
2365 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2366 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2367 (SUBREG_TO_REG (i32 0),
2368 (VMOVSSZrr (v4i32 (V_SET0)),
2369 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2370 }
2371
2372 let AddedComplexity = 20 in {
2373 // MOVSSrm zeros the high parts of the register; represent this
2374 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2375 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2376 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2377 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2378 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2379 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2380 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2381
2382 // MOVSDrm zeros the high parts of the register; represent this
2383 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2384 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2385 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2386 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2387 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2388 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2389 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2390 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2391 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2392 def : Pat<(v2f64 (X86vzload addr:$src)),
2393 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2394
2395 // Represent the same patterns above but in the form they appear for
2396 // 256-bit types
2397 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2398 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]2399 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2400 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2401 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2402 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2403 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2404 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2405 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2406 }
2407 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2408 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2409 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2410 FR32X:$src)), sub_xmm)>;
2411 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2412 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2413 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2414 FR64X:$src)), sub_xmm)>;
2415 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2416 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]2417 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2418
2419 // Move low f64 and clear high bits.
2420 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2421 (SUBREG_TO_REG (i32 0),
2422 (VMOVSDZrr (v2f64 (V_SET0)),
2423 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2424
2425 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2426 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2427 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2428
2429 // Extract and store.
2430 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2431 addr:$dst),
2432 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2433 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2434 addr:$dst),
2435 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2436
2437 // Shuffle with VMOVSS
2438 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2439 (VMOVSSZrr (v4i32 VR128X:$src1),
2440 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2441 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2442 (VMOVSSZrr (v4f32 VR128X:$src1),
2443 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2444
2445 // 256-bit variants
2446 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2447 (SUBREG_TO_REG (i32 0),
2448 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2449 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2450 sub_xmm)>;
2451 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2452 (SUBREG_TO_REG (i32 0),
2453 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2454 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2455 sub_xmm)>;
2456
2457 // Shuffle with VMOVSD
2458 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2459 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2460 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2461 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2462 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2463 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2464 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2465 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2466
2467 // 256-bit variants
2468 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2469 (SUBREG_TO_REG (i32 0),
2470 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2471 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2472 sub_xmm)>;
2473 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2474 (SUBREG_TO_REG (i32 0),
2475 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2476 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2477 sub_xmm)>;
2478
2479 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2480 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2481 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2482 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2483 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2484 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2485 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2486 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2487}
2488
2489let AddedComplexity = 15 in
2490def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2491 (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2492 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2493 [(set VR128X:$dst, (v2i64 (X86vzmovl
2494 (v2i64 VR128X:$src))))],
2495 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2496
2497let AddedComplexity = 20 in
2498def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2499 (ins i128mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2500 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2501 [(set VR128X:$dst, (v2i64 (X86vzmovl
2502 (loadv2i64 addr:$src))))],
2503 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2504 EVEX_CD8<8, CD8VT8>;
2505
2506let Predicates = [HasAVX512] in {
2507 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2508 let AddedComplexity = 20 in {
2509 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2510 (VMOVDI2PDIZrm addr:$src)>;
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]2511 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2512 (VMOV64toPQIZrr GR64:$src)>;
2513 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2514 (VMOVDI2PDIZrr GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2515
2516 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2517 (VMOVDI2PDIZrm addr:$src)>;
2518 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2519 (VMOVDI2PDIZrm addr:$src)>;
2520 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2521 (VMOVZPQILo2PQIZrm addr:$src)>;
2522 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2523 (VMOVZPQILo2PQIZrr VR128X:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +0000[diff] [blame]2524 def : Pat<(v2i64 (X86vzload addr:$src)),
2525 (VMOVZPQILo2PQIZrm addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2526 }
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]2527
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2528 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2529 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2530 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2531 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2532 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2533 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2534 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2535}
2536
2537def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2538 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2539
2540def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2541 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2542
2543def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2544 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2545
2546def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2547 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2548
2549//===----------------------------------------------------------------------===//
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2550// AVX-512 - Non-temporals
2551//===----------------------------------------------------------------------===//
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2552let SchedRW = [WriteLoad] in {
2553 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2554 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2555 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2556 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2557 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2558
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2559 let Predicates = [HasAVX512, HasVLX] in {
2560 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2561 (ins i256mem:$src),
2562 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2563 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2564 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2565
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2566 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2567 (ins i128mem:$src),
2568 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2569 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2570 EVEX_CD8<64, CD8VF>;
2571 }
Adam Nemetefd07852014-06-18 16:51:10 +0000[diff] [blame]2572}
2573
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2574multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2575 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2576 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2577 let SchedRW = [WriteStore], mayStore = 1,
2578 AddedComplexity = 400 in
2579 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2580 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2581 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2582}
2583
2584multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2585 string elty, string elsz, string vsz512,
2586 string vsz256, string vsz128, Domain d,
2587 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2588 let Predicates = [prd] in
2589 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2590 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2591 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2592 EVEX_V512;
2593
2594 let Predicates = [prd, HasVLX] in {
2595 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2596 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2597 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2598 EVEX_V256;
2599
2600 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2601 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2602 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2603 EVEX_V128;
2604 }
2605}
2606
2607defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2608 "i", "64", "8", "4", "2", SSEPackedInt,
2609 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2610
2611defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2612 "f", "64", "8", "4", "2", SSEPackedDouble,
2613 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2614
2615defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2616 "f", "32", "16", "8", "4", SSEPackedSingle,
2617 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2618
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2619//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2620// AVX-512 - Integer arithmetic
2621//
2622multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2623 X86VectorVTInfo _, OpndItins itins,
2624 bit IsCommutable = 0> {
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]2625 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2626 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2627 "$src2, $src1", "$src1, $src2",
2628 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2629 itins.rr, IsCommutable>,
2630 AVX512BIBase, EVEX_4V;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2631
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2632 let mayLoad = 1 in
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]2633 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2634 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2635 "$src2, $src1", "$src1, $src2",
2636 (_.VT (OpNode _.RC:$src1,
2637 (bitconvert (_.LdFrag addr:$src2)))),
2638 itins.rm>,
2639 AVX512BIBase, EVEX_4V;
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2640}
2641
2642multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2643 X86VectorVTInfo _, OpndItins itins,
2644 bit IsCommutable = 0> :
2645 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2646 let mayLoad = 1 in
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]2647 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2648 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2649 "${src2}"##_.BroadcastStr##", $src1",
2650 "$src1, ${src2}"##_.BroadcastStr,
2651 (_.VT (OpNode _.RC:$src1,
2652 (X86VBroadcast
2653 (_.ScalarLdFrag addr:$src2)))),
2654 itins.rm>,
2655 AVX512BIBase, EVEX_4V, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2656}
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2657
Robert Khasanovd5b14f72014-10-09 08:38:48 +0000[diff] [blame]2658multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2659 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2660 Predicate prd, bit IsCommutable = 0> {
2661 let Predicates = [prd] in
2662 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2663 IsCommutable>, EVEX_V512;
2664
2665 let Predicates = [prd, HasVLX] in {
2666 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2667 IsCommutable>, EVEX_V256;
2668 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2669 IsCommutable>, EVEX_V128;
2670 }
2671}
2672
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2673multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2674 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2675 Predicate prd, bit IsCommutable = 0> {
2676 let Predicates = [prd] in
2677 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2678 IsCommutable>, EVEX_V512;
2679
2680 let Predicates = [prd, HasVLX] in {
2681 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2682 IsCommutable>, EVEX_V256;
2683 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2684 IsCommutable>, EVEX_V128;
2685 }
2686}
2687
2688multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2689 OpndItins itins, Predicate prd,
2690 bit IsCommutable = 0> {
2691 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2692 itins, prd, IsCommutable>,
2693 VEX_W, EVEX_CD8<64, CD8VF>;
2694}
2695
2696multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2697 OpndItins itins, Predicate prd,
2698 bit IsCommutable = 0> {
2699 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2700 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2701}
2702
2703multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2704 OpndItins itins, Predicate prd,
2705 bit IsCommutable = 0> {
2706 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2707 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2708}
2709
2710multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2711 OpndItins itins, Predicate prd,
2712 bit IsCommutable = 0> {
2713 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2714 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2715}
2716
2717multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2718 SDNode OpNode, OpndItins itins, Predicate prd,
2719 bit IsCommutable = 0> {
2720 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2721 IsCommutable>;
2722
2723 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2724 IsCommutable>;
2725}
2726
2727multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2728 SDNode OpNode, OpndItins itins, Predicate prd,
2729 bit IsCommutable = 0> {
2730 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2731 IsCommutable>;
2732
2733 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2734 IsCommutable>;
2735}
2736
2737multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2738 bits<8> opc_d, bits<8> opc_q,
2739 string OpcodeStr, SDNode OpNode,
2740 OpndItins itins, bit IsCommutable = 0> {
2741 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2742 itins, HasAVX512, IsCommutable>,
2743 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2744 itins, HasBWI, IsCommutable>;
2745}
2746
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2747multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2748 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2749 PatFrag memop_frag, X86MemOperand x86memop,
2750 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2751 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2752 let isCommutable = IsCommutable in
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2753 {
2754 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2755 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2756 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2757 []>, EVEX_4V;
2758 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2759 (ins KRC:$mask, RC:$src1, RC:$src2),
2760 !strconcat(OpcodeStr,
2761 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2762 [], itins.rr>, EVEX_4V, EVEX_K;
2763 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2764 (ins KRC:$mask, RC:$src1, RC:$src2),
2765 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2766 "|$dst {${mask}} {z}, $src1, $src2}"),
2767 [], itins.rr>, EVEX_4V, EVEX_KZ;
2768 }
2769 let mayLoad = 1 in {
2770 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2771 (ins RC:$src1, x86memop:$src2),
2772 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2773 []>, EVEX_4V;
2774 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2775 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2776 !strconcat(OpcodeStr,
2777 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2778 [], itins.rm>, EVEX_4V, EVEX_K;
2779 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2780 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2781 !strconcat(OpcodeStr,
2782 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2783 [], itins.rm>, EVEX_4V, EVEX_KZ;
2784 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2785 (ins RC:$src1, x86scalar_mop:$src2),
2786 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2787 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2788 [], itins.rm>, EVEX_4V, EVEX_B;
2789 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2790 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2791 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2792 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2793 BrdcstStr, "}"),
2794 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2795 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2796 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2797 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2798 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2799 BrdcstStr, "}"),
2800 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2801 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2802}
2803
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2804defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
2805 SSE_INTALU_ITINS_P, 1>;
2806defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
2807 SSE_INTALU_ITINS_P, 0>;
2808defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
2809 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2810defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
2811 SSE_INTALU_ITINS_P, HasBWI, 1>;
Robert Khasanov1a77f662014-10-14 15:13:56 +0000[diff] [blame]2812defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
2813 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2814
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2815defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2816 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2817 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2818 EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2819
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2820defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2821 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2822 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2823
2824def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2825 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2826
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2827def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2828 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2829 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2830def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2831 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2832 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2833
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2834defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
2835 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2836defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
2837 SSE_INTALU_ITINS_P, HasBWI, 1>;
2838defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
2839 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2840
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2841defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
2842 SSE_INTALU_ITINS_P, HasBWI, 1>;
2843defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
2844 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2845defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
2846 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2847
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2848defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
2849 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2850defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
2851 SSE_INTALU_ITINS_P, HasBWI, 1>;
2852defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
2853 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2854
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2855defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
2856 SSE_INTALU_ITINS_P, HasBWI, 1>;
2857defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
2858 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2859defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
2860 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2861
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2862def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2863 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2864 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2865def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2866 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2867 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2868def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2869 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2870 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2871def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2872 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2873 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2874def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2875 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2876 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2877def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2878 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2879 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2880def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2881 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2882 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2883def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2884 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2885 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2886//===----------------------------------------------------------------------===//
2887// AVX-512 - Unpack Instructions
2888//===----------------------------------------------------------------------===//
2889
2890multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2891 PatFrag mem_frag, RegisterClass RC,
2892 X86MemOperand x86memop, string asm,
2893 Domain d> {
2894 def rr : AVX512PI<opc, MRMSrcReg,
2895 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2896 asm, [(set RC:$dst,
2897 (vt (OpNode RC:$src1, RC:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]2898 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2899 def rm : AVX512PI<opc, MRMSrcMem,
2900 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2901 asm, [(set RC:$dst,
2902 (vt (OpNode RC:$src1,
2903 (bitconvert (mem_frag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]2904 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2905}
2906
2907defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2908 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2909 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2910defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2911 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2912 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2913defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2914 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2915 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2916defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2917 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2918 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2919
2920multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2921 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2922 X86MemOperand x86memop> {
2923 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2924 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2925 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2926 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2927 IIC_SSE_UNPCK>, EVEX_4V;
2928 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2929 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2930 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2931 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2932 (bitconvert (memop_frag addr:$src2)))))],
2933 IIC_SSE_UNPCK>, EVEX_4V;
2934}
2935defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2936 VR512, memopv16i32, i512mem>, EVEX_V512,
2937 EVEX_CD8<32, CD8VF>;
2938defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2939 VR512, memopv8i64, i512mem>, EVEX_V512,
2940 VEX_W, EVEX_CD8<64, CD8VF>;
2941defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2942 VR512, memopv16i32, i512mem>, EVEX_V512,
2943 EVEX_CD8<32, CD8VF>;
2944defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2945 VR512, memopv8i64, i512mem>, EVEX_V512,
2946 VEX_W, EVEX_CD8<64, CD8VF>;
2947//===----------------------------------------------------------------------===//
2948// AVX-512 - PSHUFD
2949//
2950
2951multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2952 SDNode OpNode, PatFrag mem_frag,
2953 X86MemOperand x86memop, ValueType OpVT> {
2954 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2955 (ins RC:$src1, i8imm:$src2),
2956 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2957 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2958 [(set RC:$dst,
2959 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2960 EVEX;
2961 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2962 (ins x86memop:$src1, i8imm:$src2),
2963 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2964 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2965 [(set RC:$dst,
2966 (OpVT (OpNode (mem_frag addr:$src1),
2967 (i8 imm:$src2))))]>, EVEX;
2968}
2969
2970defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2971 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2972
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2973//===----------------------------------------------------------------------===//
2974// AVX-512 Logical Instructions
2975//===----------------------------------------------------------------------===//
2976
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2977defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
2978 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2979defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
2980 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2981defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
2982 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2983defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
2984 SSE_INTALU_ITINS_P, HasAVX512, 1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2985
2986//===----------------------------------------------------------------------===//
2987// AVX-512 FP arithmetic
2988//===----------------------------------------------------------------------===//
2989
2990multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2991 SizeItins itins> {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2992 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2993 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2994 EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2995 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2996 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2997 EVEX_CD8<64, CD8VT1>;
2998}
2999
3000let isCommutable = 1 in {
3001defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3002defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3003defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3004defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3005}
3006let isCommutable = 0 in {
3007defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3008defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3009}
3010
3011multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanov595e5982014-10-29 15:43:02 +0000[diff] [blame]3012 X86VectorVTInfo _, bit IsCommutable> {
3013 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3014 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3015 "$src2, $src1", "$src1, $src2",
3016 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3017 let mayLoad = 1 in {
Robert Khasanov595e5982014-10-29 15:43:02 +0000[diff] [blame]3018 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3019 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3020 "$src2, $src1", "$src1, $src2",
3021 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3022 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3023 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3024 "${src2}"##_.BroadcastStr##", $src1",
3025 "$src1, ${src2}"##_.BroadcastStr,
3026 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3027 (_.ScalarLdFrag addr:$src2))))>,
3028 EVEX_4V, EVEX_B;
3029 }//let mayLoad = 1
3030}
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3031
Robert Khasanov595e5982014-10-29 15:43:02 +0000[diff] [blame]3032multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3033 bit IsCommutable = 0> {
3034 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3035 IsCommutable>, EVEX_V512, PS,
3036 EVEX_CD8<32, CD8VF>;
3037 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3038 IsCommutable>, EVEX_V512, PD, VEX_W,
3039 EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3040
Robert Khasanov595e5982014-10-29 15:43:02 +0000[diff] [blame]3041 // Define only if AVX512VL feature is present.
3042 let Predicates = [HasVLX] in {
3043 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3044 IsCommutable>, EVEX_V128, PS,
3045 EVEX_CD8<32, CD8VF>;
3046 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3047 IsCommutable>, EVEX_V256, PS,
3048 EVEX_CD8<32, CD8VF>;
3049 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3050 IsCommutable>, EVEX_V128, PD, VEX_W,
3051 EVEX_CD8<64, CD8VF>;
3052 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3053 IsCommutable>, EVEX_V256, PD, VEX_W,
3054 EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3055 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3056}
3057
Robert Khasanov595e5982014-10-29 15:43:02 +0000[diff] [blame]3058defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>;
3059defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>;
3060defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3061defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3062defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>;
3063defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3064
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3065def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3066 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3067 (i16 -1), FROUND_CURRENT)),
3068 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3069
3070def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3071 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3072 (i8 -1), FROUND_CURRENT)),
3073 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3074
3075def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3076 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3077 (i16 -1), FROUND_CURRENT)),
3078 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3079
3080def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3081 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3082 (i8 -1), FROUND_CURRENT)),
3083 (VMINPDZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3084//===----------------------------------------------------------------------===//
3085// AVX-512 VPTESTM instructions
3086//===----------------------------------------------------------------------===//
3087
3088multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3089 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3090 SDNode OpNode, ValueType vt> {
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3091 def rr : AVX512PI<opc, MRMSrcReg,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3092 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3093 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3094 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3095 SSEPackedInt>, EVEX_4V;
3096 def rm : AVX512PI<opc, MRMSrcMem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3097 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3098 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3099 [(set KRC:$dst, (OpNode (vt RC:$src1),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3100 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3101}
3102
3103defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3104 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3105 EVEX_CD8<32, CD8VF>;
3106defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]3107 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3108 EVEX_CD8<64, CD8VF>;
3109
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3110let Predicates = [HasCDI] in {
3111defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3112 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3113 EVEX_CD8<32, CD8VF>;
3114defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]3115 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3116 EVEX_CD8<64, CD8VF>;
3117}
3118
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3119def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3120 (v16i32 VR512:$src2), (i16 -1))),
3121 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3122
3123def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3124 (v8i64 VR512:$src2), (i8 -1))),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]3125 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3126//===----------------------------------------------------------------------===//
3127// AVX-512 Shift instructions
3128//===----------------------------------------------------------------------===//
3129multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3130 string OpcodeStr, SDNode OpNode, RegisterClass RC,
3131 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
3132 RegisterClass KRC> {
3133 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3134 (ins RC:$src1, i8imm:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3135 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3136 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3137 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3138 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3139 (ins KRC:$mask, RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3140 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3141 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3142 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3143 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3144 (ins x86memop:$src1, i8imm:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3145 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3146 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3147 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3148 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3149 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3150 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3151 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3152 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3153}
3154
3155multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3156 RegisterClass RC, ValueType vt, ValueType SrcVT,
3157 PatFrag bc_frag, RegisterClass KRC> {
3158 // src2 is always 128-bit
3159 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3160 (ins RC:$src1, VR128X:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3161 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3162 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
3163 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3164 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3165 (ins KRC:$mask, RC:$src1, VR128X:$src2),
3166 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3167 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3168 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3169 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3170 (ins RC:$src1, i128mem:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3171 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3172 [(set RC:$dst, (vt (OpNode RC:$src1,
3173 (bc_frag (memopv2i64 addr:$src2)))))],
3174 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3175 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3176 (ins KRC:$mask, RC:$src1, i128mem:$src2),
3177 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3178 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3179 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3180}
3181
3182defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3183 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3184 EVEX_V512, EVEX_CD8<32, CD8VF>;
3185defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
3186 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3187 EVEX_CD8<32, CD8VQ>;
3188
3189defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3190 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3191 EVEX_CD8<64, CD8VF>, VEX_W;
3192defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
3193 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3194 EVEX_CD8<64, CD8VQ>, VEX_W;
3195
3196defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3197 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
3198 EVEX_CD8<32, CD8VF>;
3199defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
3200 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3201 EVEX_CD8<32, CD8VQ>;
3202
3203defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3204 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3205 EVEX_CD8<64, CD8VF>, VEX_W;
3206defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
3207 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3208 EVEX_CD8<64, CD8VQ>, VEX_W;
3209
3210defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3211 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3212 EVEX_V512, EVEX_CD8<32, CD8VF>;
3213defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
3214 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3215 EVEX_CD8<32, CD8VQ>;
3216
3217defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3218 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3219 EVEX_CD8<64, CD8VF>, VEX_W;
3220defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
3221 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3222 EVEX_CD8<64, CD8VQ>, VEX_W;
3223
3224//===-------------------------------------------------------------------===//
3225// Variable Bit Shifts
3226//===-------------------------------------------------------------------===//
3227multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3228 RegisterClass RC, ValueType vt,
3229 X86MemOperand x86memop, PatFrag mem_frag> {
3230 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3231 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3232 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3233 [(set RC:$dst,
3234 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3235 EVEX_4V;
3236 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3237 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3238 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3239 [(set RC:$dst,
3240 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3241 EVEX_4V;
3242}
3243
3244defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3245 i512mem, memopv16i32>, EVEX_V512,
3246 EVEX_CD8<32, CD8VF>;
3247defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3248 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3249 EVEX_CD8<64, CD8VF>;
3250defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3251 i512mem, memopv16i32>, EVEX_V512,
3252 EVEX_CD8<32, CD8VF>;
3253defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3254 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3255 EVEX_CD8<64, CD8VF>;
3256defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3257 i512mem, memopv16i32>, EVEX_V512,
3258 EVEX_CD8<32, CD8VF>;
3259defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3260 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3261 EVEX_CD8<64, CD8VF>;
3262
3263//===----------------------------------------------------------------------===//
3264// AVX-512 - MOVDDUP
3265//===----------------------------------------------------------------------===//
3266
3267multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3268 X86MemOperand x86memop, PatFrag memop_frag> {
3269def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3270 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3271 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3272def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3273 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3274 [(set RC:$dst,
3275 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3276}
3277
3278defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3279 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3280def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3281 (VMOVDDUPZrm addr:$src)>;
3282
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3283//===---------------------------------------------------------------------===//
3284// Replicate Single FP - MOVSHDUP and MOVSLDUP
3285//===---------------------------------------------------------------------===//
3286multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3287 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3288 X86MemOperand x86memop> {
3289 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3290 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3291 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3292 let mayLoad = 1 in
3293 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3294 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3295 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3296}
3297
3298defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3299 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3300 EVEX_CD8<32, CD8VF>;
3301defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3302 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3303 EVEX_CD8<32, CD8VF>;
3304
3305def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3306def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3307 (VMOVSHDUPZrm addr:$src)>;
3308def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3309def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3310 (VMOVSLDUPZrm addr:$src)>;
3311
3312//===----------------------------------------------------------------------===//
3313// Move Low to High and High to Low packed FP Instructions
3314//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3315def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3316 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3317 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3318 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3319 IIC_SSE_MOV_LH>, EVEX_4V;
3320def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3321 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3322 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3323 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3324 IIC_SSE_MOV_LH>, EVEX_4V;
3325
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]3326let Predicates = [HasAVX512] in {
3327 // MOVLHPS patterns
3328 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3329 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3330 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3331 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3332
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]3333 // MOVHLPS patterns
3334 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3335 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3336}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3337
3338//===----------------------------------------------------------------------===//
3339// FMA - Fused Multiply Operations
3340//
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3341
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3342let Constraints = "$src1 = $dst" in {
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3343// Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3344multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3345 SDPatternOperator OpNode = null_frag> {
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]3346 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3347 (ins _.RC:$src2, _.RC:$src3),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3348 OpcodeStr, "$src3, $src2", "$src2, $src3",
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3349 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3350 AVX512FMA3Base;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3351
3352 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3353 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3354 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3355 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3356 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3357 (_.MemOpFrag addr:$src3))))]>;
3358 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3359 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3360 !strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
3361 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3362 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3363 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3364}
3365} // Constraints = "$src1 = $dst"
3366
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3367multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3368 string OpcodeStr, X86VectorVTInfo VTI,
3369 SDPatternOperator OpNode> {
3370 defm v213 : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3371 VTI, OpNode>,
3372 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3373
3374 defm v231 : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3375 VTI>,
3376 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3377}
3378
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3379let ExeDomain = SSEPackedSingle in {
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3380 defm VFMADDPSZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3381 v16f32_info, X86Fmadd>;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3382 defm VFMSUBPSZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3383 v16f32_info, X86Fmsub>;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3384 defm VFMADDSUBPSZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3385 v16f32_info, X86Fmaddsub>;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3386 defm VFMSUBADDPSZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3387 v16f32_info, X86Fmsubadd>;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3388 defm VFNMADDPSZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3389 v16f32_info, X86Fnmadd>;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3390 defm VFNMSUBPSZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3391 v16f32_info, X86Fnmsub>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3392}
3393let ExeDomain = SSEPackedDouble in {
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3394 defm VFMADDPDZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3395 v8f64_info, X86Fmadd>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3396 defm VFMSUBPDZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3397 v8f64_info, X86Fmsub>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3398 defm VFMADDSUBPDZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3399 v8f64_info, X86Fmaddsub>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3400 defm VFMSUBADDPDZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3401 v8f64_info, X86Fmsubadd>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3402 defm VFNMADDPDZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3403 v8f64_info, X86Fnmadd>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3404 defm VFNMSUBPDZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3405 v8f64_info, X86Fnmsub>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3406}
3407
3408let Constraints = "$src1 = $dst" in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3409multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3410 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3411 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3412 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3413 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3414 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3415 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3416 _.RC:$src3)))]>;
3417 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3418 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3419 !strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
3420 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3421 [(set _.RC:$dst,
3422 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3423 (_.ScalarLdFrag addr:$src2))),
3424 _.RC:$src3))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3425}
3426} // Constraints = "$src1 = $dst"
3427
3428
3429let ExeDomain = SSEPackedSingle in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3430 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3431 v16f32_info>,
3432 EVEX_V512, EVEX_CD8<32, CD8VF>;
3433 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3434 v16f32_info>,
3435 EVEX_V512, EVEX_CD8<32, CD8VF>;
3436 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3437 v16f32_info>,
3438 EVEX_V512, EVEX_CD8<32, CD8VF>;
3439 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3440 v16f32_info>,
3441 EVEX_V512, EVEX_CD8<32, CD8VF>;
3442 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3443 v16f32_info>,
3444 EVEX_V512, EVEX_CD8<32, CD8VF>;
3445 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3446 v16f32_info>,
3447 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3448}
3449let ExeDomain = SSEPackedDouble in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3450 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3451 v8f64_info>,
3452 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3453 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3454 v8f64_info>,
3455 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3456 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3457 v8f64_info>,
3458 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3459 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3460 v8f64_info>,
3461 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3462 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3463 v8f64_info>,
3464 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3465 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3466 v8f64_info>,
3467 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3468}
3469
3470// Scalar FMA
3471let Constraints = "$src1 = $dst" in {
3472multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3473 RegisterClass RC, ValueType OpVT,
3474 X86MemOperand x86memop, Operand memop,
3475 PatFrag mem_frag> {
3476 let isCommutable = 1 in
3477 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3478 (ins RC:$src1, RC:$src2, RC:$src3),
3479 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3480 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3481 [(set RC:$dst,
3482 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3483 let mayLoad = 1 in
3484 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3485 (ins RC:$src1, RC:$src2, f128mem:$src3),
3486 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3487 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3488 [(set RC:$dst,
3489 (OpVT (OpNode RC:$src2, RC:$src1,
3490 (mem_frag addr:$src3))))]>;
3491}
3492
3493} // Constraints = "$src1 = $dst"
3494
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3495defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3496 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3497defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3498 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3499defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3500 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3501defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3502 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3503defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3504 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3505defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3506 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3507defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3508 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3509defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3510 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3511
3512//===----------------------------------------------------------------------===//
3513// AVX-512 Scalar convert from sign integer to float/double
3514//===----------------------------------------------------------------------===//
3515
3516multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3517 X86MemOperand x86memop, string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3518let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3519 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3520 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3521 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3522 let mayLoad = 1 in
3523 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3524 (ins DstRC:$src1, x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3525 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3526 EVEX_4V;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3527} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3528}
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]3529let Predicates = [HasAVX512] in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3530defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3531 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3532defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3533 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3534defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3535 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3536defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3537 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3538
3539def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3540 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3541def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3542 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3543def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3544 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3545def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3546 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3547
3548def : Pat<(f32 (sint_to_fp GR32:$src)),
3549 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3550def : Pat<(f32 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3551 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3552def : Pat<(f64 (sint_to_fp GR32:$src)),
3553 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3554def : Pat<(f64 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3555 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3556
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3557defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3558 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3559defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3560 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3561defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3562 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3563defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3564 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3565
3566def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3567 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3568def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3569 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3570def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3571 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3572def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3573 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3574
3575def : Pat<(f32 (uint_to_fp GR32:$src)),
3576 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3577def : Pat<(f32 (uint_to_fp GR64:$src)),
3578 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3579def : Pat<(f64 (uint_to_fp GR32:$src)),
3580 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3581def : Pat<(f64 (uint_to_fp GR64:$src)),
3582 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]3583}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3584
3585//===----------------------------------------------------------------------===//
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3586// AVX-512 Scalar convert from float/double to integer
3587//===----------------------------------------------------------------------===//
3588multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3589 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3590 string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3591let hasSideEffects = 0 in {
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3592 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3593 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3594 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3595 Requires<[HasAVX512]>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3596 let mayLoad = 1 in
3597 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3598 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3599 Requires<[HasAVX512]>;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3600} // hasSideEffects = 0
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3601}
3602let Predicates = [HasAVX512] in {
3603// Convert float/double to signed/unsigned int 32/64
3604defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3605 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3606 XS, EVEX_CD8<32, CD8VT1>;
3607defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3608 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3609 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3610defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3611 ssmem, sse_load_f32, "cvtss2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3612 XS, EVEX_CD8<32, CD8VT1>;
3613defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3614 int_x86_avx512_cvtss2usi64, ssmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3615 sse_load_f32, "cvtss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3616 EVEX_CD8<32, CD8VT1>;
3617defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3618 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3619 XD, EVEX_CD8<64, CD8VT1>;
3620defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3621 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3622 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3623defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3624 sdmem, sse_load_f64, "cvtsd2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3625 XD, EVEX_CD8<64, CD8VT1>;
3626defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3627 int_x86_avx512_cvtsd2usi64, sdmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3628 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3629 EVEX_CD8<64, CD8VT1>;
3630
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3631let isCodeGenOnly = 1 in {
3632 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3633 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3634 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3635 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3636 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3637 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3638 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3639 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3640 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3641 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3642 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3643 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3644
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3645 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3646 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3647 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3648 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3649 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3650 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3651 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3652 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3653 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3654 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3655 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3656 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3657} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3658
3659// Convert float/double to signed/unsigned int 32/64 with truncation
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3660let isCodeGenOnly = 1 in {
3661 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3662 ssmem, sse_load_f32, "cvttss2si">,
3663 XS, EVEX_CD8<32, CD8VT1>;
3664 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3665 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3666 "cvttss2si">, XS, VEX_W,
3667 EVEX_CD8<32, CD8VT1>;
3668 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3669 sdmem, sse_load_f64, "cvttsd2si">, XD,
3670 EVEX_CD8<64, CD8VT1>;
3671 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3672 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3673 "cvttsd2si">, XD, VEX_W,
3674 EVEX_CD8<64, CD8VT1>;
3675 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3676 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3677 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3678 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3679 int_x86_avx512_cvttss2usi64, ssmem,
3680 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3681 EVEX_CD8<32, CD8VT1>;
3682 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3683 int_x86_avx512_cvttsd2usi,
3684 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3685 EVEX_CD8<64, CD8VT1>;
3686 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3687 int_x86_avx512_cvttsd2usi64, sdmem,
3688 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3689 EVEX_CD8<64, CD8VT1>;
3690} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3691
3692multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3693 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3694 string asm> {
3695 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3696 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3697 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3698 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3699 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3700 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3701}
3702
3703defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3704 loadf32, "cvttss2si">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3705 EVEX_CD8<32, CD8VT1>;
3706defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3707 loadf32, "cvttss2usi">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3708 EVEX_CD8<32, CD8VT1>;
3709defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3710 loadf32, "cvttss2si">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3711 EVEX_CD8<32, CD8VT1>;
3712defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3713 loadf32, "cvttss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3714 EVEX_CD8<32, CD8VT1>;
3715defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3716 loadf64, "cvttsd2si">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3717 EVEX_CD8<64, CD8VT1>;
3718defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3719 loadf64, "cvttsd2usi">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3720 EVEX_CD8<64, CD8VT1>;
3721defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3722 loadf64, "cvttsd2si">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3723 EVEX_CD8<64, CD8VT1>;
3724defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3725 loadf64, "cvttsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3726 EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3727} // HasAVX512
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3728//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3729// AVX-512 Convert form float to double and back
3730//===----------------------------------------------------------------------===//
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3731let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3732def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3733 (ins FR32X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3734 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3735 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3736let mayLoad = 1 in
3737def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3738 (ins FR32X:$src1, f32mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3739 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3740 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3741 EVEX_CD8<32, CD8VT1>;
3742
3743// Convert scalar double to scalar single
3744def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3745 (ins FR64X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3746 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3747 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3748let mayLoad = 1 in
3749def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3750 (ins FR64X:$src1, f64mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3751 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3752 []>, EVEX_4V, VEX_LIG, VEX_W,
3753 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3754}
3755
3756def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3757 Requires<[HasAVX512]>;
3758def : Pat<(fextend (loadf32 addr:$src)),
3759 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3760
3761def : Pat<(extloadf32 addr:$src),
3762 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3763 Requires<[HasAVX512, OptForSize]>;
3764
3765def : Pat<(extloadf32 addr:$src),
3766 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3767 Requires<[HasAVX512, OptForSpeed]>;
3768
3769def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3770 Requires<[HasAVX512]>;
3771
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3772multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3773 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3774 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3775 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3776let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3777 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3778 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3779 [(set DstRC:$dst,
3780 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3781 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3782 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3783 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3784 let mayLoad = 1 in
3785 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3786 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3787 [(set DstRC:$dst,
3788 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3789} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3790}
3791
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3792multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3793 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3794 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3795 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3796let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3797 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3798 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3799 [(set DstRC:$dst,
3800 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3801 let mayLoad = 1 in
3802 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3803 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3804 [(set DstRC:$dst,
3805 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3806} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3807}
3808
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3809defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3810 memopv8f64, f512mem, v8f32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3811 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3812 EVEX_CD8<64, CD8VF>;
3813
3814defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3815 memopv4f64, f256mem, v8f64, v8f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3816 SSEPackedDouble>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3817 EVEX_CD8<32, CD8VH>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3818def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3819 (VCVTPS2PDZrm addr:$src)>;
Elena Demikhovsky3629b4a2014-01-06 08:45:54 +0000[diff] [blame]3820
3821def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3822 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3823 (VCVTPD2PSZrr VR512:$src)>;
3824
3825def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3826 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3827 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3828
3829//===----------------------------------------------------------------------===//
3830// AVX-512 Vector convert from sign integer to float/double
3831//===----------------------------------------------------------------------===//
3832
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3833defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3834 memopv8i64, i512mem, v16f32, v16i32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3835 SSEPackedSingle>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3836 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3837
3838defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3839 memopv4i64, i256mem, v8f64, v8i32,
3840 SSEPackedDouble>, EVEX_V512, XS,
3841 EVEX_CD8<32, CD8VH>;
3842
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3843defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3844 memopv16f32, f512mem, v16i32, v16f32,
3845 SSEPackedSingle>, EVEX_V512, XS,
3846 EVEX_CD8<32, CD8VF>;
3847
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3848defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3849 memopv8f64, f512mem, v8i32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3850 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3851 EVEX_CD8<64, CD8VF>;
3852
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3853defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3854 memopv16f32, f512mem, v16i32, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3855 SSEPackedSingle>, EVEX_V512, PS,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3856 EVEX_CD8<32, CD8VF>;
3857
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3858// cvttps2udq (src, 0, mask-all-ones, sae-current)
3859def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3860 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3861 (VCVTTPS2UDQZrr VR512:$src)>;
3862
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3863defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3864 memopv8f64, f512mem, v8i32, v8f64,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3865 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3866 EVEX_CD8<64, CD8VF>;
3867
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3868// cvttpd2udq (src, 0, mask-all-ones, sae-current)
3869def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3870 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3871 (VCVTTPD2UDQZrr VR512:$src)>;
3872
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3873defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3874 memopv4i64, f256mem, v8f64, v8i32,
3875 SSEPackedDouble>, EVEX_V512, XS,
3876 EVEX_CD8<32, CD8VH>;
3877
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3878defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3879 memopv16i32, f512mem, v16f32, v16i32,
3880 SSEPackedSingle>, EVEX_V512, XD,
3881 EVEX_CD8<32, CD8VF>;
3882
3883def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3884 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3885 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3886
Elena Demikhovsky3dcfbdf2014-04-08 07:24:02 +0000[diff] [blame]3887def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3888 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3889 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3890
3891def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3892 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3893 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3894
3895def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3896 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3897 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3898
Cameron McInallyf10a7c92014-06-18 14:04:37 +0000[diff] [blame]3899def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3900 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3901 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3902
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3903def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3904 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3905 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3906def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3907 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3908 (VCVTDQ2PDZrr VR256X:$src)>;
3909def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3910 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3911 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3912def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3913 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3914 (VCVTUDQ2PDZrr VR256X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3915
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3916multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3917 RegisterClass DstRC, PatFrag mem_frag,
3918 X86MemOperand x86memop, Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3919let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3920 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3921 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3922 [], d>, EVEX;
3923 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3924 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3925 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3926 let mayLoad = 1 in
3927 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3928 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3929 [], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3930} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3931}
3932
3933defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3934 memopv16f32, f512mem, SSEPackedSingle>, PD,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3935 EVEX_V512, EVEX_CD8<32, CD8VF>;
3936defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3937 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3938 EVEX_V512, EVEX_CD8<64, CD8VF>;
3939
3940def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3941 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3942 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3943
3944def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3945 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3946 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3947
3948defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3949 memopv16f32, f512mem, SSEPackedSingle>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3950 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3951defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3952 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3953 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3954
3955def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3956 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3957 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3958
3959def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3960 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3961 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3962
3963let Predicates = [HasAVX512] in {
3964 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3965 (VCVTPD2PSZrm addr:$src)>;
3966 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3967 (VCVTPS2PDZrm addr:$src)>;
3968}
3969
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3970//===----------------------------------------------------------------------===//
3971// Half precision conversion instructions
3972//===----------------------------------------------------------------------===//
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3973multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3974 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3975 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3976 "vcvtph2ps\t{$src, $dst|$dst, $src}",
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3977 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3978 let hasSideEffects = 0, mayLoad = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3979 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3980 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3981}
3982
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3983multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3984 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3985 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3986 (ins srcRC:$src1, i32i8imm:$src2),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3987 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3988 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3989 let hasSideEffects = 0, mayStore = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3990 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3991 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3992 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3993}
3994
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3995defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3996 EVEX_CD8<32, CD8VH>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3997defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3998 EVEX_CD8<32, CD8VH>;
3999
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]4000def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4001 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4002 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4003
4004def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4005 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4006 (VCVTPH2PSZrr VR256X:$src)>;
4007
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4008let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4009 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]4010 "ucomiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4011 EVEX_CD8<32, CD8VT1>;
4012 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]4013 "ucomisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4014 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4015 let Pattern = []<dag> in {
4016 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]4017 "comiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4018 EVEX_CD8<32, CD8VT1>;
4019 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]4020 "comisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4021 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4022 }
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4023 let isCodeGenOnly = 1 in {
4024 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]4025 load, "ucomiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4026 EVEX_CD8<32, CD8VT1>;
4027 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]4028 load, "ucomisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4029 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4030
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4031 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]4032 load, "comiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4033 EVEX_CD8<32, CD8VT1>;
4034 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]4035 load, "comisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4036 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4037 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4038}
4039
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4040/// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4041multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4042 X86MemOperand x86memop> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4043 let hasSideEffects = 0 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4044 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4045 (ins RC:$src1, RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4046 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4047 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4048 let mayLoad = 1 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4049 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4050 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4051 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4052 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4053 }
4054}
4055}
4056
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4057defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4058 EVEX_CD8<32, CD8VT1>;
4059defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4060 VEX_W, EVEX_CD8<64, CD8VT1>;
4061defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4062 EVEX_CD8<32, CD8VT1>;
4063defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4064 VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4065
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4066def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4067 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4068 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4069 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4070
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4071def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4072 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4073 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4074 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4075
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4076def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4077 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4078 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4079 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4080
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4081def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4082 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4083 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4084 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4085
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4086/// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4087multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanov3e534c92014-10-28 16:37:13 +0000[diff] [blame]4088 X86VectorVTInfo _> {
4089 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4090 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4091 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4092 let mayLoad = 1 in {
4093 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4094 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4095 (OpNode (_.FloatVT
4096 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4097 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4098 (ins _.ScalarMemOp:$src), OpcodeStr,
4099 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4100 (OpNode (_.FloatVT
4101 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4102 EVEX, T8PD, EVEX_B;
4103 }
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4104}
Robert Khasanov3e534c92014-10-28 16:37:13 +0000[diff] [blame]4105
4106multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4107 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4108 EVEX_V512, EVEX_CD8<32, CD8VF>;
4109 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4110 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4111
4112 // Define only if AVX512VL feature is present.
4113 let Predicates = [HasVLX] in {
4114 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4115 OpNode, v4f32x_info>,
4116 EVEX_V128, EVEX_CD8<32, CD8VF>;
4117 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4118 OpNode, v8f32x_info>,
4119 EVEX_V256, EVEX_CD8<32, CD8VF>;
4120 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4121 OpNode, v2f64x_info>,
4122 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4123 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4124 OpNode, v4f64x_info>,
4125 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4126 }
4127}
4128
4129defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4130defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4131
4132def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4133 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4134 (VRSQRT14PSZr VR512:$src)>;
4135def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4136 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4137 (VRSQRT14PDZr VR512:$src)>;
4138
4139def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4140 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4141 (VRCP14PSZr VR512:$src)>;
4142def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4143 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4144 (VRCP14PDZr VR512:$src)>;
4145
4146/// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4147multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4148 X86MemOperand x86memop> {
4149 let hasSideEffects = 0, Predicates = [HasERI] in {
4150 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4151 (ins RC:$src1, RC:$src2),
4152 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4153 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4154 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4155 (ins RC:$src1, RC:$src2),
4156 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4157 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4158 []>, EVEX_4V, EVEX_B;
4159 let mayLoad = 1 in {
4160 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4161 (ins RC:$src1, x86memop:$src2),
4162 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4163 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4164 }
4165}
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4166}
4167
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4168defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
4169 EVEX_CD8<32, CD8VT1>;
4170defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
4171 VEX_W, EVEX_CD8<64, CD8VT1>;
4172defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
4173 EVEX_CD8<32, CD8VT1>;
4174defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
4175 VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4176
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4177def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
4178 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4179 FROUND_NO_EXC)),
4180 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4181 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4182
4183def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
4184 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4185 FROUND_NO_EXC)),
4186 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4187 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4188
4189def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
4190 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4191 FROUND_NO_EXC)),
4192 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4193 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4194
4195def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
4196 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4197 FROUND_NO_EXC)),
4198 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4199 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4200
4201/// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4202multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
4203 RegisterClass RC, X86MemOperand x86memop> {
4204 let hasSideEffects = 0, Predicates = [HasERI] in {
4205 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4206 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4207 " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4208 []>, EVEX;
4209 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4210 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4211 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4212 []>, EVEX, EVEX_B;
4213 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4214 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4215 []>, EVEX;
4216 }
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4217}
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4218defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
4219 EVEX_V512, EVEX_CD8<32, CD8VF>;
4220defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
4221 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4222defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
4223 EVEX_V512, EVEX_CD8<32, CD8VF>;
4224defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
4225 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4226
4227def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
4228 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4229 (VRSQRT28PSZrb VR512:$src)>;
4230def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
4231 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4232 (VRSQRT28PDZrb VR512:$src)>;
4233
4234def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
4235 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4236 (VRCP28PSZrb VR512:$src)>;
4237def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
4238 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4239 (VRCP28PDZrb VR512:$src)>;
4240
Robert Khasanoveb126392014-10-28 18:15:20 +0000[diff] [blame]4241multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4242 SDNode OpNode, X86VectorVTInfo _>{
Robert Khasanov1cf354c2014-10-28 18:22:41 +0000[diff] [blame]4243 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
Robert Khasanoveb126392014-10-28 18:15:20 +0000[diff] [blame]4244 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4245 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4246 let mayLoad = 1 in {
Robert Khasanov1cf354c2014-10-28 18:22:41 +0000[diff] [blame]4247 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
Robert Khasanoveb126392014-10-28 18:15:20 +0000[diff] [blame]4248 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4249 (OpNode (_.FloatVT
4250 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4251
Robert Khasanov1cf354c2014-10-28 18:22:41 +0000[diff] [blame]4252 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
Robert Khasanoveb126392014-10-28 18:15:20 +0000[diff] [blame]4253 (ins _.ScalarMemOp:$src), OpcodeStr,
4254 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4255 (OpNode (_.FloatVT
4256 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4257 EVEX, EVEX_B;
4258 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4259}
4260
4261multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4262 Intrinsic F32Int, Intrinsic F64Int,
4263 OpndItins itins_s, OpndItins itins_d> {
4264 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4265 (ins FR32X:$src1, FR32X:$src2),
4266 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4267 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4268 [], itins_s.rr>, XS, EVEX_4V;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4269 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4270 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4271 (ins VR128X:$src1, VR128X:$src2),
4272 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4273 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4274 [(set VR128X:$dst,
4275 (F32Int VR128X:$src1, VR128X:$src2))],
4276 itins_s.rr>, XS, EVEX_4V;
4277 let mayLoad = 1 in {
4278 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4279 (ins FR32X:$src1, f32mem:$src2),
4280 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4281 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4282 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4283 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4284 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4285 (ins VR128X:$src1, ssmem:$src2),
4286 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4287 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4288 [(set VR128X:$dst,
4289 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4290 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4291 }
4292 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4293 (ins FR64X:$src1, FR64X:$src2),
4294 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4295 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4296 XD, EVEX_4V, VEX_W;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4297 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4298 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4299 (ins VR128X:$src1, VR128X:$src2),
4300 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4301 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4302 [(set VR128X:$dst,
4303 (F64Int VR128X:$src1, VR128X:$src2))],
4304 itins_s.rr>, XD, EVEX_4V, VEX_W;
4305 let mayLoad = 1 in {
4306 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4307 (ins FR64X:$src1, f64mem:$src2),
4308 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4309 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4310 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4311 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4312 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4313 (ins VR128X:$src1, sdmem:$src2),
4314 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4315 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4316 [(set VR128X:$dst,
4317 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4318 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4319 }
4320}
4321
Robert Khasanoveb126392014-10-28 18:15:20 +0000[diff] [blame]4322multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4323 SDNode OpNode> {
4324 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4325 v16f32_info>,
4326 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4327 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4328 v8f64_info>,
4329 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4330 // Define only if AVX512VL feature is present.
4331 let Predicates = [HasVLX] in {
4332 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4333 OpNode, v4f32x_info>,
4334 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4335 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4336 OpNode, v8f32x_info>,
4337 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4338 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4339 OpNode, v2f64x_info>,
4340 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4341 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4342 OpNode, v4f64x_info>,
4343 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4344 }
4345}
4346
4347defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4348
4349defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4350 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
Robert Khasanoveb126392014-10-28 18:15:20 +0000[diff] [blame]4351 SSE_SQRTSS, SSE_SQRTSD>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4352
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4353let Predicates = [HasAVX512] in {
Elena Demikhovskyf1648592014-07-22 11:07:31 +0000[diff] [blame]4354 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4355 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
Robert Khasanov1cf354c2014-10-28 18:22:41 +0000[diff] [blame]4356 (VSQRTPSZr VR512:$src1)>;
Elena Demikhovskyf1648592014-07-22 11:07:31 +0000[diff] [blame]4357 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4358 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
Robert Khasanov1cf354c2014-10-28 18:22:41 +0000[diff] [blame]4359 (VSQRTPDZr VR512:$src1)>;
Elena Demikhovskyf1648592014-07-22 11:07:31 +0000[diff] [blame]4360
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4361 def : Pat<(f32 (fsqrt FR32X:$src)),
4362 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4363 def : Pat<(f32 (fsqrt (load addr:$src))),
4364 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4365 Requires<[OptForSize]>;
4366 def : Pat<(f64 (fsqrt FR64X:$src)),
4367 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4368 def : Pat<(f64 (fsqrt (load addr:$src))),
4369 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4370 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4371
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4372 def : Pat<(f32 (X86frsqrt FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4373 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4374 def : Pat<(f32 (X86frsqrt (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4375 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4376 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4377
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4378 def : Pat<(f32 (X86frcp FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4379 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4380 def : Pat<(f32 (X86frcp (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4381 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4382 Requires<[OptForSize]>;
4383
4384 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4385 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4386 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4387 VR128X)>;
4388 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4389 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4390
4391 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4392 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4393 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4394 VR128X)>;
4395 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4396 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4397}
4398
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4399
4400multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4401 X86MemOperand x86memop, RegisterClass RC,
4402 PatFrag mem_frag32, PatFrag mem_frag64,
4403 Intrinsic V4F32Int, Intrinsic V2F64Int,
4404 CD8VForm VForm> {
4405let ExeDomain = SSEPackedSingle in {
4406 // Intrinsic operation, reg.
4407 // Vector intrinsic operation, reg
4408 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4409 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4410 !strconcat(OpcodeStr,
4411 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4412 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4413
4414 // Vector intrinsic operation, mem
4415 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4416 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4417 !strconcat(OpcodeStr,
4418 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4419 [(set RC:$dst,
4420 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4421 EVEX_CD8<32, VForm>;
4422} // ExeDomain = SSEPackedSingle
4423
4424let ExeDomain = SSEPackedDouble in {
4425 // Vector intrinsic operation, reg
4426 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4427 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4428 !strconcat(OpcodeStr,
4429 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4430 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4431
4432 // Vector intrinsic operation, mem
4433 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4434 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4435 !strconcat(OpcodeStr,
4436 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4437 [(set RC:$dst,
4438 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4439 EVEX_CD8<64, VForm>;
4440} // ExeDomain = SSEPackedDouble
4441}
4442
4443multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4444 string OpcodeStr,
4445 Intrinsic F32Int,
4446 Intrinsic F64Int> {
4447let ExeDomain = GenericDomain in {
4448 // Operation, reg.
4449 let hasSideEffects = 0 in
4450 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4451 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4452 !strconcat(OpcodeStr,
4453 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4454 []>;
4455
4456 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4457 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4458 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4459 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4460 !strconcat(OpcodeStr,
4461 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4462 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4463
4464 // Intrinsic operation, mem.
4465 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4466 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4467 !strconcat(OpcodeStr,
4468 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4469 [(set VR128X:$dst, (F32Int VR128X:$src1,
4470 sse_load_f32:$src2, imm:$src3))]>,
4471 EVEX_CD8<32, CD8VT1>;
4472
4473 // Operation, reg.
4474 let hasSideEffects = 0 in
4475 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4476 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4477 !strconcat(OpcodeStr,
4478 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4479 []>, VEX_W;
4480
4481 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4482 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4483 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4484 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4485 !strconcat(OpcodeStr,
4486 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4487 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4488 VEX_W;
4489
4490 // Intrinsic operation, mem.
4491 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4492 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4493 !strconcat(OpcodeStr,
4494 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4495 [(set VR128X:$dst,
4496 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4497 VEX_W, EVEX_CD8<64, CD8VT1>;
4498} // ExeDomain = GenericDomain
4499}
4500
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4501multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4502 X86MemOperand x86memop, RegisterClass RC,
4503 PatFrag mem_frag, Domain d> {
4504let ExeDomain = d in {
4505 // Intrinsic operation, reg.
4506 // Vector intrinsic operation, reg
4507 def r : AVX512AIi8<opc, MRMSrcReg,
4508 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4509 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4510 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4511 []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4512
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4513 // Vector intrinsic operation, mem
4514 def m : AVX512AIi8<opc, MRMSrcMem,
4515 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4516 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4517 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4518 []>, EVEX;
4519} // ExeDomain
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4520}
4521
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4522
4523defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4524 memopv16f32, SSEPackedSingle>, EVEX_V512,
4525 EVEX_CD8<32, CD8VF>;
4526
4527def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]4528 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4529 FROUND_CURRENT)),
4530 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4531
4532
4533defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4534 memopv8f64, SSEPackedDouble>, EVEX_V512,
4535 VEX_W, EVEX_CD8<64, CD8VF>;
4536
4537def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]4538 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4539 FROUND_CURRENT)),
4540 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4541
4542multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4543 Operand x86memop, RegisterClass RC, Domain d> {
4544let ExeDomain = d in {
4545 def r : AVX512AIi8<opc, MRMSrcReg,
4546 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4547 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4548 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4549 []>, EVEX_4V;
4550
4551 def m : AVX512AIi8<opc, MRMSrcMem,
4552 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4553 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4554 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4555 []>, EVEX_4V;
4556} // ExeDomain
4557}
4558
4559defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4560 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4561
4562defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4563 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4564
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4565def : Pat<(ffloor FR32X:$src),
4566 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4567def : Pat<(f64 (ffloor FR64X:$src)),
4568 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4569def : Pat<(f32 (fnearbyint FR32X:$src)),
4570 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4571def : Pat<(f64 (fnearbyint FR64X:$src)),
4572 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4573def : Pat<(f32 (fceil FR32X:$src)),
4574 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4575def : Pat<(f64 (fceil FR64X:$src)),
4576 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4577def : Pat<(f32 (frint FR32X:$src)),
4578 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4579def : Pat<(f64 (frint FR64X:$src)),
4580 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4581def : Pat<(f32 (ftrunc FR32X:$src)),
4582 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4583def : Pat<(f64 (ftrunc FR64X:$src)),
4584 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4585
4586def : Pat<(v16f32 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4587 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4588def : Pat<(v16f32 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4589 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4590def : Pat<(v16f32 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4591 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4592def : Pat<(v16f32 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4593 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4594def : Pat<(v16f32 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4595 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4596
4597def : Pat<(v8f64 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4598 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4599def : Pat<(v8f64 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4600 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4601def : Pat<(v8f64 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4602 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4603def : Pat<(v8f64 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4604 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4605def : Pat<(v8f64 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4606 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4607
4608//-------------------------------------------------
4609// Integer truncate and extend operations
4610//-------------------------------------------------
4611
4612multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4613 RegisterClass dstRC, RegisterClass srcRC,
4614 RegisterClass KRC, X86MemOperand x86memop> {
4615 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4616 (ins srcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4617 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4618 []>, EVEX;
4619
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4620 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4621 (ins KRC:$mask, srcRC:$src),
4622 !strconcat(OpcodeStr,
4623 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4624 []>, EVEX, EVEX_K;
4625
4626 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4627 (ins KRC:$mask, srcRC:$src),
4628 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4629 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4630 []>, EVEX, EVEX_KZ;
4631
4632 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4633 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4634 []>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4635
4636 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4637 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4638 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4639 []>, EVEX, EVEX_K;
4640
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4641}
4642defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4643 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4644defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4645 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4646defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4647 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4648defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4649 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4650defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4651 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4652defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4653 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4654defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4655 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4656defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4657 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4658defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4659 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4660defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4661 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4662defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4663 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4664defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4665 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4666defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4667 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4668defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4669 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4670defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4671 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4672
4673def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4674def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4675def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4676def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4677def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4678
4679def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4680 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4681def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4682 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4683def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4684 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4685def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4686 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4687
4688
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4689multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4690 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4691 PatFrag mem_frag, X86MemOperand x86memop,
4692 ValueType OpVT, ValueType InVT> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4693
4694 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4695 (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4696 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4697 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4698
4699 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4700 (ins KRC:$mask, SrcRC:$src),
4701 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4702 []>, EVEX, EVEX_K;
4703
4704 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4705 (ins KRC:$mask, SrcRC:$src),
4706 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4707 []>, EVEX, EVEX_KZ;
4708
4709 let mayLoad = 1 in {
4710 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4711 (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4712 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4713 [(set DstRC:$dst,
4714 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4715 EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4716
4717 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4718 (ins KRC:$mask, x86memop:$src),
4719 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4720 []>,
4721 EVEX, EVEX_K;
4722
4723 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4724 (ins KRC:$mask, x86memop:$src),
4725 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4726 []>,
4727 EVEX, EVEX_KZ;
4728 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4729}
4730
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4731defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4732 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4733 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4734defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4735 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4736 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4737defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4738 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4739 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4740defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4741 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4742 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4743defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4744 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4745 EVEX_CD8<32, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4746
4747defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4748 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4749 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4750defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4751 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4752 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4753defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4754 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4755 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4756defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4757 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4758 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4759defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4760 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4761 EVEX_CD8<32, CD8VH>;
4762
4763//===----------------------------------------------------------------------===//
4764// GATHER - SCATTER Operations
4765
4766multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4767 RegisterClass RC, X86MemOperand memop> {
4768let mayLoad = 1,
4769 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4770 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4771 (ins RC:$src1, KRC:$mask, memop:$src2),
4772 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4773 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4774 []>, EVEX, EVEX_K;
4775}
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4776
4777let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4778defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4779 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4780defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4781 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4782}
4783
4784let ExeDomain = SSEPackedSingle in {
4785defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4786 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4787defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4788 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4789}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4790
4791defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4792 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4793defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4794 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4795
4796defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4797 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4798defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4799 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4800
4801multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4802 RegisterClass RC, X86MemOperand memop> {
4803let mayStore = 1, Constraints = "$mask = $mask_wb" in
4804 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4805 (ins memop:$dst, KRC:$mask, RC:$src2),
4806 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4807 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4808 []>, EVEX, EVEX_K;
4809}
4810
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4811let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4812defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4813 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4814defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4815 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4816}
4817
4818let ExeDomain = SSEPackedSingle in {
4819defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4820 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4821defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4822 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4823}
4824
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4825defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4826 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4827defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4828 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4829
4830defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4831 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4832defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4833 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4834
Elena Demikhovsky8e8fde82014-05-12 07:18:51 +0000[diff] [blame]4835// prefetch
4836multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4837 RegisterClass KRC, X86MemOperand memop> {
4838 let Predicates = [HasPFI], hasSideEffects = 1 in
4839 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4840 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4841 []>, EVEX, EVEX_K;
4842}
4843
4844defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4845 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4846
4847defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4848 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4849
4850defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4851 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4852
4853defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4854 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4855
4856defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4857 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4858
4859defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4860 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4861
4862defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4863 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4864
4865defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4866 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4867
4868defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4869 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4870
4871defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4872 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4873
4874defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4875 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4876
4877defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4878 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4879
4880defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4881 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4882
4883defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4884 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4885
4886defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4887 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4888
4889defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4890 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4891//===----------------------------------------------------------------------===//
4892// VSHUFPS - VSHUFPD Operations
4893
4894multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4895 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4896 Domain d> {
4897 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4898 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4899 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4900 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4901 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4902 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]4903 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4904 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4905 (ins RC:$src1, RC:$src2, i8imm:$src3),
4906 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4907 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4908 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4909 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]4910 EVEX_4V, Sched<[WriteShuffle]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4911}
4912
4913defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]4914 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4915defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]4916 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4917
Elena Demikhovsky462a2d22013-10-06 06:11:18 +0000[diff] [blame]4918def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4919 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4920def : Pat<(v16i32 (X86Shufp VR512:$src1,
4921 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4922 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4923
4924def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4925 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4926def : Pat<(v8i64 (X86Shufp VR512:$src1,
4927 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4928 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4929
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4930multiclass avx512_valign<X86VectorVTInfo _> {
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]4931 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4932 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4933 "valign"##_.Suffix,
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]4934 "$src3, $src2, $src1", "$src1, $src2, $src3",
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4935 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]4936 (i8 imm:$src3)))>,
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]4937 AVX512AIi8Base, EVEX_4V;
Adam Nemetfd2161b2014-08-05 17:23:04 +0000[diff] [blame]4938
Adam Nemetf92139d2014-08-05 17:22:50 +0000[diff] [blame]4939 // Also match valign of packed floats.
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4940 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4941 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
Adam Nemetf92139d2014-08-05 17:22:50 +0000[diff] [blame]4942
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4943 let mayLoad = 1 in
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4944 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4945 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4946 !strconcat("valign"##_.Suffix,
Adam Nemet1c752d82014-08-05 17:22:47 +0000[diff] [blame]4947 " \t{$src3, $src2, $src1, $dst|"
4948 "$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4949 []>, EVEX_4V;
4950}
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4951defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4952defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4953
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4954// Helper fragments to match sext vXi1 to vXiY.
4955def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4956def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4957
4958multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4959 RegisterClass KRC, RegisterClass RC,
4960 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4961 string BrdcstStr> {
4962 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4963 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4964 []>, EVEX;
4965 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4966 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4967 []>, EVEX, EVEX_K;
4968 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4969 !strconcat(OpcodeStr,
4970 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4971 []>, EVEX, EVEX_KZ;
4972 let mayLoad = 1 in {
4973 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4974 (ins x86memop:$src),
4975 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4976 []>, EVEX;
4977 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4978 (ins KRC:$mask, x86memop:$src),
4979 !strconcat(OpcodeStr,
4980 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4981 []>, EVEX, EVEX_K;
4982 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4983 (ins KRC:$mask, x86memop:$src),
4984 !strconcat(OpcodeStr,
4985 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4986 []>, EVEX, EVEX_KZ;
4987 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4988 (ins x86scalar_mop:$src),
4989 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4990 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4991 []>, EVEX, EVEX_B;
4992 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4993 (ins KRC:$mask, x86scalar_mop:$src),
4994 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4995 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4996 []>, EVEX, EVEX_B, EVEX_K;
4997 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4998 (ins KRC:$mask, x86scalar_mop:$src),
4999 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
5000 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5001 BrdcstStr, "}"),
5002 []>, EVEX, EVEX_B, EVEX_KZ;
5003 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]5004}
5005
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]5006defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5007 i512mem, i32mem, "{1to16}">, EVEX_V512,
5008 EVEX_CD8<32, CD8VF>;
5009defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5010 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5011 EVEX_CD8<64, CD8VF>;
5012
5013def : Pat<(xor
5014 (bc_v16i32 (v16i1sextv16i32)),
5015 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5016 (VPABSDZrr VR512:$src)>;
5017def : Pat<(xor
5018 (bc_v8i64 (v8i1sextv8i64)),
5019 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5020 (VPABSQZrr VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]5021
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]5022def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5023 (v16i32 immAllZerosV), (i16 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]5024 (VPABSDZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]5025def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5026 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]5027 (VPABSQZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]5028
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5029multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5030 RegisterClass RC, RegisterClass KRC,
5031 X86MemOperand x86memop,
5032 X86MemOperand x86scalar_mop, string BrdcstStr> {
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5033 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5034 (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5035 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5036 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5037 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5038 (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5039 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5040 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5041 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5042 (ins x86scalar_mop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5043 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5044 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5045 []>, EVEX, EVEX_B;
5046 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5047 (ins KRC:$mask, RC:$src),
5048 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5049 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5050 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5051 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5052 (ins KRC:$mask, x86memop:$src),
5053 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5054 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5055 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5056 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5057 (ins KRC:$mask, x86scalar_mop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5058 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5059 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5060 BrdcstStr, "}"),
5061 []>, EVEX, EVEX_KZ, EVEX_B;
5062
5063 let Constraints = "$src1 = $dst" in {
5064 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5065 (ins RC:$src1, KRC:$mask, RC:$src2),
5066 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5067 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5068 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5069 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5070 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5071 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5072 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5073 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5074 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5075 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5076 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5077 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5078 []>, EVEX, EVEX_K, EVEX_B;
5079 }
5080}
5081
5082let Predicates = [HasCDI] in {
5083defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5084 i512mem, i32mem, "{1to16}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5085 EVEX_V512, EVEX_CD8<32, CD8VF>;
5086
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5087
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5088defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5089 i512mem, i64mem, "{1to8}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5090 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5091
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5092}
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5093
5094def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5095 GR16:$mask),
5096 (VPCONFLICTDrrk VR512:$src1,
5097 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5098
5099def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5100 GR8:$mask),
5101 (VPCONFLICTQrrk VR512:$src1,
5102 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]5103
Cameron McInally5d1b7b92014-06-11 12:54:45 +0000[diff] [blame]5104let Predicates = [HasCDI] in {
5105defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5106 i512mem, i32mem, "{1to16}">,
5107 EVEX_V512, EVEX_CD8<32, CD8VF>;
5108
5109
5110defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5111 i512mem, i64mem, "{1to8}">,
5112 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5113
5114}
5115
5116def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5117 GR16:$mask),
5118 (VPLZCNTDrrk VR512:$src1,
5119 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5120
5121def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5122 GR8:$mask),
5123 (VPLZCNTQrrk VR512:$src1,
5124 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5125
Cameron McInally0d0489c2014-06-16 14:12:28 +0000[diff] [blame]5126def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5127 (VPLZCNTDrm addr:$src)>;
5128def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5129 (VPLZCNTDrr VR512:$src)>;
5130def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5131 (VPLZCNTQrm addr:$src)>;
5132def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5133 (VPLZCNTQrr VR512:$src)>;
5134
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]5135def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5136def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5137def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
Elena Demikhovskyacc5c9e2014-04-22 14:13:10 +0000[diff] [blame]5138
5139def : Pat<(store VK1:$src, addr:$dst),
5140 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5141
5142def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5143 (truncstore node:$val, node:$ptr), [{
5144 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5145}]>;
5146
5147def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5148 (MOV8mr addr:$dst, GR8:$src)>;
5149
Elena Demikhovsky44bf0632014-10-05 14:11:08 +0000[diff] [blame]5150multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5151def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5152 !strconcat(OpcodeStr##Vec.Suffix, " \t{$src, $dst|$dst, $src}"),
5153 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5154}
5155
5156multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5157 string OpcodeStr, Predicate prd> {
5158let Predicates = [prd] in
5159 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5160
5161 let Predicates = [prd, HasVLX] in {
5162 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5163 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5164 }
5165}
5166
5167multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5168 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5169 HasBWI>;
5170 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5171 HasBWI>, VEX_W;
5172 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5173 HasDQI>;
5174 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5175 HasDQI>, VEX_W;
5176}
5177
5178defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;