blob: d378bd736a5a4cb398d02b389468862200d0ce78 [file] [log] [blame]
Adam Nemet5ed17da2014-08-21 19:50:07 +00001// Group template arguments that can be derived from the vector type (EltNum x
2// EltVT). These are things like the register class for the writemask, etc.
3// The idea is to pass one of these as the template argument rather than the
4// individual arguments.
Elena Demikhovskyfa4a6c12014-12-09 07:06:32 +00005// The template is also used for scalar types, in this case numelts is 1.
Adam Nemet449b3f02014-10-15 23:42:09 +00006class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc,
Adam Nemet5ed17da2014-08-21 19:50:07 +00007 string suffix = ""> {
8 RegisterClass RC = rc;
Adam Nemet449b3f02014-10-15 23:42:09 +00009 int NumElts = numelts;
Adam Nemet5ed17da2014-08-21 19:50:07 +000010
11 // Corresponding mask register class.
12 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
13
14 // Corresponding write-mask register class.
15 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
16
17 // The GPR register class that can hold the write mask. Use GR8 for fewer
18 // than 8 elements. Use shift-right and equal to work around the lack of
19 // !lt in tablegen.
20 RegisterClass MRC =
21 !cast<RegisterClass>("GR" #
22 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
23
24 // Suffix used in the instruction mnemonic.
25 string Suffix = suffix;
26
Elena Demikhovskyfa4a6c12014-12-09 07:06:32 +000027 // VTName is a string name for vector VT. For vector types it will be
28 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
29 // It is a little bit complex for scalar types, where NumElts = 1.
30 // In this case we build v4f32 or v2f64
31 string VTName = "v" # !if (!eq (NumElts, 1),
32 !if (!eq (EltVT.Size, 32), 4,
33 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
Robert Khasanov2ea081d2014-08-25 14:49:34 +000034
Adam Nemet5ed17da2014-08-21 19:50:07 +000035 // The vector VT.
Robert Khasanov2ea081d2014-08-25 14:49:34 +000036 ValueType VT = !cast<ValueType>(VTName);
Adam Nemet5ed17da2014-08-21 19:50:07 +000037
38 string EltTypeName = !cast<string>(EltVT);
39 // Size of the element type in bits, e.g. 32 for v16i32.
Robert Khasanov2ea081d2014-08-25 14:49:34 +000040 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
41 int EltSize = EltVT.Size;
Adam Nemet5ed17da2014-08-21 19:50:07 +000042
43 // "i" for integer types and "f" for floating-point types
Robert Khasanov2ea081d2014-08-25 14:49:34 +000044 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
Adam Nemet5ed17da2014-08-21 19:50:07 +000045
46 // Size of RC in bits, e.g. 512 for VR512.
47 int Size = VT.Size;
48
49 // The corresponding memory operand, e.g. i512mem for VR512.
50 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
Robert Khasanov2ea081d2014-08-25 14:49:34 +000051 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
52
53 // Load patterns
54 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
55 // due to load promotion during legalization
56 PatFrag LdFrag = !cast<PatFrag>("load" #
57 !if (!eq (TypeVariantName, "i"),
58 !if (!eq (Size, 128), "v2i64",
59 !if (!eq (Size, 256), "v4i64",
60 VTName)), VTName));
61 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
Adam Nemet5ed17da2014-08-21 19:50:07 +000062
Adam Nemet6bddb8c2014-09-29 22:54:41 +000063 // Load patterns used for memory operands. We only have this defined in
64 // case of i64 element types for sub-512 integer vectors. For now, keep
65 // MemOpFrag undefined in these cases.
66 PatFrag MemOpFrag =
Elena Demikhovsky905a5a62014-11-26 10:46:49 +000067 !if (!eq (NumElts#EltTypeName, "1f32"), !cast<PatFrag>("memopfsf32"),
68 !if (!eq (NumElts#EltTypeName, "1f64"), !cast<PatFrag>("memopfsf64"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +000069 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
70 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
Elena Demikhovsky905a5a62014-11-26 10:46:49 +000071 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)))));
Adam Nemet6bddb8c2014-09-29 22:54:41 +000072
Adam Nemet5ed17da2014-08-21 19:50:07 +000073 // The corresponding float type, e.g. v16f32 for v16i32
Robert Khasanov2ea081d2014-08-25 14:49:34 +000074 // Note: For EltSize < 32, FloatVT is illegal and TableGen
75 // fails to compile, so we choose FloatVT = VT
76 ValueType FloatVT = !cast<ValueType>(
77 !if (!eq (!srl(EltSize,5),0),
78 VTName,
79 !if (!eq(TypeVariantName, "i"),
80 "v" # NumElts # "f" # EltSize,
81 VTName)));
Adam Nemet5ed17da2014-08-21 19:50:07 +000082
83 // The string to specify embedded broadcast in assembly.
84 string BroadcastStr = "{1to" # NumElts # "}";
Adam Nemet55536c62014-09-25 23:48:45 +000085
Adam Nemet449b3f02014-10-15 23:42:09 +000086 // 8-bit compressed displacement tuple/subvector format. This is only
87 // defined for NumElts <= 8.
88 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
89 !cast<CD8VForm>("CD8VT" # NumElts), ?);
90
Adam Nemet55536c62014-09-25 23:48:45 +000091 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
92 !if (!eq (Size, 256), sub_ymm, ?));
93
94 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
95 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
96 SSEPackedInt));
Adam Nemet09377232014-10-08 23:25:31 +000097
98 // A vector type of the same width with element type i32. This is used to
99 // create the canonical constant zero node ImmAllZerosV.
100 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
101 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
Adam Nemet5ed17da2014-08-21 19:50:07 +0000102}
103
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000104def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
105def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000106def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
107def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000108def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
109def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000110
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000111// "x" in v32i8x_info means RC = VR256X
112def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
113def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
114def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
115def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
Robert Khasanov3e534c92014-10-28 16:37:13 +0000116def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
117def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000118
119def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
120def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
121def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
122def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
Robert Khasanov3e534c92014-10-28 16:37:13 +0000123def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
124def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000125
Elena Demikhovskyfa4a6c12014-12-09 07:06:32 +0000126// We map scalar types to the smallest (128-bit) vector type
127// with the appropriate element type. This allows to use the same masking logic.
Elena Demikhovsky905a5a62014-11-26 10:46:49 +0000128def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
129def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
130
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000131class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
132 X86VectorVTInfo i128> {
133 X86VectorVTInfo info512 = i512;
134 X86VectorVTInfo info256 = i256;
135 X86VectorVTInfo info128 = i128;
136}
137
138def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
139 v16i8x_info>;
140def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
141 v8i16x_info>;
142def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
143 v4i32x_info>;
144def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
145 v2i64x_info>;
Robert Khasanovaf318f72014-10-30 14:21:47 +0000146def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
147 v4f32x_info>;
148def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
149 v2f64x_info>;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000150
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000151// This multiclass generates the masking variants from the non-masking
152// variant. It only provides the assembly pieces for the masking variants.
153// It assumes custom ISel patterns for masking which can be provided as
154// template arguments.
Adam Nemet34801422014-10-08 23:25:39 +0000155multiclass AVX512_maskable_custom<bits<8> O, Format F,
156 dag Outs,
157 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
158 string OpcodeStr,
159 string AttSrcAsm, string IntelSrcAsm,
160 list<dag> Pattern,
161 list<dag> MaskingPattern,
162 list<dag> ZeroMaskingPattern,
Elena Demikhovskybe8808d2014-11-12 07:31:03 +0000163 string Round = "",
Adam Nemet34801422014-10-08 23:25:39 +0000164 string MaskingConstraint = "",
165 InstrItinClass itin = NoItinerary,
166 bit IsCommutable = 0> {
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000167 let isCommutable = IsCommutable in
168 def NAME: AVX512<O, F, Outs, Ins,
Elena Demikhovskybe8808d2014-11-12 07:31:03 +0000169 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
170 "$dst "#Round#", "#IntelSrcAsm#"}",
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000171 Pattern, itin>;
172
173 // Prefer over VMOV*rrk Pat<>
174 let AddedComplexity = 20 in
175 def NAME#k: AVX512<O, F, Outs, MaskingIns,
Elena Demikhovskybe8808d2014-11-12 07:31:03 +0000176 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
177 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000178 MaskingPattern, itin>,
179 EVEX_K {
180 // In case of the 3src subclass this is overridden with a let.
181 string Constraints = MaskingConstraint;
182 }
183 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
184 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
Elena Demikhovskybe8808d2014-11-12 07:31:03 +0000185 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
186 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000187 ZeroMaskingPattern,
188 itin>,
189 EVEX_KZ;
190}
191
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000192
Adam Nemet34801422014-10-08 23:25:39 +0000193// Common base class of AVX512_maskable and AVX512_maskable_3src.
194multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
195 dag Outs,
196 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
197 string OpcodeStr,
198 string AttSrcAsm, string IntelSrcAsm,
199 dag RHS, dag MaskingRHS,
Elena Demikhovsky905a5a62014-11-26 10:46:49 +0000200 SDNode Select = vselect, string Round = "",
Adam Nemet34801422014-10-08 23:25:39 +0000201 string MaskingConstraint = "",
202 InstrItinClass itin = NoItinerary,
203 bit IsCommutable = 0> :
204 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
205 AttSrcAsm, IntelSrcAsm,
206 [(set _.RC:$dst, RHS)],
207 [(set _.RC:$dst, MaskingRHS)],
208 [(set _.RC:$dst,
Elena Demikhovsky905a5a62014-11-26 10:46:49 +0000209 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
Elena Demikhovskybe8808d2014-11-12 07:31:03 +0000210 Round, MaskingConstraint, NoItinerary, IsCommutable>;
Adam Nemet2e2537f2014-08-07 17:53:55 +0000211
Adam Nemet2e91ee52014-08-14 17:13:19 +0000212// This multiclass generates the unconditional/non-masking, the masking and
Elena Demikhovsky905a5a62014-11-26 10:46:49 +0000213// the zero-masking variant of the vector instruction. In the masking case, the
Adam Nemet2e91ee52014-08-14 17:13:19 +0000214// perserved vector elements come from a new dummy input operand tied to $dst.
Adam Nemet34801422014-10-08 23:25:39 +0000215multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
216 dag Outs, dag Ins, string OpcodeStr,
217 string AttSrcAsm, string IntelSrcAsm,
Elena Demikhovskybe8808d2014-11-12 07:31:03 +0000218 dag RHS, string Round = "",
219 InstrItinClass itin = NoItinerary,
Adam Nemet34801422014-10-08 23:25:39 +0000220 bit IsCommutable = 0> :
221 AVX512_maskable_common<O, F, _, Outs, Ins,
222 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
223 !con((ins _.KRCWM:$mask), Ins),
224 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
Elena Demikhovsky905a5a62014-11-26 10:46:49 +0000225 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
226 Round, "$src0 = $dst", itin, IsCommutable>;
227
228// This multiclass generates the unconditional/non-masking, the masking and
229// the zero-masking variant of the scalar instruction.
230multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
231 dag Outs, dag Ins, string OpcodeStr,
232 string AttSrcAsm, string IntelSrcAsm,
233 dag RHS, string Round = "",
234 InstrItinClass itin = NoItinerary,
235 bit IsCommutable = 0> :
236 AVX512_maskable_common<O, F, _, Outs, Ins,
237 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
238 !con((ins _.KRCWM:$mask), Ins),
239 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
240 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
241 Round, "$src0 = $dst", itin, IsCommutable>;
Adam Nemet2e91ee52014-08-14 17:13:19 +0000242
Adam Nemet34801422014-10-08 23:25:39 +0000243// Similar to AVX512_maskable but in this case one of the source operands
Adam Nemet2e91ee52014-08-14 17:13:19 +0000244// ($src1) is already tied to $dst so we just use that for the preserved
245// vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
246// $src1.
Adam Nemet34801422014-10-08 23:25:39 +0000247multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
248 dag Outs, dag NonTiedIns, string OpcodeStr,
249 string AttSrcAsm, string IntelSrcAsm,
250 dag RHS> :
251 AVX512_maskable_common<O, F, _, Outs,
252 !con((ins _.RC:$src1), NonTiedIns),
253 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
254 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
255 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
256 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
Adam Nemet2e91ee52014-08-14 17:13:19 +0000257
Adam Nemet2b5cdbb2014-10-08 23:25:33 +0000258
Adam Nemet34801422014-10-08 23:25:39 +0000259multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
260 dag Outs, dag Ins,
261 string OpcodeStr,
262 string AttSrcAsm, string IntelSrcAsm,
263 list<dag> Pattern> :
264 AVX512_maskable_custom<O, F, Outs, Ins,
265 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
266 !con((ins _.KRCWM:$mask), Ins),
Elena Demikhovskybe8808d2014-11-12 07:31:03 +0000267 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
Adam Nemet34801422014-10-08 23:25:39 +0000268 "$src0 = $dst">;
Adam Nemet2b5cdbb2014-10-08 23:25:33 +0000269
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000270// Bitcasts between 512-bit vector types. Return the original type since
271// no instruction is needed for the conversion
272let Predicates = [HasAVX512] in {
Robert Khasanovbfa01312014-07-21 14:54:21 +0000273 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000274 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000275 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
276 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
277 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000278 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000279 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
280 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
281 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000282 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000283 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000284 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
285 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000286 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000287 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
288 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovsky40a77142014-08-11 09:59:08 +0000289 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000290 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
291 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000292 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000293 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
294 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
295 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
296 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
297 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
298 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
299 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
300 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
301 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
302 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
303 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000304
305 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
306 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
307 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
308 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
309 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
310 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
311 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
312 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
313 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
314 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
315 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
316 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
317 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
318 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
319 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
320 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
321 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
322 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
323 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
324 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
325 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
326 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
327 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
328 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
329 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
330 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
331 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
332 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
333 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
334 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
335
336// Bitcasts between 256-bit vector types. Return the original type since
337// no instruction is needed for the conversion
338 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
339 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
340 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
341 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
342 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
343 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
344 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
345 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
346 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
347 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
348 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
349 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
350 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
351 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
352 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
353 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
354 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
355 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
356 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
357 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
358 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
359 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
360 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
361 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
362 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
363 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
364 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
365 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
366 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
367 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
368}
369
370//
371// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
372//
373
374let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
375 isPseudo = 1, Predicates = [HasAVX512] in {
376def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
377 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
378}
379
Craig Topperfb1746b2014-01-30 06:03:19 +0000380let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000381def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
382def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
383def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
Craig Topperfb1746b2014-01-30 06:03:19 +0000384}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000385
386//===----------------------------------------------------------------------===//
387// AVX-512 - VECTOR INSERT
388//
Adam Nemet4e2ef472014-10-02 23:18:28 +0000389
Adam Nemet4285c1f2014-10-15 23:42:17 +0000390multiclass vinsert_for_size_no_alt<int Opcode,
391 X86VectorVTInfo From, X86VectorVTInfo To,
392 PatFrag vinsert_insert,
393 SDNodeXForm INSERT_get_vinsert_imm> {
Adam Nemet4e2ef472014-10-02 23:18:28 +0000394 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
395 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
396 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
Adam Nemet449b3f02014-10-15 23:42:09 +0000397 "vinsert" # From.EltTypeName # "x" # From.NumElts #
398 "\t{$src3, $src2, $src1, $dst|"
Adam Nemet4e2ef472014-10-02 23:18:28 +0000399 "$dst, $src1, $src2, $src3}",
Adam Nemet4dca3ce2014-10-02 23:18:30 +0000400 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
401 (From.VT From.RC:$src2),
402 (iPTR imm)))]>,
403 EVEX_4V, EVEX_V512;
Adam Nemet4e2ef472014-10-02 23:18:28 +0000404
405 let mayLoad = 1 in
406 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
407 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
Adam Nemet449b3f02014-10-15 23:42:09 +0000408 "vinsert" # From.EltTypeName # "x" # From.NumElts #
409 "\t{$src3, $src2, $src1, $dst|"
Adam Nemet4e2ef472014-10-02 23:18:28 +0000410 "$dst, $src1, $src2, $src3}",
Adam Nemet449b3f02014-10-15 23:42:09 +0000411 []>,
412 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
Adam Nemet4e2ef472014-10-02 23:18:28 +0000413 }
Adam Nemet4285c1f2014-10-15 23:42:17 +0000414}
Adam Nemet4e2ef472014-10-02 23:18:28 +0000415
Adam Nemet4285c1f2014-10-15 23:42:17 +0000416multiclass vinsert_for_size<int Opcode,
417 X86VectorVTInfo From, X86VectorVTInfo To,
418 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
419 PatFrag vinsert_insert,
420 SDNodeXForm INSERT_get_vinsert_imm> :
421 vinsert_for_size_no_alt<Opcode, From, To,
422 vinsert_insert, INSERT_get_vinsert_imm> {
Adam Nemet4e2ef472014-10-02 23:18:28 +0000423 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
Adam Nemet4285c1f2014-10-15 23:42:17 +0000424 // vinserti32x4. Only add this if 64x2 and friends are not supported
425 // natively via AVX512DQ.
426 let Predicates = [NoDQI] in
427 def : Pat<(vinsert_insert:$ins
428 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
429 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
430 VR512:$src1, From.RC:$src2,
431 (INSERT_get_vinsert_imm VR512:$ins)))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000432}
433
Adam Nemetb1c3ef42014-10-15 23:42:04 +0000434multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
435 ValueType EltVT64, int Opcode256> {
436 defm NAME # "32x4" : vinsert_for_size<Opcode128,
Adam Nemet4e2ef472014-10-02 23:18:28 +0000437 X86VectorVTInfo< 4, EltVT32, VR128X>,
438 X86VectorVTInfo<16, EltVT32, VR512>,
439 X86VectorVTInfo< 2, EltVT64, VR128X>,
440 X86VectorVTInfo< 8, EltVT64, VR512>,
441 vinsert128_insert,
442 INSERT_get_vinsert128_imm>;
Adam Nemet4285c1f2014-10-15 23:42:17 +0000443 let Predicates = [HasDQI] in
444 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
445 X86VectorVTInfo< 2, EltVT64, VR128X>,
446 X86VectorVTInfo< 8, EltVT64, VR512>,
447 vinsert128_insert,
448 INSERT_get_vinsert128_imm>, VEX_W;
Adam Nemetb1c3ef42014-10-15 23:42:04 +0000449 defm NAME # "64x4" : vinsert_for_size<Opcode256,
Adam Nemet4e2ef472014-10-02 23:18:28 +0000450 X86VectorVTInfo< 4, EltVT64, VR256X>,
451 X86VectorVTInfo< 8, EltVT64, VR512>,
452 X86VectorVTInfo< 8, EltVT32, VR256>,
453 X86VectorVTInfo<16, EltVT32, VR512>,
454 vinsert256_insert,
455 INSERT_get_vinsert256_imm>, VEX_W;
Adam Nemet4285c1f2014-10-15 23:42:17 +0000456 let Predicates = [HasDQI] in
457 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
458 X86VectorVTInfo< 8, EltVT32, VR256X>,
459 X86VectorVTInfo<16, EltVT32, VR512>,
460 vinsert256_insert,
461 INSERT_get_vinsert256_imm>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000462}
463
Adam Nemet4e2ef472014-10-02 23:18:28 +0000464defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
465defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000466
467// vinsertps - insert f32 to XMM
468def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000469 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000470 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000471 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000472 EVEX_4V;
473def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000474 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000475 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000476 [(set VR128X:$dst, (X86insertps VR128X:$src1,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000477 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
478 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
479
480//===----------------------------------------------------------------------===//
481// AVX-512 VECTOR EXTRACT
482//---
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000483
Adam Nemet55536c62014-09-25 23:48:45 +0000484multiclass vextract_for_size<int Opcode,
485 X86VectorVTInfo From, X86VectorVTInfo To,
486 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
487 PatFrag vextract_extract,
488 SDNodeXForm EXTRACT_get_vextract_imm> {
489 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
Adam Nemet34801422014-10-08 23:25:39 +0000490 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
Adam Nemet2b5cdbb2014-10-08 23:25:33 +0000491 (ins VR512:$src1, i8imm:$idx),
492 "vextract" # To.EltTypeName # "x4",
493 "$idx, $src1", "$src1, $idx",
494 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
495 (iPTR imm)))]>,
496 AVX512AIi8Base, EVEX, EVEX_V512;
Adam Nemet55536c62014-09-25 23:48:45 +0000497 let mayStore = 1 in
498 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
499 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
500 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
501 "$dst, $src1, $src2}",
502 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
503 }
504
Adam Nemet55536c62014-09-25 23:48:45 +0000505 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
506 // vextracti32x4
507 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
508 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
509 VR512:$src1,
510 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
511
512 // A 128/256-bit subvector extract from the first 512-bit vector position is
513 // a subregister copy that needs no instruction.
514 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
515 (To.VT
516 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
517
518 // And for the alternative types.
519 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
520 (AltTo.VT
521 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
Adam Nemet47b2d5f2014-10-08 23:25:37 +0000522
523 // Intrinsic call with masking.
524 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
525 "x4_512")
526 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
527 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
528 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
529 VR512:$src1, imm:$idx)>;
530
531 // Intrinsic call with zero-masking.
532 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
533 "x4_512")
534 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
535 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
536 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
537 VR512:$src1, imm:$idx)>;
538
539 // Intrinsic call without masking.
540 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
541 "x4_512")
542 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
543 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
544 VR512:$src1, imm:$idx)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000545}
546
Adam Nemet55536c62014-09-25 23:48:45 +0000547multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
548 ValueType EltVT64, int Opcode64> {
549 defm NAME # "32x4" : vextract_for_size<Opcode32,
550 X86VectorVTInfo<16, EltVT32, VR512>,
551 X86VectorVTInfo< 4, EltVT32, VR128X>,
552 X86VectorVTInfo< 8, EltVT64, VR512>,
553 X86VectorVTInfo< 2, EltVT64, VR128X>,
554 vextract128_extract,
555 EXTRACT_get_vextract128_imm>;
556 defm NAME # "64x4" : vextract_for_size<Opcode64,
557 X86VectorVTInfo< 8, EltVT64, VR512>,
558 X86VectorVTInfo< 4, EltVT64, VR256X>,
559 X86VectorVTInfo<16, EltVT32, VR512>,
560 X86VectorVTInfo< 8, EltVT32, VR256>,
561 vextract256_extract,
562 EXTRACT_get_vextract256_imm>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000563}
564
Adam Nemet55536c62014-09-25 23:48:45 +0000565defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
566defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000567
568// A 128-bit subvector insert to the first 512-bit vector position
569// is a subregister copy that needs no instruction.
570def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
571 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
572 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
573 sub_ymm)>;
574def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
575 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
576 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
577 sub_ymm)>;
578def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
579 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
580 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
581 sub_ymm)>;
582def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
583 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
584 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
585 sub_ymm)>;
586
587def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
588 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
589def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
590 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
591def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
592 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
593def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
594 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
595
596// vextractps - extract 32 bits from XMM
597def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000598 (ins VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000599 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000600 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
601 EVEX;
602
603def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000604 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000605 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000606 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
Elena Demikhovsky2aafc222014-02-11 07:25:59 +0000607 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000608
609//===---------------------------------------------------------------------===//
610// AVX-512 BROADCAST
611//---
Robert Khasanovaf318f72014-10-30 14:21:47 +0000612multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
613 ValueType svt, X86VectorVTInfo _> {
614 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
615 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
616 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
617 T8PD, EVEX;
618
619 let mayLoad = 1 in {
620 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
621 (ins _.ScalarMemOp:$src),
622 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
623 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
624 T8PD, EVEX;
625 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000626}
Robert Khasanovaf318f72014-10-30 14:21:47 +0000627
628multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
629 AVX512VLVectorVTInfo _> {
630 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
631 EVEX_V512;
632
633 let Predicates = [HasVLX] in {
634 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
635 EVEX_V256;
636 }
637}
638
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000639let ExeDomain = SSEPackedSingle in {
Robert Khasanovaf318f72014-10-30 14:21:47 +0000640 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
641 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
642 let Predicates = [HasVLX] in {
643 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
644 v4f32, v4f32x_info>, EVEX_V128,
645 EVEX_CD8<32, CD8VT1>;
646 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000647}
648
649let ExeDomain = SSEPackedDouble in {
Robert Khasanovaf318f72014-10-30 14:21:47 +0000650 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
651 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000652}
653
654def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000655 (VBROADCASTSSZm addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000656def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000657 (VBROADCASTSDZm addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000658
Quentin Colombet4bf1c282013-10-25 17:47:18 +0000659def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000660 (VBROADCASTSSZm addr:$src)>;
Quentin Colombet4bf1c282013-10-25 17:47:18 +0000661def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000662 (VBROADCASTSDZm addr:$src)>;
Quentin Colombet4bf1c282013-10-25 17:47:18 +0000663
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000664multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
665 RegisterClass SrcRC, RegisterClass KRC> {
666 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +0000667 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000668 []>, EVEX, EVEX_V512;
Michael Liao5bf95782014-12-04 05:20:33 +0000669 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000670 (ins KRC:$mask, SrcRC:$src),
Michael Liao5bf95782014-12-04 05:20:33 +0000671 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +0000672 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000673 []>, EVEX, EVEX_V512, EVEX_KZ;
674}
675
676defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
677defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
678 VEX_W;
Michael Liao5bf95782014-12-04 05:20:33 +0000679
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000680def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
681 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
682
683def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
684 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
685
686def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
687 (VPBROADCASTDrZrr GR32:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +0000688def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
689 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000690def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
691 (VPBROADCASTQrZrr GR64:$src)>;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000692def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
693 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000694
Cameron McInally394d5572013-10-31 13:56:31 +0000695def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
696 (VPBROADCASTDrZrr GR32:$src)>;
697def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
698 (VPBROADCASTQrZrr GR64:$src)>;
699
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000700def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
701 (v16i32 immAllZerosV), (i16 GR16:$mask))),
702 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
703def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
704 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
705 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
706
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000707multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
708 X86MemOperand x86memop, PatFrag ld_frag,
709 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
710 RegisterClass KRC> {
711 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
Craig Topperedb09112014-11-25 20:11:23 +0000712 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000713 [(set DstRC:$dst,
714 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
715 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
716 VR128X:$src),
Michael Liao5bf95782014-12-04 05:20:33 +0000717 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +0000718 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000719 [(set DstRC:$dst,
720 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
721 EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000722 let mayLoad = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000723 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Craig Topperedb09112014-11-25 20:11:23 +0000724 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
Michael Liao5bf95782014-12-04 05:20:33 +0000725 [(set DstRC:$dst,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000726 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
727 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
728 x86memop:$src),
Michael Liao5bf95782014-12-04 05:20:33 +0000729 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +0000730 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Michael Liao5bf95782014-12-04 05:20:33 +0000731 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000732 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000733 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000734}
735
736defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
737 loadi32, VR512, v16i32, v4i32, VK16WM>,
738 EVEX_V512, EVEX_CD8<32, CD8VT1>;
739defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
740 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
741 EVEX_CD8<64, CD8VT1>;
742
Adam Nemet73f72e12014-06-27 00:43:38 +0000743multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
744 X86MemOperand x86memop, PatFrag ld_frag,
745 RegisterClass KRC> {
746 let mayLoad = 1 in {
747 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
Craig Topperedb09112014-11-25 20:11:23 +0000748 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
Adam Nemet73f72e12014-06-27 00:43:38 +0000749 []>, EVEX;
750 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
751 x86memop:$src),
752 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +0000753 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Adam Nemet73f72e12014-06-27 00:43:38 +0000754 []>, EVEX, EVEX_KZ;
755 }
756}
757
758defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
759 i128mem, loadv2i64, VK16WM>,
760 EVEX_V512, EVEX_CD8<32, CD8VT4>;
761defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
762 i256mem, loadv4i64, VK16WM>, VEX_W,
763 EVEX_V512, EVEX_CD8<64, CD8VT4>;
764
Cameron McInally394d5572013-10-31 13:56:31 +0000765def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
766 (VPBROADCASTDZrr VR128X:$src)>;
767def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
768 (VPBROADCASTQZrr VR128X:$src)>;
769
Robert Khasanovdd09a8f2014-10-28 12:28:51 +0000770def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000771 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
Robert Khasanovdd09a8f2014-10-28 12:28:51 +0000772def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000773 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
Robert Khasanovdd09a8f2014-10-28 12:28:51 +0000774
775def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
776 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
777def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
778 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
779
Quentin Colombet8761a8f2013-10-25 18:04:12 +0000780def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000781 (VBROADCASTSSZr VR128X:$src)>;
Quentin Colombet8761a8f2013-10-25 18:04:12 +0000782def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000783 (VBROADCASTSDZr VR128X:$src)>;
Michael Liao5bf95782014-12-04 05:20:33 +0000784
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000785// Provide fallback in case the load node that is used in the patterns above
786// is used by additional users, which prevents the pattern selection.
787def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000788 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000789def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
Robert Khasanovaf318f72014-10-30 14:21:47 +0000790 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000791
792
793let Predicates = [HasAVX512] in {
794def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
Michael Liao5bf95782014-12-04 05:20:33 +0000795 (EXTRACT_SUBREG
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000796 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
797 addr:$src)), sub_ymm)>;
798}
799//===----------------------------------------------------------------------===//
800// AVX-512 BROADCAST MASK TO VECTOR REGISTER
801//---
802
803multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
Elena Demikhovsky4b01b732014-10-26 09:52:24 +0000804 RegisterClass KRC> {
805let Predicates = [HasCDI] in
806def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +0000807 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
Elena Demikhovsky4b01b732014-10-26 09:52:24 +0000808 []>, EVEX, EVEX_V512;
Michael Liao5bf95782014-12-04 05:20:33 +0000809
Elena Demikhovsky4b01b732014-10-26 09:52:24 +0000810let Predicates = [HasCDI, HasVLX] in {
811def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +0000812 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
Elena Demikhovsky4b01b732014-10-26 09:52:24 +0000813 []>, EVEX, EVEX_V128;
814def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +0000815 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
Elena Demikhovsky4b01b732014-10-26 09:52:24 +0000816 []>, EVEX, EVEX_V256;
817}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000818}
819
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000820let Predicates = [HasCDI] in {
Elena Demikhovsky4b01b732014-10-26 09:52:24 +0000821defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
822 VK16>;
823defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
824 VK8>, VEX_W;
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000825}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000826
827//===----------------------------------------------------------------------===//
828// AVX-512 - VPERM
829//
830// -- immediate form --
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000831multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
832 X86VectorVTInfo _> {
833 let ExeDomain = _.ExeDomain in {
834 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
835 (ins _.RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000836 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +0000837 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000838 [(set _.RC:$dst,
839 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000840 EVEX;
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000841 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
842 (ins _.MemOp:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000843 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +0000844 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000845 [(set _.RC:$dst,
846 (_.VT (OpNode (_.MemOpFrag addr:$src1),
847 (i8 imm:$src2))))]>,
848 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
849}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000850}
851
Adam Nemetcf7a4a22014-10-27 23:08:40 +0000852multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
853 X86VectorVTInfo Ctrl> :
854 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
855 let ExeDomain = _.ExeDomain in {
856 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
857 (ins _.RC:$src1, _.RC:$src2),
858 !strconcat("vpermil" # _.Suffix,
Craig Topperedb09112014-11-25 20:11:23 +0000859 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Adam Nemetcf7a4a22014-10-27 23:08:40 +0000860 [(set _.RC:$dst,
861 (_.VT (X86VPermilpv _.RC:$src1,
862 (Ctrl.VT Ctrl.RC:$src2))))]>,
863 EVEX_4V;
864 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
865 (ins _.RC:$src1, Ctrl.MemOp:$src2),
866 !strconcat("vpermil" # _.Suffix,
Craig Topperedb09112014-11-25 20:11:23 +0000867 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Adam Nemetcf7a4a22014-10-27 23:08:40 +0000868 [(set _.RC:$dst,
869 (_.VT (X86VPermilpv _.RC:$src1,
870 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>,
871 EVEX_4V;
872 }
873}
874
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000875defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
876 EVEX_V512, VEX_W;
877defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
878 EVEX_V512, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000879
Adam Nemetcf7a4a22014-10-27 23:08:40 +0000880defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000881 EVEX_V512;
Adam Nemetcf7a4a22014-10-27 23:08:40 +0000882defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000883 EVEX_V512, VEX_W;
Adam Nemet9aad1312014-10-27 23:08:34 +0000884
885def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
886 (VPERMILPSZri VR512:$src1, imm:$imm)>;
887def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
888 (VPERMILPDZri VR512:$src1, imm:$imm)>;
889
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000890// -- VPERM - register form --
Michael Liao5bf95782014-12-04 05:20:33 +0000891multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000892 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
893
894 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
895 (ins RC:$src1, RC:$src2),
896 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +0000897 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000898 [(set RC:$dst,
899 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
900
901 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
902 (ins RC:$src1, x86memop:$src2),
903 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +0000904 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000905 [(set RC:$dst,
906 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
907 EVEX_4V;
908}
909
910defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
911 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
Michael Liao5bf95782014-12-04 05:20:33 +0000912defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000913 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
914let ExeDomain = SSEPackedSingle in
915defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
916 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
917let ExeDomain = SSEPackedDouble in
Michael Liao5bf95782014-12-04 05:20:33 +0000918defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000919 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
920
921// -- VPERM2I - 3 source operands form --
922multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
923 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet2415a492014-07-02 21:25:54 +0000924 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000925let Constraints = "$src1 = $dst" in {
926 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
927 (ins RC:$src1, RC:$src2, RC:$src3),
928 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +0000929 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000930 [(set RC:$dst,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000931 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000932 EVEX_4V;
933
Adam Nemet2415a492014-07-02 21:25:54 +0000934 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
935 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
936 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +0000937 "\t{$src3, $src2, $dst {${mask}}|"
Adam Nemet2415a492014-07-02 21:25:54 +0000938 "$dst {${mask}}, $src2, $src3}"),
939 [(set RC:$dst, (OpVT (vselect KRC:$mask,
940 (OpNode RC:$src1, RC:$src2,
941 RC:$src3),
942 RC:$src1)))]>,
943 EVEX_4V, EVEX_K;
944
945 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
946 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
947 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
948 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +0000949 "\t{$src3, $src2, $dst {${mask}} {z} |",
Adam Nemet2415a492014-07-02 21:25:54 +0000950 "$dst {${mask}} {z}, $src2, $src3}"),
951 [(set RC:$dst, (OpVT (vselect KRC:$mask,
952 (OpNode RC:$src1, RC:$src2,
953 RC:$src3),
954 (OpVT (bitconvert
955 (v16i32 immAllZerosV))))))]>,
956 EVEX_4V, EVEX_KZ;
957
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000958 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
959 (ins RC:$src1, RC:$src2, x86memop:$src3),
960 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +0000961 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000962 [(set RC:$dst,
Adam Nemet2415a492014-07-02 21:25:54 +0000963 (OpVT (OpNode RC:$src1, RC:$src2,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000964 (mem_frag addr:$src3))))]>, EVEX_4V;
Adam Nemet2415a492014-07-02 21:25:54 +0000965
966 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
967 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
968 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +0000969 "\t{$src3, $src2, $dst {${mask}}|"
Adam Nemet2415a492014-07-02 21:25:54 +0000970 "$dst {${mask}}, $src2, $src3}"),
971 [(set RC:$dst,
972 (OpVT (vselect KRC:$mask,
973 (OpNode RC:$src1, RC:$src2,
974 (mem_frag addr:$src3)),
975 RC:$src1)))]>,
976 EVEX_4V, EVEX_K;
977
978 let AddedComplexity = 10 in // Prefer over the rrkz variant
979 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
980 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
981 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +0000982 "\t{$src3, $src2, $dst {${mask}} {z}|"
Adam Nemet2415a492014-07-02 21:25:54 +0000983 "$dst {${mask}} {z}, $src2, $src3}"),
984 [(set RC:$dst,
985 (OpVT (vselect KRC:$mask,
986 (OpNode RC:$src1, RC:$src2,
987 (mem_frag addr:$src3)),
988 (OpVT (bitconvert
989 (v16i32 immAllZerosV))))))]>,
990 EVEX_4V, EVEX_KZ;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000991 }
992}
Adam Nemet2415a492014-07-02 21:25:54 +0000993defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
994 i512mem, X86VPermiv3, v16i32, VK16WM>,
995 EVEX_V512, EVEX_CD8<32, CD8VF>;
996defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
997 i512mem, X86VPermiv3, v8i64, VK8WM>,
998 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
999defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
1000 i512mem, X86VPermiv3, v16f32, VK16WM>,
1001 EVEX_V512, EVEX_CD8<32, CD8VF>;
1002defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
1003 i512mem, X86VPermiv3, v8f64, VK8WM>,
1004 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001005
Adam Nemetefe9c982014-07-02 21:25:58 +00001006multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1007 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet11dd5cf2014-07-02 21:26:01 +00001008 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1009 ValueType MaskVT, RegisterClass MRC> :
Adam Nemetefe9c982014-07-02 21:25:58 +00001010 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1011 OpVT, KRC> {
1012 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1013 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1014 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
Adam Nemet11dd5cf2014-07-02 21:26:01 +00001015
1016 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1017 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1018 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1019 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
Adam Nemetefe9c982014-07-02 21:25:58 +00001020}
1021
1022defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +00001023 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1024 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +00001025defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +00001026 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1027 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +00001028defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +00001029 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1030 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +00001031defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +00001032 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1033 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky299cf5112014-04-29 09:09:15 +00001034
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001035//===----------------------------------------------------------------------===//
1036// AVX-512 - BLEND using mask
1037//
Elena Demikhovsky172a27c2014-01-08 10:54:22 +00001038multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001039 RegisterClass KRC, RegisterClass RC,
1040 X86MemOperand x86memop, PatFrag mem_frag,
1041 SDNode OpNode, ValueType vt> {
1042 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +00001043 (ins KRC:$mask, RC:$src1, RC:$src2),
1044 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00001045 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +00001046 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001047 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +00001048 let mayLoad = 1 in
1049 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1050 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1051 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00001052 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +00001053 []>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001054}
1055
1056let ExeDomain = SSEPackedSingle in
Michael Liao5bf95782014-12-04 05:20:33 +00001057defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
Cameron McInallyd80f7d32013-11-04 19:14:56 +00001058 VK16WM, VR512, f512mem,
Michael Liao5bf95782014-12-04 05:20:33 +00001059 memopv16f32, vselect, v16f32>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001060 EVEX_CD8<32, CD8VF>, EVEX_V512;
1061let ExeDomain = SSEPackedDouble in
Michael Liao5bf95782014-12-04 05:20:33 +00001062defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
Cameron McInallyd80f7d32013-11-04 19:14:56 +00001063 VK8WM, VR512, f512mem,
Michael Liao5bf95782014-12-04 05:20:33 +00001064 memopv8f64, vselect, v8f64>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001065 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1066
Elena Demikhovsky172a27c2014-01-08 10:54:22 +00001067def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
1068 (v16f32 VR512:$src2), (i16 GR16:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00001069 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +00001070 VR512:$src1, VR512:$src2)>;
1071
1072def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
1073 (v8f64 VR512:$src2), (i8 GR8:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00001074 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +00001075 VR512:$src1, VR512:$src2)>;
1076
Michael Liao5bf95782014-12-04 05:20:33 +00001077defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
1078 VK16WM, VR512, f512mem,
1079 memopv16i32, vselect, v16i32>,
Cameron McInallyd80f7d32013-11-04 19:14:56 +00001080 EVEX_CD8<32, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001081
Michael Liao5bf95782014-12-04 05:20:33 +00001082defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
1083 VK8WM, VR512, f512mem,
1084 memopv8i64, vselect, v8i64>,
Cameron McInallyd80f7d32013-11-04 19:14:56 +00001085 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001086
Elena Demikhovsky172a27c2014-01-08 10:54:22 +00001087def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
1088 (v16i32 VR512:$src2), (i16 GR16:$mask))),
1089 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
1090 VR512:$src1, VR512:$src2)>;
1091
1092def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
1093 (v8i64 VR512:$src2), (i8 GR8:$mask))),
1094 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
1095 VR512:$src1, VR512:$src2)>;
1096
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001097let Predicates = [HasAVX512] in {
1098def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1099 (v8f32 VR256X:$src2))),
Michael Liao5bf95782014-12-04 05:20:33 +00001100 (EXTRACT_SUBREG
1101 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001102 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1103 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1104
1105def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1106 (v8i32 VR256X:$src2))),
Michael Liao5bf95782014-12-04 05:20:33 +00001107 (EXTRACT_SUBREG
1108 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001109 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1110 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1111}
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +00001112//===----------------------------------------------------------------------===//
1113// Compare Instructions
1114//===----------------------------------------------------------------------===//
1115
1116// avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1117multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1118 Operand CC, SDNode OpNode, ValueType VT,
1119 PatFrag ld_frag, string asm, string asm_alt> {
1120 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1121 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
1122 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1123 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1124 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1125 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
1126 [(set VK1:$dst, (OpNode (VT RC:$src1),
1127 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Craig Topper0550ce72014-01-05 04:55:55 +00001128 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +00001129 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1130 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1131 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1132 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1133 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1134 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1135 }
1136}
1137
1138let Predicates = [HasAVX512] in {
1139defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1140 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1141 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1142 XS;
1143defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1144 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1145 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1146 XD, VEX_W;
1147}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001148
Robert Khasanov2ea081d2014-08-25 14:49:34 +00001149multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1150 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001151 def rr : AVX512BI<opc, MRMSrcReg,
Robert Khasanov2ea081d2014-08-25 14:49:34 +00001152 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1153 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1154 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001155 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +00001156 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001157 def rm : AVX512BI<opc, MRMSrcMem,
Robert Khasanov2ea081d2014-08-25 14:49:34 +00001158 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1159 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1160 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1161 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001162 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +00001163 def rrk : AVX512BI<opc, MRMSrcReg,
1164 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1165 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1166 "$dst {${mask}}, $src1, $src2}"),
1167 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1168 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1169 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1170 let mayLoad = 1 in
1171 def rmk : AVX512BI<opc, MRMSrcMem,
1172 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1173 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1174 "$dst {${mask}}, $src1, $src2}"),
1175 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1176 (OpNode (_.VT _.RC:$src1),
1177 (_.VT (bitconvert
1178 (_.LdFrag addr:$src2))))))],
1179 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001180}
1181
Robert Khasanov2ea081d2014-08-25 14:49:34 +00001182multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +00001183 X86VectorVTInfo _> :
1184 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
Robert Khasanov2ea081d2014-08-25 14:49:34 +00001185 let mayLoad = 1 in {
1186 def rmb : AVX512BI<opc, MRMSrcMem,
1187 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1188 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1189 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1190 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1191 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1192 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1193 def rmbk : AVX512BI<opc, MRMSrcMem,
1194 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1195 _.ScalarMemOp:$src2),
1196 !strconcat(OpcodeStr,
1197 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1198 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1199 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1200 (OpNode (_.VT _.RC:$src1),
1201 (X86VBroadcast
1202 (_.ScalarLdFrag addr:$src2)))))],
1203 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1204 }
1205}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001206
Robert Khasanov2ea081d2014-08-25 14:49:34 +00001207multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1208 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1209 let Predicates = [prd] in
1210 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1211 EVEX_V512;
1212
1213 let Predicates = [prd, HasVLX] in {
1214 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1215 EVEX_V256;
1216 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1217 EVEX_V128;
1218 }
1219}
1220
1221multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1222 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1223 Predicate prd> {
1224 let Predicates = [prd] in
1225 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1226 EVEX_V512;
1227
1228 let Predicates = [prd, HasVLX] in {
1229 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1230 EVEX_V256;
1231 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1232 EVEX_V128;
1233 }
1234}
1235
1236defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1237 avx512vl_i8_info, HasBWI>,
1238 EVEX_CD8<8, CD8VF>;
1239
1240defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1241 avx512vl_i16_info, HasBWI>,
1242 EVEX_CD8<16, CD8VF>;
1243
Robert Khasanovf70f7982014-09-18 14:06:55 +00001244defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +00001245 avx512vl_i32_info, HasAVX512>,
1246 EVEX_CD8<32, CD8VF>;
1247
Robert Khasanovf70f7982014-09-18 14:06:55 +00001248defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +00001249 avx512vl_i64_info, HasAVX512>,
1250 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1251
1252defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1253 avx512vl_i8_info, HasBWI>,
1254 EVEX_CD8<8, CD8VF>;
1255
1256defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1257 avx512vl_i16_info, HasBWI>,
1258 EVEX_CD8<16, CD8VF>;
1259
Robert Khasanovf70f7982014-09-18 14:06:55 +00001260defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +00001261 avx512vl_i32_info, HasAVX512>,
1262 EVEX_CD8<32, CD8VF>;
1263
Robert Khasanovf70f7982014-09-18 14:06:55 +00001264defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +00001265 avx512vl_i64_info, HasAVX512>,
1266 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001267
1268def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +00001269 (COPY_TO_REGCLASS (VPCMPGTDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001270 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1271 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1272
1273def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +00001274 (COPY_TO_REGCLASS (VPCMPEQDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001275 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1276 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1277
Robert Khasanov29e3b962014-08-27 09:34:37 +00001278multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1279 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001280 def rri : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +00001281 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +00001282 !strconcat("vpcmp${cc}", Suffix,
1283 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +00001284 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1285 imm:$cc))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001286 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +00001287 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001288 def rmi : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +00001289 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +00001290 !strconcat("vpcmp${cc}", Suffix,
1291 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +00001292 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1293 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1294 imm:$cc))],
1295 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1296 def rrik : AVX512AIi8<opc, MRMSrcReg,
1297 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1298 AVXCC:$cc),
1299 !strconcat("vpcmp${cc}", Suffix,
1300 "\t{$src2, $src1, $dst {${mask}}|",
1301 "$dst {${mask}}, $src1, $src2}"),
1302 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1303 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1304 imm:$cc)))],
1305 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1306 let mayLoad = 1 in
1307 def rmik : AVX512AIi8<opc, MRMSrcMem,
1308 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1309 AVXCC:$cc),
1310 !strconcat("vpcmp${cc}", Suffix,
1311 "\t{$src2, $src1, $dst {${mask}}|",
1312 "$dst {${mask}}, $src1, $src2}"),
1313 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1314 (OpNode (_.VT _.RC:$src1),
1315 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1316 imm:$cc)))],
1317 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1318
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001319 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +00001320 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001321 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +00001322 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1323 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1324 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +00001325 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001326 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +00001327 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1328 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1329 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +00001330 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +00001331 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1332 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1333 i8imm:$cc),
Adam Nemet16de2482014-07-01 18:03:45 +00001334 !strconcat("vpcmp", Suffix,
Robert Khasanov29e3b962014-08-27 09:34:37 +00001335 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1336 "$dst {${mask}}, $src1, $src2, $cc}"),
1337 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1338 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1339 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1340 i8imm:$cc),
1341 !strconcat("vpcmp", Suffix,
1342 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1343 "$dst {${mask}}, $src1, $src2, $cc}"),
Adam Nemet16de2482014-07-01 18:03:45 +00001344 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001345 }
1346}
1347
Robert Khasanov29e3b962014-08-27 09:34:37 +00001348multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +00001349 X86VectorVTInfo _> :
1350 avx512_icmp_cc<opc, Suffix, OpNode, _> {
Robert Khasanov29e3b962014-08-27 09:34:37 +00001351 let mayLoad = 1 in {
1352 def rmib : AVX512AIi8<opc, MRMSrcMem,
1353 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1354 AVXCC:$cc),
1355 !strconcat("vpcmp${cc}", Suffix,
1356 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1357 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1358 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1359 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1360 imm:$cc))],
1361 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1362 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1363 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1364 _.ScalarMemOp:$src2, AVXCC:$cc),
1365 !strconcat("vpcmp${cc}", Suffix,
1366 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1367 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1368 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1369 (OpNode (_.VT _.RC:$src1),
1370 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1371 imm:$cc)))],
1372 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1373 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001374
Robert Khasanov29e3b962014-08-27 09:34:37 +00001375 // Accept explicit immediate argument form instead of comparison code.
1376 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1377 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1378 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1379 i8imm:$cc),
1380 !strconcat("vpcmp", Suffix,
1381 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1382 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1383 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1384 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1385 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1386 _.ScalarMemOp:$src2, i8imm:$cc),
1387 !strconcat("vpcmp", Suffix,
1388 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1389 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1390 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1391 }
1392}
1393
1394multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1395 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1396 let Predicates = [prd] in
1397 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1398
1399 let Predicates = [prd, HasVLX] in {
1400 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1401 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1402 }
1403}
1404
1405multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1406 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1407 let Predicates = [prd] in
1408 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1409 EVEX_V512;
1410
1411 let Predicates = [prd, HasVLX] in {
1412 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1413 EVEX_V256;
1414 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1415 EVEX_V128;
1416 }
1417}
1418
1419defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1420 HasBWI>, EVEX_CD8<8, CD8VF>;
1421defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1422 HasBWI>, EVEX_CD8<8, CD8VF>;
1423
1424defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1425 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1426defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1427 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1428
Robert Khasanovf70f7982014-09-18 14:06:55 +00001429defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +00001430 HasAVX512>, EVEX_CD8<32, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +00001431defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +00001432 HasAVX512>, EVEX_CD8<32, CD8VF>;
1433
Robert Khasanovf70f7982014-09-18 14:06:55 +00001434defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +00001435 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +00001436defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +00001437 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001438
Adam Nemet905832b2014-06-26 00:21:12 +00001439// avx512_cmp_packed - compare packed instructions
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001440multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00001441 X86MemOperand x86memop, ValueType vt,
1442 string suffix, Domain d> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001443 def rri : AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00001444 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1445 !strconcat("vcmp${cc}", suffix,
Craig Topperedb09112014-11-25 20:11:23 +00001446 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00001447 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1448 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00001449 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00001450 !strconcat("vcmp${cc}", suffix,
Craig Topperedb09112014-11-25 20:11:23 +00001451 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00001452 [], d>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001453 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00001454 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +00001455 !strconcat("vcmp${cc}", suffix,
Craig Topperedb09112014-11-25 20:11:23 +00001456 "\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001457 [(set KRC:$dst,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00001458 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001459
1460 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +00001461 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Craig Toppera328ee42013-10-09 04:24:38 +00001462 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
Adam Nemet905832b2014-06-26 00:21:12 +00001463 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00001464 !strconcat("vcmp", suffix,
Craig Topperedb09112014-11-25 20:11:23 +00001465 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Craig Toppera328ee42013-10-09 04:24:38 +00001466 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
Adam Nemet905832b2014-06-26 00:21:12 +00001467 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00001468 !strconcat("vcmp", suffix,
Craig Topperedb09112014-11-25 20:11:23 +00001469 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001470 }
1471}
1472
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00001473defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +00001474 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
Craig Topperda7160d2014-02-01 08:17:56 +00001475 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00001476defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +00001477 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001478 EVEX_CD8<64, CD8VF>;
1479
1480def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1481 (COPY_TO_REGCLASS (VCMPPSZrri
1482 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1483 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1484 imm:$cc), VK8)>;
1485def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1486 (COPY_TO_REGCLASS (VPCMPDZrri
1487 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1488 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1489 imm:$cc), VK8)>;
1490def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1491 (COPY_TO_REGCLASS (VPCMPUDZrri
1492 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1493 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1494 imm:$cc), VK8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00001495
1496def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1497 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1498 FROUND_NO_EXC)),
1499 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00001500 (I8Imm imm:$cc)), GR16)>;
Michael Liao5bf95782014-12-04 05:20:33 +00001501
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00001502def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1503 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1504 FROUND_NO_EXC)),
1505 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00001506 (I8Imm imm:$cc)), GR8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00001507
1508def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1509 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1510 FROUND_CURRENT)),
1511 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1512 (I8Imm imm:$cc)), GR16)>;
1513
1514def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1515 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1516 FROUND_CURRENT)),
1517 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1518 (I8Imm imm:$cc)), GR8)>;
1519
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001520// Mask register copy, including
1521// - copy between mask registers
1522// - load/store mask registers
1523// - copy from GPR to mask register and vice versa
1524//
1525multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1526 string OpcodeStr, RegisterClass KRC,
Robert Khasanov74acbb72014-07-23 14:49:42 +00001527 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +00001528 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001529 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00001530 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001531 let mayLoad = 1 in
1532 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00001533 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
Robert Khasanov74acbb72014-07-23 14:49:42 +00001534 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001535 let mayStore = 1 in
1536 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00001537 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001538 }
1539}
1540
1541multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1542 string OpcodeStr,
1543 RegisterClass KRC, RegisterClass GRC> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +00001544 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001545 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00001546 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001547 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00001548 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001549 }
1550}
1551
Robert Khasanov74acbb72014-07-23 14:49:42 +00001552let Predicates = [HasDQI] in
1553 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1554 i8mem>,
1555 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1556 VEX, PD;
1557
1558let Predicates = [HasAVX512] in
1559 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1560 i16mem>,
1561 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
Craig Topper5ccb6172014-02-18 00:21:49 +00001562 VEX, PS;
Robert Khasanov74acbb72014-07-23 14:49:42 +00001563
1564let Predicates = [HasBWI] in {
1565 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1566 i32mem>, VEX, PD, VEX_W;
1567 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1568 VEX, XD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001569}
1570
Robert Khasanov74acbb72014-07-23 14:49:42 +00001571let Predicates = [HasBWI] in {
1572 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1573 i64mem>, VEX, PS, VEX_W;
1574 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1575 VEX, XD, VEX_W;
1576}
1577
1578// GR from/to mask register
1579let Predicates = [HasDQI] in {
1580 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1581 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1582 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1583 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1584}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001585let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001586 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1587 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1588 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1589 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +00001590}
1591let Predicates = [HasBWI] in {
1592 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1593 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1594}
1595let Predicates = [HasBWI] in {
1596 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1597 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1598}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001599
Robert Khasanov74acbb72014-07-23 14:49:42 +00001600// Load/store kreg
1601let Predicates = [HasDQI] in {
1602 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1603 (KMOVBmk addr:$dst, VK8:$src)>;
1604}
1605let Predicates = [HasAVX512] in {
1606 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001607 (KMOVWmk addr:$dst, VK16:$src)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +00001608 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +00001609 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +00001610 def : Pat<(i1 (load addr:$src)),
1611 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +00001612 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +00001613 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +00001614}
1615let Predicates = [HasBWI] in {
1616 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1617 (KMOVDmk addr:$dst, VK32:$src)>;
1618}
1619let Predicates = [HasBWI] in {
1620 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1621 (KMOVQmk addr:$dst, VK64:$src)>;
1622}
Elena Demikhovskyc5f67262013-12-17 08:33:15 +00001623
Robert Khasanov74acbb72014-07-23 14:49:42 +00001624let Predicates = [HasAVX512] in {
Elena Demikhovsky34d2d762014-08-18 11:59:06 +00001625 def : Pat<(i1 (trunc (i64 GR64:$src))),
1626 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1627 (i32 1))), VK1)>;
1628
Elena Demikhovsky64c95482013-12-24 14:24:07 +00001629 def : Pat<(i1 (trunc (i32 GR32:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +00001630 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +00001631
1632 def : Pat<(i1 (trunc (i8 GR8:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +00001633 (COPY_TO_REGCLASS
1634 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1635 VK1)>;
1636 def : Pat<(i1 (trunc (i16 GR16:$src))),
1637 (COPY_TO_REGCLASS
1638 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1639 VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +00001640
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +00001641 def : Pat<(i32 (zext VK1:$src)),
1642 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +00001643 def : Pat<(i8 (zext VK1:$src)),
1644 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +00001645 (AND32ri (KMOVWrk
1646 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00001647 def : Pat<(i64 (zext VK1:$src)),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +00001648 (AND64ri8 (SUBREG_TO_REG (i64 0),
1649 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
Elena Demikhovsky750498c2014-02-17 07:29:33 +00001650 def : Pat<(i16 (zext VK1:$src)),
1651 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +00001652 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1653 sub_16bit)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +00001654 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1655 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1656 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1657 (COPY_TO_REGCLASS VK1:$src, VK8)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001658}
Robert Khasanov74acbb72014-07-23 14:49:42 +00001659let Predicates = [HasBWI] in {
1660 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1661 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1662 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1663 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1664}
1665
1666
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001667// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1668let Predicates = [HasAVX512] in {
1669 // GR from/to 8-bit mask without native support
1670 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1671 (COPY_TO_REGCLASS
1672 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1673 VK8)>;
1674 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1675 (EXTRACT_SUBREG
1676 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1677 sub_8bit)>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +00001678
Elena Demikhovsky9f423d62014-02-10 07:02:39 +00001679 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +00001680 (COPY_TO_REGCLASS VK16:$src, VK1)>;
Elena Demikhovsky9f423d62014-02-10 07:02:39 +00001681 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +00001682 (COPY_TO_REGCLASS VK8:$src, VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +00001683}
1684let Predicates = [HasBWI] in {
1685 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1686 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1687 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1688 (COPY_TO_REGCLASS VK64:$src, VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001689}
1690
1691// Mask unary operation
1692// - KNOT
1693multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
Robert Khasanov74acbb72014-07-23 14:49:42 +00001694 RegisterClass KRC, SDPatternOperator OpNode,
1695 Predicate prd> {
1696 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001697 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00001698 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001699 [(set KRC:$dst, (OpNode KRC:$src))]>;
1700}
1701
Robert Khasanov74acbb72014-07-23 14:49:42 +00001702multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1703 SDPatternOperator OpNode> {
1704 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1705 HasDQI>, VEX, PD;
1706 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1707 HasAVX512>, VEX, PS;
1708 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1709 HasBWI>, VEX, PD, VEX_W;
1710 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1711 HasBWI>, VEX, PS, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001712}
1713
Robert Khasanov74acbb72014-07-23 14:49:42 +00001714defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001715
Elena Demikhovskye382c3f2013-12-10 13:53:10 +00001716multiclass avx512_mask_unop_int<string IntName, string InstName> {
1717 let Predicates = [HasAVX512] in
1718 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1719 (i16 GR16:$src)),
1720 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1721 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1722}
1723defm : avx512_mask_unop_int<"knot", "KNOT">;
1724
Robert Khasanov74acbb72014-07-23 14:49:42 +00001725let Predicates = [HasDQI] in
1726def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1727let Predicates = [HasAVX512] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001728def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +00001729let Predicates = [HasBWI] in
1730def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1731let Predicates = [HasBWI] in
1732def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1733
1734// KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1735let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001736def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1737 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1738
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001739def : Pat<(not VK8:$src),
1740 (COPY_TO_REGCLASS
1741 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +00001742}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001743
1744// Mask binary operation
Elena Demikhovskye382c3f2013-12-10 13:53:10 +00001745// - KAND, KANDN, KOR, KXNOR, KXOR
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001746multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
Robert Khasanov595683d2014-07-28 13:46:45 +00001747 RegisterClass KRC, SDPatternOperator OpNode,
1748 Predicate prd> {
1749 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001750 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1751 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00001752 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001753 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1754}
1755
Robert Khasanov595683d2014-07-28 13:46:45 +00001756multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1757 SDPatternOperator OpNode> {
1758 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1759 HasDQI>, VEX_4V, VEX_L, PD;
1760 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1761 HasAVX512>, VEX_4V, VEX_L, PS;
1762 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1763 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1764 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1765 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001766}
1767
1768def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1769def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1770
1771let isCommutable = 1 in {
Robert Khasanov595683d2014-07-28 13:46:45 +00001772 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1773 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1774 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1775 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001776}
Robert Khasanov595683d2014-07-28 13:46:45 +00001777let isCommutable = 0 in
1778 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001779
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +00001780def : Pat<(xor VK1:$src1, VK1:$src2),
1781 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1782 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1783
1784def : Pat<(or VK1:$src1, VK1:$src2),
1785 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1786 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1787
Elena Demikhovskyb64d7e82013-12-25 10:06:40 +00001788def : Pat<(and VK1:$src1, VK1:$src2),
1789 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1790 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1791
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001792multiclass avx512_mask_binop_int<string IntName, string InstName> {
1793 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +00001794 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1795 (i16 GR16:$src1), (i16 GR16:$src2)),
1796 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1797 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1798 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001799}
1800
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001801defm : avx512_mask_binop_int<"kand", "KAND">;
1802defm : avx512_mask_binop_int<"kandn", "KANDN">;
1803defm : avx512_mask_binop_int<"kor", "KOR">;
1804defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1805defm : avx512_mask_binop_int<"kxor", "KXOR">;
Elena Demikhovskye382c3f2013-12-10 13:53:10 +00001806
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001807// With AVX-512, 8-bit mask is promoted to 16-bit mask.
1808multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1809 let Predicates = [HasAVX512] in
1810 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1811 (COPY_TO_REGCLASS
1812 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1813 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1814}
1815
1816defm : avx512_binop_pat<and, KANDWrr>;
1817defm : avx512_binop_pat<andn, KANDNWrr>;
1818defm : avx512_binop_pat<or, KORWrr>;
1819defm : avx512_binop_pat<xnor, KXNORWrr>;
1820defm : avx512_binop_pat<xor, KXORWrr>;
1821
1822// Mask unpacking
1823multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
Elena Demikhovskye382c3f2013-12-10 13:53:10 +00001824 RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001825 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +00001826 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001827 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00001828 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001829}
1830
1831multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
Elena Demikhovskye382c3f2013-12-10 13:53:10 +00001832 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
Craig Topperae11aed2014-01-14 07:41:20 +00001833 VEX_4V, VEX_L, PD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001834}
1835
1836defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
Elena Demikhovskyc5f67262013-12-17 08:33:15 +00001837def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1838 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1839 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1840
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001841
1842multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1843 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +00001844 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1845 (i16 GR16:$src1), (i16 GR16:$src2)),
1846 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1847 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1848 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001849}
Elena Demikhovskye382c3f2013-12-10 13:53:10 +00001850defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001851
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001852// Mask bit testing
1853multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1854 SDNode OpNode> {
1855 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1856 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
Craig Topperedb09112014-11-25 20:11:23 +00001857 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001858 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1859}
1860
1861multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1862 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topper5ccb6172014-02-18 00:21:49 +00001863 VEX, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001864}
1865
1866defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +00001867
Elena Demikhovsky64c95482013-12-24 14:24:07 +00001868def : Pat<(X86cmp VK1:$src1, (i1 0)),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +00001869 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
Elena Demikhovsky64c95482013-12-24 14:24:07 +00001870 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001871
1872// Mask shift
1873multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1874 SDNode OpNode> {
1875 let Predicates = [HasAVX512] in
1876 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1877 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00001878 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001879 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1880}
1881
1882multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1883 SDNode OpNode> {
1884 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topperae11aed2014-01-14 07:41:20 +00001885 VEX, TAPD, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001886}
1887
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +00001888defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1889defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001890
1891// Mask setting all 0s or 1s
1892multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1893 let Predicates = [HasAVX512] in
1894 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1895 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1896 [(set KRC:$dst, (VT Val))]>;
1897}
1898
1899multiclass avx512_mask_setop_w<PatFrag Val> {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +00001900 defm B : avx512_mask_setop<VK8, v8i1, Val>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001901 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1902}
1903
1904defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1905defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1906
1907// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1908let Predicates = [HasAVX512] in {
1909 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1910 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00001911 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1912 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1913 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001914}
1915def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1916 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1917
1918def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1919 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1920
1921def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1922 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1923
Robert Khasanov5aa44452014-09-30 11:41:54 +00001924let Predicates = [HasVLX] in {
1925 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1926 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1927 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1928 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1929 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1930 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1931 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1932 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1933}
1934
Elena Demikhovsky9737e382014-03-02 09:19:44 +00001935def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1936 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1937
1938def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1939 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001940//===----------------------------------------------------------------------===//
1941// AVX-512 - Aligned and unaligned load and store
1942//
1943
Robert Khasanov7ca7df02014-08-04 14:35:15 +00001944multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1945 RegisterClass KRC, RegisterClass RC,
1946 ValueType vt, ValueType zvt, X86MemOperand memop,
1947 Domain d, bit IsReMaterializable = 1> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +00001948let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001949 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +00001950 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1951 d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +00001952 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +00001953 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1954 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
Elena Demikhovskyfd056672014-03-13 12:05:52 +00001955 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +00001956 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1957 SchedRW = [WriteLoad] in
1958 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1959 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1960 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1961 d>, EVEX;
1962
1963 let AddedComplexity = 20 in {
1964 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1965 let hasSideEffects = 0 in
1966 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1967 (ins RC:$src0, KRC:$mask, RC:$src1),
1968 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1969 "${dst} {${mask}}, $src1}"),
1970 [(set RC:$dst, (vt (vselect KRC:$mask,
1971 (vt RC:$src1),
1972 (vt RC:$src0))))],
1973 d>, EVEX, EVEX_K;
1974 let mayLoad = 1, SchedRW = [WriteLoad] in
1975 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1976 (ins RC:$src0, KRC:$mask, memop:$src1),
1977 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1978 "${dst} {${mask}}, $src1}"),
1979 [(set RC:$dst, (vt
1980 (vselect KRC:$mask,
1981 (vt (bitconvert (ld_frag addr:$src1))),
1982 (vt RC:$src0))))],
1983 d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +00001984 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +00001985 let mayLoad = 1, SchedRW = [WriteLoad] in
1986 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1987 (ins KRC:$mask, memop:$src),
1988 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1989 "${dst} {${mask}} {z}, $src}"),
1990 [(set RC:$dst, (vt
1991 (vselect KRC:$mask,
1992 (vt (bitconvert (ld_frag addr:$src))),
1993 (vt (bitconvert (zvt immAllZerosV))))))],
1994 d>, EVEX, EVEX_KZ;
1995 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00001996}
1997
Robert Khasanov7ca7df02014-08-04 14:35:15 +00001998multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1999 string elty, string elsz, string vsz512,
2000 string vsz256, string vsz128, Domain d,
2001 Predicate prd, bit IsReMaterializable = 1> {
2002 let Predicates = [prd] in
2003 defm Z : avx512_load<opc, OpcodeStr,
2004 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
2005 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2006 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
2007 !cast<X86MemOperand>(elty##"512mem"), d,
2008 IsReMaterializable>, EVEX_V512;
2009
2010 let Predicates = [prd, HasVLX] in {
2011 defm Z256 : avx512_load<opc, OpcodeStr,
2012 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2013 "v"##vsz256##elty##elsz, "v4i64")),
2014 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2015 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
2016 !cast<X86MemOperand>(elty##"256mem"), d,
2017 IsReMaterializable>, EVEX_V256;
2018
2019 defm Z128 : avx512_load<opc, OpcodeStr,
2020 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2021 "v"##vsz128##elty##elsz, "v2i64")),
2022 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2023 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
2024 !cast<X86MemOperand>(elty##"128mem"), d,
2025 IsReMaterializable>, EVEX_V128;
2026 }
2027}
2028
2029
2030multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2031 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2032 X86MemOperand memop, Domain d> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +00002033 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2034 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +00002035 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +00002036 EVEX;
2037 let Constraints = "$src1 = $dst" in
Robert Khasanov7ca7df02014-08-04 14:35:15 +00002038 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2039 (ins RC:$src1, KRC:$mask, RC:$src2),
2040 !strconcat(OpcodeStr,
2041 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +00002042 EVEX, EVEX_K;
Robert Khasanov7ca7df02014-08-04 14:35:15 +00002043 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
Elena Demikhovskyfd056672014-03-13 12:05:52 +00002044 (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +00002045 !strconcat(OpcodeStr,
2046 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +00002047 [], d>, EVEX, EVEX_KZ;
2048 }
2049 let mayStore = 1 in {
Robert Khasanov7ca7df02014-08-04 14:35:15 +00002050 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2051 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2052 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +00002053 def mrk : AVX512PI<opc, MRMDestMem, (outs),
Robert Khasanov7ca7df02014-08-04 14:35:15 +00002054 (ins memop:$dst, KRC:$mask, RC:$src),
2055 !strconcat(OpcodeStr,
2056 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +00002057 [], d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +00002058 }
2059}
2060
Robert Khasanov7ca7df02014-08-04 14:35:15 +00002061
2062multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2063 string st_suff_512, string st_suff_256,
2064 string st_suff_128, string elty, string elsz,
2065 string vsz512, string vsz256, string vsz128,
2066 Domain d, Predicate prd> {
2067 let Predicates = [prd] in
2068 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2069 !cast<ValueType>("v"##vsz512##elty##elsz),
2070 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2071 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2072
2073 let Predicates = [prd, HasVLX] in {
2074 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2075 !cast<ValueType>("v"##vsz256##elty##elsz),
2076 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2077 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2078
2079 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2080 !cast<ValueType>("v"##vsz128##elty##elsz),
2081 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2082 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2083 }
2084}
2085
2086defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2087 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2088 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2089 "512", "256", "", "f", "32", "16", "8", "4",
2090 SSEPackedSingle, HasAVX512>,
2091 PS, EVEX_CD8<32, CD8VF>;
2092
2093defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2094 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2095 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2096 "512", "256", "", "f", "64", "8", "4", "2",
2097 SSEPackedDouble, HasAVX512>,
2098 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2099
2100defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2101 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2102 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2103 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2104 PS, EVEX_CD8<32, CD8VF>;
2105
2106defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2107 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2108 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2109 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2110 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2111
Elena Demikhovskyfd056672014-03-13 12:05:52 +00002112def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +00002113 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
Elena Demikhovskyfd056672014-03-13 12:05:52 +00002114 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002115
Elena Demikhovskyfd056672014-03-13 12:05:52 +00002116def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2117 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2118 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002119
Elena Demikhovskyfd056672014-03-13 12:05:52 +00002120def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2121 GR16:$mask),
2122 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2123 VR512:$src)>;
2124def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2125 GR8:$mask),
2126 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2127 VR512:$src)>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +00002128
Elena Demikhovskyf1de34b2014-12-04 09:40:44 +00002129def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2130 (VMOVUPSZmrk addr:$ptr,
2131 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2132 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2133
2134def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2135 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2136 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2137
2138def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src)),
2139 (VMOVUPSZmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2140
2141def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src)),
2142 (VMOVUPDZmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2143
2144def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2145 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2146
2147def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask,
2148 (bc_v16f32 (v16i32 immAllZerosV)))),
2149 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2150
2151def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src0))),
2152 (VMOVUPSZrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2153
2154def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2155 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2156
2157def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask,
2158 (bc_v8f64 (v16i32 immAllZerosV)))),
2159 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2160
2161def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src0))),
2162 (VMOVUPDZrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2163
Robert Khasanov7ca7df02014-08-04 14:35:15 +00002164defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2165 "16", "8", "4", SSEPackedInt, HasAVX512>,
2166 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2167 "512", "256", "", "i", "32", "16", "8", "4",
2168 SSEPackedInt, HasAVX512>,
2169 PD, EVEX_CD8<32, CD8VF>;
2170
2171defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2172 "8", "4", "2", SSEPackedInt, HasAVX512>,
2173 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2174 "512", "256", "", "i", "64", "8", "4", "2",
2175 SSEPackedInt, HasAVX512>,
2176 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2177
2178defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2179 "64", "32", "16", SSEPackedInt, HasBWI>,
2180 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2181 "i", "8", "64", "32", "16", SSEPackedInt,
2182 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2183
2184defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2185 "32", "16", "8", SSEPackedInt, HasBWI>,
2186 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2187 "i", "16", "32", "16", "8", SSEPackedInt,
2188 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2189
2190defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2191 "16", "8", "4", SSEPackedInt, HasAVX512>,
2192 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2193 "i", "32", "16", "8", "4", SSEPackedInt,
2194 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2195
2196defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2197 "8", "4", "2", SSEPackedInt, HasAVX512>,
2198 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2199 "i", "64", "8", "4", "2", SSEPackedInt,
2200 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +00002201
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +00002202def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2203 (v16i32 immAllZerosV), GR16:$mask)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +00002204 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +00002205
2206def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +00002207 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2208 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +00002209
Elena Demikhovskye73333a2014-05-04 13:35:37 +00002210def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +00002211 GR16:$mask),
2212 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +00002213 VR512:$src)>;
2214def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +00002215 GR8:$mask),
2216 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +00002217 VR512:$src)>;
2218
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002219let AddedComplexity = 20 in {
Elena Demikhovskya30e4372014-02-05 07:05:03 +00002220def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +00002221 (bc_v8i64 (v16i32 immAllZerosV)))),
2222 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +00002223
2224def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +00002225 (v8i64 VR512:$src))),
2226 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
Elena Demikhovskya30e4372014-02-05 07:05:03 +00002227 VK8), VR512:$src)>;
2228
2229def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2230 (v16i32 immAllZerosV))),
Robert Khasanov7ca7df02014-08-04 14:35:15 +00002231 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +00002232
2233def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
Robert Khasanov7ca7df02014-08-04 14:35:15 +00002234 (v16i32 VR512:$src))),
2235 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002236}
Robert Khasanov7ca7df02014-08-04 14:35:15 +00002237
Elena Demikhovskyf1de34b2014-12-04 09:40:44 +00002238def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 immAllZerosV))),
2239 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2240
2241def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2242 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2243
2244def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src0))),
2245 (VMOVDQU32Zrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2246
2247def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask,
2248 (bc_v8i64 (v16i32 immAllZerosV)))),
2249 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2250
2251def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2252 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2253
2254def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src0))),
2255 (VMOVDQU64Zrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2256
2257def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src)),
2258 (VMOVDQU32Zmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2259
2260def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src)),
2261 (VMOVDQU64Zmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2262
2263// SKX replacement
2264def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2265 (VMOVDQU32Z256mrk addr:$ptr, VK8WM:$mask, VR256:$src)>;
2266
2267// KNL replacement
2268def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2269 (VMOVDQU32Zmrk addr:$ptr,
2270 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2271 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2272
2273def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2274 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2275 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2276
2277
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002278// Move Int Doubleword to Packed Double Int
2279//
Elena Demikhovsky767fc962014-01-14 15:10:08 +00002280def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +00002281 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002282 [(set VR128X:$dst,
2283 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2284 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +00002285def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +00002286 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002287 [(set VR128X:$dst,
2288 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2289 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +00002290def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +00002291 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002292 [(set VR128X:$dst,
2293 (v2i64 (scalar_to_vector GR64:$src)))],
2294 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
Craig Topper88adf2a2013-10-12 05:41:08 +00002295let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +00002296def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +00002297 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002298 [(set FR64:$dst, (bitconvert GR64:$src))],
2299 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +00002300def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +00002301 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002302 [(set GR64:$dst, (bitconvert FR64:$src))],
2303 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Craig Topper88adf2a2013-10-12 05:41:08 +00002304}
Elena Demikhovsky767fc962014-01-14 15:10:08 +00002305def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +00002306 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002307 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2308 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2309 EVEX_CD8<64, CD8VT1>;
2310
2311// Move Int Doubleword to Single Scalar
2312//
Craig Topper88adf2a2013-10-12 05:41:08 +00002313let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +00002314def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +00002315 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002316 [(set FR32X:$dst, (bitconvert GR32:$src))],
2317 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2318
Elena Demikhovsky767fc962014-01-14 15:10:08 +00002319def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +00002320 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002321 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2322 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +00002323}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002324
Elena Demikhovsky767fc962014-01-14 15:10:08 +00002325// Move doubleword from xmm register to r/m32
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002326//
Elena Demikhovsky767fc962014-01-14 15:10:08 +00002327def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +00002328 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002329 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2330 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2331 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +00002332def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002333 (ins i32mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +00002334 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002335 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2336 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2337 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2338
Elena Demikhovsky767fc962014-01-14 15:10:08 +00002339// Move quadword from xmm1 register to r/m64
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002340//
2341def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +00002342 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002343 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2344 (iPTR 0)))],
Craig Topperae11aed2014-01-14 07:41:20 +00002345 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002346 Requires<[HasAVX512, In64BitMode]>;
2347
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +00002348def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002349 (ins i64mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +00002350 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002351 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2352 addr:$dst)], IIC_SSE_MOVDQ>,
Craig Topperae11aed2014-01-14 07:41:20 +00002353 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002354 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2355
2356// Move Scalar Single to Double Int
2357//
Craig Topper88adf2a2013-10-12 05:41:08 +00002358let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +00002359def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002360 (ins FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +00002361 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002362 [(set GR32:$dst, (bitconvert FR32X:$src))],
2363 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +00002364def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002365 (ins i32mem:$dst, FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +00002366 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002367 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2368 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +00002369}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002370
2371// Move Quadword Int to Packed Quadword Int
2372//
Elena Demikhovsky767fc962014-01-14 15:10:08 +00002373def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002374 (ins i64mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +00002375 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002376 [(set VR128X:$dst,
2377 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2378 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2379
2380//===----------------------------------------------------------------------===//
2381// AVX-512 MOVSS, MOVSD
2382//===----------------------------------------------------------------------===//
2383
Michael Liao5bf95782014-12-04 05:20:33 +00002384multiclass avx512_move_scalar <string asm, RegisterClass RC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002385 SDNode OpNode, ValueType vt,
2386 X86MemOperand x86memop, PatFrag mem_pat> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +00002387 let hasSideEffects = 0 in {
Michael Liao5bf95782014-12-04 05:20:33 +00002388 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
Craig Topperedb09112014-11-25 20:11:23 +00002389 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002390 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2391 (scalar_to_vector RC:$src2))))],
2392 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +00002393 let Constraints = "$src1 = $dst" in
2394 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2395 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2396 !strconcat(asm,
Craig Topperedb09112014-11-25 20:11:23 +00002397 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +00002398 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002399 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00002400 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002401 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2402 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +00002403 let mayStore = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002404 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00002405 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002406 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2407 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +00002408 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00002409 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
Elena Demikhovskyff620ed2014-08-27 07:38:43 +00002410 [], IIC_SSE_MOV_S_MR>,
2411 EVEX, VEX_LIG, EVEX_K;
2412 } // mayStore
Elena Demikhovskyf404e052014-01-05 14:21:07 +00002413 } //hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002414}
2415
2416let ExeDomain = SSEPackedSingle in
Elena Demikhovskycf088092013-12-11 14:31:04 +00002417defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002418 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2419
2420let ExeDomain = SSEPackedDouble in
Elena Demikhovskycf088092013-12-11 14:31:04 +00002421defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002422 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2423
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +00002424def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2425 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2426 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2427
2428def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2429 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2430 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002431
Elena Demikhovskyff620ed2014-08-27 07:38:43 +00002432def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2433 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2434 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2435
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002436// For the disassembler
Craig Topper3484fc22014-01-05 04:17:28 +00002437let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002438 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2439 (ins VR128X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +00002440 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002441 IIC_SSE_MOV_S_RR>,
2442 XS, EVEX_4V, VEX_LIG;
2443 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2444 (ins VR128X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +00002445 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002446 IIC_SSE_MOV_S_RR>,
2447 XD, EVEX_4V, VEX_LIG, VEX_W;
2448}
2449
2450let Predicates = [HasAVX512] in {
2451 let AddedComplexity = 15 in {
2452 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2453 // MOVS{S,D} to the lower bits.
2454 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2455 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2456 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2457 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2458 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2459 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2460 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2461 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2462
2463 // Move low f32 and clear high bits.
2464 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2465 (SUBREG_TO_REG (i32 0),
Michael Liao5bf95782014-12-04 05:20:33 +00002466 (VMOVSSZrr (v4f32 (V_SET0)),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002467 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2468 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2469 (SUBREG_TO_REG (i32 0),
2470 (VMOVSSZrr (v4i32 (V_SET0)),
2471 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2472 }
2473
2474 let AddedComplexity = 20 in {
2475 // MOVSSrm zeros the high parts of the register; represent this
2476 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2477 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2478 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2479 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2480 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2481 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2482 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2483
2484 // MOVSDrm zeros the high parts of the register; represent this
2485 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2486 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2487 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2488 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2489 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2490 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2491 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2492 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2493 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2494 def : Pat<(v2f64 (X86vzload addr:$src)),
2495 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2496
2497 // Represent the same patterns above but in the form they appear for
2498 // 256-bit types
2499 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2500 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +00002501 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002502 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2503 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2504 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2505 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2506 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2507 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2508 }
2509 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2510 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2511 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2512 FR32X:$src)), sub_xmm)>;
2513 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2514 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2515 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2516 FR64X:$src)), sub_xmm)>;
2517 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2518 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +00002519 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002520
2521 // Move low f64 and clear high bits.
2522 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2523 (SUBREG_TO_REG (i32 0),
2524 (VMOVSDZrr (v2f64 (V_SET0)),
2525 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2526
2527 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2528 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2529 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2530
2531 // Extract and store.
2532 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2533 addr:$dst),
2534 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2535 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2536 addr:$dst),
2537 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2538
2539 // Shuffle with VMOVSS
2540 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2541 (VMOVSSZrr (v4i32 VR128X:$src1),
2542 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2543 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2544 (VMOVSSZrr (v4f32 VR128X:$src1),
2545 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2546
2547 // 256-bit variants
2548 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2549 (SUBREG_TO_REG (i32 0),
2550 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2551 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2552 sub_xmm)>;
2553 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2554 (SUBREG_TO_REG (i32 0),
2555 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2556 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2557 sub_xmm)>;
2558
2559 // Shuffle with VMOVSD
2560 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2561 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2562 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2563 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2564 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2565 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2566 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2567 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2568
2569 // 256-bit variants
2570 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2571 (SUBREG_TO_REG (i32 0),
2572 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2573 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2574 sub_xmm)>;
2575 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2576 (SUBREG_TO_REG (i32 0),
2577 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2578 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2579 sub_xmm)>;
2580
2581 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2582 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2583 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2584 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2585 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2586 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2587 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2588 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2589}
2590
2591let AddedComplexity = 15 in
2592def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2593 (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +00002594 "vmovq\t{$src, $dst|$dst, $src}",
Michael Liao5bf95782014-12-04 05:20:33 +00002595 [(set VR128X:$dst, (v2i64 (X86vzmovl
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002596 (v2i64 VR128X:$src))))],
2597 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2598
2599let AddedComplexity = 20 in
2600def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2601 (ins i128mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +00002602 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002603 [(set VR128X:$dst, (v2i64 (X86vzmovl
2604 (loadv2i64 addr:$src))))],
2605 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2606 EVEX_CD8<8, CD8VT8>;
2607
2608let Predicates = [HasAVX512] in {
2609 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2610 let AddedComplexity = 20 in {
2611 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2612 (VMOVDI2PDIZrm addr:$src)>;
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +00002613 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2614 (VMOV64toPQIZrr GR64:$src)>;
2615 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2616 (VMOVDI2PDIZrr GR32:$src)>;
Michael Liao5bf95782014-12-04 05:20:33 +00002617
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002618 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2619 (VMOVDI2PDIZrm addr:$src)>;
2620 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2621 (VMOVDI2PDIZrm addr:$src)>;
2622 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2623 (VMOVZPQILo2PQIZrm addr:$src)>;
2624 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2625 (VMOVZPQILo2PQIZrr VR128X:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +00002626 def : Pat<(v2i64 (X86vzload addr:$src)),
2627 (VMOVZPQILo2PQIZrm addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002628 }
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +00002629
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002630 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2631 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2632 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2633 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2634 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2635 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2636 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2637}
2638
2639def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2640 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2641
2642def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2643 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2644
2645def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2646 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2647
2648def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2649 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2650
2651//===----------------------------------------------------------------------===//
Adam Nemet7f62b232014-06-10 16:39:53 +00002652// AVX-512 - Non-temporals
2653//===----------------------------------------------------------------------===//
Robert Khasanoved882972014-08-13 10:46:00 +00002654let SchedRW = [WriteLoad] in {
2655 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2656 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2657 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2658 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2659 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +00002660
Robert Khasanoved882972014-08-13 10:46:00 +00002661 let Predicates = [HasAVX512, HasVLX] in {
2662 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2663 (ins i256mem:$src),
2664 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2665 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2666 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +00002667
Robert Khasanoved882972014-08-13 10:46:00 +00002668 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2669 (ins i128mem:$src),
2670 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2671 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2672 EVEX_CD8<64, CD8VF>;
2673 }
Adam Nemetefd07852014-06-18 16:51:10 +00002674}
2675
Robert Khasanoved882972014-08-13 10:46:00 +00002676multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2677 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2678 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2679 let SchedRW = [WriteStore], mayStore = 1,
2680 AddedComplexity = 400 in
2681 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2682 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2683 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2684}
2685
2686multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2687 string elty, string elsz, string vsz512,
2688 string vsz256, string vsz128, Domain d,
2689 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2690 let Predicates = [prd] in
2691 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2692 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2693 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2694 EVEX_V512;
2695
2696 let Predicates = [prd, HasVLX] in {
2697 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2698 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2699 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2700 EVEX_V256;
2701
2702 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2703 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2704 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2705 EVEX_V128;
2706 }
2707}
2708
2709defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2710 "i", "64", "8", "4", "2", SSEPackedInt,
2711 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2712
2713defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2714 "f", "64", "8", "4", "2", SSEPackedDouble,
2715 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2716
2717defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2718 "f", "32", "16", "8", "4", SSEPackedSingle,
2719 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2720
Adam Nemet7f62b232014-06-10 16:39:53 +00002721//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002722// AVX-512 - Integer arithmetic
2723//
2724multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanov44241442014-10-08 14:37:45 +00002725 X86VectorVTInfo _, OpndItins itins,
2726 bit IsCommutable = 0> {
Adam Nemet34801422014-10-08 23:25:39 +00002727 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
Robert Khasanov44241442014-10-08 14:37:45 +00002728 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2729 "$src2, $src1", "$src1, $src2",
2730 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
Elena Demikhovskybe8808d2014-11-12 07:31:03 +00002731 "", itins.rr, IsCommutable>,
Robert Khasanov44241442014-10-08 14:37:45 +00002732 AVX512BIBase, EVEX_4V;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00002733
Robert Khasanov545d1b72014-10-14 14:36:19 +00002734 let mayLoad = 1 in
Adam Nemet34801422014-10-08 23:25:39 +00002735 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
Robert Khasanov44241442014-10-08 14:37:45 +00002736 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2737 "$src2, $src1", "$src1, $src2",
2738 (_.VT (OpNode _.RC:$src1,
2739 (bitconvert (_.LdFrag addr:$src2)))),
Elena Demikhovskybe8808d2014-11-12 07:31:03 +00002740 "", itins.rm>,
Robert Khasanov44241442014-10-08 14:37:45 +00002741 AVX512BIBase, EVEX_4V;
Robert Khasanov545d1b72014-10-14 14:36:19 +00002742}
2743
2744multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2745 X86VectorVTInfo _, OpndItins itins,
2746 bit IsCommutable = 0> :
2747 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2748 let mayLoad = 1 in
Adam Nemet34801422014-10-08 23:25:39 +00002749 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
Robert Khasanov44241442014-10-08 14:37:45 +00002750 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2751 "${src2}"##_.BroadcastStr##", $src1",
2752 "$src1, ${src2}"##_.BroadcastStr,
2753 (_.VT (OpNode _.RC:$src1,
2754 (X86VBroadcast
2755 (_.ScalarLdFrag addr:$src2)))),
Elena Demikhovskybe8808d2014-11-12 07:31:03 +00002756 "", itins.rm>,
Robert Khasanov44241442014-10-08 14:37:45 +00002757 AVX512BIBase, EVEX_4V, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002758}
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00002759
Robert Khasanovd5b14f72014-10-09 08:38:48 +00002760multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2761 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2762 Predicate prd, bit IsCommutable = 0> {
2763 let Predicates = [prd] in
2764 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2765 IsCommutable>, EVEX_V512;
2766
2767 let Predicates = [prd, HasVLX] in {
2768 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2769 IsCommutable>, EVEX_V256;
2770 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2771 IsCommutable>, EVEX_V128;
2772 }
2773}
2774
Robert Khasanov545d1b72014-10-14 14:36:19 +00002775multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2776 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2777 Predicate prd, bit IsCommutable = 0> {
2778 let Predicates = [prd] in
2779 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2780 IsCommutable>, EVEX_V512;
2781
2782 let Predicates = [prd, HasVLX] in {
2783 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2784 IsCommutable>, EVEX_V256;
2785 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2786 IsCommutable>, EVEX_V128;
2787 }
2788}
2789
2790multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2791 OpndItins itins, Predicate prd,
2792 bit IsCommutable = 0> {
2793 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2794 itins, prd, IsCommutable>,
2795 VEX_W, EVEX_CD8<64, CD8VF>;
2796}
2797
2798multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2799 OpndItins itins, Predicate prd,
2800 bit IsCommutable = 0> {
2801 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2802 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2803}
2804
2805multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2806 OpndItins itins, Predicate prd,
2807 bit IsCommutable = 0> {
2808 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2809 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2810}
2811
2812multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2813 OpndItins itins, Predicate prd,
2814 bit IsCommutable = 0> {
2815 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2816 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2817}
2818
2819multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2820 SDNode OpNode, OpndItins itins, Predicate prd,
2821 bit IsCommutable = 0> {
2822 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2823 IsCommutable>;
2824
2825 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2826 IsCommutable>;
2827}
2828
2829multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2830 SDNode OpNode, OpndItins itins, Predicate prd,
2831 bit IsCommutable = 0> {
2832 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2833 IsCommutable>;
2834
2835 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2836 IsCommutable>;
2837}
2838
2839multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2840 bits<8> opc_d, bits<8> opc_q,
2841 string OpcodeStr, SDNode OpNode,
2842 OpndItins itins, bit IsCommutable = 0> {
2843 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2844 itins, HasAVX512, IsCommutable>,
2845 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2846 itins, HasBWI, IsCommutable>;
2847}
2848
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00002849multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2850 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2851 PatFrag memop_frag, X86MemOperand x86memop,
2852 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2853 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002854 let isCommutable = IsCommutable in
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00002855 {
2856 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002857 (ins RC:$src1, RC:$src2),
Craig Topperedb09112014-11-25 20:11:23 +00002858 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00002859 []>, EVEX_4V;
2860 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2861 (ins KRC:$mask, RC:$src1, RC:$src2),
2862 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00002863 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00002864 [], itins.rr>, EVEX_4V, EVEX_K;
2865 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2866 (ins KRC:$mask, RC:$src1, RC:$src2),
Craig Topperedb09112014-11-25 20:11:23 +00002867 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}} {z}" ,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00002868 "|$dst {${mask}} {z}, $src1, $src2}"),
2869 [], itins.rr>, EVEX_4V, EVEX_KZ;
2870 }
2871 let mayLoad = 1 in {
2872 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2873 (ins RC:$src1, x86memop:$src2),
Craig Topperedb09112014-11-25 20:11:23 +00002874 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00002875 []>, EVEX_4V;
2876 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2877 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2878 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00002879 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00002880 [], itins.rm>, EVEX_4V, EVEX_K;
2881 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2882 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2883 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00002884 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00002885 [], itins.rm>, EVEX_4V, EVEX_KZ;
2886 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2887 (ins RC:$src1, x86scalar_mop:$src2),
Craig Topperedb09112014-11-25 20:11:23 +00002888 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00002889 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2890 [], itins.rm>, EVEX_4V, EVEX_B;
2891 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2892 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
Craig Topperedb09112014-11-25 20:11:23 +00002893 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00002894 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2895 BrdcstStr, "}"),
2896 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2897 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2898 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
Craig Topperedb09112014-11-25 20:11:23 +00002899 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00002900 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2901 BrdcstStr, "}"),
2902 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2903 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002904}
2905
Robert Khasanov545d1b72014-10-14 14:36:19 +00002906defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
2907 SSE_INTALU_ITINS_P, 1>;
2908defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
2909 SSE_INTALU_ITINS_P, 0>;
2910defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
2911 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2912defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
2913 SSE_INTALU_ITINS_P, HasBWI, 1>;
Robert Khasanov1a77f662014-10-14 15:13:56 +00002914defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
2915 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002916
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00002917defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2918 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2919 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2920 EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002921
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00002922defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2923 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2924 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002925
2926def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2927 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2928
Elena Demikhovsky172a27c2014-01-08 10:54:22 +00002929def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2930 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2931 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2932def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2933 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2934 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2935
Robert Khasanov545d1b72014-10-14 14:36:19 +00002936defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
2937 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2938defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
2939 SSE_INTALU_ITINS_P, HasBWI, 1>;
2940defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
2941 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
Elena Demikhovsky199c8232013-10-27 08:18:37 +00002942
Robert Khasanov545d1b72014-10-14 14:36:19 +00002943defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
2944 SSE_INTALU_ITINS_P, HasBWI, 1>;
2945defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
2946 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2947defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
2948 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
Elena Demikhovsky199c8232013-10-27 08:18:37 +00002949
Robert Khasanov545d1b72014-10-14 14:36:19 +00002950defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
2951 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2952defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
2953 SSE_INTALU_ITINS_P, HasBWI, 1>;
2954defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
2955 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
Elena Demikhovsky199c8232013-10-27 08:18:37 +00002956
Robert Khasanov545d1b72014-10-14 14:36:19 +00002957defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
2958 SSE_INTALU_ITINS_P, HasBWI, 1>;
2959defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
2960 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2961defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
2962 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
Elena Demikhovsky199c8232013-10-27 08:18:37 +00002963
Elena Demikhovsky172a27c2014-01-08 10:54:22 +00002964def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2965 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2966 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2967def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2968 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2969 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2970def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2971 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2972 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2973def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2974 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2975 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2976def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2977 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2978 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2979def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2980 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2981 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2982def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2983 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2984 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2985def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2986 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2987 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00002988//===----------------------------------------------------------------------===//
2989// AVX-512 - Unpack Instructions
2990//===----------------------------------------------------------------------===//
2991
2992multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2993 PatFrag mem_frag, RegisterClass RC,
2994 X86MemOperand x86memop, string asm,
2995 Domain d> {
2996 def rr : AVX512PI<opc, MRMSrcReg,
2997 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2998 asm, [(set RC:$dst,
2999 (vt (OpNode RC:$src1, RC:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +00003000 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003001 def rm : AVX512PI<opc, MRMSrcMem,
3002 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3003 asm, [(set RC:$dst,
3004 (vt (OpNode RC:$src1,
3005 (bitconvert (mem_frag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +00003006 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003007}
3008
3009defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
3010 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +00003011 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003012defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
3013 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +00003014 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003015defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
3016 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +00003017 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003018defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
3019 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +00003020 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003021
3022multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3023 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3024 X86MemOperand x86memop> {
3025 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3026 (ins RC:$src1, RC:$src2),
Craig Topperedb09112014-11-25 20:11:23 +00003027 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Michael Liao5bf95782014-12-04 05:20:33 +00003028 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003029 IIC_SSE_UNPCK>, EVEX_4V;
3030 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3031 (ins RC:$src1, x86memop:$src2),
Craig Topperedb09112014-11-25 20:11:23 +00003032 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003033 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3034 (bitconvert (memop_frag addr:$src2)))))],
3035 IIC_SSE_UNPCK>, EVEX_4V;
3036}
3037defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3038 VR512, memopv16i32, i512mem>, EVEX_V512,
3039 EVEX_CD8<32, CD8VF>;
3040defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3041 VR512, memopv8i64, i512mem>, EVEX_V512,
3042 VEX_W, EVEX_CD8<64, CD8VF>;
3043defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3044 VR512, memopv16i32, i512mem>, EVEX_V512,
3045 EVEX_CD8<32, CD8VF>;
3046defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3047 VR512, memopv8i64, i512mem>, EVEX_V512,
3048 VEX_W, EVEX_CD8<64, CD8VF>;
3049//===----------------------------------------------------------------------===//
3050// AVX-512 - PSHUFD
3051//
3052
3053multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
Michael Liao5bf95782014-12-04 05:20:33 +00003054 SDNode OpNode, PatFrag mem_frag,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003055 X86MemOperand x86memop, ValueType OpVT> {
3056 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3057 (ins RC:$src1, i8imm:$src2),
3058 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00003059 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003060 [(set RC:$dst,
3061 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3062 EVEX;
3063 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3064 (ins x86memop:$src1, i8imm:$src2),
3065 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00003066 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003067 [(set RC:$dst,
3068 (OpVT (OpNode (mem_frag addr:$src1),
3069 (i8 imm:$src2))))]>, EVEX;
3070}
3071
3072defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
Craig Topperae11aed2014-01-14 07:41:20 +00003073 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003074
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003075//===----------------------------------------------------------------------===//
3076// AVX-512 Logical Instructions
3077//===----------------------------------------------------------------------===//
3078
Robert Khasanov545d1b72014-10-14 14:36:19 +00003079defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3080 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3081defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3082 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3083defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3084 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3085defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3086 SSE_INTALU_ITINS_P, HasAVX512, 1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003087
3088//===----------------------------------------------------------------------===//
3089// AVX-512 FP arithmetic
3090//===----------------------------------------------------------------------===//
3091
3092multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3093 SizeItins itins> {
Elena Demikhovskycf088092013-12-11 14:31:04 +00003094 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003095 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
3096 EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +00003097 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003098 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
3099 EVEX_CD8<64, CD8VT1>;
3100}
3101
3102let isCommutable = 1 in {
3103defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3104defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3105defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3106defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3107}
3108let isCommutable = 0 in {
3109defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3110defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3111}
3112
3113multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanov595e5982014-10-29 15:43:02 +00003114 X86VectorVTInfo _, bit IsCommutable> {
3115 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3116 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3117 "$src2, $src1", "$src1, $src2",
3118 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003119 let mayLoad = 1 in {
Robert Khasanov595e5982014-10-29 15:43:02 +00003120 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3121 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3122 "$src2, $src1", "$src1, $src2",
3123 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3124 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3125 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3126 "${src2}"##_.BroadcastStr##", $src1",
3127 "$src1, ${src2}"##_.BroadcastStr,
3128 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3129 (_.ScalarLdFrag addr:$src2))))>,
3130 EVEX_4V, EVEX_B;
3131 }//let mayLoad = 1
3132}
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +00003133
Robert Khasanov595e5982014-10-29 15:43:02 +00003134multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3135 bit IsCommutable = 0> {
3136 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3137 IsCommutable>, EVEX_V512, PS,
3138 EVEX_CD8<32, CD8VF>;
3139 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3140 IsCommutable>, EVEX_V512, PD, VEX_W,
3141 EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +00003142
Robert Khasanov595e5982014-10-29 15:43:02 +00003143 // Define only if AVX512VL feature is present.
3144 let Predicates = [HasVLX] in {
3145 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3146 IsCommutable>, EVEX_V128, PS,
3147 EVEX_CD8<32, CD8VF>;
3148 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3149 IsCommutable>, EVEX_V256, PS,
3150 EVEX_CD8<32, CD8VF>;
3151 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3152 IsCommutable>, EVEX_V128, PD, VEX_W,
3153 EVEX_CD8<64, CD8VF>;
3154 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3155 IsCommutable>, EVEX_V256, PD, VEX_W,
3156 EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +00003157 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003158}
3159
Robert Khasanov595e5982014-10-29 15:43:02 +00003160defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>;
3161defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>;
3162defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3163defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3164defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>;
3165defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003166
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +00003167def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3168 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3169 (i16 -1), FROUND_CURRENT)),
3170 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3171
3172def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3173 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3174 (i8 -1), FROUND_CURRENT)),
3175 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3176
3177def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3178 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3179 (i16 -1), FROUND_CURRENT)),
3180 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3181
3182def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3183 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3184 (i8 -1), FROUND_CURRENT)),
3185 (VMINPDZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003186//===----------------------------------------------------------------------===//
3187// AVX-512 VPTESTM instructions
3188//===----------------------------------------------------------------------===//
3189
Michael Liao5bf95782014-12-04 05:20:33 +00003190multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3191 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003192 SDNode OpNode, ValueType vt> {
Elena Demikhovskya30e4372014-02-05 07:05:03 +00003193 def rr : AVX512PI<opc, MRMSrcReg,
Michael Liao5bf95782014-12-04 05:20:33 +00003194 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
Craig Topperedb09112014-11-25 20:11:23 +00003195 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya30e4372014-02-05 07:05:03 +00003196 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3197 SSEPackedInt>, EVEX_4V;
3198 def rm : AVX512PI<opc, MRMSrcMem,
Michael Liao5bf95782014-12-04 05:20:33 +00003199 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
Craig Topperedb09112014-11-25 20:11:23 +00003200 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Michael Liao5bf95782014-12-04 05:20:33 +00003201 [(set KRC:$dst, (OpNode (vt RC:$src1),
Elena Demikhovskya30e4372014-02-05 07:05:03 +00003202 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003203}
3204
3205defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
Elena Demikhovskya30e4372014-02-05 07:05:03 +00003206 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003207 EVEX_CD8<32, CD8VF>;
3208defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +00003209 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003210 EVEX_CD8<64, CD8VF>;
3211
Elena Demikhovskya30e4372014-02-05 07:05:03 +00003212let Predicates = [HasCDI] in {
3213defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3214 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3215 EVEX_CD8<32, CD8VF>;
3216defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +00003217 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
Elena Demikhovskya30e4372014-02-05 07:05:03 +00003218 EVEX_CD8<64, CD8VF>;
3219}
3220
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00003221def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3222 (v16i32 VR512:$src2), (i16 -1))),
3223 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3224
3225def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3226 (v8i64 VR512:$src2), (i8 -1))),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +00003227 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
Cameron McInally9b7c15a2014-11-25 20:41:51 +00003228
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003229//===----------------------------------------------------------------------===//
3230// AVX-512 Shift instructions
3231//===----------------------------------------------------------------------===//
3232multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
Michael Liao5bf95782014-12-04 05:20:33 +00003233 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
Cameron McInally04400442014-11-14 15:43:00 +00003234 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3235 (ins _.RC:$src1, i8imm:$src2), OpcodeStr,
3236 "$src2, $src1", "$src1, $src2",
3237 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3238 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3239 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3240 (ins _.MemOp:$src1, i8imm:$src2), OpcodeStr,
3241 "$src2, $src1", "$src1, $src2",
3242 (_.VT (OpNode (_.MemOpFrag addr:$src1), (i8 imm:$src2))),
3243 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003244}
3245
3246multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
Cameron McInally9b7c15a2014-11-25 20:41:51 +00003247 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3248 // src2 is always 128-bit
3249 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3250 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3251 "$src2, $src1", "$src1, $src2",
3252 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3253 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3254 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3255 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3256 "$src2, $src1", "$src1, $src2",
3257 (_.VT (OpNode _.RC:$src1, (bc_frag (memopv2i64 addr:$src2)))),
3258 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase, EVEX_4V;
3259}
3260
3261multiclass avx512_varshift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3262 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3263 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag, _>, EVEX_V512;
3264}
3265
Michael Liao5bf95782014-12-04 05:20:33 +00003266multiclass avx512_varshift_types<bits<8> opcd, bits<8> opcq, string OpcodeStr,
Cameron McInally9b7c15a2014-11-25 20:41:51 +00003267 SDNode OpNode> {
Michael Liao5bf95782014-12-04 05:20:33 +00003268 defm D : avx512_varshift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3269 v16i32_info>, EVEX_CD8<32, CD8VQ>;
3270 defm Q : avx512_varshift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
Cameron McInally9b7c15a2014-11-25 20:41:51 +00003271 v8i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003272}
3273
3274defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
Cameron McInally04400442014-11-14 15:43:00 +00003275 v16i32_info>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003276 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003277defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
Cameron McInally04400442014-11-14 15:43:00 +00003278 v8i64_info>, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003279 EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003280
3281defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
Cameron McInally04400442014-11-14 15:43:00 +00003282 v16i32_info>, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003283 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003284defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
Cameron McInally04400442014-11-14 15:43:00 +00003285 v8i64_info>, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003286 EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003287
3288defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
Cameron McInally04400442014-11-14 15:43:00 +00003289 v16i32_info>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003290 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003291defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
Cameron McInally04400442014-11-14 15:43:00 +00003292 v8i64_info>, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003293 EVEX_CD8<64, CD8VF>, VEX_W;
Cameron McInally9b7c15a2014-11-25 20:41:51 +00003294
3295defm VPSRL : avx512_varshift_types<0xD2, 0xD3, "vpsrl", X86vsrl>;
3296defm VPSLL : avx512_varshift_types<0xF2, 0xF3, "vpsll", X86vshl>;
3297defm VPSRA : avx512_varshift_types<0xE2, 0xE2, "vpsra", X86vsra>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003298
3299//===-------------------------------------------------------------------===//
3300// Variable Bit Shifts
3301//===-------------------------------------------------------------------===//
3302multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3303 RegisterClass RC, ValueType vt,
3304 X86MemOperand x86memop, PatFrag mem_frag> {
3305 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3306 (ins RC:$src1, RC:$src2),
Craig Topperedb09112014-11-25 20:11:23 +00003307 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003308 [(set RC:$dst,
3309 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3310 EVEX_4V;
3311 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3312 (ins RC:$src1, x86memop:$src2),
Craig Topperedb09112014-11-25 20:11:23 +00003313 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003314 [(set RC:$dst,
3315 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3316 EVEX_4V;
3317}
3318
Michael Liao5bf95782014-12-04 05:20:33 +00003319defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003320 i512mem, memopv16i32>, EVEX_V512,
3321 EVEX_CD8<32, CD8VF>;
Michael Liao5bf95782014-12-04 05:20:33 +00003322defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003323 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3324 EVEX_CD8<64, CD8VF>;
Michael Liao5bf95782014-12-04 05:20:33 +00003325defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003326 i512mem, memopv16i32>, EVEX_V512,
3327 EVEX_CD8<32, CD8VF>;
Michael Liao5bf95782014-12-04 05:20:33 +00003328defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003329 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3330 EVEX_CD8<64, CD8VF>;
Michael Liao5bf95782014-12-04 05:20:33 +00003331defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003332 i512mem, memopv16i32>, EVEX_V512,
3333 EVEX_CD8<32, CD8VF>;
Michael Liao5bf95782014-12-04 05:20:33 +00003334defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003335 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3336 EVEX_CD8<64, CD8VF>;
3337
3338//===----------------------------------------------------------------------===//
3339// AVX-512 - MOVDDUP
3340//===----------------------------------------------------------------------===//
3341
Michael Liao5bf95782014-12-04 05:20:33 +00003342multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003343 X86MemOperand x86memop, PatFrag memop_frag> {
3344def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00003345 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003346 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3347def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00003348 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003349 [(set RC:$dst,
3350 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3351}
3352
3353defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3354 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3355def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3356 (VMOVDDUPZrm addr:$src)>;
3357
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +00003358//===---------------------------------------------------------------------===//
3359// Replicate Single FP - MOVSHDUP and MOVSLDUP
3360//===---------------------------------------------------------------------===//
3361multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3362 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3363 X86MemOperand x86memop> {
3364 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00003365 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +00003366 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3367 let mayLoad = 1 in
3368 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00003369 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +00003370 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3371}
3372
3373defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3374 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3375 EVEX_CD8<32, CD8VF>;
3376defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3377 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3378 EVEX_CD8<32, CD8VF>;
3379
3380def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3381def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3382 (VMOVSHDUPZrm addr:$src)>;
3383def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3384def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3385 (VMOVSLDUPZrm addr:$src)>;
3386
3387//===----------------------------------------------------------------------===//
3388// Move Low to High and High to Low packed FP Instructions
3389//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003390def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3391 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +00003392 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003393 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3394 IIC_SSE_MOV_LH>, EVEX_4V;
3395def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3396 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +00003397 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003398 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3399 IIC_SSE_MOV_LH>, EVEX_4V;
3400
Craig Topperdbe8b7d2013-09-27 07:20:47 +00003401let Predicates = [HasAVX512] in {
3402 // MOVLHPS patterns
3403 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3404 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3405 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3406 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003407
Craig Topperdbe8b7d2013-09-27 07:20:47 +00003408 // MOVHLPS patterns
3409 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3410 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3411}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003412
3413//===----------------------------------------------------------------------===//
3414// FMA - Fused Multiply Operations
3415//
Adam Nemet26371ce2014-10-24 00:02:55 +00003416
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003417let Constraints = "$src1 = $dst" in {
Adam Nemet26371ce2014-10-24 00:02:55 +00003418// Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3419multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3420 SDPatternOperator OpNode = null_frag> {
Adam Nemet34801422014-10-08 23:25:39 +00003421 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
Adam Nemet6bddb8c2014-09-29 22:54:41 +00003422 (ins _.RC:$src2, _.RC:$src3),
Adam Nemet2e91ee52014-08-14 17:13:19 +00003423 OpcodeStr, "$src3, $src2", "$src2, $src3",
Adam Nemet6bddb8c2014-09-29 22:54:41 +00003424 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
Adam Nemet2e91ee52014-08-14 17:13:19 +00003425 AVX512FMA3Base;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003426
3427 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +00003428 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3429 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
Craig Topperedb09112014-11-25 20:11:23 +00003430 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +00003431 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3432 (_.MemOpFrag addr:$src3))))]>;
3433 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3434 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
Craig Topperedb09112014-11-25 20:11:23 +00003435 !strconcat(OpcodeStr, "\t{${src3}", _.BroadcastStr,
Adam Nemet6bddb8c2014-09-29 22:54:41 +00003436 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3437 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3438 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003439}
3440} // Constraints = "$src1 = $dst"
3441
Adam Nemet832ec5e2014-10-24 00:03:00 +00003442multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
Adam Nemet26371ce2014-10-24 00:02:55 +00003443 string OpcodeStr, X86VectorVTInfo VTI,
3444 SDPatternOperator OpNode> {
3445 defm v213 : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3446 VTI, OpNode>,
3447 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
Adam Nemet832ec5e2014-10-24 00:03:00 +00003448
3449 defm v231 : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3450 VTI>,
3451 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
Adam Nemet26371ce2014-10-24 00:02:55 +00003452}
3453
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003454let ExeDomain = SSEPackedSingle in {
Adam Nemet832ec5e2014-10-24 00:03:00 +00003455 defm VFMADDPSZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
Adam Nemet26371ce2014-10-24 00:02:55 +00003456 v16f32_info, X86Fmadd>;
Adam Nemet832ec5e2014-10-24 00:03:00 +00003457 defm VFMSUBPSZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
Adam Nemet26371ce2014-10-24 00:02:55 +00003458 v16f32_info, X86Fmsub>;
Adam Nemet832ec5e2014-10-24 00:03:00 +00003459 defm VFMADDSUBPSZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
Adam Nemet26371ce2014-10-24 00:02:55 +00003460 v16f32_info, X86Fmaddsub>;
Adam Nemet832ec5e2014-10-24 00:03:00 +00003461 defm VFMSUBADDPSZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
Adam Nemet26371ce2014-10-24 00:02:55 +00003462 v16f32_info, X86Fmsubadd>;
Adam Nemet832ec5e2014-10-24 00:03:00 +00003463 defm VFNMADDPSZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
Adam Nemet26371ce2014-10-24 00:02:55 +00003464 v16f32_info, X86Fnmadd>;
Adam Nemet832ec5e2014-10-24 00:03:00 +00003465 defm VFNMSUBPSZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
Adam Nemet26371ce2014-10-24 00:02:55 +00003466 v16f32_info, X86Fnmsub>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003467}
3468let ExeDomain = SSEPackedDouble in {
Adam Nemet832ec5e2014-10-24 00:03:00 +00003469 defm VFMADDPDZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
Adam Nemet26371ce2014-10-24 00:02:55 +00003470 v8f64_info, X86Fmadd>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +00003471 defm VFMSUBPDZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
Adam Nemet26371ce2014-10-24 00:02:55 +00003472 v8f64_info, X86Fmsub>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +00003473 defm VFMADDSUBPDZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
Adam Nemet26371ce2014-10-24 00:02:55 +00003474 v8f64_info, X86Fmaddsub>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +00003475 defm VFMSUBADDPDZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
Adam Nemet26371ce2014-10-24 00:02:55 +00003476 v8f64_info, X86Fmsubadd>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +00003477 defm VFNMADDPDZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
Adam Nemet26371ce2014-10-24 00:02:55 +00003478 v8f64_info, X86Fnmadd>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +00003479 defm VFNMSUBPDZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
Adam Nemet26371ce2014-10-24 00:02:55 +00003480 v8f64_info, X86Fnmsub>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003481}
3482
3483let Constraints = "$src1 = $dst" in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +00003484multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3485 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003486 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +00003487 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3488 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
Craig Topperedb09112014-11-25 20:11:23 +00003489 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +00003490 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3491 _.RC:$src3)))]>;
3492 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3493 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
Craig Topperedb09112014-11-25 20:11:23 +00003494 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
Adam Nemet6bddb8c2014-09-29 22:54:41 +00003495 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3496 [(set _.RC:$dst,
3497 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3498 (_.ScalarLdFrag addr:$src2))),
3499 _.RC:$src3))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003500}
3501} // Constraints = "$src1 = $dst"
3502
3503
3504let ExeDomain = SSEPackedSingle in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +00003505 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3506 v16f32_info>,
3507 EVEX_V512, EVEX_CD8<32, CD8VF>;
3508 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3509 v16f32_info>,
3510 EVEX_V512, EVEX_CD8<32, CD8VF>;
3511 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3512 v16f32_info>,
3513 EVEX_V512, EVEX_CD8<32, CD8VF>;
3514 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3515 v16f32_info>,
3516 EVEX_V512, EVEX_CD8<32, CD8VF>;
3517 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3518 v16f32_info>,
3519 EVEX_V512, EVEX_CD8<32, CD8VF>;
3520 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3521 v16f32_info>,
3522 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003523}
3524let ExeDomain = SSEPackedDouble in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +00003525 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3526 v8f64_info>,
3527 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3528 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3529 v8f64_info>,
3530 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3531 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3532 v8f64_info>,
3533 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3534 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3535 v8f64_info>,
3536 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3537 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3538 v8f64_info>,
3539 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3540 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3541 v8f64_info>,
3542 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003543}
3544
3545// Scalar FMA
3546let Constraints = "$src1 = $dst" in {
Michael Liao5bf95782014-12-04 05:20:33 +00003547multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3548 RegisterClass RC, ValueType OpVT,
3549 X86MemOperand x86memop, Operand memop,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003550 PatFrag mem_frag> {
3551 let isCommutable = 1 in
3552 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3553 (ins RC:$src1, RC:$src2, RC:$src3),
3554 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00003555 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003556 [(set RC:$dst,
3557 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3558 let mayLoad = 1 in
3559 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3560 (ins RC:$src1, RC:$src2, f128mem:$src3),
3561 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00003562 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003563 [(set RC:$dst,
3564 (OpVT (OpNode RC:$src2, RC:$src1,
3565 (mem_frag addr:$src3))))]>;
3566}
3567
3568} // Constraints = "$src1 = $dst"
3569
Elena Demikhovskycf088092013-12-11 14:31:04 +00003570defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003571 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +00003572defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003573 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +00003574defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003575 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +00003576defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003577 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +00003578defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003579 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +00003580defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003581 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +00003582defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003583 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +00003584defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003585 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3586
3587//===----------------------------------------------------------------------===//
3588// AVX-512 Scalar convert from sign integer to float/double
3589//===----------------------------------------------------------------------===//
3590
3591multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3592 X86MemOperand x86memop, string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +00003593let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003594 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00003595 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003596 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003597 let mayLoad = 1 in
3598 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3599 (ins DstRC:$src1, x86memop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00003600 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003601 EVEX_4V;
Elena Demikhovskyf404e052014-01-05 14:21:07 +00003602} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003603}
Andrew Trick15a47742013-10-09 05:11:10 +00003604let Predicates = [HasAVX512] in {
Elena Demikhovskycf088092013-12-11 14:31:04 +00003605defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003606 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +00003607defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003608 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +00003609defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003610 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +00003611defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003612 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3613
3614def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3615 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3616def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003617 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003618def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3619 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3620def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003621 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003622
3623def : Pat<(f32 (sint_to_fp GR32:$src)),
3624 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3625def : Pat<(f32 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003626 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003627def : Pat<(f64 (sint_to_fp GR32:$src)),
3628 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3629def : Pat<(f64 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003630 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3631
Elena Demikhovskycf088092013-12-11 14:31:04 +00003632defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003633 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +00003634defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003635 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +00003636defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003637 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +00003638defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003639 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3640
3641def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3642 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3643def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3644 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3645def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3646 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3647def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3648 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3649
3650def : Pat<(f32 (uint_to_fp GR32:$src)),
3651 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3652def : Pat<(f32 (uint_to_fp GR64:$src)),
3653 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3654def : Pat<(f64 (uint_to_fp GR32:$src)),
3655 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3656def : Pat<(f64 (uint_to_fp GR64:$src)),
3657 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
Andrew Trick15a47742013-10-09 05:11:10 +00003658}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003659
3660//===----------------------------------------------------------------------===//
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003661// AVX-512 Scalar convert from float/double to integer
3662//===----------------------------------------------------------------------===//
3663multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3664 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3665 string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +00003666let hasSideEffects = 0 in {
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003667 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00003668 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
Elena Demikhovskycf088092013-12-11 14:31:04 +00003669 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3670 Requires<[HasAVX512]>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003671 let mayLoad = 1 in
3672 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00003673 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
Elena Demikhovskycf088092013-12-11 14:31:04 +00003674 Requires<[HasAVX512]>;
Elena Demikhovskyf404e052014-01-05 14:21:07 +00003675} // hasSideEffects = 0
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003676}
3677let Predicates = [HasAVX512] in {
3678// Convert float/double to signed/unsigned int 32/64
3679defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +00003680 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003681 XS, EVEX_CD8<32, CD8VT1>;
3682defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +00003683 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003684 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3685defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +00003686 ssmem, sse_load_f32, "cvtss2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003687 XS, EVEX_CD8<32, CD8VT1>;
3688defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3689 int_x86_avx512_cvtss2usi64, ssmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +00003690 sse_load_f32, "cvtss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003691 EVEX_CD8<32, CD8VT1>;
3692defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +00003693 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003694 XD, EVEX_CD8<64, CD8VT1>;
3695defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +00003696 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003697 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3698defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +00003699 sdmem, sse_load_f64, "cvtsd2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003700 XD, EVEX_CD8<64, CD8VT1>;
3701defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3702 int_x86_avx512_cvtsd2usi64, sdmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +00003703 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003704 EVEX_CD8<64, CD8VT1>;
3705
Craig Topper9dd48c82014-01-02 17:28:14 +00003706let isCodeGenOnly = 1 in {
3707 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3708 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3709 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3710 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3711 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3712 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3713 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3714 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3715 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3716 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3717 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3718 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003719
Craig Topper9dd48c82014-01-02 17:28:14 +00003720 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3721 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3722 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3723 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3724 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3725 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3726 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3727 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3728 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3729 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3730 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3731 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3732} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003733
3734// Convert float/double to signed/unsigned int 32/64 with truncation
Craig Topper9dd48c82014-01-02 17:28:14 +00003735let isCodeGenOnly = 1 in {
3736 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3737 ssmem, sse_load_f32, "cvttss2si">,
3738 XS, EVEX_CD8<32, CD8VT1>;
3739 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3740 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3741 "cvttss2si">, XS, VEX_W,
3742 EVEX_CD8<32, CD8VT1>;
3743 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3744 sdmem, sse_load_f64, "cvttsd2si">, XD,
3745 EVEX_CD8<64, CD8VT1>;
3746 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3747 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3748 "cvttsd2si">, XD, VEX_W,
3749 EVEX_CD8<64, CD8VT1>;
3750 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3751 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3752 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3753 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3754 int_x86_avx512_cvttss2usi64, ssmem,
3755 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3756 EVEX_CD8<32, CD8VT1>;
3757 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3758 int_x86_avx512_cvttsd2usi,
3759 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3760 EVEX_CD8<64, CD8VT1>;
3761 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3762 int_x86_avx512_cvttsd2usi64, sdmem,
3763 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3764 EVEX_CD8<64, CD8VT1>;
3765} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003766
3767multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3768 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3769 string asm> {
3770 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00003771 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003772 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3773 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00003774 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003775 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3776}
3777
3778defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +00003779 loadf32, "cvttss2si">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003780 EVEX_CD8<32, CD8VT1>;
3781defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +00003782 loadf32, "cvttss2usi">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003783 EVEX_CD8<32, CD8VT1>;
3784defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +00003785 loadf32, "cvttss2si">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003786 EVEX_CD8<32, CD8VT1>;
3787defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +00003788 loadf32, "cvttss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003789 EVEX_CD8<32, CD8VT1>;
3790defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +00003791 loadf64, "cvttsd2si">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003792 EVEX_CD8<64, CD8VT1>;
3793defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +00003794 loadf64, "cvttsd2usi">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003795 EVEX_CD8<64, CD8VT1>;
3796defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +00003797 loadf64, "cvttsd2si">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003798 EVEX_CD8<64, CD8VT1>;
3799defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +00003800 loadf64, "cvttsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003801 EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +00003802} // HasAVX512
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +00003803//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003804// AVX-512 Convert form float to double and back
3805//===----------------------------------------------------------------------===//
Elena Demikhovskyf404e052014-01-05 14:21:07 +00003806let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003807def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3808 (ins FR32X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +00003809 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003810 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3811let mayLoad = 1 in
3812def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3813 (ins FR32X:$src1, f32mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +00003814 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003815 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3816 EVEX_CD8<32, CD8VT1>;
3817
3818// Convert scalar double to scalar single
3819def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3820 (ins FR64X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +00003821 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003822 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3823let mayLoad = 1 in
3824def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3825 (ins FR64X:$src1, f64mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +00003826 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003827 []>, EVEX_4V, VEX_LIG, VEX_W,
3828 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3829}
3830
3831def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3832 Requires<[HasAVX512]>;
3833def : Pat<(fextend (loadf32 addr:$src)),
3834 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3835
3836def : Pat<(extloadf32 addr:$src),
3837 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3838 Requires<[HasAVX512, OptForSize]>;
3839
3840def : Pat<(extloadf32 addr:$src),
3841 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3842 Requires<[HasAVX512, OptForSpeed]>;
3843
3844def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3845 Requires<[HasAVX512]>;
3846
Michael Liao5bf95782014-12-04 05:20:33 +00003847multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3848 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003849 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3850 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +00003851let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003852 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00003853 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003854 [(set DstRC:$dst,
3855 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00003856 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Craig Topperedb09112014-11-25 20:11:23 +00003857 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00003858 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003859 let mayLoad = 1 in
3860 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00003861 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003862 [(set DstRC:$dst,
3863 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +00003864} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003865}
3866
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +00003867multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00003868 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3869 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3870 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +00003871let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00003872 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00003873 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00003874 [(set DstRC:$dst,
3875 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3876 let mayLoad = 1 in
3877 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00003878 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00003879 [(set DstRC:$dst,
3880 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +00003881} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00003882}
3883
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +00003884defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003885 memopv8f64, f512mem, v8f32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +00003886 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003887 EVEX_CD8<64, CD8VF>;
3888
3889defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3890 memopv4f64, f256mem, v8f64, v8f32,
Craig Topper5ccb6172014-02-18 00:21:49 +00003891 SSEPackedDouble>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +00003892 EVEX_CD8<32, CD8VH>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003893def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3894 (VCVTPS2PDZrm addr:$src)>;
Michael Liao5bf95782014-12-04 05:20:33 +00003895
Elena Demikhovsky3629b4a2014-01-06 08:45:54 +00003896def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3897 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3898 (VCVTPD2PSZrr VR512:$src)>;
3899
3900def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3901 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3902 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003903
3904//===----------------------------------------------------------------------===//
3905// AVX-512 Vector convert from sign integer to float/double
3906//===----------------------------------------------------------------------===//
3907
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +00003908defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003909 memopv8i64, i512mem, v16f32, v16i32,
Craig Topper5ccb6172014-02-18 00:21:49 +00003910 SSEPackedSingle>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +00003911 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003912
3913defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3914 memopv4i64, i256mem, v8f64, v8i32,
3915 SSEPackedDouble>, EVEX_V512, XS,
3916 EVEX_CD8<32, CD8VH>;
3917
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +00003918defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003919 memopv16f32, f512mem, v16i32, v16f32,
3920 SSEPackedSingle>, EVEX_V512, XS,
3921 EVEX_CD8<32, CD8VF>;
3922
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +00003923defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
Michael Liao5bf95782014-12-04 05:20:33 +00003924 memopv8f64, f512mem, v8i32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +00003925 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003926 EVEX_CD8<64, CD8VF>;
3927
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +00003928defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003929 memopv16f32, f512mem, v16i32, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +00003930 SSEPackedSingle>, EVEX_V512, PS,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003931 EVEX_CD8<32, CD8VF>;
3932
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00003933// cvttps2udq (src, 0, mask-all-ones, sae-current)
3934def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3935 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3936 (VCVTTPS2UDQZrr VR512:$src)>;
3937
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +00003938defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003939 memopv8f64, f512mem, v8i32, v8f64,
Craig Topper5ccb6172014-02-18 00:21:49 +00003940 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003941 EVEX_CD8<64, CD8VF>;
Michael Liao5bf95782014-12-04 05:20:33 +00003942
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00003943// cvttpd2udq (src, 0, mask-all-ones, sae-current)
3944def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3945 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3946 (VCVTTPD2UDQZrr VR512:$src)>;
3947
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003948defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3949 memopv4i64, f256mem, v8f64, v8i32,
3950 SSEPackedDouble>, EVEX_V512, XS,
3951 EVEX_CD8<32, CD8VH>;
Michael Liao5bf95782014-12-04 05:20:33 +00003952
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +00003953defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003954 memopv16i32, f512mem, v16f32, v16i32,
3955 SSEPackedSingle>, EVEX_V512, XD,
3956 EVEX_CD8<32, CD8VF>;
3957
3958def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
Michael Liao5bf95782014-12-04 05:20:33 +00003959 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003960 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
Michael Liao5bf95782014-12-04 05:20:33 +00003961
Elena Demikhovsky3dcfbdf2014-04-08 07:24:02 +00003962def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3963 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3964 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3965
3966def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3967 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3968 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
Michael Liao5bf95782014-12-04 05:20:33 +00003969
Elena Demikhovsky3dcfbdf2014-04-08 07:24:02 +00003970def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3971 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3972 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003973
Cameron McInallyf10a7c92014-06-18 14:04:37 +00003974def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3975 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3976 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3977
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00003978def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +00003979 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00003980 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +00003981def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3982 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3983 (VCVTDQ2PDZrr VR256X:$src)>;
3984def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3985 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3986 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3987def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3988 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3989 (VCVTUDQ2PDZrr VR256X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00003990
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00003991multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3992 RegisterClass DstRC, PatFrag mem_frag,
3993 X86MemOperand x86memop, Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +00003994let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00003995 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00003996 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00003997 [], d>, EVEX;
3998 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Craig Topperedb09112014-11-25 20:11:23 +00003999 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004000 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004001 let mayLoad = 1 in
4002 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00004003 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004004 [], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +00004005} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004006}
4007
4008defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
Craig Topperae11aed2014-01-14 07:41:20 +00004009 memopv16f32, f512mem, SSEPackedSingle>, PD,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004010 EVEX_V512, EVEX_CD8<32, CD8VF>;
4011defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4012 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4013 EVEX_V512, EVEX_CD8<64, CD8VF>;
4014
4015def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4016 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4017 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4018
4019def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4020 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4021 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4022
4023defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4024 memopv16f32, f512mem, SSEPackedSingle>,
Craig Topper5ccb6172014-02-18 00:21:49 +00004025 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004026defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4027 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
Craig Topper5ccb6172014-02-18 00:21:49 +00004028 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004029
4030def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4031 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4032 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4033
4034def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4035 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4036 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004037
4038let Predicates = [HasAVX512] in {
4039 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4040 (VCVTPD2PSZrm addr:$src)>;
4041 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4042 (VCVTPS2PDZrm addr:$src)>;
4043}
4044
Elena Demikhovskydd0794e2013-10-24 07:16:35 +00004045//===----------------------------------------------------------------------===//
4046// Half precision conversion instructions
4047//===----------------------------------------------------------------------===//
Elena Demikhovskya30e4372014-02-05 07:05:03 +00004048multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4049 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +00004050 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4051 "vcvtph2ps\t{$src, $dst|$dst, $src}",
Elena Demikhovskya30e4372014-02-05 07:05:03 +00004052 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +00004053 let hasSideEffects = 0, mayLoad = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +00004054 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4055 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4056}
4057
Elena Demikhovskya30e4372014-02-05 07:05:03 +00004058multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4059 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +00004060 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4061 (ins srcRC:$src1, i32i8imm:$src2),
Craig Topperedb09112014-11-25 20:11:23 +00004062 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskya30e4372014-02-05 07:05:03 +00004063 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +00004064 let hasSideEffects = 0, mayStore = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +00004065 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4066 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
Craig Topperedb09112014-11-25 20:11:23 +00004067 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +00004068}
4069
Elena Demikhovskya30e4372014-02-05 07:05:03 +00004070defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +00004071 EVEX_CD8<32, CD8VH>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +00004072defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +00004073 EVEX_CD8<32, CD8VH>;
4074
Elena Demikhovskya30e4372014-02-05 07:05:03 +00004075def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4076 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4077 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4078
4079def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4080 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4081 (VCVTPH2PSZrr VR256X:$src)>;
4082
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004083let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4084 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
Craig Topper5ccb6172014-02-18 00:21:49 +00004085 "ucomiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004086 EVEX_CD8<32, CD8VT1>;
4087 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
Craig Topperae11aed2014-01-14 07:41:20 +00004088 "ucomisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004089 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4090 let Pattern = []<dag> in {
4091 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
Craig Topper5ccb6172014-02-18 00:21:49 +00004092 "comiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004093 EVEX_CD8<32, CD8VT1>;
4094 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
Craig Topperae11aed2014-01-14 07:41:20 +00004095 "comisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004096 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4097 }
Craig Topper9dd48c82014-01-02 17:28:14 +00004098 let isCodeGenOnly = 1 in {
4099 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +00004100 load, "ucomiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +00004101 EVEX_CD8<32, CD8VT1>;
4102 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +00004103 load, "ucomisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +00004104 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004105
Craig Topper9dd48c82014-01-02 17:28:14 +00004106 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +00004107 load, "comiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +00004108 EVEX_CD8<32, CD8VT1>;
4109 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +00004110 load, "comisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +00004111 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4112 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004113}
Michael Liao5bf95782014-12-04 05:20:33 +00004114
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004115/// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4116multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4117 X86MemOperand x86memop> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004118 let hasSideEffects = 0 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004119 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4120 (ins RC:$src1, RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004121 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00004122 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004123 let mayLoad = 1 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004124 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4125 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004126 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00004127 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004128 }
4129}
4130}
4131
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004132defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4133 EVEX_CD8<32, CD8VT1>;
4134defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4135 VEX_W, EVEX_CD8<64, CD8VT1>;
4136defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4137 EVEX_CD8<32, CD8VT1>;
4138defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4139 VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004140
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004141def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4142 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4143 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4144 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004145
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004146def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4147 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4148 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4149 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +00004150
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004151def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4152 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4153 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4154 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +00004155
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004156def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4157 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4158 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4159 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +00004160
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004161/// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4162multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanov3e534c92014-10-28 16:37:13 +00004163 X86VectorVTInfo _> {
4164 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4165 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4166 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4167 let mayLoad = 1 in {
4168 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4169 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4170 (OpNode (_.FloatVT
4171 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4172 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4173 (ins _.ScalarMemOp:$src), OpcodeStr,
4174 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4175 (OpNode (_.FloatVT
4176 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4177 EVEX, T8PD, EVEX_B;
4178 }
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004179}
Robert Khasanov3e534c92014-10-28 16:37:13 +00004180
4181multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4182 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4183 EVEX_V512, EVEX_CD8<32, CD8VF>;
4184 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4185 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4186
4187 // Define only if AVX512VL feature is present.
4188 let Predicates = [HasVLX] in {
4189 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4190 OpNode, v4f32x_info>,
4191 EVEX_V128, EVEX_CD8<32, CD8VF>;
4192 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4193 OpNode, v8f32x_info>,
4194 EVEX_V256, EVEX_CD8<32, CD8VF>;
4195 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4196 OpNode, v2f64x_info>,
4197 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4198 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4199 OpNode, v4f64x_info>,
4200 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4201 }
4202}
4203
4204defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4205defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004206
4207def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4208 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4209 (VRSQRT14PSZr VR512:$src)>;
4210def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4211 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4212 (VRSQRT14PDZr VR512:$src)>;
4213
4214def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4215 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4216 (VRCP14PSZr VR512:$src)>;
4217def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4218 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4219 (VRCP14PDZr VR512:$src)>;
4220
4221/// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
Elena Demikhovsky905a5a62014-11-26 10:46:49 +00004222multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4223 SDNode OpNode> {
4224
4225 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4226 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4227 "$src2, $src1", "$src1, $src2",
4228 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4229 (i32 FROUND_CURRENT))>;
4230
4231 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4232 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4233 "$src2, $src1", "$src1, $src2",
4234 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4235 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4236
4237 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4238 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4239 "$src2, $src1", "$src1, $src2",
4240 (OpNode (_.VT _.RC:$src1),
4241 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4242 (i32 FROUND_CURRENT))>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +00004243}
4244
Elena Demikhovsky905a5a62014-11-26 10:46:49 +00004245multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4246 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4247 EVEX_CD8<32, CD8VT1>;
4248 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4249 EVEX_CD8<64, CD8VT1>, VEX_W;
4250}
Elena Demikhovskya3a71402013-10-09 08:16:14 +00004251
Elena Demikhovsky905a5a62014-11-26 10:46:49 +00004252let hasSideEffects = 0, Predicates = [HasERI] in {
4253 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4254 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4255}
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004256/// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
Elena Demikhovskybe8808d2014-11-12 07:31:03 +00004257
4258multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4259 SDNode OpNode> {
4260
4261 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4262 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4263 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4264
4265 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4266 (ins _.RC:$src), OpcodeStr,
4267 "$src", "$src",
Elena Demikhovsky905a5a62014-11-26 10:46:49 +00004268 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)),
4269 "{sae}">, EVEX_B;
Elena Demikhovskybe8808d2014-11-12 07:31:03 +00004270
4271 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4272 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4273 (OpNode (_.FloatVT
Elena Demikhovsky905a5a62014-11-26 10:46:49 +00004274 (bitconvert (_.LdFrag addr:$src))),
4275 (i32 FROUND_CURRENT))>;
Elena Demikhovskybe8808d2014-11-12 07:31:03 +00004276
4277 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4278 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4279 (OpNode (_.FloatVT
4280 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4281 (i32 FROUND_CURRENT))>, EVEX_B;
Elena Demikhovskya3a71402013-10-09 08:16:14 +00004282}
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004283
Elena Demikhovskybe8808d2014-11-12 07:31:03 +00004284multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4285 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4286 EVEX_CD8<32, CD8VF>;
4287 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4288 VEX_W, EVEX_CD8<32, CD8VF>;
4289}
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004290
Elena Demikhovskybe8808d2014-11-12 07:31:03 +00004291let Predicates = [HasERI], hasSideEffects = 0 in {
Michael Liao5bf95782014-12-04 05:20:33 +00004292
Elena Demikhovskybe8808d2014-11-12 07:31:03 +00004293 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4294 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4295 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4296}
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004297
Robert Khasanoveb126392014-10-28 18:15:20 +00004298multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4299 SDNode OpNode, X86VectorVTInfo _>{
Robert Khasanov1cf354c2014-10-28 18:22:41 +00004300 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
Robert Khasanoveb126392014-10-28 18:15:20 +00004301 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4302 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4303 let mayLoad = 1 in {
Robert Khasanov1cf354c2014-10-28 18:22:41 +00004304 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
Robert Khasanoveb126392014-10-28 18:15:20 +00004305 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4306 (OpNode (_.FloatVT
4307 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004308
Robert Khasanov1cf354c2014-10-28 18:22:41 +00004309 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
Robert Khasanoveb126392014-10-28 18:15:20 +00004310 (ins _.ScalarMemOp:$src), OpcodeStr,
4311 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4312 (OpNode (_.FloatVT
4313 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4314 EVEX, EVEX_B;
4315 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004316}
4317
4318multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4319 Intrinsic F32Int, Intrinsic F64Int,
4320 OpndItins itins_s, OpndItins itins_d> {
4321 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4322 (ins FR32X:$src1, FR32X:$src2),
4323 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +00004324 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004325 [], itins_s.rr>, XS, EVEX_4V;
Craig Topper9dd48c82014-01-02 17:28:14 +00004326 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004327 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4328 (ins VR128X:$src1, VR128X:$src2),
4329 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +00004330 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Michael Liao5bf95782014-12-04 05:20:33 +00004331 [(set VR128X:$dst,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004332 (F32Int VR128X:$src1, VR128X:$src2))],
4333 itins_s.rr>, XS, EVEX_4V;
4334 let mayLoad = 1 in {
4335 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4336 (ins FR32X:$src1, f32mem:$src2),
4337 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +00004338 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004339 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +00004340 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004341 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4342 (ins VR128X:$src1, ssmem:$src2),
4343 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +00004344 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Michael Liao5bf95782014-12-04 05:20:33 +00004345 [(set VR128X:$dst,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004346 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4347 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4348 }
4349 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4350 (ins FR64X:$src1, FR64X:$src2),
4351 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +00004352 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004353 XD, EVEX_4V, VEX_W;
Craig Topper9dd48c82014-01-02 17:28:14 +00004354 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004355 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4356 (ins VR128X:$src1, VR128X:$src2),
4357 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +00004358 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Michael Liao5bf95782014-12-04 05:20:33 +00004359 [(set VR128X:$dst,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004360 (F64Int VR128X:$src1, VR128X:$src2))],
4361 itins_s.rr>, XD, EVEX_4V, VEX_W;
4362 let mayLoad = 1 in {
4363 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4364 (ins FR64X:$src1, f64mem:$src2),
4365 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +00004366 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004367 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +00004368 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004369 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4370 (ins VR128X:$src1, sdmem:$src2),
4371 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +00004372 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Michael Liao5bf95782014-12-04 05:20:33 +00004373 [(set VR128X:$dst,
4374 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004375 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4376 }
4377}
4378
Robert Khasanoveb126392014-10-28 18:15:20 +00004379multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4380 SDNode OpNode> {
4381 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4382 v16f32_info>,
4383 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4384 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4385 v8f64_info>,
4386 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4387 // Define only if AVX512VL feature is present.
4388 let Predicates = [HasVLX] in {
4389 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4390 OpNode, v4f32x_info>,
4391 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4392 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4393 OpNode, v8f32x_info>,
4394 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4395 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4396 OpNode, v2f64x_info>,
4397 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4398 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4399 OpNode, v4f64x_info>,
4400 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4401 }
4402}
4403
4404defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004405
Michael Liao5bf95782014-12-04 05:20:33 +00004406defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4407 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
Robert Khasanoveb126392014-10-28 18:15:20 +00004408 SSE_SQRTSS, SSE_SQRTSD>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004409
Elena Demikhovskya3a71402013-10-09 08:16:14 +00004410let Predicates = [HasAVX512] in {
Elena Demikhovskyf1648592014-07-22 11:07:31 +00004411 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4412 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
Robert Khasanov1cf354c2014-10-28 18:22:41 +00004413 (VSQRTPSZr VR512:$src1)>;
Elena Demikhovskyf1648592014-07-22 11:07:31 +00004414 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4415 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
Robert Khasanov1cf354c2014-10-28 18:22:41 +00004416 (VSQRTPDZr VR512:$src1)>;
Michael Liao5bf95782014-12-04 05:20:33 +00004417
Elena Demikhovskya3a71402013-10-09 08:16:14 +00004418 def : Pat<(f32 (fsqrt FR32X:$src)),
4419 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4420 def : Pat<(f32 (fsqrt (load addr:$src))),
4421 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4422 Requires<[OptForSize]>;
4423 def : Pat<(f64 (fsqrt FR64X:$src)),
4424 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4425 def : Pat<(f64 (fsqrt (load addr:$src))),
4426 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4427 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004428
Elena Demikhovskya3a71402013-10-09 08:16:14 +00004429 def : Pat<(f32 (X86frsqrt FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004430 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +00004431 def : Pat<(f32 (X86frsqrt (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004432 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +00004433 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004434
Elena Demikhovskya3a71402013-10-09 08:16:14 +00004435 def : Pat<(f32 (X86frcp FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004436 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +00004437 def : Pat<(f32 (X86frcp (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +00004438 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +00004439 Requires<[OptForSize]>;
4440
4441 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4442 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4443 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4444 VR128X)>;
4445 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4446 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4447
4448 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4449 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4450 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4451 VR128X)>;
4452 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4453 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4454}
4455
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004456
4457multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4458 X86MemOperand x86memop, RegisterClass RC,
4459 PatFrag mem_frag32, PatFrag mem_frag64,
4460 Intrinsic V4F32Int, Intrinsic V2F64Int,
4461 CD8VForm VForm> {
4462let ExeDomain = SSEPackedSingle in {
4463 // Intrinsic operation, reg.
4464 // Vector intrinsic operation, reg
4465 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4466 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4467 !strconcat(OpcodeStr,
4468 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4469 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4470
4471 // Vector intrinsic operation, mem
4472 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4473 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4474 !strconcat(OpcodeStr,
4475 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4476 [(set RC:$dst,
4477 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4478 EVEX_CD8<32, VForm>;
4479} // ExeDomain = SSEPackedSingle
4480
4481let ExeDomain = SSEPackedDouble in {
4482 // Vector intrinsic operation, reg
4483 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4484 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4485 !strconcat(OpcodeStr,
4486 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4487 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4488
4489 // Vector intrinsic operation, mem
4490 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4491 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4492 !strconcat(OpcodeStr,
4493 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4494 [(set RC:$dst,
4495 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4496 EVEX_CD8<64, VForm>;
4497} // ExeDomain = SSEPackedDouble
4498}
4499
4500multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4501 string OpcodeStr,
4502 Intrinsic F32Int,
4503 Intrinsic F64Int> {
4504let ExeDomain = GenericDomain in {
4505 // Operation, reg.
4506 let hasSideEffects = 0 in
4507 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4508 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4509 !strconcat(OpcodeStr,
4510 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4511 []>;
4512
4513 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +00004514 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004515 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4516 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4517 !strconcat(OpcodeStr,
4518 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4519 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4520
4521 // Intrinsic operation, mem.
4522 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4523 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4524 !strconcat(OpcodeStr,
4525 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Michael Liao5bf95782014-12-04 05:20:33 +00004526 [(set VR128X:$dst, (F32Int VR128X:$src1,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004527 sse_load_f32:$src2, imm:$src3))]>,
4528 EVEX_CD8<32, CD8VT1>;
4529
4530 // Operation, reg.
4531 let hasSideEffects = 0 in
4532 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4533 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4534 !strconcat(OpcodeStr,
4535 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4536 []>, VEX_W;
4537
4538 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +00004539 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004540 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4541 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4542 !strconcat(OpcodeStr,
4543 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4544 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4545 VEX_W;
4546
4547 // Intrinsic operation, mem.
4548 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4549 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4550 !strconcat(OpcodeStr,
4551 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4552 [(set VR128X:$dst,
4553 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4554 VEX_W, EVEX_CD8<64, CD8VT1>;
4555} // ExeDomain = GenericDomain
4556}
4557
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004558multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4559 X86MemOperand x86memop, RegisterClass RC,
4560 PatFrag mem_frag, Domain d> {
4561let ExeDomain = d in {
4562 // Intrinsic operation, reg.
4563 // Vector intrinsic operation, reg
4564 def r : AVX512AIi8<opc, MRMSrcReg,
4565 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4566 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00004567 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004568 []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004569
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004570 // Vector intrinsic operation, mem
4571 def m : AVX512AIi8<opc, MRMSrcMem,
4572 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4573 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00004574 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004575 []>, EVEX;
4576} // ExeDomain
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004577}
4578
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004579
4580defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4581 memopv16f32, SSEPackedSingle>, EVEX_V512,
4582 EVEX_CD8<32, CD8VF>;
4583
4584def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +00004585 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004586 FROUND_CURRENT)),
4587 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4588
4589
4590defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4591 memopv8f64, SSEPackedDouble>, EVEX_V512,
4592 VEX_W, EVEX_CD8<64, CD8VF>;
4593
4594def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +00004595 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004596 FROUND_CURRENT)),
4597 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4598
4599multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4600 Operand x86memop, RegisterClass RC, Domain d> {
4601let ExeDomain = d in {
4602 def r : AVX512AIi8<opc, MRMSrcReg,
4603 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4604 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00004605 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004606 []>, EVEX_4V;
4607
4608 def m : AVX512AIi8<opc, MRMSrcMem,
4609 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4610 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00004611 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004612 []>, EVEX_4V;
4613} // ExeDomain
4614}
4615
4616defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4617 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
Michael Liao5bf95782014-12-04 05:20:33 +00004618
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004619defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4620 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4621
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004622def : Pat<(ffloor FR32X:$src),
4623 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4624def : Pat<(f64 (ffloor FR64X:$src)),
4625 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4626def : Pat<(f32 (fnearbyint FR32X:$src)),
4627 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4628def : Pat<(f64 (fnearbyint FR64X:$src)),
4629 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4630def : Pat<(f32 (fceil FR32X:$src)),
4631 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4632def : Pat<(f64 (fceil FR64X:$src)),
4633 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4634def : Pat<(f32 (frint FR32X:$src)),
4635 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4636def : Pat<(f64 (frint FR64X:$src)),
4637 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4638def : Pat<(f32 (ftrunc FR32X:$src)),
4639 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4640def : Pat<(f64 (ftrunc FR64X:$src)),
4641 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4642
4643def : Pat<(v16f32 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004644 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004645def : Pat<(v16f32 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004646 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004647def : Pat<(v16f32 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004648 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004649def : Pat<(v16f32 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004650 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004651def : Pat<(v16f32 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004652 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004653
4654def : Pat<(v8f64 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004655 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004656def : Pat<(v8f64 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004657 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004658def : Pat<(v8f64 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004659 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004660def : Pat<(v8f64 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004661 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004662def : Pat<(v8f64 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +00004663 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004664
4665//-------------------------------------------------
4666// Integer truncate and extend operations
4667//-------------------------------------------------
4668
4669multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4670 RegisterClass dstRC, RegisterClass srcRC,
4671 RegisterClass KRC, X86MemOperand x86memop> {
4672 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4673 (ins srcRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00004674 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004675 []>, EVEX;
4676
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004677 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4678 (ins KRC:$mask, srcRC:$src),
4679 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00004680 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004681 []>, EVEX, EVEX_K;
4682
4683 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004684 (ins KRC:$mask, srcRC:$src),
4685 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00004686 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004687 []>, EVEX, EVEX_KZ;
4688
4689 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00004690 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004691 []>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004692
4693 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4694 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00004695 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004696 []>, EVEX, EVEX_K;
4697
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004698}
Michael Liao5bf95782014-12-04 05:20:33 +00004699defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004700 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4701defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4702 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4703defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4704 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4705defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4706 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4707defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4708 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4709defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4710 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4711defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4712 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4713defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4714 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4715defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4716 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4717defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4718 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4719defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4720 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4721defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4722 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4723defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4724 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4725defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4726 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4727defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4728 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4729
4730def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4731def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4732def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4733def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4734def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4735
4736def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004737 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004738def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004739 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004740def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004741 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004742def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004743 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004744
4745
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004746multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4747 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4748 PatFrag mem_frag, X86MemOperand x86memop,
4749 ValueType OpVT, ValueType InVT> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004750
4751 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4752 (ins SrcRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00004753 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004754 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004755
4756 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4757 (ins KRC:$mask, SrcRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00004758 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004759 []>, EVEX, EVEX_K;
4760
4761 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4762 (ins KRC:$mask, SrcRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00004763 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004764 []>, EVEX, EVEX_KZ;
4765
4766 let mayLoad = 1 in {
4767 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004768 (ins x86memop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00004769 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004770 [(set DstRC:$dst,
4771 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4772 EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004773
4774 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4775 (ins KRC:$mask, x86memop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00004776 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004777 []>,
4778 EVEX, EVEX_K;
4779
4780 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4781 (ins KRC:$mask, x86memop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00004782 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004783 []>,
4784 EVEX, EVEX_KZ;
4785 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004786}
4787
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004788defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004789 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4790 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004791defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004792 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4793 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004794defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004795 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4796 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004797defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004798 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4799 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004800defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004801 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4802 EVEX_CD8<32, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004803
4804defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004805 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4806 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004807defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004808 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4809 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004810defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004811 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4812 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004813defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004814 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4815 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +00004816defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004817 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4818 EVEX_CD8<32, CD8VH>;
4819
4820//===----------------------------------------------------------------------===//
4821// GATHER - SCATTER Operations
4822
4823multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4824 RegisterClass RC, X86MemOperand memop> {
4825let mayLoad = 1,
4826 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4827 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4828 (ins RC:$src1, KRC:$mask, memop:$src2),
4829 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00004830 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004831 []>, EVEX, EVEX_K;
4832}
Cameron McInally45325962014-03-26 13:50:50 +00004833
4834let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004835defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4836 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004837defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4838 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +00004839}
4840
4841let ExeDomain = SSEPackedSingle in {
4842defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4843 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004844defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4845 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +00004846}
Michael Liao5bf95782014-12-04 05:20:33 +00004847
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004848defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4849 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4850defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4851 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4852
4853defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4854 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4855defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4856 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4857
4858multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4859 RegisterClass RC, X86MemOperand memop> {
4860let mayStore = 1, Constraints = "$mask = $mask_wb" in
4861 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4862 (ins memop:$dst, KRC:$mask, RC:$src2),
4863 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00004864 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004865 []>, EVEX, EVEX_K;
4866}
4867
Cameron McInally45325962014-03-26 13:50:50 +00004868let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004869defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4870 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004871defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4872 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +00004873}
4874
4875let ExeDomain = SSEPackedSingle in {
4876defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4877 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004878defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4879 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +00004880}
4881
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004882defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4883 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4884defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4885 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4886
4887defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4888 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4889defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4890 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4891
Elena Demikhovsky8e8fde82014-05-12 07:18:51 +00004892// prefetch
4893multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4894 RegisterClass KRC, X86MemOperand memop> {
4895 let Predicates = [HasPFI], hasSideEffects = 1 in
4896 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00004897 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
Elena Demikhovsky8e8fde82014-05-12 07:18:51 +00004898 []>, EVEX, EVEX_K;
4899}
4900
4901defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4902 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4903
4904defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4905 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4906
4907defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4908 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4909
4910defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4911 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Michael Liao5bf95782014-12-04 05:20:33 +00004912
Elena Demikhovsky8e8fde82014-05-12 07:18:51 +00004913defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4914 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4915
4916defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4917 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4918
4919defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4920 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4921
4922defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4923 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4924
4925defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4926 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4927
4928defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4929 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4930
4931defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4932 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4933
4934defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4935 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4936
4937defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4938 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4939
4940defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4941 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4942
4943defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4944 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4945
4946defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4947 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004948//===----------------------------------------------------------------------===//
4949// VSHUFPS - VSHUFPD Operations
4950
4951multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4952 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4953 Domain d> {
4954 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4955 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4956 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00004957 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004958 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4959 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +00004960 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004961 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4962 (ins RC:$src1, RC:$src2, i8imm:$src3),
4963 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00004964 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004965 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4966 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +00004967 EVEX_4V, Sched<[WriteShuffle]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004968}
4969
4970defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +00004971 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004972defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
Craig Topperae11aed2014-01-14 07:41:20 +00004973 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004974
Elena Demikhovsky462a2d22013-10-06 06:11:18 +00004975def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4976 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4977def : Pat<(v16i32 (X86Shufp VR512:$src1,
4978 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4979 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4980
4981def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4982 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4983def : Pat<(v8i64 (X86Shufp VR512:$src1,
4984 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4985 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00004986
Adam Nemet5ed17da2014-08-21 19:50:07 +00004987multiclass avx512_valign<X86VectorVTInfo _> {
Adam Nemet34801422014-10-08 23:25:39 +00004988 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
Adam Nemet5ed17da2014-08-21 19:50:07 +00004989 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4990 "valign"##_.Suffix,
Adam Nemet2e2537f2014-08-07 17:53:55 +00004991 "$src3, $src2, $src1", "$src1, $src2, $src3",
Adam Nemet5ed17da2014-08-21 19:50:07 +00004992 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
Adam Nemet6bddb8c2014-09-29 22:54:41 +00004993 (i8 imm:$src3)))>,
Adam Nemet2e2537f2014-08-07 17:53:55 +00004994 AVX512AIi8Base, EVEX_4V;
Adam Nemetfd2161b2014-08-05 17:23:04 +00004995
Adam Nemetf92139d2014-08-05 17:22:50 +00004996 // Also match valign of packed floats.
Adam Nemet5ed17da2014-08-21 19:50:07 +00004997 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4998 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
Adam Nemetf92139d2014-08-05 17:22:50 +00004999
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +00005000 let mayLoad = 1 in
Adam Nemet5ed17da2014-08-21 19:50:07 +00005001 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5002 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
5003 !strconcat("valign"##_.Suffix,
Craig Topperedb09112014-11-25 20:11:23 +00005004 "\t{$src3, $src2, $src1, $dst|"
Adam Nemet1c752d82014-08-05 17:22:47 +00005005 "$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00005006 []>, EVEX_4V;
5007}
Adam Nemet5ed17da2014-08-21 19:50:07 +00005008defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5009defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00005010
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00005011// Helper fragments to match sext vXi1 to vXiY.
5012def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5013def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5014
5015multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5016 RegisterClass KRC, RegisterClass RC,
5017 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5018 string BrdcstStr> {
5019 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00005020 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00005021 []>, EVEX;
5022 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00005023 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00005024 []>, EVEX, EVEX_K;
5025 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5026 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00005027 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00005028 []>, EVEX, EVEX_KZ;
5029 let mayLoad = 1 in {
5030 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5031 (ins x86memop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00005032 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00005033 []>, EVEX;
5034 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5035 (ins KRC:$mask, x86memop:$src),
5036 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00005037 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00005038 []>, EVEX, EVEX_K;
5039 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5040 (ins KRC:$mask, x86memop:$src),
5041 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00005042 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00005043 []>, EVEX, EVEX_KZ;
5044 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5045 (ins x86scalar_mop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00005046 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00005047 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5048 []>, EVEX, EVEX_B;
5049 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5050 (ins KRC:$mask, x86scalar_mop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00005051 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00005052 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5053 []>, EVEX, EVEX_B, EVEX_K;
5054 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5055 (ins KRC:$mask, x86scalar_mop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00005056 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00005057 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5058 BrdcstStr, "}"),
5059 []>, EVEX, EVEX_B, EVEX_KZ;
5060 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00005061}
5062
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00005063defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5064 i512mem, i32mem, "{1to16}">, EVEX_V512,
5065 EVEX_CD8<32, CD8VF>;
5066defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5067 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5068 EVEX_CD8<64, CD8VF>;
5069
5070def : Pat<(xor
5071 (bc_v16i32 (v16i1sextv16i32)),
5072 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5073 (VPABSDZrr VR512:$src)>;
5074def : Pat<(xor
5075 (bc_v8i64 (v8i1sextv8i64)),
5076 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5077 (VPABSQZrr VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +00005078
Elena Demikhovsky172a27c2014-01-08 10:54:22 +00005079def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5080 (v16i32 immAllZerosV), (i16 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00005081 (VPABSDZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +00005082def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5083 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +00005084 (VPABSQZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +00005085
Michael Liao5bf95782014-12-04 05:20:33 +00005086multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
Elena Demikhovsky6270b382013-12-10 11:58:35 +00005087 RegisterClass RC, RegisterClass KRC,
5088 X86MemOperand x86memop,
5089 X86MemOperand x86scalar_mop, string BrdcstStr> {
Elena Demikhovskydacddb02013-11-03 13:46:31 +00005090 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5091 (ins RC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00005092 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +00005093 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +00005094 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5095 (ins x86memop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00005096 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +00005097 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +00005098 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5099 (ins x86scalar_mop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00005100 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +00005101 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5102 []>, EVEX, EVEX_B;
5103 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5104 (ins KRC:$mask, RC:$src),
5105 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00005106 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +00005107 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +00005108 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5109 (ins KRC:$mask, x86memop:$src),
5110 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00005111 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +00005112 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +00005113 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5114 (ins KRC:$mask, x86scalar_mop:$src),
Craig Topperedb09112014-11-25 20:11:23 +00005115 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +00005116 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5117 BrdcstStr, "}"),
5118 []>, EVEX, EVEX_KZ, EVEX_B;
Michael Liao5bf95782014-12-04 05:20:33 +00005119
Elena Demikhovskydacddb02013-11-03 13:46:31 +00005120 let Constraints = "$src1 = $dst" in {
5121 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5122 (ins RC:$src1, KRC:$mask, RC:$src2),
5123 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00005124 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +00005125 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +00005126 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5127 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5128 !strconcat(OpcodeStr,
Craig Topperedb09112014-11-25 20:11:23 +00005129 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +00005130 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +00005131 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5132 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
Craig Topperedb09112014-11-25 20:11:23 +00005133 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +00005134 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5135 []>, EVEX, EVEX_K, EVEX_B;
5136 }
5137}
5138
5139let Predicates = [HasCDI] in {
5140defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +00005141 i512mem, i32mem, "{1to16}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +00005142 EVEX_V512, EVEX_CD8<32, CD8VF>;
5143
Elena Demikhovsky6270b382013-12-10 11:58:35 +00005144
Elena Demikhovskydacddb02013-11-03 13:46:31 +00005145defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +00005146 i512mem, i64mem, "{1to8}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +00005147 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky6270b382013-12-10 11:58:35 +00005148
Elena Demikhovskydacddb02013-11-03 13:46:31 +00005149}
Elena Demikhovsky6270b382013-12-10 11:58:35 +00005150
5151def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5152 GR16:$mask),
5153 (VPCONFLICTDrrk VR512:$src1,
5154 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5155
5156def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5157 GR8:$mask),
5158 (VPCONFLICTQrrk VR512:$src1,
5159 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +00005160
Cameron McInally5d1b7b92014-06-11 12:54:45 +00005161let Predicates = [HasCDI] in {
5162defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5163 i512mem, i32mem, "{1to16}">,
5164 EVEX_V512, EVEX_CD8<32, CD8VF>;
5165
5166
5167defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5168 i512mem, i64mem, "{1to8}">,
5169 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5170
5171}
5172
5173def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5174 GR16:$mask),
5175 (VPLZCNTDrrk VR512:$src1,
5176 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5177
5178def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5179 GR8:$mask),
5180 (VPLZCNTQrrk VR512:$src1,
5181 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5182
Cameron McInally0d0489c2014-06-16 14:12:28 +00005183def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5184 (VPLZCNTDrm addr:$src)>;
5185def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5186 (VPLZCNTDrr VR512:$src)>;
5187def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5188 (VPLZCNTQrm addr:$src)>;
5189def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5190 (VPLZCNTQrr VR512:$src)>;
5191
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +00005192def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5193def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5194def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
Elena Demikhovskyacc5c9e2014-04-22 14:13:10 +00005195
5196def : Pat<(store VK1:$src, addr:$dst),
5197 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5198
5199def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5200 (truncstore node:$val, node:$ptr), [{
5201 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5202}]>;
5203
5204def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5205 (MOV8mr addr:$dst, GR8:$src)>;
5206
Elena Demikhovsky44bf0632014-10-05 14:11:08 +00005207multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5208def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
Craig Topperedb09112014-11-25 20:11:23 +00005209 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
Elena Demikhovsky44bf0632014-10-05 14:11:08 +00005210 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5211}
Michael Liao5bf95782014-12-04 05:20:33 +00005212
Elena Demikhovsky44bf0632014-10-05 14:11:08 +00005213multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5214 string OpcodeStr, Predicate prd> {
5215let Predicates = [prd] in
5216 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5217
5218 let Predicates = [prd, HasVLX] in {
5219 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5220 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5221 }
5222}
5223
5224multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5225 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5226 HasBWI>;
5227 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5228 HasBWI>, VEX_W;
5229 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5230 HasDQI>;
5231 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5232 HasDQI>, VEX_W;
5233}
Michael Liao5bf95782014-12-04 05:20:33 +00005234
Elena Demikhovsky44bf0632014-10-05 14:11:08 +00005235defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;