Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
| 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 4 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 6 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the |
| 10 | * "Software"), to deal in the Software without restriction, including |
| 11 | * without limitation the rights to use, copy, modify, merge, publish, |
| 12 | * distribute, sub license, and/or sell copies of the Software, and to |
| 13 | * permit persons to whom the Software is furnished to do so, subject to |
| 14 | * the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice (including the |
| 17 | * next paragraph) shall be included in all copies or substantial portions |
| 18 | * of the Software. |
| 19 | * |
| 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 27 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 28 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 30 | #include <linux/device.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 31 | #include <drm/drmP.h> |
| 32 | #include <drm/i915_drm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | #include "i915_drv.h" |
Chris Wilson | 990bbda | 2012-07-02 11:51:02 -0300 | [diff] [blame] | 34 | #include "i915_trace.h" |
Kenneth Graunke | f49f058 | 2010-09-11 01:19:14 -0700 | [diff] [blame] | 35 | #include "intel_drv.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 37 | #include <linux/console.h> |
Paul Gortmaker | e0cd360 | 2011-08-30 11:04:30 -0400 | [diff] [blame] | 38 | #include <linux/module.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 39 | #include <drm/drm_crtc_helper.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 40 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 41 | static int i915_modeset __read_mostly = -1; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 42 | module_param_named(modeset, i915_modeset, int, 0400); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 43 | MODULE_PARM_DESC(modeset, |
| 44 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " |
| 45 | "1=on, -1=force vga console preference [default])"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 46 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 47 | unsigned int i915_fbpercrtc __always_unused = 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 48 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 50 | int i915_panel_ignore_lid __read_mostly = 0; |
Chris Wilson | fca8740 | 2011-02-17 13:44:48 +0000 | [diff] [blame] | 51 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 52 | MODULE_PARM_DESC(panel_ignore_lid, |
| 53 | "Override lid status (0=autodetect [default], 1=lid open, " |
| 54 | "-1=lid closed)"); |
Chris Wilson | fca8740 | 2011-02-17 13:44:48 +0000 | [diff] [blame] | 55 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 56 | unsigned int i915_powersave __read_mostly = 1; |
Chris Wilson | 0aa9927 | 2010-11-02 09:20:50 +0000 | [diff] [blame] | 57 | module_param_named(powersave, i915_powersave, int, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 58 | MODULE_PARM_DESC(powersave, |
| 59 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 60 | |
Eugeni Dodonov | f45b555 | 2011-12-09 17:16:37 -0800 | [diff] [blame] | 61 | int i915_semaphores __read_mostly = -1; |
Chris Wilson | a1656b9 | 2011-03-04 18:48:03 +0000 | [diff] [blame] | 62 | module_param_named(semaphores, i915_semaphores, int, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 63 | MODULE_PARM_DESC(semaphores, |
Eugeni Dodonov | f45b555 | 2011-12-09 17:16:37 -0800 | [diff] [blame] | 64 | "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); |
Chris Wilson | a1656b9 | 2011-03-04 18:48:03 +0000 | [diff] [blame] | 65 | |
Keith Packard | c0f372b3 | 2011-11-16 22:24:52 -0800 | [diff] [blame] | 66 | int i915_enable_rc6 __read_mostly = -1; |
Jesse Barnes | f57f9c1 | 2012-04-11 09:39:02 -0700 | [diff] [blame] | 67 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 68 | MODULE_PARM_DESC(i915_enable_rc6, |
Eugeni Dodonov | 83b7f9a | 2012-03-23 11:57:18 -0300 | [diff] [blame] | 69 | "Enable power-saving render C-state 6. " |
| 70 | "Different stages can be selected via bitmask values " |
| 71 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " |
| 72 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " |
| 73 | "default: -1 (use per-chip default)"); |
Chris Wilson | ac66808 | 2011-02-09 16:15:32 +0000 | [diff] [blame] | 74 | |
Keith Packard | 4415e63 | 2011-11-09 09:57:50 -0800 | [diff] [blame] | 75 | int i915_enable_fbc __read_mostly = -1; |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 76 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 77 | MODULE_PARM_DESC(i915_enable_fbc, |
| 78 | "Enable frame buffer compression for power savings " |
Keith Packard | cd0de03 | 2011-09-19 21:34:19 -0700 | [diff] [blame] | 79 | "(default: -1 (use per-chip default))"); |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 80 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 81 | unsigned int i915_lvds_downclock __read_mostly = 0; |
Jesse Barnes | 3381434 | 2010-01-14 20:48:02 +0000 | [diff] [blame] | 82 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 83 | MODULE_PARM_DESC(lvds_downclock, |
| 84 | "Use panel (LVDS/eDP) downclocking for power savings " |
| 85 | "(default: false)"); |
Jesse Barnes | 3381434 | 2010-01-14 20:48:02 +0000 | [diff] [blame] | 86 | |
Takashi Iwai | 121d527 | 2012-03-20 13:07:06 +0100 | [diff] [blame] | 87 | int i915_lvds_channel_mode __read_mostly; |
| 88 | module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600); |
| 89 | MODULE_PARM_DESC(lvds_channel_mode, |
| 90 | "Specify LVDS channel mode " |
| 91 | "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); |
| 92 | |
Keith Packard | 4415e63 | 2011-11-09 09:57:50 -0800 | [diff] [blame] | 93 | int i915_panel_use_ssc __read_mostly = -1; |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 94 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 95 | MODULE_PARM_DESC(lvds_use_ssc, |
| 96 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " |
Keith Packard | 72bbe58 | 2011-09-26 16:09:45 -0700 | [diff] [blame] | 97 | "(default: auto from VBT)"); |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 98 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 99 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
Chris Wilson | 5a1e5b6 | 2011-01-29 16:50:25 +0000 | [diff] [blame] | 100 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 101 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
Mathias Fröhlich | c10e408 | 2012-03-01 06:44:35 +0100 | [diff] [blame] | 102 | "Override/Ignore selection of SDVO panel mode in the VBT " |
| 103 | "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); |
Chris Wilson | 5a1e5b6 | 2011-01-29 16:50:25 +0000 | [diff] [blame] | 104 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 105 | static bool i915_try_reset __read_mostly = true; |
Chris Wilson | d78cb50 | 2010-12-23 13:33:15 +0000 | [diff] [blame] | 106 | module_param_named(reset, i915_try_reset, bool, 0600); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 107 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
Chris Wilson | d78cb50 | 2010-12-23 13:33:15 +0000 | [diff] [blame] | 108 | |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 109 | bool i915_enable_hangcheck __read_mostly = true; |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 110 | module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); |
Ben Widawsky | 6e96e77 | 2011-07-13 14:38:18 -0700 | [diff] [blame] | 111 | MODULE_PARM_DESC(enable_hangcheck, |
| 112 | "Periodically check GPU activity for detecting hangs. " |
| 113 | "WARNING: Disabling this can cause system wide hangs. " |
| 114 | "(default: true)"); |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 115 | |
Daniel Vetter | 650dc07 | 2012-04-02 10:08:35 +0200 | [diff] [blame] | 116 | int i915_enable_ppgtt __read_mostly = -1; |
| 117 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 118 | MODULE_PARM_DESC(i915_enable_ppgtt, |
| 119 | "Enable PPGTT (default: true)"); |
| 120 | |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 121 | static struct drm_driver driver; |
Zhenyu Wang | 1f7a6e3 | 2010-02-23 14:05:24 +0800 | [diff] [blame] | 122 | extern int intel_agp_enabled; |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 123 | |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 124 | #define INTEL_VGA_DEVICE(id, info) { \ |
Daniel Vetter | 80a2901 | 2011-10-11 10:59:05 +0200 | [diff] [blame] | 125 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ |
Chris Wilson | 934f992 | 2011-01-20 13:09:12 +0000 | [diff] [blame] | 126 | .class_mask = 0xff0000, \ |
Kristian Høgsberg | 49ae35f | 2009-12-16 15:16:15 -0500 | [diff] [blame] | 127 | .vendor = 0x8086, \ |
| 128 | .device = id, \ |
| 129 | .subvendor = PCI_ANY_ID, \ |
| 130 | .subdevice = PCI_ANY_ID, \ |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 131 | .driver_data = (unsigned long) info } |
Kristian Høgsberg | 49ae35f | 2009-12-16 15:16:15 -0500 | [diff] [blame] | 132 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 133 | static const struct intel_device_info intel_i830_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 134 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 135 | .has_overlay = 1, .overlay_needs_physical = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 136 | }; |
| 137 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 138 | static const struct intel_device_info intel_845g_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 139 | .gen = 2, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 140 | .has_overlay = 1, .overlay_needs_physical = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 141 | }; |
| 142 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 143 | static const struct intel_device_info intel_i85x_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 144 | .gen = 2, .is_i85x = 1, .is_mobile = 1, |
Adam Jackson | 5ce8ba7 | 2010-04-15 14:03:30 -0400 | [diff] [blame] | 145 | .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 146 | .has_overlay = 1, .overlay_needs_physical = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 147 | }; |
| 148 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 149 | static const struct intel_device_info intel_i865g_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 150 | .gen = 2, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 151 | .has_overlay = 1, .overlay_needs_physical = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 152 | }; |
| 153 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 154 | static const struct intel_device_info intel_i915g_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 155 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 156 | .has_overlay = 1, .overlay_needs_physical = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 157 | }; |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 158 | static const struct intel_device_info intel_i915gm_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 159 | .gen = 3, .is_mobile = 1, |
Kristian Høgsberg | b295d1b | 2009-12-16 15:16:17 -0500 | [diff] [blame] | 160 | .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 161 | .has_overlay = 1, .overlay_needs_physical = 1, |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 162 | .supports_tv = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 163 | }; |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 164 | static const struct intel_device_info intel_i945g_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 165 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 166 | .has_overlay = 1, .overlay_needs_physical = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 167 | }; |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 168 | static const struct intel_device_info intel_i945gm_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 169 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, |
Kristian Høgsberg | b295d1b | 2009-12-16 15:16:17 -0500 | [diff] [blame] | 170 | .has_hotplug = 1, .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 171 | .has_overlay = 1, .overlay_needs_physical = 1, |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 172 | .supports_tv = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 173 | }; |
| 174 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 175 | static const struct intel_device_info intel_i965g_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 176 | .gen = 4, .is_broadwater = 1, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 177 | .has_hotplug = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 178 | .has_overlay = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 179 | }; |
| 180 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 181 | static const struct intel_device_info intel_i965gm_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 182 | .gen = 4, .is_crestline = 1, |
Chris Wilson | e3c4e5d | 2010-12-05 16:49:51 +0000 | [diff] [blame] | 183 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 184 | .has_overlay = 1, |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 185 | .supports_tv = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 186 | }; |
| 187 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 188 | static const struct intel_device_info intel_g33_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 189 | .gen = 3, .is_g33 = 1, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 190 | .need_gfx_hws = 1, .has_hotplug = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 191 | .has_overlay = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 192 | }; |
| 193 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 194 | static const struct intel_device_info intel_g45_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 195 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 196 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
Xiang, Haihao | 92f49d9 | 2010-09-16 10:43:10 +0800 | [diff] [blame] | 197 | .has_bsd_ring = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 198 | }; |
| 199 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 200 | static const struct intel_device_info intel_gm45_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 201 | .gen = 4, .is_g4x = 1, |
Chris Wilson | e3c4e5d | 2010-12-05 16:49:51 +0000 | [diff] [blame] | 202 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 203 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 204 | .supports_tv = 1, |
Xiang, Haihao | 92f49d9 | 2010-09-16 10:43:10 +0800 | [diff] [blame] | 205 | .has_bsd_ring = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 206 | }; |
| 207 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 208 | static const struct intel_device_info intel_pineview_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 209 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 210 | .need_gfx_hws = 1, .has_hotplug = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 211 | .has_overlay = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 212 | }; |
| 213 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 214 | static const struct intel_device_info intel_ironlake_d_info = { |
Chris Wilson | f00a3dd | 2010-10-21 14:57:17 +0100 | [diff] [blame] | 215 | .gen = 5, |
Eugeni Dodonov | 5a117db | 2012-01-05 09:34:29 -0200 | [diff] [blame] | 216 | .need_gfx_hws = 1, .has_hotplug = 1, |
Xiang, Haihao | 92f49d9 | 2010-09-16 10:43:10 +0800 | [diff] [blame] | 217 | .has_bsd_ring = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 218 | }; |
| 219 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 220 | static const struct intel_device_info intel_ironlake_m_info = { |
Chris Wilson | f00a3dd | 2010-10-21 14:57:17 +0100 | [diff] [blame] | 221 | .gen = 5, .is_mobile = 1, |
Chris Wilson | e3c4e5d | 2010-12-05 16:49:51 +0000 | [diff] [blame] | 222 | .need_gfx_hws = 1, .has_hotplug = 1, |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 223 | .has_fbc = 1, |
Xiang, Haihao | 92f49d9 | 2010-09-16 10:43:10 +0800 | [diff] [blame] | 224 | .has_bsd_ring = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 225 | }; |
| 226 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 227 | static const struct intel_device_info intel_sandybridge_d_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 228 | .gen = 6, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 229 | .need_gfx_hws = 1, .has_hotplug = 1, |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 230 | .has_bsd_ring = 1, |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 231 | .has_blt_ring = 1, |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 232 | .has_llc = 1, |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 233 | .has_force_wake = 1, |
Eric Anholt | f6e450a | 2009-11-02 12:08:22 -0800 | [diff] [blame] | 234 | }; |
| 235 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 236 | static const struct intel_device_info intel_sandybridge_m_info = { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 237 | .gen = 6, .is_mobile = 1, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 238 | .need_gfx_hws = 1, .has_hotplug = 1, |
Yuanhan Liu | 9c04f01 | 2010-12-15 15:42:32 +0800 | [diff] [blame] | 239 | .has_fbc = 1, |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 240 | .has_bsd_ring = 1, |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 241 | .has_blt_ring = 1, |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 242 | .has_llc = 1, |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 243 | .has_force_wake = 1, |
Eric Anholt | a13e409 | 2010-01-07 15:08:18 -0800 | [diff] [blame] | 244 | }; |
| 245 | |
Jesse Barnes | c76b615 | 2011-04-28 14:32:07 -0700 | [diff] [blame] | 246 | static const struct intel_device_info intel_ivybridge_d_info = { |
| 247 | .is_ivybridge = 1, .gen = 7, |
| 248 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 249 | .has_bsd_ring = 1, |
| 250 | .has_blt_ring = 1, |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 251 | .has_llc = 1, |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 252 | .has_force_wake = 1, |
Jesse Barnes | c76b615 | 2011-04-28 14:32:07 -0700 | [diff] [blame] | 253 | }; |
| 254 | |
| 255 | static const struct intel_device_info intel_ivybridge_m_info = { |
| 256 | .is_ivybridge = 1, .gen = 7, .is_mobile = 1, |
| 257 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 258 | .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ |
| 259 | .has_bsd_ring = 1, |
| 260 | .has_blt_ring = 1, |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 261 | .has_llc = 1, |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 262 | .has_force_wake = 1, |
Jesse Barnes | c76b615 | 2011-04-28 14:32:07 -0700 | [diff] [blame] | 263 | }; |
| 264 | |
Jesse Barnes | 70a3eb7 | 2012-03-28 13:39:21 -0700 | [diff] [blame] | 265 | static const struct intel_device_info intel_valleyview_m_info = { |
| 266 | .gen = 7, .is_mobile = 1, |
| 267 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 268 | .has_fbc = 0, |
| 269 | .has_bsd_ring = 1, |
| 270 | .has_blt_ring = 1, |
| 271 | .is_valleyview = 1, |
| 272 | }; |
| 273 | |
| 274 | static const struct intel_device_info intel_valleyview_d_info = { |
| 275 | .gen = 7, |
| 276 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 277 | .has_fbc = 0, |
| 278 | .has_bsd_ring = 1, |
| 279 | .has_blt_ring = 1, |
| 280 | .is_valleyview = 1, |
| 281 | }; |
| 282 | |
Eugeni Dodonov | 4cae9ae | 2012-03-29 12:32:18 -0300 | [diff] [blame] | 283 | static const struct intel_device_info intel_haswell_d_info = { |
| 284 | .is_haswell = 1, .gen = 7, |
| 285 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 286 | .has_bsd_ring = 1, |
| 287 | .has_blt_ring = 1, |
| 288 | .has_llc = 1, |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 289 | .has_force_wake = 1, |
Eugeni Dodonov | 4cae9ae | 2012-03-29 12:32:18 -0300 | [diff] [blame] | 290 | }; |
| 291 | |
| 292 | static const struct intel_device_info intel_haswell_m_info = { |
| 293 | .is_haswell = 1, .gen = 7, .is_mobile = 1, |
| 294 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 295 | .has_bsd_ring = 1, |
| 296 | .has_blt_ring = 1, |
| 297 | .has_llc = 1, |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 298 | .has_force_wake = 1, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 299 | }; |
| 300 | |
Chris Wilson | 6103da0 | 2010-07-05 18:01:47 +0100 | [diff] [blame] | 301 | static const struct pci_device_id pciidlist[] = { /* aka */ |
| 302 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ |
| 303 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ |
| 304 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ |
Adam Jackson | 5ce8ba7 | 2010-04-15 14:03:30 -0400 | [diff] [blame] | 305 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), |
Chris Wilson | 6103da0 | 2010-07-05 18:01:47 +0100 | [diff] [blame] | 306 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ |
| 307 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ |
| 308 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ |
| 309 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ |
| 310 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ |
| 311 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ |
| 312 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ |
| 313 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ |
| 314 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ |
| 315 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ |
| 316 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ |
| 317 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ |
| 318 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ |
| 319 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ |
| 320 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ |
| 321 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ |
| 322 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ |
| 323 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ |
| 324 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ |
| 325 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ |
| 326 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ |
| 327 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ |
Chris Wilson | 41a5142 | 2010-09-17 08:22:30 +0100 | [diff] [blame] | 328 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 329 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
| 330 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), |
| 331 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), |
| 332 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), |
Eric Anholt | f6e450a | 2009-11-02 12:08:22 -0800 | [diff] [blame] | 333 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
Zhenyu Wang | 8554048 | 2010-09-07 13:45:32 +0800 | [diff] [blame] | 334 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
| 335 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), |
Eric Anholt | a13e409 | 2010-01-07 15:08:18 -0800 | [diff] [blame] | 336 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
Zhenyu Wang | 8554048 | 2010-09-07 13:45:32 +0800 | [diff] [blame] | 337 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
Zhenyu Wang | 4fefe43 | 2010-08-19 09:46:16 +0800 | [diff] [blame] | 338 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
Zhenyu Wang | 8554048 | 2010-09-07 13:45:32 +0800 | [diff] [blame] | 339 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
Jesse Barnes | c76b615 | 2011-04-28 14:32:07 -0700 | [diff] [blame] | 340 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
| 341 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ |
| 342 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ |
| 343 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ |
| 344 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ |
Eugeni Dodonov | cc22a93 | 2012-03-29 20:55:48 -0300 | [diff] [blame] | 345 | INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ |
Eugeni Dodonov | c14f528 | 2012-05-09 15:37:32 -0300 | [diff] [blame] | 346 | INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */ |
| 347 | INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */ |
Paulo Zanoni | da612d8 | 2012-08-06 18:45:01 -0300 | [diff] [blame] | 348 | INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */ |
Eugeni Dodonov | c14f528 | 2012-05-09 15:37:32 -0300 | [diff] [blame] | 349 | INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */ |
| 350 | INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */ |
Paulo Zanoni | da612d8 | 2012-08-06 18:45:01 -0300 | [diff] [blame] | 351 | INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */ |
Eugeni Dodonov | c14f528 | 2012-05-09 15:37:32 -0300 | [diff] [blame] | 352 | INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */ |
| 353 | INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */ |
Paulo Zanoni | da612d8 | 2012-08-06 18:45:01 -0300 | [diff] [blame] | 354 | INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */ |
| 355 | INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */ |
| 356 | INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */ |
| 357 | INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */ |
| 358 | INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */ |
| 359 | INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */ |
| 360 | INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */ |
| 361 | INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */ |
| 362 | INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */ |
| 363 | INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */ |
| 364 | INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */ |
| 365 | INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */ |
| 366 | INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */ |
| 367 | INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */ |
| 368 | INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */ |
| 369 | INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */ |
| 370 | INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */ |
| 371 | INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */ |
| 372 | INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */ |
| 373 | INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */ |
| 374 | INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */ |
| 375 | INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */ |
| 376 | INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */ |
| 377 | INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */ |
| 378 | INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */ |
| 379 | INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */ |
| 380 | INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */ |
| 381 | INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */ |
Jesse Barnes | ff049b6 | 2012-06-20 10:53:13 -0700 | [diff] [blame] | 382 | INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info), |
| 383 | INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info), |
| 384 | INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info), |
Kristian Høgsberg | 49ae35f | 2009-12-16 15:16:15 -0500 | [diff] [blame] | 385 | {0, 0, 0} |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 386 | }; |
| 387 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 388 | #if defined(CONFIG_DRM_I915_KMS) |
| 389 | MODULE_DEVICE_TABLE(pci, pciidlist); |
| 390 | #endif |
| 391 | |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 392 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
Jesse Barnes | 90711d5 | 2011-04-28 14:48:02 -0700 | [diff] [blame] | 393 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 394 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
Jesse Barnes | c792513 | 2011-04-07 12:33:56 -0700 | [diff] [blame] | 395 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
Eugeni Dodonov | eb877eb | 2012-03-29 12:32:20 -0300 | [diff] [blame] | 396 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 397 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 398 | void intel_detect_pch(struct drm_device *dev) |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 399 | { |
| 400 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 401 | struct pci_dev *pch; |
| 402 | |
| 403 | /* |
| 404 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to |
| 405 | * make graphics device passthrough work easy for VMM, that only |
| 406 | * need to expose ISA bridge to let driver know the real hardware |
| 407 | * underneath. This is a requirement from virtualization team. |
| 408 | */ |
| 409 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); |
| 410 | if (pch) { |
| 411 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
| 412 | int id; |
| 413 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
| 414 | |
Jesse Barnes | 90711d5 | 2011-04-28 14:48:02 -0700 | [diff] [blame] | 415 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
| 416 | dev_priv->pch_type = PCH_IBX; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 417 | dev_priv->num_pch_pll = 2; |
Jesse Barnes | 90711d5 | 2011-04-28 14:48:02 -0700 | [diff] [blame] | 418 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); |
Daniel Vetter | 7fcb83c | 2012-10-31 22:52:27 +0100 | [diff] [blame] | 419 | WARN_ON(!IS_GEN5(dev)); |
Jesse Barnes | 90711d5 | 2011-04-28 14:48:02 -0700 | [diff] [blame] | 420 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 421 | dev_priv->pch_type = PCH_CPT; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 422 | dev_priv->num_pch_pll = 2; |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 423 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); |
Daniel Vetter | 7fcb83c | 2012-10-31 22:52:27 +0100 | [diff] [blame] | 424 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
Jesse Barnes | c792513 | 2011-04-07 12:33:56 -0700 | [diff] [blame] | 425 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
| 426 | /* PantherPoint is CPT compatible */ |
| 427 | dev_priv->pch_type = PCH_CPT; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 428 | dev_priv->num_pch_pll = 2; |
Jesse Barnes | c792513 | 2011-04-07 12:33:56 -0700 | [diff] [blame] | 429 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); |
Daniel Vetter | 7fcb83c | 2012-10-31 22:52:27 +0100 | [diff] [blame] | 430 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
Eugeni Dodonov | eb877eb | 2012-03-29 12:32:20 -0300 | [diff] [blame] | 431 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
| 432 | dev_priv->pch_type = PCH_LPT; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 433 | dev_priv->num_pch_pll = 0; |
Eugeni Dodonov | eb877eb | 2012-03-29 12:32:20 -0300 | [diff] [blame] | 434 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); |
Daniel Vetter | 7fcb83c | 2012-10-31 22:52:27 +0100 | [diff] [blame] | 435 | WARN_ON(!IS_HASWELL(dev)); |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 436 | } |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 437 | BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS); |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 438 | } |
| 439 | pci_dev_put(pch); |
| 440 | } |
| 441 | } |
| 442 | |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 443 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
| 444 | { |
| 445 | if (INTEL_INFO(dev)->gen < 6) |
| 446 | return 0; |
| 447 | |
| 448 | if (i915_semaphores >= 0) |
| 449 | return i915_semaphores; |
| 450 | |
Daniel Vetter | 59de329 | 2012-04-02 20:48:43 +0200 | [diff] [blame] | 451 | #ifdef CONFIG_INTEL_IOMMU |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 452 | /* Enable semaphores on SNB when IO remapping is off */ |
Daniel Vetter | 59de329 | 2012-04-02 20:48:43 +0200 | [diff] [blame] | 453 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
| 454 | return false; |
| 455 | #endif |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 456 | |
| 457 | return 1; |
| 458 | } |
| 459 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 460 | static int i915_drm_freeze(struct drm_device *dev) |
| 461 | { |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 462 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 463 | |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 464 | drm_kms_helper_poll_disable(dev); |
| 465 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 466 | pci_save_state(dev->pdev); |
| 467 | |
| 468 | /* If KMS is active, we do the leavevt stuff here */ |
| 469 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 470 | int error = i915_gem_idle(dev); |
| 471 | if (error) { |
| 472 | dev_err(&dev->pdev->dev, |
| 473 | "GEM idle failed, resume might fail\n"); |
| 474 | return error; |
| 475 | } |
Daniel Vetter | a261b24 | 2012-07-26 19:21:47 +0200 | [diff] [blame] | 476 | |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 477 | cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); |
| 478 | |
Daniel Vetter | a261b24 | 2012-07-26 19:21:47 +0200 | [diff] [blame] | 479 | intel_modeset_disable(dev); |
| 480 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 481 | drm_irq_uninstall(dev); |
| 482 | } |
| 483 | |
| 484 | i915_save_state(dev); |
| 485 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 486 | intel_opregion_fini(dev); |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 487 | |
| 488 | /* Modeset on resume, not lid events */ |
| 489 | dev_priv->modeset_on_lid = 0; |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 490 | |
Dave Airlie | 3fa016a | 2012-03-28 10:48:49 +0100 | [diff] [blame] | 491 | console_lock(); |
| 492 | intel_fbdev_set_suspend(dev, 1); |
| 493 | console_unlock(); |
| 494 | |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 495 | return 0; |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 496 | } |
| 497 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 498 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 499 | { |
| 500 | int error; |
| 501 | |
| 502 | if (!dev || !dev->dev_private) { |
| 503 | DRM_ERROR("dev: %p\n", dev); |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 504 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 505 | return -ENODEV; |
| 506 | } |
| 507 | |
Dave Airlie | b932ccb | 2008-02-20 10:02:20 +1000 | [diff] [blame] | 508 | if (state.event == PM_EVENT_PRETHAW) |
| 509 | return 0; |
| 510 | |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 511 | |
| 512 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 513 | return 0; |
Chris Wilson | 6eecba3 | 2010-09-08 09:45:11 +0100 | [diff] [blame] | 514 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 515 | error = i915_drm_freeze(dev); |
| 516 | if (error) |
| 517 | return error; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 518 | |
Dave Airlie | b932ccb | 2008-02-20 10:02:20 +1000 | [diff] [blame] | 519 | if (state.event == PM_EVENT_SUSPEND) { |
| 520 | /* Shut down the device */ |
| 521 | pci_disable_device(dev->pdev); |
| 522 | pci_set_power_state(dev->pdev, PCI_D3hot); |
| 523 | } |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 524 | |
| 525 | return 0; |
| 526 | } |
| 527 | |
Jesse Barnes | 073f34d | 2012-11-02 11:13:59 -0700 | [diff] [blame] | 528 | void intel_console_resume(struct work_struct *work) |
| 529 | { |
| 530 | struct drm_i915_private *dev_priv = |
| 531 | container_of(work, struct drm_i915_private, |
| 532 | console_resume_work); |
| 533 | struct drm_device *dev = dev_priv->dev; |
| 534 | |
| 535 | console_lock(); |
| 536 | intel_fbdev_set_suspend(dev, 0); |
| 537 | console_unlock(); |
| 538 | } |
| 539 | |
Jesse Barnes | 1abd02e | 2012-11-02 11:14:02 -0700 | [diff] [blame^] | 540 | static int __i915_drm_thaw(struct drm_device *dev) |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 541 | { |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 542 | struct drm_i915_private *dev_priv = dev->dev_private; |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 543 | int error = 0; |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 544 | |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 545 | i915_restore_state(dev); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 546 | intel_opregion_setup(dev); |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 547 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 548 | /* KMS EnterVT equivalent */ |
| 549 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
Paulo Zanoni | 40579ab | 2012-07-03 15:57:33 -0300 | [diff] [blame] | 550 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
Chris Wilson | 1833b13 | 2012-05-09 11:56:28 +0100 | [diff] [blame] | 551 | ironlake_init_pch_refclk(dev); |
| 552 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 553 | mutex_lock(&dev->struct_mutex); |
| 554 | dev_priv->mm.suspended = 0; |
| 555 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 556 | error = i915_gem_init_hw(dev); |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 557 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 226485e | 2009-02-23 15:41:09 -0800 | [diff] [blame] | 558 | |
Chris Wilson | 1833b13 | 2012-05-09 11:56:28 +0100 | [diff] [blame] | 559 | intel_modeset_init_hw(dev); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 560 | intel_modeset_setup_hw_state(dev); |
Jesse Barnes | 226485e | 2009-02-23 15:41:09 -0800 | [diff] [blame] | 561 | drm_irq_install(dev); |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 562 | } |
Jesse Barnes | 1daed3f | 2011-01-05 12:01:25 -0800 | [diff] [blame] | 563 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 564 | intel_opregion_init(dev); |
| 565 | |
Linus Torvalds | c9354c8 | 2009-11-02 09:29:55 -0800 | [diff] [blame] | 566 | dev_priv->modeset_on_lid = 0; |
Jesse Barnes | 06891e2 | 2009-09-14 10:58:48 -0700 | [diff] [blame] | 567 | |
Jesse Barnes | 073f34d | 2012-11-02 11:13:59 -0700 | [diff] [blame] | 568 | /* |
| 569 | * The console lock can be pretty contented on resume due |
| 570 | * to all the printk activity. Try to keep it out of the hot |
| 571 | * path of resume if possible. |
| 572 | */ |
| 573 | if (console_trylock()) { |
| 574 | intel_fbdev_set_suspend(dev, 0); |
| 575 | console_unlock(); |
| 576 | } else { |
| 577 | schedule_work(&dev_priv->console_resume_work); |
| 578 | } |
| 579 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 580 | return error; |
| 581 | } |
| 582 | |
Jesse Barnes | 1abd02e | 2012-11-02 11:14:02 -0700 | [diff] [blame^] | 583 | static int i915_drm_thaw(struct drm_device *dev) |
| 584 | { |
| 585 | int error = 0; |
| 586 | |
| 587 | intel_gt_reset(dev); |
| 588 | |
| 589 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 590 | mutex_lock(&dev->struct_mutex); |
| 591 | i915_gem_restore_gtt_mappings(dev); |
| 592 | mutex_unlock(&dev->struct_mutex); |
| 593 | } |
| 594 | |
| 595 | __i915_drm_thaw(dev); |
| 596 | |
| 597 | return error; |
| 598 | } |
| 599 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 600 | int i915_resume(struct drm_device *dev) |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 601 | { |
Jesse Barnes | 1abd02e | 2012-11-02 11:14:02 -0700 | [diff] [blame^] | 602 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 6eecba3 | 2010-09-08 09:45:11 +0100 | [diff] [blame] | 603 | int ret; |
| 604 | |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 605 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 606 | return 0; |
| 607 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 608 | if (pci_enable_device(dev->pdev)) |
| 609 | return -EIO; |
| 610 | |
| 611 | pci_set_master(dev->pdev); |
| 612 | |
Jesse Barnes | 1abd02e | 2012-11-02 11:14:02 -0700 | [diff] [blame^] | 613 | intel_gt_reset(dev); |
| 614 | |
| 615 | /* |
| 616 | * Platforms with opregion should have sane BIOS, older ones (gen3 and |
| 617 | * earlier) need this since the BIOS might clear all our scratch PTEs. |
| 618 | */ |
| 619 | if (drm_core_check_feature(dev, DRIVER_MODESET) && |
| 620 | !dev_priv->opregion.header) { |
| 621 | mutex_lock(&dev->struct_mutex); |
| 622 | i915_gem_restore_gtt_mappings(dev); |
| 623 | mutex_unlock(&dev->struct_mutex); |
| 624 | } |
| 625 | |
| 626 | ret = __i915_drm_thaw(dev); |
Chris Wilson | 6eecba3 | 2010-09-08 09:45:11 +0100 | [diff] [blame] | 627 | if (ret) |
| 628 | return ret; |
| 629 | |
| 630 | drm_kms_helper_poll_enable(dev); |
| 631 | return 0; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 632 | } |
| 633 | |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 634 | static int i8xx_do_reset(struct drm_device *dev) |
Chris Wilson | dc96e9b | 2010-10-01 12:05:06 +0100 | [diff] [blame] | 635 | { |
| 636 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 637 | |
| 638 | if (IS_I85X(dev)) |
| 639 | return -ENODEV; |
| 640 | |
| 641 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); |
| 642 | POSTING_READ(D_STATE); |
| 643 | |
| 644 | if (IS_I830(dev) || IS_845G(dev)) { |
| 645 | I915_WRITE(DEBUG_RESET_I830, |
| 646 | DEBUG_RESET_DISPLAY | |
| 647 | DEBUG_RESET_RENDER | |
| 648 | DEBUG_RESET_FULL); |
| 649 | POSTING_READ(DEBUG_RESET_I830); |
| 650 | msleep(1); |
| 651 | |
| 652 | I915_WRITE(DEBUG_RESET_I830, 0); |
| 653 | POSTING_READ(DEBUG_RESET_I830); |
| 654 | } |
| 655 | |
| 656 | msleep(1); |
| 657 | |
| 658 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); |
| 659 | POSTING_READ(D_STATE); |
| 660 | |
| 661 | return 0; |
| 662 | } |
| 663 | |
Kenneth Graunke | f49f058 | 2010-09-11 01:19:14 -0700 | [diff] [blame] | 664 | static int i965_reset_complete(struct drm_device *dev) |
| 665 | { |
| 666 | u8 gdrst; |
Kenneth Graunke | eeccdca | 2010-09-11 01:24:50 -0700 | [diff] [blame] | 667 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
Daniel Vetter | 5fe9fe8 | 2012-05-02 21:33:52 +0200 | [diff] [blame] | 668 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
Kenneth Graunke | f49f058 | 2010-09-11 01:19:14 -0700 | [diff] [blame] | 669 | } |
| 670 | |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 671 | static int i965_do_reset(struct drm_device *dev) |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 672 | { |
Daniel Vetter | 5ccce18 | 2012-04-27 15:17:45 +0200 | [diff] [blame] | 673 | int ret; |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 674 | u8 gdrst; |
| 675 | |
Chris Wilson | ae681d9 | 2010-10-01 14:57:56 +0100 | [diff] [blame] | 676 | /* |
| 677 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as |
| 678 | * well as the reset bit (GR/bit 0). Setting the GR bit |
| 679 | * triggers the reset; when done, the hardware will clear it. |
| 680 | */ |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 681 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 682 | pci_write_config_byte(dev->pdev, I965_GDRST, |
Daniel Vetter | 5ccce18 | 2012-04-27 15:17:45 +0200 | [diff] [blame] | 683 | gdrst | GRDOM_RENDER | |
| 684 | GRDOM_RESET_ENABLE); |
| 685 | ret = wait_for(i965_reset_complete(dev), 500); |
| 686 | if (ret) |
| 687 | return ret; |
| 688 | |
| 689 | /* We can't reset render&media without also resetting display ... */ |
| 690 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
| 691 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 692 | gdrst | GRDOM_MEDIA | |
| 693 | GRDOM_RESET_ENABLE); |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 694 | |
| 695 | return wait_for(i965_reset_complete(dev), 500); |
| 696 | } |
| 697 | |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 698 | static int ironlake_do_reset(struct drm_device *dev) |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 699 | { |
| 700 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 5ccce18 | 2012-04-27 15:17:45 +0200 | [diff] [blame] | 701 | u32 gdrst; |
| 702 | int ret; |
| 703 | |
| 704 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 705 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
Daniel Vetter | 5ccce18 | 2012-04-27 15:17:45 +0200 | [diff] [blame] | 706 | gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
| 707 | ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
| 708 | if (ret) |
| 709 | return ret; |
| 710 | |
| 711 | /* We can't reset render&media without also resetting display ... */ |
| 712 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); |
| 713 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
| 714 | gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 715 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 716 | } |
| 717 | |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 718 | static int gen6_do_reset(struct drm_device *dev) |
Eric Anholt | cff458c | 2010-11-18 09:31:14 +0800 | [diff] [blame] | 719 | { |
| 720 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | b6e45f8 | 2012-01-06 11:34:04 -0800 | [diff] [blame] | 721 | int ret; |
| 722 | unsigned long irqflags; |
Eric Anholt | cff458c | 2010-11-18 09:31:14 +0800 | [diff] [blame] | 723 | |
Keith Packard | 286fed4 | 2012-01-06 11:44:11 -0800 | [diff] [blame] | 724 | /* Hold gt_lock across reset to prevent any register access |
| 725 | * with forcewake not set correctly |
| 726 | */ |
Keith Packard | b6e45f8 | 2012-01-06 11:34:04 -0800 | [diff] [blame] | 727 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
Keith Packard | 286fed4 | 2012-01-06 11:44:11 -0800 | [diff] [blame] | 728 | |
| 729 | /* Reset the chip */ |
| 730 | |
| 731 | /* GEN6_GDRST is not in the gt power well, no need to check |
| 732 | * for fifo space for the write or forcewake the chip for |
| 733 | * the read |
| 734 | */ |
| 735 | I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL); |
| 736 | |
| 737 | /* Spin waiting for the device to ack the reset request */ |
| 738 | ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); |
| 739 | |
| 740 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ |
Keith Packard | b6e45f8 | 2012-01-06 11:34:04 -0800 | [diff] [blame] | 741 | if (dev_priv->forcewake_count) |
Chris Wilson | 990bbda | 2012-07-02 11:51:02 -0300 | [diff] [blame] | 742 | dev_priv->gt.force_wake_get(dev_priv); |
Keith Packard | 286fed4 | 2012-01-06 11:44:11 -0800 | [diff] [blame] | 743 | else |
Chris Wilson | 990bbda | 2012-07-02 11:51:02 -0300 | [diff] [blame] | 744 | dev_priv->gt.force_wake_put(dev_priv); |
Keith Packard | 286fed4 | 2012-01-06 11:44:11 -0800 | [diff] [blame] | 745 | |
| 746 | /* Restore fifo count */ |
| 747 | dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); |
| 748 | |
Keith Packard | b6e45f8 | 2012-01-06 11:34:04 -0800 | [diff] [blame] | 749 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
| 750 | return ret; |
Eric Anholt | cff458c | 2010-11-18 09:31:14 +0800 | [diff] [blame] | 751 | } |
| 752 | |
Ben Widawsky | 8e96d9c | 2012-06-04 14:42:56 -0700 | [diff] [blame] | 753 | int intel_gpu_reset(struct drm_device *dev) |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 754 | { |
Daniel Vetter | 2b9dc9a | 2012-04-27 15:17:43 +0200 | [diff] [blame] | 755 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 756 | int ret = -ENODEV; |
| 757 | |
| 758 | switch (INTEL_INFO(dev)->gen) { |
| 759 | case 7: |
| 760 | case 6: |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 761 | ret = gen6_do_reset(dev); |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 762 | break; |
| 763 | case 5: |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 764 | ret = ironlake_do_reset(dev); |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 765 | break; |
| 766 | case 4: |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 767 | ret = i965_do_reset(dev); |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 768 | break; |
| 769 | case 2: |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 770 | ret = i8xx_do_reset(dev); |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 771 | break; |
| 772 | } |
| 773 | |
Daniel Vetter | 2b9dc9a | 2012-04-27 15:17:43 +0200 | [diff] [blame] | 774 | /* Also reset the gpu hangman. */ |
| 775 | if (dev_priv->stop_rings) { |
| 776 | DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n"); |
| 777 | dev_priv->stop_rings = 0; |
| 778 | if (ret == -ENODEV) { |
| 779 | DRM_ERROR("Reset not implemented, but ignoring " |
| 780 | "error for simulated gpu hangs\n"); |
| 781 | ret = 0; |
| 782 | } |
| 783 | } |
| 784 | |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 785 | return ret; |
| 786 | } |
| 787 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 788 | /** |
Eugeni Dodonov | f3953dc | 2011-11-28 16:15:17 -0200 | [diff] [blame] | 789 | * i915_reset - reset chip after a hang |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 790 | * @dev: drm device to reset |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 791 | * |
| 792 | * Reset the chip. Useful if a hang is detected. Returns zero on successful |
| 793 | * reset or otherwise an error code. |
| 794 | * |
| 795 | * Procedure is fairly simple: |
| 796 | * - reset the chip using the reset reg |
| 797 | * - re-init context state |
| 798 | * - re-init hardware status page |
| 799 | * - re-init ring buffer |
| 800 | * - re-init interrupt state |
| 801 | * - re-init display |
| 802 | */ |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 803 | int i915_reset(struct drm_device *dev) |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 804 | { |
| 805 | drm_i915_private_t *dev_priv = dev->dev_private; |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 806 | int ret; |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 807 | |
Chris Wilson | d78cb50 | 2010-12-23 13:33:15 +0000 | [diff] [blame] | 808 | if (!i915_try_reset) |
| 809 | return 0; |
| 810 | |
Daniel Vetter | d54a02c | 2012-07-04 22:18:39 +0200 | [diff] [blame] | 811 | mutex_lock(&dev->struct_mutex); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 812 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 813 | i915_gem_reset(dev); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 814 | |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 815 | ret = -ENODEV; |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 816 | if (get_seconds() - dev_priv->last_gpu_reset < 5) |
Chris Wilson | ae681d9 | 2010-10-01 14:57:56 +0100 | [diff] [blame] | 817 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 818 | else |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 819 | ret = intel_gpu_reset(dev); |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 820 | |
Chris Wilson | ae681d9 | 2010-10-01 14:57:56 +0100 | [diff] [blame] | 821 | dev_priv->last_gpu_reset = get_seconds(); |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 822 | if (ret) { |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 823 | DRM_ERROR("Failed to reset chip.\n"); |
Daniel J Blueman | f953c93 | 2010-05-17 14:23:52 +0100 | [diff] [blame] | 824 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 825 | return ret; |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 826 | } |
| 827 | |
| 828 | /* Ok, now get things going again... */ |
| 829 | |
| 830 | /* |
| 831 | * Everything depends on having the GTT running, so we need to start |
| 832 | * there. Fortunately we don't need to do this unless we reset the |
| 833 | * chip at a PCI level. |
| 834 | * |
| 835 | * Next we need to restore the context, but we don't use those |
| 836 | * yet either... |
| 837 | * |
| 838 | * Ring buffer needs to be re-initialized in the KMS case, or if X |
| 839 | * was running at the time of the reset (i.e. we weren't VT |
| 840 | * switched away). |
| 841 | */ |
| 842 | if (drm_core_check_feature(dev, DRIVER_MODESET) || |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 843 | !dev_priv->mm.suspended) { |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 844 | struct intel_ring_buffer *ring; |
| 845 | int i; |
| 846 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 847 | dev_priv->mm.suspended = 0; |
Eric Anholt | 75a6898 | 2010-11-18 09:31:13 +0800 | [diff] [blame] | 848 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 849 | i915_gem_init_swizzling(dev); |
| 850 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 851 | for_each_ring(ring, dev_priv, i) |
| 852 | ring->init(ring); |
Eric Anholt | 75a6898 | 2010-11-18 09:31:13 +0800 | [diff] [blame] | 853 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 854 | i915_gem_context_init(dev); |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 855 | i915_gem_init_ppgtt(dev); |
| 856 | |
Daniel Vetter | 8e88a2b | 2012-06-19 18:40:00 +0200 | [diff] [blame] | 857 | /* |
| 858 | * It would make sense to re-init all the other hw state, at |
| 859 | * least the rps/rc6/emon init done within modeset_init_hw. For |
| 860 | * some unknown reason, this blows up my ilk, so don't. |
| 861 | */ |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 862 | |
Daniel Vetter | 8e88a2b | 2012-06-19 18:40:00 +0200 | [diff] [blame] | 863 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 864 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 865 | drm_irq_uninstall(dev); |
| 866 | drm_irq_install(dev); |
Daniel Vetter | bcbc324 | 2012-04-27 15:17:41 +0200 | [diff] [blame] | 867 | } else { |
| 868 | mutex_unlock(&dev->struct_mutex); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 869 | } |
| 870 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 871 | return 0; |
| 872 | } |
| 873 | |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 874 | static int __devinit |
| 875 | i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 876 | { |
Daniel Vetter | 01a0685 | 2012-06-25 15:58:49 +0200 | [diff] [blame] | 877 | struct intel_device_info *intel_info = |
| 878 | (struct intel_device_info *) ent->driver_data; |
| 879 | |
Chris Wilson | 5fe49d8 | 2011-02-01 19:43:02 +0000 | [diff] [blame] | 880 | /* Only bind to function 0 of the device. Early generations |
| 881 | * used function 1 as a placeholder for multi-head. This causes |
| 882 | * us confusion instead, especially on the systems where both |
| 883 | * functions have the same PCI-ID! |
| 884 | */ |
| 885 | if (PCI_FUNC(pdev->devfn)) |
| 886 | return -ENODEV; |
| 887 | |
Daniel Vetter | 01a0685 | 2012-06-25 15:58:49 +0200 | [diff] [blame] | 888 | /* We've managed to ship a kms-enabled ddx that shipped with an XvMC |
| 889 | * implementation for gen3 (and only gen3) that used legacy drm maps |
| 890 | * (gasp!) to share buffers between X and the client. Hence we need to |
| 891 | * keep around the fake agp stuff for gen3, even when kms is enabled. */ |
| 892 | if (intel_info->gen != 3) { |
| 893 | driver.driver_features &= |
| 894 | ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP); |
| 895 | } else if (!intel_agp_enabled) { |
| 896 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); |
| 897 | return -ENODEV; |
| 898 | } |
| 899 | |
Jordan Crouse | dcdb167 | 2010-05-27 13:40:25 -0600 | [diff] [blame] | 900 | return drm_get_pci_dev(pdev, ent, &driver); |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 901 | } |
| 902 | |
| 903 | static void |
| 904 | i915_pci_remove(struct pci_dev *pdev) |
| 905 | { |
| 906 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 907 | |
| 908 | drm_put_dev(dev); |
| 909 | } |
| 910 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 911 | static int i915_pm_suspend(struct device *dev) |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 912 | { |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 913 | struct pci_dev *pdev = to_pci_dev(dev); |
| 914 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
| 915 | int error; |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 916 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 917 | if (!drm_dev || !drm_dev->dev_private) { |
| 918 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); |
| 919 | return -ENODEV; |
| 920 | } |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 921 | |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 922 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 923 | return 0; |
| 924 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 925 | error = i915_drm_freeze(drm_dev); |
| 926 | if (error) |
| 927 | return error; |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 928 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 929 | pci_disable_device(pdev); |
| 930 | pci_set_power_state(pdev, PCI_D3hot); |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 931 | |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 932 | return 0; |
| 933 | } |
| 934 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 935 | static int i915_pm_resume(struct device *dev) |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 936 | { |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 937 | struct pci_dev *pdev = to_pci_dev(dev); |
| 938 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
| 939 | |
| 940 | return i915_resume(drm_dev); |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 941 | } |
| 942 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 943 | static int i915_pm_freeze(struct device *dev) |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 944 | { |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 945 | struct pci_dev *pdev = to_pci_dev(dev); |
| 946 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
| 947 | |
| 948 | if (!drm_dev || !drm_dev->dev_private) { |
| 949 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); |
| 950 | return -ENODEV; |
| 951 | } |
| 952 | |
| 953 | return i915_drm_freeze(drm_dev); |
| 954 | } |
| 955 | |
| 956 | static int i915_pm_thaw(struct device *dev) |
| 957 | { |
| 958 | struct pci_dev *pdev = to_pci_dev(dev); |
| 959 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
| 960 | |
| 961 | return i915_drm_thaw(drm_dev); |
| 962 | } |
| 963 | |
| 964 | static int i915_pm_poweroff(struct device *dev) |
| 965 | { |
| 966 | struct pci_dev *pdev = to_pci_dev(dev); |
| 967 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 968 | |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 969 | return i915_drm_freeze(drm_dev); |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 970 | } |
| 971 | |
Chris Wilson | b4b78d1 | 2010-06-06 15:40:20 +0100 | [diff] [blame] | 972 | static const struct dev_pm_ops i915_pm_ops = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 973 | .suspend = i915_pm_suspend, |
| 974 | .resume = i915_pm_resume, |
| 975 | .freeze = i915_pm_freeze, |
| 976 | .thaw = i915_pm_thaw, |
| 977 | .poweroff = i915_pm_poweroff, |
| 978 | .restore = i915_pm_resume, |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 979 | }; |
| 980 | |
Laurent Pinchart | 78b6855 | 2012-05-17 13:27:22 +0200 | [diff] [blame] | 981 | static const struct vm_operations_struct i915_gem_vm_ops = { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 982 | .fault = i915_gem_fault, |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 983 | .open = drm_gem_vm_open, |
| 984 | .close = drm_gem_vm_close, |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 985 | }; |
| 986 | |
Arjan van de Ven | e08e96d | 2011-10-31 07:28:57 -0700 | [diff] [blame] | 987 | static const struct file_operations i915_driver_fops = { |
| 988 | .owner = THIS_MODULE, |
| 989 | .open = drm_open, |
| 990 | .release = drm_release, |
| 991 | .unlocked_ioctl = drm_ioctl, |
| 992 | .mmap = drm_gem_mmap, |
| 993 | .poll = drm_poll, |
| 994 | .fasync = drm_fasync, |
| 995 | .read = drm_read, |
| 996 | #ifdef CONFIG_COMPAT |
| 997 | .compat_ioctl = i915_compat_ioctl, |
| 998 | #endif |
| 999 | .llseek = noop_llseek, |
| 1000 | }; |
| 1001 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1002 | static struct drm_driver driver = { |
Michael Witten | 0c54781 | 2011-08-25 17:55:54 +0000 | [diff] [blame] | 1003 | /* Don't use MTRRs here; the Xserver or userspace app should |
| 1004 | * deal with them for Intel hardware. |
Dave Airlie | 792d2b9 | 2005-11-11 23:30:27 +1100 | [diff] [blame] | 1005 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1006 | .driver_features = |
| 1007 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1008 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME, |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 1009 | .load = i915_driver_load, |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1010 | .unload = i915_driver_unload, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1011 | .open = i915_driver_open, |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 1012 | .lastclose = i915_driver_lastclose, |
| 1013 | .preclose = i915_driver_preclose, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1014 | .postclose = i915_driver_postclose, |
Rafael J. Wysocki | d8e2920 | 2010-01-09 00:45:33 +0100 | [diff] [blame] | 1015 | |
| 1016 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ |
| 1017 | .suspend = i915_suspend, |
| 1018 | .resume = i915_resume, |
| 1019 | |
Dave Airlie | cda1738 | 2005-07-10 17:31:26 +1000 | [diff] [blame] | 1020 | .device_is_agp = i915_driver_device_is_agp, |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1021 | .master_create = i915_master_create, |
| 1022 | .master_destroy = i915_master_destroy, |
Ben Gamari | 955b12d | 2009-02-17 20:08:49 -0500 | [diff] [blame] | 1023 | #if defined(CONFIG_DEBUG_FS) |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 1024 | .debugfs_init = i915_debugfs_init, |
| 1025 | .debugfs_cleanup = i915_debugfs_cleanup, |
Ben Gamari | 955b12d | 2009-02-17 20:08:49 -0500 | [diff] [blame] | 1026 | #endif |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1027 | .gem_init_object = i915_gem_init_object, |
| 1028 | .gem_free_object = i915_gem_free_object, |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1029 | .gem_vm_ops = &i915_gem_vm_ops, |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1030 | |
| 1031 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
| 1032 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
| 1033 | .gem_prime_export = i915_gem_prime_export, |
| 1034 | .gem_prime_import = i915_gem_prime_import, |
| 1035 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1036 | .dumb_create = i915_gem_dumb_create, |
| 1037 | .dumb_map_offset = i915_gem_mmap_gtt, |
| 1038 | .dumb_destroy = i915_gem_dumb_destroy, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1039 | .ioctls = i915_ioctls, |
Arjan van de Ven | e08e96d | 2011-10-31 07:28:57 -0700 | [diff] [blame] | 1040 | .fops = &i915_driver_fops, |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 1041 | .name = DRIVER_NAME, |
| 1042 | .desc = DRIVER_DESC, |
| 1043 | .date = DRIVER_DATE, |
| 1044 | .major = DRIVER_MAJOR, |
| 1045 | .minor = DRIVER_MINOR, |
| 1046 | .patchlevel = DRIVER_PATCHLEVEL, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1047 | }; |
| 1048 | |
Dave Airlie | 8410ea3 | 2010-12-15 03:16:38 +1000 | [diff] [blame] | 1049 | static struct pci_driver i915_pci_driver = { |
| 1050 | .name = DRIVER_NAME, |
| 1051 | .id_table = pciidlist, |
| 1052 | .probe = i915_pci_probe, |
| 1053 | .remove = i915_pci_remove, |
| 1054 | .driver.pm = &i915_pm_ops, |
| 1055 | }; |
| 1056 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1057 | static int __init i915_init(void) |
| 1058 | { |
| 1059 | driver.num_ioctls = i915_max_ioctl; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1060 | |
| 1061 | /* |
| 1062 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless |
| 1063 | * explicitly disabled with the module pararmeter. |
| 1064 | * |
| 1065 | * Otherwise, just follow the parameter (defaulting to off). |
| 1066 | * |
| 1067 | * Allow optional vga_text_mode_force boot option to override |
| 1068 | * the default behavior. |
| 1069 | */ |
| 1070 | #if defined(CONFIG_DRM_I915_KMS) |
| 1071 | if (i915_modeset != 0) |
| 1072 | driver.driver_features |= DRIVER_MODESET; |
| 1073 | #endif |
| 1074 | if (i915_modeset == 1) |
| 1075 | driver.driver_features |= DRIVER_MODESET; |
| 1076 | |
| 1077 | #ifdef CONFIG_VGA_CONSOLE |
| 1078 | if (vgacon_text_force() && i915_modeset == -1) |
| 1079 | driver.driver_features &= ~DRIVER_MODESET; |
| 1080 | #endif |
| 1081 | |
Chris Wilson | 3885c6b | 2011-01-23 10:45:14 +0000 | [diff] [blame] | 1082 | if (!(driver.driver_features & DRIVER_MODESET)) |
| 1083 | driver.get_vblank_timestamp = NULL; |
| 1084 | |
Dave Airlie | 8410ea3 | 2010-12-15 03:16:38 +1000 | [diff] [blame] | 1085 | return drm_pci_init(&driver, &i915_pci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1086 | } |
| 1087 | |
| 1088 | static void __exit i915_exit(void) |
| 1089 | { |
Dave Airlie | 8410ea3 | 2010-12-15 03:16:38 +1000 | [diff] [blame] | 1090 | drm_pci_exit(&driver, &i915_pci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1091 | } |
| 1092 | |
| 1093 | module_init(i915_init); |
| 1094 | module_exit(i915_exit); |
| 1095 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1096 | MODULE_AUTHOR(DRIVER_AUTHOR); |
| 1097 | MODULE_DESCRIPTION(DRIVER_DESC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1098 | MODULE_LICENSE("GPL and additional rights"); |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1099 | |
Jesse Barnes | b7d8409 | 2012-03-22 14:38:43 -0700 | [diff] [blame] | 1100 | /* We give fast paths for the really cool registers */ |
| 1101 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 1102 | ((HAS_FORCE_WAKE((dev_priv)->dev)) && \ |
| 1103 | ((reg) < 0x40000) && \ |
| 1104 | ((reg) != FORCEWAKE)) |
Jesse Barnes | b7d8409 | 2012-03-22 14:38:43 -0700 | [diff] [blame] | 1105 | |
Jesse Barnes | f7dff0c | 2012-06-15 11:55:17 -0700 | [diff] [blame] | 1106 | static bool IS_DISPLAYREG(u32 reg) |
| 1107 | { |
| 1108 | /* |
| 1109 | * This should make it easier to transition modules over to the |
| 1110 | * new register block scheme, since we can do it incrementally. |
| 1111 | */ |
Daniel Vetter | a7e806d | 2012-07-11 16:27:55 +0200 | [diff] [blame] | 1112 | if (reg >= VLV_DISPLAY_BASE) |
Jesse Barnes | f7dff0c | 2012-06-15 11:55:17 -0700 | [diff] [blame] | 1113 | return false; |
| 1114 | |
| 1115 | if (reg >= RENDER_RING_BASE && |
| 1116 | reg < RENDER_RING_BASE + 0xff) |
| 1117 | return false; |
| 1118 | if (reg >= GEN6_BSD_RING_BASE && |
| 1119 | reg < GEN6_BSD_RING_BASE + 0xff) |
| 1120 | return false; |
| 1121 | if (reg >= BLT_RING_BASE && |
| 1122 | reg < BLT_RING_BASE + 0xff) |
| 1123 | return false; |
| 1124 | |
| 1125 | if (reg == PGTBL_ER) |
| 1126 | return false; |
| 1127 | |
| 1128 | if (reg >= IPEIR_I965 && |
| 1129 | reg < HWSTAM) |
| 1130 | return false; |
| 1131 | |
| 1132 | if (reg == MI_MODE) |
| 1133 | return false; |
| 1134 | |
| 1135 | if (reg == GFX_MODE_GEN7) |
| 1136 | return false; |
| 1137 | |
| 1138 | if (reg == RENDER_HWS_PGA_GEN7 || |
| 1139 | reg == BSD_HWS_PGA_GEN7 || |
| 1140 | reg == BLT_HWS_PGA_GEN7) |
| 1141 | return false; |
| 1142 | |
| 1143 | if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL || |
| 1144 | reg == GEN6_BSD_RNCID) |
| 1145 | return false; |
| 1146 | |
| 1147 | if (reg == GEN6_BLITTER_ECOSKPD) |
| 1148 | return false; |
| 1149 | |
| 1150 | if (reg >= 0x4000c && |
| 1151 | reg <= 0x4002c) |
| 1152 | return false; |
| 1153 | |
| 1154 | if (reg >= 0x4f000 && |
| 1155 | reg <= 0x4f08f) |
| 1156 | return false; |
| 1157 | |
| 1158 | if (reg >= 0x4f100 && |
| 1159 | reg <= 0x4f11f) |
| 1160 | return false; |
| 1161 | |
| 1162 | if (reg >= VLV_MASTER_IER && |
| 1163 | reg <= GEN6_PMIER) |
| 1164 | return false; |
| 1165 | |
| 1166 | if (reg >= FENCE_REG_SANDYBRIDGE_0 && |
| 1167 | reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8))) |
| 1168 | return false; |
| 1169 | |
| 1170 | if (reg >= VLV_IIR_RW && |
| 1171 | reg <= VLV_ISR) |
| 1172 | return false; |
| 1173 | |
| 1174 | if (reg == FORCEWAKE_VLV || |
| 1175 | reg == FORCEWAKE_ACK_VLV) |
| 1176 | return false; |
| 1177 | |
| 1178 | if (reg == GEN6_GDRST) |
| 1179 | return false; |
| 1180 | |
Jesse Barnes | 8ab4397 | 2012-10-25 12:15:42 -0700 | [diff] [blame] | 1181 | switch (reg) { |
Jesse Barnes | 310c53a | 2012-10-25 12:15:48 -0700 | [diff] [blame] | 1182 | case _3D_CHICKEN3: |
| 1183 | case IVB_CHICKEN3: |
| 1184 | case GEN7_COMMON_SLICE_CHICKEN1: |
| 1185 | case GEN7_L3CNTLREG1: |
| 1186 | case GEN7_L3_CHICKEN_MODE_REGISTER: |
Jesse Barnes | 8ab4397 | 2012-10-25 12:15:42 -0700 | [diff] [blame] | 1187 | case GEN7_ROW_CHICKEN2: |
Jesse Barnes | 310c53a | 2012-10-25 12:15:48 -0700 | [diff] [blame] | 1188 | case GEN7_L3SQCREG4: |
| 1189 | case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG: |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 1190 | case GEN7_HALF_SLICE_CHICKEN1: |
Jesse Barnes | 310c53a | 2012-10-25 12:15:48 -0700 | [diff] [blame] | 1191 | case GEN6_MBCTL: |
| 1192 | case GEN6_UCGCTL2: |
Jesse Barnes | 8ab4397 | 2012-10-25 12:15:42 -0700 | [diff] [blame] | 1193 | return false; |
| 1194 | default: |
| 1195 | break; |
| 1196 | } |
| 1197 | |
Jesse Barnes | f7dff0c | 2012-06-15 11:55:17 -0700 | [diff] [blame] | 1198 | return true; |
| 1199 | } |
| 1200 | |
Daniel Vetter | a8b1397 | 2012-10-18 14:16:09 +0200 | [diff] [blame] | 1201 | static void |
| 1202 | ilk_dummy_write(struct drm_i915_private *dev_priv) |
| 1203 | { |
| 1204 | /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the |
| 1205 | * chip from rc6 before touching it for real. MI_MODE is masked, hence |
| 1206 | * harmless to write 0 into. */ |
| 1207 | I915_WRITE_NOTRACE(MI_MODE, 0); |
| 1208 | } |
| 1209 | |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1210 | #define __i915_read(x, y) \ |
| 1211 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ |
| 1212 | u##x val = 0; \ |
Daniel Vetter | a8b1397 | 2012-10-18 14:16:09 +0200 | [diff] [blame] | 1213 | if (IS_GEN5(dev_priv->dev)) \ |
| 1214 | ilk_dummy_write(dev_priv); \ |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1215 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
Keith Packard | c937504 | 2012-01-06 11:48:38 -0800 | [diff] [blame] | 1216 | unsigned long irqflags; \ |
| 1217 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ |
| 1218 | if (dev_priv->forcewake_count == 0) \ |
Chris Wilson | 990bbda | 2012-07-02 11:51:02 -0300 | [diff] [blame] | 1219 | dev_priv->gt.force_wake_get(dev_priv); \ |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1220 | val = read##y(dev_priv->regs + reg); \ |
Keith Packard | c937504 | 2012-01-06 11:48:38 -0800 | [diff] [blame] | 1221 | if (dev_priv->forcewake_count == 0) \ |
Chris Wilson | 990bbda | 2012-07-02 11:51:02 -0300 | [diff] [blame] | 1222 | dev_priv->gt.force_wake_put(dev_priv); \ |
Keith Packard | c937504 | 2012-01-06 11:48:38 -0800 | [diff] [blame] | 1223 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ |
Jesse Barnes | f7dff0c | 2012-06-15 11:55:17 -0700 | [diff] [blame] | 1224 | } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ |
| 1225 | val = read##y(dev_priv->regs + reg + 0x180000); \ |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1226 | } else { \ |
| 1227 | val = read##y(dev_priv->regs + reg); \ |
| 1228 | } \ |
| 1229 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ |
| 1230 | return val; \ |
| 1231 | } |
| 1232 | |
| 1233 | __i915_read(8, b) |
| 1234 | __i915_read(16, w) |
| 1235 | __i915_read(32, l) |
| 1236 | __i915_read(64, q) |
| 1237 | #undef __i915_read |
| 1238 | |
| 1239 | #define __i915_write(x, y) \ |
| 1240 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ |
Ben Widawsky | 67a3744 | 2012-02-09 10:15:20 +0100 | [diff] [blame] | 1241 | u32 __fifo_ret = 0; \ |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1242 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
| 1243 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
Ben Widawsky | 67a3744 | 2012-02-09 10:15:20 +0100 | [diff] [blame] | 1244 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1245 | } \ |
Daniel Vetter | a8b1397 | 2012-10-18 14:16:09 +0200 | [diff] [blame] | 1246 | if (IS_GEN5(dev_priv->dev)) \ |
| 1247 | ilk_dummy_write(dev_priv); \ |
Jesse Barnes | f7dff0c | 2012-06-15 11:55:17 -0700 | [diff] [blame] | 1248 | if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ |
| 1249 | write##y(val, dev_priv->regs + reg + 0x180000); \ |
| 1250 | } else { \ |
| 1251 | write##y(val, dev_priv->regs + reg); \ |
| 1252 | } \ |
Ben Widawsky | 67a3744 | 2012-02-09 10:15:20 +0100 | [diff] [blame] | 1253 | if (unlikely(__fifo_ret)) { \ |
| 1254 | gen6_gt_check_fifodbg(dev_priv); \ |
| 1255 | } \ |
Ben Widawsky | b4c145c | 2012-08-20 16:15:14 -0700 | [diff] [blame] | 1256 | if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ |
| 1257 | DRM_ERROR("Unclaimed write to %x\n", reg); \ |
| 1258 | writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT); \ |
| 1259 | } \ |
Andi Kleen | f700088 | 2011-10-13 16:08:51 -0700 | [diff] [blame] | 1260 | } |
| 1261 | __i915_write(8, b) |
| 1262 | __i915_write(16, w) |
| 1263 | __i915_write(32, l) |
| 1264 | __i915_write(64, q) |
| 1265 | #undef __i915_write |
Ben Widawsky | c0c7bab | 2012-07-12 11:01:05 -0700 | [diff] [blame] | 1266 | |
| 1267 | static const struct register_whitelist { |
| 1268 | uint64_t offset; |
| 1269 | uint32_t size; |
| 1270 | uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
| 1271 | } whitelist[] = { |
| 1272 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 }, |
| 1273 | }; |
| 1274 | |
| 1275 | int i915_reg_read_ioctl(struct drm_device *dev, |
| 1276 | void *data, struct drm_file *file) |
| 1277 | { |
| 1278 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1279 | struct drm_i915_reg_read *reg = data; |
| 1280 | struct register_whitelist const *entry = whitelist; |
| 1281 | int i; |
| 1282 | |
| 1283 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { |
| 1284 | if (entry->offset == reg->offset && |
| 1285 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) |
| 1286 | break; |
| 1287 | } |
| 1288 | |
| 1289 | if (i == ARRAY_SIZE(whitelist)) |
| 1290 | return -EINVAL; |
| 1291 | |
| 1292 | switch (entry->size) { |
| 1293 | case 8: |
| 1294 | reg->val = I915_READ64(reg->offset); |
| 1295 | break; |
| 1296 | case 4: |
| 1297 | reg->val = I915_READ(reg->offset); |
| 1298 | break; |
| 1299 | case 2: |
| 1300 | reg->val = I915_READ16(reg->offset); |
| 1301 | break; |
| 1302 | case 1: |
| 1303 | reg->val = I915_READ8(reg->offset); |
| 1304 | break; |
| 1305 | default: |
| 1306 | WARN_ON(1); |
| 1307 | return -EINVAL; |
| 1308 | } |
| 1309 | |
| 1310 | return 0; |
| 1311 | } |