Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008-2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Zou Nan hai <nanhai.zou@intel.com> |
| 26 | * Xiang Hai hao<haihao.xiang@intel.com> |
| 27 | * |
| 28 | */ |
| 29 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/drmP.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 31 | #include "i915_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 32 | #include <drm/i915_drm.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 33 | #include "i915_trace.h" |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 34 | #include "intel_drv.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 35 | |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 36 | static inline int ring_space(struct intel_ring_buffer *ring) |
| 37 | { |
Ville Syrjälä | 633cf8f | 2012-12-03 18:43:32 +0200 | [diff] [blame] | 38 | int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE); |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 39 | if (space < 0) |
| 40 | space += ring->size; |
| 41 | return space; |
| 42 | } |
| 43 | |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 44 | void __intel_ring_advance(struct intel_ring_buffer *ring) |
| 45 | { |
| 46 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 47 | |
| 48 | ring->tail &= ring->size - 1; |
| 49 | if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring)) |
| 50 | return; |
| 51 | ring->write_tail(ring, ring->tail); |
| 52 | } |
| 53 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 54 | static int |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 55 | gen2_render_ring_flush(struct intel_ring_buffer *ring, |
| 56 | u32 invalidate_domains, |
| 57 | u32 flush_domains) |
| 58 | { |
| 59 | u32 cmd; |
| 60 | int ret; |
| 61 | |
| 62 | cmd = MI_FLUSH; |
Daniel Vetter | 31b14c9 | 2012-04-19 16:45:22 +0200 | [diff] [blame] | 63 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 64 | cmd |= MI_NO_WRITE_FLUSH; |
| 65 | |
| 66 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 67 | cmd |= MI_READ_FLUSH; |
| 68 | |
| 69 | ret = intel_ring_begin(ring, 2); |
| 70 | if (ret) |
| 71 | return ret; |
| 72 | |
| 73 | intel_ring_emit(ring, cmd); |
| 74 | intel_ring_emit(ring, MI_NOOP); |
| 75 | intel_ring_advance(ring); |
| 76 | |
| 77 | return 0; |
| 78 | } |
| 79 | |
| 80 | static int |
| 81 | gen4_render_ring_flush(struct intel_ring_buffer *ring, |
| 82 | u32 invalidate_domains, |
| 83 | u32 flush_domains) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 84 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 85 | struct drm_device *dev = ring->dev; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 86 | u32 cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 87 | int ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 88 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 89 | /* |
| 90 | * read/write caches: |
| 91 | * |
| 92 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 93 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 94 | * also flushed at 2d versus 3d pipeline switches. |
| 95 | * |
| 96 | * read-only caches: |
| 97 | * |
| 98 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 99 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 100 | * |
| 101 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 102 | * |
| 103 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 104 | * invalidated when MI_EXE_FLUSH is set. |
| 105 | * |
| 106 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 107 | * invalidated with every MI_FLUSH. |
| 108 | * |
| 109 | * TLBs: |
| 110 | * |
| 111 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 112 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 113 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 114 | * are flushed at any MI_FLUSH. |
| 115 | */ |
| 116 | |
| 117 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 118 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 119 | cmd &= ~MI_NO_WRITE_FLUSH; |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 120 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 121 | cmd |= MI_EXE_FLUSH; |
| 122 | |
| 123 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
| 124 | (IS_G4X(dev) || IS_GEN5(dev))) |
| 125 | cmd |= MI_INVALIDATE_ISP; |
| 126 | |
| 127 | ret = intel_ring_begin(ring, 2); |
| 128 | if (ret) |
| 129 | return ret; |
| 130 | |
| 131 | intel_ring_emit(ring, cmd); |
| 132 | intel_ring_emit(ring, MI_NOOP); |
| 133 | intel_ring_advance(ring); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 134 | |
| 135 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 136 | } |
| 137 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 138 | /** |
| 139 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
| 140 | * implementing two workarounds on gen6. From section 1.4.7.1 |
| 141 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: |
| 142 | * |
| 143 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those |
| 144 | * produced by non-pipelined state commands), software needs to first |
| 145 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != |
| 146 | * 0. |
| 147 | * |
| 148 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable |
| 149 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. |
| 150 | * |
| 151 | * And the workaround for these two requires this workaround first: |
| 152 | * |
| 153 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent |
| 154 | * BEFORE the pipe-control with a post-sync op and no write-cache |
| 155 | * flushes. |
| 156 | * |
| 157 | * And this last workaround is tricky because of the requirements on |
| 158 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM |
| 159 | * volume 2 part 1: |
| 160 | * |
| 161 | * "1 of the following must also be set: |
| 162 | * - Render Target Cache Flush Enable ([12] of DW1) |
| 163 | * - Depth Cache Flush Enable ([0] of DW1) |
| 164 | * - Stall at Pixel Scoreboard ([1] of DW1) |
| 165 | * - Depth Stall ([13] of DW1) |
| 166 | * - Post-Sync Operation ([13] of DW1) |
| 167 | * - Notify Enable ([8] of DW1)" |
| 168 | * |
| 169 | * The cache flushes require the workaround flush that triggered this |
| 170 | * one, so we can't use it. Depth stall would trigger the same. |
| 171 | * Post-sync nonzero is what triggered this second workaround, so we |
| 172 | * can't use that one either. Notify enable is IRQs, which aren't |
| 173 | * really our business. That leaves only stall at scoreboard. |
| 174 | */ |
| 175 | static int |
| 176 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) |
| 177 | { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 178 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 179 | int ret; |
| 180 | |
| 181 | |
| 182 | ret = intel_ring_begin(ring, 6); |
| 183 | if (ret) |
| 184 | return ret; |
| 185 | |
| 186 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 187 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 188 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 189 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 190 | intel_ring_emit(ring, 0); /* low dword */ |
| 191 | intel_ring_emit(ring, 0); /* high dword */ |
| 192 | intel_ring_emit(ring, MI_NOOP); |
| 193 | intel_ring_advance(ring); |
| 194 | |
| 195 | ret = intel_ring_begin(ring, 6); |
| 196 | if (ret) |
| 197 | return ret; |
| 198 | |
| 199 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 200 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); |
| 201 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 202 | intel_ring_emit(ring, 0); |
| 203 | intel_ring_emit(ring, 0); |
| 204 | intel_ring_emit(ring, MI_NOOP); |
| 205 | intel_ring_advance(ring); |
| 206 | |
| 207 | return 0; |
| 208 | } |
| 209 | |
| 210 | static int |
| 211 | gen6_render_ring_flush(struct intel_ring_buffer *ring, |
| 212 | u32 invalidate_domains, u32 flush_domains) |
| 213 | { |
| 214 | u32 flags = 0; |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 215 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 216 | int ret; |
| 217 | |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 218 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
| 219 | ret = intel_emit_post_sync_nonzero_flush(ring); |
| 220 | if (ret) |
| 221 | return ret; |
| 222 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 223 | /* Just flush everything. Experiments have shown that reducing the |
| 224 | * number of bits based on the write domains has little performance |
| 225 | * impact. |
| 226 | */ |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 227 | if (flush_domains) { |
| 228 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 229 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 230 | /* |
| 231 | * Ensure that any following seqno writes only happen |
| 232 | * when the render cache is indeed flushed. |
| 233 | */ |
Daniel Vetter | 97f209b | 2012-06-28 09:48:42 +0200 | [diff] [blame] | 234 | flags |= PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 235 | } |
| 236 | if (invalidate_domains) { |
| 237 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 238 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 239 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 240 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 241 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 242 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 243 | /* |
| 244 | * TLB invalidate requires a post-sync write. |
| 245 | */ |
Jesse Barnes | 3ac7831 | 2012-10-25 12:15:47 -0700 | [diff] [blame] | 246 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 247 | } |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 248 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 249 | ret = intel_ring_begin(ring, 4); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 250 | if (ret) |
| 251 | return ret; |
| 252 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 253 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 254 | intel_ring_emit(ring, flags); |
| 255 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 256 | intel_ring_emit(ring, 0); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 257 | intel_ring_advance(ring); |
| 258 | |
| 259 | return 0; |
| 260 | } |
| 261 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 262 | static int |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 263 | gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) |
| 264 | { |
| 265 | int ret; |
| 266 | |
| 267 | ret = intel_ring_begin(ring, 4); |
| 268 | if (ret) |
| 269 | return ret; |
| 270 | |
| 271 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
| 272 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 273 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 274 | intel_ring_emit(ring, 0); |
| 275 | intel_ring_emit(ring, 0); |
| 276 | intel_ring_advance(ring); |
| 277 | |
| 278 | return 0; |
| 279 | } |
| 280 | |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 281 | static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value) |
| 282 | { |
| 283 | int ret; |
| 284 | |
| 285 | if (!ring->fbc_dirty) |
| 286 | return 0; |
| 287 | |
| 288 | ret = intel_ring_begin(ring, 4); |
| 289 | if (ret) |
| 290 | return ret; |
| 291 | intel_ring_emit(ring, MI_NOOP); |
| 292 | /* WaFbcNukeOn3DBlt:ivb/hsw */ |
| 293 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 294 | intel_ring_emit(ring, MSG_FBC_REND_STATE); |
| 295 | intel_ring_emit(ring, value); |
| 296 | intel_ring_advance(ring); |
| 297 | |
| 298 | ring->fbc_dirty = false; |
| 299 | return 0; |
| 300 | } |
| 301 | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 302 | static int |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 303 | gen7_render_ring_flush(struct intel_ring_buffer *ring, |
| 304 | u32 invalidate_domains, u32 flush_domains) |
| 305 | { |
| 306 | u32 flags = 0; |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 307 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 308 | int ret; |
| 309 | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 310 | /* |
| 311 | * Ensure that any following seqno writes only happen when the render |
| 312 | * cache is indeed flushed. |
| 313 | * |
| 314 | * Workaround: 4th PIPE_CONTROL command (except the ones with only |
| 315 | * read-cache invalidate bits set) must have the CS_STALL bit set. We |
| 316 | * don't try to be clever and just set it unconditionally. |
| 317 | */ |
| 318 | flags |= PIPE_CONTROL_CS_STALL; |
| 319 | |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 320 | /* Just flush everything. Experiments have shown that reducing the |
| 321 | * number of bits based on the write domains has little performance |
| 322 | * impact. |
| 323 | */ |
| 324 | if (flush_domains) { |
| 325 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 326 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 327 | } |
| 328 | if (invalidate_domains) { |
| 329 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 330 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 331 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 332 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 333 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 334 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 335 | /* |
| 336 | * TLB invalidate requires a post-sync write. |
| 337 | */ |
| 338 | flags |= PIPE_CONTROL_QW_WRITE; |
Ville Syrjälä | b9e1faa | 2013-02-14 21:53:51 +0200 | [diff] [blame] | 339 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 340 | |
| 341 | /* Workaround: we must issue a pipe_control with CS-stall bit |
| 342 | * set before a pipe_control command that has the state cache |
| 343 | * invalidate bit set. */ |
| 344 | gen7_render_ring_cs_stall_wa(ring); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 345 | } |
| 346 | |
| 347 | ret = intel_ring_begin(ring, 4); |
| 348 | if (ret) |
| 349 | return ret; |
| 350 | |
| 351 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
| 352 | intel_ring_emit(ring, flags); |
Ville Syrjälä | b9e1faa | 2013-02-14 21:53:51 +0200 | [diff] [blame] | 353 | intel_ring_emit(ring, scratch_addr); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 354 | intel_ring_emit(ring, 0); |
| 355 | intel_ring_advance(ring); |
| 356 | |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 357 | if (flush_domains) |
| 358 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
| 359 | |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 360 | return 0; |
| 361 | } |
| 362 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 363 | static void ring_write_tail(struct intel_ring_buffer *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 364 | u32 value) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 365 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 366 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 367 | I915_WRITE_TAIL(ring, value); |
Xiang, Haihao | d46eefa | 2010-09-16 10:43:12 +0800 | [diff] [blame] | 368 | } |
| 369 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 370 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 371 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 372 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 373 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? |
Daniel Vetter | 3d281d8 | 2010-09-24 21:14:22 +0200 | [diff] [blame] | 374 | RING_ACTHD(ring->mmio_base) : ACTHD; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 375 | |
| 376 | return I915_READ(acthd_reg); |
| 377 | } |
| 378 | |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 379 | static void ring_setup_phys_status_page(struct intel_ring_buffer *ring) |
| 380 | { |
| 381 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 382 | u32 addr; |
| 383 | |
| 384 | addr = dev_priv->status_page_dmah->busaddr; |
| 385 | if (INTEL_INFO(ring->dev)->gen >= 4) |
| 386 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
| 387 | I915_WRITE(HWS_PGA, addr); |
| 388 | } |
| 389 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 390 | static int init_ring_common(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 391 | { |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 392 | struct drm_device *dev = ring->dev; |
| 393 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 394 | struct drm_i915_gem_object *obj = ring->obj; |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 395 | int ret = 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 396 | u32 head; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 397 | |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 398 | if (HAS_FORCE_WAKE(dev)) |
| 399 | gen6_gt_force_wake_get(dev_priv); |
| 400 | |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 401 | if (I915_NEED_GFX_HWS(dev)) |
| 402 | intel_ring_setup_status_page(ring); |
| 403 | else |
| 404 | ring_setup_phys_status_page(ring); |
| 405 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 406 | /* Stop the ring if it's running. */ |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 407 | I915_WRITE_CTL(ring, 0); |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 408 | I915_WRITE_HEAD(ring, 0); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 409 | ring->write_tail(ring, 0); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 410 | |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 411 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 412 | |
| 413 | /* G45 ring initialization fails to reset head to zero */ |
| 414 | if (head != 0) { |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 415 | DRM_DEBUG_KMS("%s head not reset to zero " |
| 416 | "ctl %08x head %08x tail %08x start %08x\n", |
| 417 | ring->name, |
| 418 | I915_READ_CTL(ring), |
| 419 | I915_READ_HEAD(ring), |
| 420 | I915_READ_TAIL(ring), |
| 421 | I915_READ_START(ring)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 422 | |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 423 | I915_WRITE_HEAD(ring, 0); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 424 | |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 425 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
| 426 | DRM_ERROR("failed to set %s head to zero " |
| 427 | "ctl %08x head %08x tail %08x start %08x\n", |
| 428 | ring->name, |
| 429 | I915_READ_CTL(ring), |
| 430 | I915_READ_HEAD(ring), |
| 431 | I915_READ_TAIL(ring), |
| 432 | I915_READ_START(ring)); |
| 433 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 434 | } |
| 435 | |
Daniel Vetter | 0d8957c | 2012-08-07 09:54:14 +0200 | [diff] [blame] | 436 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
| 437 | * registers with the above sequence (the readback of the HEAD registers |
| 438 | * also enforces ordering), otherwise the hw might lose the new ring |
| 439 | * register values. */ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 440 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 441 | I915_WRITE_CTL(ring, |
Chris Wilson | ae69b42 | 2010-11-07 11:45:52 +0000 | [diff] [blame] | 442 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
Chris Wilson | 5d031e5 | 2012-02-08 13:34:13 +0000 | [diff] [blame] | 443 | | RING_VALID); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 444 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 445 | /* If the head is still not zero, the ring is dead */ |
Sean Paul | f01db98 | 2012-03-16 12:43:22 -0400 | [diff] [blame] | 446 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 447 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
Sean Paul | f01db98 | 2012-03-16 12:43:22 -0400 | [diff] [blame] | 448 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
Chris Wilson | e74cfed | 2010-11-09 10:16:56 +0000 | [diff] [blame] | 449 | DRM_ERROR("%s initialization failed " |
| 450 | "ctl %08x head %08x tail %08x start %08x\n", |
| 451 | ring->name, |
| 452 | I915_READ_CTL(ring), |
| 453 | I915_READ_HEAD(ring), |
| 454 | I915_READ_TAIL(ring), |
| 455 | I915_READ_START(ring)); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 456 | ret = -EIO; |
| 457 | goto out; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 458 | } |
| 459 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 460 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
| 461 | i915_kernel_lost_context(ring->dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 462 | else { |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 463 | ring->head = I915_READ_HEAD(ring); |
Daniel Vetter | 870e86d | 2010-08-02 16:29:44 +0200 | [diff] [blame] | 464 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 465 | ring->space = ring_space(ring); |
Chris Wilson | c3b2003 | 2012-05-28 22:33:02 +0100 | [diff] [blame] | 466 | ring->last_retired_head = -1; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 467 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 468 | |
Chris Wilson | 50f018d | 2013-06-10 11:20:19 +0100 | [diff] [blame] | 469 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
| 470 | |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 471 | out: |
| 472 | if (HAS_FORCE_WAKE(dev)) |
| 473 | gen6_gt_force_wake_put(dev_priv); |
| 474 | |
| 475 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 476 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 477 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 478 | static int |
| 479 | init_pipe_control(struct intel_ring_buffer *ring) |
| 480 | { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 481 | int ret; |
| 482 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 483 | if (ring->scratch.obj) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 484 | return 0; |
| 485 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 486 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
| 487 | if (ring->scratch.obj == NULL) { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 488 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 489 | ret = -ENOMEM; |
| 490 | goto err; |
| 491 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 492 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 493 | i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 494 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 495 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, true, false); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 496 | if (ret) |
| 497 | goto err_unref; |
| 498 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 499 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
| 500 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); |
| 501 | if (ring->scratch.cpu_page == NULL) { |
Wei Yongjun | 56b085a | 2013-05-28 17:51:44 +0800 | [diff] [blame] | 502 | ret = -ENOMEM; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 503 | goto err_unpin; |
Wei Yongjun | 56b085a | 2013-05-28 17:51:44 +0800 | [diff] [blame] | 504 | } |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 505 | |
Ville Syrjälä | 2b1086c | 2013-02-12 22:01:38 +0200 | [diff] [blame] | 506 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 507 | ring->name, ring->scratch.gtt_offset); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 508 | return 0; |
| 509 | |
| 510 | err_unpin: |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 511 | i915_gem_object_unpin(ring->scratch.obj); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 512 | err_unref: |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 513 | drm_gem_object_unreference(&ring->scratch.obj->base); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 514 | err: |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 515 | return ret; |
| 516 | } |
| 517 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 518 | static int init_render_ring(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 519 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 520 | struct drm_device *dev = ring->dev; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 521 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 522 | int ret = init_ring_common(ring); |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 523 | |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 524 | if (INTEL_INFO(dev)->gen > 3) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 525 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 526 | |
| 527 | /* We need to disable the AsyncFlip performance optimisations in order |
| 528 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be |
| 529 | * programmed to '1' on all products. |
Damien Lespiau | 8693a82 | 2013-05-03 18:48:11 +0100 | [diff] [blame] | 530 | * |
| 531 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 532 | */ |
| 533 | if (INTEL_INFO(dev)->gen >= 6) |
| 534 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
| 535 | |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 536 | /* Required for the hardware to program scanline values for waiting */ |
| 537 | if (INTEL_INFO(dev)->gen == 6) |
| 538 | I915_WRITE(GFX_MODE, |
| 539 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS)); |
| 540 | |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 541 | if (IS_GEN7(dev)) |
| 542 | I915_WRITE(GFX_MODE_GEN7, |
| 543 | _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | |
| 544 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 545 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 546 | if (INTEL_INFO(dev)->gen >= 5) { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 547 | ret = init_pipe_control(ring); |
| 548 | if (ret) |
| 549 | return ret; |
| 550 | } |
| 551 | |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 552 | if (IS_GEN6(dev)) { |
Kenneth Graunke | 3a69ddd | 2012-04-27 12:44:41 -0700 | [diff] [blame] | 553 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
| 554 | * "If this bit is set, STCunit will have LRA as replacement |
| 555 | * policy. [...] This bit must be reset. LRA replacement |
| 556 | * policy is not supported." |
| 557 | */ |
| 558 | I915_WRITE(CACHE_MODE_0, |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 559 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
Ben Widawsky | 12b0286 | 2012-06-04 14:42:50 -0700 | [diff] [blame] | 560 | |
| 561 | /* This is not explicitly set for GEN6, so read the register. |
| 562 | * see intel_ring_mi_set_context() for why we care. |
| 563 | * TODO: consider explicitly setting the bit for GEN5 |
| 564 | */ |
| 565 | ring->itlb_before_ctx_switch = |
| 566 | !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS); |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 567 | } |
| 568 | |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 569 | if (INTEL_INFO(dev)->gen >= 6) |
| 570 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 571 | |
Ben Widawsky | e1ef7cc | 2012-07-24 20:47:31 -0700 | [diff] [blame] | 572 | if (HAS_L3_GPU_CACHE(dev)) |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame^] | 573 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 574 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 575 | return ret; |
| 576 | } |
| 577 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 578 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
| 579 | { |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 580 | struct drm_device *dev = ring->dev; |
| 581 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 582 | if (ring->scratch.obj == NULL) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 583 | return; |
| 584 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 585 | if (INTEL_INFO(dev)->gen >= 5) { |
| 586 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); |
| 587 | i915_gem_object_unpin(ring->scratch.obj); |
| 588 | } |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 589 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 590 | drm_gem_object_unreference(&ring->scratch.obj->base); |
| 591 | ring->scratch.obj = NULL; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 592 | } |
| 593 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 594 | static void |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 595 | update_mboxes(struct intel_ring_buffer *ring, |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 596 | u32 mmio_offset) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 597 | { |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 598 | /* NB: In order to be able to do semaphore MBOX updates for varying number |
| 599 | * of rings, it's easiest if we round up each individual update to a |
| 600 | * multiple of 2 (since ring updates must always be a multiple of 2) |
| 601 | * even though the actual update only requires 3 dwords. |
| 602 | */ |
| 603 | #define MBOX_UPDATE_DWORDS 4 |
Chris Wilson | 1c8b46f | 2012-11-14 09:15:14 +0000 | [diff] [blame] | 604 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 605 | intel_ring_emit(ring, mmio_offset); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 606 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 607 | intel_ring_emit(ring, MI_NOOP); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 608 | } |
| 609 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 610 | /** |
| 611 | * gen6_add_request - Update the semaphore mailbox registers |
| 612 | * |
| 613 | * @ring - ring that is adding a request |
| 614 | * @seqno - return seqno stuck into the ring |
| 615 | * |
| 616 | * Update the mailbox registers in the *other* rings with the current seqno. |
| 617 | * This acts like a signal in the canonical semaphore. |
| 618 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 619 | static int |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 620 | gen6_add_request(struct intel_ring_buffer *ring) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 621 | { |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 622 | struct drm_device *dev = ring->dev; |
| 623 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 624 | struct intel_ring_buffer *useless; |
| 625 | int i, ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 626 | |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 627 | ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) * |
| 628 | MBOX_UPDATE_DWORDS) + |
| 629 | 4); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 630 | if (ret) |
| 631 | return ret; |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 632 | #undef MBOX_UPDATE_DWORDS |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 633 | |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 634 | for_each_ring(useless, dev_priv, i) { |
| 635 | u32 mbox_reg = ring->signal_mbox[i]; |
| 636 | if (mbox_reg != GEN6_NOSYNC) |
| 637 | update_mboxes(ring, mbox_reg); |
| 638 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 639 | |
| 640 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 641 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 642 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 643 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 644 | __intel_ring_advance(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 645 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 646 | return 0; |
| 647 | } |
| 648 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 649 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
| 650 | u32 seqno) |
| 651 | { |
| 652 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 653 | return dev_priv->last_seqno < seqno; |
| 654 | } |
| 655 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 656 | /** |
| 657 | * intel_ring_sync - sync the waiter to the signaller on seqno |
| 658 | * |
| 659 | * @waiter - ring that is waiting |
| 660 | * @signaller - ring which has, or will signal |
| 661 | * @seqno - seqno which the waiter will block on |
| 662 | */ |
| 663 | static int |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 664 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
| 665 | struct intel_ring_buffer *signaller, |
| 666 | u32 seqno) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 667 | { |
| 668 | int ret; |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 669 | u32 dw1 = MI_SEMAPHORE_MBOX | |
| 670 | MI_SEMAPHORE_COMPARE | |
| 671 | MI_SEMAPHORE_REGISTER; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 672 | |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 673 | /* Throughout all of the GEM code, seqno passed implies our current |
| 674 | * seqno is >= the last seqno executed. However for hardware the |
| 675 | * comparison is strictly greater than. |
| 676 | */ |
| 677 | seqno -= 1; |
| 678 | |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 679 | WARN_ON(signaller->semaphore_register[waiter->id] == |
| 680 | MI_SEMAPHORE_SYNC_INVALID); |
| 681 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 682 | ret = intel_ring_begin(waiter, 4); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 683 | if (ret) |
| 684 | return ret; |
| 685 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 686 | /* If seqno wrap happened, omit the wait with no-ops */ |
| 687 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { |
| 688 | intel_ring_emit(waiter, |
| 689 | dw1 | |
| 690 | signaller->semaphore_register[waiter->id]); |
| 691 | intel_ring_emit(waiter, seqno); |
| 692 | intel_ring_emit(waiter, 0); |
| 693 | intel_ring_emit(waiter, MI_NOOP); |
| 694 | } else { |
| 695 | intel_ring_emit(waiter, MI_NOOP); |
| 696 | intel_ring_emit(waiter, MI_NOOP); |
| 697 | intel_ring_emit(waiter, MI_NOOP); |
| 698 | intel_ring_emit(waiter, MI_NOOP); |
| 699 | } |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 700 | intel_ring_advance(waiter); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 701 | |
| 702 | return 0; |
| 703 | } |
| 704 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 705 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
| 706 | do { \ |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 707 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
| 708 | PIPE_CONTROL_DEPTH_STALL); \ |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 709 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
| 710 | intel_ring_emit(ring__, 0); \ |
| 711 | intel_ring_emit(ring__, 0); \ |
| 712 | } while (0) |
| 713 | |
| 714 | static int |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 715 | pc_render_add_request(struct intel_ring_buffer *ring) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 716 | { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 717 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 718 | int ret; |
| 719 | |
| 720 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
| 721 | * incoherent with writes to memory, i.e. completely fubar, |
| 722 | * so we need to use PIPE_NOTIFY instead. |
| 723 | * |
| 724 | * However, we also need to workaround the qword write |
| 725 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
| 726 | * memory before requesting an interrupt. |
| 727 | */ |
| 728 | ret = intel_ring_begin(ring, 32); |
| 729 | if (ret) |
| 730 | return ret; |
| 731 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 732 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 733 | PIPE_CONTROL_WRITE_FLUSH | |
| 734 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 735 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 736 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 737 | intel_ring_emit(ring, 0); |
| 738 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 739 | scratch_addr += 128; /* write to separate cachelines */ |
| 740 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 741 | scratch_addr += 128; |
| 742 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 743 | scratch_addr += 128; |
| 744 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 745 | scratch_addr += 128; |
| 746 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 747 | scratch_addr += 128; |
| 748 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 749 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 750 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 751 | PIPE_CONTROL_WRITE_FLUSH | |
| 752 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 753 | PIPE_CONTROL_NOTIFY); |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 754 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 755 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 756 | intel_ring_emit(ring, 0); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 757 | __intel_ring_advance(ring); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 758 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 759 | return 0; |
| 760 | } |
| 761 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 762 | static u32 |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 763 | gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 764 | { |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 765 | /* Workaround to force correct ordering between irq and seqno writes on |
| 766 | * ivb (and maybe also on snb) by reading from a CS register (like |
| 767 | * ACTHD) before reading the status page. */ |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 768 | if (!lazy_coherency) |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 769 | intel_ring_get_active_head(ring); |
| 770 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 771 | } |
| 772 | |
| 773 | static u32 |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 774 | ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 775 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 776 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 777 | } |
| 778 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 779 | static void |
| 780 | ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 781 | { |
| 782 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); |
| 783 | } |
| 784 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 785 | static u32 |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 786 | pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 787 | { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 788 | return ring->scratch.cpu_page[0]; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 789 | } |
| 790 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 791 | static void |
| 792 | pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 793 | { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 794 | ring->scratch.cpu_page[0] = seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 795 | } |
| 796 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 797 | static bool |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 798 | gen5_ring_get_irq(struct intel_ring_buffer *ring) |
| 799 | { |
| 800 | struct drm_device *dev = ring->dev; |
| 801 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 802 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 803 | |
| 804 | if (!dev->irq_enabled) |
| 805 | return false; |
| 806 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 807 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 808 | if (ring->irq_refcount++ == 0) |
| 809 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 810 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 811 | |
| 812 | return true; |
| 813 | } |
| 814 | |
| 815 | static void |
| 816 | gen5_ring_put_irq(struct intel_ring_buffer *ring) |
| 817 | { |
| 818 | struct drm_device *dev = ring->dev; |
| 819 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 820 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 821 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 822 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 823 | if (--ring->irq_refcount == 0) |
| 824 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 825 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 826 | } |
| 827 | |
| 828 | static bool |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 829 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 830 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 831 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 832 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 833 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 834 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 835 | if (!dev->irq_enabled) |
| 836 | return false; |
| 837 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 838 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 839 | if (ring->irq_refcount++ == 0) { |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 840 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 841 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 842 | POSTING_READ(IMR); |
| 843 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 844 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 845 | |
| 846 | return true; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 847 | } |
| 848 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 849 | static void |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 850 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 851 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 852 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 853 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 854 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 855 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 856 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 857 | if (--ring->irq_refcount == 0) { |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 858 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 859 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 860 | POSTING_READ(IMR); |
| 861 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 862 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 863 | } |
| 864 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 865 | static bool |
| 866 | i8xx_ring_get_irq(struct intel_ring_buffer *ring) |
| 867 | { |
| 868 | struct drm_device *dev = ring->dev; |
| 869 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 870 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 871 | |
| 872 | if (!dev->irq_enabled) |
| 873 | return false; |
| 874 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 875 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 876 | if (ring->irq_refcount++ == 0) { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 877 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 878 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 879 | POSTING_READ16(IMR); |
| 880 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 881 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 882 | |
| 883 | return true; |
| 884 | } |
| 885 | |
| 886 | static void |
| 887 | i8xx_ring_put_irq(struct intel_ring_buffer *ring) |
| 888 | { |
| 889 | struct drm_device *dev = ring->dev; |
| 890 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 891 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 892 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 893 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 894 | if (--ring->irq_refcount == 0) { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 895 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 896 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 897 | POSTING_READ16(IMR); |
| 898 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 899 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 900 | } |
| 901 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 902 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 903 | { |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 904 | struct drm_device *dev = ring->dev; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 905 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 906 | u32 mmio = 0; |
| 907 | |
| 908 | /* The ring status page addresses are no longer next to the rest of |
| 909 | * the ring registers as of gen7. |
| 910 | */ |
| 911 | if (IS_GEN7(dev)) { |
| 912 | switch (ring->id) { |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 913 | case RCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 914 | mmio = RENDER_HWS_PGA_GEN7; |
| 915 | break; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 916 | case BCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 917 | mmio = BLT_HWS_PGA_GEN7; |
| 918 | break; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 919 | case VCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 920 | mmio = BSD_HWS_PGA_GEN7; |
| 921 | break; |
Ben Widawsky | 4a3dd19 | 2013-05-28 19:22:19 -0700 | [diff] [blame] | 922 | case VECS: |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 923 | mmio = VEBOX_HWS_PGA_GEN7; |
| 924 | break; |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 925 | } |
| 926 | } else if (IS_GEN6(ring->dev)) { |
| 927 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); |
| 928 | } else { |
| 929 | mmio = RING_HWS_PGA(ring->mmio_base); |
| 930 | } |
| 931 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 932 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
| 933 | POSTING_READ(mmio); |
Chris Wilson | 884020b | 2013-08-06 19:01:14 +0100 | [diff] [blame] | 934 | |
| 935 | /* Flush the TLB for this page */ |
| 936 | if (INTEL_INFO(dev)->gen >= 6) { |
| 937 | u32 reg = RING_INSTPM(ring->mmio_base); |
| 938 | I915_WRITE(reg, |
| 939 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | |
| 940 | INSTPM_SYNC_FLUSH)); |
| 941 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, |
| 942 | 1000)) |
| 943 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
| 944 | ring->name); |
| 945 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 946 | } |
| 947 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 948 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 949 | bsd_ring_flush(struct intel_ring_buffer *ring, |
| 950 | u32 invalidate_domains, |
| 951 | u32 flush_domains) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 952 | { |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 953 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 954 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 955 | ret = intel_ring_begin(ring, 2); |
| 956 | if (ret) |
| 957 | return ret; |
| 958 | |
| 959 | intel_ring_emit(ring, MI_FLUSH); |
| 960 | intel_ring_emit(ring, MI_NOOP); |
| 961 | intel_ring_advance(ring); |
| 962 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 963 | } |
| 964 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 965 | static int |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 966 | i9xx_add_request(struct intel_ring_buffer *ring) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 967 | { |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 968 | int ret; |
| 969 | |
| 970 | ret = intel_ring_begin(ring, 4); |
| 971 | if (ret) |
| 972 | return ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 973 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 974 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 975 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 976 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 977 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 978 | __intel_ring_advance(ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 979 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 980 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 981 | } |
| 982 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 983 | static bool |
Ben Widawsky | 25c0630 | 2012-03-29 19:11:27 -0700 | [diff] [blame] | 984 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 985 | { |
| 986 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 987 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 988 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 989 | |
| 990 | if (!dev->irq_enabled) |
| 991 | return false; |
| 992 | |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 993 | /* It looks like we need to prevent the gt from suspending while waiting |
| 994 | * for an notifiy irq, otherwise irqs seem to get lost on at least the |
| 995 | * blt/bsd rings on ivb. */ |
Daniel Vetter | 99ffa16 | 2012-01-25 14:04:00 +0100 | [diff] [blame] | 996 | gen6_gt_force_wake_get(dev_priv); |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 997 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 998 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 999 | if (ring->irq_refcount++ == 0) { |
Ben Widawsky | e1ef7cc | 2012-07-24 20:47:31 -0700 | [diff] [blame] | 1000 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1001 | I915_WRITE_IMR(ring, |
| 1002 | ~(ring->irq_enable_mask | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame^] | 1003 | GT_PARITY_ERROR(dev))); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 1004 | else |
| 1005 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 1006 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1007 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1008 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1009 | |
| 1010 | return true; |
| 1011 | } |
| 1012 | |
| 1013 | static void |
Ben Widawsky | 25c0630 | 2012-03-29 19:11:27 -0700 | [diff] [blame] | 1014 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1015 | { |
| 1016 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 1017 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1018 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1019 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1020 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1021 | if (--ring->irq_refcount == 0) { |
Ben Widawsky | e1ef7cc | 2012-07-24 20:47:31 -0700 | [diff] [blame] | 1022 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame^] | 1023 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 1024 | else |
| 1025 | I915_WRITE_IMR(ring, ~0); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 1026 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1027 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1028 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1029 | |
Daniel Vetter | 99ffa16 | 2012-01-25 14:04:00 +0100 | [diff] [blame] | 1030 | gen6_gt_force_wake_put(dev_priv); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1031 | } |
| 1032 | |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1033 | static bool |
| 1034 | hsw_vebox_get_irq(struct intel_ring_buffer *ring) |
| 1035 | { |
| 1036 | struct drm_device *dev = ring->dev; |
| 1037 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1038 | unsigned long flags; |
| 1039 | |
| 1040 | if (!dev->irq_enabled) |
| 1041 | return false; |
| 1042 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1043 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1044 | if (ring->irq_refcount++ == 0) { |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1045 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 1046 | snb_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1047 | } |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1048 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1049 | |
| 1050 | return true; |
| 1051 | } |
| 1052 | |
| 1053 | static void |
| 1054 | hsw_vebox_put_irq(struct intel_ring_buffer *ring) |
| 1055 | { |
| 1056 | struct drm_device *dev = ring->dev; |
| 1057 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1058 | unsigned long flags; |
| 1059 | |
| 1060 | if (!dev->irq_enabled) |
| 1061 | return; |
| 1062 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1063 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1064 | if (--ring->irq_refcount == 0) { |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1065 | I915_WRITE_IMR(ring, ~0); |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 1066 | snb_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1067 | } |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1068 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1069 | } |
| 1070 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1071 | static int |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1072 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1073 | u32 offset, u32 length, |
| 1074 | unsigned flags) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1075 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1076 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1077 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1078 | ret = intel_ring_begin(ring, 2); |
| 1079 | if (ret) |
| 1080 | return ret; |
| 1081 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1082 | intel_ring_emit(ring, |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 1083 | MI_BATCH_BUFFER_START | |
| 1084 | MI_BATCH_GTT | |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1085 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1086 | intel_ring_emit(ring, offset); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1087 | intel_ring_advance(ring); |
| 1088 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1089 | return 0; |
| 1090 | } |
| 1091 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1092 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
| 1093 | #define I830_BATCH_LIMIT (256*1024) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1094 | static int |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1095 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1096 | u32 offset, u32 len, |
| 1097 | unsigned flags) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1098 | { |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1099 | int ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1100 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1101 | if (flags & I915_DISPATCH_PINNED) { |
| 1102 | ret = intel_ring_begin(ring, 4); |
| 1103 | if (ret) |
| 1104 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1105 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1106 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 1107 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
| 1108 | intel_ring_emit(ring, offset + len - 8); |
| 1109 | intel_ring_emit(ring, MI_NOOP); |
| 1110 | intel_ring_advance(ring); |
| 1111 | } else { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 1112 | u32 cs_offset = ring->scratch.gtt_offset; |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1113 | |
| 1114 | if (len > I830_BATCH_LIMIT) |
| 1115 | return -ENOSPC; |
| 1116 | |
| 1117 | ret = intel_ring_begin(ring, 9+3); |
| 1118 | if (ret) |
| 1119 | return ret; |
| 1120 | /* Blit the batch (which has now all relocs applied) to the stable batch |
| 1121 | * scratch bo area (so that the CS never stumbles over its tlb |
| 1122 | * invalidation bug) ... */ |
| 1123 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | |
| 1124 | XY_SRC_COPY_BLT_WRITE_ALPHA | |
| 1125 | XY_SRC_COPY_BLT_WRITE_RGB); |
| 1126 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); |
| 1127 | intel_ring_emit(ring, 0); |
| 1128 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); |
| 1129 | intel_ring_emit(ring, cs_offset); |
| 1130 | intel_ring_emit(ring, 0); |
| 1131 | intel_ring_emit(ring, 4096); |
| 1132 | intel_ring_emit(ring, offset); |
| 1133 | intel_ring_emit(ring, MI_FLUSH); |
| 1134 | |
| 1135 | /* ... and execute it. */ |
| 1136 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 1137 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
| 1138 | intel_ring_emit(ring, cs_offset + len - 8); |
| 1139 | intel_ring_advance(ring); |
| 1140 | } |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1141 | |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1142 | return 0; |
| 1143 | } |
| 1144 | |
| 1145 | static int |
| 1146 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1147 | u32 offset, u32 len, |
| 1148 | unsigned flags) |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1149 | { |
| 1150 | int ret; |
| 1151 | |
| 1152 | ret = intel_ring_begin(ring, 2); |
| 1153 | if (ret) |
| 1154 | return ret; |
| 1155 | |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 1156 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1157 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1158 | intel_ring_advance(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1159 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1160 | return 0; |
| 1161 | } |
| 1162 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1163 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1164 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1165 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1166 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1167 | obj = ring->status_page.obj; |
| 1168 | if (obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1169 | return; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1170 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1171 | kunmap(sg_page(obj->pages->sgl)); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1172 | i915_gem_object_unpin(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1173 | drm_gem_object_unreference(&obj->base); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1174 | ring->status_page.obj = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1175 | } |
| 1176 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1177 | static int init_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1178 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1179 | struct drm_device *dev = ring->dev; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1180 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1181 | int ret; |
| 1182 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1183 | obj = i915_gem_alloc_object(dev, 4096); |
| 1184 | if (obj == NULL) { |
| 1185 | DRM_ERROR("Failed to allocate status page\n"); |
| 1186 | ret = -ENOMEM; |
| 1187 | goto err; |
| 1188 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 1189 | |
| 1190 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1191 | |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 1192 | ret = i915_gem_obj_ggtt_pin(obj, 4096, true, false); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1193 | if (ret != 0) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1194 | goto err_unref; |
| 1195 | } |
| 1196 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1197 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1198 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1199 | if (ring->status_page.page_addr == NULL) { |
Ben Widawsky | 2e6c21e | 2012-07-12 23:16:12 -0700 | [diff] [blame] | 1200 | ret = -ENOMEM; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1201 | goto err_unpin; |
| 1202 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1203 | ring->status_page.obj = obj; |
| 1204 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1205 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1206 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
| 1207 | ring->name, ring->status_page.gfx_addr); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1208 | |
| 1209 | return 0; |
| 1210 | |
| 1211 | err_unpin: |
| 1212 | i915_gem_object_unpin(obj); |
| 1213 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1214 | drm_gem_object_unreference(&obj->base); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1215 | err: |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1216 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1217 | } |
| 1218 | |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 1219 | static int init_phys_status_page(struct intel_ring_buffer *ring) |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1220 | { |
| 1221 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1222 | |
| 1223 | if (!dev_priv->status_page_dmah) { |
| 1224 | dev_priv->status_page_dmah = |
| 1225 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); |
| 1226 | if (!dev_priv->status_page_dmah) |
| 1227 | return -ENOMEM; |
| 1228 | } |
| 1229 | |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1230 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 1231 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
| 1232 | |
| 1233 | return 0; |
| 1234 | } |
| 1235 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 1236 | static int intel_init_ring_buffer(struct drm_device *dev, |
| 1237 | struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1238 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1239 | struct drm_i915_gem_object *obj; |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1240 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1241 | int ret; |
| 1242 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1243 | ring->dev = dev; |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1244 | INIT_LIST_HEAD(&ring->active_list); |
| 1245 | INIT_LIST_HEAD(&ring->request_list); |
Daniel Vetter | dfc9ef2 | 2012-04-11 22:12:47 +0200 | [diff] [blame] | 1246 | ring->size = 32 * PAGE_SIZE; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1247 | memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno)); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 1248 | |
Chris Wilson | b259f67 | 2011-03-29 13:19:09 +0100 | [diff] [blame] | 1249 | init_waitqueue_head(&ring->irq_queue); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1250 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1251 | if (I915_NEED_GFX_HWS(dev)) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1252 | ret = init_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1253 | if (ret) |
| 1254 | return ret; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1255 | } else { |
| 1256 | BUG_ON(ring->id != RCS); |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 1257 | ret = init_phys_status_page(ring); |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1258 | if (ret) |
| 1259 | return ret; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1260 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1261 | |
Chris Wilson | ebc052e | 2012-11-15 11:32:28 +0000 | [diff] [blame] | 1262 | obj = NULL; |
| 1263 | if (!HAS_LLC(dev)) |
| 1264 | obj = i915_gem_object_create_stolen(dev, ring->size); |
| 1265 | if (obj == NULL) |
| 1266 | obj = i915_gem_alloc_object(dev, ring->size); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1267 | if (obj == NULL) { |
| 1268 | DRM_ERROR("Failed to allocate ringbuffer\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1269 | ret = -ENOMEM; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1270 | goto err_hws; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1271 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1272 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1273 | ring->obj = obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1274 | |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 1275 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, true, false); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1276 | if (ret) |
| 1277 | goto err_unref; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1278 | |
Chris Wilson | 3eef891 | 2012-06-04 17:05:40 +0100 | [diff] [blame] | 1279 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 1280 | if (ret) |
| 1281 | goto err_unpin; |
| 1282 | |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1283 | ring->virtual_start = |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1284 | ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj), |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1285 | ring->size); |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1286 | if (ring->virtual_start == NULL) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1287 | DRM_ERROR("Failed to map ringbuffer.\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1288 | ret = -EINVAL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1289 | goto err_unpin; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1290 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1291 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1292 | ret = ring->init(ring); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1293 | if (ret) |
| 1294 | goto err_unmap; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1295 | |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1296 | /* Workaround an erratum on the i830 which causes a hang if |
| 1297 | * the TAIL pointer points to within the last 2 cachelines |
| 1298 | * of the buffer. |
| 1299 | */ |
| 1300 | ring->effective_size = ring->size; |
Chris Wilson | 27c1cbd | 2012-04-09 13:59:46 +0100 | [diff] [blame] | 1301 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1302 | ring->effective_size -= 128; |
| 1303 | |
Chris Wilson | c584fe4 | 2010-10-29 18:15:52 +0100 | [diff] [blame] | 1304 | return 0; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1305 | |
| 1306 | err_unmap: |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1307 | iounmap(ring->virtual_start); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1308 | err_unpin: |
| 1309 | i915_gem_object_unpin(obj); |
| 1310 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1311 | drm_gem_object_unreference(&obj->base); |
| 1312 | ring->obj = NULL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1313 | err_hws: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1314 | cleanup_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1315 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1316 | } |
| 1317 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1318 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1319 | { |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1320 | struct drm_i915_private *dev_priv; |
| 1321 | int ret; |
| 1322 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1323 | if (ring->obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1324 | return; |
| 1325 | |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1326 | /* Disable the ring buffer. The ring must be idle at this point */ |
| 1327 | dev_priv = ring->dev->dev_private; |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1328 | ret = intel_ring_idle(ring); |
Chris Wilson | 29ee399 | 2011-01-24 16:35:42 +0000 | [diff] [blame] | 1329 | if (ret) |
| 1330 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
| 1331 | ring->name, ret); |
| 1332 | |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1333 | I915_WRITE_CTL(ring, 0); |
| 1334 | |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1335 | iounmap(ring->virtual_start); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1336 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1337 | i915_gem_object_unpin(ring->obj); |
| 1338 | drm_gem_object_unreference(&ring->obj->base); |
| 1339 | ring->obj = NULL; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1340 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1341 | if (ring->cleanup) |
| 1342 | ring->cleanup(ring); |
| 1343 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1344 | cleanup_status_page(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1345 | } |
| 1346 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1347 | static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 1348 | { |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1349 | int ret; |
| 1350 | |
Ben Widawsky | 199b2bc | 2012-05-24 15:03:11 -0700 | [diff] [blame] | 1351 | ret = i915_wait_seqno(ring, seqno); |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 1352 | if (!ret) |
| 1353 | i915_gem_retire_requests_ring(ring); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1354 | |
| 1355 | return ret; |
| 1356 | } |
| 1357 | |
| 1358 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) |
| 1359 | { |
| 1360 | struct drm_i915_gem_request *request; |
| 1361 | u32 seqno = 0; |
| 1362 | int ret; |
| 1363 | |
| 1364 | i915_gem_retire_requests_ring(ring); |
| 1365 | |
| 1366 | if (ring->last_retired_head != -1) { |
| 1367 | ring->head = ring->last_retired_head; |
| 1368 | ring->last_retired_head = -1; |
| 1369 | ring->space = ring_space(ring); |
| 1370 | if (ring->space >= n) |
| 1371 | return 0; |
| 1372 | } |
| 1373 | |
| 1374 | list_for_each_entry(request, &ring->request_list, list) { |
| 1375 | int space; |
| 1376 | |
| 1377 | if (request->tail == -1) |
| 1378 | continue; |
| 1379 | |
Ville Syrjälä | 633cf8f | 2012-12-03 18:43:32 +0200 | [diff] [blame] | 1380 | space = request->tail - (ring->tail + I915_RING_FREE_SPACE); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1381 | if (space < 0) |
| 1382 | space += ring->size; |
| 1383 | if (space >= n) { |
| 1384 | seqno = request->seqno; |
| 1385 | break; |
| 1386 | } |
| 1387 | |
| 1388 | /* Consume this request in case we need more space than |
| 1389 | * is available and so need to prevent a race between |
| 1390 | * updating last_retired_head and direct reads of |
| 1391 | * I915_RING_HEAD. It also provides a nice sanity check. |
| 1392 | */ |
| 1393 | request->tail = -1; |
| 1394 | } |
| 1395 | |
| 1396 | if (seqno == 0) |
| 1397 | return -ENOSPC; |
| 1398 | |
| 1399 | ret = intel_ring_wait_seqno(ring, seqno); |
| 1400 | if (ret) |
| 1401 | return ret; |
| 1402 | |
| 1403 | if (WARN_ON(ring->last_retired_head == -1)) |
| 1404 | return -ENOSPC; |
| 1405 | |
| 1406 | ring->head = ring->last_retired_head; |
| 1407 | ring->last_retired_head = -1; |
| 1408 | ring->space = ring_space(ring); |
| 1409 | if (WARN_ON(ring->space < n)) |
| 1410 | return -ENOSPC; |
| 1411 | |
| 1412 | return 0; |
| 1413 | } |
| 1414 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1415 | static int ring_wait_for_space(struct intel_ring_buffer *ring, int n) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1416 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1417 | struct drm_device *dev = ring->dev; |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1418 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1419 | unsigned long end; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1420 | int ret; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1421 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1422 | ret = intel_ring_wait_request(ring, n); |
| 1423 | if (ret != -ENOSPC) |
| 1424 | return ret; |
| 1425 | |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 1426 | /* force the tail write in case we have been skipping them */ |
| 1427 | __intel_ring_advance(ring); |
| 1428 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1429 | trace_i915_ring_wait_begin(ring); |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 1430 | /* With GEM the hangcheck timer should kick us out of the loop, |
| 1431 | * leaving it early runs the risk of corrupting GEM state (due |
| 1432 | * to running on almost untested codepaths). But on resume |
| 1433 | * timers don't work yet, so prevent a complete hang in that |
| 1434 | * case by choosing an insanely large timeout. */ |
| 1435 | end = jiffies + 60 * HZ; |
Daniel Vetter | e6bfaf8 | 2011-12-14 13:56:59 +0100 | [diff] [blame] | 1436 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1437 | do { |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1438 | ring->head = I915_READ_HEAD(ring); |
| 1439 | ring->space = ring_space(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1440 | if (ring->space >= n) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1441 | trace_i915_ring_wait_end(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1442 | return 0; |
| 1443 | } |
| 1444 | |
| 1445 | if (dev->primary->master) { |
| 1446 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
| 1447 | if (master_priv->sarea_priv) |
| 1448 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
| 1449 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1450 | |
Chris Wilson | e60a0b1 | 2010-10-13 10:09:14 +0100 | [diff] [blame] | 1451 | msleep(1); |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 1452 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1453 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 1454 | dev_priv->mm.interruptible); |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 1455 | if (ret) |
| 1456 | return ret; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1457 | } while (!time_after(jiffies, end)); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1458 | trace_i915_ring_wait_end(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1459 | return -EBUSY; |
| 1460 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1461 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1462 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
| 1463 | { |
| 1464 | uint32_t __iomem *virt; |
| 1465 | int rem = ring->size - ring->tail; |
| 1466 | |
| 1467 | if (ring->space < rem) { |
| 1468 | int ret = ring_wait_for_space(ring, rem); |
| 1469 | if (ret) |
| 1470 | return ret; |
| 1471 | } |
| 1472 | |
| 1473 | virt = ring->virtual_start + ring->tail; |
| 1474 | rem /= 4; |
| 1475 | while (rem--) |
| 1476 | iowrite32(MI_NOOP, virt++); |
| 1477 | |
| 1478 | ring->tail = 0; |
| 1479 | ring->space = ring_space(ring); |
| 1480 | |
| 1481 | return 0; |
| 1482 | } |
| 1483 | |
| 1484 | int intel_ring_idle(struct intel_ring_buffer *ring) |
| 1485 | { |
| 1486 | u32 seqno; |
| 1487 | int ret; |
| 1488 | |
| 1489 | /* We need to add any requests required to flush the objects and ring */ |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1490 | if (ring->outstanding_lazy_seqno) { |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 1491 | ret = i915_add_request(ring, NULL); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1492 | if (ret) |
| 1493 | return ret; |
| 1494 | } |
| 1495 | |
| 1496 | /* Wait upon the last request to be completed */ |
| 1497 | if (list_empty(&ring->request_list)) |
| 1498 | return 0; |
| 1499 | |
| 1500 | seqno = list_entry(ring->request_list.prev, |
| 1501 | struct drm_i915_gem_request, |
| 1502 | list)->seqno; |
| 1503 | |
| 1504 | return i915_wait_seqno(ring, seqno); |
| 1505 | } |
| 1506 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1507 | static int |
| 1508 | intel_ring_alloc_seqno(struct intel_ring_buffer *ring) |
| 1509 | { |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1510 | if (ring->outstanding_lazy_seqno) |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1511 | return 0; |
| 1512 | |
Chris Wilson | 3c0e234 | 2013-09-04 10:45:52 +0100 | [diff] [blame] | 1513 | if (ring->preallocated_lazy_request == NULL) { |
| 1514 | struct drm_i915_gem_request *request; |
| 1515 | |
| 1516 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
| 1517 | if (request == NULL) |
| 1518 | return -ENOMEM; |
| 1519 | |
| 1520 | ring->preallocated_lazy_request = request; |
| 1521 | } |
| 1522 | |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1523 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1524 | } |
| 1525 | |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 1526 | static int __intel_ring_begin(struct intel_ring_buffer *ring, |
| 1527 | int bytes) |
| 1528 | { |
| 1529 | int ret; |
| 1530 | |
| 1531 | if (unlikely(ring->tail + bytes > ring->effective_size)) { |
| 1532 | ret = intel_wrap_ring_buffer(ring); |
| 1533 | if (unlikely(ret)) |
| 1534 | return ret; |
| 1535 | } |
| 1536 | |
| 1537 | if (unlikely(ring->space < bytes)) { |
| 1538 | ret = ring_wait_for_space(ring, bytes); |
| 1539 | if (unlikely(ret)) |
| 1540 | return ret; |
| 1541 | } |
| 1542 | |
| 1543 | ring->space -= bytes; |
| 1544 | return 0; |
| 1545 | } |
| 1546 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1547 | int intel_ring_begin(struct intel_ring_buffer *ring, |
| 1548 | int num_dwords) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1549 | { |
Daniel Vetter | de2b998 | 2012-07-04 22:52:50 +0200 | [diff] [blame] | 1550 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1551 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1552 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1553 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 1554 | dev_priv->mm.interruptible); |
Daniel Vetter | de2b998 | 2012-07-04 22:52:50 +0200 | [diff] [blame] | 1555 | if (ret) |
| 1556 | return ret; |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 1557 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1558 | /* Preallocate the olr before touching the ring */ |
| 1559 | ret = intel_ring_alloc_seqno(ring); |
| 1560 | if (ret) |
| 1561 | return ret; |
| 1562 | |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 1563 | return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1564 | } |
| 1565 | |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 1566 | void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno) |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 1567 | { |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 1568 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 1569 | |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1570 | BUG_ON(ring->outstanding_lazy_seqno); |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 1571 | |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 1572 | if (INTEL_INFO(ring->dev)->gen >= 6) { |
| 1573 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); |
| 1574 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); |
Ben Widawsky | 5020150 | 2013-08-12 16:53:03 -0700 | [diff] [blame] | 1575 | if (HAS_VEBOX(ring->dev)) |
| 1576 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1577 | } |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 1578 | |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 1579 | ring->set_seqno(ring, seqno); |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 1580 | ring->hangcheck.seqno = seqno; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1581 | } |
| 1582 | |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1583 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
| 1584 | u32 value) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1585 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1586 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1587 | |
| 1588 | /* Every tail move must follow the sequence below */ |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1589 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1590 | /* Disable notification that the ring is IDLE. The GT |
| 1591 | * will then assume that it is busy and bring it out of rc6. |
| 1592 | */ |
| 1593 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 1594 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
| 1595 | |
| 1596 | /* Clear the context id. Here be magic! */ |
| 1597 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); |
| 1598 | |
| 1599 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1600 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1601 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
| 1602 | 50)) |
| 1603 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1604 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1605 | /* Now that the ring is fully powered up, update the tail */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1606 | I915_WRITE_TAIL(ring, value); |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1607 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
| 1608 | |
| 1609 | /* Let the ring send IDLE messages to the GT again, |
| 1610 | * and so let it sleep to conserve power when idle. |
| 1611 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1612 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1613 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1614 | } |
| 1615 | |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 1616 | static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring, |
| 1617 | u32 invalidate, u32 flush) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1618 | { |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1619 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1620 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1621 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1622 | ret = intel_ring_begin(ring, 4); |
| 1623 | if (ret) |
| 1624 | return ret; |
| 1625 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1626 | cmd = MI_FLUSH_DW; |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1627 | /* |
| 1628 | * Bspec vol 1c.5 - video engine command streamer: |
| 1629 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 1630 | * operation is complete. This bit is only valid when the |
| 1631 | * Post-Sync Operation field is a value of 1h or 3h." |
| 1632 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1633 | if (invalidate & I915_GEM_GPU_DOMAINS) |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1634 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
| 1635 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1636 | intel_ring_emit(ring, cmd); |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1637 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1638 | intel_ring_emit(ring, 0); |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1639 | intel_ring_emit(ring, MI_NOOP); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1640 | intel_ring_advance(ring); |
| 1641 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1642 | } |
| 1643 | |
| 1644 | static int |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1645 | hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1646 | u32 offset, u32 len, |
| 1647 | unsigned flags) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1648 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1649 | int ret; |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1650 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1651 | ret = intel_ring_begin(ring, 2); |
| 1652 | if (ret) |
| 1653 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1654 | |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1655 | intel_ring_emit(ring, |
| 1656 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | |
| 1657 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); |
| 1658 | /* bit0-7 is the length on GEN6+ */ |
| 1659 | intel_ring_emit(ring, offset); |
| 1660 | intel_ring_advance(ring); |
| 1661 | |
| 1662 | return 0; |
| 1663 | } |
| 1664 | |
| 1665 | static int |
| 1666 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1667 | u32 offset, u32 len, |
| 1668 | unsigned flags) |
| 1669 | { |
| 1670 | int ret; |
| 1671 | |
| 1672 | ret = intel_ring_begin(ring, 2); |
| 1673 | if (ret) |
| 1674 | return ret; |
| 1675 | |
| 1676 | intel_ring_emit(ring, |
| 1677 | MI_BATCH_BUFFER_START | |
| 1678 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1679 | /* bit0-7 is the length on GEN6+ */ |
| 1680 | intel_ring_emit(ring, offset); |
| 1681 | intel_ring_advance(ring); |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1682 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1683 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1684 | } |
| 1685 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1686 | /* Blitter support (SandyBridge+) */ |
| 1687 | |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 1688 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
| 1689 | u32 invalidate, u32 flush) |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1690 | { |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 1691 | struct drm_device *dev = ring->dev; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1692 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1693 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1694 | |
Daniel Vetter | 6a233c7 | 2011-12-14 13:57:07 +0100 | [diff] [blame] | 1695 | ret = intel_ring_begin(ring, 4); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1696 | if (ret) |
| 1697 | return ret; |
| 1698 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1699 | cmd = MI_FLUSH_DW; |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1700 | /* |
| 1701 | * Bspec vol 1c.3 - blitter engine command streamer: |
| 1702 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 1703 | * operation is complete. This bit is only valid when the |
| 1704 | * Post-Sync Operation field is a value of 1h or 3h." |
| 1705 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1706 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1707 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
Daniel Vetter | b3fcabb | 2012-11-04 12:24:47 +0100 | [diff] [blame] | 1708 | MI_FLUSH_DW_OP_STOREDW; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1709 | intel_ring_emit(ring, cmd); |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1710 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1711 | intel_ring_emit(ring, 0); |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1712 | intel_ring_emit(ring, MI_NOOP); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1713 | intel_ring_advance(ring); |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 1714 | |
| 1715 | if (IS_GEN7(dev) && flush) |
| 1716 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); |
| 1717 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1718 | return 0; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1719 | } |
| 1720 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1721 | int intel_init_render_ring_buffer(struct drm_device *dev) |
| 1722 | { |
| 1723 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1724 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1725 | |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1726 | ring->name = "render ring"; |
| 1727 | ring->id = RCS; |
| 1728 | ring->mmio_base = RENDER_RING_BASE; |
| 1729 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1730 | if (INTEL_INFO(dev)->gen >= 6) { |
| 1731 | ring->add_request = gen6_add_request; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 1732 | ring->flush = gen7_render_ring_flush; |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 1733 | if (INTEL_INFO(dev)->gen == 6) |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 1734 | ring->flush = gen6_render_ring_flush; |
Ben Widawsky | 25c0630 | 2012-03-29 19:11:27 -0700 | [diff] [blame] | 1735 | ring->irq_get = gen6_ring_get_irq; |
| 1736 | ring->irq_put = gen6_ring_put_irq; |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1737 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1738 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1739 | ring->set_seqno = ring_set_seqno; |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1740 | ring->sync_to = gen6_ring_sync; |
Ben Widawsky | 5586181 | 2013-05-28 19:22:17 -0700 | [diff] [blame] | 1741 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 1742 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV; |
| 1743 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB; |
Ben Widawsky | 1950de1 | 2013-05-28 19:22:20 -0700 | [diff] [blame] | 1744 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE; |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 1745 | ring->signal_mbox[RCS] = GEN6_NOSYNC; |
| 1746 | ring->signal_mbox[VCS] = GEN6_VRSYNC; |
| 1747 | ring->signal_mbox[BCS] = GEN6_BRSYNC; |
Ben Widawsky | 1950de1 | 2013-05-28 19:22:20 -0700 | [diff] [blame] | 1748 | ring->signal_mbox[VECS] = GEN6_VERSYNC; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1749 | } else if (IS_GEN5(dev)) { |
| 1750 | ring->add_request = pc_render_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 1751 | ring->flush = gen4_render_ring_flush; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1752 | ring->get_seqno = pc_render_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1753 | ring->set_seqno = pc_render_set_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1754 | ring->irq_get = gen5_ring_get_irq; |
| 1755 | ring->irq_put = gen5_ring_put_irq; |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1756 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
| 1757 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1758 | } else { |
Daniel Vetter | 8620a3a | 2012-04-11 22:12:57 +0200 | [diff] [blame] | 1759 | ring->add_request = i9xx_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 1760 | if (INTEL_INFO(dev)->gen < 4) |
| 1761 | ring->flush = gen2_render_ring_flush; |
| 1762 | else |
| 1763 | ring->flush = gen4_render_ring_flush; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1764 | ring->get_seqno = ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1765 | ring->set_seqno = ring_set_seqno; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1766 | if (IS_GEN2(dev)) { |
| 1767 | ring->irq_get = i8xx_ring_get_irq; |
| 1768 | ring->irq_put = i8xx_ring_put_irq; |
| 1769 | } else { |
| 1770 | ring->irq_get = i9xx_ring_get_irq; |
| 1771 | ring->irq_put = i9xx_ring_put_irq; |
| 1772 | } |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1773 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1774 | } |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1775 | ring->write_tail = ring_write_tail; |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1776 | if (IS_HASWELL(dev)) |
| 1777 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
| 1778 | else if (INTEL_INFO(dev)->gen >= 6) |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1779 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
| 1780 | else if (INTEL_INFO(dev)->gen >= 4) |
| 1781 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
| 1782 | else if (IS_I830(dev) || IS_845G(dev)) |
| 1783 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
| 1784 | else |
| 1785 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1786 | ring->init = init_render_ring; |
| 1787 | ring->cleanup = render_ring_cleanup; |
| 1788 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1789 | /* Workaround batchbuffer to combat CS tlb bug. */ |
| 1790 | if (HAS_BROKEN_CS_TLB(dev)) { |
| 1791 | struct drm_i915_gem_object *obj; |
| 1792 | int ret; |
| 1793 | |
| 1794 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); |
| 1795 | if (obj == NULL) { |
| 1796 | DRM_ERROR("Failed to allocate batch bo\n"); |
| 1797 | return -ENOMEM; |
| 1798 | } |
| 1799 | |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 1800 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1801 | if (ret != 0) { |
| 1802 | drm_gem_object_unreference(&obj->base); |
| 1803 | DRM_ERROR("Failed to ping batch bo\n"); |
| 1804 | return ret; |
| 1805 | } |
| 1806 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 1807 | ring->scratch.obj = obj; |
| 1808 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1809 | } |
| 1810 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1811 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1812 | } |
| 1813 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1814 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
| 1815 | { |
| 1816 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1817 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1818 | int ret; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1819 | |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1820 | ring->name = "render ring"; |
| 1821 | ring->id = RCS; |
| 1822 | ring->mmio_base = RENDER_RING_BASE; |
| 1823 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1824 | if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | b4178f8 | 2012-04-11 22:12:51 +0200 | [diff] [blame] | 1825 | /* non-kms not supported on gen6+ */ |
| 1826 | return -ENODEV; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1827 | } |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 1828 | |
| 1829 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding |
| 1830 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up |
| 1831 | * the special gen5 functions. */ |
| 1832 | ring->add_request = i9xx_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 1833 | if (INTEL_INFO(dev)->gen < 4) |
| 1834 | ring->flush = gen2_render_ring_flush; |
| 1835 | else |
| 1836 | ring->flush = gen4_render_ring_flush; |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 1837 | ring->get_seqno = ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1838 | ring->set_seqno = ring_set_seqno; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1839 | if (IS_GEN2(dev)) { |
| 1840 | ring->irq_get = i8xx_ring_get_irq; |
| 1841 | ring->irq_put = i8xx_ring_put_irq; |
| 1842 | } else { |
| 1843 | ring->irq_get = i9xx_ring_get_irq; |
| 1844 | ring->irq_put = i9xx_ring_put_irq; |
| 1845 | } |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 1846 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1847 | ring->write_tail = ring_write_tail; |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1848 | if (INTEL_INFO(dev)->gen >= 4) |
| 1849 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
| 1850 | else if (IS_I830(dev) || IS_845G(dev)) |
| 1851 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
| 1852 | else |
| 1853 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1854 | ring->init = init_render_ring; |
| 1855 | ring->cleanup = render_ring_cleanup; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1856 | |
| 1857 | ring->dev = dev; |
| 1858 | INIT_LIST_HEAD(&ring->active_list); |
| 1859 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1860 | |
| 1861 | ring->size = size; |
| 1862 | ring->effective_size = ring->size; |
Mika Kuoppala | 17f10fd | 2012-10-29 16:59:26 +0200 | [diff] [blame] | 1863 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1864 | ring->effective_size -= 128; |
| 1865 | |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1866 | ring->virtual_start = ioremap_wc(start, size); |
| 1867 | if (ring->virtual_start == NULL) { |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1868 | DRM_ERROR("can not ioremap virtual address for" |
| 1869 | " ring buffer\n"); |
| 1870 | return -ENOMEM; |
| 1871 | } |
| 1872 | |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1873 | if (!I915_NEED_GFX_HWS(dev)) { |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 1874 | ret = init_phys_status_page(ring); |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1875 | if (ret) |
| 1876 | return ret; |
| 1877 | } |
| 1878 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1879 | return 0; |
| 1880 | } |
| 1881 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1882 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
| 1883 | { |
| 1884 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1885 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1886 | |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1887 | ring->name = "bsd ring"; |
| 1888 | ring->id = VCS; |
| 1889 | |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 1890 | ring->write_tail = ring_write_tail; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1891 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
| 1892 | ring->mmio_base = GEN6_BSD_RING_BASE; |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 1893 | /* gen6 bsd needs a special wa for tail updates */ |
| 1894 | if (IS_GEN6(dev)) |
| 1895 | ring->write_tail = gen6_bsd_ring_write_tail; |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 1896 | ring->flush = gen6_bsd_ring_flush; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1897 | ring->add_request = gen6_add_request; |
| 1898 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1899 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1900 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1901 | ring->irq_get = gen6_ring_get_irq; |
| 1902 | ring->irq_put = gen6_ring_put_irq; |
| 1903 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1904 | ring->sync_to = gen6_ring_sync; |
Ben Widawsky | 5586181 | 2013-05-28 19:22:17 -0700 | [diff] [blame] | 1905 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR; |
| 1906 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 1907 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB; |
Ben Widawsky | 1950de1 | 2013-05-28 19:22:20 -0700 | [diff] [blame] | 1908 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE; |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 1909 | ring->signal_mbox[RCS] = GEN6_RVSYNC; |
| 1910 | ring->signal_mbox[VCS] = GEN6_NOSYNC; |
| 1911 | ring->signal_mbox[BCS] = GEN6_BVSYNC; |
Ben Widawsky | 1950de1 | 2013-05-28 19:22:20 -0700 | [diff] [blame] | 1912 | ring->signal_mbox[VECS] = GEN6_VEVSYNC; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1913 | } else { |
| 1914 | ring->mmio_base = BSD_RING_BASE; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1915 | ring->flush = bsd_ring_flush; |
Daniel Vetter | 8620a3a | 2012-04-11 22:12:57 +0200 | [diff] [blame] | 1916 | ring->add_request = i9xx_add_request; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1917 | ring->get_seqno = ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1918 | ring->set_seqno = ring_set_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1919 | if (IS_GEN5(dev)) { |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1920 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1921 | ring->irq_get = gen5_ring_get_irq; |
| 1922 | ring->irq_put = gen5_ring_put_irq; |
| 1923 | } else { |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1924 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1925 | ring->irq_get = i9xx_ring_get_irq; |
| 1926 | ring->irq_put = i9xx_ring_put_irq; |
| 1927 | } |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1928 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1929 | } |
| 1930 | ring->init = init_ring_common; |
| 1931 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1932 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1933 | } |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1934 | |
| 1935 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
| 1936 | { |
| 1937 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1938 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1939 | |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 1940 | ring->name = "blitter ring"; |
| 1941 | ring->id = BCS; |
| 1942 | |
| 1943 | ring->mmio_base = BLT_RING_BASE; |
| 1944 | ring->write_tail = ring_write_tail; |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 1945 | ring->flush = gen6_ring_flush; |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 1946 | ring->add_request = gen6_add_request; |
| 1947 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1948 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1949 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 1950 | ring->irq_get = gen6_ring_get_irq; |
| 1951 | ring->irq_put = gen6_ring_put_irq; |
| 1952 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1953 | ring->sync_to = gen6_ring_sync; |
Ben Widawsky | 5586181 | 2013-05-28 19:22:17 -0700 | [diff] [blame] | 1954 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR; |
| 1955 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV; |
| 1956 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID; |
Ben Widawsky | 1950de1 | 2013-05-28 19:22:20 -0700 | [diff] [blame] | 1957 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE; |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 1958 | ring->signal_mbox[RCS] = GEN6_RBSYNC; |
| 1959 | ring->signal_mbox[VCS] = GEN6_VBSYNC; |
| 1960 | ring->signal_mbox[BCS] = GEN6_NOSYNC; |
Ben Widawsky | 1950de1 | 2013-05-28 19:22:20 -0700 | [diff] [blame] | 1961 | ring->signal_mbox[VECS] = GEN6_VEBSYNC; |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 1962 | ring->init = init_ring_common; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1963 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1964 | return intel_init_ring_buffer(dev, ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1965 | } |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 1966 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 1967 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
| 1968 | { |
| 1969 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1970 | struct intel_ring_buffer *ring = &dev_priv->ring[VECS]; |
| 1971 | |
| 1972 | ring->name = "video enhancement ring"; |
| 1973 | ring->id = VECS; |
| 1974 | |
| 1975 | ring->mmio_base = VEBOX_RING_BASE; |
| 1976 | ring->write_tail = ring_write_tail; |
| 1977 | ring->flush = gen6_ring_flush; |
| 1978 | ring->add_request = gen6_add_request; |
| 1979 | ring->get_seqno = gen6_ring_get_seqno; |
| 1980 | ring->set_seqno = ring_set_seqno; |
Daniel Vetter | c0d6a3d | 2013-07-04 23:35:30 +0200 | [diff] [blame] | 1981 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1982 | ring->irq_get = hsw_vebox_get_irq; |
| 1983 | ring->irq_put = hsw_vebox_put_irq; |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 1984 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
| 1985 | ring->sync_to = gen6_ring_sync; |
| 1986 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER; |
| 1987 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV; |
| 1988 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB; |
| 1989 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID; |
| 1990 | ring->signal_mbox[RCS] = GEN6_RVESYNC; |
| 1991 | ring->signal_mbox[VCS] = GEN6_VVESYNC; |
| 1992 | ring->signal_mbox[BCS] = GEN6_BVESYNC; |
| 1993 | ring->signal_mbox[VECS] = GEN6_NOSYNC; |
| 1994 | ring->init = init_ring_common; |
| 1995 | |
| 1996 | return intel_init_ring_buffer(dev, ring); |
| 1997 | } |
| 1998 | |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 1999 | int |
| 2000 | intel_ring_flush_all_caches(struct intel_ring_buffer *ring) |
| 2001 | { |
| 2002 | int ret; |
| 2003 | |
| 2004 | if (!ring->gpu_caches_dirty) |
| 2005 | return 0; |
| 2006 | |
| 2007 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 2008 | if (ret) |
| 2009 | return ret; |
| 2010 | |
| 2011 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 2012 | |
| 2013 | ring->gpu_caches_dirty = false; |
| 2014 | return 0; |
| 2015 | } |
| 2016 | |
| 2017 | int |
| 2018 | intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) |
| 2019 | { |
| 2020 | uint32_t flush_domains; |
| 2021 | int ret; |
| 2022 | |
| 2023 | flush_domains = 0; |
| 2024 | if (ring->gpu_caches_dirty) |
| 2025 | flush_domains = I915_GEM_GPU_DOMAINS; |
| 2026 | |
| 2027 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 2028 | if (ret) |
| 2029 | return ret; |
| 2030 | |
| 2031 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 2032 | |
| 2033 | ring->gpu_caches_dirty = false; |
| 2034 | return 0; |
| 2035 | } |