Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 34 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 35 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include <linux/pci.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 37 | |
Chris Wilson | 3619df0 | 2010-11-28 15:37:17 +0000 | [diff] [blame] | 38 | static void i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
| 40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
| 41 | static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 42 | bool write); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 43 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 44 | uint64_t offset, |
| 45 | uint64_t size); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 46 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 47 | static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 48 | unsigned alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 49 | bool map_and_fenceable); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 50 | static void i915_gem_clear_fence_reg(struct drm_i915_gem_object *obj); |
| 51 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
| 52 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 53 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 54 | struct drm_file *file); |
| 55 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 56 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 57 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
| 58 | int nr_to_scan, |
| 59 | gfp_t gfp_mask); |
| 60 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 61 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 62 | /* some bookkeeping */ |
| 63 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 64 | size_t size) |
| 65 | { |
| 66 | dev_priv->mm.object_count++; |
| 67 | dev_priv->mm.object_memory += size; |
| 68 | } |
| 69 | |
| 70 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 71 | size_t size) |
| 72 | { |
| 73 | dev_priv->mm.object_count--; |
| 74 | dev_priv->mm.object_memory -= size; |
| 75 | } |
| 76 | |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 77 | int |
| 78 | i915_gem_check_is_wedged(struct drm_device *dev) |
| 79 | { |
| 80 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 81 | struct completion *x = &dev_priv->error_completion; |
| 82 | unsigned long flags; |
| 83 | int ret; |
| 84 | |
| 85 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 86 | return 0; |
| 87 | |
| 88 | ret = wait_for_completion_interruptible(x); |
| 89 | if (ret) |
| 90 | return ret; |
| 91 | |
| 92 | /* Success, we reset the GPU! */ |
| 93 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 94 | return 0; |
| 95 | |
| 96 | /* GPU is hung, bump the completion count to account for |
| 97 | * the token we just consumed so that we never hit zero and |
| 98 | * end up waiting upon a subsequent completion event that |
| 99 | * will never happen. |
| 100 | */ |
| 101 | spin_lock_irqsave(&x->wait.lock, flags); |
| 102 | x->done++; |
| 103 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 104 | return -EIO; |
| 105 | } |
| 106 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 107 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 108 | { |
| 109 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 110 | int ret; |
| 111 | |
| 112 | ret = i915_gem_check_is_wedged(dev); |
| 113 | if (ret) |
| 114 | return ret; |
| 115 | |
| 116 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 117 | if (ret) |
| 118 | return ret; |
| 119 | |
| 120 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 121 | mutex_unlock(&dev->struct_mutex); |
| 122 | return -EAGAIN; |
| 123 | } |
| 124 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 125 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 126 | return 0; |
| 127 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 128 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 129 | static inline bool |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 130 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 131 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 132 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 133 | } |
| 134 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 135 | void i915_gem_do_init(struct drm_device *dev, |
| 136 | unsigned long start, |
| 137 | unsigned long mappable_end, |
| 138 | unsigned long end) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 139 | { |
| 140 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 141 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 142 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
| 143 | end - start); |
| 144 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 145 | dev_priv->mm.gtt_total = end - start; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 146 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 147 | dev_priv->mm.gtt_mappable_end = mappable_end; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 148 | } |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 149 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 150 | int |
| 151 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 152 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 153 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 154 | struct drm_i915_gem_init *args = data; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 155 | |
| 156 | if (args->gtt_start >= args->gtt_end || |
| 157 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) |
| 158 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 159 | |
| 160 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 161 | i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 162 | mutex_unlock(&dev->struct_mutex); |
| 163 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 164 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 165 | } |
| 166 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 167 | int |
| 168 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 169 | struct drm_file *file) |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 170 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 171 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 172 | struct drm_i915_gem_get_aperture *args = data; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 173 | struct drm_i915_gem_object *obj; |
| 174 | size_t pinned; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 175 | |
| 176 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 177 | return -ENODEV; |
| 178 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 179 | pinned = 0; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 180 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 181 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
| 182 | pinned += obj->gtt_space->size; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 183 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 184 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 185 | args->aper_size = dev_priv->mm.gtt_total; |
| 186 | args->aper_available_size = args->aper_size -pinned; |
| 187 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 188 | return 0; |
| 189 | } |
| 190 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 191 | /** |
| 192 | * Creates a new mm object and returns a handle to it. |
| 193 | */ |
| 194 | int |
| 195 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 196 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 197 | { |
| 198 | struct drm_i915_gem_create *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 199 | struct drm_i915_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 200 | int ret; |
| 201 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 202 | |
| 203 | args->size = roundup(args->size, PAGE_SIZE); |
| 204 | |
| 205 | /* Allocate the new object */ |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 206 | obj = i915_gem_alloc_object(dev, args->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 207 | if (obj == NULL) |
| 208 | return -ENOMEM; |
| 209 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 210 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 211 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 212 | drm_gem_object_release(&obj->base); |
| 213 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 214 | kfree(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 215 | return ret; |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 216 | } |
| 217 | |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 218 | /* drop reference from allocate - handle holds it now */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 219 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 220 | trace_i915_gem_object_create(obj); |
| 221 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 222 | args->handle = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 223 | return 0; |
| 224 | } |
| 225 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 226 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 227 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 228 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 229 | |
| 230 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 231 | obj->tiling_mode != I915_TILING_NONE; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 232 | } |
| 233 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 234 | static inline void |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 235 | slow_shmem_copy(struct page *dst_page, |
| 236 | int dst_offset, |
| 237 | struct page *src_page, |
| 238 | int src_offset, |
| 239 | int length) |
| 240 | { |
| 241 | char *dst_vaddr, *src_vaddr; |
| 242 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 243 | dst_vaddr = kmap(dst_page); |
| 244 | src_vaddr = kmap(src_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 245 | |
| 246 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); |
| 247 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 248 | kunmap(src_page); |
| 249 | kunmap(dst_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 250 | } |
| 251 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 252 | static inline void |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 253 | slow_shmem_bit17_copy(struct page *gpu_page, |
| 254 | int gpu_offset, |
| 255 | struct page *cpu_page, |
| 256 | int cpu_offset, |
| 257 | int length, |
| 258 | int is_read) |
| 259 | { |
| 260 | char *gpu_vaddr, *cpu_vaddr; |
| 261 | |
| 262 | /* Use the unswizzled path if this page isn't affected. */ |
| 263 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { |
| 264 | if (is_read) |
| 265 | return slow_shmem_copy(cpu_page, cpu_offset, |
| 266 | gpu_page, gpu_offset, length); |
| 267 | else |
| 268 | return slow_shmem_copy(gpu_page, gpu_offset, |
| 269 | cpu_page, cpu_offset, length); |
| 270 | } |
| 271 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 272 | gpu_vaddr = kmap(gpu_page); |
| 273 | cpu_vaddr = kmap(cpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 274 | |
| 275 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's |
| 276 | * XORing with the other bits (A9 for Y, A9 and A10 for X) |
| 277 | */ |
| 278 | while (length > 0) { |
| 279 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 280 | int this_length = min(cacheline_end - gpu_offset, length); |
| 281 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 282 | |
| 283 | if (is_read) { |
| 284 | memcpy(cpu_vaddr + cpu_offset, |
| 285 | gpu_vaddr + swizzled_gpu_offset, |
| 286 | this_length); |
| 287 | } else { |
| 288 | memcpy(gpu_vaddr + swizzled_gpu_offset, |
| 289 | cpu_vaddr + cpu_offset, |
| 290 | this_length); |
| 291 | } |
| 292 | cpu_offset += this_length; |
| 293 | gpu_offset += this_length; |
| 294 | length -= this_length; |
| 295 | } |
| 296 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 297 | kunmap(cpu_page); |
| 298 | kunmap(gpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 299 | } |
| 300 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 301 | /** |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 302 | * This is the fast shmem pread path, which attempts to copy_from_user directly |
| 303 | * from the backing pages of the object to the user's address space. On a |
| 304 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). |
| 305 | */ |
| 306 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 307 | i915_gem_shmem_pread_fast(struct drm_device *dev, |
| 308 | struct drm_i915_gem_object *obj, |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 309 | struct drm_i915_gem_pread *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 310 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 311 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 312 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 313 | ssize_t remain; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 314 | loff_t offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 315 | char __user *user_data; |
| 316 | int page_offset, page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 317 | |
| 318 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 319 | remain = args->size; |
| 320 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 321 | offset = args->offset; |
| 322 | |
| 323 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 324 | struct page *page; |
| 325 | char *vaddr; |
| 326 | int ret; |
| 327 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 328 | /* Operation in this page |
| 329 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 330 | * page_offset = offset within page |
| 331 | * page_length = bytes to copy for this page |
| 332 | */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 333 | page_offset = offset & (PAGE_SIZE-1); |
| 334 | page_length = remain; |
| 335 | if ((page_offset + remain) > PAGE_SIZE) |
| 336 | page_length = PAGE_SIZE - page_offset; |
| 337 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 338 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
| 339 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 340 | if (IS_ERR(page)) |
| 341 | return PTR_ERR(page); |
| 342 | |
| 343 | vaddr = kmap_atomic(page); |
| 344 | ret = __copy_to_user_inatomic(user_data, |
| 345 | vaddr + page_offset, |
| 346 | page_length); |
| 347 | kunmap_atomic(vaddr); |
| 348 | |
| 349 | mark_page_accessed(page); |
| 350 | page_cache_release(page); |
| 351 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 352 | return -EFAULT; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 353 | |
| 354 | remain -= page_length; |
| 355 | user_data += page_length; |
| 356 | offset += page_length; |
| 357 | } |
| 358 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 359 | return 0; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 360 | } |
| 361 | |
| 362 | /** |
| 363 | * This is the fallback shmem pread path, which allocates temporary storage |
| 364 | * in kernel space to copy_to_user into outside of the struct_mutex, so we |
| 365 | * can copy out of the object's backing pages while holding the struct mutex |
| 366 | * and not take page faults. |
| 367 | */ |
| 368 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 369 | i915_gem_shmem_pread_slow(struct drm_device *dev, |
| 370 | struct drm_i915_gem_object *obj, |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 371 | struct drm_i915_gem_pread *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 372 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 373 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 374 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 375 | struct mm_struct *mm = current->mm; |
| 376 | struct page **user_pages; |
| 377 | ssize_t remain; |
| 378 | loff_t offset, pinned_pages, i; |
| 379 | loff_t first_data_page, last_data_page, num_pages; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 380 | int shmem_page_offset; |
| 381 | int data_page_index, data_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 382 | int page_length; |
| 383 | int ret; |
| 384 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 385 | int do_bit17_swizzling; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 386 | |
| 387 | remain = args->size; |
| 388 | |
| 389 | /* Pin the user pages containing the data. We can't fault while |
| 390 | * holding the struct mutex, yet we want to hold it while |
| 391 | * dereferencing the user data. |
| 392 | */ |
| 393 | first_data_page = data_ptr / PAGE_SIZE; |
| 394 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 395 | num_pages = last_data_page - first_data_page + 1; |
| 396 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 397 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 398 | if (user_pages == NULL) |
| 399 | return -ENOMEM; |
| 400 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 401 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 402 | down_read(&mm->mmap_sem); |
| 403 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
Eric Anholt | e5e9ecd | 2009-04-07 16:01:22 -0700 | [diff] [blame] | 404 | num_pages, 1, 0, user_pages, NULL); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 405 | up_read(&mm->mmap_sem); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 406 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 407 | if (pinned_pages < num_pages) { |
| 408 | ret = -EFAULT; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 409 | goto out; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 410 | } |
| 411 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 412 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
| 413 | args->offset, |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 414 | args->size); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 415 | if (ret) |
| 416 | goto out; |
| 417 | |
| 418 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 419 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 420 | offset = args->offset; |
| 421 | |
| 422 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 423 | struct page *page; |
| 424 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 425 | /* Operation in this page |
| 426 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 427 | * shmem_page_offset = offset within page in shmem file |
| 428 | * data_page_index = page number in get_user_pages return |
| 429 | * data_page_offset = offset with data_page_index page. |
| 430 | * page_length = bytes to copy for this page |
| 431 | */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 432 | shmem_page_offset = offset & ~PAGE_MASK; |
| 433 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 434 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 435 | |
| 436 | page_length = remain; |
| 437 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 438 | page_length = PAGE_SIZE - shmem_page_offset; |
| 439 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 440 | page_length = PAGE_SIZE - data_page_offset; |
| 441 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 442 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
| 443 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 444 | if (IS_ERR(page)) |
| 445 | return PTR_ERR(page); |
| 446 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 447 | if (do_bit17_swizzling) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 448 | slow_shmem_bit17_copy(page, |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 449 | shmem_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 450 | user_pages[data_page_index], |
| 451 | data_page_offset, |
| 452 | page_length, |
| 453 | 1); |
| 454 | } else { |
| 455 | slow_shmem_copy(user_pages[data_page_index], |
| 456 | data_page_offset, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 457 | page, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 458 | shmem_page_offset, |
| 459 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 460 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 461 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 462 | mark_page_accessed(page); |
| 463 | page_cache_release(page); |
| 464 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 465 | remain -= page_length; |
| 466 | data_ptr += page_length; |
| 467 | offset += page_length; |
| 468 | } |
| 469 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 470 | out: |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 471 | for (i = 0; i < pinned_pages; i++) { |
| 472 | SetPageDirty(user_pages[i]); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 473 | mark_page_accessed(user_pages[i]); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 474 | page_cache_release(user_pages[i]); |
| 475 | } |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 476 | drm_free_large(user_pages); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 477 | |
| 478 | return ret; |
| 479 | } |
| 480 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 481 | /** |
| 482 | * Reads data from the object referenced by handle. |
| 483 | * |
| 484 | * On error, the contents of *data are undefined. |
| 485 | */ |
| 486 | int |
| 487 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 488 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 489 | { |
| 490 | struct drm_i915_gem_pread *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 491 | struct drm_i915_gem_object *obj; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 492 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 493 | |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 494 | if (args->size == 0) |
| 495 | return 0; |
| 496 | |
| 497 | if (!access_ok(VERIFY_WRITE, |
| 498 | (char __user *)(uintptr_t)args->data_ptr, |
| 499 | args->size)) |
| 500 | return -EFAULT; |
| 501 | |
| 502 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, |
| 503 | args->size); |
| 504 | if (ret) |
| 505 | return -EFAULT; |
| 506 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 507 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 508 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 509 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 510 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 511 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 512 | if (obj == NULL) { |
| 513 | ret = -ENOENT; |
| 514 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 515 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 516 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 517 | /* Bounds check source. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 518 | if (args->offset > obj->base.size || |
| 519 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 520 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 521 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 522 | } |
| 523 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 524 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
| 525 | args->offset, |
| 526 | args->size); |
| 527 | if (ret) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 528 | goto out; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 529 | |
| 530 | ret = -EFAULT; |
| 531 | if (!i915_gem_object_needs_bit17_swizzle(obj)) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 532 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 533 | if (ret == -EFAULT) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 534 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 535 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 536 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 537 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 538 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 539 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 540 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 541 | } |
| 542 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 543 | /* This is the fast write path which cannot handle |
| 544 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 545 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 546 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 547 | static inline int |
| 548 | fast_user_write(struct io_mapping *mapping, |
| 549 | loff_t page_base, int page_offset, |
| 550 | char __user *user_data, |
| 551 | int length) |
| 552 | { |
| 553 | char *vaddr_atomic; |
| 554 | unsigned long unwritten; |
| 555 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 556 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 557 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
| 558 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 559 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 560 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 561 | } |
| 562 | |
| 563 | /* Here's the write path which can sleep for |
| 564 | * page faults |
| 565 | */ |
| 566 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 567 | static inline void |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 568 | slow_kernel_write(struct io_mapping *mapping, |
| 569 | loff_t gtt_base, int gtt_offset, |
| 570 | struct page *user_page, int user_offset, |
| 571 | int length) |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 572 | { |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 573 | char __iomem *dst_vaddr; |
| 574 | char *src_vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 575 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 576 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
| 577 | src_vaddr = kmap(user_page); |
| 578 | |
| 579 | memcpy_toio(dst_vaddr + gtt_offset, |
| 580 | src_vaddr + user_offset, |
| 581 | length); |
| 582 | |
| 583 | kunmap(user_page); |
| 584 | io_mapping_unmap(dst_vaddr); |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 585 | } |
| 586 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 587 | /** |
| 588 | * This is the fast pwrite path, where we copy the data directly from the |
| 589 | * user into the GTT, uncached. |
| 590 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 591 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 592 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 593 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 594 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 595 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 596 | { |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 597 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 598 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 599 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 600 | char __user *user_data; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 601 | int page_offset, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 602 | |
| 603 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 604 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 605 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 606 | offset = obj->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 607 | |
| 608 | while (remain > 0) { |
| 609 | /* Operation in this page |
| 610 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 611 | * page_base = page offset within aperture |
| 612 | * page_offset = offset within page |
| 613 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 614 | */ |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 615 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 616 | page_offset = offset & (PAGE_SIZE-1); |
| 617 | page_length = remain; |
| 618 | if ((page_offset + remain) > PAGE_SIZE) |
| 619 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 620 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 621 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 622 | * source page isn't available. Return the error and we'll |
| 623 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 624 | */ |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 625 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
| 626 | page_offset, user_data, page_length)) |
| 627 | |
| 628 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 629 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 630 | remain -= page_length; |
| 631 | user_data += page_length; |
| 632 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 633 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 634 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 635 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 636 | } |
| 637 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 638 | /** |
| 639 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin |
| 640 | * the memory and maps it using kmap_atomic for copying. |
| 641 | * |
| 642 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU |
| 643 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). |
| 644 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 645 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 646 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, |
| 647 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 648 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 649 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 650 | { |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 651 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 652 | ssize_t remain; |
| 653 | loff_t gtt_page_base, offset; |
| 654 | loff_t first_data_page, last_data_page, num_pages; |
| 655 | loff_t pinned_pages, i; |
| 656 | struct page **user_pages; |
| 657 | struct mm_struct *mm = current->mm; |
| 658 | int gtt_page_offset, data_page_offset, data_page_index, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 659 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 660 | uint64_t data_ptr = args->data_ptr; |
| 661 | |
| 662 | remain = args->size; |
| 663 | |
| 664 | /* Pin the user pages containing the data. We can't fault while |
| 665 | * holding the struct mutex, and all of the pwrite implementations |
| 666 | * want to hold it while dereferencing the user data. |
| 667 | */ |
| 668 | first_data_page = data_ptr / PAGE_SIZE; |
| 669 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 670 | num_pages = last_data_page - first_data_page + 1; |
| 671 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 672 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 673 | if (user_pages == NULL) |
| 674 | return -ENOMEM; |
| 675 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 676 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 677 | down_read(&mm->mmap_sem); |
| 678 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 679 | num_pages, 0, 0, user_pages, NULL); |
| 680 | up_read(&mm->mmap_sem); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 681 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 682 | if (pinned_pages < num_pages) { |
| 683 | ret = -EFAULT; |
| 684 | goto out_unpin_pages; |
| 685 | } |
| 686 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 687 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 688 | if (ret) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 689 | goto out_unpin_pages; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 690 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 691 | offset = obj->gtt_offset + args->offset; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 692 | |
| 693 | while (remain > 0) { |
| 694 | /* Operation in this page |
| 695 | * |
| 696 | * gtt_page_base = page offset within aperture |
| 697 | * gtt_page_offset = offset within page in aperture |
| 698 | * data_page_index = page number in get_user_pages return |
| 699 | * data_page_offset = offset with data_page_index page. |
| 700 | * page_length = bytes to copy for this page |
| 701 | */ |
| 702 | gtt_page_base = offset & PAGE_MASK; |
| 703 | gtt_page_offset = offset & ~PAGE_MASK; |
| 704 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 705 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 706 | |
| 707 | page_length = remain; |
| 708 | if ((gtt_page_offset + page_length) > PAGE_SIZE) |
| 709 | page_length = PAGE_SIZE - gtt_page_offset; |
| 710 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 711 | page_length = PAGE_SIZE - data_page_offset; |
| 712 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 713 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
| 714 | gtt_page_base, gtt_page_offset, |
| 715 | user_pages[data_page_index], |
| 716 | data_page_offset, |
| 717 | page_length); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 718 | |
| 719 | remain -= page_length; |
| 720 | offset += page_length; |
| 721 | data_ptr += page_length; |
| 722 | } |
| 723 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 724 | out_unpin_pages: |
| 725 | for (i = 0; i < pinned_pages; i++) |
| 726 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 727 | drm_free_large(user_pages); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 728 | |
| 729 | return ret; |
| 730 | } |
| 731 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 732 | /** |
| 733 | * This is the fast shmem pwrite path, which attempts to directly |
| 734 | * copy_from_user into the kmapped pages backing the object. |
| 735 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 736 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 737 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, |
| 738 | struct drm_i915_gem_object *obj, |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 739 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 740 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 741 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 742 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 743 | ssize_t remain; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 744 | loff_t offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 745 | char __user *user_data; |
| 746 | int page_offset, page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 747 | |
| 748 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 749 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 750 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 751 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 752 | obj->dirty = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 753 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 754 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 755 | struct page *page; |
| 756 | char *vaddr; |
| 757 | int ret; |
| 758 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 759 | /* Operation in this page |
| 760 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 761 | * page_offset = offset within page |
| 762 | * page_length = bytes to copy for this page |
| 763 | */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 764 | page_offset = offset & (PAGE_SIZE-1); |
| 765 | page_length = remain; |
| 766 | if ((page_offset + remain) > PAGE_SIZE) |
| 767 | page_length = PAGE_SIZE - page_offset; |
| 768 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 769 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
| 770 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 771 | if (IS_ERR(page)) |
| 772 | return PTR_ERR(page); |
| 773 | |
| 774 | vaddr = kmap_atomic(page, KM_USER0); |
| 775 | ret = __copy_from_user_inatomic(vaddr + page_offset, |
| 776 | user_data, |
| 777 | page_length); |
| 778 | kunmap_atomic(vaddr, KM_USER0); |
| 779 | |
| 780 | set_page_dirty(page); |
| 781 | mark_page_accessed(page); |
| 782 | page_cache_release(page); |
| 783 | |
| 784 | /* If we get a fault while copying data, then (presumably) our |
| 785 | * source page isn't available. Return the error and we'll |
| 786 | * retry in the slow path. |
| 787 | */ |
| 788 | if (ret) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 789 | return -EFAULT; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 790 | |
| 791 | remain -= page_length; |
| 792 | user_data += page_length; |
| 793 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 794 | } |
| 795 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 796 | return 0; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 797 | } |
| 798 | |
| 799 | /** |
| 800 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin |
| 801 | * the memory and maps it using kmap_atomic for copying. |
| 802 | * |
| 803 | * This avoids taking mmap_sem for faulting on the user's address while the |
| 804 | * struct_mutex is held. |
| 805 | */ |
| 806 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 807 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, |
| 808 | struct drm_i915_gem_object *obj, |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 809 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 810 | struct drm_file *file) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 811 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 812 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 813 | struct mm_struct *mm = current->mm; |
| 814 | struct page **user_pages; |
| 815 | ssize_t remain; |
| 816 | loff_t offset, pinned_pages, i; |
| 817 | loff_t first_data_page, last_data_page, num_pages; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 818 | int shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 819 | int data_page_index, data_page_offset; |
| 820 | int page_length; |
| 821 | int ret; |
| 822 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 823 | int do_bit17_swizzling; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 824 | |
| 825 | remain = args->size; |
| 826 | |
| 827 | /* Pin the user pages containing the data. We can't fault while |
| 828 | * holding the struct mutex, and all of the pwrite implementations |
| 829 | * want to hold it while dereferencing the user data. |
| 830 | */ |
| 831 | first_data_page = data_ptr / PAGE_SIZE; |
| 832 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 833 | num_pages = last_data_page - first_data_page + 1; |
| 834 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 835 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 836 | if (user_pages == NULL) |
| 837 | return -ENOMEM; |
| 838 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 839 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 840 | down_read(&mm->mmap_sem); |
| 841 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 842 | num_pages, 0, 0, user_pages, NULL); |
| 843 | up_read(&mm->mmap_sem); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 844 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 845 | if (pinned_pages < num_pages) { |
| 846 | ret = -EFAULT; |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 847 | goto out; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 848 | } |
| 849 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 850 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 851 | if (ret) |
| 852 | goto out; |
| 853 | |
| 854 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 855 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 856 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 857 | obj->dirty = 1; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 858 | |
| 859 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 860 | struct page *page; |
| 861 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 862 | /* Operation in this page |
| 863 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 864 | * shmem_page_offset = offset within page in shmem file |
| 865 | * data_page_index = page number in get_user_pages return |
| 866 | * data_page_offset = offset with data_page_index page. |
| 867 | * page_length = bytes to copy for this page |
| 868 | */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 869 | shmem_page_offset = offset & ~PAGE_MASK; |
| 870 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 871 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 872 | |
| 873 | page_length = remain; |
| 874 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 875 | page_length = PAGE_SIZE - shmem_page_offset; |
| 876 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 877 | page_length = PAGE_SIZE - data_page_offset; |
| 878 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 879 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
| 880 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 881 | if (IS_ERR(page)) { |
| 882 | ret = PTR_ERR(page); |
| 883 | goto out; |
| 884 | } |
| 885 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 886 | if (do_bit17_swizzling) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 887 | slow_shmem_bit17_copy(page, |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 888 | shmem_page_offset, |
| 889 | user_pages[data_page_index], |
| 890 | data_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 891 | page_length, |
| 892 | 0); |
| 893 | } else { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 894 | slow_shmem_copy(page, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 895 | shmem_page_offset, |
| 896 | user_pages[data_page_index], |
| 897 | data_page_offset, |
| 898 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 899 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 900 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 901 | set_page_dirty(page); |
| 902 | mark_page_accessed(page); |
| 903 | page_cache_release(page); |
| 904 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 905 | remain -= page_length; |
| 906 | data_ptr += page_length; |
| 907 | offset += page_length; |
| 908 | } |
| 909 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 910 | out: |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 911 | for (i = 0; i < pinned_pages; i++) |
| 912 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 913 | drm_free_large(user_pages); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 914 | |
| 915 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 916 | } |
| 917 | |
| 918 | /** |
| 919 | * Writes data to the object referenced by handle. |
| 920 | * |
| 921 | * On error, the contents of the buffer that were to be modified are undefined. |
| 922 | */ |
| 923 | int |
| 924 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 925 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 926 | { |
| 927 | struct drm_i915_gem_pwrite *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 928 | struct drm_i915_gem_object *obj; |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 929 | int ret; |
| 930 | |
| 931 | if (args->size == 0) |
| 932 | return 0; |
| 933 | |
| 934 | if (!access_ok(VERIFY_READ, |
| 935 | (char __user *)(uintptr_t)args->data_ptr, |
| 936 | args->size)) |
| 937 | return -EFAULT; |
| 938 | |
| 939 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, |
| 940 | args->size); |
| 941 | if (ret) |
| 942 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 943 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 944 | ret = i915_mutex_lock_interruptible(dev); |
| 945 | if (ret) |
| 946 | return ret; |
| 947 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 948 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 949 | if (obj == NULL) { |
| 950 | ret = -ENOENT; |
| 951 | goto unlock; |
| 952 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 953 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 954 | /* Bounds check destination. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 955 | if (args->offset > obj->base.size || |
| 956 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 957 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 958 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 959 | } |
| 960 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 961 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 962 | * it would end up going through the fenced access, and we'll get |
| 963 | * different detiling behavior between reading and writing. |
| 964 | * pread/pwrite currently are reading and writing from the CPU |
| 965 | * perspective, requiring manual detiling by the client. |
| 966 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 967 | if (obj->phys_obj) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 968 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 969 | else if (obj->tiling_mode == I915_TILING_NONE && |
| 970 | obj->gtt_space && |
| 971 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 972 | ret = i915_gem_object_pin(obj, 0, true); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 973 | if (ret) |
| 974 | goto out; |
| 975 | |
| 976 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 977 | if (ret) |
| 978 | goto out_unpin; |
| 979 | |
| 980 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
| 981 | if (ret == -EFAULT) |
| 982 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); |
| 983 | |
| 984 | out_unpin: |
| 985 | i915_gem_object_unpin(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 986 | } else { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 987 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 988 | if (ret) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 989 | goto out; |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 990 | |
| 991 | ret = -EFAULT; |
| 992 | if (!i915_gem_object_needs_bit17_swizzle(obj)) |
| 993 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); |
| 994 | if (ret == -EFAULT) |
| 995 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 996 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 997 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 998 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 999 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1000 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1001 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1002 | return ret; |
| 1003 | } |
| 1004 | |
| 1005 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1006 | * Called when user space prepares to use an object with the CPU, either |
| 1007 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1008 | */ |
| 1009 | int |
| 1010 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1011 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1012 | { |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1013 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1014 | struct drm_i915_gem_set_domain *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1015 | struct drm_i915_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1016 | uint32_t read_domains = args->read_domains; |
| 1017 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1018 | int ret; |
| 1019 | |
| 1020 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1021 | return -ENODEV; |
| 1022 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1023 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1024 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1025 | return -EINVAL; |
| 1026 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1027 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1028 | return -EINVAL; |
| 1029 | |
| 1030 | /* Having something in the write domain implies it's in the read |
| 1031 | * domain, and only that read domain. Enforce that in the request. |
| 1032 | */ |
| 1033 | if (write_domain != 0 && read_domains != write_domain) |
| 1034 | return -EINVAL; |
| 1035 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1036 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1037 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1038 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1039 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1040 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1041 | if (obj == NULL) { |
| 1042 | ret = -ENOENT; |
| 1043 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1044 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1045 | |
| 1046 | intel_mark_busy(dev, obj); |
| 1047 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1048 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1049 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1050 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1051 | /* Update the LRU on the fence for the CPU access that's |
| 1052 | * about to occur. |
| 1053 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1054 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1055 | struct drm_i915_fence_reg *reg = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1056 | &dev_priv->fence_regs[obj->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1057 | list_move_tail(®->lru_list, |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1058 | &dev_priv->mm.fence_list); |
| 1059 | } |
| 1060 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1061 | /* Silently promote "you're not bound, there was nothing to do" |
| 1062 | * to success, since the client was just asking us to |
| 1063 | * make sure everything was done. |
| 1064 | */ |
| 1065 | if (ret == -EINVAL) |
| 1066 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1067 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1068 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1069 | } |
| 1070 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1071 | /* Maintain LRU order of "inactive" objects */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1072 | if (ret == 0 && i915_gem_object_is_inactive(obj)) |
| 1073 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1074 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1075 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1076 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1077 | mutex_unlock(&dev->struct_mutex); |
| 1078 | return ret; |
| 1079 | } |
| 1080 | |
| 1081 | /** |
| 1082 | * Called when user space has done writes to this buffer |
| 1083 | */ |
| 1084 | int |
| 1085 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1086 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1087 | { |
| 1088 | struct drm_i915_gem_sw_finish *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1089 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1090 | int ret = 0; |
| 1091 | |
| 1092 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1093 | return -ENODEV; |
| 1094 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1095 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1096 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1097 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1098 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1099 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1100 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1101 | ret = -ENOENT; |
| 1102 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1103 | } |
| 1104 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1105 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1106 | if (obj->pin_count) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1107 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1108 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1109 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1110 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1111 | mutex_unlock(&dev->struct_mutex); |
| 1112 | return ret; |
| 1113 | } |
| 1114 | |
| 1115 | /** |
| 1116 | * Maps the contents of an object, returning the address it is mapped |
| 1117 | * into. |
| 1118 | * |
| 1119 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1120 | * imply a ref on the object itself. |
| 1121 | */ |
| 1122 | int |
| 1123 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1124 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1125 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1126 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1127 | struct drm_i915_gem_mmap *args = data; |
| 1128 | struct drm_gem_object *obj; |
| 1129 | loff_t offset; |
| 1130 | unsigned long addr; |
| 1131 | |
| 1132 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1133 | return -ENODEV; |
| 1134 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1135 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1136 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1137 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1138 | |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1139 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
| 1140 | drm_gem_object_unreference_unlocked(obj); |
| 1141 | return -E2BIG; |
| 1142 | } |
| 1143 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1144 | offset = args->offset; |
| 1145 | |
| 1146 | down_write(¤t->mm->mmap_sem); |
| 1147 | addr = do_mmap(obj->filp, 0, args->size, |
| 1148 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1149 | args->offset); |
| 1150 | up_write(¤t->mm->mmap_sem); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1151 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1152 | if (IS_ERR((void *)addr)) |
| 1153 | return addr; |
| 1154 | |
| 1155 | args->addr_ptr = (uint64_t) addr; |
| 1156 | |
| 1157 | return 0; |
| 1158 | } |
| 1159 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1160 | /** |
| 1161 | * i915_gem_fault - fault a page into the GTT |
| 1162 | * vma: VMA in question |
| 1163 | * vmf: fault info |
| 1164 | * |
| 1165 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1166 | * from userspace. The fault handler takes care of binding the object to |
| 1167 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1168 | * only if needed based on whether the old reg is still valid or the object |
| 1169 | * is tiled) and inserting a new PTE into the faulting process. |
| 1170 | * |
| 1171 | * Note that the faulting process may involve evicting existing objects |
| 1172 | * from the GTT and/or fence registers to make room. So performance may |
| 1173 | * suffer if the GTT working set is large or there are few fence registers |
| 1174 | * left. |
| 1175 | */ |
| 1176 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1177 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1178 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1179 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1180 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1181 | pgoff_t page_offset; |
| 1182 | unsigned long pfn; |
| 1183 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1184 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1185 | |
| 1186 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1187 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1188 | PAGE_SHIFT; |
| 1189 | |
| 1190 | /* Now bind it into the GTT if needed */ |
| 1191 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1192 | |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 1193 | if (!obj->map_and_fenceable) { |
| 1194 | ret = i915_gem_object_unbind(obj); |
| 1195 | if (ret) |
| 1196 | goto unlock; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1197 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1198 | if (!obj->gtt_space) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1199 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1200 | if (ret) |
| 1201 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1202 | } |
| 1203 | |
Chris Wilson | 4a684a4 | 2010-10-28 14:44:08 +0100 | [diff] [blame] | 1204 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1205 | if (ret) |
| 1206 | goto unlock; |
| 1207 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1208 | /* Need a new fence register? */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1209 | if (obj->tiling_mode != I915_TILING_NONE) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 1210 | ret = i915_gem_object_get_fence_reg(obj, true); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1211 | if (ret) |
| 1212 | goto unlock; |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 1213 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1214 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1215 | if (i915_gem_object_is_inactive(obj)) |
| 1216 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1217 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1218 | obj->fault_mappable = true; |
| 1219 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1220 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1221 | page_offset; |
| 1222 | |
| 1223 | /* Finally, remap it using the new GTT offset */ |
| 1224 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1225 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1226 | mutex_unlock(&dev->struct_mutex); |
| 1227 | |
| 1228 | switch (ret) { |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1229 | case -EAGAIN: |
| 1230 | set_need_resched(); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1231 | case 0: |
| 1232 | case -ERESTARTSYS: |
| 1233 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1234 | case -ENOMEM: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1235 | return VM_FAULT_OOM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1236 | default: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1237 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1238 | } |
| 1239 | } |
| 1240 | |
| 1241 | /** |
| 1242 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object |
| 1243 | * @obj: obj in question |
| 1244 | * |
| 1245 | * GEM memory mapping works by handing back to userspace a fake mmap offset |
| 1246 | * it can use in a subsequent mmap(2) call. The DRM core code then looks |
| 1247 | * up the object based on the offset and sets up the various memory mapping |
| 1248 | * structures. |
| 1249 | * |
| 1250 | * This routine allocates and attaches a fake offset for @obj. |
| 1251 | */ |
| 1252 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1253 | i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1254 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1255 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1256 | struct drm_gem_mm *mm = dev->mm_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1257 | struct drm_map_list *list; |
Benjamin Herrenschmidt | f77d390 | 2009-02-02 16:55:46 +1100 | [diff] [blame] | 1258 | struct drm_local_map *map; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1259 | int ret = 0; |
| 1260 | |
| 1261 | /* Set the object up for mmap'ing */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1262 | list = &obj->base.map_list; |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1263 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1264 | if (!list->map) |
| 1265 | return -ENOMEM; |
| 1266 | |
| 1267 | map = list->map; |
| 1268 | map->type = _DRM_GEM; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1269 | map->size = obj->base.size; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1270 | map->handle = obj; |
| 1271 | |
| 1272 | /* Get a DRM GEM mmap offset allocated... */ |
| 1273 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1274 | obj->base.size / PAGE_SIZE, |
| 1275 | 0, 0); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1276 | if (!list->file_offset_node) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1277 | DRM_ERROR("failed to allocate offset for bo %d\n", |
| 1278 | obj->base.name); |
Chris Wilson | 9e0ae534 | 2010-09-21 15:05:24 +0100 | [diff] [blame] | 1279 | ret = -ENOSPC; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1280 | goto out_free_list; |
| 1281 | } |
| 1282 | |
| 1283 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1284 | obj->base.size / PAGE_SIZE, |
| 1285 | 0); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1286 | if (!list->file_offset_node) { |
| 1287 | ret = -ENOMEM; |
| 1288 | goto out_free_list; |
| 1289 | } |
| 1290 | |
| 1291 | list->hash.key = list->file_offset_node->start; |
Chris Wilson | 9e0ae534 | 2010-09-21 15:05:24 +0100 | [diff] [blame] | 1292 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
| 1293 | if (ret) { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1294 | DRM_ERROR("failed to add to map hash\n"); |
| 1295 | goto out_free_mm; |
| 1296 | } |
| 1297 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1298 | return 0; |
| 1299 | |
| 1300 | out_free_mm: |
| 1301 | drm_mm_put_block(list->file_offset_node); |
| 1302 | out_free_list: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1303 | kfree(list->map); |
Chris Wilson | 39a01d1 | 2010-10-28 13:03:06 +0100 | [diff] [blame] | 1304 | list->map = NULL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1305 | |
| 1306 | return ret; |
| 1307 | } |
| 1308 | |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1309 | /** |
| 1310 | * i915_gem_release_mmap - remove physical page mappings |
| 1311 | * @obj: obj in question |
| 1312 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1313 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1314 | * relinquish ownership of the pages back to the system. |
| 1315 | * |
| 1316 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1317 | * object through the GTT and then lose the fence register due to |
| 1318 | * resource pressure. Similarly if the object has been moved out of the |
| 1319 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1320 | * mapping will then trigger a page fault on the next user access, allowing |
| 1321 | * fixup by i915_gem_fault(). |
| 1322 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1323 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1324 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1325 | { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1326 | if (!obj->fault_mappable) |
| 1327 | return; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1328 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1329 | unmap_mapping_range(obj->base.dev->dev_mapping, |
| 1330 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, |
| 1331 | obj->base.size, 1); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1332 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1333 | obj->fault_mappable = false; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1334 | } |
| 1335 | |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1336 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1337 | i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj) |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1338 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1339 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1340 | struct drm_gem_mm *mm = dev->mm_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1341 | struct drm_map_list *list = &obj->base.map_list; |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1342 | |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1343 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
Chris Wilson | 39a01d1 | 2010-10-28 13:03:06 +0100 | [diff] [blame] | 1344 | drm_mm_put_block(list->file_offset_node); |
| 1345 | kfree(list->map); |
| 1346 | list->map = NULL; |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1347 | } |
| 1348 | |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1349 | static uint32_t |
| 1350 | i915_gem_get_gtt_size(struct drm_i915_gem_object *obj) |
| 1351 | { |
| 1352 | struct drm_device *dev = obj->base.dev; |
| 1353 | uint32_t size; |
| 1354 | |
| 1355 | if (INTEL_INFO(dev)->gen >= 4 || |
| 1356 | obj->tiling_mode == I915_TILING_NONE) |
| 1357 | return obj->base.size; |
| 1358 | |
| 1359 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1360 | if (INTEL_INFO(dev)->gen == 3) |
| 1361 | size = 1024*1024; |
| 1362 | else |
| 1363 | size = 512*1024; |
| 1364 | |
| 1365 | while (size < obj->base.size) |
| 1366 | size <<= 1; |
| 1367 | |
| 1368 | return size; |
| 1369 | } |
| 1370 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1371 | /** |
| 1372 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1373 | * @obj: object to check |
| 1374 | * |
| 1375 | * Return the required GTT alignment for an object, taking into account |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1376 | * potential fence register mapping. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1377 | */ |
| 1378 | static uint32_t |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1379 | i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1380 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1381 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1382 | |
| 1383 | /* |
| 1384 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1385 | * if a fence register is needed for the object. |
| 1386 | */ |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1387 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1388 | obj->tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1389 | return 4096; |
| 1390 | |
| 1391 | /* |
| 1392 | * Previous chips need to be aligned to the size of the smallest |
| 1393 | * fence register that can contain the object. |
| 1394 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1395 | return i915_gem_get_gtt_size(obj); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1396 | } |
| 1397 | |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1398 | /** |
| 1399 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an |
| 1400 | * unfenced object |
| 1401 | * @obj: object to check |
| 1402 | * |
| 1403 | * Return the required GTT alignment for an object, only taking into account |
| 1404 | * unfenced tiled surface requirements. |
| 1405 | */ |
| 1406 | static uint32_t |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1407 | i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1408 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1409 | struct drm_device *dev = obj->base.dev; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1410 | int tile_height; |
| 1411 | |
| 1412 | /* |
| 1413 | * Minimum alignment is 4k (GTT page size) for sane hw. |
| 1414 | */ |
| 1415 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1416 | obj->tiling_mode == I915_TILING_NONE) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1417 | return 4096; |
| 1418 | |
| 1419 | /* |
| 1420 | * Older chips need unfenced tiled buffers to be aligned to the left |
| 1421 | * edge of an even tile row (where tile rows are counted as if the bo is |
| 1422 | * placed in a fenced gtt region). |
| 1423 | */ |
| 1424 | if (IS_GEN2(dev) || |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1425 | (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1426 | tile_height = 32; |
| 1427 | else |
| 1428 | tile_height = 8; |
| 1429 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1430 | return tile_height * obj->stride * 2; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1431 | } |
| 1432 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1433 | /** |
| 1434 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1435 | * @dev: DRM device |
| 1436 | * @data: GTT mapping ioctl data |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1437 | * @file: GEM object info |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1438 | * |
| 1439 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1440 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1441 | * up so we can get faults in the handler above. |
| 1442 | * |
| 1443 | * The fault handler will take care of binding the object into the GTT |
| 1444 | * (since it may have been evicted to make room for something), allocating |
| 1445 | * a fence register, and mapping the appropriate aperture address into |
| 1446 | * userspace. |
| 1447 | */ |
| 1448 | int |
| 1449 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1450 | struct drm_file *file) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1451 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1452 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1453 | struct drm_i915_gem_mmap_gtt *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1454 | struct drm_i915_gem_object *obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1455 | int ret; |
| 1456 | |
| 1457 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1458 | return -ENODEV; |
| 1459 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1460 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1461 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1462 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1463 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1464 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1465 | if (obj == NULL) { |
| 1466 | ret = -ENOENT; |
| 1467 | goto unlock; |
| 1468 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1469 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1470 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1471 | ret = -E2BIG; |
| 1472 | goto unlock; |
| 1473 | } |
| 1474 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1475 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1476 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1477 | ret = -EINVAL; |
| 1478 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1479 | } |
| 1480 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1481 | if (!obj->base.map_list.map) { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1482 | ret = i915_gem_create_mmap_offset(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1483 | if (ret) |
| 1484 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1485 | } |
| 1486 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1487 | args->offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1488 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1489 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1490 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1491 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1492 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1493 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1494 | } |
| 1495 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1496 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1497 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1498 | gfp_t gfpmask) |
| 1499 | { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1500 | int page_count, i; |
| 1501 | struct address_space *mapping; |
| 1502 | struct inode *inode; |
| 1503 | struct page *page; |
| 1504 | |
| 1505 | /* Get the list of pages out of our struct file. They'll be pinned |
| 1506 | * at this point until we release them. |
| 1507 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1508 | page_count = obj->base.size / PAGE_SIZE; |
| 1509 | BUG_ON(obj->pages != NULL); |
| 1510 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); |
| 1511 | if (obj->pages == NULL) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1512 | return -ENOMEM; |
| 1513 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1514 | inode = obj->base.filp->f_path.dentry->d_inode; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1515 | mapping = inode->i_mapping; |
| 1516 | for (i = 0; i < page_count; i++) { |
| 1517 | page = read_cache_page_gfp(mapping, i, |
| 1518 | GFP_HIGHUSER | |
| 1519 | __GFP_COLD | |
| 1520 | __GFP_RECLAIMABLE | |
| 1521 | gfpmask); |
| 1522 | if (IS_ERR(page)) |
| 1523 | goto err_pages; |
| 1524 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1525 | obj->pages[i] = page; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1526 | } |
| 1527 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1528 | if (obj->tiling_mode != I915_TILING_NONE) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1529 | i915_gem_object_do_bit_17_swizzle(obj); |
| 1530 | |
| 1531 | return 0; |
| 1532 | |
| 1533 | err_pages: |
| 1534 | while (i--) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1535 | page_cache_release(obj->pages[i]); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1536 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1537 | drm_free_large(obj->pages); |
| 1538 | obj->pages = NULL; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1539 | return PTR_ERR(page); |
| 1540 | } |
| 1541 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1542 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1543 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1544 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1545 | int page_count = obj->base.size / PAGE_SIZE; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1546 | int i; |
| 1547 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1548 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1549 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1550 | if (obj->tiling_mode != I915_TILING_NONE) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1551 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1552 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1553 | if (obj->madv == I915_MADV_DONTNEED) |
| 1554 | obj->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1555 | |
| 1556 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1557 | if (obj->dirty) |
| 1558 | set_page_dirty(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1559 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1560 | if (obj->madv == I915_MADV_WILLNEED) |
| 1561 | mark_page_accessed(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1562 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1563 | page_cache_release(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1564 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1565 | obj->dirty = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1566 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1567 | drm_free_large(obj->pages); |
| 1568 | obj->pages = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1569 | } |
| 1570 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1571 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1572 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1573 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1574 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1575 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1576 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1577 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1578 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1579 | BUG_ON(ring == NULL); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1580 | obj->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1581 | |
| 1582 | /* Add a reference if we're newly entering the active list. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1583 | if (!obj->active) { |
| 1584 | drm_gem_object_reference(&obj->base); |
| 1585 | obj->active = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1586 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1587 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1588 | /* Move from whatever list we were on to the tail of execution. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1589 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
| 1590 | list_move_tail(&obj->ring_list, &ring->active_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1591 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1592 | obj->last_rendering_seqno = seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1593 | if (obj->fenced_gpu_access) { |
| 1594 | struct drm_i915_fence_reg *reg; |
| 1595 | |
| 1596 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); |
| 1597 | |
| 1598 | obj->last_fenced_seqno = seqno; |
| 1599 | obj->last_fenced_ring = ring; |
| 1600 | |
| 1601 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
| 1602 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
| 1603 | } |
| 1604 | } |
| 1605 | |
| 1606 | static void |
| 1607 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) |
| 1608 | { |
| 1609 | list_del_init(&obj->ring_list); |
| 1610 | obj->last_rendering_seqno = 0; |
| 1611 | obj->last_fenced_seqno = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1612 | } |
| 1613 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1614 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1615 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1616 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1617 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1618 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1619 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1620 | BUG_ON(!obj->active); |
| 1621 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1622 | |
| 1623 | i915_gem_object_move_off_active(obj); |
| 1624 | } |
| 1625 | |
| 1626 | static void |
| 1627 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
| 1628 | { |
| 1629 | struct drm_device *dev = obj->base.dev; |
| 1630 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1631 | |
| 1632 | if (obj->pin_count != 0) |
| 1633 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); |
| 1634 | else |
| 1635 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
| 1636 | |
| 1637 | BUG_ON(!list_empty(&obj->gpu_write_list)); |
| 1638 | BUG_ON(!obj->active); |
| 1639 | obj->ring = NULL; |
| 1640 | |
| 1641 | i915_gem_object_move_off_active(obj); |
| 1642 | obj->fenced_gpu_access = false; |
| 1643 | obj->last_fenced_ring = NULL; |
| 1644 | |
| 1645 | obj->active = 0; |
| 1646 | drm_gem_object_unreference(&obj->base); |
| 1647 | |
| 1648 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1649 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1650 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1651 | /* Immediately discard the backing storage */ |
| 1652 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1653 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1654 | { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1655 | struct inode *inode; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1656 | |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1657 | /* Our goal here is to return as much of the memory as |
| 1658 | * is possible back to the system as we are called from OOM. |
| 1659 | * To do this we must instruct the shmfs to drop all of its |
| 1660 | * backing pages, *now*. Here we mirror the actions taken |
| 1661 | * when by shmem_delete_inode() to release the backing store. |
| 1662 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1663 | inode = obj->base.filp->f_path.dentry->d_inode; |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1664 | truncate_inode_pages(inode->i_mapping, 0); |
| 1665 | if (inode->i_op->truncate_range) |
| 1666 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1667 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1668 | obj->madv = __I915_MADV_PURGED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1669 | } |
| 1670 | |
| 1671 | static inline int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1672 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1673 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1674 | return obj->madv == I915_MADV_DONTNEED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1675 | } |
| 1676 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1677 | static void |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1678 | i915_gem_process_flushing_list(struct drm_device *dev, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1679 | uint32_t flush_domains, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1680 | struct intel_ring_buffer *ring) |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1681 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1682 | struct drm_i915_gem_object *obj, *next; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1683 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1684 | list_for_each_entry_safe(obj, next, |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 1685 | &ring->gpu_write_list, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1686 | gpu_write_list) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1687 | if (obj->base.write_domain & flush_domains) { |
| 1688 | uint32_t old_write_domain = obj->base.write_domain; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1689 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1690 | obj->base.write_domain = 0; |
| 1691 | list_del_init(&obj->gpu_write_list); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1692 | i915_gem_object_move_to_active(obj, ring); |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1693 | |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1694 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1695 | obj->base.read_domains, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1696 | old_write_domain); |
| 1697 | } |
| 1698 | } |
| 1699 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1700 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1701 | int |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1702 | i915_add_request(struct drm_device *dev, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1703 | struct drm_file *file, |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 1704 | struct drm_i915_gem_request *request, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1705 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1706 | { |
| 1707 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1708 | struct drm_i915_file_private *file_priv = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1709 | uint32_t seqno; |
| 1710 | int was_empty; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1711 | int ret; |
| 1712 | |
| 1713 | BUG_ON(request == NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1714 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1715 | if (file != NULL) |
| 1716 | file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1717 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1718 | ret = ring->add_request(ring, &seqno); |
| 1719 | if (ret) |
| 1720 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1721 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1722 | ring->outstanding_lazy_request = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1723 | |
| 1724 | request->seqno = seqno; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1725 | request->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1726 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1727 | was_empty = list_empty(&ring->request_list); |
| 1728 | list_add_tail(&request->list, &ring->request_list); |
| 1729 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1730 | if (file_priv) { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1731 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1732 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1733 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1734 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1735 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1736 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1737 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1738 | if (!dev_priv->mm.suspended) { |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1739 | mod_timer(&dev_priv->hangcheck_timer, |
| 1740 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1741 | if (was_empty) |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1742 | queue_delayed_work(dev_priv->wq, |
| 1743 | &dev_priv->mm.retire_work, HZ); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1744 | } |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1745 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1746 | } |
| 1747 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1748 | static inline void |
| 1749 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1750 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1751 | struct drm_i915_file_private *file_priv = request->file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1752 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1753 | if (!file_priv) |
| 1754 | return; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1755 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1756 | spin_lock(&file_priv->mm.lock); |
| 1757 | list_del(&request->client_list); |
| 1758 | request->file_priv = NULL; |
| 1759 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1760 | } |
| 1761 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1762 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
| 1763 | struct intel_ring_buffer *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1764 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1765 | while (!list_empty(&ring->request_list)) { |
| 1766 | struct drm_i915_gem_request *request; |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1767 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1768 | request = list_first_entry(&ring->request_list, |
| 1769 | struct drm_i915_gem_request, |
| 1770 | list); |
| 1771 | |
| 1772 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1773 | i915_gem_request_remove_from_client(request); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1774 | kfree(request); |
| 1775 | } |
| 1776 | |
| 1777 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1778 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1779 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1780 | obj = list_first_entry(&ring->active_list, |
| 1781 | struct drm_i915_gem_object, |
| 1782 | ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1783 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1784 | obj->base.write_domain = 0; |
| 1785 | list_del_init(&obj->gpu_write_list); |
| 1786 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1787 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1788 | } |
| 1789 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1790 | static void i915_gem_reset_fences(struct drm_device *dev) |
| 1791 | { |
| 1792 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1793 | int i; |
| 1794 | |
| 1795 | for (i = 0; i < 16; i++) { |
| 1796 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame^] | 1797 | struct drm_i915_gem_object *obj = reg->obj; |
| 1798 | |
| 1799 | if (!obj) |
| 1800 | continue; |
| 1801 | |
| 1802 | if (obj->tiling_mode) |
| 1803 | i915_gem_release_mmap(obj); |
| 1804 | |
| 1805 | i915_gem_clear_fence_reg(obj); |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1806 | } |
| 1807 | } |
| 1808 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1809 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1810 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1811 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1812 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1813 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1814 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 1815 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1816 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1817 | |
| 1818 | /* Remove anything from the flushing lists. The GPU cache is likely |
| 1819 | * to be lost on reset along with the data, so simply move the |
| 1820 | * lost bo to the inactive list. |
| 1821 | */ |
| 1822 | while (!list_empty(&dev_priv->mm.flushing_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1823 | obj= list_first_entry(&dev_priv->mm.flushing_list, |
| 1824 | struct drm_i915_gem_object, |
| 1825 | mm_list); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1826 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1827 | obj->base.write_domain = 0; |
| 1828 | list_del_init(&obj->gpu_write_list); |
| 1829 | i915_gem_object_move_to_inactive(obj); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1830 | } |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1831 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1832 | /* Move everything out of the GPU domains to ensure we do any |
| 1833 | * necessary invalidation upon reuse. |
| 1834 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1835 | list_for_each_entry(obj, |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1836 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1837 | mm_list) |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1838 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1839 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1840 | } |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1841 | |
| 1842 | /* The fence registers are invalidated so clear them out */ |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1843 | i915_gem_reset_fences(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1844 | } |
| 1845 | |
| 1846 | /** |
| 1847 | * This function clears the request list as sequence numbers are passed. |
| 1848 | */ |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1849 | static void |
| 1850 | i915_gem_retire_requests_ring(struct drm_device *dev, |
| 1851 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1852 | { |
| 1853 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1854 | uint32_t seqno; |
| 1855 | |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1856 | if (!ring->status_page.page_addr || |
| 1857 | list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 1858 | return; |
| 1859 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1860 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1861 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1862 | seqno = ring->get_seqno(ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1863 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1864 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1865 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1866 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1867 | struct drm_i915_gem_request, |
| 1868 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1869 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1870 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1871 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1872 | |
| 1873 | trace_i915_gem_request_retire(dev, request->seqno); |
| 1874 | |
| 1875 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1876 | i915_gem_request_remove_from_client(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1877 | kfree(request); |
| 1878 | } |
| 1879 | |
| 1880 | /* Move any buffers on the active list that are no longer referenced |
| 1881 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 1882 | */ |
| 1883 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1884 | struct drm_i915_gem_object *obj; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1885 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1886 | obj= list_first_entry(&ring->active_list, |
| 1887 | struct drm_i915_gem_object, |
| 1888 | ring_list); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1889 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1890 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1891 | break; |
| 1892 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1893 | if (obj->base.write_domain != 0) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1894 | i915_gem_object_move_to_flushing(obj); |
| 1895 | else |
| 1896 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1897 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1898 | |
| 1899 | if (unlikely (dev_priv->trace_irq_seqno && |
| 1900 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1901 | ring->user_irq_put(ring); |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1902 | dev_priv->trace_irq_seqno = 0; |
| 1903 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1904 | |
| 1905 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1906 | } |
| 1907 | |
| 1908 | void |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1909 | i915_gem_retire_requests(struct drm_device *dev) |
| 1910 | { |
| 1911 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1912 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1913 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1914 | struct drm_i915_gem_object *obj, *next; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1915 | |
| 1916 | /* We must be careful that during unbind() we do not |
| 1917 | * accidentally infinitely recurse into retire requests. |
| 1918 | * Currently: |
| 1919 | * retire -> free -> unbind -> wait -> retire_ring |
| 1920 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1921 | list_for_each_entry_safe(obj, next, |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1922 | &dev_priv->mm.deferred_free_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1923 | mm_list) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1924 | i915_gem_free_object_tail(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1925 | } |
| 1926 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1927 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 1928 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1929 | i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1930 | } |
| 1931 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 1932 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1933 | i915_gem_retire_work_handler(struct work_struct *work) |
| 1934 | { |
| 1935 | drm_i915_private_t *dev_priv; |
| 1936 | struct drm_device *dev; |
| 1937 | |
| 1938 | dev_priv = container_of(work, drm_i915_private_t, |
| 1939 | mm.retire_work.work); |
| 1940 | dev = dev_priv->dev; |
| 1941 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 1942 | /* Come back later if the device is busy... */ |
| 1943 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 1944 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 1945 | return; |
| 1946 | } |
| 1947 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1948 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1949 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 1950 | if (!dev_priv->mm.suspended && |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1951 | (!list_empty(&dev_priv->render_ring.request_list) || |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1952 | !list_empty(&dev_priv->bsd_ring.request_list) || |
| 1953 | !list_empty(&dev_priv->blt_ring.request_list))) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1954 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1955 | mutex_unlock(&dev->struct_mutex); |
| 1956 | } |
| 1957 | |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 1958 | int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1959 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1960 | bool interruptible, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1961 | { |
| 1962 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1963 | u32 ier; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1964 | int ret = 0; |
| 1965 | |
| 1966 | BUG_ON(seqno == 0); |
| 1967 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1968 | if (atomic_read(&dev_priv->mm.wedged)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 1969 | return -EAGAIN; |
Ben Gamari | ffed1d0 | 2009-09-14 17:48:41 -0400 | [diff] [blame] | 1970 | |
Chris Wilson | 5d97eb6 | 2010-11-10 20:40:02 +0000 | [diff] [blame] | 1971 | if (seqno == ring->outstanding_lazy_request) { |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1972 | struct drm_i915_gem_request *request; |
| 1973 | |
| 1974 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 1975 | if (request == NULL) |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1976 | return -ENOMEM; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1977 | |
| 1978 | ret = i915_add_request(dev, NULL, request, ring); |
| 1979 | if (ret) { |
| 1980 | kfree(request); |
| 1981 | return ret; |
| 1982 | } |
| 1983 | |
| 1984 | seqno = request->seqno; |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1985 | } |
| 1986 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1987 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1988 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1989 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
| 1990 | else |
| 1991 | ier = I915_READ(IER); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1992 | if (!ier) { |
| 1993 | DRM_ERROR("something (likely vbetool) disabled " |
| 1994 | "interrupts, re-enabling\n"); |
| 1995 | i915_driver_irq_preinstall(dev); |
| 1996 | i915_driver_irq_postinstall(dev); |
| 1997 | } |
| 1998 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1999 | trace_i915_gem_request_wait_begin(dev, seqno); |
| 2000 | |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 2001 | ring->waiting_seqno = seqno; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2002 | ring->user_irq_get(ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2003 | if (interruptible) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2004 | ret = wait_event_interruptible(ring->irq_queue, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2005 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2006 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2007 | else |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2008 | wait_event(ring->irq_queue, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2009 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2010 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2011 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2012 | ring->user_irq_put(ring); |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 2013 | ring->waiting_seqno = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2014 | |
| 2015 | trace_i915_gem_request_wait_end(dev, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2016 | } |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 2017 | if (atomic_read(&dev_priv->mm.wedged)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 2018 | ret = -EAGAIN; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2019 | |
| 2020 | if (ret && ret != -ERESTARTSYS) |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2021 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2022 | __func__, ret, seqno, ring->get_seqno(ring), |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2023 | dev_priv->next_seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2024 | |
| 2025 | /* Directly dispatch request retiring. While we have the work queue |
| 2026 | * to handle this, the waiter on a request often wants an associated |
| 2027 | * buffer to have made it to the inactive list, and we would need |
| 2028 | * a separate wait queue to handle that. |
| 2029 | */ |
| 2030 | if (ret == 0) |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2031 | i915_gem_retire_requests_ring(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2032 | |
| 2033 | return ret; |
| 2034 | } |
| 2035 | |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2036 | /** |
| 2037 | * Waits for a sequence number to be signaled, and cleans up the |
| 2038 | * request and object lists appropriately for that event. |
| 2039 | */ |
| 2040 | static int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2041 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2042 | struct intel_ring_buffer *ring) |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2043 | { |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2044 | return i915_do_wait_request(dev, seqno, 1, ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2045 | } |
| 2046 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2047 | /** |
| 2048 | * Ensures that all rendering to the object has completed and the object is |
| 2049 | * safe to unbind from the GTT or access from the CPU. |
| 2050 | */ |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2051 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2052 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2053 | bool interruptible) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2054 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2055 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2056 | int ret; |
| 2057 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2058 | /* This function only exists to support waiting for existing rendering, |
| 2059 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2060 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2061 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2062 | |
| 2063 | /* If there is rendering queued on the buffer being evicted, wait for |
| 2064 | * it. |
| 2065 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2066 | if (obj->active) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2067 | ret = i915_do_wait_request(dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2068 | obj->last_rendering_seqno, |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2069 | interruptible, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2070 | obj->ring); |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2071 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2072 | return ret; |
| 2073 | } |
| 2074 | |
| 2075 | return 0; |
| 2076 | } |
| 2077 | |
| 2078 | /** |
| 2079 | * Unbinds an object from the GTT aperture. |
| 2080 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2081 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2082 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2083 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2084 | int ret = 0; |
| 2085 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2086 | if (obj->gtt_space == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2087 | return 0; |
| 2088 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2089 | if (obj->pin_count != 0) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2090 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
| 2091 | return -EINVAL; |
| 2092 | } |
| 2093 | |
Eric Anholt | 5323fd0 | 2009-09-09 11:50:45 -0700 | [diff] [blame] | 2094 | /* blow away mappings if mapped through GTT */ |
| 2095 | i915_gem_release_mmap(obj); |
| 2096 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2097 | /* Move the object to the CPU domain to ensure that |
| 2098 | * any possible CPU writes while it's not in the GTT |
| 2099 | * are flushed when we go to remap it. This will |
| 2100 | * also ensure that all pending GPU writes are finished |
| 2101 | * before we unbind. |
| 2102 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2103 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2104 | if (ret == -ERESTARTSYS) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2105 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2106 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2107 | * should be safe and we need to cleanup or else we might |
| 2108 | * cause memory corruption through use-after-free. |
| 2109 | */ |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2110 | if (ret) { |
| 2111 | i915_gem_clflush_object(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2112 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2113 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2114 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2115 | /* release the fence reg _after_ flushing */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2116 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2117 | i915_gem_clear_fence_reg(obj); |
| 2118 | |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 2119 | i915_gem_gtt_unbind_object(obj); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2120 | i915_gem_object_put_pages_gtt(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2121 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2122 | list_del_init(&obj->gtt_list); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2123 | list_del_init(&obj->mm_list); |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2124 | /* Avoid an unnecessary call to unbind on rebind. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2125 | obj->map_and_fenceable = true; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2126 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2127 | drm_mm_put_block(obj->gtt_space); |
| 2128 | obj->gtt_space = NULL; |
| 2129 | obj->gtt_offset = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2130 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2131 | if (i915_gem_object_is_purgeable(obj)) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2132 | i915_gem_object_truncate(obj); |
| 2133 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2134 | trace_i915_gem_object_unbind(obj); |
| 2135 | |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2136 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2137 | } |
| 2138 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2139 | void |
| 2140 | i915_gem_flush_ring(struct drm_device *dev, |
| 2141 | struct intel_ring_buffer *ring, |
| 2142 | uint32_t invalidate_domains, |
| 2143 | uint32_t flush_domains) |
| 2144 | { |
| 2145 | ring->flush(ring, invalidate_domains, flush_domains); |
| 2146 | i915_gem_process_flushing_list(dev, flush_domains, ring); |
| 2147 | } |
| 2148 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2149 | static int i915_ring_idle(struct drm_device *dev, |
| 2150 | struct intel_ring_buffer *ring) |
| 2151 | { |
Chris Wilson | 395b70b | 2010-10-28 21:28:46 +0100 | [diff] [blame] | 2152 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 2153 | return 0; |
| 2154 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2155 | i915_gem_flush_ring(dev, ring, |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2156 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 2157 | return i915_wait_request(dev, |
| 2158 | i915_gem_next_request_seqno(dev, ring), |
| 2159 | ring); |
| 2160 | } |
| 2161 | |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 2162 | int |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2163 | i915_gpu_idle(struct drm_device *dev) |
| 2164 | { |
| 2165 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2166 | bool lists_empty; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2167 | int ret; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2168 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2169 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
Chris Wilson | 395b70b | 2010-10-28 21:28:46 +0100 | [diff] [blame] | 2170 | list_empty(&dev_priv->mm.active_list)); |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2171 | if (lists_empty) |
| 2172 | return 0; |
| 2173 | |
| 2174 | /* Flush everything onto the inactive list. */ |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2175 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2176 | if (ret) |
| 2177 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2178 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 2179 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
| 2180 | if (ret) |
| 2181 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2182 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2183 | ret = i915_ring_idle(dev, &dev_priv->blt_ring); |
| 2184 | if (ret) |
| 2185 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2186 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2187 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2188 | } |
| 2189 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2190 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2191 | struct intel_ring_buffer *pipelined) |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2192 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2193 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2194 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2195 | u32 size = obj->gtt_space->size; |
| 2196 | int regnum = obj->fence_reg; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2197 | uint64_t val; |
| 2198 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2199 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2200 | 0xfffff000) << 32; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2201 | val |= obj->gtt_offset & 0xfffff000; |
| 2202 | val |= (uint64_t)((obj->stride / 128) - 1) << |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2203 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 2204 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2205 | if (obj->tiling_mode == I915_TILING_Y) |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2206 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2207 | val |= I965_FENCE_REG_VALID; |
| 2208 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2209 | if (pipelined) { |
| 2210 | int ret = intel_ring_begin(pipelined, 6); |
| 2211 | if (ret) |
| 2212 | return ret; |
| 2213 | |
| 2214 | intel_ring_emit(pipelined, MI_NOOP); |
| 2215 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); |
| 2216 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); |
| 2217 | intel_ring_emit(pipelined, (u32)val); |
| 2218 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); |
| 2219 | intel_ring_emit(pipelined, (u32)(val >> 32)); |
| 2220 | intel_ring_advance(pipelined); |
| 2221 | } else |
| 2222 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); |
| 2223 | |
| 2224 | return 0; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2225 | } |
| 2226 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2227 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2228 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2229 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2230 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2231 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2232 | u32 size = obj->gtt_space->size; |
| 2233 | int regnum = obj->fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2234 | uint64_t val; |
| 2235 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2236 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2237 | 0xfffff000) << 32; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2238 | val |= obj->gtt_offset & 0xfffff000; |
| 2239 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2240 | if (obj->tiling_mode == I915_TILING_Y) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2241 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2242 | val |= I965_FENCE_REG_VALID; |
| 2243 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2244 | if (pipelined) { |
| 2245 | int ret = intel_ring_begin(pipelined, 6); |
| 2246 | if (ret) |
| 2247 | return ret; |
| 2248 | |
| 2249 | intel_ring_emit(pipelined, MI_NOOP); |
| 2250 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); |
| 2251 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); |
| 2252 | intel_ring_emit(pipelined, (u32)val); |
| 2253 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); |
| 2254 | intel_ring_emit(pipelined, (u32)(val >> 32)); |
| 2255 | intel_ring_advance(pipelined); |
| 2256 | } else |
| 2257 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); |
| 2258 | |
| 2259 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2260 | } |
| 2261 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2262 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2263 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2264 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2265 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2266 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2267 | u32 size = obj->gtt_space->size; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2268 | u32 fence_reg, val, pitch_val; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2269 | int tile_width; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2270 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2271 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2272 | (size & -size) != size || |
| 2273 | (obj->gtt_offset & (size - 1)), |
| 2274 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
| 2275 | obj->gtt_offset, obj->map_and_fenceable, size)) |
| 2276 | return -EINVAL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2277 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2278 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2279 | tile_width = 128; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2280 | else |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2281 | tile_width = 512; |
| 2282 | |
| 2283 | /* Note: pitch better be a power of two tile widths */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2284 | pitch_val = obj->stride / tile_width; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2285 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2286 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2287 | val = obj->gtt_offset; |
| 2288 | if (obj->tiling_mode == I915_TILING_Y) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2289 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2290 | val |= I915_FENCE_SIZE_BITS(size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2291 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2292 | val |= I830_FENCE_REG_VALID; |
| 2293 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2294 | fence_reg = obj->fence_reg; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2295 | if (fence_reg < 8) |
| 2296 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2297 | else |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2298 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2299 | |
| 2300 | if (pipelined) { |
| 2301 | int ret = intel_ring_begin(pipelined, 4); |
| 2302 | if (ret) |
| 2303 | return ret; |
| 2304 | |
| 2305 | intel_ring_emit(pipelined, MI_NOOP); |
| 2306 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); |
| 2307 | intel_ring_emit(pipelined, fence_reg); |
| 2308 | intel_ring_emit(pipelined, val); |
| 2309 | intel_ring_advance(pipelined); |
| 2310 | } else |
| 2311 | I915_WRITE(fence_reg, val); |
| 2312 | |
| 2313 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2314 | } |
| 2315 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2316 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2317 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2318 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2319 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2320 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2321 | u32 size = obj->gtt_space->size; |
| 2322 | int regnum = obj->fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2323 | uint32_t val; |
| 2324 | uint32_t pitch_val; |
| 2325 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2326 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
| 2327 | (size & -size) != size || |
| 2328 | (obj->gtt_offset & (size - 1)), |
| 2329 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", |
| 2330 | obj->gtt_offset, size)) |
| 2331 | return -EINVAL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2332 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2333 | pitch_val = obj->stride / 128; |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2334 | pitch_val = ffs(pitch_val) - 1; |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2335 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2336 | val = obj->gtt_offset; |
| 2337 | if (obj->tiling_mode == I915_TILING_Y) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2338 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2339 | val |= I830_FENCE_SIZE_BITS(size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2340 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2341 | val |= I830_FENCE_REG_VALID; |
| 2342 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2343 | if (pipelined) { |
| 2344 | int ret = intel_ring_begin(pipelined, 4); |
| 2345 | if (ret) |
| 2346 | return ret; |
| 2347 | |
| 2348 | intel_ring_emit(pipelined, MI_NOOP); |
| 2349 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); |
| 2350 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); |
| 2351 | intel_ring_emit(pipelined, val); |
| 2352 | intel_ring_advance(pipelined); |
| 2353 | } else |
| 2354 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); |
| 2355 | |
| 2356 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2357 | } |
| 2358 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2359 | static int i915_find_fence_reg(struct drm_device *dev, |
| 2360 | bool interruptible) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2361 | { |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2362 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2363 | struct drm_i915_fence_reg *reg; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2364 | struct drm_i915_gem_object *obj = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2365 | int i, avail, ret; |
| 2366 | |
| 2367 | /* First try to find a free reg */ |
| 2368 | avail = 0; |
| 2369 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2370 | reg = &dev_priv->fence_regs[i]; |
| 2371 | if (!reg->obj) |
| 2372 | return i; |
| 2373 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2374 | if (!reg->obj->pin_count) |
| 2375 | avail++; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2376 | } |
| 2377 | |
| 2378 | if (avail == 0) |
| 2379 | return -ENOSPC; |
| 2380 | |
| 2381 | /* None available, try to steal one or wait for a user to finish */ |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2382 | avail = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2383 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
| 2384 | lru_list) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2385 | obj = reg->obj; |
| 2386 | if (obj->pin_count) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2387 | continue; |
| 2388 | |
| 2389 | /* found one! */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2390 | avail = obj->fence_reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2391 | break; |
| 2392 | } |
| 2393 | |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2394 | BUG_ON(avail == I915_FENCE_REG_NONE); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2395 | |
| 2396 | /* We only have a reference on obj from the active list. put_fence_reg |
| 2397 | * might drop that one, causing a use-after-free in it. So hold a |
| 2398 | * private reference to obj like the other callers of put_fence_reg |
| 2399 | * (set_tiling ioctl) do. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2400 | drm_gem_object_reference(&obj->base); |
| 2401 | ret = i915_gem_object_put_fence_reg(obj, interruptible); |
| 2402 | drm_gem_object_unreference(&obj->base); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2403 | if (ret != 0) |
| 2404 | return ret; |
| 2405 | |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2406 | return avail; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2407 | } |
| 2408 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2409 | /** |
| 2410 | * i915_gem_object_get_fence_reg - set up a fence reg for an object |
| 2411 | * @obj: object to map through a fence reg |
| 2412 | * |
| 2413 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2414 | * to them without having to worry about swizzling if the object is tiled. |
| 2415 | * |
| 2416 | * This function walks the fence regs looking for a free one for @obj, |
| 2417 | * stealing one if it can't find any. |
| 2418 | * |
| 2419 | * It then sets up the reg based on the object's properties: address, pitch |
| 2420 | * and tiling format. |
| 2421 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2422 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2423 | i915_gem_object_get_fence_reg(struct drm_i915_gem_object *obj, |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2424 | bool interruptible) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2425 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2426 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2427 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2428 | struct drm_i915_fence_reg *reg = NULL; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2429 | struct intel_ring_buffer *pipelined = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2430 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2431 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2432 | /* Just update our place in the LRU if our fence is getting used. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2433 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2434 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2435 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2436 | return 0; |
| 2437 | } |
| 2438 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2439 | switch (obj->tiling_mode) { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2440 | case I915_TILING_NONE: |
| 2441 | WARN(1, "allocating a fence for non-tiled object?\n"); |
| 2442 | break; |
| 2443 | case I915_TILING_X: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2444 | if (!obj->stride) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2445 | return -EINVAL; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2446 | WARN((obj->stride & (512 - 1)), |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2447 | "object 0x%08x is X tiled but has non-512B pitch\n", |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2448 | obj->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2449 | break; |
| 2450 | case I915_TILING_Y: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2451 | if (!obj->stride) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2452 | return -EINVAL; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2453 | WARN((obj->stride & (128 - 1)), |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2454 | "object 0x%08x is Y tiled but has non-128B pitch\n", |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2455 | obj->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2456 | break; |
| 2457 | } |
| 2458 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2459 | ret = i915_find_fence_reg(dev, interruptible); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2460 | if (ret < 0) |
| 2461 | return ret; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2462 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2463 | obj->fence_reg = ret; |
| 2464 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2465 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2466 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2467 | reg->obj = obj; |
| 2468 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2469 | switch (INTEL_INFO(dev)->gen) { |
| 2470 | case 6: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2471 | ret = sandybridge_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2472 | break; |
| 2473 | case 5: |
| 2474 | case 4: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2475 | ret = i965_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2476 | break; |
| 2477 | case 3: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2478 | ret = i915_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2479 | break; |
| 2480 | case 2: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2481 | ret = i830_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2482 | break; |
| 2483 | } |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2484 | |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2485 | trace_i915_gem_object_get_fence(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2486 | obj->fence_reg, |
| 2487 | obj->tiling_mode); |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2488 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2489 | } |
| 2490 | |
| 2491 | /** |
| 2492 | * i915_gem_clear_fence_reg - clear out fence register info |
| 2493 | * @obj: object to clear |
| 2494 | * |
| 2495 | * Zeroes out the fence register itself and clears out the associated |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2496 | * data structures in dev_priv and obj. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2497 | */ |
| 2498 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2499 | i915_gem_clear_fence_reg(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2500 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2501 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2502 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2503 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[obj->fence_reg]; |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2504 | uint32_t fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2505 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2506 | switch (INTEL_INFO(dev)->gen) { |
| 2507 | case 6: |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2508 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2509 | (obj->fence_reg * 8), 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2510 | break; |
| 2511 | case 5: |
| 2512 | case 4: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2513 | I915_WRITE64(FENCE_REG_965_0 + (obj->fence_reg * 8), 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2514 | break; |
| 2515 | case 3: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2516 | if (obj->fence_reg >= 8) |
| 2517 | fence_reg = FENCE_REG_945_8 + (obj->fence_reg - 8) * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2518 | else |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2519 | case 2: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2520 | fence_reg = FENCE_REG_830_0 + obj->fence_reg * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2521 | |
| 2522 | I915_WRITE(fence_reg, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2523 | break; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2524 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2525 | |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2526 | reg->obj = NULL; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2527 | obj->fence_reg = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2528 | list_del_init(®->lru_list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2529 | } |
| 2530 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2531 | /** |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2532 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access |
| 2533 | * to the buffer to finish, and then resets the fence register. |
| 2534 | * @obj: tiled object holding a fence register. |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2535 | * @bool: whether the wait upon the fence is interruptible |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2536 | * |
| 2537 | * Zeroes out the fence register itself and clears out the associated |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2538 | * data structures in dev_priv and obj. |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2539 | */ |
| 2540 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2541 | i915_gem_object_put_fence_reg(struct drm_i915_gem_object *obj, |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2542 | bool interruptible) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2543 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2544 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2545 | int ret; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2546 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2547 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2548 | return 0; |
| 2549 | |
Daniel Vetter | 10ae9bd | 2010-02-01 13:59:17 +0100 | [diff] [blame] | 2550 | /* If we've changed tiling, GTT-mappings of the object |
| 2551 | * need to re-fault to ensure that the correct fence register |
| 2552 | * setup is in place. |
| 2553 | */ |
| 2554 | i915_gem_release_mmap(obj); |
| 2555 | |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2556 | /* On the i915, GPU access to tiled buffers is via a fence, |
| 2557 | * therefore we must wait for any outstanding access to complete |
| 2558 | * before clearing the fence. |
| 2559 | */ |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2560 | if (obj->fenced_gpu_access) { |
Chris Wilson | 3619df0 | 2010-11-28 15:37:17 +0000 | [diff] [blame] | 2561 | i915_gem_object_flush_gpu_write_domain(obj); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2562 | obj->fenced_gpu_access = false; |
| 2563 | } |
| 2564 | |
| 2565 | if (obj->last_fenced_seqno) { |
| 2566 | ret = i915_do_wait_request(dev, |
| 2567 | obj->last_fenced_seqno, |
| 2568 | interruptible, |
| 2569 | obj->last_fenced_ring); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2570 | if (ret) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2571 | return ret; |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2572 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2573 | obj->last_fenced_seqno = false; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2574 | } |
| 2575 | |
Daniel Vetter | 4a72661 | 2010-02-01 13:59:16 +0100 | [diff] [blame] | 2576 | i915_gem_object_flush_gtt_write_domain(obj); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2577 | i915_gem_clear_fence_reg(obj); |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2578 | |
| 2579 | return 0; |
| 2580 | } |
| 2581 | |
| 2582 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2583 | * Finds free space in the GTT aperture and binds the object there. |
| 2584 | */ |
| 2585 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2586 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2587 | unsigned alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2588 | bool map_and_fenceable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2589 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2590 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2591 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2592 | struct drm_mm_node *free_space; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2593 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2594 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2595 | bool mappable, fenceable; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2596 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2597 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2598 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2599 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2600 | return -EINVAL; |
| 2601 | } |
| 2602 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2603 | fence_size = i915_gem_get_gtt_size(obj); |
| 2604 | fence_alignment = i915_gem_get_gtt_alignment(obj); |
| 2605 | unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2606 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2607 | if (alignment == 0) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2608 | alignment = map_and_fenceable ? fence_alignment : |
| 2609 | unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2610 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2611 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2612 | return -EINVAL; |
| 2613 | } |
| 2614 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2615 | size = map_and_fenceable ? fence_size : obj->base.size; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2616 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2617 | /* If the object is bigger than the entire aperture, reject it early |
| 2618 | * before evicting everything in a vain attempt to find space. |
| 2619 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2620 | if (obj->base.size > |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2621 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2622 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
| 2623 | return -E2BIG; |
| 2624 | } |
| 2625 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2626 | search_free: |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2627 | if (map_and_fenceable) |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2628 | free_space = |
| 2629 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2630 | size, alignment, 0, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2631 | dev_priv->mm.gtt_mappable_end, |
| 2632 | 0); |
| 2633 | else |
| 2634 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2635 | size, alignment, 0); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2636 | |
| 2637 | if (free_space != NULL) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2638 | if (map_and_fenceable) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2639 | obj->gtt_space = |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2640 | drm_mm_get_block_range_generic(free_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2641 | size, alignment, 0, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2642 | dev_priv->mm.gtt_mappable_end, |
| 2643 | 0); |
| 2644 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2645 | obj->gtt_space = |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2646 | drm_mm_get_block(free_space, size, alignment); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2647 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2648 | if (obj->gtt_space == NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2649 | /* If the gtt is empty and we're still having trouble |
| 2650 | * fitting our object in, we're out of memory. |
| 2651 | */ |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2652 | ret = i915_gem_evict_something(dev, size, alignment, |
| 2653 | map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2654 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2655 | return ret; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2656 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2657 | goto search_free; |
| 2658 | } |
| 2659 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2660 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2661 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2662 | drm_mm_put_block(obj->gtt_space); |
| 2663 | obj->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2664 | |
| 2665 | if (ret == -ENOMEM) { |
| 2666 | /* first try to clear up some space from the GTT */ |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2667 | ret = i915_gem_evict_something(dev, size, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2668 | alignment, |
| 2669 | map_and_fenceable); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2670 | if (ret) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2671 | /* now try to shrink everyone else */ |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2672 | if (gfpmask) { |
| 2673 | gfpmask = 0; |
| 2674 | goto search_free; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2675 | } |
| 2676 | |
| 2677 | return ret; |
| 2678 | } |
| 2679 | |
| 2680 | goto search_free; |
| 2681 | } |
| 2682 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2683 | return ret; |
| 2684 | } |
| 2685 | |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 2686 | ret = i915_gem_gtt_bind_object(obj); |
| 2687 | if (ret) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2688 | i915_gem_object_put_pages_gtt(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2689 | drm_mm_put_block(obj->gtt_space); |
| 2690 | obj->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2691 | |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2692 | ret = i915_gem_evict_something(dev, size, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2693 | alignment, map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2694 | if (ret) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2695 | return ret; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2696 | |
| 2697 | goto search_free; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2698 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2699 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2700 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2701 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2702 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2703 | /* Assert that the object is not currently in any GPU domain. As it |
| 2704 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2705 | * a GPU cache |
| 2706 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2707 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 2708 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2709 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2710 | obj->gtt_offset = obj->gtt_space->start; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2711 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2712 | fenceable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2713 | obj->gtt_space->size == fence_size && |
| 2714 | (obj->gtt_space->start & (fence_alignment -1)) == 0; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2715 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2716 | mappable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2717 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2718 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2719 | obj->map_and_fenceable = mappable && fenceable; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2720 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2721 | trace_i915_gem_object_bind(obj, obj->gtt_offset, map_and_fenceable); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2722 | return 0; |
| 2723 | } |
| 2724 | |
| 2725 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2726 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2727 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2728 | /* If we don't have a page list set up, then we're not pinned |
| 2729 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2730 | * again at bind time. |
| 2731 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2732 | if (obj->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2733 | return; |
| 2734 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2735 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 2736 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2737 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2738 | } |
| 2739 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2740 | /** Flushes any GPU write domain for the object if it's dirty. */ |
Chris Wilson | 3619df0 | 2010-11-28 15:37:17 +0000 | [diff] [blame] | 2741 | static void |
| 2742 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2743 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2744 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2745 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2746 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 3619df0 | 2010-11-28 15:37:17 +0000 | [diff] [blame] | 2747 | return; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2748 | |
| 2749 | /* Queue the GPU write cache flushing we need. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2750 | i915_gem_flush_ring(dev, obj->ring, 0, obj->base.write_domain); |
| 2751 | BUG_ON(obj->base.write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2752 | } |
| 2753 | |
| 2754 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 2755 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2756 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2757 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2758 | uint32_t old_write_domain; |
| 2759 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2760 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2761 | return; |
| 2762 | |
| 2763 | /* No actual flushing is required for the GTT write domain. Writes |
| 2764 | * to it immediately go to main memory as far as we know, so there's |
| 2765 | * no chipset flush. It also doesn't land in render cache. |
| 2766 | */ |
Chris Wilson | 4a684a4 | 2010-10-28 14:44:08 +0100 | [diff] [blame] | 2767 | i915_gem_release_mmap(obj); |
| 2768 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2769 | old_write_domain = obj->base.write_domain; |
| 2770 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2771 | |
| 2772 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2773 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2774 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2775 | } |
| 2776 | |
| 2777 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 2778 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2779 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2780 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2781 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2782 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2783 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2784 | return; |
| 2785 | |
| 2786 | i915_gem_clflush_object(obj); |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 2787 | intel_gtt_chipset_flush(); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2788 | old_write_domain = obj->base.write_domain; |
| 2789 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2790 | |
| 2791 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2792 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2793 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2794 | } |
| 2795 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2796 | /** |
| 2797 | * Moves a single object to the GTT read, and possibly write domain. |
| 2798 | * |
| 2799 | * This function returns when the move is complete, including waiting on |
| 2800 | * flushes to occur. |
| 2801 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2802 | int |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2803 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2804 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2805 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2806 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2807 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2808 | /* Not valid to be called on unbound objects. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2809 | if (obj->gtt_space == NULL) |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2810 | return -EINVAL; |
| 2811 | |
Chris Wilson | 3619df0 | 2010-11-28 15:37:17 +0000 | [diff] [blame] | 2812 | i915_gem_object_flush_gpu_write_domain(obj); |
Daniel Vetter | de18a29 | 2010-11-27 22:30:41 +0100 | [diff] [blame] | 2813 | ret = i915_gem_object_wait_rendering(obj, true); |
| 2814 | if (ret) |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2815 | return ret; |
| 2816 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2817 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2818 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2819 | old_write_domain = obj->base.write_domain; |
| 2820 | old_read_domains = obj->base.read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2821 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2822 | /* It should now be out of any other write domains, and we can update |
| 2823 | * the domain values for our changes. |
| 2824 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2825 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2826 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2827 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2828 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 2829 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 2830 | obj->dirty = 1; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2831 | } |
| 2832 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2833 | trace_i915_gem_object_change_domain(obj, |
| 2834 | old_read_domains, |
| 2835 | old_write_domain); |
| 2836 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2837 | return 0; |
| 2838 | } |
| 2839 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2840 | /* |
| 2841 | * Prepare buffer for display plane. Use uninterruptible for possible flush |
| 2842 | * wait, as in modesetting process we're not supposed to be interrupted. |
| 2843 | */ |
| 2844 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2845 | i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2846 | struct intel_ring_buffer *pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2847 | { |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2848 | uint32_t old_read_domains; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2849 | int ret; |
| 2850 | |
| 2851 | /* Not valid to be called on unbound objects. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2852 | if (obj->gtt_space == NULL) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2853 | return -EINVAL; |
| 2854 | |
Chris Wilson | 3619df0 | 2010-11-28 15:37:17 +0000 | [diff] [blame] | 2855 | i915_gem_object_flush_gpu_write_domain(obj); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2856 | |
Chris Wilson | ced270f | 2010-09-26 22:47:46 +0100 | [diff] [blame] | 2857 | /* Currently, we are always called from an non-interruptible context. */ |
| 2858 | if (!pipelined) { |
| 2859 | ret = i915_gem_object_wait_rendering(obj, false); |
| 2860 | if (ret) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2861 | return ret; |
| 2862 | } |
| 2863 | |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 2864 | i915_gem_object_flush_cpu_write_domain(obj); |
| 2865 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2866 | old_read_domains = obj->base.read_domains; |
| 2867 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2868 | |
| 2869 | trace_i915_gem_object_change_domain(obj, |
| 2870 | old_read_domains, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2871 | obj->base.write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2872 | |
| 2873 | return 0; |
| 2874 | } |
| 2875 | |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 2876 | int |
| 2877 | i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj, |
| 2878 | bool interruptible) |
| 2879 | { |
| 2880 | if (!obj->active) |
| 2881 | return 0; |
| 2882 | |
| 2883 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2884 | i915_gem_flush_ring(obj->base.dev, obj->ring, |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 2885 | 0, obj->base.write_domain); |
| 2886 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2887 | return i915_gem_object_wait_rendering(obj, interruptible); |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 2888 | } |
| 2889 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2890 | /** |
| 2891 | * Moves a single object to the CPU read, and possibly write domain. |
| 2892 | * |
| 2893 | * This function returns when the move is complete, including waiting on |
| 2894 | * flushes to occur. |
| 2895 | */ |
| 2896 | static int |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2897 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2898 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2899 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2900 | int ret; |
| 2901 | |
Chris Wilson | 3619df0 | 2010-11-28 15:37:17 +0000 | [diff] [blame] | 2902 | i915_gem_object_flush_gpu_write_domain(obj); |
Daniel Vetter | de18a29 | 2010-11-27 22:30:41 +0100 | [diff] [blame] | 2903 | ret = i915_gem_object_wait_rendering(obj, true); |
| 2904 | if (ret) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2905 | return ret; |
| 2906 | |
| 2907 | i915_gem_object_flush_gtt_write_domain(obj); |
| 2908 | |
| 2909 | /* If we have a partially-valid cache of the object in the CPU, |
| 2910 | * finish invalidating it and free the per-page flags. |
| 2911 | */ |
| 2912 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
| 2913 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2914 | old_write_domain = obj->base.write_domain; |
| 2915 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2916 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2917 | /* Flush the CPU cache if it's still invalid. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2918 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2919 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2920 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2921 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2922 | } |
| 2923 | |
| 2924 | /* It should now be out of any other write domains, and we can update |
| 2925 | * the domain values for our changes. |
| 2926 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2927 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2928 | |
| 2929 | /* If we're writing through the CPU, then the GPU read domains will |
| 2930 | * need to be invalidated at next use. |
| 2931 | */ |
| 2932 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2933 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 2934 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2935 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2936 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2937 | trace_i915_gem_object_change_domain(obj, |
| 2938 | old_read_domains, |
| 2939 | old_write_domain); |
| 2940 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2941 | return 0; |
| 2942 | } |
| 2943 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2944 | /** |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2945 | * Moves the object from a partially CPU read to a full one. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2946 | * |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2947 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
| 2948 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). |
| 2949 | */ |
| 2950 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2951 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2952 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2953 | if (!obj->page_cpu_valid) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2954 | return; |
| 2955 | |
| 2956 | /* If we're partially in the CPU read domain, finish moving it in. |
| 2957 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2958 | if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2959 | int i; |
| 2960 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2961 | for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) { |
| 2962 | if (obj->page_cpu_valid[i]) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2963 | continue; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2964 | drm_clflush_pages(obj->pages + i, 1); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2965 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2966 | } |
| 2967 | |
| 2968 | /* Free the page_cpu_valid mappings which are now stale, whether |
| 2969 | * or not we've got I915_GEM_DOMAIN_CPU. |
| 2970 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2971 | kfree(obj->page_cpu_valid); |
| 2972 | obj->page_cpu_valid = NULL; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2973 | } |
| 2974 | |
| 2975 | /** |
| 2976 | * Set the CPU read domain on a range of the object. |
| 2977 | * |
| 2978 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's |
| 2979 | * not entirely valid. The page_cpu_valid member of the object flags which |
| 2980 | * pages have been flushed, and will be respected by |
| 2981 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping |
| 2982 | * of the whole object. |
| 2983 | * |
| 2984 | * This function returns when the move is complete, including waiting on |
| 2985 | * flushes to occur. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2986 | */ |
| 2987 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2988 | i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2989 | uint64_t offset, uint64_t size) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2990 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2991 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2992 | int i, ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2993 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2994 | if (offset == 0 && size == obj->base.size) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2995 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
| 2996 | |
Chris Wilson | 3619df0 | 2010-11-28 15:37:17 +0000 | [diff] [blame] | 2997 | i915_gem_object_flush_gpu_write_domain(obj); |
Daniel Vetter | de18a29 | 2010-11-27 22:30:41 +0100 | [diff] [blame] | 2998 | ret = i915_gem_object_wait_rendering(obj, true); |
| 2999 | if (ret) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3000 | return ret; |
Daniel Vetter | de18a29 | 2010-11-27 22:30:41 +0100 | [diff] [blame] | 3001 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3002 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3003 | |
| 3004 | /* If we're already fully in the CPU read domain, we're done. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3005 | if (obj->page_cpu_valid == NULL && |
| 3006 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3007 | return 0; |
| 3008 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3009 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
| 3010 | * newly adding I915_GEM_DOMAIN_CPU |
| 3011 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3012 | if (obj->page_cpu_valid == NULL) { |
| 3013 | obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE, |
| 3014 | GFP_KERNEL); |
| 3015 | if (obj->page_cpu_valid == NULL) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3016 | return -ENOMEM; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3017 | } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 3018 | memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3019 | |
| 3020 | /* Flush the cache on any pages that are still invalid from the CPU's |
| 3021 | * perspective. |
| 3022 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3023 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
| 3024 | i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3025 | if (obj->page_cpu_valid[i]) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3026 | continue; |
| 3027 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3028 | drm_clflush_pages(obj->pages + i, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3029 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3030 | obj->page_cpu_valid[i] = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3031 | } |
| 3032 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3033 | /* It should now be out of any other write domains, and we can update |
| 3034 | * the domain values for our changes. |
| 3035 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3036 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3037 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3038 | old_read_domains = obj->base.read_domains; |
| 3039 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3040 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3041 | trace_i915_gem_object_change_domain(obj, |
| 3042 | old_read_domains, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3043 | obj->base.write_domain); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3044 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3045 | return 0; |
| 3046 | } |
| 3047 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3048 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3049 | * emitted over 20 msec ago. |
| 3050 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3051 | * Note that if we were to use the current jiffies each time around the loop, |
| 3052 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3053 | * render a frame was over 20ms. |
| 3054 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3055 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3056 | * relatively low latency when blocking on a particular request to finish. |
| 3057 | */ |
| 3058 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3059 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3060 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3061 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3062 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3063 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3064 | struct drm_i915_gem_request *request; |
| 3065 | struct intel_ring_buffer *ring = NULL; |
| 3066 | u32 seqno = 0; |
| 3067 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3068 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3069 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3070 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3071 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3072 | break; |
| 3073 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3074 | ring = request->ring; |
| 3075 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3076 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3077 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3078 | |
| 3079 | if (seqno == 0) |
| 3080 | return 0; |
| 3081 | |
| 3082 | ret = 0; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3083 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3084 | /* And wait for the seqno passing without holding any locks and |
| 3085 | * causing extra latency for others. This is safe as the irq |
| 3086 | * generation is designed to be run atomically and so is |
| 3087 | * lockless. |
| 3088 | */ |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3089 | ring->user_irq_get(ring); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3090 | ret = wait_event_interruptible(ring->irq_queue, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3091 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3092 | || atomic_read(&dev_priv->mm.wedged)); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3093 | ring->user_irq_put(ring); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3094 | |
| 3095 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
| 3096 | ret = -EIO; |
| 3097 | } |
| 3098 | |
| 3099 | if (ret == 0) |
| 3100 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3101 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3102 | return ret; |
| 3103 | } |
| 3104 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3105 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3106 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 3107 | uint32_t alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3108 | bool map_and_fenceable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3109 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3110 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 3111 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3112 | int ret; |
| 3113 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3114 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3115 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3116 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3117 | if (obj->gtt_space != NULL) { |
| 3118 | if ((alignment && obj->gtt_offset & (alignment - 1)) || |
| 3119 | (map_and_fenceable && !obj->map_and_fenceable)) { |
| 3120 | WARN(obj->pin_count, |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 3121 | "bo is already pinned with incorrect alignment:" |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3122 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
| 3123 | " obj->map_and_fenceable=%d\n", |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3124 | obj->gtt_offset, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3125 | map_and_fenceable, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3126 | obj->map_and_fenceable); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3127 | ret = i915_gem_object_unbind(obj); |
| 3128 | if (ret) |
| 3129 | return ret; |
| 3130 | } |
| 3131 | } |
| 3132 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3133 | if (obj->gtt_space == NULL) { |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3134 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3135 | map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3136 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3137 | return ret; |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 3138 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3139 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3140 | if (obj->pin_count++ == 0) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3141 | if (!obj->active) |
| 3142 | list_move_tail(&obj->mm_list, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 3143 | &dev_priv->mm.pinned_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3144 | } |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3145 | obj->pin_mappable |= map_and_fenceable; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3146 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3147 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3148 | return 0; |
| 3149 | } |
| 3150 | |
| 3151 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3152 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3153 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3154 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3155 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3156 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3157 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3158 | BUG_ON(obj->pin_count == 0); |
| 3159 | BUG_ON(obj->gtt_space == NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3160 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3161 | if (--obj->pin_count == 0) { |
| 3162 | if (!obj->active) |
| 3163 | list_move_tail(&obj->mm_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3164 | &dev_priv->mm.inactive_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3165 | obj->pin_mappable = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3166 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3167 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3168 | } |
| 3169 | |
| 3170 | int |
| 3171 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3172 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3173 | { |
| 3174 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3175 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3176 | int ret; |
| 3177 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3178 | ret = i915_mutex_lock_interruptible(dev); |
| 3179 | if (ret) |
| 3180 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3181 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3182 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3183 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3184 | ret = -ENOENT; |
| 3185 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3186 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3187 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3188 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3189 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3190 | ret = -EINVAL; |
| 3191 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3192 | } |
| 3193 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3194 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3195 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 3196 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3197 | ret = -EINVAL; |
| 3198 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3199 | } |
| 3200 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3201 | obj->user_pin_count++; |
| 3202 | obj->pin_filp = file; |
| 3203 | if (obj->user_pin_count == 1) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3204 | ret = i915_gem_object_pin(obj, args->alignment, true); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3205 | if (ret) |
| 3206 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3207 | } |
| 3208 | |
| 3209 | /* XXX - flush the CPU caches for pinned objects |
| 3210 | * as the X server doesn't manage domains yet |
| 3211 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3212 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3213 | args->offset = obj->gtt_offset; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3214 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3215 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3216 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3217 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3218 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3219 | } |
| 3220 | |
| 3221 | int |
| 3222 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3223 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3224 | { |
| 3225 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3226 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3227 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3228 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3229 | ret = i915_mutex_lock_interruptible(dev); |
| 3230 | if (ret) |
| 3231 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3232 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3233 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3234 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3235 | ret = -ENOENT; |
| 3236 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3237 | } |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3238 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3239 | if (obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3240 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 3241 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3242 | ret = -EINVAL; |
| 3243 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3244 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3245 | obj->user_pin_count--; |
| 3246 | if (obj->user_pin_count == 0) { |
| 3247 | obj->pin_filp = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3248 | i915_gem_object_unpin(obj); |
| 3249 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3250 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3251 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3252 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3253 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3254 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3255 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3256 | } |
| 3257 | |
| 3258 | int |
| 3259 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3260 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3261 | { |
| 3262 | struct drm_i915_gem_busy *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3263 | struct drm_i915_gem_object *obj; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3264 | int ret; |
| 3265 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3266 | ret = i915_mutex_lock_interruptible(dev); |
| 3267 | if (ret) |
| 3268 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3269 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3270 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3271 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3272 | ret = -ENOENT; |
| 3273 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3274 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3275 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3276 | /* Count all active objects as busy, even if they are currently not used |
| 3277 | * by the gpu. Users of this interface expect objects to eventually |
| 3278 | * become non-busy without any further actions, therefore emit any |
| 3279 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 3280 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3281 | args->busy = obj->active; |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3282 | if (args->busy) { |
| 3283 | /* Unconditionally flush objects, even when the gpu still uses this |
| 3284 | * object. Userspace calling this function indicates that it wants to |
| 3285 | * use this buffer rather sooner than later, so issuing the required |
| 3286 | * flush earlier is beneficial. |
| 3287 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3288 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) |
| 3289 | i915_gem_flush_ring(dev, obj->ring, |
| 3290 | 0, obj->base.write_domain); |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3291 | |
| 3292 | /* Update the active list for the hardware's current position. |
| 3293 | * Otherwise this only updates on a delayed timer or when irqs |
| 3294 | * are actually unmasked, and our working set ends up being |
| 3295 | * larger than required. |
| 3296 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3297 | i915_gem_retire_requests_ring(dev, obj->ring); |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3298 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3299 | args->busy = obj->active; |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3300 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3301 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3302 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3303 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3304 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3305 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3306 | } |
| 3307 | |
| 3308 | int |
| 3309 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 3310 | struct drm_file *file_priv) |
| 3311 | { |
| 3312 | return i915_gem_ring_throttle(dev, file_priv); |
| 3313 | } |
| 3314 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3315 | int |
| 3316 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 3317 | struct drm_file *file_priv) |
| 3318 | { |
| 3319 | struct drm_i915_gem_madvise *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3320 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3321 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3322 | |
| 3323 | switch (args->madv) { |
| 3324 | case I915_MADV_DONTNEED: |
| 3325 | case I915_MADV_WILLNEED: |
| 3326 | break; |
| 3327 | default: |
| 3328 | return -EINVAL; |
| 3329 | } |
| 3330 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3331 | ret = i915_mutex_lock_interruptible(dev); |
| 3332 | if (ret) |
| 3333 | return ret; |
| 3334 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3335 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3336 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3337 | ret = -ENOENT; |
| 3338 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3339 | } |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3340 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3341 | if (obj->pin_count) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3342 | ret = -EINVAL; |
| 3343 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3344 | } |
| 3345 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3346 | if (obj->madv != __I915_MADV_PURGED) |
| 3347 | obj->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3348 | |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 3349 | /* if the object is no longer bound, discard its backing storage */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3350 | if (i915_gem_object_is_purgeable(obj) && |
| 3351 | obj->gtt_space == NULL) |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 3352 | i915_gem_object_truncate(obj); |
| 3353 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3354 | args->retained = obj->madv != __I915_MADV_PURGED; |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3355 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3356 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3357 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3358 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3359 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3360 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3361 | } |
| 3362 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3363 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 3364 | size_t size) |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3365 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3366 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3367 | struct drm_i915_gem_object *obj; |
| 3368 | |
| 3369 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
| 3370 | if (obj == NULL) |
| 3371 | return NULL; |
| 3372 | |
| 3373 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
| 3374 | kfree(obj); |
| 3375 | return NULL; |
| 3376 | } |
| 3377 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3378 | i915_gem_info_add_obj(dev_priv, size); |
| 3379 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3380 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3381 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3382 | |
| 3383 | obj->agp_type = AGP_USER_MEMORY; |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 3384 | obj->base.driver_private = NULL; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3385 | obj->fence_reg = I915_FENCE_REG_NONE; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3386 | INIT_LIST_HEAD(&obj->mm_list); |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 3387 | INIT_LIST_HEAD(&obj->gtt_list); |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3388 | INIT_LIST_HEAD(&obj->ring_list); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 3389 | INIT_LIST_HEAD(&obj->exec_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3390 | INIT_LIST_HEAD(&obj->gpu_write_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3391 | obj->madv = I915_MADV_WILLNEED; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3392 | /* Avoid an unnecessary call to unbind on the first bind. */ |
| 3393 | obj->map_and_fenceable = true; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3394 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3395 | return obj; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3396 | } |
| 3397 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3398 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 3399 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3400 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3401 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3402 | return 0; |
| 3403 | } |
| 3404 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3405 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3406 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3407 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3408 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3409 | int ret; |
| 3410 | |
| 3411 | ret = i915_gem_object_unbind(obj); |
| 3412 | if (ret == -ERESTARTSYS) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3413 | list_move(&obj->mm_list, |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3414 | &dev_priv->mm.deferred_free_list); |
| 3415 | return; |
| 3416 | } |
| 3417 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3418 | if (obj->base.map_list.map) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3419 | i915_gem_free_mmap_offset(obj); |
| 3420 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3421 | drm_gem_object_release(&obj->base); |
| 3422 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3423 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3424 | kfree(obj->page_cpu_valid); |
| 3425 | kfree(obj->bit_17); |
| 3426 | kfree(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3427 | } |
| 3428 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3429 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3430 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3431 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
| 3432 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3433 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3434 | trace_i915_gem_object_destroy(obj); |
| 3435 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3436 | while (obj->pin_count > 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3437 | i915_gem_object_unpin(obj); |
| 3438 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3439 | if (obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3440 | i915_gem_detach_phys_object(dev, obj); |
| 3441 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3442 | i915_gem_free_object_tail(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3443 | } |
| 3444 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 3445 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3446 | i915_gem_idle(struct drm_device *dev) |
| 3447 | { |
| 3448 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3449 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3450 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3451 | mutex_lock(&dev->struct_mutex); |
| 3452 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 3453 | if (dev_priv->mm.suspended) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3454 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3455 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3456 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3457 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3458 | ret = i915_gpu_idle(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3459 | if (ret) { |
| 3460 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3461 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3462 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3463 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3464 | /* Under UMS, be paranoid and evict. */ |
| 3465 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { |
Chris Wilson | 5eac3ab | 2010-10-31 08:49:47 +0000 | [diff] [blame] | 3466 | ret = i915_gem_evict_inactive(dev, false); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3467 | if (ret) { |
| 3468 | mutex_unlock(&dev->struct_mutex); |
| 3469 | return ret; |
| 3470 | } |
| 3471 | } |
| 3472 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 3473 | i915_gem_reset_fences(dev); |
| 3474 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3475 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 3476 | * We need to replace this with a semaphore, or something. |
| 3477 | * And not confound mm.suspended! |
| 3478 | */ |
| 3479 | dev_priv->mm.suspended = 1; |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 3480 | del_timer_sync(&dev_priv->hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3481 | |
| 3482 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3483 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3484 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3485 | mutex_unlock(&dev->struct_mutex); |
| 3486 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3487 | /* Cancel the retire work handler, which should be idle now. */ |
| 3488 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 3489 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3490 | return 0; |
| 3491 | } |
| 3492 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3493 | int |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3494 | i915_gem_init_ringbuffer(struct drm_device *dev) |
| 3495 | { |
| 3496 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3497 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3498 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3499 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3500 | if (ret) |
Chris Wilson | b6913e4 | 2010-11-12 10:46:37 +0000 | [diff] [blame] | 3501 | return ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3502 | |
| 3503 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3504 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3505 | if (ret) |
| 3506 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3507 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3508 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3509 | if (HAS_BLT(dev)) { |
| 3510 | ret = intel_init_blt_ring_buffer(dev); |
| 3511 | if (ret) |
| 3512 | goto cleanup_bsd_ring; |
| 3513 | } |
| 3514 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 3515 | dev_priv->next_seqno = 1; |
| 3516 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3517 | return 0; |
| 3518 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3519 | cleanup_bsd_ring: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3520 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3521 | cleanup_render_ring: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3522 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3523 | return ret; |
| 3524 | } |
| 3525 | |
| 3526 | void |
| 3527 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 3528 | { |
| 3529 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3530 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3531 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
| 3532 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
| 3533 | intel_cleanup_ring_buffer(&dev_priv->blt_ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3534 | } |
| 3535 | |
| 3536 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3537 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 3538 | struct drm_file *file_priv) |
| 3539 | { |
| 3540 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3541 | int ret; |
| 3542 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3543 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3544 | return 0; |
| 3545 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3546 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3547 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3548 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3549 | } |
| 3550 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3551 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3552 | dev_priv->mm.suspended = 0; |
| 3553 | |
| 3554 | ret = i915_gem_init_ringbuffer(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 3555 | if (ret != 0) { |
| 3556 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3557 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 3558 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3559 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3560 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3561 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 3562 | BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list)); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3563 | BUG_ON(!list_empty(&dev_priv->blt_ring.active_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3564 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 3565 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3566 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 3567 | BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list)); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3568 | BUG_ON(!list_empty(&dev_priv->blt_ring.request_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3569 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3570 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 3571 | ret = drm_irq_install(dev); |
| 3572 | if (ret) |
| 3573 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3574 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3575 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 3576 | |
| 3577 | cleanup_ringbuffer: |
| 3578 | mutex_lock(&dev->struct_mutex); |
| 3579 | i915_gem_cleanup_ringbuffer(dev); |
| 3580 | dev_priv->mm.suspended = 1; |
| 3581 | mutex_unlock(&dev->struct_mutex); |
| 3582 | |
| 3583 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3584 | } |
| 3585 | |
| 3586 | int |
| 3587 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 3588 | struct drm_file *file_priv) |
| 3589 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3590 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3591 | return 0; |
| 3592 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3593 | drm_irq_uninstall(dev); |
Linus Torvalds | e6890f6 | 2009-09-08 17:09:24 -0700 | [diff] [blame] | 3594 | return i915_gem_idle(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3595 | } |
| 3596 | |
| 3597 | void |
| 3598 | i915_gem_lastclose(struct drm_device *dev) |
| 3599 | { |
| 3600 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3601 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 3602 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3603 | return; |
| 3604 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3605 | ret = i915_gem_idle(dev); |
| 3606 | if (ret) |
| 3607 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3608 | } |
| 3609 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 3610 | static void |
| 3611 | init_ring_lists(struct intel_ring_buffer *ring) |
| 3612 | { |
| 3613 | INIT_LIST_HEAD(&ring->active_list); |
| 3614 | INIT_LIST_HEAD(&ring->request_list); |
| 3615 | INIT_LIST_HEAD(&ring->gpu_write_list); |
| 3616 | } |
| 3617 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3618 | void |
| 3619 | i915_gem_load(struct drm_device *dev) |
| 3620 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3621 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3622 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3623 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3624 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3625 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
| 3626 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 3627 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 3628 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3629 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 3630 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 3631 | init_ring_lists(&dev_priv->render_ring); |
| 3632 | init_ring_lists(&dev_priv->bsd_ring); |
| 3633 | init_ring_lists(&dev_priv->blt_ring); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 3634 | for (i = 0; i < 16; i++) |
| 3635 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3636 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 3637 | i915_gem_retire_work_handler); |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3638 | init_completion(&dev_priv->error_completion); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3639 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 3640 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 3641 | if (IS_GEN3(dev)) { |
| 3642 | u32 tmp = I915_READ(MI_ARB_STATE); |
| 3643 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { |
| 3644 | /* arb state is a masked write, so set bit + bit in mask */ |
| 3645 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); |
| 3646 | I915_WRITE(MI_ARB_STATE, tmp); |
| 3647 | } |
| 3648 | } |
| 3649 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3650 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 3651 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3652 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3653 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3654 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3655 | dev_priv->num_fence_regs = 16; |
| 3656 | else |
| 3657 | dev_priv->num_fence_regs = 8; |
| 3658 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3659 | /* Initialize fence registers to zero */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3660 | switch (INTEL_INFO(dev)->gen) { |
| 3661 | case 6: |
| 3662 | for (i = 0; i < 16; i++) |
| 3663 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); |
| 3664 | break; |
| 3665 | case 5: |
| 3666 | case 4: |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3667 | for (i = 0; i < 16; i++) |
| 3668 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3669 | break; |
| 3670 | case 3: |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3671 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 3672 | for (i = 0; i < 8; i++) |
| 3673 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3674 | case 2: |
| 3675 | for (i = 0; i < 8; i++) |
| 3676 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); |
| 3677 | break; |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3678 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3679 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3680 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3681 | |
| 3682 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
| 3683 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
| 3684 | register_shrinker(&dev_priv->mm.inactive_shrinker); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3685 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3686 | |
| 3687 | /* |
| 3688 | * Create a physically contiguous memory object for this object |
| 3689 | * e.g. for cursor + overlay regs |
| 3690 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 3691 | static int i915_gem_init_phys_object(struct drm_device *dev, |
| 3692 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3693 | { |
| 3694 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3695 | struct drm_i915_gem_phys_object *phys_obj; |
| 3696 | int ret; |
| 3697 | |
| 3698 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 3699 | return 0; |
| 3700 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3701 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3702 | if (!phys_obj) |
| 3703 | return -ENOMEM; |
| 3704 | |
| 3705 | phys_obj->id = id; |
| 3706 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 3707 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3708 | if (!phys_obj->handle) { |
| 3709 | ret = -ENOMEM; |
| 3710 | goto kfree_obj; |
| 3711 | } |
| 3712 | #ifdef CONFIG_X86 |
| 3713 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 3714 | #endif |
| 3715 | |
| 3716 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 3717 | |
| 3718 | return 0; |
| 3719 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3720 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3721 | return ret; |
| 3722 | } |
| 3723 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 3724 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3725 | { |
| 3726 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3727 | struct drm_i915_gem_phys_object *phys_obj; |
| 3728 | |
| 3729 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 3730 | return; |
| 3731 | |
| 3732 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 3733 | if (phys_obj->cur_obj) { |
| 3734 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 3735 | } |
| 3736 | |
| 3737 | #ifdef CONFIG_X86 |
| 3738 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 3739 | #endif |
| 3740 | drm_pci_free(dev, phys_obj->handle); |
| 3741 | kfree(phys_obj); |
| 3742 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 3743 | } |
| 3744 | |
| 3745 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 3746 | { |
| 3747 | int i; |
| 3748 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 3749 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3750 | i915_gem_free_phys_object(dev, i); |
| 3751 | } |
| 3752 | |
| 3753 | void i915_gem_detach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3754 | struct drm_i915_gem_object *obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3755 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3756 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3757 | char *vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3758 | int i; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3759 | int page_count; |
| 3760 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3761 | if (!obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3762 | return; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3763 | vaddr = obj->phys_obj->handle->vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3764 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3765 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3766 | for (i = 0; i < page_count; i++) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3767 | struct page *page = read_cache_page_gfp(mapping, i, |
| 3768 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 3769 | if (!IS_ERR(page)) { |
| 3770 | char *dst = kmap_atomic(page); |
| 3771 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); |
| 3772 | kunmap_atomic(dst); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3773 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3774 | drm_clflush_pages(&page, 1); |
| 3775 | |
| 3776 | set_page_dirty(page); |
| 3777 | mark_page_accessed(page); |
| 3778 | page_cache_release(page); |
| 3779 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3780 | } |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 3781 | intel_gtt_chipset_flush(); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 3782 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3783 | obj->phys_obj->cur_obj = NULL; |
| 3784 | obj->phys_obj = NULL; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3785 | } |
| 3786 | |
| 3787 | int |
| 3788 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3789 | struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 3790 | int id, |
| 3791 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3792 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3793 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3794 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3795 | int ret = 0; |
| 3796 | int page_count; |
| 3797 | int i; |
| 3798 | |
| 3799 | if (id > I915_MAX_PHYS_OBJECT) |
| 3800 | return -EINVAL; |
| 3801 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3802 | if (obj->phys_obj) { |
| 3803 | if (obj->phys_obj->id == id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3804 | return 0; |
| 3805 | i915_gem_detach_phys_object(dev, obj); |
| 3806 | } |
| 3807 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3808 | /* create a new object */ |
| 3809 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 3810 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3811 | obj->base.size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3812 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3813 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
| 3814 | id, obj->base.size); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3815 | return ret; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3816 | } |
| 3817 | } |
| 3818 | |
| 3819 | /* bind to the object */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3820 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 3821 | obj->phys_obj->cur_obj = obj; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3822 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3823 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3824 | |
| 3825 | for (i = 0; i < page_count; i++) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3826 | struct page *page; |
| 3827 | char *dst, *src; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3828 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3829 | page = read_cache_page_gfp(mapping, i, |
| 3830 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 3831 | if (IS_ERR(page)) |
| 3832 | return PTR_ERR(page); |
| 3833 | |
Chris Wilson | ff75b9b | 2010-10-30 22:52:31 +0100 | [diff] [blame] | 3834 | src = kmap_atomic(page); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3835 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3836 | memcpy(dst, src, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 3837 | kunmap_atomic(src); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3838 | |
| 3839 | mark_page_accessed(page); |
| 3840 | page_cache_release(page); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3841 | } |
| 3842 | |
| 3843 | return 0; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3844 | } |
| 3845 | |
| 3846 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3847 | i915_gem_phys_pwrite(struct drm_device *dev, |
| 3848 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3849 | struct drm_i915_gem_pwrite *args, |
| 3850 | struct drm_file *file_priv) |
| 3851 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3852 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 3853 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3854 | |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 3855 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 3856 | unsigned long unwritten; |
| 3857 | |
| 3858 | /* The physical object once assigned is fixed for the lifetime |
| 3859 | * of the obj, so we can safely drop the lock and continue |
| 3860 | * to access vaddr. |
| 3861 | */ |
| 3862 | mutex_unlock(&dev->struct_mutex); |
| 3863 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 3864 | mutex_lock(&dev->struct_mutex); |
| 3865 | if (unwritten) |
| 3866 | return -EFAULT; |
| 3867 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3868 | |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 3869 | intel_gtt_chipset_flush(); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3870 | return 0; |
| 3871 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3872 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3873 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3874 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3875 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3876 | |
| 3877 | /* Clean up our request list when the client is going away, so that |
| 3878 | * later retire_requests won't dereference our soon-to-be-gone |
| 3879 | * file_priv. |
| 3880 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3881 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3882 | while (!list_empty(&file_priv->mm.request_list)) { |
| 3883 | struct drm_i915_gem_request *request; |
| 3884 | |
| 3885 | request = list_first_entry(&file_priv->mm.request_list, |
| 3886 | struct drm_i915_gem_request, |
| 3887 | client_list); |
| 3888 | list_del(&request->client_list); |
| 3889 | request->file_priv = NULL; |
| 3890 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3891 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3892 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3893 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3894 | static int |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 3895 | i915_gpu_is_active(struct drm_device *dev) |
| 3896 | { |
| 3897 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3898 | int lists_empty; |
| 3899 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 3900 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3901 | list_empty(&dev_priv->mm.active_list); |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 3902 | |
| 3903 | return !lists_empty; |
| 3904 | } |
| 3905 | |
| 3906 | static int |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3907 | i915_gem_inactive_shrink(struct shrinker *shrinker, |
| 3908 | int nr_to_scan, |
| 3909 | gfp_t gfp_mask) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3910 | { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3911 | struct drm_i915_private *dev_priv = |
| 3912 | container_of(shrinker, |
| 3913 | struct drm_i915_private, |
| 3914 | mm.inactive_shrinker); |
| 3915 | struct drm_device *dev = dev_priv->dev; |
| 3916 | struct drm_i915_gem_object *obj, *next; |
| 3917 | int cnt; |
| 3918 | |
| 3919 | if (!mutex_trylock(&dev->struct_mutex)) |
Chris Wilson | bbe2e11 | 2010-10-28 22:35:07 +0100 | [diff] [blame] | 3920 | return 0; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3921 | |
| 3922 | /* "fast-path" to count number of available objects */ |
| 3923 | if (nr_to_scan == 0) { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3924 | cnt = 0; |
| 3925 | list_for_each_entry(obj, |
| 3926 | &dev_priv->mm.inactive_list, |
| 3927 | mm_list) |
| 3928 | cnt++; |
| 3929 | mutex_unlock(&dev->struct_mutex); |
| 3930 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3931 | } |
| 3932 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 3933 | rescan: |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3934 | /* first scan for clean buffers */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3935 | i915_gem_retire_requests(dev); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3936 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3937 | list_for_each_entry_safe(obj, next, |
| 3938 | &dev_priv->mm.inactive_list, |
| 3939 | mm_list) { |
| 3940 | if (i915_gem_object_is_purgeable(obj)) { |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 3941 | if (i915_gem_object_unbind(obj) == 0 && |
| 3942 | --nr_to_scan == 0) |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3943 | break; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3944 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3945 | } |
| 3946 | |
| 3947 | /* second pass, evict/count anything still on the inactive list */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3948 | cnt = 0; |
| 3949 | list_for_each_entry_safe(obj, next, |
| 3950 | &dev_priv->mm.inactive_list, |
| 3951 | mm_list) { |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 3952 | if (nr_to_scan && |
| 3953 | i915_gem_object_unbind(obj) == 0) |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3954 | nr_to_scan--; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 3955 | else |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3956 | cnt++; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3957 | } |
| 3958 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3959 | if (nr_to_scan && i915_gpu_is_active(dev)) { |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 3960 | /* |
| 3961 | * We are desperate for pages, so as a last resort, wait |
| 3962 | * for the GPU to finish and discard whatever we can. |
| 3963 | * This has a dramatic impact to reduce the number of |
| 3964 | * OOM-killer events whilst running the GPU aggressively. |
| 3965 | */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3966 | if (i915_gpu_idle(dev) == 0) |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 3967 | goto rescan; |
| 3968 | } |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3969 | mutex_unlock(&dev->struct_mutex); |
| 3970 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3971 | } |