Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 34 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 35 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include <linux/pci.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 37 | |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 38 | struct change_domains { |
| 39 | uint32_t invalidate_domains; |
| 40 | uint32_t flush_domains; |
| 41 | uint32_t flush_rings; |
| 42 | }; |
| 43 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 44 | static int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 45 | struct intel_ring_buffer *pipelined); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 46 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
| 47 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
| 48 | static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 49 | bool write); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 50 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 51 | uint64_t offset, |
| 52 | uint64_t size); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 53 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj); |
| 54 | static int i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 55 | bool interruptible); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 56 | static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 57 | unsigned alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 58 | bool map_and_fenceable); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 59 | static void i915_gem_clear_fence_reg(struct drm_i915_gem_object *obj); |
| 60 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
| 61 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 62 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 63 | struct drm_file *file); |
| 64 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 65 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 66 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
| 67 | int nr_to_scan, |
| 68 | gfp_t gfp_mask); |
| 69 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 70 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 71 | /* some bookkeeping */ |
| 72 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 73 | size_t size) |
| 74 | { |
| 75 | dev_priv->mm.object_count++; |
| 76 | dev_priv->mm.object_memory += size; |
| 77 | } |
| 78 | |
| 79 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 80 | size_t size) |
| 81 | { |
| 82 | dev_priv->mm.object_count--; |
| 83 | dev_priv->mm.object_memory -= size; |
| 84 | } |
| 85 | |
| 86 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 87 | struct drm_i915_gem_object *obj) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 88 | { |
| 89 | dev_priv->mm.gtt_count++; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 90 | dev_priv->mm.gtt_memory += obj->gtt_space->size; |
| 91 | if (obj->gtt_offset < dev_priv->mm.gtt_mappable_end) { |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 92 | dev_priv->mm.mappable_gtt_used += |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 93 | min_t(size_t, obj->gtt_space->size, |
| 94 | dev_priv->mm.gtt_mappable_end - obj->gtt_offset); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 95 | } |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 96 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 97 | } |
| 98 | |
| 99 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 100 | struct drm_i915_gem_object *obj) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 101 | { |
| 102 | dev_priv->mm.gtt_count--; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 103 | dev_priv->mm.gtt_memory -= obj->gtt_space->size; |
| 104 | if (obj->gtt_offset < dev_priv->mm.gtt_mappable_end) { |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 105 | dev_priv->mm.mappable_gtt_used -= |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 106 | min_t(size_t, obj->gtt_space->size, |
| 107 | dev_priv->mm.gtt_mappable_end - obj->gtt_offset); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 108 | } |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 109 | list_del_init(&obj->gtt_list); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 110 | } |
| 111 | |
| 112 | /** |
| 113 | * Update the mappable working set counters. Call _only_ when there is a change |
| 114 | * in one of (pin|fault)_mappable and update *_mappable _before_ calling. |
| 115 | * @mappable: new state the changed mappable flag (either pin_ or fault_). |
| 116 | */ |
| 117 | static void |
| 118 | i915_gem_info_update_mappable(struct drm_i915_private *dev_priv, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 119 | struct drm_i915_gem_object *obj, |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 120 | bool mappable) |
| 121 | { |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 122 | if (mappable) { |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 123 | if (obj->pin_mappable && obj->fault_mappable) |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 124 | /* Combined state was already mappable. */ |
| 125 | return; |
| 126 | dev_priv->mm.gtt_mappable_count++; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 127 | dev_priv->mm.gtt_mappable_memory += obj->gtt_space->size; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 128 | } else { |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 129 | if (obj->pin_mappable || obj->fault_mappable) |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 130 | /* Combined state still mappable. */ |
| 131 | return; |
| 132 | dev_priv->mm.gtt_mappable_count--; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 133 | dev_priv->mm.gtt_mappable_memory -= obj->gtt_space->size; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 134 | } |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 135 | } |
| 136 | |
| 137 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 138 | struct drm_i915_gem_object *obj, |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 139 | bool mappable) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 140 | { |
| 141 | dev_priv->mm.pin_count++; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 142 | dev_priv->mm.pin_memory += obj->gtt_space->size; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 143 | if (mappable) { |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 144 | obj->pin_mappable = true; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 145 | i915_gem_info_update_mappable(dev_priv, obj, true); |
| 146 | } |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 147 | } |
| 148 | |
| 149 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 150 | struct drm_i915_gem_object *obj) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 151 | { |
| 152 | dev_priv->mm.pin_count--; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 153 | dev_priv->mm.pin_memory -= obj->gtt_space->size; |
| 154 | if (obj->pin_mappable) { |
| 155 | obj->pin_mappable = false; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 156 | i915_gem_info_update_mappable(dev_priv, obj, false); |
| 157 | } |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 158 | } |
| 159 | |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 160 | int |
| 161 | i915_gem_check_is_wedged(struct drm_device *dev) |
| 162 | { |
| 163 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 164 | struct completion *x = &dev_priv->error_completion; |
| 165 | unsigned long flags; |
| 166 | int ret; |
| 167 | |
| 168 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 169 | return 0; |
| 170 | |
| 171 | ret = wait_for_completion_interruptible(x); |
| 172 | if (ret) |
| 173 | return ret; |
| 174 | |
| 175 | /* Success, we reset the GPU! */ |
| 176 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 177 | return 0; |
| 178 | |
| 179 | /* GPU is hung, bump the completion count to account for |
| 180 | * the token we just consumed so that we never hit zero and |
| 181 | * end up waiting upon a subsequent completion event that |
| 182 | * will never happen. |
| 183 | */ |
| 184 | spin_lock_irqsave(&x->wait.lock, flags); |
| 185 | x->done++; |
| 186 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 187 | return -EIO; |
| 188 | } |
| 189 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 190 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
| 191 | { |
| 192 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 193 | int ret; |
| 194 | |
| 195 | ret = i915_gem_check_is_wedged(dev); |
| 196 | if (ret) |
| 197 | return ret; |
| 198 | |
| 199 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 200 | if (ret) |
| 201 | return ret; |
| 202 | |
| 203 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 204 | mutex_unlock(&dev->struct_mutex); |
| 205 | return -EAGAIN; |
| 206 | } |
| 207 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 208 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 209 | return 0; |
| 210 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 211 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 212 | static inline bool |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 213 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 214 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 215 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 216 | } |
| 217 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 218 | int i915_gem_do_init(struct drm_device *dev, |
| 219 | unsigned long start, |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 220 | unsigned long mappable_end, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 221 | unsigned long end) |
| 222 | { |
| 223 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 224 | |
| 225 | if (start >= end || |
| 226 | (start & (PAGE_SIZE - 1)) != 0 || |
| 227 | (end & (PAGE_SIZE - 1)) != 0) { |
| 228 | return -EINVAL; |
| 229 | } |
| 230 | |
| 231 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
| 232 | end - start); |
| 233 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 234 | dev_priv->mm.gtt_total = end - start; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 235 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 236 | dev_priv->mm.gtt_mappable_end = mappable_end; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 237 | |
| 238 | return 0; |
| 239 | } |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 240 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 241 | int |
| 242 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 243 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 244 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 245 | struct drm_i915_gem_init *args = data; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 246 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 247 | |
| 248 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 249 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 250 | mutex_unlock(&dev->struct_mutex); |
| 251 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 252 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 253 | } |
| 254 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 255 | int |
| 256 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 257 | struct drm_file *file) |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 258 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 259 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 260 | struct drm_i915_gem_get_aperture *args = data; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 261 | |
| 262 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 263 | return -ENODEV; |
| 264 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 265 | mutex_lock(&dev->struct_mutex); |
| 266 | args->aper_size = dev_priv->mm.gtt_total; |
| 267 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; |
| 268 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 269 | |
| 270 | return 0; |
| 271 | } |
| 272 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 273 | |
| 274 | /** |
| 275 | * Creates a new mm object and returns a handle to it. |
| 276 | */ |
| 277 | int |
| 278 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 279 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 280 | { |
| 281 | struct drm_i915_gem_create *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 282 | struct drm_i915_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 283 | int ret; |
| 284 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 285 | |
| 286 | args->size = roundup(args->size, PAGE_SIZE); |
| 287 | |
| 288 | /* Allocate the new object */ |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 289 | obj = i915_gem_alloc_object(dev, args->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 290 | if (obj == NULL) |
| 291 | return -ENOMEM; |
| 292 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 293 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 294 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 295 | drm_gem_object_release(&obj->base); |
| 296 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 297 | kfree(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 298 | return ret; |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 299 | } |
| 300 | |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 301 | /* drop reference from allocate - handle holds it now */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 302 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 303 | trace_i915_gem_object_create(obj); |
| 304 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 305 | args->handle = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 306 | return 0; |
| 307 | } |
| 308 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 309 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 310 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 311 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 312 | |
| 313 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 314 | obj->tiling_mode != I915_TILING_NONE; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 315 | } |
| 316 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 317 | static inline void |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 318 | slow_shmem_copy(struct page *dst_page, |
| 319 | int dst_offset, |
| 320 | struct page *src_page, |
| 321 | int src_offset, |
| 322 | int length) |
| 323 | { |
| 324 | char *dst_vaddr, *src_vaddr; |
| 325 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 326 | dst_vaddr = kmap(dst_page); |
| 327 | src_vaddr = kmap(src_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 328 | |
| 329 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); |
| 330 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 331 | kunmap(src_page); |
| 332 | kunmap(dst_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 333 | } |
| 334 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 335 | static inline void |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 336 | slow_shmem_bit17_copy(struct page *gpu_page, |
| 337 | int gpu_offset, |
| 338 | struct page *cpu_page, |
| 339 | int cpu_offset, |
| 340 | int length, |
| 341 | int is_read) |
| 342 | { |
| 343 | char *gpu_vaddr, *cpu_vaddr; |
| 344 | |
| 345 | /* Use the unswizzled path if this page isn't affected. */ |
| 346 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { |
| 347 | if (is_read) |
| 348 | return slow_shmem_copy(cpu_page, cpu_offset, |
| 349 | gpu_page, gpu_offset, length); |
| 350 | else |
| 351 | return slow_shmem_copy(gpu_page, gpu_offset, |
| 352 | cpu_page, cpu_offset, length); |
| 353 | } |
| 354 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 355 | gpu_vaddr = kmap(gpu_page); |
| 356 | cpu_vaddr = kmap(cpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 357 | |
| 358 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's |
| 359 | * XORing with the other bits (A9 for Y, A9 and A10 for X) |
| 360 | */ |
| 361 | while (length > 0) { |
| 362 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 363 | int this_length = min(cacheline_end - gpu_offset, length); |
| 364 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 365 | |
| 366 | if (is_read) { |
| 367 | memcpy(cpu_vaddr + cpu_offset, |
| 368 | gpu_vaddr + swizzled_gpu_offset, |
| 369 | this_length); |
| 370 | } else { |
| 371 | memcpy(gpu_vaddr + swizzled_gpu_offset, |
| 372 | cpu_vaddr + cpu_offset, |
| 373 | this_length); |
| 374 | } |
| 375 | cpu_offset += this_length; |
| 376 | gpu_offset += this_length; |
| 377 | length -= this_length; |
| 378 | } |
| 379 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 380 | kunmap(cpu_page); |
| 381 | kunmap(gpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 382 | } |
| 383 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 384 | /** |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 385 | * This is the fast shmem pread path, which attempts to copy_from_user directly |
| 386 | * from the backing pages of the object to the user's address space. On a |
| 387 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). |
| 388 | */ |
| 389 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 390 | i915_gem_shmem_pread_fast(struct drm_device *dev, |
| 391 | struct drm_i915_gem_object *obj, |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 392 | struct drm_i915_gem_pread *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 393 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 394 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 395 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 396 | ssize_t remain; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 397 | loff_t offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 398 | char __user *user_data; |
| 399 | int page_offset, page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 400 | |
| 401 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 402 | remain = args->size; |
| 403 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 404 | offset = args->offset; |
| 405 | |
| 406 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 407 | struct page *page; |
| 408 | char *vaddr; |
| 409 | int ret; |
| 410 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 411 | /* Operation in this page |
| 412 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 413 | * page_offset = offset within page |
| 414 | * page_length = bytes to copy for this page |
| 415 | */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 416 | page_offset = offset & (PAGE_SIZE-1); |
| 417 | page_length = remain; |
| 418 | if ((page_offset + remain) > PAGE_SIZE) |
| 419 | page_length = PAGE_SIZE - page_offset; |
| 420 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 421 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
| 422 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 423 | if (IS_ERR(page)) |
| 424 | return PTR_ERR(page); |
| 425 | |
| 426 | vaddr = kmap_atomic(page); |
| 427 | ret = __copy_to_user_inatomic(user_data, |
| 428 | vaddr + page_offset, |
| 429 | page_length); |
| 430 | kunmap_atomic(vaddr); |
| 431 | |
| 432 | mark_page_accessed(page); |
| 433 | page_cache_release(page); |
| 434 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 435 | return -EFAULT; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 436 | |
| 437 | remain -= page_length; |
| 438 | user_data += page_length; |
| 439 | offset += page_length; |
| 440 | } |
| 441 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 442 | return 0; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 443 | } |
| 444 | |
| 445 | /** |
| 446 | * This is the fallback shmem pread path, which allocates temporary storage |
| 447 | * in kernel space to copy_to_user into outside of the struct_mutex, so we |
| 448 | * can copy out of the object's backing pages while holding the struct mutex |
| 449 | * and not take page faults. |
| 450 | */ |
| 451 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 452 | i915_gem_shmem_pread_slow(struct drm_device *dev, |
| 453 | struct drm_i915_gem_object *obj, |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 454 | struct drm_i915_gem_pread *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 455 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 456 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 457 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 458 | struct mm_struct *mm = current->mm; |
| 459 | struct page **user_pages; |
| 460 | ssize_t remain; |
| 461 | loff_t offset, pinned_pages, i; |
| 462 | loff_t first_data_page, last_data_page, num_pages; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 463 | int shmem_page_offset; |
| 464 | int data_page_index, data_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 465 | int page_length; |
| 466 | int ret; |
| 467 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 468 | int do_bit17_swizzling; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 469 | |
| 470 | remain = args->size; |
| 471 | |
| 472 | /* Pin the user pages containing the data. We can't fault while |
| 473 | * holding the struct mutex, yet we want to hold it while |
| 474 | * dereferencing the user data. |
| 475 | */ |
| 476 | first_data_page = data_ptr / PAGE_SIZE; |
| 477 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 478 | num_pages = last_data_page - first_data_page + 1; |
| 479 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 480 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 481 | if (user_pages == NULL) |
| 482 | return -ENOMEM; |
| 483 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 484 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 485 | down_read(&mm->mmap_sem); |
| 486 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
Eric Anholt | e5e9ecd | 2009-04-07 16:01:22 -0700 | [diff] [blame] | 487 | num_pages, 1, 0, user_pages, NULL); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 488 | up_read(&mm->mmap_sem); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 489 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 490 | if (pinned_pages < num_pages) { |
| 491 | ret = -EFAULT; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 492 | goto out; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 493 | } |
| 494 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 495 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
| 496 | args->offset, |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 497 | args->size); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 498 | if (ret) |
| 499 | goto out; |
| 500 | |
| 501 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 502 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 503 | offset = args->offset; |
| 504 | |
| 505 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 506 | struct page *page; |
| 507 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 508 | /* Operation in this page |
| 509 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 510 | * shmem_page_offset = offset within page in shmem file |
| 511 | * data_page_index = page number in get_user_pages return |
| 512 | * data_page_offset = offset with data_page_index page. |
| 513 | * page_length = bytes to copy for this page |
| 514 | */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 515 | shmem_page_offset = offset & ~PAGE_MASK; |
| 516 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 517 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 518 | |
| 519 | page_length = remain; |
| 520 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 521 | page_length = PAGE_SIZE - shmem_page_offset; |
| 522 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 523 | page_length = PAGE_SIZE - data_page_offset; |
| 524 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 525 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
| 526 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 527 | if (IS_ERR(page)) |
| 528 | return PTR_ERR(page); |
| 529 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 530 | if (do_bit17_swizzling) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 531 | slow_shmem_bit17_copy(page, |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 532 | shmem_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 533 | user_pages[data_page_index], |
| 534 | data_page_offset, |
| 535 | page_length, |
| 536 | 1); |
| 537 | } else { |
| 538 | slow_shmem_copy(user_pages[data_page_index], |
| 539 | data_page_offset, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 540 | page, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 541 | shmem_page_offset, |
| 542 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 543 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 544 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 545 | mark_page_accessed(page); |
| 546 | page_cache_release(page); |
| 547 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 548 | remain -= page_length; |
| 549 | data_ptr += page_length; |
| 550 | offset += page_length; |
| 551 | } |
| 552 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 553 | out: |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 554 | for (i = 0; i < pinned_pages; i++) { |
| 555 | SetPageDirty(user_pages[i]); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 556 | mark_page_accessed(user_pages[i]); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 557 | page_cache_release(user_pages[i]); |
| 558 | } |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 559 | drm_free_large(user_pages); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 560 | |
| 561 | return ret; |
| 562 | } |
| 563 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 564 | /** |
| 565 | * Reads data from the object referenced by handle. |
| 566 | * |
| 567 | * On error, the contents of *data are undefined. |
| 568 | */ |
| 569 | int |
| 570 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 571 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 572 | { |
| 573 | struct drm_i915_gem_pread *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 574 | struct drm_i915_gem_object *obj; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 575 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 576 | |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 577 | if (args->size == 0) |
| 578 | return 0; |
| 579 | |
| 580 | if (!access_ok(VERIFY_WRITE, |
| 581 | (char __user *)(uintptr_t)args->data_ptr, |
| 582 | args->size)) |
| 583 | return -EFAULT; |
| 584 | |
| 585 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, |
| 586 | args->size); |
| 587 | if (ret) |
| 588 | return -EFAULT; |
| 589 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 590 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 591 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 592 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 593 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 594 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 595 | if (obj == NULL) { |
| 596 | ret = -ENOENT; |
| 597 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 598 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 599 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 600 | /* Bounds check source. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 601 | if (args->offset > obj->base.size || |
| 602 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 603 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 604 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 605 | } |
| 606 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 607 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
| 608 | args->offset, |
| 609 | args->size); |
| 610 | if (ret) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 611 | goto out; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 612 | |
| 613 | ret = -EFAULT; |
| 614 | if (!i915_gem_object_needs_bit17_swizzle(obj)) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 615 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 616 | if (ret == -EFAULT) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 617 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 618 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 619 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 620 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 621 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 622 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 623 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 624 | } |
| 625 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 626 | /* This is the fast write path which cannot handle |
| 627 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 628 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 629 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 630 | static inline int |
| 631 | fast_user_write(struct io_mapping *mapping, |
| 632 | loff_t page_base, int page_offset, |
| 633 | char __user *user_data, |
| 634 | int length) |
| 635 | { |
| 636 | char *vaddr_atomic; |
| 637 | unsigned long unwritten; |
| 638 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 639 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 640 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
| 641 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 642 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 643 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 644 | } |
| 645 | |
| 646 | /* Here's the write path which can sleep for |
| 647 | * page faults |
| 648 | */ |
| 649 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 650 | static inline void |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 651 | slow_kernel_write(struct io_mapping *mapping, |
| 652 | loff_t gtt_base, int gtt_offset, |
| 653 | struct page *user_page, int user_offset, |
| 654 | int length) |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 655 | { |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 656 | char __iomem *dst_vaddr; |
| 657 | char *src_vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 658 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 659 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
| 660 | src_vaddr = kmap(user_page); |
| 661 | |
| 662 | memcpy_toio(dst_vaddr + gtt_offset, |
| 663 | src_vaddr + user_offset, |
| 664 | length); |
| 665 | |
| 666 | kunmap(user_page); |
| 667 | io_mapping_unmap(dst_vaddr); |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 668 | } |
| 669 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 670 | /** |
| 671 | * This is the fast pwrite path, where we copy the data directly from the |
| 672 | * user into the GTT, uncached. |
| 673 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 674 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 675 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 676 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 677 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 678 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 679 | { |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 680 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 681 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 682 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 683 | char __user *user_data; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 684 | int page_offset, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 685 | |
| 686 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 687 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 688 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 689 | offset = obj->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 690 | |
| 691 | while (remain > 0) { |
| 692 | /* Operation in this page |
| 693 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 694 | * page_base = page offset within aperture |
| 695 | * page_offset = offset within page |
| 696 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 697 | */ |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 698 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 699 | page_offset = offset & (PAGE_SIZE-1); |
| 700 | page_length = remain; |
| 701 | if ((page_offset + remain) > PAGE_SIZE) |
| 702 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 703 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 704 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 705 | * source page isn't available. Return the error and we'll |
| 706 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 707 | */ |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 708 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
| 709 | page_offset, user_data, page_length)) |
| 710 | |
| 711 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 712 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 713 | remain -= page_length; |
| 714 | user_data += page_length; |
| 715 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 716 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 717 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 718 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 719 | } |
| 720 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 721 | /** |
| 722 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin |
| 723 | * the memory and maps it using kmap_atomic for copying. |
| 724 | * |
| 725 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU |
| 726 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). |
| 727 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 728 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 729 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, |
| 730 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 731 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 732 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 733 | { |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 734 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 735 | ssize_t remain; |
| 736 | loff_t gtt_page_base, offset; |
| 737 | loff_t first_data_page, last_data_page, num_pages; |
| 738 | loff_t pinned_pages, i; |
| 739 | struct page **user_pages; |
| 740 | struct mm_struct *mm = current->mm; |
| 741 | int gtt_page_offset, data_page_offset, data_page_index, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 742 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 743 | uint64_t data_ptr = args->data_ptr; |
| 744 | |
| 745 | remain = args->size; |
| 746 | |
| 747 | /* Pin the user pages containing the data. We can't fault while |
| 748 | * holding the struct mutex, and all of the pwrite implementations |
| 749 | * want to hold it while dereferencing the user data. |
| 750 | */ |
| 751 | first_data_page = data_ptr / PAGE_SIZE; |
| 752 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 753 | num_pages = last_data_page - first_data_page + 1; |
| 754 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 755 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 756 | if (user_pages == NULL) |
| 757 | return -ENOMEM; |
| 758 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 759 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 760 | down_read(&mm->mmap_sem); |
| 761 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 762 | num_pages, 0, 0, user_pages, NULL); |
| 763 | up_read(&mm->mmap_sem); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 764 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 765 | if (pinned_pages < num_pages) { |
| 766 | ret = -EFAULT; |
| 767 | goto out_unpin_pages; |
| 768 | } |
| 769 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 770 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 771 | if (ret) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 772 | goto out_unpin_pages; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 773 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 774 | offset = obj->gtt_offset + args->offset; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 775 | |
| 776 | while (remain > 0) { |
| 777 | /* Operation in this page |
| 778 | * |
| 779 | * gtt_page_base = page offset within aperture |
| 780 | * gtt_page_offset = offset within page in aperture |
| 781 | * data_page_index = page number in get_user_pages return |
| 782 | * data_page_offset = offset with data_page_index page. |
| 783 | * page_length = bytes to copy for this page |
| 784 | */ |
| 785 | gtt_page_base = offset & PAGE_MASK; |
| 786 | gtt_page_offset = offset & ~PAGE_MASK; |
| 787 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 788 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 789 | |
| 790 | page_length = remain; |
| 791 | if ((gtt_page_offset + page_length) > PAGE_SIZE) |
| 792 | page_length = PAGE_SIZE - gtt_page_offset; |
| 793 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 794 | page_length = PAGE_SIZE - data_page_offset; |
| 795 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 796 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
| 797 | gtt_page_base, gtt_page_offset, |
| 798 | user_pages[data_page_index], |
| 799 | data_page_offset, |
| 800 | page_length); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 801 | |
| 802 | remain -= page_length; |
| 803 | offset += page_length; |
| 804 | data_ptr += page_length; |
| 805 | } |
| 806 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 807 | out_unpin_pages: |
| 808 | for (i = 0; i < pinned_pages; i++) |
| 809 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 810 | drm_free_large(user_pages); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 811 | |
| 812 | return ret; |
| 813 | } |
| 814 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 815 | /** |
| 816 | * This is the fast shmem pwrite path, which attempts to directly |
| 817 | * copy_from_user into the kmapped pages backing the object. |
| 818 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 819 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 820 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, |
| 821 | struct drm_i915_gem_object *obj, |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 822 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 823 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 824 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 825 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 826 | ssize_t remain; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 827 | loff_t offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 828 | char __user *user_data; |
| 829 | int page_offset, page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 830 | |
| 831 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 832 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 833 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 834 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 835 | obj->dirty = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 836 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 837 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 838 | struct page *page; |
| 839 | char *vaddr; |
| 840 | int ret; |
| 841 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 842 | /* Operation in this page |
| 843 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 844 | * page_offset = offset within page |
| 845 | * page_length = bytes to copy for this page |
| 846 | */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 847 | page_offset = offset & (PAGE_SIZE-1); |
| 848 | page_length = remain; |
| 849 | if ((page_offset + remain) > PAGE_SIZE) |
| 850 | page_length = PAGE_SIZE - page_offset; |
| 851 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 852 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
| 853 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 854 | if (IS_ERR(page)) |
| 855 | return PTR_ERR(page); |
| 856 | |
| 857 | vaddr = kmap_atomic(page, KM_USER0); |
| 858 | ret = __copy_from_user_inatomic(vaddr + page_offset, |
| 859 | user_data, |
| 860 | page_length); |
| 861 | kunmap_atomic(vaddr, KM_USER0); |
| 862 | |
| 863 | set_page_dirty(page); |
| 864 | mark_page_accessed(page); |
| 865 | page_cache_release(page); |
| 866 | |
| 867 | /* If we get a fault while copying data, then (presumably) our |
| 868 | * source page isn't available. Return the error and we'll |
| 869 | * retry in the slow path. |
| 870 | */ |
| 871 | if (ret) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 872 | return -EFAULT; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 873 | |
| 874 | remain -= page_length; |
| 875 | user_data += page_length; |
| 876 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 877 | } |
| 878 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 879 | return 0; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 880 | } |
| 881 | |
| 882 | /** |
| 883 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin |
| 884 | * the memory and maps it using kmap_atomic for copying. |
| 885 | * |
| 886 | * This avoids taking mmap_sem for faulting on the user's address while the |
| 887 | * struct_mutex is held. |
| 888 | */ |
| 889 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 890 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, |
| 891 | struct drm_i915_gem_object *obj, |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 892 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 893 | struct drm_file *file) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 894 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 895 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 896 | struct mm_struct *mm = current->mm; |
| 897 | struct page **user_pages; |
| 898 | ssize_t remain; |
| 899 | loff_t offset, pinned_pages, i; |
| 900 | loff_t first_data_page, last_data_page, num_pages; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 901 | int shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 902 | int data_page_index, data_page_offset; |
| 903 | int page_length; |
| 904 | int ret; |
| 905 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 906 | int do_bit17_swizzling; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 907 | |
| 908 | remain = args->size; |
| 909 | |
| 910 | /* Pin the user pages containing the data. We can't fault while |
| 911 | * holding the struct mutex, and all of the pwrite implementations |
| 912 | * want to hold it while dereferencing the user data. |
| 913 | */ |
| 914 | first_data_page = data_ptr / PAGE_SIZE; |
| 915 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 916 | num_pages = last_data_page - first_data_page + 1; |
| 917 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 918 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 919 | if (user_pages == NULL) |
| 920 | return -ENOMEM; |
| 921 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 922 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 923 | down_read(&mm->mmap_sem); |
| 924 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 925 | num_pages, 0, 0, user_pages, NULL); |
| 926 | up_read(&mm->mmap_sem); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 927 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 928 | if (pinned_pages < num_pages) { |
| 929 | ret = -EFAULT; |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 930 | goto out; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 931 | } |
| 932 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 933 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 934 | if (ret) |
| 935 | goto out; |
| 936 | |
| 937 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 938 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 939 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 940 | obj->dirty = 1; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 941 | |
| 942 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 943 | struct page *page; |
| 944 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 945 | /* Operation in this page |
| 946 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 947 | * shmem_page_offset = offset within page in shmem file |
| 948 | * data_page_index = page number in get_user_pages return |
| 949 | * data_page_offset = offset with data_page_index page. |
| 950 | * page_length = bytes to copy for this page |
| 951 | */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 952 | shmem_page_offset = offset & ~PAGE_MASK; |
| 953 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 954 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 955 | |
| 956 | page_length = remain; |
| 957 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 958 | page_length = PAGE_SIZE - shmem_page_offset; |
| 959 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 960 | page_length = PAGE_SIZE - data_page_offset; |
| 961 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 962 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
| 963 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 964 | if (IS_ERR(page)) { |
| 965 | ret = PTR_ERR(page); |
| 966 | goto out; |
| 967 | } |
| 968 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 969 | if (do_bit17_swizzling) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 970 | slow_shmem_bit17_copy(page, |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 971 | shmem_page_offset, |
| 972 | user_pages[data_page_index], |
| 973 | data_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 974 | page_length, |
| 975 | 0); |
| 976 | } else { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 977 | slow_shmem_copy(page, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 978 | shmem_page_offset, |
| 979 | user_pages[data_page_index], |
| 980 | data_page_offset, |
| 981 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 982 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 983 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 984 | set_page_dirty(page); |
| 985 | mark_page_accessed(page); |
| 986 | page_cache_release(page); |
| 987 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 988 | remain -= page_length; |
| 989 | data_ptr += page_length; |
| 990 | offset += page_length; |
| 991 | } |
| 992 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 993 | out: |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 994 | for (i = 0; i < pinned_pages; i++) |
| 995 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 996 | drm_free_large(user_pages); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 997 | |
| 998 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 999 | } |
| 1000 | |
| 1001 | /** |
| 1002 | * Writes data to the object referenced by handle. |
| 1003 | * |
| 1004 | * On error, the contents of the buffer that were to be modified are undefined. |
| 1005 | */ |
| 1006 | int |
| 1007 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1008 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1009 | { |
| 1010 | struct drm_i915_gem_pwrite *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1011 | struct drm_i915_gem_object *obj; |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 1012 | int ret; |
| 1013 | |
| 1014 | if (args->size == 0) |
| 1015 | return 0; |
| 1016 | |
| 1017 | if (!access_ok(VERIFY_READ, |
| 1018 | (char __user *)(uintptr_t)args->data_ptr, |
| 1019 | args->size)) |
| 1020 | return -EFAULT; |
| 1021 | |
| 1022 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, |
| 1023 | args->size); |
| 1024 | if (ret) |
| 1025 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1026 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1027 | ret = i915_mutex_lock_interruptible(dev); |
| 1028 | if (ret) |
| 1029 | return ret; |
| 1030 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1031 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1032 | if (obj == NULL) { |
| 1033 | ret = -ENOENT; |
| 1034 | goto unlock; |
| 1035 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1036 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 1037 | /* Bounds check destination. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1038 | if (args->offset > obj->base.size || |
| 1039 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1040 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1041 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1042 | } |
| 1043 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1044 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 1045 | * it would end up going through the fenced access, and we'll get |
| 1046 | * different detiling behavior between reading and writing. |
| 1047 | * pread/pwrite currently are reading and writing from the CPU |
| 1048 | * perspective, requiring manual detiling by the client. |
| 1049 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1050 | if (obj->phys_obj) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1051 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1052 | else if (obj->tiling_mode == I915_TILING_NONE && |
| 1053 | obj->gtt_space && |
| 1054 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1055 | ret = i915_gem_object_pin(obj, 0, true); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1056 | if (ret) |
| 1057 | goto out; |
| 1058 | |
| 1059 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 1060 | if (ret) |
| 1061 | goto out_unpin; |
| 1062 | |
| 1063 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
| 1064 | if (ret == -EFAULT) |
| 1065 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); |
| 1066 | |
| 1067 | out_unpin: |
| 1068 | i915_gem_object_unpin(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1069 | } else { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1070 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 1071 | if (ret) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1072 | goto out; |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1073 | |
| 1074 | ret = -EFAULT; |
| 1075 | if (!i915_gem_object_needs_bit17_swizzle(obj)) |
| 1076 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); |
| 1077 | if (ret == -EFAULT) |
| 1078 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1079 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1080 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1081 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1082 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1083 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1084 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1085 | return ret; |
| 1086 | } |
| 1087 | |
| 1088 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1089 | * Called when user space prepares to use an object with the CPU, either |
| 1090 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1091 | */ |
| 1092 | int |
| 1093 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1094 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1095 | { |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1096 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1097 | struct drm_i915_gem_set_domain *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1098 | struct drm_i915_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1099 | uint32_t read_domains = args->read_domains; |
| 1100 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1101 | int ret; |
| 1102 | |
| 1103 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1104 | return -ENODEV; |
| 1105 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1106 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1107 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1108 | return -EINVAL; |
| 1109 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1110 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1111 | return -EINVAL; |
| 1112 | |
| 1113 | /* Having something in the write domain implies it's in the read |
| 1114 | * domain, and only that read domain. Enforce that in the request. |
| 1115 | */ |
| 1116 | if (write_domain != 0 && read_domains != write_domain) |
| 1117 | return -EINVAL; |
| 1118 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1119 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1120 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1121 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1122 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1123 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1124 | if (obj == NULL) { |
| 1125 | ret = -ENOENT; |
| 1126 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1127 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1128 | |
| 1129 | intel_mark_busy(dev, obj); |
| 1130 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1131 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1132 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1133 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1134 | /* Update the LRU on the fence for the CPU access that's |
| 1135 | * about to occur. |
| 1136 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1137 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1138 | struct drm_i915_fence_reg *reg = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1139 | &dev_priv->fence_regs[obj->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1140 | list_move_tail(®->lru_list, |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1141 | &dev_priv->mm.fence_list); |
| 1142 | } |
| 1143 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1144 | /* Silently promote "you're not bound, there was nothing to do" |
| 1145 | * to success, since the client was just asking us to |
| 1146 | * make sure everything was done. |
| 1147 | */ |
| 1148 | if (ret == -EINVAL) |
| 1149 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1150 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1151 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1152 | } |
| 1153 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1154 | /* Maintain LRU order of "inactive" objects */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1155 | if (ret == 0 && i915_gem_object_is_inactive(obj)) |
| 1156 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1157 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1158 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1159 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1160 | mutex_unlock(&dev->struct_mutex); |
| 1161 | return ret; |
| 1162 | } |
| 1163 | |
| 1164 | /** |
| 1165 | * Called when user space has done writes to this buffer |
| 1166 | */ |
| 1167 | int |
| 1168 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1169 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1170 | { |
| 1171 | struct drm_i915_gem_sw_finish *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1172 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1173 | int ret = 0; |
| 1174 | |
| 1175 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1176 | return -ENODEV; |
| 1177 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1178 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1179 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1180 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1181 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1182 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1183 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1184 | ret = -ENOENT; |
| 1185 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1186 | } |
| 1187 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1188 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1189 | if (obj->pin_count) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1190 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1191 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1192 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1193 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1194 | mutex_unlock(&dev->struct_mutex); |
| 1195 | return ret; |
| 1196 | } |
| 1197 | |
| 1198 | /** |
| 1199 | * Maps the contents of an object, returning the address it is mapped |
| 1200 | * into. |
| 1201 | * |
| 1202 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1203 | * imply a ref on the object itself. |
| 1204 | */ |
| 1205 | int |
| 1206 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1207 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1208 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1209 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1210 | struct drm_i915_gem_mmap *args = data; |
| 1211 | struct drm_gem_object *obj; |
| 1212 | loff_t offset; |
| 1213 | unsigned long addr; |
| 1214 | |
| 1215 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1216 | return -ENODEV; |
| 1217 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1218 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1219 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1220 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1221 | |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1222 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
| 1223 | drm_gem_object_unreference_unlocked(obj); |
| 1224 | return -E2BIG; |
| 1225 | } |
| 1226 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1227 | offset = args->offset; |
| 1228 | |
| 1229 | down_write(¤t->mm->mmap_sem); |
| 1230 | addr = do_mmap(obj->filp, 0, args->size, |
| 1231 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1232 | args->offset); |
| 1233 | up_write(¤t->mm->mmap_sem); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1234 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1235 | if (IS_ERR((void *)addr)) |
| 1236 | return addr; |
| 1237 | |
| 1238 | args->addr_ptr = (uint64_t) addr; |
| 1239 | |
| 1240 | return 0; |
| 1241 | } |
| 1242 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1243 | /** |
| 1244 | * i915_gem_fault - fault a page into the GTT |
| 1245 | * vma: VMA in question |
| 1246 | * vmf: fault info |
| 1247 | * |
| 1248 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1249 | * from userspace. The fault handler takes care of binding the object to |
| 1250 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1251 | * only if needed based on whether the old reg is still valid or the object |
| 1252 | * is tiled) and inserting a new PTE into the faulting process. |
| 1253 | * |
| 1254 | * Note that the faulting process may involve evicting existing objects |
| 1255 | * from the GTT and/or fence registers to make room. So performance may |
| 1256 | * suffer if the GTT working set is large or there are few fence registers |
| 1257 | * left. |
| 1258 | */ |
| 1259 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1260 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1261 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1262 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1263 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1264 | pgoff_t page_offset; |
| 1265 | unsigned long pfn; |
| 1266 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1267 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1268 | |
| 1269 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1270 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1271 | PAGE_SHIFT; |
| 1272 | |
| 1273 | /* Now bind it into the GTT if needed */ |
| 1274 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1275 | BUG_ON(obj->pin_count && !obj->pin_mappable); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1276 | |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 1277 | if (!obj->map_and_fenceable) { |
| 1278 | ret = i915_gem_object_unbind(obj); |
| 1279 | if (ret) |
| 1280 | goto unlock; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1281 | } |
Daniel Vetter | 16e809a | 2010-09-16 19:37:04 +0200 | [diff] [blame] | 1282 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1283 | if (!obj->gtt_space) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1284 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1285 | if (ret) |
| 1286 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1287 | } |
| 1288 | |
Chris Wilson | 4a684a4 | 2010-10-28 14:44:08 +0100 | [diff] [blame] | 1289 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1290 | if (ret) |
| 1291 | goto unlock; |
| 1292 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1293 | if (!obj->fault_mappable) { |
| 1294 | obj->fault_mappable = true; |
| 1295 | i915_gem_info_update_mappable(dev_priv, obj, true); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1296 | } |
| 1297 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1298 | /* Need a new fence register? */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1299 | if (obj->tiling_mode != I915_TILING_NONE) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 1300 | ret = i915_gem_object_get_fence_reg(obj, true); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1301 | if (ret) |
| 1302 | goto unlock; |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 1303 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1304 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1305 | if (i915_gem_object_is_inactive(obj)) |
| 1306 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1307 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1308 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1309 | page_offset; |
| 1310 | |
| 1311 | /* Finally, remap it using the new GTT offset */ |
| 1312 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1313 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1314 | mutex_unlock(&dev->struct_mutex); |
| 1315 | |
| 1316 | switch (ret) { |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1317 | case -EAGAIN: |
| 1318 | set_need_resched(); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1319 | case 0: |
| 1320 | case -ERESTARTSYS: |
| 1321 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1322 | case -ENOMEM: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1323 | return VM_FAULT_OOM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1324 | default: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1325 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1326 | } |
| 1327 | } |
| 1328 | |
| 1329 | /** |
| 1330 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object |
| 1331 | * @obj: obj in question |
| 1332 | * |
| 1333 | * GEM memory mapping works by handing back to userspace a fake mmap offset |
| 1334 | * it can use in a subsequent mmap(2) call. The DRM core code then looks |
| 1335 | * up the object based on the offset and sets up the various memory mapping |
| 1336 | * structures. |
| 1337 | * |
| 1338 | * This routine allocates and attaches a fake offset for @obj. |
| 1339 | */ |
| 1340 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1341 | i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1342 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1343 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1344 | struct drm_gem_mm *mm = dev->mm_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1345 | struct drm_map_list *list; |
Benjamin Herrenschmidt | f77d390 | 2009-02-02 16:55:46 +1100 | [diff] [blame] | 1346 | struct drm_local_map *map; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1347 | int ret = 0; |
| 1348 | |
| 1349 | /* Set the object up for mmap'ing */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1350 | list = &obj->base.map_list; |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1351 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1352 | if (!list->map) |
| 1353 | return -ENOMEM; |
| 1354 | |
| 1355 | map = list->map; |
| 1356 | map->type = _DRM_GEM; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1357 | map->size = obj->base.size; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1358 | map->handle = obj; |
| 1359 | |
| 1360 | /* Get a DRM GEM mmap offset allocated... */ |
| 1361 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1362 | obj->base.size / PAGE_SIZE, |
| 1363 | 0, 0); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1364 | if (!list->file_offset_node) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1365 | DRM_ERROR("failed to allocate offset for bo %d\n", |
| 1366 | obj->base.name); |
Chris Wilson | 9e0ae534 | 2010-09-21 15:05:24 +0100 | [diff] [blame] | 1367 | ret = -ENOSPC; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1368 | goto out_free_list; |
| 1369 | } |
| 1370 | |
| 1371 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1372 | obj->base.size / PAGE_SIZE, |
| 1373 | 0); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1374 | if (!list->file_offset_node) { |
| 1375 | ret = -ENOMEM; |
| 1376 | goto out_free_list; |
| 1377 | } |
| 1378 | |
| 1379 | list->hash.key = list->file_offset_node->start; |
Chris Wilson | 9e0ae534 | 2010-09-21 15:05:24 +0100 | [diff] [blame] | 1380 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
| 1381 | if (ret) { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1382 | DRM_ERROR("failed to add to map hash\n"); |
| 1383 | goto out_free_mm; |
| 1384 | } |
| 1385 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1386 | return 0; |
| 1387 | |
| 1388 | out_free_mm: |
| 1389 | drm_mm_put_block(list->file_offset_node); |
| 1390 | out_free_list: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1391 | kfree(list->map); |
Chris Wilson | 39a01d1 | 2010-10-28 13:03:06 +0100 | [diff] [blame] | 1392 | list->map = NULL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1393 | |
| 1394 | return ret; |
| 1395 | } |
| 1396 | |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1397 | /** |
| 1398 | * i915_gem_release_mmap - remove physical page mappings |
| 1399 | * @obj: obj in question |
| 1400 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1401 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1402 | * relinquish ownership of the pages back to the system. |
| 1403 | * |
| 1404 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1405 | * object through the GTT and then lose the fence register due to |
| 1406 | * resource pressure. Similarly if the object has been moved out of the |
| 1407 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1408 | * mapping will then trigger a page fault on the next user access, allowing |
| 1409 | * fixup by i915_gem_fault(). |
| 1410 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1411 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1412 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1413 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1414 | struct drm_device *dev = obj->base.dev; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1415 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1416 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1417 | if (unlikely(obj->base.map_list.map && dev->dev_mapping)) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1418 | unmap_mapping_range(dev->dev_mapping, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1419 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, |
| 1420 | obj->base.size, 1); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1421 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1422 | if (obj->fault_mappable) { |
| 1423 | obj->fault_mappable = false; |
| 1424 | i915_gem_info_update_mappable(dev_priv, obj, false); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1425 | } |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1426 | } |
| 1427 | |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1428 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1429 | i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj) |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1430 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1431 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1432 | struct drm_gem_mm *mm = dev->mm_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1433 | struct drm_map_list *list = &obj->base.map_list; |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1434 | |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1435 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
Chris Wilson | 39a01d1 | 2010-10-28 13:03:06 +0100 | [diff] [blame] | 1436 | drm_mm_put_block(list->file_offset_node); |
| 1437 | kfree(list->map); |
| 1438 | list->map = NULL; |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1439 | } |
| 1440 | |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1441 | static uint32_t |
| 1442 | i915_gem_get_gtt_size(struct drm_i915_gem_object *obj) |
| 1443 | { |
| 1444 | struct drm_device *dev = obj->base.dev; |
| 1445 | uint32_t size; |
| 1446 | |
| 1447 | if (INTEL_INFO(dev)->gen >= 4 || |
| 1448 | obj->tiling_mode == I915_TILING_NONE) |
| 1449 | return obj->base.size; |
| 1450 | |
| 1451 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1452 | if (INTEL_INFO(dev)->gen == 3) |
| 1453 | size = 1024*1024; |
| 1454 | else |
| 1455 | size = 512*1024; |
| 1456 | |
| 1457 | while (size < obj->base.size) |
| 1458 | size <<= 1; |
| 1459 | |
| 1460 | return size; |
| 1461 | } |
| 1462 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1463 | /** |
| 1464 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1465 | * @obj: object to check |
| 1466 | * |
| 1467 | * Return the required GTT alignment for an object, taking into account |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1468 | * potential fence register mapping. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1469 | */ |
| 1470 | static uint32_t |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1471 | i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1472 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1473 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1474 | |
| 1475 | /* |
| 1476 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1477 | * if a fence register is needed for the object. |
| 1478 | */ |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1479 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1480 | obj->tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1481 | return 4096; |
| 1482 | |
| 1483 | /* |
| 1484 | * Previous chips need to be aligned to the size of the smallest |
| 1485 | * fence register that can contain the object. |
| 1486 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1487 | return i915_gem_get_gtt_size(obj); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1488 | } |
| 1489 | |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1490 | /** |
| 1491 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an |
| 1492 | * unfenced object |
| 1493 | * @obj: object to check |
| 1494 | * |
| 1495 | * Return the required GTT alignment for an object, only taking into account |
| 1496 | * unfenced tiled surface requirements. |
| 1497 | */ |
| 1498 | static uint32_t |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1499 | i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1500 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1501 | struct drm_device *dev = obj->base.dev; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1502 | int tile_height; |
| 1503 | |
| 1504 | /* |
| 1505 | * Minimum alignment is 4k (GTT page size) for sane hw. |
| 1506 | */ |
| 1507 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1508 | obj->tiling_mode == I915_TILING_NONE) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1509 | return 4096; |
| 1510 | |
| 1511 | /* |
| 1512 | * Older chips need unfenced tiled buffers to be aligned to the left |
| 1513 | * edge of an even tile row (where tile rows are counted as if the bo is |
| 1514 | * placed in a fenced gtt region). |
| 1515 | */ |
| 1516 | if (IS_GEN2(dev) || |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1517 | (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1518 | tile_height = 32; |
| 1519 | else |
| 1520 | tile_height = 8; |
| 1521 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1522 | return tile_height * obj->stride * 2; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1523 | } |
| 1524 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1525 | /** |
| 1526 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1527 | * @dev: DRM device |
| 1528 | * @data: GTT mapping ioctl data |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1529 | * @file: GEM object info |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1530 | * |
| 1531 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1532 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1533 | * up so we can get faults in the handler above. |
| 1534 | * |
| 1535 | * The fault handler will take care of binding the object into the GTT |
| 1536 | * (since it may have been evicted to make room for something), allocating |
| 1537 | * a fence register, and mapping the appropriate aperture address into |
| 1538 | * userspace. |
| 1539 | */ |
| 1540 | int |
| 1541 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1542 | struct drm_file *file) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1543 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1544 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1545 | struct drm_i915_gem_mmap_gtt *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1546 | struct drm_i915_gem_object *obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1547 | int ret; |
| 1548 | |
| 1549 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1550 | return -ENODEV; |
| 1551 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1552 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1553 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1554 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1555 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1556 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1557 | if (obj == NULL) { |
| 1558 | ret = -ENOENT; |
| 1559 | goto unlock; |
| 1560 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1561 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1562 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1563 | ret = -E2BIG; |
| 1564 | goto unlock; |
| 1565 | } |
| 1566 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1567 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1568 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1569 | ret = -EINVAL; |
| 1570 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1571 | } |
| 1572 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1573 | if (!obj->base.map_list.map) { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1574 | ret = i915_gem_create_mmap_offset(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1575 | if (ret) |
| 1576 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1577 | } |
| 1578 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1579 | args->offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1580 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1581 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1582 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1583 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1584 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1585 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1586 | } |
| 1587 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1588 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1589 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1590 | gfp_t gfpmask) |
| 1591 | { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1592 | int page_count, i; |
| 1593 | struct address_space *mapping; |
| 1594 | struct inode *inode; |
| 1595 | struct page *page; |
| 1596 | |
| 1597 | /* Get the list of pages out of our struct file. They'll be pinned |
| 1598 | * at this point until we release them. |
| 1599 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1600 | page_count = obj->base.size / PAGE_SIZE; |
| 1601 | BUG_ON(obj->pages != NULL); |
| 1602 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); |
| 1603 | if (obj->pages == NULL) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1604 | return -ENOMEM; |
| 1605 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1606 | inode = obj->base.filp->f_path.dentry->d_inode; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1607 | mapping = inode->i_mapping; |
| 1608 | for (i = 0; i < page_count; i++) { |
| 1609 | page = read_cache_page_gfp(mapping, i, |
| 1610 | GFP_HIGHUSER | |
| 1611 | __GFP_COLD | |
| 1612 | __GFP_RECLAIMABLE | |
| 1613 | gfpmask); |
| 1614 | if (IS_ERR(page)) |
| 1615 | goto err_pages; |
| 1616 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1617 | obj->pages[i] = page; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1618 | } |
| 1619 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1620 | if (obj->tiling_mode != I915_TILING_NONE) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1621 | i915_gem_object_do_bit_17_swizzle(obj); |
| 1622 | |
| 1623 | return 0; |
| 1624 | |
| 1625 | err_pages: |
| 1626 | while (i--) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1627 | page_cache_release(obj->pages[i]); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1628 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1629 | drm_free_large(obj->pages); |
| 1630 | obj->pages = NULL; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1631 | return PTR_ERR(page); |
| 1632 | } |
| 1633 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1634 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1635 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1636 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1637 | int page_count = obj->base.size / PAGE_SIZE; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1638 | int i; |
| 1639 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1640 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1641 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1642 | if (obj->tiling_mode != I915_TILING_NONE) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1643 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1644 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1645 | if (obj->madv == I915_MADV_DONTNEED) |
| 1646 | obj->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1647 | |
| 1648 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1649 | if (obj->dirty) |
| 1650 | set_page_dirty(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1651 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1652 | if (obj->madv == I915_MADV_WILLNEED) |
| 1653 | mark_page_accessed(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1654 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1655 | page_cache_release(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1656 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1657 | obj->dirty = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1658 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1659 | drm_free_large(obj->pages); |
| 1660 | obj->pages = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1661 | } |
| 1662 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1663 | static uint32_t |
| 1664 | i915_gem_next_request_seqno(struct drm_device *dev, |
| 1665 | struct intel_ring_buffer *ring) |
| 1666 | { |
| 1667 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 5d97eb6 | 2010-11-10 20:40:02 +0000 | [diff] [blame] | 1668 | return ring->outstanding_lazy_request = dev_priv->next_seqno; |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1669 | } |
| 1670 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1671 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1672 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1673 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1674 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1675 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1676 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1677 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1678 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1679 | BUG_ON(ring == NULL); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1680 | obj->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1681 | |
| 1682 | /* Add a reference if we're newly entering the active list. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1683 | if (!obj->active) { |
| 1684 | drm_gem_object_reference(&obj->base); |
| 1685 | obj->active = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1686 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1687 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1688 | /* Move from whatever list we were on to the tail of execution. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1689 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
| 1690 | list_move_tail(&obj->ring_list, &ring->active_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1691 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1692 | obj->last_rendering_seqno = seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1693 | if (obj->fenced_gpu_access) { |
| 1694 | struct drm_i915_fence_reg *reg; |
| 1695 | |
| 1696 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); |
| 1697 | |
| 1698 | obj->last_fenced_seqno = seqno; |
| 1699 | obj->last_fenced_ring = ring; |
| 1700 | |
| 1701 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
| 1702 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
| 1703 | } |
| 1704 | } |
| 1705 | |
| 1706 | static void |
| 1707 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) |
| 1708 | { |
| 1709 | list_del_init(&obj->ring_list); |
| 1710 | obj->last_rendering_seqno = 0; |
| 1711 | obj->last_fenced_seqno = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1712 | } |
| 1713 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1714 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1715 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1716 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1717 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1718 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1719 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1720 | BUG_ON(!obj->active); |
| 1721 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1722 | |
| 1723 | i915_gem_object_move_off_active(obj); |
| 1724 | } |
| 1725 | |
| 1726 | static void |
| 1727 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
| 1728 | { |
| 1729 | struct drm_device *dev = obj->base.dev; |
| 1730 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1731 | |
| 1732 | if (obj->pin_count != 0) |
| 1733 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); |
| 1734 | else |
| 1735 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
| 1736 | |
| 1737 | BUG_ON(!list_empty(&obj->gpu_write_list)); |
| 1738 | BUG_ON(!obj->active); |
| 1739 | obj->ring = NULL; |
| 1740 | |
| 1741 | i915_gem_object_move_off_active(obj); |
| 1742 | obj->fenced_gpu_access = false; |
| 1743 | obj->last_fenced_ring = NULL; |
| 1744 | |
| 1745 | obj->active = 0; |
| 1746 | drm_gem_object_unreference(&obj->base); |
| 1747 | |
| 1748 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1749 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1750 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1751 | /* Immediately discard the backing storage */ |
| 1752 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1753 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1754 | { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1755 | struct inode *inode; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1756 | |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1757 | /* Our goal here is to return as much of the memory as |
| 1758 | * is possible back to the system as we are called from OOM. |
| 1759 | * To do this we must instruct the shmfs to drop all of its |
| 1760 | * backing pages, *now*. Here we mirror the actions taken |
| 1761 | * when by shmem_delete_inode() to release the backing store. |
| 1762 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1763 | inode = obj->base.filp->f_path.dentry->d_inode; |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1764 | truncate_inode_pages(inode->i_mapping, 0); |
| 1765 | if (inode->i_op->truncate_range) |
| 1766 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1767 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1768 | obj->madv = __I915_MADV_PURGED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1769 | } |
| 1770 | |
| 1771 | static inline int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1772 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1773 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1774 | return obj->madv == I915_MADV_DONTNEED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1775 | } |
| 1776 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1777 | static void |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1778 | i915_gem_process_flushing_list(struct drm_device *dev, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1779 | uint32_t flush_domains, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1780 | struct intel_ring_buffer *ring) |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1781 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1782 | struct drm_i915_gem_object *obj, *next; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1783 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1784 | list_for_each_entry_safe(obj, next, |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 1785 | &ring->gpu_write_list, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1786 | gpu_write_list) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1787 | if (obj->base.write_domain & flush_domains) { |
| 1788 | uint32_t old_write_domain = obj->base.write_domain; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1789 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1790 | obj->base.write_domain = 0; |
| 1791 | list_del_init(&obj->gpu_write_list); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1792 | i915_gem_object_move_to_active(obj, ring); |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1793 | |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1794 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1795 | obj->base.read_domains, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1796 | old_write_domain); |
| 1797 | } |
| 1798 | } |
| 1799 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1800 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1801 | int |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1802 | i915_add_request(struct drm_device *dev, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1803 | struct drm_file *file, |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 1804 | struct drm_i915_gem_request *request, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1805 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1806 | { |
| 1807 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1808 | struct drm_i915_file_private *file_priv = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1809 | uint32_t seqno; |
| 1810 | int was_empty; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1811 | int ret; |
| 1812 | |
| 1813 | BUG_ON(request == NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1814 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1815 | if (file != NULL) |
| 1816 | file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1817 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1818 | ret = ring->add_request(ring, &seqno); |
| 1819 | if (ret) |
| 1820 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1821 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1822 | ring->outstanding_lazy_request = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1823 | |
| 1824 | request->seqno = seqno; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1825 | request->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1826 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1827 | was_empty = list_empty(&ring->request_list); |
| 1828 | list_add_tail(&request->list, &ring->request_list); |
| 1829 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1830 | if (file_priv) { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1831 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1832 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1833 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1834 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1835 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1836 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1837 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1838 | if (!dev_priv->mm.suspended) { |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1839 | mod_timer(&dev_priv->hangcheck_timer, |
| 1840 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1841 | if (was_empty) |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1842 | queue_delayed_work(dev_priv->wq, |
| 1843 | &dev_priv->mm.retire_work, HZ); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1844 | } |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1845 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1846 | } |
| 1847 | |
| 1848 | /** |
| 1849 | * Command execution barrier |
| 1850 | * |
| 1851 | * Ensures that all commands in the ring are finished |
| 1852 | * before signalling the CPU |
| 1853 | */ |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1854 | static void |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1855 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1856 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1857 | uint32_t flush_domains = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1858 | |
| 1859 | /* The sampler always gets flushed on i965 (sigh) */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1860 | if (INTEL_INFO(dev)->gen >= 4) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1861 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1862 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1863 | ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1864 | } |
| 1865 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1866 | static inline void |
| 1867 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1868 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1869 | struct drm_i915_file_private *file_priv = request->file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1870 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1871 | if (!file_priv) |
| 1872 | return; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1873 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1874 | spin_lock(&file_priv->mm.lock); |
| 1875 | list_del(&request->client_list); |
| 1876 | request->file_priv = NULL; |
| 1877 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1878 | } |
| 1879 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1880 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
| 1881 | struct intel_ring_buffer *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1882 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1883 | while (!list_empty(&ring->request_list)) { |
| 1884 | struct drm_i915_gem_request *request; |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1885 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1886 | request = list_first_entry(&ring->request_list, |
| 1887 | struct drm_i915_gem_request, |
| 1888 | list); |
| 1889 | |
| 1890 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1891 | i915_gem_request_remove_from_client(request); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1892 | kfree(request); |
| 1893 | } |
| 1894 | |
| 1895 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1896 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1897 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1898 | obj = list_first_entry(&ring->active_list, |
| 1899 | struct drm_i915_gem_object, |
| 1900 | ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1901 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1902 | obj->base.write_domain = 0; |
| 1903 | list_del_init(&obj->gpu_write_list); |
| 1904 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1905 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1906 | } |
| 1907 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame^] | 1908 | static void i915_gem_reset_fences(struct drm_device *dev) |
| 1909 | { |
| 1910 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1911 | int i; |
| 1912 | |
| 1913 | for (i = 0; i < 16; i++) { |
| 1914 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
| 1915 | if (reg->obj) |
| 1916 | i915_gem_clear_fence_reg(reg->obj); |
| 1917 | } |
| 1918 | } |
| 1919 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1920 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1921 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1922 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1923 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1924 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1925 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 1926 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1927 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1928 | |
| 1929 | /* Remove anything from the flushing lists. The GPU cache is likely |
| 1930 | * to be lost on reset along with the data, so simply move the |
| 1931 | * lost bo to the inactive list. |
| 1932 | */ |
| 1933 | while (!list_empty(&dev_priv->mm.flushing_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1934 | obj= list_first_entry(&dev_priv->mm.flushing_list, |
| 1935 | struct drm_i915_gem_object, |
| 1936 | mm_list); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1937 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1938 | obj->base.write_domain = 0; |
| 1939 | list_del_init(&obj->gpu_write_list); |
| 1940 | i915_gem_object_move_to_inactive(obj); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1941 | } |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1942 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1943 | /* Move everything out of the GPU domains to ensure we do any |
| 1944 | * necessary invalidation upon reuse. |
| 1945 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1946 | list_for_each_entry(obj, |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1947 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1948 | mm_list) |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1949 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1950 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1951 | } |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1952 | |
| 1953 | /* The fence registers are invalidated so clear them out */ |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame^] | 1954 | i915_gem_reset_fences(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1955 | } |
| 1956 | |
| 1957 | /** |
| 1958 | * This function clears the request list as sequence numbers are passed. |
| 1959 | */ |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1960 | static void |
| 1961 | i915_gem_retire_requests_ring(struct drm_device *dev, |
| 1962 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1963 | { |
| 1964 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1965 | uint32_t seqno; |
| 1966 | |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1967 | if (!ring->status_page.page_addr || |
| 1968 | list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 1969 | return; |
| 1970 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1971 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1972 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1973 | seqno = ring->get_seqno(ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1974 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1975 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1976 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1977 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1978 | struct drm_i915_gem_request, |
| 1979 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1980 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1981 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1982 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1983 | |
| 1984 | trace_i915_gem_request_retire(dev, request->seqno); |
| 1985 | |
| 1986 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1987 | i915_gem_request_remove_from_client(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1988 | kfree(request); |
| 1989 | } |
| 1990 | |
| 1991 | /* Move any buffers on the active list that are no longer referenced |
| 1992 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 1993 | */ |
| 1994 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1995 | struct drm_i915_gem_object *obj; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1996 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1997 | obj= list_first_entry(&ring->active_list, |
| 1998 | struct drm_i915_gem_object, |
| 1999 | ring_list); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2000 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2001 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2002 | break; |
| 2003 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2004 | if (obj->base.write_domain != 0) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2005 | i915_gem_object_move_to_flushing(obj); |
| 2006 | else |
| 2007 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2008 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 2009 | |
| 2010 | if (unlikely (dev_priv->trace_irq_seqno && |
| 2011 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2012 | ring->user_irq_put(ring); |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 2013 | dev_priv->trace_irq_seqno = 0; |
| 2014 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 2015 | |
| 2016 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2017 | } |
| 2018 | |
| 2019 | void |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2020 | i915_gem_retire_requests(struct drm_device *dev) |
| 2021 | { |
| 2022 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2023 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 2024 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2025 | struct drm_i915_gem_object *obj, *next; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 2026 | |
| 2027 | /* We must be careful that during unbind() we do not |
| 2028 | * accidentally infinitely recurse into retire requests. |
| 2029 | * Currently: |
| 2030 | * retire -> free -> unbind -> wait -> retire_ring |
| 2031 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2032 | list_for_each_entry_safe(obj, next, |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 2033 | &dev_priv->mm.deferred_free_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 2034 | mm_list) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2035 | i915_gem_free_object_tail(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 2036 | } |
| 2037 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2038 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 2039 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2040 | i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2041 | } |
| 2042 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 2043 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2044 | i915_gem_retire_work_handler(struct work_struct *work) |
| 2045 | { |
| 2046 | drm_i915_private_t *dev_priv; |
| 2047 | struct drm_device *dev; |
| 2048 | |
| 2049 | dev_priv = container_of(work, drm_i915_private_t, |
| 2050 | mm.retire_work.work); |
| 2051 | dev = dev_priv->dev; |
| 2052 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 2053 | /* Come back later if the device is busy... */ |
| 2054 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 2055 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 2056 | return; |
| 2057 | } |
| 2058 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2059 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2060 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 2061 | if (!dev_priv->mm.suspended && |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2062 | (!list_empty(&dev_priv->render_ring.request_list) || |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2063 | !list_empty(&dev_priv->bsd_ring.request_list) || |
| 2064 | !list_empty(&dev_priv->blt_ring.request_list))) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 2065 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2066 | mutex_unlock(&dev->struct_mutex); |
| 2067 | } |
| 2068 | |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 2069 | int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2070 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2071 | bool interruptible, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2072 | { |
| 2073 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 2074 | u32 ier; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2075 | int ret = 0; |
| 2076 | |
| 2077 | BUG_ON(seqno == 0); |
| 2078 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 2079 | if (atomic_read(&dev_priv->mm.wedged)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 2080 | return -EAGAIN; |
Ben Gamari | ffed1d0 | 2009-09-14 17:48:41 -0400 | [diff] [blame] | 2081 | |
Chris Wilson | 5d97eb6 | 2010-11-10 20:40:02 +0000 | [diff] [blame] | 2082 | if (seqno == ring->outstanding_lazy_request) { |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2083 | struct drm_i915_gem_request *request; |
| 2084 | |
| 2085 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 2086 | if (request == NULL) |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2087 | return -ENOMEM; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2088 | |
| 2089 | ret = i915_add_request(dev, NULL, request, ring); |
| 2090 | if (ret) { |
| 2091 | kfree(request); |
| 2092 | return ret; |
| 2093 | } |
| 2094 | |
| 2095 | seqno = request->seqno; |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2096 | } |
| 2097 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2098 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 2099 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2100 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
| 2101 | else |
| 2102 | ier = I915_READ(IER); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 2103 | if (!ier) { |
| 2104 | DRM_ERROR("something (likely vbetool) disabled " |
| 2105 | "interrupts, re-enabling\n"); |
| 2106 | i915_driver_irq_preinstall(dev); |
| 2107 | i915_driver_irq_postinstall(dev); |
| 2108 | } |
| 2109 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2110 | trace_i915_gem_request_wait_begin(dev, seqno); |
| 2111 | |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 2112 | ring->waiting_seqno = seqno; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2113 | ring->user_irq_get(ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2114 | if (interruptible) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2115 | ret = wait_event_interruptible(ring->irq_queue, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2116 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2117 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2118 | else |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2119 | wait_event(ring->irq_queue, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2120 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2121 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2122 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2123 | ring->user_irq_put(ring); |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 2124 | ring->waiting_seqno = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2125 | |
| 2126 | trace_i915_gem_request_wait_end(dev, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2127 | } |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 2128 | if (atomic_read(&dev_priv->mm.wedged)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 2129 | ret = -EAGAIN; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2130 | |
| 2131 | if (ret && ret != -ERESTARTSYS) |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2132 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2133 | __func__, ret, seqno, ring->get_seqno(ring), |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2134 | dev_priv->next_seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2135 | |
| 2136 | /* Directly dispatch request retiring. While we have the work queue |
| 2137 | * to handle this, the waiter on a request often wants an associated |
| 2138 | * buffer to have made it to the inactive list, and we would need |
| 2139 | * a separate wait queue to handle that. |
| 2140 | */ |
| 2141 | if (ret == 0) |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2142 | i915_gem_retire_requests_ring(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2143 | |
| 2144 | return ret; |
| 2145 | } |
| 2146 | |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2147 | /** |
| 2148 | * Waits for a sequence number to be signaled, and cleans up the |
| 2149 | * request and object lists appropriately for that event. |
| 2150 | */ |
| 2151 | static int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2152 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2153 | struct intel_ring_buffer *ring) |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2154 | { |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2155 | return i915_do_wait_request(dev, seqno, 1, ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2156 | } |
| 2157 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2158 | static void |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2159 | i915_gem_flush_ring(struct drm_device *dev, |
| 2160 | struct intel_ring_buffer *ring, |
| 2161 | uint32_t invalidate_domains, |
| 2162 | uint32_t flush_domains) |
| 2163 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2164 | ring->flush(ring, invalidate_domains, flush_domains); |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2165 | i915_gem_process_flushing_list(dev, flush_domains, ring); |
| 2166 | } |
| 2167 | |
| 2168 | static void |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2169 | i915_gem_flush(struct drm_device *dev, |
| 2170 | uint32_t invalidate_domains, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2171 | uint32_t flush_domains, |
| 2172 | uint32_t flush_rings) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2173 | { |
| 2174 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2175 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2176 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 2177 | intel_gtt_chipset_flush(); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2178 | |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2179 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
| 2180 | if (flush_rings & RING_RENDER) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2181 | i915_gem_flush_ring(dev, &dev_priv->render_ring, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2182 | invalidate_domains, flush_domains); |
| 2183 | if (flush_rings & RING_BSD) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2184 | i915_gem_flush_ring(dev, &dev_priv->bsd_ring, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2185 | invalidate_domains, flush_domains); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2186 | if (flush_rings & RING_BLT) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2187 | i915_gem_flush_ring(dev, &dev_priv->blt_ring, |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2188 | invalidate_domains, flush_domains); |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2189 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2190 | } |
| 2191 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2192 | /** |
| 2193 | * Ensures that all rendering to the object has completed and the object is |
| 2194 | * safe to unbind from the GTT or access from the CPU. |
| 2195 | */ |
| 2196 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2197 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2198 | bool interruptible) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2199 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2200 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2201 | int ret; |
| 2202 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2203 | /* This function only exists to support waiting for existing rendering, |
| 2204 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2205 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2206 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2207 | |
| 2208 | /* If there is rendering queued on the buffer being evicted, wait for |
| 2209 | * it. |
| 2210 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2211 | if (obj->active) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2212 | ret = i915_do_wait_request(dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2213 | obj->last_rendering_seqno, |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2214 | interruptible, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2215 | obj->ring); |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2216 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2217 | return ret; |
| 2218 | } |
| 2219 | |
| 2220 | return 0; |
| 2221 | } |
| 2222 | |
| 2223 | /** |
| 2224 | * Unbinds an object from the GTT aperture. |
| 2225 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2226 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2227 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2228 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2229 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2230 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2231 | int ret = 0; |
| 2232 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2233 | if (obj->gtt_space == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2234 | return 0; |
| 2235 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2236 | if (obj->pin_count != 0) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2237 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
| 2238 | return -EINVAL; |
| 2239 | } |
| 2240 | |
Eric Anholt | 5323fd0 | 2009-09-09 11:50:45 -0700 | [diff] [blame] | 2241 | /* blow away mappings if mapped through GTT */ |
| 2242 | i915_gem_release_mmap(obj); |
| 2243 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2244 | /* Move the object to the CPU domain to ensure that |
| 2245 | * any possible CPU writes while it's not in the GTT |
| 2246 | * are flushed when we go to remap it. This will |
| 2247 | * also ensure that all pending GPU writes are finished |
| 2248 | * before we unbind. |
| 2249 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2250 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2251 | if (ret == -ERESTARTSYS) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2252 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2253 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2254 | * should be safe and we need to cleanup or else we might |
| 2255 | * cause memory corruption through use-after-free. |
| 2256 | */ |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2257 | if (ret) { |
| 2258 | i915_gem_clflush_object(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2259 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2260 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2261 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2262 | /* release the fence reg _after_ flushing */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2263 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2264 | i915_gem_clear_fence_reg(obj); |
| 2265 | |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 2266 | i915_gem_gtt_unbind_object(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2267 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2268 | i915_gem_object_put_pages_gtt(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2269 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2270 | i915_gem_info_remove_gtt(dev_priv, obj); |
| 2271 | list_del_init(&obj->mm_list); |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2272 | /* Avoid an unnecessary call to unbind on rebind. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2273 | obj->map_and_fenceable = true; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2274 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2275 | drm_mm_put_block(obj->gtt_space); |
| 2276 | obj->gtt_space = NULL; |
| 2277 | obj->gtt_offset = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2278 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2279 | if (i915_gem_object_is_purgeable(obj)) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2280 | i915_gem_object_truncate(obj); |
| 2281 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2282 | trace_i915_gem_object_unbind(obj); |
| 2283 | |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2284 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2285 | } |
| 2286 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2287 | static int i915_ring_idle(struct drm_device *dev, |
| 2288 | struct intel_ring_buffer *ring) |
| 2289 | { |
Chris Wilson | 395b70b | 2010-10-28 21:28:46 +0100 | [diff] [blame] | 2290 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 2291 | return 0; |
| 2292 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2293 | i915_gem_flush_ring(dev, ring, |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2294 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 2295 | return i915_wait_request(dev, |
| 2296 | i915_gem_next_request_seqno(dev, ring), |
| 2297 | ring); |
| 2298 | } |
| 2299 | |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 2300 | int |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2301 | i915_gpu_idle(struct drm_device *dev) |
| 2302 | { |
| 2303 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2304 | bool lists_empty; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2305 | int ret; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2306 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2307 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
Chris Wilson | 395b70b | 2010-10-28 21:28:46 +0100 | [diff] [blame] | 2308 | list_empty(&dev_priv->mm.active_list)); |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2309 | if (lists_empty) |
| 2310 | return 0; |
| 2311 | |
| 2312 | /* Flush everything onto the inactive list. */ |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2313 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2314 | if (ret) |
| 2315 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2316 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 2317 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
| 2318 | if (ret) |
| 2319 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2320 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2321 | ret = i915_ring_idle(dev, &dev_priv->blt_ring); |
| 2322 | if (ret) |
| 2323 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2324 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2325 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2326 | } |
| 2327 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2328 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2329 | struct intel_ring_buffer *pipelined) |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2330 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2331 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2332 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2333 | u32 size = obj->gtt_space->size; |
| 2334 | int regnum = obj->fence_reg; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2335 | uint64_t val; |
| 2336 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2337 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2338 | 0xfffff000) << 32; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2339 | val |= obj->gtt_offset & 0xfffff000; |
| 2340 | val |= (uint64_t)((obj->stride / 128) - 1) << |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2341 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 2342 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2343 | if (obj->tiling_mode == I915_TILING_Y) |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2344 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2345 | val |= I965_FENCE_REG_VALID; |
| 2346 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2347 | if (pipelined) { |
| 2348 | int ret = intel_ring_begin(pipelined, 6); |
| 2349 | if (ret) |
| 2350 | return ret; |
| 2351 | |
| 2352 | intel_ring_emit(pipelined, MI_NOOP); |
| 2353 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); |
| 2354 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); |
| 2355 | intel_ring_emit(pipelined, (u32)val); |
| 2356 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); |
| 2357 | intel_ring_emit(pipelined, (u32)(val >> 32)); |
| 2358 | intel_ring_advance(pipelined); |
| 2359 | } else |
| 2360 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); |
| 2361 | |
| 2362 | return 0; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2363 | } |
| 2364 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2365 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2366 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2367 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2368 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2369 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2370 | u32 size = obj->gtt_space->size; |
| 2371 | int regnum = obj->fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2372 | uint64_t val; |
| 2373 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2374 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2375 | 0xfffff000) << 32; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2376 | val |= obj->gtt_offset & 0xfffff000; |
| 2377 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2378 | if (obj->tiling_mode == I915_TILING_Y) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2379 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2380 | val |= I965_FENCE_REG_VALID; |
| 2381 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2382 | if (pipelined) { |
| 2383 | int ret = intel_ring_begin(pipelined, 6); |
| 2384 | if (ret) |
| 2385 | return ret; |
| 2386 | |
| 2387 | intel_ring_emit(pipelined, MI_NOOP); |
| 2388 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); |
| 2389 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); |
| 2390 | intel_ring_emit(pipelined, (u32)val); |
| 2391 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); |
| 2392 | intel_ring_emit(pipelined, (u32)(val >> 32)); |
| 2393 | intel_ring_advance(pipelined); |
| 2394 | } else |
| 2395 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); |
| 2396 | |
| 2397 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2398 | } |
| 2399 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2400 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2401 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2402 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2403 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2404 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2405 | u32 size = obj->gtt_space->size; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2406 | u32 fence_reg, val, pitch_val; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2407 | int tile_width; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2408 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2409 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2410 | (size & -size) != size || |
| 2411 | (obj->gtt_offset & (size - 1)), |
| 2412 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
| 2413 | obj->gtt_offset, obj->map_and_fenceable, size)) |
| 2414 | return -EINVAL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2415 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2416 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2417 | tile_width = 128; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2418 | else |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2419 | tile_width = 512; |
| 2420 | |
| 2421 | /* Note: pitch better be a power of two tile widths */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2422 | pitch_val = obj->stride / tile_width; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2423 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2424 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2425 | val = obj->gtt_offset; |
| 2426 | if (obj->tiling_mode == I915_TILING_Y) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2427 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2428 | val |= I915_FENCE_SIZE_BITS(size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2429 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2430 | val |= I830_FENCE_REG_VALID; |
| 2431 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2432 | fence_reg = obj->fence_reg; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2433 | if (fence_reg < 8) |
| 2434 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2435 | else |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2436 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2437 | |
| 2438 | if (pipelined) { |
| 2439 | int ret = intel_ring_begin(pipelined, 4); |
| 2440 | if (ret) |
| 2441 | return ret; |
| 2442 | |
| 2443 | intel_ring_emit(pipelined, MI_NOOP); |
| 2444 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); |
| 2445 | intel_ring_emit(pipelined, fence_reg); |
| 2446 | intel_ring_emit(pipelined, val); |
| 2447 | intel_ring_advance(pipelined); |
| 2448 | } else |
| 2449 | I915_WRITE(fence_reg, val); |
| 2450 | |
| 2451 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2452 | } |
| 2453 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2454 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2455 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2456 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2457 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2458 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2459 | u32 size = obj->gtt_space->size; |
| 2460 | int regnum = obj->fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2461 | uint32_t val; |
| 2462 | uint32_t pitch_val; |
| 2463 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2464 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
| 2465 | (size & -size) != size || |
| 2466 | (obj->gtt_offset & (size - 1)), |
| 2467 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", |
| 2468 | obj->gtt_offset, size)) |
| 2469 | return -EINVAL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2470 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2471 | pitch_val = obj->stride / 128; |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2472 | pitch_val = ffs(pitch_val) - 1; |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2473 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2474 | val = obj->gtt_offset; |
| 2475 | if (obj->tiling_mode == I915_TILING_Y) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2476 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2477 | val |= I830_FENCE_SIZE_BITS(size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2478 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2479 | val |= I830_FENCE_REG_VALID; |
| 2480 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2481 | if (pipelined) { |
| 2482 | int ret = intel_ring_begin(pipelined, 4); |
| 2483 | if (ret) |
| 2484 | return ret; |
| 2485 | |
| 2486 | intel_ring_emit(pipelined, MI_NOOP); |
| 2487 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); |
| 2488 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); |
| 2489 | intel_ring_emit(pipelined, val); |
| 2490 | intel_ring_advance(pipelined); |
| 2491 | } else |
| 2492 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); |
| 2493 | |
| 2494 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2495 | } |
| 2496 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2497 | static int i915_find_fence_reg(struct drm_device *dev, |
| 2498 | bool interruptible) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2499 | { |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2500 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2501 | struct drm_i915_fence_reg *reg; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2502 | struct drm_i915_gem_object *obj = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2503 | int i, avail, ret; |
| 2504 | |
| 2505 | /* First try to find a free reg */ |
| 2506 | avail = 0; |
| 2507 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2508 | reg = &dev_priv->fence_regs[i]; |
| 2509 | if (!reg->obj) |
| 2510 | return i; |
| 2511 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2512 | if (!reg->obj->pin_count) |
| 2513 | avail++; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2514 | } |
| 2515 | |
| 2516 | if (avail == 0) |
| 2517 | return -ENOSPC; |
| 2518 | |
| 2519 | /* None available, try to steal one or wait for a user to finish */ |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2520 | avail = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2521 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
| 2522 | lru_list) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2523 | obj = reg->obj; |
| 2524 | if (obj->pin_count) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2525 | continue; |
| 2526 | |
| 2527 | /* found one! */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2528 | avail = obj->fence_reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2529 | break; |
| 2530 | } |
| 2531 | |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2532 | BUG_ON(avail == I915_FENCE_REG_NONE); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2533 | |
| 2534 | /* We only have a reference on obj from the active list. put_fence_reg |
| 2535 | * might drop that one, causing a use-after-free in it. So hold a |
| 2536 | * private reference to obj like the other callers of put_fence_reg |
| 2537 | * (set_tiling ioctl) do. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2538 | drm_gem_object_reference(&obj->base); |
| 2539 | ret = i915_gem_object_put_fence_reg(obj, interruptible); |
| 2540 | drm_gem_object_unreference(&obj->base); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2541 | if (ret != 0) |
| 2542 | return ret; |
| 2543 | |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2544 | return avail; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2545 | } |
| 2546 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2547 | /** |
| 2548 | * i915_gem_object_get_fence_reg - set up a fence reg for an object |
| 2549 | * @obj: object to map through a fence reg |
| 2550 | * |
| 2551 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2552 | * to them without having to worry about swizzling if the object is tiled. |
| 2553 | * |
| 2554 | * This function walks the fence regs looking for a free one for @obj, |
| 2555 | * stealing one if it can't find any. |
| 2556 | * |
| 2557 | * It then sets up the reg based on the object's properties: address, pitch |
| 2558 | * and tiling format. |
| 2559 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2560 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2561 | i915_gem_object_get_fence_reg(struct drm_i915_gem_object *obj, |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2562 | bool interruptible) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2563 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2564 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2565 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2566 | struct drm_i915_fence_reg *reg = NULL; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2567 | struct intel_ring_buffer *pipelined = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2568 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2569 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2570 | /* Just update our place in the LRU if our fence is getting used. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2571 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2572 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2573 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2574 | return 0; |
| 2575 | } |
| 2576 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2577 | switch (obj->tiling_mode) { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2578 | case I915_TILING_NONE: |
| 2579 | WARN(1, "allocating a fence for non-tiled object?\n"); |
| 2580 | break; |
| 2581 | case I915_TILING_X: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2582 | if (!obj->stride) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2583 | return -EINVAL; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2584 | WARN((obj->stride & (512 - 1)), |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2585 | "object 0x%08x is X tiled but has non-512B pitch\n", |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2586 | obj->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2587 | break; |
| 2588 | case I915_TILING_Y: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2589 | if (!obj->stride) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2590 | return -EINVAL; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2591 | WARN((obj->stride & (128 - 1)), |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2592 | "object 0x%08x is Y tiled but has non-128B pitch\n", |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2593 | obj->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2594 | break; |
| 2595 | } |
| 2596 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2597 | ret = i915_find_fence_reg(dev, interruptible); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2598 | if (ret < 0) |
| 2599 | return ret; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2600 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2601 | obj->fence_reg = ret; |
| 2602 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2603 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2604 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2605 | reg->obj = obj; |
| 2606 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2607 | switch (INTEL_INFO(dev)->gen) { |
| 2608 | case 6: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2609 | ret = sandybridge_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2610 | break; |
| 2611 | case 5: |
| 2612 | case 4: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2613 | ret = i965_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2614 | break; |
| 2615 | case 3: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2616 | ret = i915_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2617 | break; |
| 2618 | case 2: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2619 | ret = i830_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2620 | break; |
| 2621 | } |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2622 | |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2623 | trace_i915_gem_object_get_fence(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2624 | obj->fence_reg, |
| 2625 | obj->tiling_mode); |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2626 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2627 | } |
| 2628 | |
| 2629 | /** |
| 2630 | * i915_gem_clear_fence_reg - clear out fence register info |
| 2631 | * @obj: object to clear |
| 2632 | * |
| 2633 | * Zeroes out the fence register itself and clears out the associated |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2634 | * data structures in dev_priv and obj. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2635 | */ |
| 2636 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2637 | i915_gem_clear_fence_reg(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2638 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2639 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2640 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2641 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[obj->fence_reg]; |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2642 | uint32_t fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2643 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2644 | switch (INTEL_INFO(dev)->gen) { |
| 2645 | case 6: |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2646 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2647 | (obj->fence_reg * 8), 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2648 | break; |
| 2649 | case 5: |
| 2650 | case 4: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2651 | I915_WRITE64(FENCE_REG_965_0 + (obj->fence_reg * 8), 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2652 | break; |
| 2653 | case 3: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2654 | if (obj->fence_reg >= 8) |
| 2655 | fence_reg = FENCE_REG_945_8 + (obj->fence_reg - 8) * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2656 | else |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2657 | case 2: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2658 | fence_reg = FENCE_REG_830_0 + obj->fence_reg * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2659 | |
| 2660 | I915_WRITE(fence_reg, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2661 | break; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2662 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2663 | |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2664 | reg->obj = NULL; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2665 | obj->fence_reg = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2666 | list_del_init(®->lru_list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2667 | } |
| 2668 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2669 | /** |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2670 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access |
| 2671 | * to the buffer to finish, and then resets the fence register. |
| 2672 | * @obj: tiled object holding a fence register. |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2673 | * @bool: whether the wait upon the fence is interruptible |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2674 | * |
| 2675 | * Zeroes out the fence register itself and clears out the associated |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2676 | * data structures in dev_priv and obj. |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2677 | */ |
| 2678 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2679 | i915_gem_object_put_fence_reg(struct drm_i915_gem_object *obj, |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2680 | bool interruptible) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2681 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2682 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2683 | int ret; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2684 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2685 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2686 | return 0; |
| 2687 | |
Daniel Vetter | 10ae9bd | 2010-02-01 13:59:17 +0100 | [diff] [blame] | 2688 | /* If we've changed tiling, GTT-mappings of the object |
| 2689 | * need to re-fault to ensure that the correct fence register |
| 2690 | * setup is in place. |
| 2691 | */ |
| 2692 | i915_gem_release_mmap(obj); |
| 2693 | |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2694 | /* On the i915, GPU access to tiled buffers is via a fence, |
| 2695 | * therefore we must wait for any outstanding access to complete |
| 2696 | * before clearing the fence. |
| 2697 | */ |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2698 | if (obj->fenced_gpu_access) { |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2699 | ret = i915_gem_object_flush_gpu_write_domain(obj, NULL); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2700 | if (ret) |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2701 | return ret; |
| 2702 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2703 | obj->fenced_gpu_access = false; |
| 2704 | } |
| 2705 | |
| 2706 | if (obj->last_fenced_seqno) { |
| 2707 | ret = i915_do_wait_request(dev, |
| 2708 | obj->last_fenced_seqno, |
| 2709 | interruptible, |
| 2710 | obj->last_fenced_ring); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2711 | if (ret) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2712 | return ret; |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2713 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2714 | obj->last_fenced_seqno = false; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2715 | } |
| 2716 | |
Daniel Vetter | 4a72661 | 2010-02-01 13:59:16 +0100 | [diff] [blame] | 2717 | i915_gem_object_flush_gtt_write_domain(obj); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2718 | i915_gem_clear_fence_reg(obj); |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2719 | |
| 2720 | return 0; |
| 2721 | } |
| 2722 | |
| 2723 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2724 | * Finds free space in the GTT aperture and binds the object there. |
| 2725 | */ |
| 2726 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2727 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2728 | unsigned alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2729 | bool map_and_fenceable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2730 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2731 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2732 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2733 | struct drm_mm_node *free_space; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2734 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2735 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2736 | bool mappable, fenceable; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2737 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2738 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2739 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2740 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2741 | return -EINVAL; |
| 2742 | } |
| 2743 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2744 | fence_size = i915_gem_get_gtt_size(obj); |
| 2745 | fence_alignment = i915_gem_get_gtt_alignment(obj); |
| 2746 | unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2747 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2748 | if (alignment == 0) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2749 | alignment = map_and_fenceable ? fence_alignment : |
| 2750 | unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2751 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2752 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2753 | return -EINVAL; |
| 2754 | } |
| 2755 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2756 | size = map_and_fenceable ? fence_size : obj->base.size; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2757 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2758 | /* If the object is bigger than the entire aperture, reject it early |
| 2759 | * before evicting everything in a vain attempt to find space. |
| 2760 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2761 | if (obj->base.size > |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2762 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2763 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
| 2764 | return -E2BIG; |
| 2765 | } |
| 2766 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2767 | search_free: |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2768 | if (map_and_fenceable) |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2769 | free_space = |
| 2770 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2771 | size, alignment, 0, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2772 | dev_priv->mm.gtt_mappable_end, |
| 2773 | 0); |
| 2774 | else |
| 2775 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2776 | size, alignment, 0); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2777 | |
| 2778 | if (free_space != NULL) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2779 | if (map_and_fenceable) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2780 | obj->gtt_space = |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2781 | drm_mm_get_block_range_generic(free_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2782 | size, alignment, 0, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2783 | dev_priv->mm.gtt_mappable_end, |
| 2784 | 0); |
| 2785 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2786 | obj->gtt_space = |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2787 | drm_mm_get_block(free_space, size, alignment); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2788 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2789 | if (obj->gtt_space == NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2790 | /* If the gtt is empty and we're still having trouble |
| 2791 | * fitting our object in, we're out of memory. |
| 2792 | */ |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2793 | ret = i915_gem_evict_something(dev, size, alignment, |
| 2794 | map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2795 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2796 | return ret; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2797 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2798 | goto search_free; |
| 2799 | } |
| 2800 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2801 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2802 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2803 | drm_mm_put_block(obj->gtt_space); |
| 2804 | obj->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2805 | |
| 2806 | if (ret == -ENOMEM) { |
| 2807 | /* first try to clear up some space from the GTT */ |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2808 | ret = i915_gem_evict_something(dev, size, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2809 | alignment, |
| 2810 | map_and_fenceable); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2811 | if (ret) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2812 | /* now try to shrink everyone else */ |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2813 | if (gfpmask) { |
| 2814 | gfpmask = 0; |
| 2815 | goto search_free; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2816 | } |
| 2817 | |
| 2818 | return ret; |
| 2819 | } |
| 2820 | |
| 2821 | goto search_free; |
| 2822 | } |
| 2823 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2824 | return ret; |
| 2825 | } |
| 2826 | |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 2827 | ret = i915_gem_gtt_bind_object(obj); |
| 2828 | if (ret) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2829 | i915_gem_object_put_pages_gtt(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2830 | drm_mm_put_block(obj->gtt_space); |
| 2831 | obj->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2832 | |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2833 | ret = i915_gem_evict_something(dev, size, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2834 | alignment, map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2835 | if (ret) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2836 | return ret; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2837 | |
| 2838 | goto search_free; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2839 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2840 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2841 | obj->gtt_offset = obj->gtt_space->start; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 2842 | |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2843 | /* keep track of bounds object by adding it to the inactive list */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2844 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
| 2845 | i915_gem_info_add_gtt(dev_priv, obj); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2846 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2847 | /* Assert that the object is not currently in any GPU domain. As it |
| 2848 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2849 | * a GPU cache |
| 2850 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2851 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 2852 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2853 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2854 | trace_i915_gem_object_bind(obj, obj->gtt_offset, map_and_fenceable); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2855 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2856 | fenceable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2857 | obj->gtt_space->size == fence_size && |
| 2858 | (obj->gtt_space->start & (fence_alignment -1)) == 0; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2859 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2860 | mappable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2861 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2862 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2863 | obj->map_and_fenceable = mappable && fenceable; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2864 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2865 | return 0; |
| 2866 | } |
| 2867 | |
| 2868 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2869 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2870 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2871 | /* If we don't have a page list set up, then we're not pinned |
| 2872 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2873 | * again at bind time. |
| 2874 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2875 | if (obj->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2876 | return; |
| 2877 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2878 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 2879 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2880 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2881 | } |
| 2882 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2883 | /** Flushes any GPU write domain for the object if it's dirty. */ |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2884 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2885 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2886 | struct intel_ring_buffer *pipelined) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2887 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2888 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2889 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2890 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2891 | return 0; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2892 | |
| 2893 | /* Queue the GPU write cache flushing we need. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2894 | i915_gem_flush_ring(dev, obj->ring, 0, obj->base.write_domain); |
| 2895 | BUG_ON(obj->base.write_domain); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2896 | |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2897 | if (pipelined && pipelined == obj->ring) |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2898 | return 0; |
| 2899 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2900 | return i915_gem_object_wait_rendering(obj, true); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2901 | } |
| 2902 | |
| 2903 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 2904 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2905 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2906 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2907 | uint32_t old_write_domain; |
| 2908 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2909 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2910 | return; |
| 2911 | |
| 2912 | /* No actual flushing is required for the GTT write domain. Writes |
| 2913 | * to it immediately go to main memory as far as we know, so there's |
| 2914 | * no chipset flush. It also doesn't land in render cache. |
| 2915 | */ |
Chris Wilson | 4a684a4 | 2010-10-28 14:44:08 +0100 | [diff] [blame] | 2916 | i915_gem_release_mmap(obj); |
| 2917 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2918 | old_write_domain = obj->base.write_domain; |
| 2919 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2920 | |
| 2921 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2922 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2923 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2924 | } |
| 2925 | |
| 2926 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 2927 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2928 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2929 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2930 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2931 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2932 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2933 | return; |
| 2934 | |
| 2935 | i915_gem_clflush_object(obj); |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 2936 | intel_gtt_chipset_flush(); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2937 | old_write_domain = obj->base.write_domain; |
| 2938 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2939 | |
| 2940 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2941 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2942 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2943 | } |
| 2944 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2945 | /** |
| 2946 | * Moves a single object to the GTT read, and possibly write domain. |
| 2947 | * |
| 2948 | * This function returns when the move is complete, including waiting on |
| 2949 | * flushes to occur. |
| 2950 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2951 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2952 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, int write) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2953 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2954 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2955 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2956 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2957 | /* Not valid to be called on unbound objects. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2958 | if (obj->gtt_space == NULL) |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2959 | return -EINVAL; |
| 2960 | |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2961 | ret = i915_gem_object_flush_gpu_write_domain(obj, NULL); |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2962 | if (ret != 0) |
| 2963 | return ret; |
| 2964 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2965 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2966 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2967 | if (write) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2968 | ret = i915_gem_object_wait_rendering(obj, true); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2969 | if (ret) |
| 2970 | return ret; |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2971 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2972 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2973 | old_write_domain = obj->base.write_domain; |
| 2974 | old_read_domains = obj->base.read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2975 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2976 | /* It should now be out of any other write domains, and we can update |
| 2977 | * the domain values for our changes. |
| 2978 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2979 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2980 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2981 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2982 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 2983 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 2984 | obj->dirty = 1; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2985 | } |
| 2986 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2987 | trace_i915_gem_object_change_domain(obj, |
| 2988 | old_read_domains, |
| 2989 | old_write_domain); |
| 2990 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2991 | return 0; |
| 2992 | } |
| 2993 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2994 | /* |
| 2995 | * Prepare buffer for display plane. Use uninterruptible for possible flush |
| 2996 | * wait, as in modesetting process we're not supposed to be interrupted. |
| 2997 | */ |
| 2998 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2999 | i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3000 | struct intel_ring_buffer *pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3001 | { |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 3002 | uint32_t old_read_domains; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3003 | int ret; |
| 3004 | |
| 3005 | /* Not valid to be called on unbound objects. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3006 | if (obj->gtt_space == NULL) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3007 | return -EINVAL; |
| 3008 | |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3009 | ret = i915_gem_object_flush_gpu_write_domain(obj, pipelined); |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 3010 | if (ret) |
| 3011 | return ret; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3012 | |
Chris Wilson | ced270f | 2010-09-26 22:47:46 +0100 | [diff] [blame] | 3013 | /* Currently, we are always called from an non-interruptible context. */ |
| 3014 | if (!pipelined) { |
| 3015 | ret = i915_gem_object_wait_rendering(obj, false); |
| 3016 | if (ret) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3017 | return ret; |
| 3018 | } |
| 3019 | |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 3020 | i915_gem_object_flush_cpu_write_domain(obj); |
| 3021 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3022 | old_read_domains = obj->base.read_domains; |
| 3023 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3024 | |
| 3025 | trace_i915_gem_object_change_domain(obj, |
| 3026 | old_read_domains, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3027 | obj->base.write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3028 | |
| 3029 | return 0; |
| 3030 | } |
| 3031 | |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3032 | int |
| 3033 | i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj, |
| 3034 | bool interruptible) |
| 3035 | { |
| 3036 | if (!obj->active) |
| 3037 | return 0; |
| 3038 | |
| 3039 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3040 | i915_gem_flush_ring(obj->base.dev, obj->ring, |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3041 | 0, obj->base.write_domain); |
| 3042 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3043 | return i915_gem_object_wait_rendering(obj, interruptible); |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3044 | } |
| 3045 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3046 | /** |
| 3047 | * Moves a single object to the CPU read, and possibly write domain. |
| 3048 | * |
| 3049 | * This function returns when the move is complete, including waiting on |
| 3050 | * flushes to occur. |
| 3051 | */ |
| 3052 | static int |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3053 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3054 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3055 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3056 | int ret; |
| 3057 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 3058 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3059 | if (ret != 0) |
| 3060 | return ret; |
| 3061 | |
| 3062 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3063 | |
| 3064 | /* If we have a partially-valid cache of the object in the CPU, |
| 3065 | * finish invalidating it and free the per-page flags. |
| 3066 | */ |
| 3067 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
| 3068 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 3069 | if (write) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 3070 | ret = i915_gem_object_wait_rendering(obj, true); |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 3071 | if (ret) |
| 3072 | return ret; |
| 3073 | } |
| 3074 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3075 | old_write_domain = obj->base.write_domain; |
| 3076 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3077 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3078 | /* Flush the CPU cache if it's still invalid. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3079 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3080 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3081 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3082 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3083 | } |
| 3084 | |
| 3085 | /* It should now be out of any other write domains, and we can update |
| 3086 | * the domain values for our changes. |
| 3087 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3088 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3089 | |
| 3090 | /* If we're writing through the CPU, then the GPU read domains will |
| 3091 | * need to be invalidated at next use. |
| 3092 | */ |
| 3093 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3094 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3095 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3096 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3097 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3098 | trace_i915_gem_object_change_domain(obj, |
| 3099 | old_read_domains, |
| 3100 | old_write_domain); |
| 3101 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3102 | return 0; |
| 3103 | } |
| 3104 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3105 | /* |
| 3106 | * Set the next domain for the specified object. This |
| 3107 | * may not actually perform the necessary flushing/invaliding though, |
| 3108 | * as that may want to be batched with other set_domain operations |
| 3109 | * |
| 3110 | * This is (we hope) the only really tricky part of gem. The goal |
| 3111 | * is fairly simple -- track which caches hold bits of the object |
| 3112 | * and make sure they remain coherent. A few concrete examples may |
| 3113 | * help to explain how it works. For shorthand, we use the notation |
| 3114 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the |
| 3115 | * a pair of read and write domain masks. |
| 3116 | * |
| 3117 | * Case 1: the batch buffer |
| 3118 | * |
| 3119 | * 1. Allocated |
| 3120 | * 2. Written by CPU |
| 3121 | * 3. Mapped to GTT |
| 3122 | * 4. Read by GPU |
| 3123 | * 5. Unmapped from GTT |
| 3124 | * 6. Freed |
| 3125 | * |
| 3126 | * Let's take these a step at a time |
| 3127 | * |
| 3128 | * 1. Allocated |
| 3129 | * Pages allocated from the kernel may still have |
| 3130 | * cache contents, so we set them to (CPU, CPU) always. |
| 3131 | * 2. Written by CPU (using pwrite) |
| 3132 | * The pwrite function calls set_domain (CPU, CPU) and |
| 3133 | * this function does nothing (as nothing changes) |
| 3134 | * 3. Mapped by GTT |
| 3135 | * This function asserts that the object is not |
| 3136 | * currently in any GPU-based read or write domains |
| 3137 | * 4. Read by GPU |
| 3138 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). |
| 3139 | * As write_domain is zero, this function adds in the |
| 3140 | * current read domains (CPU+COMMAND, 0). |
| 3141 | * flush_domains is set to CPU. |
| 3142 | * invalidate_domains is set to COMMAND |
| 3143 | * clflush is run to get data out of the CPU caches |
| 3144 | * then i915_dev_set_domain calls i915_gem_flush to |
| 3145 | * emit an MI_FLUSH and drm_agp_chipset_flush |
| 3146 | * 5. Unmapped from GTT |
| 3147 | * i915_gem_object_unbind calls set_domain (CPU, CPU) |
| 3148 | * flush_domains and invalidate_domains end up both zero |
| 3149 | * so no flushing/invalidating happens |
| 3150 | * 6. Freed |
| 3151 | * yay, done |
| 3152 | * |
| 3153 | * Case 2: The shared render buffer |
| 3154 | * |
| 3155 | * 1. Allocated |
| 3156 | * 2. Mapped to GTT |
| 3157 | * 3. Read/written by GPU |
| 3158 | * 4. set_domain to (CPU,CPU) |
| 3159 | * 5. Read/written by CPU |
| 3160 | * 6. Read/written by GPU |
| 3161 | * |
| 3162 | * 1. Allocated |
| 3163 | * Same as last example, (CPU, CPU) |
| 3164 | * 2. Mapped to GTT |
| 3165 | * Nothing changes (assertions find that it is not in the GPU) |
| 3166 | * 3. Read/written by GPU |
| 3167 | * execbuffer calls set_domain (RENDER, RENDER) |
| 3168 | * flush_domains gets CPU |
| 3169 | * invalidate_domains gets GPU |
| 3170 | * clflush (obj) |
| 3171 | * MI_FLUSH and drm_agp_chipset_flush |
| 3172 | * 4. set_domain (CPU, CPU) |
| 3173 | * flush_domains gets GPU |
| 3174 | * invalidate_domains gets CPU |
| 3175 | * wait_rendering (obj) to make sure all drawing is complete. |
| 3176 | * This will include an MI_FLUSH to get the data from GPU |
| 3177 | * to memory |
| 3178 | * clflush (obj) to invalidate the CPU cache |
| 3179 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) |
| 3180 | * 5. Read/written by CPU |
| 3181 | * cache lines are loaded and dirtied |
| 3182 | * 6. Read written by GPU |
| 3183 | * Same as last GPU access |
| 3184 | * |
| 3185 | * Case 3: The constant buffer |
| 3186 | * |
| 3187 | * 1. Allocated |
| 3188 | * 2. Written by CPU |
| 3189 | * 3. Read by GPU |
| 3190 | * 4. Updated (written) by CPU again |
| 3191 | * 5. Read by GPU |
| 3192 | * |
| 3193 | * 1. Allocated |
| 3194 | * (CPU, CPU) |
| 3195 | * 2. Written by CPU |
| 3196 | * (CPU, CPU) |
| 3197 | * 3. Read by GPU |
| 3198 | * (CPU+RENDER, 0) |
| 3199 | * flush_domains = CPU |
| 3200 | * invalidate_domains = RENDER |
| 3201 | * clflush (obj) |
| 3202 | * MI_FLUSH |
| 3203 | * drm_agp_chipset_flush |
| 3204 | * 4. Updated (written) by CPU again |
| 3205 | * (CPU, CPU) |
| 3206 | * flush_domains = 0 (no previous write domain) |
| 3207 | * invalidate_domains = 0 (no new read domains) |
| 3208 | * 5. Read by GPU |
| 3209 | * (CPU+RENDER, 0) |
| 3210 | * flush_domains = CPU |
| 3211 | * invalidate_domains = RENDER |
| 3212 | * clflush (obj) |
| 3213 | * MI_FLUSH |
| 3214 | * drm_agp_chipset_flush |
| 3215 | */ |
Keith Packard | c0d9082 | 2008-11-20 23:11:08 -0800 | [diff] [blame] | 3216 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3217 | i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj, |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 3218 | struct intel_ring_buffer *ring, |
| 3219 | struct change_domains *cd) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3220 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3221 | uint32_t invalidate_domains = 0, flush_domains = 0; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3222 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3223 | /* |
| 3224 | * If the object isn't moving to a new write domain, |
| 3225 | * let the object stay in multiple read domains |
| 3226 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3227 | if (obj->base.pending_write_domain == 0) |
| 3228 | obj->base.pending_read_domains |= obj->base.read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3229 | |
| 3230 | /* |
| 3231 | * Flush the current write domain if |
| 3232 | * the new read domains don't match. Invalidate |
| 3233 | * any read domains which differ from the old |
| 3234 | * write domain |
| 3235 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3236 | if (obj->base.write_domain && |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 3237 | (((obj->base.write_domain != obj->base.pending_read_domains || |
| 3238 | obj->ring != ring)) || |
| 3239 | (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3240 | flush_domains |= obj->base.write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3241 | invalidate_domains |= |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3242 | obj->base.pending_read_domains & ~obj->base.write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3243 | } |
| 3244 | /* |
| 3245 | * Invalidate any read caches which may have |
| 3246 | * stale data. That is, any new read domains. |
| 3247 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3248 | invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains; |
Chris Wilson | 3d2a812 | 2010-09-29 11:39:53 +0100 | [diff] [blame] | 3249 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3250 | i915_gem_clflush_object(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3251 | |
Chris Wilson | 4a684a4 | 2010-10-28 14:44:08 +0100 | [diff] [blame] | 3252 | /* blow away mappings if mapped through GTT */ |
| 3253 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_GTT) |
| 3254 | i915_gem_release_mmap(obj); |
| 3255 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3256 | /* The actual obj->write_domain will be updated with |
| 3257 | * pending_write_domain after we emit the accumulated flush for all |
| 3258 | * of our domain changes in execbuffers (which clears objects' |
| 3259 | * write_domains). So if we have a current write domain that we |
| 3260 | * aren't changing, set pending_write_domain to that. |
| 3261 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3262 | if (flush_domains == 0 && obj->base.pending_write_domain == 0) |
| 3263 | obj->base.pending_write_domain = obj->base.write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3264 | |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 3265 | cd->invalidate_domains |= invalidate_domains; |
| 3266 | cd->flush_domains |= flush_domains; |
Chris Wilson | b665145 | 2010-10-23 10:15:06 +0100 | [diff] [blame] | 3267 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3268 | cd->flush_rings |= obj->ring->id; |
Chris Wilson | b665145 | 2010-10-23 10:15:06 +0100 | [diff] [blame] | 3269 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 3270 | cd->flush_rings |= ring->id; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3271 | } |
| 3272 | |
| 3273 | /** |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3274 | * Moves the object from a partially CPU read to a full one. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3275 | * |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3276 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
| 3277 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). |
| 3278 | */ |
| 3279 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3280 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3281 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3282 | if (!obj->page_cpu_valid) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3283 | return; |
| 3284 | |
| 3285 | /* If we're partially in the CPU read domain, finish moving it in. |
| 3286 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3287 | if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3288 | int i; |
| 3289 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3290 | for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) { |
| 3291 | if (obj->page_cpu_valid[i]) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3292 | continue; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3293 | drm_clflush_pages(obj->pages + i, 1); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3294 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3295 | } |
| 3296 | |
| 3297 | /* Free the page_cpu_valid mappings which are now stale, whether |
| 3298 | * or not we've got I915_GEM_DOMAIN_CPU. |
| 3299 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3300 | kfree(obj->page_cpu_valid); |
| 3301 | obj->page_cpu_valid = NULL; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3302 | } |
| 3303 | |
| 3304 | /** |
| 3305 | * Set the CPU read domain on a range of the object. |
| 3306 | * |
| 3307 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's |
| 3308 | * not entirely valid. The page_cpu_valid member of the object flags which |
| 3309 | * pages have been flushed, and will be respected by |
| 3310 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping |
| 3311 | * of the whole object. |
| 3312 | * |
| 3313 | * This function returns when the move is complete, including waiting on |
| 3314 | * flushes to occur. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3315 | */ |
| 3316 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3317 | i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3318 | uint64_t offset, uint64_t size) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3319 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3320 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3321 | int i, ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3322 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3323 | if (offset == 0 && size == obj->base.size) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3324 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
| 3325 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 3326 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3327 | if (ret != 0) |
| 3328 | return ret; |
| 3329 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3330 | |
| 3331 | /* If we're already fully in the CPU read domain, we're done. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3332 | if (obj->page_cpu_valid == NULL && |
| 3333 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3334 | return 0; |
| 3335 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3336 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
| 3337 | * newly adding I915_GEM_DOMAIN_CPU |
| 3338 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3339 | if (obj->page_cpu_valid == NULL) { |
| 3340 | obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE, |
| 3341 | GFP_KERNEL); |
| 3342 | if (obj->page_cpu_valid == NULL) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3343 | return -ENOMEM; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3344 | } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 3345 | memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3346 | |
| 3347 | /* Flush the cache on any pages that are still invalid from the CPU's |
| 3348 | * perspective. |
| 3349 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3350 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
| 3351 | i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3352 | if (obj->page_cpu_valid[i]) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3353 | continue; |
| 3354 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3355 | drm_clflush_pages(obj->pages + i, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3356 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3357 | obj->page_cpu_valid[i] = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3358 | } |
| 3359 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3360 | /* It should now be out of any other write domains, and we can update |
| 3361 | * the domain values for our changes. |
| 3362 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3363 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3364 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3365 | old_read_domains = obj->base.read_domains; |
| 3366 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3367 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3368 | trace_i915_gem_object_change_domain(obj, |
| 3369 | old_read_domains, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3370 | obj->base.write_domain); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3371 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3372 | return 0; |
| 3373 | } |
| 3374 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3375 | static int |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3376 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, |
| 3377 | struct drm_file *file_priv, |
| 3378 | struct drm_i915_gem_exec_object2 *entry, |
| 3379 | struct drm_i915_gem_relocation_entry *reloc) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3380 | { |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3381 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3382 | struct drm_gem_object *target_obj; |
| 3383 | uint32_t target_offset; |
| 3384 | int ret = -EINVAL; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3385 | |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3386 | target_obj = drm_gem_object_lookup(dev, file_priv, |
| 3387 | reloc->target_handle); |
| 3388 | if (target_obj == NULL) |
| 3389 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3390 | |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3391 | target_offset = to_intel_bo(target_obj)->gtt_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3392 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3393 | #if WATCH_RELOC |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3394 | DRM_INFO("%s: obj %p offset %08x target %d " |
| 3395 | "read %08x write %08x gtt %08x " |
| 3396 | "presumed %08x delta %08x\n", |
| 3397 | __func__, |
| 3398 | obj, |
| 3399 | (int) reloc->offset, |
| 3400 | (int) reloc->target_handle, |
| 3401 | (int) reloc->read_domains, |
| 3402 | (int) reloc->write_domain, |
| 3403 | (int) target_offset, |
| 3404 | (int) reloc->presumed_offset, |
| 3405 | reloc->delta); |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3406 | #endif |
| 3407 | |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3408 | /* The target buffer should have appeared before us in the |
| 3409 | * exec_object list, so it should have a GTT space bound by now. |
| 3410 | */ |
| 3411 | if (target_offset == 0) { |
| 3412 | DRM_ERROR("No GTT space found for object %d\n", |
| 3413 | reloc->target_handle); |
| 3414 | goto err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3415 | } |
| 3416 | |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3417 | /* Validate that the target is in a valid r/w GPU domain */ |
| 3418 | if (reloc->write_domain & (reloc->write_domain - 1)) { |
| 3419 | DRM_ERROR("reloc with multiple write domains: " |
| 3420 | "obj %p target %d offset %d " |
| 3421 | "read %08x write %08x", |
| 3422 | obj, reloc->target_handle, |
| 3423 | (int) reloc->offset, |
| 3424 | reloc->read_domains, |
| 3425 | reloc->write_domain); |
| 3426 | goto err; |
| 3427 | } |
| 3428 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || |
| 3429 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { |
| 3430 | DRM_ERROR("reloc with read/write CPU domains: " |
| 3431 | "obj %p target %d offset %d " |
| 3432 | "read %08x write %08x", |
| 3433 | obj, reloc->target_handle, |
| 3434 | (int) reloc->offset, |
| 3435 | reloc->read_domains, |
| 3436 | reloc->write_domain); |
| 3437 | goto err; |
| 3438 | } |
| 3439 | if (reloc->write_domain && target_obj->pending_write_domain && |
| 3440 | reloc->write_domain != target_obj->pending_write_domain) { |
| 3441 | DRM_ERROR("Write domain conflict: " |
| 3442 | "obj %p target %d offset %d " |
| 3443 | "new %08x old %08x\n", |
| 3444 | obj, reloc->target_handle, |
| 3445 | (int) reloc->offset, |
| 3446 | reloc->write_domain, |
| 3447 | target_obj->pending_write_domain); |
| 3448 | goto err; |
| 3449 | } |
| 3450 | |
| 3451 | target_obj->pending_read_domains |= reloc->read_domains; |
| 3452 | target_obj->pending_write_domain |= reloc->write_domain; |
| 3453 | |
| 3454 | /* If the relocation already has the right value in it, no |
| 3455 | * more work needs to be done. |
| 3456 | */ |
| 3457 | if (target_offset == reloc->presumed_offset) |
| 3458 | goto out; |
| 3459 | |
| 3460 | /* Check that the relocation address is valid... */ |
| 3461 | if (reloc->offset > obj->base.size - 4) { |
| 3462 | DRM_ERROR("Relocation beyond object bounds: " |
| 3463 | "obj %p target %d offset %d size %d.\n", |
| 3464 | obj, reloc->target_handle, |
| 3465 | (int) reloc->offset, |
| 3466 | (int) obj->base.size); |
| 3467 | goto err; |
| 3468 | } |
| 3469 | if (reloc->offset & 3) { |
| 3470 | DRM_ERROR("Relocation not 4-byte aligned: " |
| 3471 | "obj %p target %d offset %d.\n", |
| 3472 | obj, reloc->target_handle, |
| 3473 | (int) reloc->offset); |
| 3474 | goto err; |
| 3475 | } |
| 3476 | |
| 3477 | /* and points to somewhere within the target object. */ |
| 3478 | if (reloc->delta >= target_obj->size) { |
| 3479 | DRM_ERROR("Relocation beyond target object bounds: " |
| 3480 | "obj %p target %d delta %d size %d.\n", |
| 3481 | obj, reloc->target_handle, |
| 3482 | (int) reloc->delta, |
| 3483 | (int) target_obj->size); |
| 3484 | goto err; |
| 3485 | } |
| 3486 | |
| 3487 | reloc->delta += target_offset; |
| 3488 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { |
| 3489 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; |
| 3490 | char *vaddr; |
| 3491 | |
| 3492 | vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]); |
| 3493 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; |
| 3494 | kunmap_atomic(vaddr); |
| 3495 | } else { |
| 3496 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3497 | uint32_t __iomem *reloc_entry; |
| 3498 | void __iomem *reloc_page; |
| 3499 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3500 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3501 | if (ret) |
| 3502 | goto err; |
| 3503 | |
| 3504 | /* Map the page containing the relocation we're going to perform. */ |
| 3505 | reloc->offset += obj->gtt_offset; |
| 3506 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
| 3507 | reloc->offset & PAGE_MASK); |
| 3508 | reloc_entry = (uint32_t __iomem *) |
| 3509 | (reloc_page + (reloc->offset & ~PAGE_MASK)); |
| 3510 | iowrite32(reloc->delta, reloc_entry); |
| 3511 | io_mapping_unmap_atomic(reloc_page); |
| 3512 | } |
| 3513 | |
| 3514 | /* and update the user's relocation entry */ |
| 3515 | reloc->presumed_offset = target_offset; |
| 3516 | |
| 3517 | out: |
| 3518 | ret = 0; |
| 3519 | err: |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3520 | drm_gem_object_unreference(target_obj); |
| 3521 | return ret; |
| 3522 | } |
| 3523 | |
| 3524 | static int |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3525 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, |
| 3526 | struct drm_file *file_priv, |
| 3527 | struct drm_i915_gem_exec_object2 *entry) |
| 3528 | { |
| 3529 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
| 3530 | int i, ret; |
| 3531 | |
| 3532 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
| 3533 | for (i = 0; i < entry->relocation_count; i++) { |
| 3534 | struct drm_i915_gem_relocation_entry reloc; |
| 3535 | |
| 3536 | if (__copy_from_user_inatomic(&reloc, |
| 3537 | user_relocs+i, |
| 3538 | sizeof(reloc))) |
| 3539 | return -EFAULT; |
| 3540 | |
| 3541 | ret = i915_gem_execbuffer_relocate_entry(obj, file_priv, entry, &reloc); |
| 3542 | if (ret) |
| 3543 | return ret; |
| 3544 | |
| 3545 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, |
| 3546 | &reloc.presumed_offset, |
| 3547 | sizeof(reloc.presumed_offset))) |
| 3548 | return -EFAULT; |
| 3549 | } |
| 3550 | |
| 3551 | return 0; |
| 3552 | } |
| 3553 | |
| 3554 | static int |
| 3555 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, |
| 3556 | struct drm_file *file_priv, |
| 3557 | struct drm_i915_gem_exec_object2 *entry, |
| 3558 | struct drm_i915_gem_relocation_entry *relocs) |
| 3559 | { |
| 3560 | int i, ret; |
| 3561 | |
| 3562 | for (i = 0; i < entry->relocation_count; i++) { |
| 3563 | ret = i915_gem_execbuffer_relocate_entry(obj, file_priv, entry, &relocs[i]); |
| 3564 | if (ret) |
| 3565 | return ret; |
| 3566 | } |
| 3567 | |
| 3568 | return 0; |
| 3569 | } |
| 3570 | |
| 3571 | static int |
| 3572 | i915_gem_execbuffer_relocate(struct drm_device *dev, |
| 3573 | struct drm_file *file, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3574 | struct drm_i915_gem_object **object_list, |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3575 | struct drm_i915_gem_exec_object2 *exec_list, |
| 3576 | int count) |
| 3577 | { |
| 3578 | int i, ret; |
| 3579 | |
| 3580 | for (i = 0; i < count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3581 | struct drm_i915_gem_object *obj = object_list[i]; |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3582 | obj->base.pending_read_domains = 0; |
| 3583 | obj->base.pending_write_domain = 0; |
| 3584 | ret = i915_gem_execbuffer_relocate_object(obj, file, |
| 3585 | &exec_list[i]); |
| 3586 | if (ret) |
| 3587 | return ret; |
| 3588 | } |
| 3589 | |
| 3590 | return 0; |
| 3591 | } |
| 3592 | |
| 3593 | static int |
| 3594 | i915_gem_execbuffer_reserve(struct drm_device *dev, |
| 3595 | struct drm_file *file, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3596 | struct drm_i915_gem_object **object_list, |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3597 | struct drm_i915_gem_exec_object2 *exec_list, |
| 3598 | int count) |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3599 | { |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3600 | int ret, i, retry; |
| 3601 | |
Chris Wilson | a7a09ae | 2010-11-12 13:49:09 +0000 | [diff] [blame] | 3602 | /* Attempt to pin all of the buffers into the GTT. |
| 3603 | * This is done in 3 phases: |
| 3604 | * |
| 3605 | * 1a. Unbind all objects that do not match the GTT constraints for |
| 3606 | * the execbuffer (fenceable, mappable, alignment etc). |
| 3607 | * 1b. Increment pin count for already bound objects. |
| 3608 | * 2. Bind new objects. |
| 3609 | * 3. Decrement pin count. |
| 3610 | * |
| 3611 | * This avoid unnecessary unbinding of later objects in order to makr |
| 3612 | * room for the earlier objects *unless* we need to defragment. |
| 3613 | */ |
Chris Wilson | 5eac3ab | 2010-10-31 08:49:47 +0000 | [diff] [blame] | 3614 | retry = 0; |
| 3615 | do { |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3616 | ret = 0; |
Chris Wilson | a7a09ae | 2010-11-12 13:49:09 +0000 | [diff] [blame] | 3617 | |
| 3618 | /* Unbind any ill-fitting objects or pin. */ |
| 3619 | for (i = 0; i < count; i++) { |
| 3620 | struct drm_i915_gem_object *obj = object_list[i]; |
| 3621 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; |
| 3622 | bool need_fence, need_mappable; |
| 3623 | |
| 3624 | if (!obj->gtt_space) |
| 3625 | continue; |
| 3626 | |
| 3627 | need_fence = |
| 3628 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
| 3629 | obj->tiling_mode != I915_TILING_NONE; |
| 3630 | need_mappable = |
| 3631 | entry->relocation_count ? true : need_fence; |
| 3632 | |
| 3633 | if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || |
| 3634 | (need_mappable && !obj->map_and_fenceable)) |
| 3635 | ret = i915_gem_object_unbind(obj); |
| 3636 | else |
| 3637 | ret = i915_gem_object_pin(obj, |
| 3638 | entry->alignment, |
| 3639 | need_mappable); |
| 3640 | if (ret) { |
| 3641 | count = i; |
| 3642 | goto err; |
| 3643 | } |
| 3644 | } |
| 3645 | |
| 3646 | /* Bind fresh objects */ |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3647 | for (i = 0; i < count; i++) { |
| 3648 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3649 | struct drm_i915_gem_object *obj = object_list[i]; |
Chris Wilson | a7a09ae | 2010-11-12 13:49:09 +0000 | [diff] [blame] | 3650 | bool need_fence; |
| 3651 | |
| 3652 | need_fence = |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3653 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
| 3654 | obj->tiling_mode != I915_TILING_NONE; |
| 3655 | |
Chris Wilson | a7a09ae | 2010-11-12 13:49:09 +0000 | [diff] [blame] | 3656 | if (!obj->gtt_space) { |
| 3657 | bool need_mappable = |
| 3658 | entry->relocation_count ? true : need_fence; |
Daniel Vetter | 16e809a | 2010-09-16 19:37:04 +0200 | [diff] [blame] | 3659 | |
Chris Wilson | a7a09ae | 2010-11-12 13:49:09 +0000 | [diff] [blame] | 3660 | ret = i915_gem_object_pin(obj, |
| 3661 | entry->alignment, |
| 3662 | need_mappable); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3663 | if (ret) |
| 3664 | break; |
| 3665 | } |
| 3666 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3667 | if (need_fence) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3668 | ret = i915_gem_object_get_fence_reg(obj, true); |
Chris Wilson | a7a09ae | 2010-11-12 13:49:09 +0000 | [diff] [blame] | 3669 | if (ret) |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3670 | break; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3671 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 3672 | obj->pending_fenced_gpu_access = true; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3673 | } |
| 3674 | |
| 3675 | entry->offset = obj->gtt_offset; |
| 3676 | } |
| 3677 | |
Chris Wilson | a7a09ae | 2010-11-12 13:49:09 +0000 | [diff] [blame] | 3678 | err: /* Decrement pin count for bound objects */ |
| 3679 | for (i = 0; i < count; i++) { |
| 3680 | struct drm_i915_gem_object *obj = object_list[i]; |
| 3681 | if (obj->gtt_space) |
| 3682 | i915_gem_object_unpin(obj); |
| 3683 | } |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3684 | |
Chris Wilson | 5eac3ab | 2010-10-31 08:49:47 +0000 | [diff] [blame] | 3685 | if (ret != -ENOSPC || retry > 1) |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3686 | return ret; |
| 3687 | |
Chris Wilson | 5eac3ab | 2010-10-31 08:49:47 +0000 | [diff] [blame] | 3688 | /* First attempt, just clear anything that is purgeable. |
| 3689 | * Second attempt, clear the entire GTT. |
| 3690 | */ |
| 3691 | ret = i915_gem_evict_everything(dev, retry == 0); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3692 | if (ret) |
| 3693 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3694 | |
Chris Wilson | 5eac3ab | 2010-10-31 08:49:47 +0000 | [diff] [blame] | 3695 | retry++; |
| 3696 | } while (1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3697 | } |
| 3698 | |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3699 | static int |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3700 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, |
| 3701 | struct drm_file *file, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3702 | struct drm_i915_gem_object **object_list, |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3703 | struct drm_i915_gem_exec_object2 *exec_list, |
| 3704 | int count) |
| 3705 | { |
| 3706 | struct drm_i915_gem_relocation_entry *reloc; |
| 3707 | int i, total, ret; |
| 3708 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3709 | for (i = 0; i < count; i++) |
| 3710 | object_list[i]->in_execbuffer = false; |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3711 | |
| 3712 | mutex_unlock(&dev->struct_mutex); |
| 3713 | |
| 3714 | total = 0; |
| 3715 | for (i = 0; i < count; i++) |
| 3716 | total += exec_list[i].relocation_count; |
| 3717 | |
| 3718 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
| 3719 | if (reloc == NULL) { |
| 3720 | mutex_lock(&dev->struct_mutex); |
| 3721 | return -ENOMEM; |
| 3722 | } |
| 3723 | |
| 3724 | total = 0; |
| 3725 | for (i = 0; i < count; i++) { |
| 3726 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
| 3727 | |
| 3728 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; |
| 3729 | |
| 3730 | if (copy_from_user(reloc+total, user_relocs, |
| 3731 | exec_list[i].relocation_count * |
| 3732 | sizeof(*reloc))) { |
| 3733 | ret = -EFAULT; |
| 3734 | mutex_lock(&dev->struct_mutex); |
| 3735 | goto err; |
| 3736 | } |
| 3737 | |
| 3738 | total += exec_list[i].relocation_count; |
| 3739 | } |
| 3740 | |
| 3741 | ret = i915_mutex_lock_interruptible(dev); |
| 3742 | if (ret) { |
| 3743 | mutex_lock(&dev->struct_mutex); |
| 3744 | goto err; |
| 3745 | } |
| 3746 | |
| 3747 | ret = i915_gem_execbuffer_reserve(dev, file, |
| 3748 | object_list, exec_list, |
| 3749 | count); |
| 3750 | if (ret) |
| 3751 | goto err; |
| 3752 | |
| 3753 | total = 0; |
| 3754 | for (i = 0; i < count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3755 | struct drm_i915_gem_object *obj = object_list[i]; |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3756 | obj->base.pending_read_domains = 0; |
| 3757 | obj->base.pending_write_domain = 0; |
| 3758 | ret = i915_gem_execbuffer_relocate_object_slow(obj, file, |
| 3759 | &exec_list[i], |
| 3760 | reloc + total); |
| 3761 | if (ret) |
| 3762 | goto err; |
| 3763 | |
| 3764 | total += exec_list[i].relocation_count; |
| 3765 | } |
| 3766 | |
| 3767 | /* Leave the user relocations as are, this is the painfully slow path, |
| 3768 | * and we want to avoid the complication of dropping the lock whilst |
| 3769 | * having buffers reserved in the aperture and so causing spurious |
| 3770 | * ENOSPC for random operations. |
| 3771 | */ |
| 3772 | |
| 3773 | err: |
| 3774 | drm_free_large(reloc); |
| 3775 | return ret; |
| 3776 | } |
| 3777 | |
| 3778 | static int |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3779 | i915_gem_execbuffer_move_to_gpu(struct drm_device *dev, |
| 3780 | struct drm_file *file, |
| 3781 | struct intel_ring_buffer *ring, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3782 | struct drm_i915_gem_object **objects, |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3783 | int count) |
| 3784 | { |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 3785 | struct change_domains cd; |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3786 | int ret, i; |
| 3787 | |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 3788 | cd.invalidate_domains = 0; |
| 3789 | cd.flush_domains = 0; |
| 3790 | cd.flush_rings = 0; |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3791 | for (i = 0; i < count; i++) |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 3792 | i915_gem_object_set_to_gpu_domain(objects[i], ring, &cd); |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3793 | |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 3794 | if (cd.invalidate_domains | cd.flush_domains) { |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3795 | #if WATCH_EXEC |
| 3796 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", |
| 3797 | __func__, |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 3798 | cd.invalidate_domains, |
| 3799 | cd.flush_domains); |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3800 | #endif |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3801 | i915_gem_flush(dev, |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 3802 | cd.invalidate_domains, |
| 3803 | cd.flush_domains, |
| 3804 | cd.flush_rings); |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3805 | } |
| 3806 | |
| 3807 | for (i = 0; i < count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3808 | struct drm_i915_gem_object *obj = objects[i]; |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3809 | /* XXX replace with semaphores */ |
| 3810 | if (obj->ring && ring != obj->ring) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3811 | ret = i915_gem_object_wait_rendering(obj, true); |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3812 | if (ret) |
| 3813 | return ret; |
| 3814 | } |
| 3815 | } |
| 3816 | |
| 3817 | return 0; |
| 3818 | } |
| 3819 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3820 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3821 | * emitted over 20 msec ago. |
| 3822 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3823 | * Note that if we were to use the current jiffies each time around the loop, |
| 3824 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3825 | * render a frame was over 20ms. |
| 3826 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3827 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3828 | * relatively low latency when blocking on a particular request to finish. |
| 3829 | */ |
| 3830 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3831 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3832 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3833 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3834 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3835 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3836 | struct drm_i915_gem_request *request; |
| 3837 | struct intel_ring_buffer *ring = NULL; |
| 3838 | u32 seqno = 0; |
| 3839 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3840 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3841 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3842 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3843 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3844 | break; |
| 3845 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3846 | ring = request->ring; |
| 3847 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3848 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3849 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3850 | |
| 3851 | if (seqno == 0) |
| 3852 | return 0; |
| 3853 | |
| 3854 | ret = 0; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3855 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3856 | /* And wait for the seqno passing without holding any locks and |
| 3857 | * causing extra latency for others. This is safe as the irq |
| 3858 | * generation is designed to be run atomically and so is |
| 3859 | * lockless. |
| 3860 | */ |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3861 | ring->user_irq_get(ring); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3862 | ret = wait_event_interruptible(ring->irq_queue, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3863 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3864 | || atomic_read(&dev_priv->mm.wedged)); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3865 | ring->user_irq_put(ring); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3866 | |
| 3867 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
| 3868 | ret = -EIO; |
| 3869 | } |
| 3870 | |
| 3871 | if (ret == 0) |
| 3872 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3873 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3874 | return ret; |
| 3875 | } |
| 3876 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3877 | static int |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3878 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec, |
| 3879 | uint64_t exec_offset) |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3880 | { |
| 3881 | uint32_t exec_start, exec_len; |
| 3882 | |
| 3883 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
| 3884 | exec_len = (uint32_t) exec->batch_len; |
| 3885 | |
| 3886 | if ((exec_start | exec_len) & 0x7) |
| 3887 | return -EINVAL; |
| 3888 | |
| 3889 | if (!exec_start) |
| 3890 | return -EINVAL; |
| 3891 | |
| 3892 | return 0; |
| 3893 | } |
| 3894 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3895 | static int |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3896 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
| 3897 | int count) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3898 | { |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3899 | int i; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3900 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3901 | for (i = 0; i < count; i++) { |
| 3902 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; |
Chris Wilson | d1d7883 | 2010-11-21 09:23:48 +0000 | [diff] [blame] | 3903 | int length; /* limited by fault_in_pages_readable() */ |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3904 | |
Chris Wilson | d1d7883 | 2010-11-21 09:23:48 +0000 | [diff] [blame] | 3905 | /* First check for malicious input causing overflow */ |
| 3906 | if (exec[i].relocation_count > |
| 3907 | INT_MAX / sizeof(struct drm_i915_gem_relocation_entry)) |
| 3908 | return -EINVAL; |
| 3909 | |
| 3910 | length = exec[i].relocation_count * |
| 3911 | sizeof(struct drm_i915_gem_relocation_entry); |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3912 | if (!access_ok(VERIFY_READ, ptr, length)) |
| 3913 | return -EFAULT; |
| 3914 | |
Chris Wilson | b5dc608 | 2010-10-20 20:59:57 +0100 | [diff] [blame] | 3915 | /* we may also need to update the presumed offsets */ |
| 3916 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
| 3917 | return -EFAULT; |
| 3918 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3919 | if (fault_in_pages_readable(ptr, length)) |
| 3920 | return -EFAULT; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3921 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3922 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3923 | return 0; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3924 | } |
| 3925 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3926 | static int |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3927 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3928 | struct drm_file *file, |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3929 | struct drm_i915_gem_execbuffer2 *args, |
| 3930 | struct drm_i915_gem_exec_object2 *exec_list) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3931 | { |
| 3932 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3933 | struct drm_i915_gem_object **object_list = NULL; |
| 3934 | struct drm_i915_gem_object *batch_obj; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3935 | struct drm_clip_rect *cliprects = NULL; |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3936 | struct drm_i915_gem_request *request = NULL; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3937 | int ret, i, flips; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3938 | uint64_t exec_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3939 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3940 | struct intel_ring_buffer *ring = NULL; |
| 3941 | |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3942 | ret = i915_gem_check_is_wedged(dev); |
| 3943 | if (ret) |
| 3944 | return ret; |
| 3945 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3946 | ret = validate_exec_list(exec_list, args->buffer_count); |
| 3947 | if (ret) |
| 3948 | return ret; |
| 3949 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3950 | #if WATCH_EXEC |
| 3951 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3952 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3953 | #endif |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3954 | switch (args->flags & I915_EXEC_RING_MASK) { |
| 3955 | case I915_EXEC_DEFAULT: |
| 3956 | case I915_EXEC_RENDER: |
| 3957 | ring = &dev_priv->render_ring; |
| 3958 | break; |
| 3959 | case I915_EXEC_BSD: |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3960 | if (!HAS_BSD(dev)) { |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3961 | DRM_ERROR("execbuf with invalid ring (BSD)\n"); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3962 | return -EINVAL; |
| 3963 | } |
| 3964 | ring = &dev_priv->bsd_ring; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3965 | break; |
| 3966 | case I915_EXEC_BLT: |
| 3967 | if (!HAS_BLT(dev)) { |
| 3968 | DRM_ERROR("execbuf with invalid ring (BLT)\n"); |
| 3969 | return -EINVAL; |
| 3970 | } |
| 3971 | ring = &dev_priv->blt_ring; |
| 3972 | break; |
| 3973 | default: |
| 3974 | DRM_ERROR("execbuf with unknown ring: %d\n", |
| 3975 | (int)(args->flags & I915_EXEC_RING_MASK)); |
| 3976 | return -EINVAL; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3977 | } |
| 3978 | |
Eric Anholt | 4f481ed | 2008-09-10 14:22:49 -0700 | [diff] [blame] | 3979 | if (args->buffer_count < 1) { |
| 3980 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 3981 | return -EINVAL; |
| 3982 | } |
Eric Anholt | c8e0f93 | 2009-11-22 03:49:37 +0100 | [diff] [blame] | 3983 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3984 | if (object_list == NULL) { |
| 3985 | DRM_ERROR("Failed to allocate object list for %d buffers\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3986 | args->buffer_count); |
| 3987 | ret = -ENOMEM; |
| 3988 | goto pre_mutex_err; |
| 3989 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3990 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3991 | if (args->num_cliprects != 0) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3992 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
| 3993 | GFP_KERNEL); |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3994 | if (cliprects == NULL) { |
| 3995 | ret = -ENOMEM; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3996 | goto pre_mutex_err; |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3997 | } |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3998 | |
| 3999 | ret = copy_from_user(cliprects, |
| 4000 | (struct drm_clip_rect __user *) |
| 4001 | (uintptr_t) args->cliprects_ptr, |
| 4002 | sizeof(*cliprects) * args->num_cliprects); |
| 4003 | if (ret != 0) { |
| 4004 | DRM_ERROR("copy %d cliprects failed: %d\n", |
| 4005 | args->num_cliprects, ret); |
Dan Carpenter | c877cdc | 2010-06-23 19:03:01 +0200 | [diff] [blame] | 4006 | ret = -EFAULT; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 4007 | goto pre_mutex_err; |
| 4008 | } |
| 4009 | } |
| 4010 | |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 4011 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 4012 | if (request == NULL) { |
| 4013 | ret = -ENOMEM; |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 4014 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4015 | } |
| 4016 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4017 | ret = i915_mutex_lock_interruptible(dev); |
| 4018 | if (ret) |
| 4019 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4020 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4021 | if (dev_priv->mm.suspended) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4022 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 4023 | ret = -EBUSY; |
| 4024 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4025 | } |
| 4026 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 4027 | /* Look up object handles */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4028 | for (i = 0; i < args->buffer_count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4029 | struct drm_i915_gem_object *obj; |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 4030 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4031 | obj = to_intel_bo (drm_gem_object_lookup(dev, file, |
| 4032 | exec_list[i].handle)); |
| 4033 | if (obj == NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4034 | DRM_ERROR("Invalid object handle %d at index %d\n", |
| 4035 | exec_list[i].handle, i); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 4036 | /* prevent error path from reading uninitialized data */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4037 | args->buffer_count = i; |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 4038 | ret = -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4039 | goto err; |
| 4040 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4041 | object_list[i] = obj; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 4042 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4043 | if (obj->in_execbuffer) { |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 4044 | DRM_ERROR("Object %p appears more than once in object list\n", |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4045 | obj); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 4046 | /* prevent error path from reading uninitialized data */ |
| 4047 | args->buffer_count = i + 1; |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 4048 | ret = -EINVAL; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 4049 | goto err; |
| 4050 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4051 | obj->in_execbuffer = true; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 4052 | obj->pending_fenced_gpu_access = false; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4053 | } |
| 4054 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 4055 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 4056 | ret = i915_gem_execbuffer_reserve(dev, file, |
| 4057 | object_list, exec_list, |
| 4058 | args->buffer_count); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 4059 | if (ret) |
| 4060 | goto err; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 4061 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 4062 | /* The objects are in their final locations, apply the relocations. */ |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 4063 | ret = i915_gem_execbuffer_relocate(dev, file, |
| 4064 | object_list, exec_list, |
| 4065 | args->buffer_count); |
| 4066 | if (ret) { |
| 4067 | if (ret == -EFAULT) { |
| 4068 | ret = i915_gem_execbuffer_relocate_slow(dev, file, |
| 4069 | object_list, |
| 4070 | exec_list, |
| 4071 | args->buffer_count); |
| 4072 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 4073 | } |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 4074 | if (ret) |
| 4075 | goto err; |
| 4076 | } |
| 4077 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4078 | /* Set the pending read domains for the batch buffer to COMMAND */ |
| 4079 | batch_obj = object_list[args->buffer_count-1]; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4080 | if (batch_obj->base.pending_write_domain) { |
Chris Wilson | 5f26a2c | 2009-06-06 09:45:58 +0100 | [diff] [blame] | 4081 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); |
| 4082 | ret = -EINVAL; |
| 4083 | goto err; |
| 4084 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4085 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4086 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 4087 | /* Sanity check the batch buffer */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4088 | exec_offset = batch_obj->gtt_offset; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 4089 | ret = i915_gem_check_execbuffer(args, exec_offset); |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 4090 | if (ret != 0) { |
| 4091 | DRM_ERROR("execbuf with invalid offset/length\n"); |
| 4092 | goto err; |
| 4093 | } |
| 4094 | |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 4095 | ret = i915_gem_execbuffer_move_to_gpu(dev, file, ring, |
| 4096 | object_list, args->buffer_count); |
| 4097 | if (ret) |
| 4098 | goto err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4099 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4100 | #if WATCH_COHERENCY |
| 4101 | for (i = 0; i < args->buffer_count; i++) { |
| 4102 | i915_gem_object_check_coherency(object_list[i], |
| 4103 | exec_list[i].handle); |
| 4104 | } |
| 4105 | #endif |
| 4106 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4107 | #if WATCH_EXEC |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 4108 | i915_gem_dump_object(batch_obj, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4109 | args->batch_len, |
| 4110 | __func__, |
| 4111 | ~0); |
| 4112 | #endif |
| 4113 | |
Chris Wilson | e59f2ba | 2010-10-07 17:28:15 +0100 | [diff] [blame] | 4114 | /* Check for any pending flips. As we only maintain a flip queue depth |
| 4115 | * of 1, we can simply insert a WAIT for the next display flip prior |
| 4116 | * to executing the batch and avoid stalling the CPU. |
| 4117 | */ |
| 4118 | flips = 0; |
| 4119 | for (i = 0; i < args->buffer_count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4120 | if (object_list[i]->base.write_domain) |
| 4121 | flips |= atomic_read(&object_list[i]->pending_flip); |
Chris Wilson | e59f2ba | 2010-10-07 17:28:15 +0100 | [diff] [blame] | 4122 | } |
| 4123 | if (flips) { |
| 4124 | int plane, flip_mask; |
| 4125 | |
| 4126 | for (plane = 0; flips >> plane; plane++) { |
| 4127 | if (((flips >> plane) & 1) == 0) |
| 4128 | continue; |
| 4129 | |
| 4130 | if (plane) |
| 4131 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 4132 | else |
| 4133 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
| 4134 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 4135 | ret = intel_ring_begin(ring, 2); |
| 4136 | if (ret) |
| 4137 | goto err; |
| 4138 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 4139 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
| 4140 | intel_ring_emit(ring, MI_NOOP); |
| 4141 | intel_ring_advance(ring); |
Chris Wilson | e59f2ba | 2010-10-07 17:28:15 +0100 | [diff] [blame] | 4142 | } |
| 4143 | } |
| 4144 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4145 | /* Exec the batchbuffer */ |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 4146 | ret = ring->dispatch_execbuffer(ring, args, cliprects, exec_offset); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4147 | if (ret) { |
| 4148 | DRM_ERROR("dispatch failed %d\n", ret); |
| 4149 | goto err; |
| 4150 | } |
| 4151 | |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 4152 | for (i = 0; i < args->buffer_count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4153 | struct drm_i915_gem_object *obj = object_list[i]; |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 4154 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4155 | obj->base.read_domains = obj->base.pending_read_domains; |
| 4156 | obj->base.write_domain = obj->base.pending_write_domain; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 4157 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 4158 | |
| 4159 | i915_gem_object_move_to_active(obj, ring); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4160 | if (obj->base.write_domain) { |
| 4161 | obj->dirty = 1; |
| 4162 | list_move_tail(&obj->gpu_write_list, |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 4163 | &ring->gpu_write_list); |
| 4164 | intel_mark_busy(dev, obj); |
| 4165 | } |
| 4166 | |
| 4167 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4168 | obj->base.read_domains, |
| 4169 | obj->base.write_domain); |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 4170 | } |
| 4171 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4172 | /* |
| 4173 | * Ensure that the commands in the batch buffer are |
| 4174 | * finished before the interrupt fires |
| 4175 | */ |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 4176 | i915_retire_commands(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4177 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 4178 | if (i915_add_request(dev, file, request, ring)) |
Chris Wilson | 5d97eb6 | 2010-11-10 20:40:02 +0000 | [diff] [blame] | 4179 | i915_gem_next_request_seqno(dev, ring); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 4180 | else |
| 4181 | request = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4182 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4183 | err: |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 4184 | for (i = 0; i < args->buffer_count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4185 | object_list[i]->in_execbuffer = false; |
| 4186 | drm_gem_object_unreference(&object_list[i]->base); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 4187 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 4188 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4189 | mutex_unlock(&dev->struct_mutex); |
| 4190 | |
Chris Wilson | 93533c2 | 2010-01-31 10:40:48 +0000 | [diff] [blame] | 4191 | pre_mutex_err: |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 4192 | drm_free_large(object_list); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4193 | kfree(cliprects); |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 4194 | kfree(request); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4195 | |
| 4196 | return ret; |
| 4197 | } |
| 4198 | |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4199 | /* |
| 4200 | * Legacy execbuffer just creates an exec2 list from the original exec object |
| 4201 | * list array and passes it to the real function. |
| 4202 | */ |
| 4203 | int |
| 4204 | i915_gem_execbuffer(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4205 | struct drm_file *file) |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4206 | { |
| 4207 | struct drm_i915_gem_execbuffer *args = data; |
| 4208 | struct drm_i915_gem_execbuffer2 exec2; |
| 4209 | struct drm_i915_gem_exec_object *exec_list = NULL; |
| 4210 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 4211 | int ret, i; |
| 4212 | |
| 4213 | #if WATCH_EXEC |
| 4214 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 4215 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 4216 | #endif |
| 4217 | |
| 4218 | if (args->buffer_count < 1) { |
| 4219 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 4220 | return -EINVAL; |
| 4221 | } |
| 4222 | |
| 4223 | /* Copy in the exec list from userland */ |
| 4224 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); |
| 4225 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 4226 | if (exec_list == NULL || exec2_list == NULL) { |
| 4227 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 4228 | args->buffer_count); |
| 4229 | drm_free_large(exec_list); |
| 4230 | drm_free_large(exec2_list); |
| 4231 | return -ENOMEM; |
| 4232 | } |
| 4233 | ret = copy_from_user(exec_list, |
| 4234 | (struct drm_i915_relocation_entry __user *) |
| 4235 | (uintptr_t) args->buffers_ptr, |
| 4236 | sizeof(*exec_list) * args->buffer_count); |
| 4237 | if (ret != 0) { |
| 4238 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 4239 | args->buffer_count, ret); |
| 4240 | drm_free_large(exec_list); |
| 4241 | drm_free_large(exec2_list); |
| 4242 | return -EFAULT; |
| 4243 | } |
| 4244 | |
| 4245 | for (i = 0; i < args->buffer_count; i++) { |
| 4246 | exec2_list[i].handle = exec_list[i].handle; |
| 4247 | exec2_list[i].relocation_count = exec_list[i].relocation_count; |
| 4248 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; |
| 4249 | exec2_list[i].alignment = exec_list[i].alignment; |
| 4250 | exec2_list[i].offset = exec_list[i].offset; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4251 | if (INTEL_INFO(dev)->gen < 4) |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4252 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
| 4253 | else |
| 4254 | exec2_list[i].flags = 0; |
| 4255 | } |
| 4256 | |
| 4257 | exec2.buffers_ptr = args->buffers_ptr; |
| 4258 | exec2.buffer_count = args->buffer_count; |
| 4259 | exec2.batch_start_offset = args->batch_start_offset; |
| 4260 | exec2.batch_len = args->batch_len; |
| 4261 | exec2.DR1 = args->DR1; |
| 4262 | exec2.DR4 = args->DR4; |
| 4263 | exec2.num_cliprects = args->num_cliprects; |
| 4264 | exec2.cliprects_ptr = args->cliprects_ptr; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4265 | exec2.flags = I915_EXEC_RENDER; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4266 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4267 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4268 | if (!ret) { |
| 4269 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 4270 | for (i = 0; i < args->buffer_count; i++) |
| 4271 | exec_list[i].offset = exec2_list[i].offset; |
| 4272 | /* ... and back out to userspace */ |
| 4273 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 4274 | (uintptr_t) args->buffers_ptr, |
| 4275 | exec_list, |
| 4276 | sizeof(*exec_list) * args->buffer_count); |
| 4277 | if (ret) { |
| 4278 | ret = -EFAULT; |
| 4279 | DRM_ERROR("failed to copy %d exec entries " |
| 4280 | "back to user (%d)\n", |
| 4281 | args->buffer_count, ret); |
| 4282 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4283 | } |
| 4284 | |
| 4285 | drm_free_large(exec_list); |
| 4286 | drm_free_large(exec2_list); |
| 4287 | return ret; |
| 4288 | } |
| 4289 | |
| 4290 | int |
| 4291 | i915_gem_execbuffer2(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4292 | struct drm_file *file) |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4293 | { |
| 4294 | struct drm_i915_gem_execbuffer2 *args = data; |
| 4295 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 4296 | int ret; |
| 4297 | |
| 4298 | #if WATCH_EXEC |
| 4299 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 4300 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 4301 | #endif |
| 4302 | |
| 4303 | if (args->buffer_count < 1) { |
| 4304 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); |
| 4305 | return -EINVAL; |
| 4306 | } |
| 4307 | |
| 4308 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 4309 | if (exec2_list == NULL) { |
| 4310 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 4311 | args->buffer_count); |
| 4312 | return -ENOMEM; |
| 4313 | } |
| 4314 | ret = copy_from_user(exec2_list, |
| 4315 | (struct drm_i915_relocation_entry __user *) |
| 4316 | (uintptr_t) args->buffers_ptr, |
| 4317 | sizeof(*exec2_list) * args->buffer_count); |
| 4318 | if (ret != 0) { |
| 4319 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 4320 | args->buffer_count, ret); |
| 4321 | drm_free_large(exec2_list); |
| 4322 | return -EFAULT; |
| 4323 | } |
| 4324 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4325 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4326 | if (!ret) { |
| 4327 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 4328 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 4329 | (uintptr_t) args->buffers_ptr, |
| 4330 | exec2_list, |
| 4331 | sizeof(*exec2_list) * args->buffer_count); |
| 4332 | if (ret) { |
| 4333 | ret = -EFAULT; |
| 4334 | DRM_ERROR("failed to copy %d exec entries " |
| 4335 | "back to user (%d)\n", |
| 4336 | args->buffer_count, ret); |
| 4337 | } |
| 4338 | } |
| 4339 | |
| 4340 | drm_free_large(exec2_list); |
| 4341 | return ret; |
| 4342 | } |
| 4343 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4344 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4345 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 4346 | uint32_t alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 4347 | bool map_and_fenceable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4348 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4349 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4350 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4351 | int ret; |
| 4352 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4353 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4354 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4355 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4356 | if (obj->gtt_space != NULL) { |
| 4357 | if ((alignment && obj->gtt_offset & (alignment - 1)) || |
| 4358 | (map_and_fenceable && !obj->map_and_fenceable)) { |
| 4359 | WARN(obj->pin_count, |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 4360 | "bo is already pinned with incorrect alignment:" |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 4361 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
| 4362 | " obj->map_and_fenceable=%d\n", |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4363 | obj->gtt_offset, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 4364 | map_and_fenceable, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4365 | obj->map_and_fenceable); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4366 | ret = i915_gem_object_unbind(obj); |
| 4367 | if (ret) |
| 4368 | return ret; |
| 4369 | } |
| 4370 | } |
| 4371 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4372 | if (obj->gtt_space == NULL) { |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 4373 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 4374 | map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 4375 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4376 | return ret; |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 4377 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4378 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4379 | if (obj->pin_count++ == 0) { |
| 4380 | i915_gem_info_add_pin(dev_priv, obj, map_and_fenceable); |
| 4381 | if (!obj->active) |
| 4382 | list_move_tail(&obj->mm_list, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4383 | &dev_priv->mm.pinned_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4384 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4385 | BUG_ON(!obj->pin_mappable && map_and_fenceable); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4386 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4387 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4388 | return 0; |
| 4389 | } |
| 4390 | |
| 4391 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4392 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4393 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4394 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4395 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4396 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4397 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4398 | BUG_ON(obj->pin_count == 0); |
| 4399 | BUG_ON(obj->gtt_space == NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4400 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4401 | if (--obj->pin_count == 0) { |
| 4402 | if (!obj->active) |
| 4403 | list_move_tail(&obj->mm_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4404 | &dev_priv->mm.inactive_list); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4405 | i915_gem_info_remove_pin(dev_priv, obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4406 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4407 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4408 | } |
| 4409 | |
| 4410 | int |
| 4411 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4412 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4413 | { |
| 4414 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4415 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4416 | int ret; |
| 4417 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4418 | ret = i915_mutex_lock_interruptible(dev); |
| 4419 | if (ret) |
| 4420 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4421 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4422 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4423 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4424 | ret = -ENOENT; |
| 4425 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4426 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4427 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4428 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4429 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4430 | ret = -EINVAL; |
| 4431 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4432 | } |
| 4433 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4434 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4435 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 4436 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4437 | ret = -EINVAL; |
| 4438 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4439 | } |
| 4440 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4441 | obj->user_pin_count++; |
| 4442 | obj->pin_filp = file; |
| 4443 | if (obj->user_pin_count == 1) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 4444 | ret = i915_gem_object_pin(obj, args->alignment, true); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4445 | if (ret) |
| 4446 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4447 | } |
| 4448 | |
| 4449 | /* XXX - flush the CPU caches for pinned objects |
| 4450 | * as the X server doesn't manage domains yet |
| 4451 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4452 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4453 | args->offset = obj->gtt_offset; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4454 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4455 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4456 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4457 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4458 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4459 | } |
| 4460 | |
| 4461 | int |
| 4462 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4463 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4464 | { |
| 4465 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4466 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4467 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4468 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4469 | ret = i915_mutex_lock_interruptible(dev); |
| 4470 | if (ret) |
| 4471 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4472 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4473 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4474 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4475 | ret = -ENOENT; |
| 4476 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4477 | } |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4478 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4479 | if (obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4480 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 4481 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4482 | ret = -EINVAL; |
| 4483 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4484 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4485 | obj->user_pin_count--; |
| 4486 | if (obj->user_pin_count == 0) { |
| 4487 | obj->pin_filp = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4488 | i915_gem_object_unpin(obj); |
| 4489 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4490 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4491 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4492 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4493 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4494 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4495 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4496 | } |
| 4497 | |
| 4498 | int |
| 4499 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4500 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4501 | { |
| 4502 | struct drm_i915_gem_busy *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4503 | struct drm_i915_gem_object *obj; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4504 | int ret; |
| 4505 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4506 | ret = i915_mutex_lock_interruptible(dev); |
| 4507 | if (ret) |
| 4508 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4509 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4510 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4511 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4512 | ret = -ENOENT; |
| 4513 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4514 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4515 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4516 | /* Count all active objects as busy, even if they are currently not used |
| 4517 | * by the gpu. Users of this interface expect objects to eventually |
| 4518 | * become non-busy without any further actions, therefore emit any |
| 4519 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 4520 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4521 | args->busy = obj->active; |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4522 | if (args->busy) { |
| 4523 | /* Unconditionally flush objects, even when the gpu still uses this |
| 4524 | * object. Userspace calling this function indicates that it wants to |
| 4525 | * use this buffer rather sooner than later, so issuing the required |
| 4526 | * flush earlier is beneficial. |
| 4527 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4528 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) |
| 4529 | i915_gem_flush_ring(dev, obj->ring, |
| 4530 | 0, obj->base.write_domain); |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4531 | |
| 4532 | /* Update the active list for the hardware's current position. |
| 4533 | * Otherwise this only updates on a delayed timer or when irqs |
| 4534 | * are actually unmasked, and our working set ends up being |
| 4535 | * larger than required. |
| 4536 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4537 | i915_gem_retire_requests_ring(dev, obj->ring); |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4538 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4539 | args->busy = obj->active; |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4540 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4541 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4542 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4543 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4544 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4545 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4546 | } |
| 4547 | |
| 4548 | int |
| 4549 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4550 | struct drm_file *file_priv) |
| 4551 | { |
| 4552 | return i915_gem_ring_throttle(dev, file_priv); |
| 4553 | } |
| 4554 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4555 | int |
| 4556 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4557 | struct drm_file *file_priv) |
| 4558 | { |
| 4559 | struct drm_i915_gem_madvise *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4560 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4561 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4562 | |
| 4563 | switch (args->madv) { |
| 4564 | case I915_MADV_DONTNEED: |
| 4565 | case I915_MADV_WILLNEED: |
| 4566 | break; |
| 4567 | default: |
| 4568 | return -EINVAL; |
| 4569 | } |
| 4570 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4571 | ret = i915_mutex_lock_interruptible(dev); |
| 4572 | if (ret) |
| 4573 | return ret; |
| 4574 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4575 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4576 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4577 | ret = -ENOENT; |
| 4578 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4579 | } |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4580 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4581 | if (obj->pin_count) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4582 | ret = -EINVAL; |
| 4583 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4584 | } |
| 4585 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4586 | if (obj->madv != __I915_MADV_PURGED) |
| 4587 | obj->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4588 | |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 4589 | /* if the object is no longer bound, discard its backing storage */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4590 | if (i915_gem_object_is_purgeable(obj) && |
| 4591 | obj->gtt_space == NULL) |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 4592 | i915_gem_object_truncate(obj); |
| 4593 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4594 | args->retained = obj->madv != __I915_MADV_PURGED; |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4595 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4596 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4597 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4598 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4599 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4600 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4601 | } |
| 4602 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4603 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 4604 | size_t size) |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4605 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4606 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4607 | struct drm_i915_gem_object *obj; |
| 4608 | |
| 4609 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
| 4610 | if (obj == NULL) |
| 4611 | return NULL; |
| 4612 | |
| 4613 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
| 4614 | kfree(obj); |
| 4615 | return NULL; |
| 4616 | } |
| 4617 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4618 | i915_gem_info_add_obj(dev_priv, size); |
| 4619 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4620 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4621 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4622 | |
| 4623 | obj->agp_type = AGP_USER_MEMORY; |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 4624 | obj->base.driver_private = NULL; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4625 | obj->fence_reg = I915_FENCE_REG_NONE; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4626 | INIT_LIST_HEAD(&obj->mm_list); |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 4627 | INIT_LIST_HEAD(&obj->gtt_list); |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4628 | INIT_LIST_HEAD(&obj->ring_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4629 | INIT_LIST_HEAD(&obj->gpu_write_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4630 | obj->madv = I915_MADV_WILLNEED; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 4631 | /* Avoid an unnecessary call to unbind on the first bind. */ |
| 4632 | obj->map_and_fenceable = true; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4633 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4634 | return obj; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4635 | } |
| 4636 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4637 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 4638 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4639 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4640 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4641 | return 0; |
| 4642 | } |
| 4643 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4644 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4645 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4646 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4647 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4648 | int ret; |
| 4649 | |
| 4650 | ret = i915_gem_object_unbind(obj); |
| 4651 | if (ret == -ERESTARTSYS) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4652 | list_move(&obj->mm_list, |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4653 | &dev_priv->mm.deferred_free_list); |
| 4654 | return; |
| 4655 | } |
| 4656 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4657 | if (obj->base.map_list.map) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4658 | i915_gem_free_mmap_offset(obj); |
| 4659 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4660 | drm_gem_object_release(&obj->base); |
| 4661 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4662 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4663 | kfree(obj->page_cpu_valid); |
| 4664 | kfree(obj->bit_17); |
| 4665 | kfree(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4666 | } |
| 4667 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4668 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4669 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4670 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
| 4671 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4672 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4673 | trace_i915_gem_object_destroy(obj); |
| 4674 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4675 | while (obj->pin_count > 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4676 | i915_gem_object_unpin(obj); |
| 4677 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4678 | if (obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4679 | i915_gem_detach_phys_object(dev, obj); |
| 4680 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4681 | i915_gem_free_object_tail(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4682 | } |
| 4683 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 4684 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4685 | i915_gem_idle(struct drm_device *dev) |
| 4686 | { |
| 4687 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4688 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4689 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4690 | mutex_lock(&dev->struct_mutex); |
| 4691 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4692 | if (dev_priv->mm.suspended) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4693 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4694 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4695 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4696 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4697 | ret = i915_gpu_idle(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4698 | if (ret) { |
| 4699 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4700 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4701 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4702 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4703 | /* Under UMS, be paranoid and evict. */ |
| 4704 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { |
Chris Wilson | 5eac3ab | 2010-10-31 08:49:47 +0000 | [diff] [blame] | 4705 | ret = i915_gem_evict_inactive(dev, false); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4706 | if (ret) { |
| 4707 | mutex_unlock(&dev->struct_mutex); |
| 4708 | return ret; |
| 4709 | } |
| 4710 | } |
| 4711 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame^] | 4712 | i915_gem_reset_fences(dev); |
| 4713 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4714 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 4715 | * We need to replace this with a semaphore, or something. |
| 4716 | * And not confound mm.suspended! |
| 4717 | */ |
| 4718 | dev_priv->mm.suspended = 1; |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 4719 | del_timer_sync(&dev_priv->hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4720 | |
| 4721 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4722 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4723 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4724 | mutex_unlock(&dev->struct_mutex); |
| 4725 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4726 | /* Cancel the retire work handler, which should be idle now. */ |
| 4727 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 4728 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4729 | return 0; |
| 4730 | } |
| 4731 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4732 | int |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4733 | i915_gem_init_ringbuffer(struct drm_device *dev) |
| 4734 | { |
| 4735 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4736 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4737 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4738 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4739 | if (ret) |
Chris Wilson | b6913e4 | 2010-11-12 10:46:37 +0000 | [diff] [blame] | 4740 | return ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4741 | |
| 4742 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4743 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4744 | if (ret) |
| 4745 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4746 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4747 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4748 | if (HAS_BLT(dev)) { |
| 4749 | ret = intel_init_blt_ring_buffer(dev); |
| 4750 | if (ret) |
| 4751 | goto cleanup_bsd_ring; |
| 4752 | } |
| 4753 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 4754 | dev_priv->next_seqno = 1; |
| 4755 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4756 | return 0; |
| 4757 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4758 | cleanup_bsd_ring: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 4759 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4760 | cleanup_render_ring: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 4761 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4762 | return ret; |
| 4763 | } |
| 4764 | |
| 4765 | void |
| 4766 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4767 | { |
| 4768 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4769 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 4770 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
| 4771 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
| 4772 | intel_cleanup_ring_buffer(&dev_priv->blt_ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4773 | } |
| 4774 | |
| 4775 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4776 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 4777 | struct drm_file *file_priv) |
| 4778 | { |
| 4779 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4780 | int ret; |
| 4781 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4782 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4783 | return 0; |
| 4784 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4785 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4786 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4787 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4788 | } |
| 4789 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4790 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4791 | dev_priv->mm.suspended = 0; |
| 4792 | |
| 4793 | ret = i915_gem_init_ringbuffer(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4794 | if (ret != 0) { |
| 4795 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4796 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4797 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4798 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4799 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4800 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4801 | BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list)); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4802 | BUG_ON(!list_empty(&dev_priv->blt_ring.active_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4803 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 4804 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4805 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4806 | BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list)); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4807 | BUG_ON(!list_empty(&dev_priv->blt_ring.request_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4808 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4809 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4810 | ret = drm_irq_install(dev); |
| 4811 | if (ret) |
| 4812 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4813 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4814 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4815 | |
| 4816 | cleanup_ringbuffer: |
| 4817 | mutex_lock(&dev->struct_mutex); |
| 4818 | i915_gem_cleanup_ringbuffer(dev); |
| 4819 | dev_priv->mm.suspended = 1; |
| 4820 | mutex_unlock(&dev->struct_mutex); |
| 4821 | |
| 4822 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4823 | } |
| 4824 | |
| 4825 | int |
| 4826 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 4827 | struct drm_file *file_priv) |
| 4828 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4829 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4830 | return 0; |
| 4831 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4832 | drm_irq_uninstall(dev); |
Linus Torvalds | e6890f6 | 2009-09-08 17:09:24 -0700 | [diff] [blame] | 4833 | return i915_gem_idle(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4834 | } |
| 4835 | |
| 4836 | void |
| 4837 | i915_gem_lastclose(struct drm_device *dev) |
| 4838 | { |
| 4839 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4840 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 4841 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4842 | return; |
| 4843 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4844 | ret = i915_gem_idle(dev); |
| 4845 | if (ret) |
| 4846 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4847 | } |
| 4848 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4849 | static void |
| 4850 | init_ring_lists(struct intel_ring_buffer *ring) |
| 4851 | { |
| 4852 | INIT_LIST_HEAD(&ring->active_list); |
| 4853 | INIT_LIST_HEAD(&ring->request_list); |
| 4854 | INIT_LIST_HEAD(&ring->gpu_write_list); |
| 4855 | } |
| 4856 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4857 | void |
| 4858 | i915_gem_load(struct drm_device *dev) |
| 4859 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4860 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4861 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4862 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4863 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4864 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
| 4865 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4866 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4867 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4868 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 4869 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4870 | init_ring_lists(&dev_priv->render_ring); |
| 4871 | init_ring_lists(&dev_priv->bsd_ring); |
| 4872 | init_ring_lists(&dev_priv->blt_ring); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 4873 | for (i = 0; i < 16; i++) |
| 4874 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4875 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 4876 | i915_gem_retire_work_handler); |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4877 | init_completion(&dev_priv->error_completion); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4878 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4879 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 4880 | if (IS_GEN3(dev)) { |
| 4881 | u32 tmp = I915_READ(MI_ARB_STATE); |
| 4882 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { |
| 4883 | /* arb state is a masked write, so set bit + bit in mask */ |
| 4884 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); |
| 4885 | I915_WRITE(MI_ARB_STATE, tmp); |
| 4886 | } |
| 4887 | } |
| 4888 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4889 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 4890 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4891 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4892 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4893 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4894 | dev_priv->num_fence_regs = 16; |
| 4895 | else |
| 4896 | dev_priv->num_fence_regs = 8; |
| 4897 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4898 | /* Initialize fence registers to zero */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4899 | switch (INTEL_INFO(dev)->gen) { |
| 4900 | case 6: |
| 4901 | for (i = 0; i < 16; i++) |
| 4902 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); |
| 4903 | break; |
| 4904 | case 5: |
| 4905 | case 4: |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4906 | for (i = 0; i < 16; i++) |
| 4907 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4908 | break; |
| 4909 | case 3: |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4910 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 4911 | for (i = 0; i < 8; i++) |
| 4912 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4913 | case 2: |
| 4914 | for (i = 0; i < 8; i++) |
| 4915 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); |
| 4916 | break; |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4917 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4918 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4919 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4920 | |
| 4921 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
| 4922 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
| 4923 | register_shrinker(&dev_priv->mm.inactive_shrinker); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4924 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4925 | |
| 4926 | /* |
| 4927 | * Create a physically contiguous memory object for this object |
| 4928 | * e.g. for cursor + overlay regs |
| 4929 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4930 | static int i915_gem_init_phys_object(struct drm_device *dev, |
| 4931 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4932 | { |
| 4933 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4934 | struct drm_i915_gem_phys_object *phys_obj; |
| 4935 | int ret; |
| 4936 | |
| 4937 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 4938 | return 0; |
| 4939 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4940 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4941 | if (!phys_obj) |
| 4942 | return -ENOMEM; |
| 4943 | |
| 4944 | phys_obj->id = id; |
| 4945 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4946 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4947 | if (!phys_obj->handle) { |
| 4948 | ret = -ENOMEM; |
| 4949 | goto kfree_obj; |
| 4950 | } |
| 4951 | #ifdef CONFIG_X86 |
| 4952 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4953 | #endif |
| 4954 | |
| 4955 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 4956 | |
| 4957 | return 0; |
| 4958 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4959 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4960 | return ret; |
| 4961 | } |
| 4962 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4963 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4964 | { |
| 4965 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4966 | struct drm_i915_gem_phys_object *phys_obj; |
| 4967 | |
| 4968 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 4969 | return; |
| 4970 | |
| 4971 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4972 | if (phys_obj->cur_obj) { |
| 4973 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 4974 | } |
| 4975 | |
| 4976 | #ifdef CONFIG_X86 |
| 4977 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4978 | #endif |
| 4979 | drm_pci_free(dev, phys_obj->handle); |
| 4980 | kfree(phys_obj); |
| 4981 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 4982 | } |
| 4983 | |
| 4984 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 4985 | { |
| 4986 | int i; |
| 4987 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 4988 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4989 | i915_gem_free_phys_object(dev, i); |
| 4990 | } |
| 4991 | |
| 4992 | void i915_gem_detach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4993 | struct drm_i915_gem_object *obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4994 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4995 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4996 | char *vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4997 | int i; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4998 | int page_count; |
| 4999 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5000 | if (!obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5001 | return; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5002 | vaddr = obj->phys_obj->handle->vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5003 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5004 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5005 | for (i = 0; i < page_count; i++) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 5006 | struct page *page = read_cache_page_gfp(mapping, i, |
| 5007 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 5008 | if (!IS_ERR(page)) { |
| 5009 | char *dst = kmap_atomic(page); |
| 5010 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); |
| 5011 | kunmap_atomic(dst); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5012 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 5013 | drm_clflush_pages(&page, 1); |
| 5014 | |
| 5015 | set_page_dirty(page); |
| 5016 | mark_page_accessed(page); |
| 5017 | page_cache_release(page); |
| 5018 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5019 | } |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 5020 | intel_gtt_chipset_flush(); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 5021 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5022 | obj->phys_obj->cur_obj = NULL; |
| 5023 | obj->phys_obj = NULL; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5024 | } |
| 5025 | |
| 5026 | int |
| 5027 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5028 | struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 5029 | int id, |
| 5030 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5031 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5032 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5033 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5034 | int ret = 0; |
| 5035 | int page_count; |
| 5036 | int i; |
| 5037 | |
| 5038 | if (id > I915_MAX_PHYS_OBJECT) |
| 5039 | return -EINVAL; |
| 5040 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5041 | if (obj->phys_obj) { |
| 5042 | if (obj->phys_obj->id == id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5043 | return 0; |
| 5044 | i915_gem_detach_phys_object(dev, obj); |
| 5045 | } |
| 5046 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5047 | /* create a new object */ |
| 5048 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 5049 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5050 | obj->base.size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5051 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5052 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
| 5053 | id, obj->base.size); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 5054 | return ret; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5055 | } |
| 5056 | } |
| 5057 | |
| 5058 | /* bind to the object */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5059 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 5060 | obj->phys_obj->cur_obj = obj; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5061 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5062 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5063 | |
| 5064 | for (i = 0; i < page_count; i++) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 5065 | struct page *page; |
| 5066 | char *dst, *src; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5067 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 5068 | page = read_cache_page_gfp(mapping, i, |
| 5069 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 5070 | if (IS_ERR(page)) |
| 5071 | return PTR_ERR(page); |
| 5072 | |
Chris Wilson | ff75b9b | 2010-10-30 22:52:31 +0100 | [diff] [blame] | 5073 | src = kmap_atomic(page); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5074 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5075 | memcpy(dst, src, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 5076 | kunmap_atomic(src); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 5077 | |
| 5078 | mark_page_accessed(page); |
| 5079 | page_cache_release(page); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5080 | } |
| 5081 | |
| 5082 | return 0; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5083 | } |
| 5084 | |
| 5085 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5086 | i915_gem_phys_pwrite(struct drm_device *dev, |
| 5087 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5088 | struct drm_i915_gem_pwrite *args, |
| 5089 | struct drm_file *file_priv) |
| 5090 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5091 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 5092 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5093 | |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 5094 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 5095 | unsigned long unwritten; |
| 5096 | |
| 5097 | /* The physical object once assigned is fixed for the lifetime |
| 5098 | * of the obj, so we can safely drop the lock and continue |
| 5099 | * to access vaddr. |
| 5100 | */ |
| 5101 | mutex_unlock(&dev->struct_mutex); |
| 5102 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 5103 | mutex_lock(&dev->struct_mutex); |
| 5104 | if (unwritten) |
| 5105 | return -EFAULT; |
| 5106 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5107 | |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 5108 | intel_gtt_chipset_flush(); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5109 | return 0; |
| 5110 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5111 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5112 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5113 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5114 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5115 | |
| 5116 | /* Clean up our request list when the client is going away, so that |
| 5117 | * later retire_requests won't dereference our soon-to-be-gone |
| 5118 | * file_priv. |
| 5119 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 5120 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5121 | while (!list_empty(&file_priv->mm.request_list)) { |
| 5122 | struct drm_i915_gem_request *request; |
| 5123 | |
| 5124 | request = list_first_entry(&file_priv->mm.request_list, |
| 5125 | struct drm_i915_gem_request, |
| 5126 | client_list); |
| 5127 | list_del(&request->client_list); |
| 5128 | request->file_priv = NULL; |
| 5129 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 5130 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5131 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5132 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5133 | static int |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5134 | i915_gpu_is_active(struct drm_device *dev) |
| 5135 | { |
| 5136 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 5137 | int lists_empty; |
| 5138 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5139 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5140 | list_empty(&dev_priv->mm.active_list); |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5141 | |
| 5142 | return !lists_empty; |
| 5143 | } |
| 5144 | |
| 5145 | static int |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5146 | i915_gem_inactive_shrink(struct shrinker *shrinker, |
| 5147 | int nr_to_scan, |
| 5148 | gfp_t gfp_mask) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5149 | { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5150 | struct drm_i915_private *dev_priv = |
| 5151 | container_of(shrinker, |
| 5152 | struct drm_i915_private, |
| 5153 | mm.inactive_shrinker); |
| 5154 | struct drm_device *dev = dev_priv->dev; |
| 5155 | struct drm_i915_gem_object *obj, *next; |
| 5156 | int cnt; |
| 5157 | |
| 5158 | if (!mutex_trylock(&dev->struct_mutex)) |
Chris Wilson | bbe2e11 | 2010-10-28 22:35:07 +0100 | [diff] [blame] | 5159 | return 0; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5160 | |
| 5161 | /* "fast-path" to count number of available objects */ |
| 5162 | if (nr_to_scan == 0) { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5163 | cnt = 0; |
| 5164 | list_for_each_entry(obj, |
| 5165 | &dev_priv->mm.inactive_list, |
| 5166 | mm_list) |
| 5167 | cnt++; |
| 5168 | mutex_unlock(&dev->struct_mutex); |
| 5169 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5170 | } |
| 5171 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5172 | rescan: |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5173 | /* first scan for clean buffers */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5174 | i915_gem_retire_requests(dev); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5175 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5176 | list_for_each_entry_safe(obj, next, |
| 5177 | &dev_priv->mm.inactive_list, |
| 5178 | mm_list) { |
| 5179 | if (i915_gem_object_is_purgeable(obj)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5180 | i915_gem_object_unbind(obj); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5181 | if (--nr_to_scan == 0) |
| 5182 | break; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5183 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5184 | } |
| 5185 | |
| 5186 | /* second pass, evict/count anything still on the inactive list */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5187 | cnt = 0; |
| 5188 | list_for_each_entry_safe(obj, next, |
| 5189 | &dev_priv->mm.inactive_list, |
| 5190 | mm_list) { |
| 5191 | if (nr_to_scan) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5192 | i915_gem_object_unbind(obj); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5193 | nr_to_scan--; |
| 5194 | } else |
| 5195 | cnt++; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5196 | } |
| 5197 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5198 | if (nr_to_scan && i915_gpu_is_active(dev)) { |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5199 | /* |
| 5200 | * We are desperate for pages, so as a last resort, wait |
| 5201 | * for the GPU to finish and discard whatever we can. |
| 5202 | * This has a dramatic impact to reduce the number of |
| 5203 | * OOM-killer events whilst running the GPU aggressively. |
| 5204 | */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5205 | if (i915_gpu_idle(dev) == 0) |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5206 | goto rescan; |
| 5207 | } |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5208 | mutex_unlock(&dev->struct_mutex); |
| 5209 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5210 | } |