Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 34 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 35 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include <linux/pci.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 37 | |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 38 | struct change_domains { |
| 39 | uint32_t invalidate_domains; |
| 40 | uint32_t flush_domains; |
| 41 | uint32_t flush_rings; |
| 42 | }; |
| 43 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 44 | static int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 45 | struct intel_ring_buffer *pipelined); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 46 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
| 47 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
| 48 | static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 49 | bool write); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 50 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 51 | uint64_t offset, |
| 52 | uint64_t size); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 53 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj); |
| 54 | static int i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 55 | bool interruptible); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 56 | static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 57 | unsigned alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 58 | bool map_and_fenceable); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 59 | static void i915_gem_clear_fence_reg(struct drm_i915_gem_object *obj); |
| 60 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
| 61 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 62 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 63 | struct drm_file *file); |
| 64 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 65 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 66 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
| 67 | int nr_to_scan, |
| 68 | gfp_t gfp_mask); |
| 69 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 70 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 71 | /* some bookkeeping */ |
| 72 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 73 | size_t size) |
| 74 | { |
| 75 | dev_priv->mm.object_count++; |
| 76 | dev_priv->mm.object_memory += size; |
| 77 | } |
| 78 | |
| 79 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 80 | size_t size) |
| 81 | { |
| 82 | dev_priv->mm.object_count--; |
| 83 | dev_priv->mm.object_memory -= size; |
| 84 | } |
| 85 | |
| 86 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 87 | struct drm_i915_gem_object *obj) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 88 | { |
| 89 | dev_priv->mm.gtt_count++; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 90 | dev_priv->mm.gtt_memory += obj->gtt_space->size; |
| 91 | if (obj->gtt_offset < dev_priv->mm.gtt_mappable_end) { |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 92 | dev_priv->mm.mappable_gtt_used += |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 93 | min_t(size_t, obj->gtt_space->size, |
| 94 | dev_priv->mm.gtt_mappable_end - obj->gtt_offset); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 95 | } |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 96 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 97 | } |
| 98 | |
| 99 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 100 | struct drm_i915_gem_object *obj) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 101 | { |
| 102 | dev_priv->mm.gtt_count--; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 103 | dev_priv->mm.gtt_memory -= obj->gtt_space->size; |
| 104 | if (obj->gtt_offset < dev_priv->mm.gtt_mappable_end) { |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 105 | dev_priv->mm.mappable_gtt_used -= |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 106 | min_t(size_t, obj->gtt_space->size, |
| 107 | dev_priv->mm.gtt_mappable_end - obj->gtt_offset); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 108 | } |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 109 | list_del_init(&obj->gtt_list); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 110 | } |
| 111 | |
| 112 | /** |
| 113 | * Update the mappable working set counters. Call _only_ when there is a change |
| 114 | * in one of (pin|fault)_mappable and update *_mappable _before_ calling. |
| 115 | * @mappable: new state the changed mappable flag (either pin_ or fault_). |
| 116 | */ |
| 117 | static void |
| 118 | i915_gem_info_update_mappable(struct drm_i915_private *dev_priv, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 119 | struct drm_i915_gem_object *obj, |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 120 | bool mappable) |
| 121 | { |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 122 | if (mappable) { |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 123 | if (obj->pin_mappable && obj->fault_mappable) |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 124 | /* Combined state was already mappable. */ |
| 125 | return; |
| 126 | dev_priv->mm.gtt_mappable_count++; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 127 | dev_priv->mm.gtt_mappable_memory += obj->gtt_space->size; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 128 | } else { |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 129 | if (obj->pin_mappable || obj->fault_mappable) |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 130 | /* Combined state still mappable. */ |
| 131 | return; |
| 132 | dev_priv->mm.gtt_mappable_count--; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 133 | dev_priv->mm.gtt_mappable_memory -= obj->gtt_space->size; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 134 | } |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 135 | } |
| 136 | |
| 137 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 138 | struct drm_i915_gem_object *obj, |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 139 | bool mappable) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 140 | { |
| 141 | dev_priv->mm.pin_count++; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 142 | dev_priv->mm.pin_memory += obj->gtt_space->size; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 143 | if (mappable) { |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 144 | obj->pin_mappable = true; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 145 | i915_gem_info_update_mappable(dev_priv, obj, true); |
| 146 | } |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 147 | } |
| 148 | |
| 149 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 150 | struct drm_i915_gem_object *obj) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 151 | { |
| 152 | dev_priv->mm.pin_count--; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 153 | dev_priv->mm.pin_memory -= obj->gtt_space->size; |
| 154 | if (obj->pin_mappable) { |
| 155 | obj->pin_mappable = false; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 156 | i915_gem_info_update_mappable(dev_priv, obj, false); |
| 157 | } |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 158 | } |
| 159 | |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 160 | int |
| 161 | i915_gem_check_is_wedged(struct drm_device *dev) |
| 162 | { |
| 163 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 164 | struct completion *x = &dev_priv->error_completion; |
| 165 | unsigned long flags; |
| 166 | int ret; |
| 167 | |
| 168 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 169 | return 0; |
| 170 | |
| 171 | ret = wait_for_completion_interruptible(x); |
| 172 | if (ret) |
| 173 | return ret; |
| 174 | |
| 175 | /* Success, we reset the GPU! */ |
| 176 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 177 | return 0; |
| 178 | |
| 179 | /* GPU is hung, bump the completion count to account for |
| 180 | * the token we just consumed so that we never hit zero and |
| 181 | * end up waiting upon a subsequent completion event that |
| 182 | * will never happen. |
| 183 | */ |
| 184 | spin_lock_irqsave(&x->wait.lock, flags); |
| 185 | x->done++; |
| 186 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 187 | return -EIO; |
| 188 | } |
| 189 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 190 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
| 191 | { |
| 192 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 193 | int ret; |
| 194 | |
| 195 | ret = i915_gem_check_is_wedged(dev); |
| 196 | if (ret) |
| 197 | return ret; |
| 198 | |
| 199 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 200 | if (ret) |
| 201 | return ret; |
| 202 | |
| 203 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 204 | mutex_unlock(&dev->struct_mutex); |
| 205 | return -EAGAIN; |
| 206 | } |
| 207 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 208 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 209 | return 0; |
| 210 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 211 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 212 | static inline bool |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 213 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 214 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 215 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 216 | } |
| 217 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 218 | int i915_gem_do_init(struct drm_device *dev, |
| 219 | unsigned long start, |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 220 | unsigned long mappable_end, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 221 | unsigned long end) |
| 222 | { |
| 223 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 224 | |
| 225 | if (start >= end || |
| 226 | (start & (PAGE_SIZE - 1)) != 0 || |
| 227 | (end & (PAGE_SIZE - 1)) != 0) { |
| 228 | return -EINVAL; |
| 229 | } |
| 230 | |
| 231 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
| 232 | end - start); |
| 233 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 234 | dev_priv->mm.gtt_total = end - start; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 235 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 236 | dev_priv->mm.gtt_mappable_end = mappable_end; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 237 | |
| 238 | return 0; |
| 239 | } |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 240 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 241 | int |
| 242 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 243 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 244 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 245 | struct drm_i915_gem_init *args = data; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 246 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 247 | |
| 248 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 249 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 250 | mutex_unlock(&dev->struct_mutex); |
| 251 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 252 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 253 | } |
| 254 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 255 | int |
| 256 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 257 | struct drm_file *file) |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 258 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 259 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 260 | struct drm_i915_gem_get_aperture *args = data; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 261 | |
| 262 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 263 | return -ENODEV; |
| 264 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 265 | mutex_lock(&dev->struct_mutex); |
| 266 | args->aper_size = dev_priv->mm.gtt_total; |
| 267 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; |
| 268 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 269 | |
| 270 | return 0; |
| 271 | } |
| 272 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 273 | |
| 274 | /** |
| 275 | * Creates a new mm object and returns a handle to it. |
| 276 | */ |
| 277 | int |
| 278 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 279 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 280 | { |
| 281 | struct drm_i915_gem_create *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 282 | struct drm_i915_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 283 | int ret; |
| 284 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 285 | |
| 286 | args->size = roundup(args->size, PAGE_SIZE); |
| 287 | |
| 288 | /* Allocate the new object */ |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 289 | obj = i915_gem_alloc_object(dev, args->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 290 | if (obj == NULL) |
| 291 | return -ENOMEM; |
| 292 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 293 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 294 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 295 | drm_gem_object_release(&obj->base); |
| 296 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 297 | kfree(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 298 | return ret; |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 299 | } |
| 300 | |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 301 | /* drop reference from allocate - handle holds it now */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 302 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 303 | trace_i915_gem_object_create(obj); |
| 304 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 305 | args->handle = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 306 | return 0; |
| 307 | } |
| 308 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 309 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 310 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 311 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 312 | |
| 313 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 314 | obj->tiling_mode != I915_TILING_NONE; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 315 | } |
| 316 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 317 | static inline void |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 318 | slow_shmem_copy(struct page *dst_page, |
| 319 | int dst_offset, |
| 320 | struct page *src_page, |
| 321 | int src_offset, |
| 322 | int length) |
| 323 | { |
| 324 | char *dst_vaddr, *src_vaddr; |
| 325 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 326 | dst_vaddr = kmap(dst_page); |
| 327 | src_vaddr = kmap(src_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 328 | |
| 329 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); |
| 330 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 331 | kunmap(src_page); |
| 332 | kunmap(dst_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 333 | } |
| 334 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 335 | static inline void |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 336 | slow_shmem_bit17_copy(struct page *gpu_page, |
| 337 | int gpu_offset, |
| 338 | struct page *cpu_page, |
| 339 | int cpu_offset, |
| 340 | int length, |
| 341 | int is_read) |
| 342 | { |
| 343 | char *gpu_vaddr, *cpu_vaddr; |
| 344 | |
| 345 | /* Use the unswizzled path if this page isn't affected. */ |
| 346 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { |
| 347 | if (is_read) |
| 348 | return slow_shmem_copy(cpu_page, cpu_offset, |
| 349 | gpu_page, gpu_offset, length); |
| 350 | else |
| 351 | return slow_shmem_copy(gpu_page, gpu_offset, |
| 352 | cpu_page, cpu_offset, length); |
| 353 | } |
| 354 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 355 | gpu_vaddr = kmap(gpu_page); |
| 356 | cpu_vaddr = kmap(cpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 357 | |
| 358 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's |
| 359 | * XORing with the other bits (A9 for Y, A9 and A10 for X) |
| 360 | */ |
| 361 | while (length > 0) { |
| 362 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 363 | int this_length = min(cacheline_end - gpu_offset, length); |
| 364 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 365 | |
| 366 | if (is_read) { |
| 367 | memcpy(cpu_vaddr + cpu_offset, |
| 368 | gpu_vaddr + swizzled_gpu_offset, |
| 369 | this_length); |
| 370 | } else { |
| 371 | memcpy(gpu_vaddr + swizzled_gpu_offset, |
| 372 | cpu_vaddr + cpu_offset, |
| 373 | this_length); |
| 374 | } |
| 375 | cpu_offset += this_length; |
| 376 | gpu_offset += this_length; |
| 377 | length -= this_length; |
| 378 | } |
| 379 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 380 | kunmap(cpu_page); |
| 381 | kunmap(gpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 382 | } |
| 383 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 384 | /** |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 385 | * This is the fast shmem pread path, which attempts to copy_from_user directly |
| 386 | * from the backing pages of the object to the user's address space. On a |
| 387 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). |
| 388 | */ |
| 389 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 390 | i915_gem_shmem_pread_fast(struct drm_device *dev, |
| 391 | struct drm_i915_gem_object *obj, |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 392 | struct drm_i915_gem_pread *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 393 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 394 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 395 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 396 | ssize_t remain; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 397 | loff_t offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 398 | char __user *user_data; |
| 399 | int page_offset, page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 400 | |
| 401 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 402 | remain = args->size; |
| 403 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 404 | offset = args->offset; |
| 405 | |
| 406 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 407 | struct page *page; |
| 408 | char *vaddr; |
| 409 | int ret; |
| 410 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 411 | /* Operation in this page |
| 412 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 413 | * page_offset = offset within page |
| 414 | * page_length = bytes to copy for this page |
| 415 | */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 416 | page_offset = offset & (PAGE_SIZE-1); |
| 417 | page_length = remain; |
| 418 | if ((page_offset + remain) > PAGE_SIZE) |
| 419 | page_length = PAGE_SIZE - page_offset; |
| 420 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 421 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
| 422 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 423 | if (IS_ERR(page)) |
| 424 | return PTR_ERR(page); |
| 425 | |
| 426 | vaddr = kmap_atomic(page); |
| 427 | ret = __copy_to_user_inatomic(user_data, |
| 428 | vaddr + page_offset, |
| 429 | page_length); |
| 430 | kunmap_atomic(vaddr); |
| 431 | |
| 432 | mark_page_accessed(page); |
| 433 | page_cache_release(page); |
| 434 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 435 | return -EFAULT; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 436 | |
| 437 | remain -= page_length; |
| 438 | user_data += page_length; |
| 439 | offset += page_length; |
| 440 | } |
| 441 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 442 | return 0; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 443 | } |
| 444 | |
| 445 | /** |
| 446 | * This is the fallback shmem pread path, which allocates temporary storage |
| 447 | * in kernel space to copy_to_user into outside of the struct_mutex, so we |
| 448 | * can copy out of the object's backing pages while holding the struct mutex |
| 449 | * and not take page faults. |
| 450 | */ |
| 451 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 452 | i915_gem_shmem_pread_slow(struct drm_device *dev, |
| 453 | struct drm_i915_gem_object *obj, |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 454 | struct drm_i915_gem_pread *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 455 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 456 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 457 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 458 | struct mm_struct *mm = current->mm; |
| 459 | struct page **user_pages; |
| 460 | ssize_t remain; |
| 461 | loff_t offset, pinned_pages, i; |
| 462 | loff_t first_data_page, last_data_page, num_pages; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 463 | int shmem_page_offset; |
| 464 | int data_page_index, data_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 465 | int page_length; |
| 466 | int ret; |
| 467 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 468 | int do_bit17_swizzling; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 469 | |
| 470 | remain = args->size; |
| 471 | |
| 472 | /* Pin the user pages containing the data. We can't fault while |
| 473 | * holding the struct mutex, yet we want to hold it while |
| 474 | * dereferencing the user data. |
| 475 | */ |
| 476 | first_data_page = data_ptr / PAGE_SIZE; |
| 477 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 478 | num_pages = last_data_page - first_data_page + 1; |
| 479 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 480 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 481 | if (user_pages == NULL) |
| 482 | return -ENOMEM; |
| 483 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 484 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 485 | down_read(&mm->mmap_sem); |
| 486 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
Eric Anholt | e5e9ecd | 2009-04-07 16:01:22 -0700 | [diff] [blame] | 487 | num_pages, 1, 0, user_pages, NULL); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 488 | up_read(&mm->mmap_sem); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 489 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 490 | if (pinned_pages < num_pages) { |
| 491 | ret = -EFAULT; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 492 | goto out; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 493 | } |
| 494 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 495 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
| 496 | args->offset, |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 497 | args->size); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 498 | if (ret) |
| 499 | goto out; |
| 500 | |
| 501 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 502 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 503 | offset = args->offset; |
| 504 | |
| 505 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 506 | struct page *page; |
| 507 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 508 | /* Operation in this page |
| 509 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 510 | * shmem_page_offset = offset within page in shmem file |
| 511 | * data_page_index = page number in get_user_pages return |
| 512 | * data_page_offset = offset with data_page_index page. |
| 513 | * page_length = bytes to copy for this page |
| 514 | */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 515 | shmem_page_offset = offset & ~PAGE_MASK; |
| 516 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 517 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 518 | |
| 519 | page_length = remain; |
| 520 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 521 | page_length = PAGE_SIZE - shmem_page_offset; |
| 522 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 523 | page_length = PAGE_SIZE - data_page_offset; |
| 524 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 525 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
| 526 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 527 | if (IS_ERR(page)) |
| 528 | return PTR_ERR(page); |
| 529 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 530 | if (do_bit17_swizzling) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 531 | slow_shmem_bit17_copy(page, |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 532 | shmem_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 533 | user_pages[data_page_index], |
| 534 | data_page_offset, |
| 535 | page_length, |
| 536 | 1); |
| 537 | } else { |
| 538 | slow_shmem_copy(user_pages[data_page_index], |
| 539 | data_page_offset, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 540 | page, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 541 | shmem_page_offset, |
| 542 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 543 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 544 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 545 | mark_page_accessed(page); |
| 546 | page_cache_release(page); |
| 547 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 548 | remain -= page_length; |
| 549 | data_ptr += page_length; |
| 550 | offset += page_length; |
| 551 | } |
| 552 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 553 | out: |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 554 | for (i = 0; i < pinned_pages; i++) { |
| 555 | SetPageDirty(user_pages[i]); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 556 | mark_page_accessed(user_pages[i]); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 557 | page_cache_release(user_pages[i]); |
| 558 | } |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 559 | drm_free_large(user_pages); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 560 | |
| 561 | return ret; |
| 562 | } |
| 563 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 564 | /** |
| 565 | * Reads data from the object referenced by handle. |
| 566 | * |
| 567 | * On error, the contents of *data are undefined. |
| 568 | */ |
| 569 | int |
| 570 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 571 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 572 | { |
| 573 | struct drm_i915_gem_pread *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 574 | struct drm_i915_gem_object *obj; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 575 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 576 | |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 577 | if (args->size == 0) |
| 578 | return 0; |
| 579 | |
| 580 | if (!access_ok(VERIFY_WRITE, |
| 581 | (char __user *)(uintptr_t)args->data_ptr, |
| 582 | args->size)) |
| 583 | return -EFAULT; |
| 584 | |
| 585 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, |
| 586 | args->size); |
| 587 | if (ret) |
| 588 | return -EFAULT; |
| 589 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 590 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 591 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 592 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 593 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 594 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 595 | if (obj == NULL) { |
| 596 | ret = -ENOENT; |
| 597 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 598 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 599 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 600 | /* Bounds check source. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 601 | if (args->offset > obj->base.size || |
| 602 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 603 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 604 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 605 | } |
| 606 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 607 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
| 608 | args->offset, |
| 609 | args->size); |
| 610 | if (ret) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 611 | goto out; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 612 | |
| 613 | ret = -EFAULT; |
| 614 | if (!i915_gem_object_needs_bit17_swizzle(obj)) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 615 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 616 | if (ret == -EFAULT) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 617 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 618 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 619 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 620 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 621 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 622 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 623 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 624 | } |
| 625 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 626 | /* This is the fast write path which cannot handle |
| 627 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 628 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 629 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 630 | static inline int |
| 631 | fast_user_write(struct io_mapping *mapping, |
| 632 | loff_t page_base, int page_offset, |
| 633 | char __user *user_data, |
| 634 | int length) |
| 635 | { |
| 636 | char *vaddr_atomic; |
| 637 | unsigned long unwritten; |
| 638 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 639 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 640 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
| 641 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 642 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 643 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 644 | } |
| 645 | |
| 646 | /* Here's the write path which can sleep for |
| 647 | * page faults |
| 648 | */ |
| 649 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 650 | static inline void |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 651 | slow_kernel_write(struct io_mapping *mapping, |
| 652 | loff_t gtt_base, int gtt_offset, |
| 653 | struct page *user_page, int user_offset, |
| 654 | int length) |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 655 | { |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 656 | char __iomem *dst_vaddr; |
| 657 | char *src_vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 658 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 659 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
| 660 | src_vaddr = kmap(user_page); |
| 661 | |
| 662 | memcpy_toio(dst_vaddr + gtt_offset, |
| 663 | src_vaddr + user_offset, |
| 664 | length); |
| 665 | |
| 666 | kunmap(user_page); |
| 667 | io_mapping_unmap(dst_vaddr); |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 668 | } |
| 669 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 670 | /** |
| 671 | * This is the fast pwrite path, where we copy the data directly from the |
| 672 | * user into the GTT, uncached. |
| 673 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 674 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 675 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 676 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 677 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 678 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 679 | { |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 680 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 681 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 682 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 683 | char __user *user_data; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 684 | int page_offset, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 685 | |
| 686 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 687 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 688 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 689 | offset = obj->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 690 | |
| 691 | while (remain > 0) { |
| 692 | /* Operation in this page |
| 693 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 694 | * page_base = page offset within aperture |
| 695 | * page_offset = offset within page |
| 696 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 697 | */ |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 698 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 699 | page_offset = offset & (PAGE_SIZE-1); |
| 700 | page_length = remain; |
| 701 | if ((page_offset + remain) > PAGE_SIZE) |
| 702 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 703 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 704 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 705 | * source page isn't available. Return the error and we'll |
| 706 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 707 | */ |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 708 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
| 709 | page_offset, user_data, page_length)) |
| 710 | |
| 711 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 712 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 713 | remain -= page_length; |
| 714 | user_data += page_length; |
| 715 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 716 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 717 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 718 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 719 | } |
| 720 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 721 | /** |
| 722 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin |
| 723 | * the memory and maps it using kmap_atomic for copying. |
| 724 | * |
| 725 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU |
| 726 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). |
| 727 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 728 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 729 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, |
| 730 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 731 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 732 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 733 | { |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 734 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 735 | ssize_t remain; |
| 736 | loff_t gtt_page_base, offset; |
| 737 | loff_t first_data_page, last_data_page, num_pages; |
| 738 | loff_t pinned_pages, i; |
| 739 | struct page **user_pages; |
| 740 | struct mm_struct *mm = current->mm; |
| 741 | int gtt_page_offset, data_page_offset, data_page_index, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 742 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 743 | uint64_t data_ptr = args->data_ptr; |
| 744 | |
| 745 | remain = args->size; |
| 746 | |
| 747 | /* Pin the user pages containing the data. We can't fault while |
| 748 | * holding the struct mutex, and all of the pwrite implementations |
| 749 | * want to hold it while dereferencing the user data. |
| 750 | */ |
| 751 | first_data_page = data_ptr / PAGE_SIZE; |
| 752 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 753 | num_pages = last_data_page - first_data_page + 1; |
| 754 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 755 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 756 | if (user_pages == NULL) |
| 757 | return -ENOMEM; |
| 758 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 759 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 760 | down_read(&mm->mmap_sem); |
| 761 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 762 | num_pages, 0, 0, user_pages, NULL); |
| 763 | up_read(&mm->mmap_sem); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 764 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 765 | if (pinned_pages < num_pages) { |
| 766 | ret = -EFAULT; |
| 767 | goto out_unpin_pages; |
| 768 | } |
| 769 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 770 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 771 | if (ret) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 772 | goto out_unpin_pages; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 773 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 774 | offset = obj->gtt_offset + args->offset; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 775 | |
| 776 | while (remain > 0) { |
| 777 | /* Operation in this page |
| 778 | * |
| 779 | * gtt_page_base = page offset within aperture |
| 780 | * gtt_page_offset = offset within page in aperture |
| 781 | * data_page_index = page number in get_user_pages return |
| 782 | * data_page_offset = offset with data_page_index page. |
| 783 | * page_length = bytes to copy for this page |
| 784 | */ |
| 785 | gtt_page_base = offset & PAGE_MASK; |
| 786 | gtt_page_offset = offset & ~PAGE_MASK; |
| 787 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 788 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 789 | |
| 790 | page_length = remain; |
| 791 | if ((gtt_page_offset + page_length) > PAGE_SIZE) |
| 792 | page_length = PAGE_SIZE - gtt_page_offset; |
| 793 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 794 | page_length = PAGE_SIZE - data_page_offset; |
| 795 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 796 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
| 797 | gtt_page_base, gtt_page_offset, |
| 798 | user_pages[data_page_index], |
| 799 | data_page_offset, |
| 800 | page_length); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 801 | |
| 802 | remain -= page_length; |
| 803 | offset += page_length; |
| 804 | data_ptr += page_length; |
| 805 | } |
| 806 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 807 | out_unpin_pages: |
| 808 | for (i = 0; i < pinned_pages; i++) |
| 809 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 810 | drm_free_large(user_pages); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 811 | |
| 812 | return ret; |
| 813 | } |
| 814 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 815 | /** |
| 816 | * This is the fast shmem pwrite path, which attempts to directly |
| 817 | * copy_from_user into the kmapped pages backing the object. |
| 818 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 819 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 820 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, |
| 821 | struct drm_i915_gem_object *obj, |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 822 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 823 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 824 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 825 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 826 | ssize_t remain; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 827 | loff_t offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 828 | char __user *user_data; |
| 829 | int page_offset, page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 830 | |
| 831 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 832 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 833 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 834 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 835 | obj->dirty = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 836 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 837 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 838 | struct page *page; |
| 839 | char *vaddr; |
| 840 | int ret; |
| 841 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 842 | /* Operation in this page |
| 843 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 844 | * page_offset = offset within page |
| 845 | * page_length = bytes to copy for this page |
| 846 | */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 847 | page_offset = offset & (PAGE_SIZE-1); |
| 848 | page_length = remain; |
| 849 | if ((page_offset + remain) > PAGE_SIZE) |
| 850 | page_length = PAGE_SIZE - page_offset; |
| 851 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 852 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
| 853 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 854 | if (IS_ERR(page)) |
| 855 | return PTR_ERR(page); |
| 856 | |
| 857 | vaddr = kmap_atomic(page, KM_USER0); |
| 858 | ret = __copy_from_user_inatomic(vaddr + page_offset, |
| 859 | user_data, |
| 860 | page_length); |
| 861 | kunmap_atomic(vaddr, KM_USER0); |
| 862 | |
| 863 | set_page_dirty(page); |
| 864 | mark_page_accessed(page); |
| 865 | page_cache_release(page); |
| 866 | |
| 867 | /* If we get a fault while copying data, then (presumably) our |
| 868 | * source page isn't available. Return the error and we'll |
| 869 | * retry in the slow path. |
| 870 | */ |
| 871 | if (ret) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 872 | return -EFAULT; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 873 | |
| 874 | remain -= page_length; |
| 875 | user_data += page_length; |
| 876 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 877 | } |
| 878 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 879 | return 0; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 880 | } |
| 881 | |
| 882 | /** |
| 883 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin |
| 884 | * the memory and maps it using kmap_atomic for copying. |
| 885 | * |
| 886 | * This avoids taking mmap_sem for faulting on the user's address while the |
| 887 | * struct_mutex is held. |
| 888 | */ |
| 889 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 890 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, |
| 891 | struct drm_i915_gem_object *obj, |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 892 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 893 | struct drm_file *file) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 894 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 895 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 896 | struct mm_struct *mm = current->mm; |
| 897 | struct page **user_pages; |
| 898 | ssize_t remain; |
| 899 | loff_t offset, pinned_pages, i; |
| 900 | loff_t first_data_page, last_data_page, num_pages; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 901 | int shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 902 | int data_page_index, data_page_offset; |
| 903 | int page_length; |
| 904 | int ret; |
| 905 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 906 | int do_bit17_swizzling; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 907 | |
| 908 | remain = args->size; |
| 909 | |
| 910 | /* Pin the user pages containing the data. We can't fault while |
| 911 | * holding the struct mutex, and all of the pwrite implementations |
| 912 | * want to hold it while dereferencing the user data. |
| 913 | */ |
| 914 | first_data_page = data_ptr / PAGE_SIZE; |
| 915 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 916 | num_pages = last_data_page - first_data_page + 1; |
| 917 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 918 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 919 | if (user_pages == NULL) |
| 920 | return -ENOMEM; |
| 921 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 922 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 923 | down_read(&mm->mmap_sem); |
| 924 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 925 | num_pages, 0, 0, user_pages, NULL); |
| 926 | up_read(&mm->mmap_sem); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 927 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 928 | if (pinned_pages < num_pages) { |
| 929 | ret = -EFAULT; |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 930 | goto out; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 931 | } |
| 932 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 933 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 934 | if (ret) |
| 935 | goto out; |
| 936 | |
| 937 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 938 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 939 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 940 | obj->dirty = 1; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 941 | |
| 942 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 943 | struct page *page; |
| 944 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 945 | /* Operation in this page |
| 946 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 947 | * shmem_page_offset = offset within page in shmem file |
| 948 | * data_page_index = page number in get_user_pages return |
| 949 | * data_page_offset = offset with data_page_index page. |
| 950 | * page_length = bytes to copy for this page |
| 951 | */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 952 | shmem_page_offset = offset & ~PAGE_MASK; |
| 953 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 954 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 955 | |
| 956 | page_length = remain; |
| 957 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 958 | page_length = PAGE_SIZE - shmem_page_offset; |
| 959 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 960 | page_length = PAGE_SIZE - data_page_offset; |
| 961 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 962 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
| 963 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 964 | if (IS_ERR(page)) { |
| 965 | ret = PTR_ERR(page); |
| 966 | goto out; |
| 967 | } |
| 968 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 969 | if (do_bit17_swizzling) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 970 | slow_shmem_bit17_copy(page, |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 971 | shmem_page_offset, |
| 972 | user_pages[data_page_index], |
| 973 | data_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 974 | page_length, |
| 975 | 0); |
| 976 | } else { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 977 | slow_shmem_copy(page, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 978 | shmem_page_offset, |
| 979 | user_pages[data_page_index], |
| 980 | data_page_offset, |
| 981 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 982 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 983 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 984 | set_page_dirty(page); |
| 985 | mark_page_accessed(page); |
| 986 | page_cache_release(page); |
| 987 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 988 | remain -= page_length; |
| 989 | data_ptr += page_length; |
| 990 | offset += page_length; |
| 991 | } |
| 992 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 993 | out: |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 994 | for (i = 0; i < pinned_pages; i++) |
| 995 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 996 | drm_free_large(user_pages); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 997 | |
| 998 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 999 | } |
| 1000 | |
| 1001 | /** |
| 1002 | * Writes data to the object referenced by handle. |
| 1003 | * |
| 1004 | * On error, the contents of the buffer that were to be modified are undefined. |
| 1005 | */ |
| 1006 | int |
| 1007 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1008 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1009 | { |
| 1010 | struct drm_i915_gem_pwrite *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1011 | struct drm_i915_gem_object *obj; |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 1012 | int ret; |
| 1013 | |
| 1014 | if (args->size == 0) |
| 1015 | return 0; |
| 1016 | |
| 1017 | if (!access_ok(VERIFY_READ, |
| 1018 | (char __user *)(uintptr_t)args->data_ptr, |
| 1019 | args->size)) |
| 1020 | return -EFAULT; |
| 1021 | |
| 1022 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, |
| 1023 | args->size); |
| 1024 | if (ret) |
| 1025 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1026 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1027 | ret = i915_mutex_lock_interruptible(dev); |
| 1028 | if (ret) |
| 1029 | return ret; |
| 1030 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1031 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1032 | if (obj == NULL) { |
| 1033 | ret = -ENOENT; |
| 1034 | goto unlock; |
| 1035 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1036 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 1037 | /* Bounds check destination. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1038 | if (args->offset > obj->base.size || |
| 1039 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1040 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1041 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1042 | } |
| 1043 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1044 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 1045 | * it would end up going through the fenced access, and we'll get |
| 1046 | * different detiling behavior between reading and writing. |
| 1047 | * pread/pwrite currently are reading and writing from the CPU |
| 1048 | * perspective, requiring manual detiling by the client. |
| 1049 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1050 | if (obj->phys_obj) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1051 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1052 | else if (obj->tiling_mode == I915_TILING_NONE && |
| 1053 | obj->gtt_space && |
| 1054 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1055 | ret = i915_gem_object_pin(obj, 0, true); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1056 | if (ret) |
| 1057 | goto out; |
| 1058 | |
| 1059 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 1060 | if (ret) |
| 1061 | goto out_unpin; |
| 1062 | |
| 1063 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
| 1064 | if (ret == -EFAULT) |
| 1065 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); |
| 1066 | |
| 1067 | out_unpin: |
| 1068 | i915_gem_object_unpin(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1069 | } else { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1070 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 1071 | if (ret) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1072 | goto out; |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1073 | |
| 1074 | ret = -EFAULT; |
| 1075 | if (!i915_gem_object_needs_bit17_swizzle(obj)) |
| 1076 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); |
| 1077 | if (ret == -EFAULT) |
| 1078 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1079 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1080 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1081 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1082 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1083 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1084 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1085 | return ret; |
| 1086 | } |
| 1087 | |
| 1088 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1089 | * Called when user space prepares to use an object with the CPU, either |
| 1090 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1091 | */ |
| 1092 | int |
| 1093 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1094 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1095 | { |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1096 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1097 | struct drm_i915_gem_set_domain *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1098 | struct drm_i915_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1099 | uint32_t read_domains = args->read_domains; |
| 1100 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1101 | int ret; |
| 1102 | |
| 1103 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1104 | return -ENODEV; |
| 1105 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1106 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1107 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1108 | return -EINVAL; |
| 1109 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1110 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1111 | return -EINVAL; |
| 1112 | |
| 1113 | /* Having something in the write domain implies it's in the read |
| 1114 | * domain, and only that read domain. Enforce that in the request. |
| 1115 | */ |
| 1116 | if (write_domain != 0 && read_domains != write_domain) |
| 1117 | return -EINVAL; |
| 1118 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1119 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1120 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1121 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1122 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1123 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1124 | if (obj == NULL) { |
| 1125 | ret = -ENOENT; |
| 1126 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1127 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1128 | |
| 1129 | intel_mark_busy(dev, obj); |
| 1130 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1131 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1132 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1133 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1134 | /* Update the LRU on the fence for the CPU access that's |
| 1135 | * about to occur. |
| 1136 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1137 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1138 | struct drm_i915_fence_reg *reg = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1139 | &dev_priv->fence_regs[obj->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1140 | list_move_tail(®->lru_list, |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1141 | &dev_priv->mm.fence_list); |
| 1142 | } |
| 1143 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1144 | /* Silently promote "you're not bound, there was nothing to do" |
| 1145 | * to success, since the client was just asking us to |
| 1146 | * make sure everything was done. |
| 1147 | */ |
| 1148 | if (ret == -EINVAL) |
| 1149 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1150 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1151 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1152 | } |
| 1153 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1154 | /* Maintain LRU order of "inactive" objects */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1155 | if (ret == 0 && i915_gem_object_is_inactive(obj)) |
| 1156 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1157 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1158 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1159 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1160 | mutex_unlock(&dev->struct_mutex); |
| 1161 | return ret; |
| 1162 | } |
| 1163 | |
| 1164 | /** |
| 1165 | * Called when user space has done writes to this buffer |
| 1166 | */ |
| 1167 | int |
| 1168 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1169 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1170 | { |
| 1171 | struct drm_i915_gem_sw_finish *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1172 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1173 | int ret = 0; |
| 1174 | |
| 1175 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1176 | return -ENODEV; |
| 1177 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1178 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1179 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1180 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1181 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1182 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1183 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1184 | ret = -ENOENT; |
| 1185 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1186 | } |
| 1187 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1188 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1189 | if (obj->pin_count) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1190 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1191 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1192 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1193 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1194 | mutex_unlock(&dev->struct_mutex); |
| 1195 | return ret; |
| 1196 | } |
| 1197 | |
| 1198 | /** |
| 1199 | * Maps the contents of an object, returning the address it is mapped |
| 1200 | * into. |
| 1201 | * |
| 1202 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1203 | * imply a ref on the object itself. |
| 1204 | */ |
| 1205 | int |
| 1206 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1207 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1208 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1209 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1210 | struct drm_i915_gem_mmap *args = data; |
| 1211 | struct drm_gem_object *obj; |
| 1212 | loff_t offset; |
| 1213 | unsigned long addr; |
| 1214 | |
| 1215 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1216 | return -ENODEV; |
| 1217 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1218 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1219 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1220 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1221 | |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1222 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
| 1223 | drm_gem_object_unreference_unlocked(obj); |
| 1224 | return -E2BIG; |
| 1225 | } |
| 1226 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1227 | offset = args->offset; |
| 1228 | |
| 1229 | down_write(¤t->mm->mmap_sem); |
| 1230 | addr = do_mmap(obj->filp, 0, args->size, |
| 1231 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1232 | args->offset); |
| 1233 | up_write(¤t->mm->mmap_sem); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1234 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1235 | if (IS_ERR((void *)addr)) |
| 1236 | return addr; |
| 1237 | |
| 1238 | args->addr_ptr = (uint64_t) addr; |
| 1239 | |
| 1240 | return 0; |
| 1241 | } |
| 1242 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1243 | /** |
| 1244 | * i915_gem_fault - fault a page into the GTT |
| 1245 | * vma: VMA in question |
| 1246 | * vmf: fault info |
| 1247 | * |
| 1248 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1249 | * from userspace. The fault handler takes care of binding the object to |
| 1250 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1251 | * only if needed based on whether the old reg is still valid or the object |
| 1252 | * is tiled) and inserting a new PTE into the faulting process. |
| 1253 | * |
| 1254 | * Note that the faulting process may involve evicting existing objects |
| 1255 | * from the GTT and/or fence registers to make room. So performance may |
| 1256 | * suffer if the GTT working set is large or there are few fence registers |
| 1257 | * left. |
| 1258 | */ |
| 1259 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1260 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1261 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1262 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1263 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1264 | pgoff_t page_offset; |
| 1265 | unsigned long pfn; |
| 1266 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1267 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1268 | |
| 1269 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1270 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1271 | PAGE_SHIFT; |
| 1272 | |
| 1273 | /* Now bind it into the GTT if needed */ |
| 1274 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1275 | BUG_ON(obj->pin_count && !obj->pin_mappable); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1276 | |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 1277 | if (!obj->map_and_fenceable) { |
| 1278 | ret = i915_gem_object_unbind(obj); |
| 1279 | if (ret) |
| 1280 | goto unlock; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1281 | } |
Daniel Vetter | 16e809a | 2010-09-16 19:37:04 +0200 | [diff] [blame] | 1282 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1283 | if (!obj->gtt_space) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1284 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1285 | if (ret) |
| 1286 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1287 | } |
| 1288 | |
Chris Wilson | 4a684a4 | 2010-10-28 14:44:08 +0100 | [diff] [blame] | 1289 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1290 | if (ret) |
| 1291 | goto unlock; |
| 1292 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1293 | if (!obj->fault_mappable) { |
| 1294 | obj->fault_mappable = true; |
| 1295 | i915_gem_info_update_mappable(dev_priv, obj, true); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1296 | } |
| 1297 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1298 | /* Need a new fence register? */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1299 | if (obj->tiling_mode != I915_TILING_NONE) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 1300 | ret = i915_gem_object_get_fence_reg(obj, true); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1301 | if (ret) |
| 1302 | goto unlock; |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 1303 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1304 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1305 | if (i915_gem_object_is_inactive(obj)) |
| 1306 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1307 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1308 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1309 | page_offset; |
| 1310 | |
| 1311 | /* Finally, remap it using the new GTT offset */ |
| 1312 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1313 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1314 | mutex_unlock(&dev->struct_mutex); |
| 1315 | |
| 1316 | switch (ret) { |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1317 | case -EAGAIN: |
| 1318 | set_need_resched(); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1319 | case 0: |
| 1320 | case -ERESTARTSYS: |
| 1321 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1322 | case -ENOMEM: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1323 | return VM_FAULT_OOM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1324 | default: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1325 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1326 | } |
| 1327 | } |
| 1328 | |
| 1329 | /** |
| 1330 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object |
| 1331 | * @obj: obj in question |
| 1332 | * |
| 1333 | * GEM memory mapping works by handing back to userspace a fake mmap offset |
| 1334 | * it can use in a subsequent mmap(2) call. The DRM core code then looks |
| 1335 | * up the object based on the offset and sets up the various memory mapping |
| 1336 | * structures. |
| 1337 | * |
| 1338 | * This routine allocates and attaches a fake offset for @obj. |
| 1339 | */ |
| 1340 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1341 | i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1342 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1343 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1344 | struct drm_gem_mm *mm = dev->mm_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1345 | struct drm_map_list *list; |
Benjamin Herrenschmidt | f77d390 | 2009-02-02 16:55:46 +1100 | [diff] [blame] | 1346 | struct drm_local_map *map; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1347 | int ret = 0; |
| 1348 | |
| 1349 | /* Set the object up for mmap'ing */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1350 | list = &obj->base.map_list; |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1351 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1352 | if (!list->map) |
| 1353 | return -ENOMEM; |
| 1354 | |
| 1355 | map = list->map; |
| 1356 | map->type = _DRM_GEM; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1357 | map->size = obj->base.size; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1358 | map->handle = obj; |
| 1359 | |
| 1360 | /* Get a DRM GEM mmap offset allocated... */ |
| 1361 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1362 | obj->base.size / PAGE_SIZE, |
| 1363 | 0, 0); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1364 | if (!list->file_offset_node) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1365 | DRM_ERROR("failed to allocate offset for bo %d\n", |
| 1366 | obj->base.name); |
Chris Wilson | 9e0ae534 | 2010-09-21 15:05:24 +0100 | [diff] [blame] | 1367 | ret = -ENOSPC; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1368 | goto out_free_list; |
| 1369 | } |
| 1370 | |
| 1371 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1372 | obj->base.size / PAGE_SIZE, |
| 1373 | 0); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1374 | if (!list->file_offset_node) { |
| 1375 | ret = -ENOMEM; |
| 1376 | goto out_free_list; |
| 1377 | } |
| 1378 | |
| 1379 | list->hash.key = list->file_offset_node->start; |
Chris Wilson | 9e0ae534 | 2010-09-21 15:05:24 +0100 | [diff] [blame] | 1380 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
| 1381 | if (ret) { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1382 | DRM_ERROR("failed to add to map hash\n"); |
| 1383 | goto out_free_mm; |
| 1384 | } |
| 1385 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1386 | return 0; |
| 1387 | |
| 1388 | out_free_mm: |
| 1389 | drm_mm_put_block(list->file_offset_node); |
| 1390 | out_free_list: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1391 | kfree(list->map); |
Chris Wilson | 39a01d1 | 2010-10-28 13:03:06 +0100 | [diff] [blame] | 1392 | list->map = NULL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1393 | |
| 1394 | return ret; |
| 1395 | } |
| 1396 | |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1397 | /** |
| 1398 | * i915_gem_release_mmap - remove physical page mappings |
| 1399 | * @obj: obj in question |
| 1400 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1401 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1402 | * relinquish ownership of the pages back to the system. |
| 1403 | * |
| 1404 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1405 | * object through the GTT and then lose the fence register due to |
| 1406 | * resource pressure. Similarly if the object has been moved out of the |
| 1407 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1408 | * mapping will then trigger a page fault on the next user access, allowing |
| 1409 | * fixup by i915_gem_fault(). |
| 1410 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1411 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1412 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1413 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1414 | struct drm_device *dev = obj->base.dev; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1415 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1416 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1417 | if (unlikely(obj->base.map_list.map && dev->dev_mapping)) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1418 | unmap_mapping_range(dev->dev_mapping, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1419 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, |
| 1420 | obj->base.size, 1); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1421 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1422 | if (obj->fault_mappable) { |
| 1423 | obj->fault_mappable = false; |
| 1424 | i915_gem_info_update_mappable(dev_priv, obj, false); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1425 | } |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1426 | } |
| 1427 | |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1428 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1429 | i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj) |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1430 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1431 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1432 | struct drm_gem_mm *mm = dev->mm_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1433 | struct drm_map_list *list = &obj->base.map_list; |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1434 | |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1435 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
Chris Wilson | 39a01d1 | 2010-10-28 13:03:06 +0100 | [diff] [blame] | 1436 | drm_mm_put_block(list->file_offset_node); |
| 1437 | kfree(list->map); |
| 1438 | list->map = NULL; |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1439 | } |
| 1440 | |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1441 | static uint32_t |
| 1442 | i915_gem_get_gtt_size(struct drm_i915_gem_object *obj) |
| 1443 | { |
| 1444 | struct drm_device *dev = obj->base.dev; |
| 1445 | uint32_t size; |
| 1446 | |
| 1447 | if (INTEL_INFO(dev)->gen >= 4 || |
| 1448 | obj->tiling_mode == I915_TILING_NONE) |
| 1449 | return obj->base.size; |
| 1450 | |
| 1451 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1452 | if (INTEL_INFO(dev)->gen == 3) |
| 1453 | size = 1024*1024; |
| 1454 | else |
| 1455 | size = 512*1024; |
| 1456 | |
| 1457 | while (size < obj->base.size) |
| 1458 | size <<= 1; |
| 1459 | |
| 1460 | return size; |
| 1461 | } |
| 1462 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1463 | /** |
| 1464 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1465 | * @obj: object to check |
| 1466 | * |
| 1467 | * Return the required GTT alignment for an object, taking into account |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1468 | * potential fence register mapping. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1469 | */ |
| 1470 | static uint32_t |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1471 | i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1472 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1473 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1474 | |
| 1475 | /* |
| 1476 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1477 | * if a fence register is needed for the object. |
| 1478 | */ |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1479 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1480 | obj->tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1481 | return 4096; |
| 1482 | |
| 1483 | /* |
| 1484 | * Previous chips need to be aligned to the size of the smallest |
| 1485 | * fence register that can contain the object. |
| 1486 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1487 | return i915_gem_get_gtt_size(obj); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1488 | } |
| 1489 | |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1490 | /** |
| 1491 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an |
| 1492 | * unfenced object |
| 1493 | * @obj: object to check |
| 1494 | * |
| 1495 | * Return the required GTT alignment for an object, only taking into account |
| 1496 | * unfenced tiled surface requirements. |
| 1497 | */ |
| 1498 | static uint32_t |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1499 | i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1500 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1501 | struct drm_device *dev = obj->base.dev; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1502 | int tile_height; |
| 1503 | |
| 1504 | /* |
| 1505 | * Minimum alignment is 4k (GTT page size) for sane hw. |
| 1506 | */ |
| 1507 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1508 | obj->tiling_mode == I915_TILING_NONE) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1509 | return 4096; |
| 1510 | |
| 1511 | /* |
| 1512 | * Older chips need unfenced tiled buffers to be aligned to the left |
| 1513 | * edge of an even tile row (where tile rows are counted as if the bo is |
| 1514 | * placed in a fenced gtt region). |
| 1515 | */ |
| 1516 | if (IS_GEN2(dev) || |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1517 | (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1518 | tile_height = 32; |
| 1519 | else |
| 1520 | tile_height = 8; |
| 1521 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1522 | return tile_height * obj->stride * 2; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1523 | } |
| 1524 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1525 | /** |
| 1526 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1527 | * @dev: DRM device |
| 1528 | * @data: GTT mapping ioctl data |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1529 | * @file: GEM object info |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1530 | * |
| 1531 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1532 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1533 | * up so we can get faults in the handler above. |
| 1534 | * |
| 1535 | * The fault handler will take care of binding the object into the GTT |
| 1536 | * (since it may have been evicted to make room for something), allocating |
| 1537 | * a fence register, and mapping the appropriate aperture address into |
| 1538 | * userspace. |
| 1539 | */ |
| 1540 | int |
| 1541 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1542 | struct drm_file *file) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1543 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1544 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1545 | struct drm_i915_gem_mmap_gtt *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1546 | struct drm_i915_gem_object *obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1547 | int ret; |
| 1548 | |
| 1549 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1550 | return -ENODEV; |
| 1551 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1552 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1553 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1554 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1555 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1556 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1557 | if (obj == NULL) { |
| 1558 | ret = -ENOENT; |
| 1559 | goto unlock; |
| 1560 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1561 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1562 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1563 | ret = -E2BIG; |
| 1564 | goto unlock; |
| 1565 | } |
| 1566 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1567 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1568 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1569 | ret = -EINVAL; |
| 1570 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1571 | } |
| 1572 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1573 | if (!obj->base.map_list.map) { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1574 | ret = i915_gem_create_mmap_offset(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1575 | if (ret) |
| 1576 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1577 | } |
| 1578 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1579 | args->offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1580 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1581 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1582 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1583 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1584 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1585 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1586 | } |
| 1587 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1588 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1589 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1590 | gfp_t gfpmask) |
| 1591 | { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1592 | int page_count, i; |
| 1593 | struct address_space *mapping; |
| 1594 | struct inode *inode; |
| 1595 | struct page *page; |
| 1596 | |
| 1597 | /* Get the list of pages out of our struct file. They'll be pinned |
| 1598 | * at this point until we release them. |
| 1599 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1600 | page_count = obj->base.size / PAGE_SIZE; |
| 1601 | BUG_ON(obj->pages != NULL); |
| 1602 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); |
| 1603 | if (obj->pages == NULL) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1604 | return -ENOMEM; |
| 1605 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1606 | inode = obj->base.filp->f_path.dentry->d_inode; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1607 | mapping = inode->i_mapping; |
| 1608 | for (i = 0; i < page_count; i++) { |
| 1609 | page = read_cache_page_gfp(mapping, i, |
| 1610 | GFP_HIGHUSER | |
| 1611 | __GFP_COLD | |
| 1612 | __GFP_RECLAIMABLE | |
| 1613 | gfpmask); |
| 1614 | if (IS_ERR(page)) |
| 1615 | goto err_pages; |
| 1616 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1617 | obj->pages[i] = page; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1618 | } |
| 1619 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1620 | if (obj->tiling_mode != I915_TILING_NONE) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1621 | i915_gem_object_do_bit_17_swizzle(obj); |
| 1622 | |
| 1623 | return 0; |
| 1624 | |
| 1625 | err_pages: |
| 1626 | while (i--) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1627 | page_cache_release(obj->pages[i]); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1628 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1629 | drm_free_large(obj->pages); |
| 1630 | obj->pages = NULL; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1631 | return PTR_ERR(page); |
| 1632 | } |
| 1633 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1634 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1635 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1636 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1637 | int page_count = obj->base.size / PAGE_SIZE; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1638 | int i; |
| 1639 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1640 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1641 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1642 | if (obj->tiling_mode != I915_TILING_NONE) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1643 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1644 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1645 | if (obj->madv == I915_MADV_DONTNEED) |
| 1646 | obj->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1647 | |
| 1648 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1649 | if (obj->dirty) |
| 1650 | set_page_dirty(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1651 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1652 | if (obj->madv == I915_MADV_WILLNEED) |
| 1653 | mark_page_accessed(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1654 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1655 | page_cache_release(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1656 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1657 | obj->dirty = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1658 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1659 | drm_free_large(obj->pages); |
| 1660 | obj->pages = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1661 | } |
| 1662 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1663 | static uint32_t |
| 1664 | i915_gem_next_request_seqno(struct drm_device *dev, |
| 1665 | struct intel_ring_buffer *ring) |
| 1666 | { |
| 1667 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 5d97eb6 | 2010-11-10 20:40:02 +0000 | [diff] [blame] | 1668 | return ring->outstanding_lazy_request = dev_priv->next_seqno; |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1669 | } |
| 1670 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1671 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1672 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1673 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1674 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1675 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1676 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1677 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1678 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1679 | BUG_ON(ring == NULL); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1680 | obj->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1681 | |
| 1682 | /* Add a reference if we're newly entering the active list. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1683 | if (!obj->active) { |
| 1684 | drm_gem_object_reference(&obj->base); |
| 1685 | obj->active = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1686 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1687 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1688 | /* Move from whatever list we were on to the tail of execution. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1689 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
| 1690 | list_move_tail(&obj->ring_list, &ring->active_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1691 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1692 | obj->last_rendering_seqno = seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1693 | if (obj->fenced_gpu_access) { |
| 1694 | struct drm_i915_fence_reg *reg; |
| 1695 | |
| 1696 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); |
| 1697 | |
| 1698 | obj->last_fenced_seqno = seqno; |
| 1699 | obj->last_fenced_ring = ring; |
| 1700 | |
| 1701 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
| 1702 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
| 1703 | } |
| 1704 | } |
| 1705 | |
| 1706 | static void |
| 1707 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) |
| 1708 | { |
| 1709 | list_del_init(&obj->ring_list); |
| 1710 | obj->last_rendering_seqno = 0; |
| 1711 | obj->last_fenced_seqno = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1712 | } |
| 1713 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1714 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1715 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1716 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1717 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1718 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1719 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1720 | BUG_ON(!obj->active); |
| 1721 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1722 | |
| 1723 | i915_gem_object_move_off_active(obj); |
| 1724 | } |
| 1725 | |
| 1726 | static void |
| 1727 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
| 1728 | { |
| 1729 | struct drm_device *dev = obj->base.dev; |
| 1730 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1731 | |
| 1732 | if (obj->pin_count != 0) |
| 1733 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); |
| 1734 | else |
| 1735 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
| 1736 | |
| 1737 | BUG_ON(!list_empty(&obj->gpu_write_list)); |
| 1738 | BUG_ON(!obj->active); |
| 1739 | obj->ring = NULL; |
| 1740 | |
| 1741 | i915_gem_object_move_off_active(obj); |
| 1742 | obj->fenced_gpu_access = false; |
| 1743 | obj->last_fenced_ring = NULL; |
| 1744 | |
| 1745 | obj->active = 0; |
| 1746 | drm_gem_object_unreference(&obj->base); |
| 1747 | |
| 1748 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1749 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1750 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1751 | /* Immediately discard the backing storage */ |
| 1752 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1753 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1754 | { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1755 | struct inode *inode; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1756 | |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1757 | /* Our goal here is to return as much of the memory as |
| 1758 | * is possible back to the system as we are called from OOM. |
| 1759 | * To do this we must instruct the shmfs to drop all of its |
| 1760 | * backing pages, *now*. Here we mirror the actions taken |
| 1761 | * when by shmem_delete_inode() to release the backing store. |
| 1762 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1763 | inode = obj->base.filp->f_path.dentry->d_inode; |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1764 | truncate_inode_pages(inode->i_mapping, 0); |
| 1765 | if (inode->i_op->truncate_range) |
| 1766 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1767 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1768 | obj->madv = __I915_MADV_PURGED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1769 | } |
| 1770 | |
| 1771 | static inline int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1772 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1773 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1774 | return obj->madv == I915_MADV_DONTNEED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1775 | } |
| 1776 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1777 | static void |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1778 | i915_gem_process_flushing_list(struct drm_device *dev, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1779 | uint32_t flush_domains, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1780 | struct intel_ring_buffer *ring) |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1781 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1782 | struct drm_i915_gem_object *obj, *next; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1783 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1784 | list_for_each_entry_safe(obj, next, |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 1785 | &ring->gpu_write_list, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1786 | gpu_write_list) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1787 | if (obj->base.write_domain & flush_domains) { |
| 1788 | uint32_t old_write_domain = obj->base.write_domain; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1789 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1790 | obj->base.write_domain = 0; |
| 1791 | list_del_init(&obj->gpu_write_list); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1792 | i915_gem_object_move_to_active(obj, ring); |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1793 | |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1794 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1795 | obj->base.read_domains, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1796 | old_write_domain); |
| 1797 | } |
| 1798 | } |
| 1799 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1800 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1801 | int |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1802 | i915_add_request(struct drm_device *dev, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1803 | struct drm_file *file, |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 1804 | struct drm_i915_gem_request *request, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1805 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1806 | { |
| 1807 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1808 | struct drm_i915_file_private *file_priv = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1809 | uint32_t seqno; |
| 1810 | int was_empty; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1811 | int ret; |
| 1812 | |
| 1813 | BUG_ON(request == NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1814 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1815 | if (file != NULL) |
| 1816 | file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1817 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1818 | ret = ring->add_request(ring, &seqno); |
| 1819 | if (ret) |
| 1820 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1821 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1822 | ring->outstanding_lazy_request = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1823 | |
| 1824 | request->seqno = seqno; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1825 | request->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1826 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1827 | was_empty = list_empty(&ring->request_list); |
| 1828 | list_add_tail(&request->list, &ring->request_list); |
| 1829 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1830 | if (file_priv) { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1831 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1832 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1833 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1834 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1835 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1836 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1837 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1838 | if (!dev_priv->mm.suspended) { |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1839 | mod_timer(&dev_priv->hangcheck_timer, |
| 1840 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1841 | if (was_empty) |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1842 | queue_delayed_work(dev_priv->wq, |
| 1843 | &dev_priv->mm.retire_work, HZ); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1844 | } |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1845 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1846 | } |
| 1847 | |
| 1848 | /** |
| 1849 | * Command execution barrier |
| 1850 | * |
| 1851 | * Ensures that all commands in the ring are finished |
| 1852 | * before signalling the CPU |
| 1853 | */ |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1854 | static void |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1855 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1856 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1857 | uint32_t flush_domains = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1858 | |
| 1859 | /* The sampler always gets flushed on i965 (sigh) */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1860 | if (INTEL_INFO(dev)->gen >= 4) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1861 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1862 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1863 | ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1864 | } |
| 1865 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1866 | static inline void |
| 1867 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1868 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1869 | struct drm_i915_file_private *file_priv = request->file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1870 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1871 | if (!file_priv) |
| 1872 | return; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1873 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1874 | spin_lock(&file_priv->mm.lock); |
| 1875 | list_del(&request->client_list); |
| 1876 | request->file_priv = NULL; |
| 1877 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1878 | } |
| 1879 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1880 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
| 1881 | struct intel_ring_buffer *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1882 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1883 | while (!list_empty(&ring->request_list)) { |
| 1884 | struct drm_i915_gem_request *request; |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1885 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1886 | request = list_first_entry(&ring->request_list, |
| 1887 | struct drm_i915_gem_request, |
| 1888 | list); |
| 1889 | |
| 1890 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1891 | i915_gem_request_remove_from_client(request); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1892 | kfree(request); |
| 1893 | } |
| 1894 | |
| 1895 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1896 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1897 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1898 | obj = list_first_entry(&ring->active_list, |
| 1899 | struct drm_i915_gem_object, |
| 1900 | ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1901 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1902 | obj->base.write_domain = 0; |
| 1903 | list_del_init(&obj->gpu_write_list); |
| 1904 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1905 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1906 | } |
| 1907 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1908 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1909 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1910 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1911 | struct drm_i915_gem_object *obj; |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1912 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1913 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1914 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 1915 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1916 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1917 | |
| 1918 | /* Remove anything from the flushing lists. The GPU cache is likely |
| 1919 | * to be lost on reset along with the data, so simply move the |
| 1920 | * lost bo to the inactive list. |
| 1921 | */ |
| 1922 | while (!list_empty(&dev_priv->mm.flushing_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1923 | obj= list_first_entry(&dev_priv->mm.flushing_list, |
| 1924 | struct drm_i915_gem_object, |
| 1925 | mm_list); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1926 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1927 | obj->base.write_domain = 0; |
| 1928 | list_del_init(&obj->gpu_write_list); |
| 1929 | i915_gem_object_move_to_inactive(obj); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1930 | } |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1931 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1932 | /* Move everything out of the GPU domains to ensure we do any |
| 1933 | * necessary invalidation upon reuse. |
| 1934 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1935 | list_for_each_entry(obj, |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1936 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1937 | mm_list) |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1938 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1939 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1940 | } |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1941 | |
| 1942 | /* The fence registers are invalidated so clear them out */ |
| 1943 | for (i = 0; i < 16; i++) { |
| 1944 | struct drm_i915_fence_reg *reg; |
| 1945 | |
| 1946 | reg = &dev_priv->fence_regs[i]; |
| 1947 | if (!reg->obj) |
| 1948 | continue; |
| 1949 | |
| 1950 | i915_gem_clear_fence_reg(reg->obj); |
| 1951 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1952 | } |
| 1953 | |
| 1954 | /** |
| 1955 | * This function clears the request list as sequence numbers are passed. |
| 1956 | */ |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1957 | static void |
| 1958 | i915_gem_retire_requests_ring(struct drm_device *dev, |
| 1959 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1960 | { |
| 1961 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1962 | uint32_t seqno; |
| 1963 | |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1964 | if (!ring->status_page.page_addr || |
| 1965 | list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 1966 | return; |
| 1967 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1968 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1969 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1970 | seqno = ring->get_seqno(ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1971 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1972 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1973 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1974 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1975 | struct drm_i915_gem_request, |
| 1976 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1977 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1978 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1979 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1980 | |
| 1981 | trace_i915_gem_request_retire(dev, request->seqno); |
| 1982 | |
| 1983 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1984 | i915_gem_request_remove_from_client(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1985 | kfree(request); |
| 1986 | } |
| 1987 | |
| 1988 | /* Move any buffers on the active list that are no longer referenced |
| 1989 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 1990 | */ |
| 1991 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1992 | struct drm_i915_gem_object *obj; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1993 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1994 | obj= list_first_entry(&ring->active_list, |
| 1995 | struct drm_i915_gem_object, |
| 1996 | ring_list); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1997 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1998 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1999 | break; |
| 2000 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2001 | if (obj->base.write_domain != 0) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2002 | i915_gem_object_move_to_flushing(obj); |
| 2003 | else |
| 2004 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2005 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 2006 | |
| 2007 | if (unlikely (dev_priv->trace_irq_seqno && |
| 2008 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2009 | ring->user_irq_put(ring); |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 2010 | dev_priv->trace_irq_seqno = 0; |
| 2011 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 2012 | |
| 2013 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2014 | } |
| 2015 | |
| 2016 | void |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2017 | i915_gem_retire_requests(struct drm_device *dev) |
| 2018 | { |
| 2019 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2020 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 2021 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2022 | struct drm_i915_gem_object *obj, *next; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 2023 | |
| 2024 | /* We must be careful that during unbind() we do not |
| 2025 | * accidentally infinitely recurse into retire requests. |
| 2026 | * Currently: |
| 2027 | * retire -> free -> unbind -> wait -> retire_ring |
| 2028 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2029 | list_for_each_entry_safe(obj, next, |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 2030 | &dev_priv->mm.deferred_free_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 2031 | mm_list) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2032 | i915_gem_free_object_tail(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 2033 | } |
| 2034 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2035 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 2036 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2037 | i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2038 | } |
| 2039 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 2040 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2041 | i915_gem_retire_work_handler(struct work_struct *work) |
| 2042 | { |
| 2043 | drm_i915_private_t *dev_priv; |
| 2044 | struct drm_device *dev; |
| 2045 | |
| 2046 | dev_priv = container_of(work, drm_i915_private_t, |
| 2047 | mm.retire_work.work); |
| 2048 | dev = dev_priv->dev; |
| 2049 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 2050 | /* Come back later if the device is busy... */ |
| 2051 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 2052 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 2053 | return; |
| 2054 | } |
| 2055 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2056 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2057 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 2058 | if (!dev_priv->mm.suspended && |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2059 | (!list_empty(&dev_priv->render_ring.request_list) || |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2060 | !list_empty(&dev_priv->bsd_ring.request_list) || |
| 2061 | !list_empty(&dev_priv->blt_ring.request_list))) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 2062 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2063 | mutex_unlock(&dev->struct_mutex); |
| 2064 | } |
| 2065 | |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 2066 | int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2067 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2068 | bool interruptible, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2069 | { |
| 2070 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 2071 | u32 ier; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2072 | int ret = 0; |
| 2073 | |
| 2074 | BUG_ON(seqno == 0); |
| 2075 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 2076 | if (atomic_read(&dev_priv->mm.wedged)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 2077 | return -EAGAIN; |
Ben Gamari | ffed1d0 | 2009-09-14 17:48:41 -0400 | [diff] [blame] | 2078 | |
Chris Wilson | 5d97eb6 | 2010-11-10 20:40:02 +0000 | [diff] [blame] | 2079 | if (seqno == ring->outstanding_lazy_request) { |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2080 | struct drm_i915_gem_request *request; |
| 2081 | |
| 2082 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 2083 | if (request == NULL) |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2084 | return -ENOMEM; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2085 | |
| 2086 | ret = i915_add_request(dev, NULL, request, ring); |
| 2087 | if (ret) { |
| 2088 | kfree(request); |
| 2089 | return ret; |
| 2090 | } |
| 2091 | |
| 2092 | seqno = request->seqno; |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2093 | } |
| 2094 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2095 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 2096 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2097 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
| 2098 | else |
| 2099 | ier = I915_READ(IER); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 2100 | if (!ier) { |
| 2101 | DRM_ERROR("something (likely vbetool) disabled " |
| 2102 | "interrupts, re-enabling\n"); |
| 2103 | i915_driver_irq_preinstall(dev); |
| 2104 | i915_driver_irq_postinstall(dev); |
| 2105 | } |
| 2106 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2107 | trace_i915_gem_request_wait_begin(dev, seqno); |
| 2108 | |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 2109 | ring->waiting_seqno = seqno; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2110 | ring->user_irq_get(ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2111 | if (interruptible) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2112 | ret = wait_event_interruptible(ring->irq_queue, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2113 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2114 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2115 | else |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2116 | wait_event(ring->irq_queue, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2117 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2118 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2119 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2120 | ring->user_irq_put(ring); |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 2121 | ring->waiting_seqno = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2122 | |
| 2123 | trace_i915_gem_request_wait_end(dev, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2124 | } |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 2125 | if (atomic_read(&dev_priv->mm.wedged)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 2126 | ret = -EAGAIN; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2127 | |
| 2128 | if (ret && ret != -ERESTARTSYS) |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2129 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2130 | __func__, ret, seqno, ring->get_seqno(ring), |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2131 | dev_priv->next_seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2132 | |
| 2133 | /* Directly dispatch request retiring. While we have the work queue |
| 2134 | * to handle this, the waiter on a request often wants an associated |
| 2135 | * buffer to have made it to the inactive list, and we would need |
| 2136 | * a separate wait queue to handle that. |
| 2137 | */ |
| 2138 | if (ret == 0) |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2139 | i915_gem_retire_requests_ring(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2140 | |
| 2141 | return ret; |
| 2142 | } |
| 2143 | |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2144 | /** |
| 2145 | * Waits for a sequence number to be signaled, and cleans up the |
| 2146 | * request and object lists appropriately for that event. |
| 2147 | */ |
| 2148 | static int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2149 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2150 | struct intel_ring_buffer *ring) |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2151 | { |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2152 | return i915_do_wait_request(dev, seqno, 1, ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2153 | } |
| 2154 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2155 | static void |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2156 | i915_gem_flush_ring(struct drm_device *dev, |
| 2157 | struct intel_ring_buffer *ring, |
| 2158 | uint32_t invalidate_domains, |
| 2159 | uint32_t flush_domains) |
| 2160 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2161 | ring->flush(ring, invalidate_domains, flush_domains); |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2162 | i915_gem_process_flushing_list(dev, flush_domains, ring); |
| 2163 | } |
| 2164 | |
| 2165 | static void |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2166 | i915_gem_flush(struct drm_device *dev, |
| 2167 | uint32_t invalidate_domains, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2168 | uint32_t flush_domains, |
| 2169 | uint32_t flush_rings) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2170 | { |
| 2171 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2172 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2173 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 2174 | intel_gtt_chipset_flush(); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2175 | |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2176 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
| 2177 | if (flush_rings & RING_RENDER) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2178 | i915_gem_flush_ring(dev, &dev_priv->render_ring, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2179 | invalidate_domains, flush_domains); |
| 2180 | if (flush_rings & RING_BSD) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2181 | i915_gem_flush_ring(dev, &dev_priv->bsd_ring, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2182 | invalidate_domains, flush_domains); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2183 | if (flush_rings & RING_BLT) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2184 | i915_gem_flush_ring(dev, &dev_priv->blt_ring, |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2185 | invalidate_domains, flush_domains); |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2186 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2187 | } |
| 2188 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2189 | /** |
| 2190 | * Ensures that all rendering to the object has completed and the object is |
| 2191 | * safe to unbind from the GTT or access from the CPU. |
| 2192 | */ |
| 2193 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2194 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2195 | bool interruptible) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2196 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2197 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2198 | int ret; |
| 2199 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2200 | /* This function only exists to support waiting for existing rendering, |
| 2201 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2202 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2203 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2204 | |
| 2205 | /* If there is rendering queued on the buffer being evicted, wait for |
| 2206 | * it. |
| 2207 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2208 | if (obj->active) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2209 | ret = i915_do_wait_request(dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2210 | obj->last_rendering_seqno, |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2211 | interruptible, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2212 | obj->ring); |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2213 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2214 | return ret; |
| 2215 | } |
| 2216 | |
| 2217 | return 0; |
| 2218 | } |
| 2219 | |
| 2220 | /** |
| 2221 | * Unbinds an object from the GTT aperture. |
| 2222 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2223 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2224 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2225 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2226 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2227 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2228 | int ret = 0; |
| 2229 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2230 | if (obj->gtt_space == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2231 | return 0; |
| 2232 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2233 | if (obj->pin_count != 0) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2234 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
| 2235 | return -EINVAL; |
| 2236 | } |
| 2237 | |
Eric Anholt | 5323fd0 | 2009-09-09 11:50:45 -0700 | [diff] [blame] | 2238 | /* blow away mappings if mapped through GTT */ |
| 2239 | i915_gem_release_mmap(obj); |
| 2240 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2241 | /* Move the object to the CPU domain to ensure that |
| 2242 | * any possible CPU writes while it's not in the GTT |
| 2243 | * are flushed when we go to remap it. This will |
| 2244 | * also ensure that all pending GPU writes are finished |
| 2245 | * before we unbind. |
| 2246 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2247 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2248 | if (ret == -ERESTARTSYS) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2249 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2250 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2251 | * should be safe and we need to cleanup or else we might |
| 2252 | * cause memory corruption through use-after-free. |
| 2253 | */ |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2254 | if (ret) { |
| 2255 | i915_gem_clflush_object(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2256 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2257 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2258 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2259 | /* release the fence reg _after_ flushing */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2260 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2261 | i915_gem_clear_fence_reg(obj); |
| 2262 | |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 2263 | i915_gem_gtt_unbind_object(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2264 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2265 | i915_gem_object_put_pages_gtt(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2266 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2267 | i915_gem_info_remove_gtt(dev_priv, obj); |
| 2268 | list_del_init(&obj->mm_list); |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2269 | /* Avoid an unnecessary call to unbind on rebind. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2270 | obj->map_and_fenceable = true; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2271 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2272 | drm_mm_put_block(obj->gtt_space); |
| 2273 | obj->gtt_space = NULL; |
| 2274 | obj->gtt_offset = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2275 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2276 | if (i915_gem_object_is_purgeable(obj)) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2277 | i915_gem_object_truncate(obj); |
| 2278 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2279 | trace_i915_gem_object_unbind(obj); |
| 2280 | |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2281 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2282 | } |
| 2283 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2284 | static int i915_ring_idle(struct drm_device *dev, |
| 2285 | struct intel_ring_buffer *ring) |
| 2286 | { |
Chris Wilson | 395b70b | 2010-10-28 21:28:46 +0100 | [diff] [blame] | 2287 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 2288 | return 0; |
| 2289 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2290 | i915_gem_flush_ring(dev, ring, |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2291 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 2292 | return i915_wait_request(dev, |
| 2293 | i915_gem_next_request_seqno(dev, ring), |
| 2294 | ring); |
| 2295 | } |
| 2296 | |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 2297 | int |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2298 | i915_gpu_idle(struct drm_device *dev) |
| 2299 | { |
| 2300 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2301 | bool lists_empty; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2302 | int ret; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2303 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2304 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
Chris Wilson | 395b70b | 2010-10-28 21:28:46 +0100 | [diff] [blame] | 2305 | list_empty(&dev_priv->mm.active_list)); |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2306 | if (lists_empty) |
| 2307 | return 0; |
| 2308 | |
| 2309 | /* Flush everything onto the inactive list. */ |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2310 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2311 | if (ret) |
| 2312 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2313 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 2314 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
| 2315 | if (ret) |
| 2316 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2317 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2318 | ret = i915_ring_idle(dev, &dev_priv->blt_ring); |
| 2319 | if (ret) |
| 2320 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2321 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2322 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2323 | } |
| 2324 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2325 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2326 | struct intel_ring_buffer *pipelined) |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2327 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2328 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2329 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2330 | u32 size = obj->gtt_space->size; |
| 2331 | int regnum = obj->fence_reg; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2332 | uint64_t val; |
| 2333 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2334 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2335 | 0xfffff000) << 32; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2336 | val |= obj->gtt_offset & 0xfffff000; |
| 2337 | val |= (uint64_t)((obj->stride / 128) - 1) << |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2338 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 2339 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2340 | if (obj->tiling_mode == I915_TILING_Y) |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2341 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2342 | val |= I965_FENCE_REG_VALID; |
| 2343 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2344 | if (pipelined) { |
| 2345 | int ret = intel_ring_begin(pipelined, 6); |
| 2346 | if (ret) |
| 2347 | return ret; |
| 2348 | |
| 2349 | intel_ring_emit(pipelined, MI_NOOP); |
| 2350 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); |
| 2351 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); |
| 2352 | intel_ring_emit(pipelined, (u32)val); |
| 2353 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); |
| 2354 | intel_ring_emit(pipelined, (u32)(val >> 32)); |
| 2355 | intel_ring_advance(pipelined); |
| 2356 | } else |
| 2357 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); |
| 2358 | |
| 2359 | return 0; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2360 | } |
| 2361 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2362 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2363 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2364 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2365 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2366 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2367 | u32 size = obj->gtt_space->size; |
| 2368 | int regnum = obj->fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2369 | uint64_t val; |
| 2370 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2371 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2372 | 0xfffff000) << 32; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2373 | val |= obj->gtt_offset & 0xfffff000; |
| 2374 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2375 | if (obj->tiling_mode == I915_TILING_Y) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2376 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2377 | val |= I965_FENCE_REG_VALID; |
| 2378 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2379 | if (pipelined) { |
| 2380 | int ret = intel_ring_begin(pipelined, 6); |
| 2381 | if (ret) |
| 2382 | return ret; |
| 2383 | |
| 2384 | intel_ring_emit(pipelined, MI_NOOP); |
| 2385 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); |
| 2386 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); |
| 2387 | intel_ring_emit(pipelined, (u32)val); |
| 2388 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); |
| 2389 | intel_ring_emit(pipelined, (u32)(val >> 32)); |
| 2390 | intel_ring_advance(pipelined); |
| 2391 | } else |
| 2392 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); |
| 2393 | |
| 2394 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2395 | } |
| 2396 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2397 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2398 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2399 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2400 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2401 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2402 | u32 size = obj->gtt_space->size; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2403 | u32 fence_reg, val, pitch_val; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2404 | int tile_width; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2405 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2406 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2407 | (size & -size) != size || |
| 2408 | (obj->gtt_offset & (size - 1)), |
| 2409 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
| 2410 | obj->gtt_offset, obj->map_and_fenceable, size)) |
| 2411 | return -EINVAL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2412 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2413 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2414 | tile_width = 128; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2415 | else |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2416 | tile_width = 512; |
| 2417 | |
| 2418 | /* Note: pitch better be a power of two tile widths */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2419 | pitch_val = obj->stride / tile_width; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2420 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2421 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2422 | val = obj->gtt_offset; |
| 2423 | if (obj->tiling_mode == I915_TILING_Y) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2424 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2425 | val |= I915_FENCE_SIZE_BITS(size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2426 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2427 | val |= I830_FENCE_REG_VALID; |
| 2428 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2429 | fence_reg = obj->fence_reg; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2430 | if (fence_reg < 8) |
| 2431 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2432 | else |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2433 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2434 | |
| 2435 | if (pipelined) { |
| 2436 | int ret = intel_ring_begin(pipelined, 4); |
| 2437 | if (ret) |
| 2438 | return ret; |
| 2439 | |
| 2440 | intel_ring_emit(pipelined, MI_NOOP); |
| 2441 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); |
| 2442 | intel_ring_emit(pipelined, fence_reg); |
| 2443 | intel_ring_emit(pipelined, val); |
| 2444 | intel_ring_advance(pipelined); |
| 2445 | } else |
| 2446 | I915_WRITE(fence_reg, val); |
| 2447 | |
| 2448 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2449 | } |
| 2450 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2451 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2452 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2453 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2454 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2455 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2456 | u32 size = obj->gtt_space->size; |
| 2457 | int regnum = obj->fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2458 | uint32_t val; |
| 2459 | uint32_t pitch_val; |
| 2460 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2461 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
| 2462 | (size & -size) != size || |
| 2463 | (obj->gtt_offset & (size - 1)), |
| 2464 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", |
| 2465 | obj->gtt_offset, size)) |
| 2466 | return -EINVAL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2467 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2468 | pitch_val = obj->stride / 128; |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2469 | pitch_val = ffs(pitch_val) - 1; |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2470 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2471 | val = obj->gtt_offset; |
| 2472 | if (obj->tiling_mode == I915_TILING_Y) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2473 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2474 | val |= I830_FENCE_SIZE_BITS(size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2475 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2476 | val |= I830_FENCE_REG_VALID; |
| 2477 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2478 | if (pipelined) { |
| 2479 | int ret = intel_ring_begin(pipelined, 4); |
| 2480 | if (ret) |
| 2481 | return ret; |
| 2482 | |
| 2483 | intel_ring_emit(pipelined, MI_NOOP); |
| 2484 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); |
| 2485 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); |
| 2486 | intel_ring_emit(pipelined, val); |
| 2487 | intel_ring_advance(pipelined); |
| 2488 | } else |
| 2489 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); |
| 2490 | |
| 2491 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2492 | } |
| 2493 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2494 | static int i915_find_fence_reg(struct drm_device *dev, |
| 2495 | bool interruptible) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2496 | { |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2497 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2498 | struct drm_i915_fence_reg *reg; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2499 | struct drm_i915_gem_object *obj = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2500 | int i, avail, ret; |
| 2501 | |
| 2502 | /* First try to find a free reg */ |
| 2503 | avail = 0; |
| 2504 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2505 | reg = &dev_priv->fence_regs[i]; |
| 2506 | if (!reg->obj) |
| 2507 | return i; |
| 2508 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2509 | if (!reg->obj->pin_count) |
| 2510 | avail++; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2511 | } |
| 2512 | |
| 2513 | if (avail == 0) |
| 2514 | return -ENOSPC; |
| 2515 | |
| 2516 | /* None available, try to steal one or wait for a user to finish */ |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2517 | avail = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2518 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
| 2519 | lru_list) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2520 | obj = reg->obj; |
| 2521 | if (obj->pin_count) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2522 | continue; |
| 2523 | |
| 2524 | /* found one! */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2525 | avail = obj->fence_reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2526 | break; |
| 2527 | } |
| 2528 | |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2529 | BUG_ON(avail == I915_FENCE_REG_NONE); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2530 | |
| 2531 | /* We only have a reference on obj from the active list. put_fence_reg |
| 2532 | * might drop that one, causing a use-after-free in it. So hold a |
| 2533 | * private reference to obj like the other callers of put_fence_reg |
| 2534 | * (set_tiling ioctl) do. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2535 | drm_gem_object_reference(&obj->base); |
| 2536 | ret = i915_gem_object_put_fence_reg(obj, interruptible); |
| 2537 | drm_gem_object_unreference(&obj->base); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2538 | if (ret != 0) |
| 2539 | return ret; |
| 2540 | |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2541 | return avail; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2542 | } |
| 2543 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2544 | /** |
| 2545 | * i915_gem_object_get_fence_reg - set up a fence reg for an object |
| 2546 | * @obj: object to map through a fence reg |
| 2547 | * |
| 2548 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2549 | * to them without having to worry about swizzling if the object is tiled. |
| 2550 | * |
| 2551 | * This function walks the fence regs looking for a free one for @obj, |
| 2552 | * stealing one if it can't find any. |
| 2553 | * |
| 2554 | * It then sets up the reg based on the object's properties: address, pitch |
| 2555 | * and tiling format. |
| 2556 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2557 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2558 | i915_gem_object_get_fence_reg(struct drm_i915_gem_object *obj, |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2559 | bool interruptible) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2560 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2561 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2562 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2563 | struct drm_i915_fence_reg *reg = NULL; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2564 | struct intel_ring_buffer *pipelined = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2565 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2566 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2567 | /* Just update our place in the LRU if our fence is getting used. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2568 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2569 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2570 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2571 | return 0; |
| 2572 | } |
| 2573 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2574 | switch (obj->tiling_mode) { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2575 | case I915_TILING_NONE: |
| 2576 | WARN(1, "allocating a fence for non-tiled object?\n"); |
| 2577 | break; |
| 2578 | case I915_TILING_X: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2579 | if (!obj->stride) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2580 | return -EINVAL; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2581 | WARN((obj->stride & (512 - 1)), |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2582 | "object 0x%08x is X tiled but has non-512B pitch\n", |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2583 | obj->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2584 | break; |
| 2585 | case I915_TILING_Y: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2586 | if (!obj->stride) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2587 | return -EINVAL; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2588 | WARN((obj->stride & (128 - 1)), |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2589 | "object 0x%08x is Y tiled but has non-128B pitch\n", |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2590 | obj->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2591 | break; |
| 2592 | } |
| 2593 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2594 | ret = i915_find_fence_reg(dev, interruptible); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2595 | if (ret < 0) |
| 2596 | return ret; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2597 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2598 | obj->fence_reg = ret; |
| 2599 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2600 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2601 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2602 | reg->obj = obj; |
| 2603 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2604 | switch (INTEL_INFO(dev)->gen) { |
| 2605 | case 6: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2606 | ret = sandybridge_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2607 | break; |
| 2608 | case 5: |
| 2609 | case 4: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2610 | ret = i965_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2611 | break; |
| 2612 | case 3: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2613 | ret = i915_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2614 | break; |
| 2615 | case 2: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2616 | ret = i830_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2617 | break; |
| 2618 | } |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2619 | |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2620 | trace_i915_gem_object_get_fence(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2621 | obj->fence_reg, |
| 2622 | obj->tiling_mode); |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame^] | 2623 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2624 | } |
| 2625 | |
| 2626 | /** |
| 2627 | * i915_gem_clear_fence_reg - clear out fence register info |
| 2628 | * @obj: object to clear |
| 2629 | * |
| 2630 | * Zeroes out the fence register itself and clears out the associated |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2631 | * data structures in dev_priv and obj. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2632 | */ |
| 2633 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2634 | i915_gem_clear_fence_reg(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2635 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2636 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2637 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2638 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[obj->fence_reg]; |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2639 | uint32_t fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2640 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2641 | switch (INTEL_INFO(dev)->gen) { |
| 2642 | case 6: |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2643 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2644 | (obj->fence_reg * 8), 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2645 | break; |
| 2646 | case 5: |
| 2647 | case 4: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2648 | I915_WRITE64(FENCE_REG_965_0 + (obj->fence_reg * 8), 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2649 | break; |
| 2650 | case 3: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2651 | if (obj->fence_reg >= 8) |
| 2652 | fence_reg = FENCE_REG_945_8 + (obj->fence_reg - 8) * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2653 | else |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2654 | case 2: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2655 | fence_reg = FENCE_REG_830_0 + obj->fence_reg * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2656 | |
| 2657 | I915_WRITE(fence_reg, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2658 | break; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2659 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2660 | |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2661 | reg->obj = NULL; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2662 | obj->fence_reg = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2663 | list_del_init(®->lru_list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2664 | } |
| 2665 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2666 | /** |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2667 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access |
| 2668 | * to the buffer to finish, and then resets the fence register. |
| 2669 | * @obj: tiled object holding a fence register. |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2670 | * @bool: whether the wait upon the fence is interruptible |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2671 | * |
| 2672 | * Zeroes out the fence register itself and clears out the associated |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2673 | * data structures in dev_priv and obj. |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2674 | */ |
| 2675 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2676 | i915_gem_object_put_fence_reg(struct drm_i915_gem_object *obj, |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2677 | bool interruptible) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2678 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2679 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2680 | int ret; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2681 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2682 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2683 | return 0; |
| 2684 | |
Daniel Vetter | 10ae9bd | 2010-02-01 13:59:17 +0100 | [diff] [blame] | 2685 | /* If we've changed tiling, GTT-mappings of the object |
| 2686 | * need to re-fault to ensure that the correct fence register |
| 2687 | * setup is in place. |
| 2688 | */ |
| 2689 | i915_gem_release_mmap(obj); |
| 2690 | |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2691 | /* On the i915, GPU access to tiled buffers is via a fence, |
| 2692 | * therefore we must wait for any outstanding access to complete |
| 2693 | * before clearing the fence. |
| 2694 | */ |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2695 | if (obj->fenced_gpu_access) { |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2696 | ret = i915_gem_object_flush_gpu_write_domain(obj, NULL); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2697 | if (ret) |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2698 | return ret; |
| 2699 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2700 | obj->fenced_gpu_access = false; |
| 2701 | } |
| 2702 | |
| 2703 | if (obj->last_fenced_seqno) { |
| 2704 | ret = i915_do_wait_request(dev, |
| 2705 | obj->last_fenced_seqno, |
| 2706 | interruptible, |
| 2707 | obj->last_fenced_ring); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2708 | if (ret) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2709 | return ret; |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2710 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2711 | obj->last_fenced_seqno = false; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2712 | } |
| 2713 | |
Daniel Vetter | 4a72661 | 2010-02-01 13:59:16 +0100 | [diff] [blame] | 2714 | i915_gem_object_flush_gtt_write_domain(obj); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2715 | i915_gem_clear_fence_reg(obj); |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2716 | |
| 2717 | return 0; |
| 2718 | } |
| 2719 | |
| 2720 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2721 | * Finds free space in the GTT aperture and binds the object there. |
| 2722 | */ |
| 2723 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2724 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2725 | unsigned alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2726 | bool map_and_fenceable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2727 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2728 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2729 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2730 | struct drm_mm_node *free_space; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2731 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2732 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2733 | bool mappable, fenceable; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2734 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2735 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2736 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2737 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2738 | return -EINVAL; |
| 2739 | } |
| 2740 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2741 | fence_size = i915_gem_get_gtt_size(obj); |
| 2742 | fence_alignment = i915_gem_get_gtt_alignment(obj); |
| 2743 | unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2744 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2745 | if (alignment == 0) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2746 | alignment = map_and_fenceable ? fence_alignment : |
| 2747 | unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2748 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2749 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2750 | return -EINVAL; |
| 2751 | } |
| 2752 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2753 | size = map_and_fenceable ? fence_size : obj->base.size; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2754 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2755 | /* If the object is bigger than the entire aperture, reject it early |
| 2756 | * before evicting everything in a vain attempt to find space. |
| 2757 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2758 | if (obj->base.size > |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2759 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2760 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
| 2761 | return -E2BIG; |
| 2762 | } |
| 2763 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2764 | search_free: |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2765 | if (map_and_fenceable) |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2766 | free_space = |
| 2767 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2768 | size, alignment, 0, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2769 | dev_priv->mm.gtt_mappable_end, |
| 2770 | 0); |
| 2771 | else |
| 2772 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2773 | size, alignment, 0); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2774 | |
| 2775 | if (free_space != NULL) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2776 | if (map_and_fenceable) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2777 | obj->gtt_space = |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2778 | drm_mm_get_block_range_generic(free_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2779 | size, alignment, 0, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2780 | dev_priv->mm.gtt_mappable_end, |
| 2781 | 0); |
| 2782 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2783 | obj->gtt_space = |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2784 | drm_mm_get_block(free_space, size, alignment); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2785 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2786 | if (obj->gtt_space == NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2787 | /* If the gtt is empty and we're still having trouble |
| 2788 | * fitting our object in, we're out of memory. |
| 2789 | */ |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2790 | ret = i915_gem_evict_something(dev, size, alignment, |
| 2791 | map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2792 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2793 | return ret; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2794 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2795 | goto search_free; |
| 2796 | } |
| 2797 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2798 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2799 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2800 | drm_mm_put_block(obj->gtt_space); |
| 2801 | obj->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2802 | |
| 2803 | if (ret == -ENOMEM) { |
| 2804 | /* first try to clear up some space from the GTT */ |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2805 | ret = i915_gem_evict_something(dev, size, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2806 | alignment, |
| 2807 | map_and_fenceable); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2808 | if (ret) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2809 | /* now try to shrink everyone else */ |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2810 | if (gfpmask) { |
| 2811 | gfpmask = 0; |
| 2812 | goto search_free; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2813 | } |
| 2814 | |
| 2815 | return ret; |
| 2816 | } |
| 2817 | |
| 2818 | goto search_free; |
| 2819 | } |
| 2820 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2821 | return ret; |
| 2822 | } |
| 2823 | |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 2824 | ret = i915_gem_gtt_bind_object(obj); |
| 2825 | if (ret) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2826 | i915_gem_object_put_pages_gtt(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2827 | drm_mm_put_block(obj->gtt_space); |
| 2828 | obj->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2829 | |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2830 | ret = i915_gem_evict_something(dev, size, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2831 | alignment, map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2832 | if (ret) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2833 | return ret; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2834 | |
| 2835 | goto search_free; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2836 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2837 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2838 | obj->gtt_offset = obj->gtt_space->start; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 2839 | |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2840 | /* keep track of bounds object by adding it to the inactive list */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2841 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
| 2842 | i915_gem_info_add_gtt(dev_priv, obj); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2843 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2844 | /* Assert that the object is not currently in any GPU domain. As it |
| 2845 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2846 | * a GPU cache |
| 2847 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2848 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 2849 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2850 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2851 | trace_i915_gem_object_bind(obj, obj->gtt_offset, map_and_fenceable); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2852 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2853 | fenceable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2854 | obj->gtt_space->size == fence_size && |
| 2855 | (obj->gtt_space->start & (fence_alignment -1)) == 0; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2856 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2857 | mappable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2858 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2859 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2860 | obj->map_and_fenceable = mappable && fenceable; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2861 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2862 | return 0; |
| 2863 | } |
| 2864 | |
| 2865 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2866 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2867 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2868 | /* If we don't have a page list set up, then we're not pinned |
| 2869 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2870 | * again at bind time. |
| 2871 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2872 | if (obj->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2873 | return; |
| 2874 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2875 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 2876 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2877 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2878 | } |
| 2879 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2880 | /** Flushes any GPU write domain for the object if it's dirty. */ |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2881 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2882 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2883 | struct intel_ring_buffer *pipelined) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2884 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2885 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2886 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2887 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2888 | return 0; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2889 | |
| 2890 | /* Queue the GPU write cache flushing we need. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2891 | i915_gem_flush_ring(dev, obj->ring, 0, obj->base.write_domain); |
| 2892 | BUG_ON(obj->base.write_domain); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2893 | |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2894 | if (pipelined && pipelined == obj->ring) |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2895 | return 0; |
| 2896 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2897 | return i915_gem_object_wait_rendering(obj, true); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2898 | } |
| 2899 | |
| 2900 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 2901 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2902 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2903 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2904 | uint32_t old_write_domain; |
| 2905 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2906 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2907 | return; |
| 2908 | |
| 2909 | /* No actual flushing is required for the GTT write domain. Writes |
| 2910 | * to it immediately go to main memory as far as we know, so there's |
| 2911 | * no chipset flush. It also doesn't land in render cache. |
| 2912 | */ |
Chris Wilson | 4a684a4 | 2010-10-28 14:44:08 +0100 | [diff] [blame] | 2913 | i915_gem_release_mmap(obj); |
| 2914 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2915 | old_write_domain = obj->base.write_domain; |
| 2916 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2917 | |
| 2918 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2919 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2920 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2921 | } |
| 2922 | |
| 2923 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 2924 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2925 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2926 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2927 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2928 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2929 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2930 | return; |
| 2931 | |
| 2932 | i915_gem_clflush_object(obj); |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 2933 | intel_gtt_chipset_flush(); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2934 | old_write_domain = obj->base.write_domain; |
| 2935 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2936 | |
| 2937 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2938 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2939 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2940 | } |
| 2941 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2942 | /** |
| 2943 | * Moves a single object to the GTT read, and possibly write domain. |
| 2944 | * |
| 2945 | * This function returns when the move is complete, including waiting on |
| 2946 | * flushes to occur. |
| 2947 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2948 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2949 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, int write) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2950 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2951 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2952 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2953 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2954 | /* Not valid to be called on unbound objects. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2955 | if (obj->gtt_space == NULL) |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2956 | return -EINVAL; |
| 2957 | |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2958 | ret = i915_gem_object_flush_gpu_write_domain(obj, NULL); |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2959 | if (ret != 0) |
| 2960 | return ret; |
| 2961 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2962 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2963 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2964 | if (write) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2965 | ret = i915_gem_object_wait_rendering(obj, true); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2966 | if (ret) |
| 2967 | return ret; |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2968 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2969 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2970 | old_write_domain = obj->base.write_domain; |
| 2971 | old_read_domains = obj->base.read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2972 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2973 | /* It should now be out of any other write domains, and we can update |
| 2974 | * the domain values for our changes. |
| 2975 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2976 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2977 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2978 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2979 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 2980 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 2981 | obj->dirty = 1; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2982 | } |
| 2983 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2984 | trace_i915_gem_object_change_domain(obj, |
| 2985 | old_read_domains, |
| 2986 | old_write_domain); |
| 2987 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2988 | return 0; |
| 2989 | } |
| 2990 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2991 | /* |
| 2992 | * Prepare buffer for display plane. Use uninterruptible for possible flush |
| 2993 | * wait, as in modesetting process we're not supposed to be interrupted. |
| 2994 | */ |
| 2995 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2996 | i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2997 | struct intel_ring_buffer *pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2998 | { |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2999 | uint32_t old_read_domains; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3000 | int ret; |
| 3001 | |
| 3002 | /* Not valid to be called on unbound objects. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3003 | if (obj->gtt_space == NULL) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3004 | return -EINVAL; |
| 3005 | |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3006 | ret = i915_gem_object_flush_gpu_write_domain(obj, pipelined); |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 3007 | if (ret) |
| 3008 | return ret; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3009 | |
Chris Wilson | ced270f | 2010-09-26 22:47:46 +0100 | [diff] [blame] | 3010 | /* Currently, we are always called from an non-interruptible context. */ |
| 3011 | if (!pipelined) { |
| 3012 | ret = i915_gem_object_wait_rendering(obj, false); |
| 3013 | if (ret) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3014 | return ret; |
| 3015 | } |
| 3016 | |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 3017 | i915_gem_object_flush_cpu_write_domain(obj); |
| 3018 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3019 | old_read_domains = obj->base.read_domains; |
| 3020 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3021 | |
| 3022 | trace_i915_gem_object_change_domain(obj, |
| 3023 | old_read_domains, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3024 | obj->base.write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3025 | |
| 3026 | return 0; |
| 3027 | } |
| 3028 | |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3029 | int |
| 3030 | i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj, |
| 3031 | bool interruptible) |
| 3032 | { |
| 3033 | if (!obj->active) |
| 3034 | return 0; |
| 3035 | |
| 3036 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3037 | i915_gem_flush_ring(obj->base.dev, obj->ring, |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3038 | 0, obj->base.write_domain); |
| 3039 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3040 | return i915_gem_object_wait_rendering(obj, interruptible); |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3041 | } |
| 3042 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3043 | /** |
| 3044 | * Moves a single object to the CPU read, and possibly write domain. |
| 3045 | * |
| 3046 | * This function returns when the move is complete, including waiting on |
| 3047 | * flushes to occur. |
| 3048 | */ |
| 3049 | static int |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3050 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3051 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3052 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3053 | int ret; |
| 3054 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 3055 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3056 | if (ret != 0) |
| 3057 | return ret; |
| 3058 | |
| 3059 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3060 | |
| 3061 | /* If we have a partially-valid cache of the object in the CPU, |
| 3062 | * finish invalidating it and free the per-page flags. |
| 3063 | */ |
| 3064 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
| 3065 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 3066 | if (write) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 3067 | ret = i915_gem_object_wait_rendering(obj, true); |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 3068 | if (ret) |
| 3069 | return ret; |
| 3070 | } |
| 3071 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3072 | old_write_domain = obj->base.write_domain; |
| 3073 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3074 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3075 | /* Flush the CPU cache if it's still invalid. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3076 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3077 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3078 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3079 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3080 | } |
| 3081 | |
| 3082 | /* It should now be out of any other write domains, and we can update |
| 3083 | * the domain values for our changes. |
| 3084 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3085 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3086 | |
| 3087 | /* If we're writing through the CPU, then the GPU read domains will |
| 3088 | * need to be invalidated at next use. |
| 3089 | */ |
| 3090 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3091 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3092 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3093 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3094 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3095 | trace_i915_gem_object_change_domain(obj, |
| 3096 | old_read_domains, |
| 3097 | old_write_domain); |
| 3098 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3099 | return 0; |
| 3100 | } |
| 3101 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3102 | /* |
| 3103 | * Set the next domain for the specified object. This |
| 3104 | * may not actually perform the necessary flushing/invaliding though, |
| 3105 | * as that may want to be batched with other set_domain operations |
| 3106 | * |
| 3107 | * This is (we hope) the only really tricky part of gem. The goal |
| 3108 | * is fairly simple -- track which caches hold bits of the object |
| 3109 | * and make sure they remain coherent. A few concrete examples may |
| 3110 | * help to explain how it works. For shorthand, we use the notation |
| 3111 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the |
| 3112 | * a pair of read and write domain masks. |
| 3113 | * |
| 3114 | * Case 1: the batch buffer |
| 3115 | * |
| 3116 | * 1. Allocated |
| 3117 | * 2. Written by CPU |
| 3118 | * 3. Mapped to GTT |
| 3119 | * 4. Read by GPU |
| 3120 | * 5. Unmapped from GTT |
| 3121 | * 6. Freed |
| 3122 | * |
| 3123 | * Let's take these a step at a time |
| 3124 | * |
| 3125 | * 1. Allocated |
| 3126 | * Pages allocated from the kernel may still have |
| 3127 | * cache contents, so we set them to (CPU, CPU) always. |
| 3128 | * 2. Written by CPU (using pwrite) |
| 3129 | * The pwrite function calls set_domain (CPU, CPU) and |
| 3130 | * this function does nothing (as nothing changes) |
| 3131 | * 3. Mapped by GTT |
| 3132 | * This function asserts that the object is not |
| 3133 | * currently in any GPU-based read or write domains |
| 3134 | * 4. Read by GPU |
| 3135 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). |
| 3136 | * As write_domain is zero, this function adds in the |
| 3137 | * current read domains (CPU+COMMAND, 0). |
| 3138 | * flush_domains is set to CPU. |
| 3139 | * invalidate_domains is set to COMMAND |
| 3140 | * clflush is run to get data out of the CPU caches |
| 3141 | * then i915_dev_set_domain calls i915_gem_flush to |
| 3142 | * emit an MI_FLUSH and drm_agp_chipset_flush |
| 3143 | * 5. Unmapped from GTT |
| 3144 | * i915_gem_object_unbind calls set_domain (CPU, CPU) |
| 3145 | * flush_domains and invalidate_domains end up both zero |
| 3146 | * so no flushing/invalidating happens |
| 3147 | * 6. Freed |
| 3148 | * yay, done |
| 3149 | * |
| 3150 | * Case 2: The shared render buffer |
| 3151 | * |
| 3152 | * 1. Allocated |
| 3153 | * 2. Mapped to GTT |
| 3154 | * 3. Read/written by GPU |
| 3155 | * 4. set_domain to (CPU,CPU) |
| 3156 | * 5. Read/written by CPU |
| 3157 | * 6. Read/written by GPU |
| 3158 | * |
| 3159 | * 1. Allocated |
| 3160 | * Same as last example, (CPU, CPU) |
| 3161 | * 2. Mapped to GTT |
| 3162 | * Nothing changes (assertions find that it is not in the GPU) |
| 3163 | * 3. Read/written by GPU |
| 3164 | * execbuffer calls set_domain (RENDER, RENDER) |
| 3165 | * flush_domains gets CPU |
| 3166 | * invalidate_domains gets GPU |
| 3167 | * clflush (obj) |
| 3168 | * MI_FLUSH and drm_agp_chipset_flush |
| 3169 | * 4. set_domain (CPU, CPU) |
| 3170 | * flush_domains gets GPU |
| 3171 | * invalidate_domains gets CPU |
| 3172 | * wait_rendering (obj) to make sure all drawing is complete. |
| 3173 | * This will include an MI_FLUSH to get the data from GPU |
| 3174 | * to memory |
| 3175 | * clflush (obj) to invalidate the CPU cache |
| 3176 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) |
| 3177 | * 5. Read/written by CPU |
| 3178 | * cache lines are loaded and dirtied |
| 3179 | * 6. Read written by GPU |
| 3180 | * Same as last GPU access |
| 3181 | * |
| 3182 | * Case 3: The constant buffer |
| 3183 | * |
| 3184 | * 1. Allocated |
| 3185 | * 2. Written by CPU |
| 3186 | * 3. Read by GPU |
| 3187 | * 4. Updated (written) by CPU again |
| 3188 | * 5. Read by GPU |
| 3189 | * |
| 3190 | * 1. Allocated |
| 3191 | * (CPU, CPU) |
| 3192 | * 2. Written by CPU |
| 3193 | * (CPU, CPU) |
| 3194 | * 3. Read by GPU |
| 3195 | * (CPU+RENDER, 0) |
| 3196 | * flush_domains = CPU |
| 3197 | * invalidate_domains = RENDER |
| 3198 | * clflush (obj) |
| 3199 | * MI_FLUSH |
| 3200 | * drm_agp_chipset_flush |
| 3201 | * 4. Updated (written) by CPU again |
| 3202 | * (CPU, CPU) |
| 3203 | * flush_domains = 0 (no previous write domain) |
| 3204 | * invalidate_domains = 0 (no new read domains) |
| 3205 | * 5. Read by GPU |
| 3206 | * (CPU+RENDER, 0) |
| 3207 | * flush_domains = CPU |
| 3208 | * invalidate_domains = RENDER |
| 3209 | * clflush (obj) |
| 3210 | * MI_FLUSH |
| 3211 | * drm_agp_chipset_flush |
| 3212 | */ |
Keith Packard | c0d9082 | 2008-11-20 23:11:08 -0800 | [diff] [blame] | 3213 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3214 | i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj, |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 3215 | struct intel_ring_buffer *ring, |
| 3216 | struct change_domains *cd) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3217 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3218 | uint32_t invalidate_domains = 0, flush_domains = 0; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3219 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3220 | /* |
| 3221 | * If the object isn't moving to a new write domain, |
| 3222 | * let the object stay in multiple read domains |
| 3223 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3224 | if (obj->base.pending_write_domain == 0) |
| 3225 | obj->base.pending_read_domains |= obj->base.read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3226 | |
| 3227 | /* |
| 3228 | * Flush the current write domain if |
| 3229 | * the new read domains don't match. Invalidate |
| 3230 | * any read domains which differ from the old |
| 3231 | * write domain |
| 3232 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3233 | if (obj->base.write_domain && |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 3234 | (((obj->base.write_domain != obj->base.pending_read_domains || |
| 3235 | obj->ring != ring)) || |
| 3236 | (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3237 | flush_domains |= obj->base.write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3238 | invalidate_domains |= |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3239 | obj->base.pending_read_domains & ~obj->base.write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3240 | } |
| 3241 | /* |
| 3242 | * Invalidate any read caches which may have |
| 3243 | * stale data. That is, any new read domains. |
| 3244 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3245 | invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains; |
Chris Wilson | 3d2a812 | 2010-09-29 11:39:53 +0100 | [diff] [blame] | 3246 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3247 | i915_gem_clflush_object(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3248 | |
Chris Wilson | 4a684a4 | 2010-10-28 14:44:08 +0100 | [diff] [blame] | 3249 | /* blow away mappings if mapped through GTT */ |
| 3250 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_GTT) |
| 3251 | i915_gem_release_mmap(obj); |
| 3252 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3253 | /* The actual obj->write_domain will be updated with |
| 3254 | * pending_write_domain after we emit the accumulated flush for all |
| 3255 | * of our domain changes in execbuffers (which clears objects' |
| 3256 | * write_domains). So if we have a current write domain that we |
| 3257 | * aren't changing, set pending_write_domain to that. |
| 3258 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3259 | if (flush_domains == 0 && obj->base.pending_write_domain == 0) |
| 3260 | obj->base.pending_write_domain = obj->base.write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3261 | |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 3262 | cd->invalidate_domains |= invalidate_domains; |
| 3263 | cd->flush_domains |= flush_domains; |
Chris Wilson | b665145 | 2010-10-23 10:15:06 +0100 | [diff] [blame] | 3264 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3265 | cd->flush_rings |= obj->ring->id; |
Chris Wilson | b665145 | 2010-10-23 10:15:06 +0100 | [diff] [blame] | 3266 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 3267 | cd->flush_rings |= ring->id; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3268 | } |
| 3269 | |
| 3270 | /** |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3271 | * Moves the object from a partially CPU read to a full one. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3272 | * |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3273 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
| 3274 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). |
| 3275 | */ |
| 3276 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3277 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3278 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3279 | if (!obj->page_cpu_valid) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3280 | return; |
| 3281 | |
| 3282 | /* If we're partially in the CPU read domain, finish moving it in. |
| 3283 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3284 | if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3285 | int i; |
| 3286 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3287 | for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) { |
| 3288 | if (obj->page_cpu_valid[i]) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3289 | continue; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3290 | drm_clflush_pages(obj->pages + i, 1); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3291 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3292 | } |
| 3293 | |
| 3294 | /* Free the page_cpu_valid mappings which are now stale, whether |
| 3295 | * or not we've got I915_GEM_DOMAIN_CPU. |
| 3296 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3297 | kfree(obj->page_cpu_valid); |
| 3298 | obj->page_cpu_valid = NULL; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3299 | } |
| 3300 | |
| 3301 | /** |
| 3302 | * Set the CPU read domain on a range of the object. |
| 3303 | * |
| 3304 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's |
| 3305 | * not entirely valid. The page_cpu_valid member of the object flags which |
| 3306 | * pages have been flushed, and will be respected by |
| 3307 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping |
| 3308 | * of the whole object. |
| 3309 | * |
| 3310 | * This function returns when the move is complete, including waiting on |
| 3311 | * flushes to occur. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3312 | */ |
| 3313 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3314 | i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3315 | uint64_t offset, uint64_t size) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3316 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3317 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3318 | int i, ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3319 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3320 | if (offset == 0 && size == obj->base.size) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3321 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
| 3322 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 3323 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3324 | if (ret != 0) |
| 3325 | return ret; |
| 3326 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3327 | |
| 3328 | /* If we're already fully in the CPU read domain, we're done. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3329 | if (obj->page_cpu_valid == NULL && |
| 3330 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3331 | return 0; |
| 3332 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3333 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
| 3334 | * newly adding I915_GEM_DOMAIN_CPU |
| 3335 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3336 | if (obj->page_cpu_valid == NULL) { |
| 3337 | obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE, |
| 3338 | GFP_KERNEL); |
| 3339 | if (obj->page_cpu_valid == NULL) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3340 | return -ENOMEM; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3341 | } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 3342 | memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3343 | |
| 3344 | /* Flush the cache on any pages that are still invalid from the CPU's |
| 3345 | * perspective. |
| 3346 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3347 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
| 3348 | i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3349 | if (obj->page_cpu_valid[i]) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3350 | continue; |
| 3351 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3352 | drm_clflush_pages(obj->pages + i, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3353 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3354 | obj->page_cpu_valid[i] = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3355 | } |
| 3356 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3357 | /* It should now be out of any other write domains, and we can update |
| 3358 | * the domain values for our changes. |
| 3359 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3360 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3361 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3362 | old_read_domains = obj->base.read_domains; |
| 3363 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3364 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3365 | trace_i915_gem_object_change_domain(obj, |
| 3366 | old_read_domains, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3367 | obj->base.write_domain); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3368 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3369 | return 0; |
| 3370 | } |
| 3371 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3372 | static int |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3373 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, |
| 3374 | struct drm_file *file_priv, |
| 3375 | struct drm_i915_gem_exec_object2 *entry, |
| 3376 | struct drm_i915_gem_relocation_entry *reloc) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3377 | { |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3378 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3379 | struct drm_gem_object *target_obj; |
| 3380 | uint32_t target_offset; |
| 3381 | int ret = -EINVAL; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3382 | |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3383 | target_obj = drm_gem_object_lookup(dev, file_priv, |
| 3384 | reloc->target_handle); |
| 3385 | if (target_obj == NULL) |
| 3386 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3387 | |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3388 | target_offset = to_intel_bo(target_obj)->gtt_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3389 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3390 | #if WATCH_RELOC |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3391 | DRM_INFO("%s: obj %p offset %08x target %d " |
| 3392 | "read %08x write %08x gtt %08x " |
| 3393 | "presumed %08x delta %08x\n", |
| 3394 | __func__, |
| 3395 | obj, |
| 3396 | (int) reloc->offset, |
| 3397 | (int) reloc->target_handle, |
| 3398 | (int) reloc->read_domains, |
| 3399 | (int) reloc->write_domain, |
| 3400 | (int) target_offset, |
| 3401 | (int) reloc->presumed_offset, |
| 3402 | reloc->delta); |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3403 | #endif |
| 3404 | |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3405 | /* The target buffer should have appeared before us in the |
| 3406 | * exec_object list, so it should have a GTT space bound by now. |
| 3407 | */ |
| 3408 | if (target_offset == 0) { |
| 3409 | DRM_ERROR("No GTT space found for object %d\n", |
| 3410 | reloc->target_handle); |
| 3411 | goto err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3412 | } |
| 3413 | |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3414 | /* Validate that the target is in a valid r/w GPU domain */ |
| 3415 | if (reloc->write_domain & (reloc->write_domain - 1)) { |
| 3416 | DRM_ERROR("reloc with multiple write domains: " |
| 3417 | "obj %p target %d offset %d " |
| 3418 | "read %08x write %08x", |
| 3419 | obj, reloc->target_handle, |
| 3420 | (int) reloc->offset, |
| 3421 | reloc->read_domains, |
| 3422 | reloc->write_domain); |
| 3423 | goto err; |
| 3424 | } |
| 3425 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || |
| 3426 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { |
| 3427 | DRM_ERROR("reloc with read/write CPU domains: " |
| 3428 | "obj %p target %d offset %d " |
| 3429 | "read %08x write %08x", |
| 3430 | obj, reloc->target_handle, |
| 3431 | (int) reloc->offset, |
| 3432 | reloc->read_domains, |
| 3433 | reloc->write_domain); |
| 3434 | goto err; |
| 3435 | } |
| 3436 | if (reloc->write_domain && target_obj->pending_write_domain && |
| 3437 | reloc->write_domain != target_obj->pending_write_domain) { |
| 3438 | DRM_ERROR("Write domain conflict: " |
| 3439 | "obj %p target %d offset %d " |
| 3440 | "new %08x old %08x\n", |
| 3441 | obj, reloc->target_handle, |
| 3442 | (int) reloc->offset, |
| 3443 | reloc->write_domain, |
| 3444 | target_obj->pending_write_domain); |
| 3445 | goto err; |
| 3446 | } |
| 3447 | |
| 3448 | target_obj->pending_read_domains |= reloc->read_domains; |
| 3449 | target_obj->pending_write_domain |= reloc->write_domain; |
| 3450 | |
| 3451 | /* If the relocation already has the right value in it, no |
| 3452 | * more work needs to be done. |
| 3453 | */ |
| 3454 | if (target_offset == reloc->presumed_offset) |
| 3455 | goto out; |
| 3456 | |
| 3457 | /* Check that the relocation address is valid... */ |
| 3458 | if (reloc->offset > obj->base.size - 4) { |
| 3459 | DRM_ERROR("Relocation beyond object bounds: " |
| 3460 | "obj %p target %d offset %d size %d.\n", |
| 3461 | obj, reloc->target_handle, |
| 3462 | (int) reloc->offset, |
| 3463 | (int) obj->base.size); |
| 3464 | goto err; |
| 3465 | } |
| 3466 | if (reloc->offset & 3) { |
| 3467 | DRM_ERROR("Relocation not 4-byte aligned: " |
| 3468 | "obj %p target %d offset %d.\n", |
| 3469 | obj, reloc->target_handle, |
| 3470 | (int) reloc->offset); |
| 3471 | goto err; |
| 3472 | } |
| 3473 | |
| 3474 | /* and points to somewhere within the target object. */ |
| 3475 | if (reloc->delta >= target_obj->size) { |
| 3476 | DRM_ERROR("Relocation beyond target object bounds: " |
| 3477 | "obj %p target %d delta %d size %d.\n", |
| 3478 | obj, reloc->target_handle, |
| 3479 | (int) reloc->delta, |
| 3480 | (int) target_obj->size); |
| 3481 | goto err; |
| 3482 | } |
| 3483 | |
| 3484 | reloc->delta += target_offset; |
| 3485 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { |
| 3486 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; |
| 3487 | char *vaddr; |
| 3488 | |
| 3489 | vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]); |
| 3490 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; |
| 3491 | kunmap_atomic(vaddr); |
| 3492 | } else { |
| 3493 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3494 | uint32_t __iomem *reloc_entry; |
| 3495 | void __iomem *reloc_page; |
| 3496 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3497 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3498 | if (ret) |
| 3499 | goto err; |
| 3500 | |
| 3501 | /* Map the page containing the relocation we're going to perform. */ |
| 3502 | reloc->offset += obj->gtt_offset; |
| 3503 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
| 3504 | reloc->offset & PAGE_MASK); |
| 3505 | reloc_entry = (uint32_t __iomem *) |
| 3506 | (reloc_page + (reloc->offset & ~PAGE_MASK)); |
| 3507 | iowrite32(reloc->delta, reloc_entry); |
| 3508 | io_mapping_unmap_atomic(reloc_page); |
| 3509 | } |
| 3510 | |
| 3511 | /* and update the user's relocation entry */ |
| 3512 | reloc->presumed_offset = target_offset; |
| 3513 | |
| 3514 | out: |
| 3515 | ret = 0; |
| 3516 | err: |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3517 | drm_gem_object_unreference(target_obj); |
| 3518 | return ret; |
| 3519 | } |
| 3520 | |
| 3521 | static int |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3522 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, |
| 3523 | struct drm_file *file_priv, |
| 3524 | struct drm_i915_gem_exec_object2 *entry) |
| 3525 | { |
| 3526 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
| 3527 | int i, ret; |
| 3528 | |
| 3529 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
| 3530 | for (i = 0; i < entry->relocation_count; i++) { |
| 3531 | struct drm_i915_gem_relocation_entry reloc; |
| 3532 | |
| 3533 | if (__copy_from_user_inatomic(&reloc, |
| 3534 | user_relocs+i, |
| 3535 | sizeof(reloc))) |
| 3536 | return -EFAULT; |
| 3537 | |
| 3538 | ret = i915_gem_execbuffer_relocate_entry(obj, file_priv, entry, &reloc); |
| 3539 | if (ret) |
| 3540 | return ret; |
| 3541 | |
| 3542 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, |
| 3543 | &reloc.presumed_offset, |
| 3544 | sizeof(reloc.presumed_offset))) |
| 3545 | return -EFAULT; |
| 3546 | } |
| 3547 | |
| 3548 | return 0; |
| 3549 | } |
| 3550 | |
| 3551 | static int |
| 3552 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, |
| 3553 | struct drm_file *file_priv, |
| 3554 | struct drm_i915_gem_exec_object2 *entry, |
| 3555 | struct drm_i915_gem_relocation_entry *relocs) |
| 3556 | { |
| 3557 | int i, ret; |
| 3558 | |
| 3559 | for (i = 0; i < entry->relocation_count; i++) { |
| 3560 | ret = i915_gem_execbuffer_relocate_entry(obj, file_priv, entry, &relocs[i]); |
| 3561 | if (ret) |
| 3562 | return ret; |
| 3563 | } |
| 3564 | |
| 3565 | return 0; |
| 3566 | } |
| 3567 | |
| 3568 | static int |
| 3569 | i915_gem_execbuffer_relocate(struct drm_device *dev, |
| 3570 | struct drm_file *file, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3571 | struct drm_i915_gem_object **object_list, |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3572 | struct drm_i915_gem_exec_object2 *exec_list, |
| 3573 | int count) |
| 3574 | { |
| 3575 | int i, ret; |
| 3576 | |
| 3577 | for (i = 0; i < count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3578 | struct drm_i915_gem_object *obj = object_list[i]; |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3579 | obj->base.pending_read_domains = 0; |
| 3580 | obj->base.pending_write_domain = 0; |
| 3581 | ret = i915_gem_execbuffer_relocate_object(obj, file, |
| 3582 | &exec_list[i]); |
| 3583 | if (ret) |
| 3584 | return ret; |
| 3585 | } |
| 3586 | |
| 3587 | return 0; |
| 3588 | } |
| 3589 | |
| 3590 | static int |
| 3591 | i915_gem_execbuffer_reserve(struct drm_device *dev, |
| 3592 | struct drm_file *file, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3593 | struct drm_i915_gem_object **object_list, |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3594 | struct drm_i915_gem_exec_object2 *exec_list, |
| 3595 | int count) |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3596 | { |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3597 | int ret, i, retry; |
| 3598 | |
Chris Wilson | a7a09ae | 2010-11-12 13:49:09 +0000 | [diff] [blame] | 3599 | /* Attempt to pin all of the buffers into the GTT. |
| 3600 | * This is done in 3 phases: |
| 3601 | * |
| 3602 | * 1a. Unbind all objects that do not match the GTT constraints for |
| 3603 | * the execbuffer (fenceable, mappable, alignment etc). |
| 3604 | * 1b. Increment pin count for already bound objects. |
| 3605 | * 2. Bind new objects. |
| 3606 | * 3. Decrement pin count. |
| 3607 | * |
| 3608 | * This avoid unnecessary unbinding of later objects in order to makr |
| 3609 | * room for the earlier objects *unless* we need to defragment. |
| 3610 | */ |
Chris Wilson | 5eac3ab | 2010-10-31 08:49:47 +0000 | [diff] [blame] | 3611 | retry = 0; |
| 3612 | do { |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3613 | ret = 0; |
Chris Wilson | a7a09ae | 2010-11-12 13:49:09 +0000 | [diff] [blame] | 3614 | |
| 3615 | /* Unbind any ill-fitting objects or pin. */ |
| 3616 | for (i = 0; i < count; i++) { |
| 3617 | struct drm_i915_gem_object *obj = object_list[i]; |
| 3618 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; |
| 3619 | bool need_fence, need_mappable; |
| 3620 | |
| 3621 | if (!obj->gtt_space) |
| 3622 | continue; |
| 3623 | |
| 3624 | need_fence = |
| 3625 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
| 3626 | obj->tiling_mode != I915_TILING_NONE; |
| 3627 | need_mappable = |
| 3628 | entry->relocation_count ? true : need_fence; |
| 3629 | |
| 3630 | if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || |
| 3631 | (need_mappable && !obj->map_and_fenceable)) |
| 3632 | ret = i915_gem_object_unbind(obj); |
| 3633 | else |
| 3634 | ret = i915_gem_object_pin(obj, |
| 3635 | entry->alignment, |
| 3636 | need_mappable); |
| 3637 | if (ret) { |
| 3638 | count = i; |
| 3639 | goto err; |
| 3640 | } |
| 3641 | } |
| 3642 | |
| 3643 | /* Bind fresh objects */ |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3644 | for (i = 0; i < count; i++) { |
| 3645 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3646 | struct drm_i915_gem_object *obj = object_list[i]; |
Chris Wilson | a7a09ae | 2010-11-12 13:49:09 +0000 | [diff] [blame] | 3647 | bool need_fence; |
| 3648 | |
| 3649 | need_fence = |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3650 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
| 3651 | obj->tiling_mode != I915_TILING_NONE; |
| 3652 | |
Chris Wilson | a7a09ae | 2010-11-12 13:49:09 +0000 | [diff] [blame] | 3653 | if (!obj->gtt_space) { |
| 3654 | bool need_mappable = |
| 3655 | entry->relocation_count ? true : need_fence; |
Daniel Vetter | 16e809a | 2010-09-16 19:37:04 +0200 | [diff] [blame] | 3656 | |
Chris Wilson | a7a09ae | 2010-11-12 13:49:09 +0000 | [diff] [blame] | 3657 | ret = i915_gem_object_pin(obj, |
| 3658 | entry->alignment, |
| 3659 | need_mappable); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3660 | if (ret) |
| 3661 | break; |
| 3662 | } |
| 3663 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3664 | if (need_fence) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3665 | ret = i915_gem_object_get_fence_reg(obj, true); |
Chris Wilson | a7a09ae | 2010-11-12 13:49:09 +0000 | [diff] [blame] | 3666 | if (ret) |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3667 | break; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3668 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 3669 | obj->pending_fenced_gpu_access = true; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3670 | } |
| 3671 | |
| 3672 | entry->offset = obj->gtt_offset; |
| 3673 | } |
| 3674 | |
Chris Wilson | a7a09ae | 2010-11-12 13:49:09 +0000 | [diff] [blame] | 3675 | err: /* Decrement pin count for bound objects */ |
| 3676 | for (i = 0; i < count; i++) { |
| 3677 | struct drm_i915_gem_object *obj = object_list[i]; |
| 3678 | if (obj->gtt_space) |
| 3679 | i915_gem_object_unpin(obj); |
| 3680 | } |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3681 | |
Chris Wilson | 5eac3ab | 2010-10-31 08:49:47 +0000 | [diff] [blame] | 3682 | if (ret != -ENOSPC || retry > 1) |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3683 | return ret; |
| 3684 | |
Chris Wilson | 5eac3ab | 2010-10-31 08:49:47 +0000 | [diff] [blame] | 3685 | /* First attempt, just clear anything that is purgeable. |
| 3686 | * Second attempt, clear the entire GTT. |
| 3687 | */ |
| 3688 | ret = i915_gem_evict_everything(dev, retry == 0); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3689 | if (ret) |
| 3690 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3691 | |
Chris Wilson | 5eac3ab | 2010-10-31 08:49:47 +0000 | [diff] [blame] | 3692 | retry++; |
| 3693 | } while (1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3694 | } |
| 3695 | |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3696 | static int |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3697 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, |
| 3698 | struct drm_file *file, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3699 | struct drm_i915_gem_object **object_list, |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3700 | struct drm_i915_gem_exec_object2 *exec_list, |
| 3701 | int count) |
| 3702 | { |
| 3703 | struct drm_i915_gem_relocation_entry *reloc; |
| 3704 | int i, total, ret; |
| 3705 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3706 | for (i = 0; i < count; i++) |
| 3707 | object_list[i]->in_execbuffer = false; |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3708 | |
| 3709 | mutex_unlock(&dev->struct_mutex); |
| 3710 | |
| 3711 | total = 0; |
| 3712 | for (i = 0; i < count; i++) |
| 3713 | total += exec_list[i].relocation_count; |
| 3714 | |
| 3715 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
| 3716 | if (reloc == NULL) { |
| 3717 | mutex_lock(&dev->struct_mutex); |
| 3718 | return -ENOMEM; |
| 3719 | } |
| 3720 | |
| 3721 | total = 0; |
| 3722 | for (i = 0; i < count; i++) { |
| 3723 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
| 3724 | |
| 3725 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; |
| 3726 | |
| 3727 | if (copy_from_user(reloc+total, user_relocs, |
| 3728 | exec_list[i].relocation_count * |
| 3729 | sizeof(*reloc))) { |
| 3730 | ret = -EFAULT; |
| 3731 | mutex_lock(&dev->struct_mutex); |
| 3732 | goto err; |
| 3733 | } |
| 3734 | |
| 3735 | total += exec_list[i].relocation_count; |
| 3736 | } |
| 3737 | |
| 3738 | ret = i915_mutex_lock_interruptible(dev); |
| 3739 | if (ret) { |
| 3740 | mutex_lock(&dev->struct_mutex); |
| 3741 | goto err; |
| 3742 | } |
| 3743 | |
| 3744 | ret = i915_gem_execbuffer_reserve(dev, file, |
| 3745 | object_list, exec_list, |
| 3746 | count); |
| 3747 | if (ret) |
| 3748 | goto err; |
| 3749 | |
| 3750 | total = 0; |
| 3751 | for (i = 0; i < count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3752 | struct drm_i915_gem_object *obj = object_list[i]; |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 3753 | obj->base.pending_read_domains = 0; |
| 3754 | obj->base.pending_write_domain = 0; |
| 3755 | ret = i915_gem_execbuffer_relocate_object_slow(obj, file, |
| 3756 | &exec_list[i], |
| 3757 | reloc + total); |
| 3758 | if (ret) |
| 3759 | goto err; |
| 3760 | |
| 3761 | total += exec_list[i].relocation_count; |
| 3762 | } |
| 3763 | |
| 3764 | /* Leave the user relocations as are, this is the painfully slow path, |
| 3765 | * and we want to avoid the complication of dropping the lock whilst |
| 3766 | * having buffers reserved in the aperture and so causing spurious |
| 3767 | * ENOSPC for random operations. |
| 3768 | */ |
| 3769 | |
| 3770 | err: |
| 3771 | drm_free_large(reloc); |
| 3772 | return ret; |
| 3773 | } |
| 3774 | |
| 3775 | static int |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3776 | i915_gem_execbuffer_move_to_gpu(struct drm_device *dev, |
| 3777 | struct drm_file *file, |
| 3778 | struct intel_ring_buffer *ring, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3779 | struct drm_i915_gem_object **objects, |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3780 | int count) |
| 3781 | { |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 3782 | struct change_domains cd; |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3783 | int ret, i; |
| 3784 | |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 3785 | cd.invalidate_domains = 0; |
| 3786 | cd.flush_domains = 0; |
| 3787 | cd.flush_rings = 0; |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3788 | for (i = 0; i < count; i++) |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 3789 | i915_gem_object_set_to_gpu_domain(objects[i], ring, &cd); |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3790 | |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 3791 | if (cd.invalidate_domains | cd.flush_domains) { |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3792 | #if WATCH_EXEC |
| 3793 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", |
| 3794 | __func__, |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 3795 | cd.invalidate_domains, |
| 3796 | cd.flush_domains); |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3797 | #endif |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3798 | i915_gem_flush(dev, |
Chris Wilson | 0f8c6d7 | 2010-11-01 12:38:44 +0000 | [diff] [blame] | 3799 | cd.invalidate_domains, |
| 3800 | cd.flush_domains, |
| 3801 | cd.flush_rings); |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3802 | } |
| 3803 | |
| 3804 | for (i = 0; i < count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3805 | struct drm_i915_gem_object *obj = objects[i]; |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3806 | /* XXX replace with semaphores */ |
| 3807 | if (obj->ring && ring != obj->ring) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3808 | ret = i915_gem_object_wait_rendering(obj, true); |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 3809 | if (ret) |
| 3810 | return ret; |
| 3811 | } |
| 3812 | } |
| 3813 | |
| 3814 | return 0; |
| 3815 | } |
| 3816 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3817 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3818 | * emitted over 20 msec ago. |
| 3819 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3820 | * Note that if we were to use the current jiffies each time around the loop, |
| 3821 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3822 | * render a frame was over 20ms. |
| 3823 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3824 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3825 | * relatively low latency when blocking on a particular request to finish. |
| 3826 | */ |
| 3827 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3828 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3829 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3830 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3831 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3832 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3833 | struct drm_i915_gem_request *request; |
| 3834 | struct intel_ring_buffer *ring = NULL; |
| 3835 | u32 seqno = 0; |
| 3836 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3837 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3838 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3839 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3840 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3841 | break; |
| 3842 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3843 | ring = request->ring; |
| 3844 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3845 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3846 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3847 | |
| 3848 | if (seqno == 0) |
| 3849 | return 0; |
| 3850 | |
| 3851 | ret = 0; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3852 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3853 | /* And wait for the seqno passing without holding any locks and |
| 3854 | * causing extra latency for others. This is safe as the irq |
| 3855 | * generation is designed to be run atomically and so is |
| 3856 | * lockless. |
| 3857 | */ |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3858 | ring->user_irq_get(ring); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3859 | ret = wait_event_interruptible(ring->irq_queue, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3860 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3861 | || atomic_read(&dev_priv->mm.wedged)); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3862 | ring->user_irq_put(ring); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3863 | |
| 3864 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
| 3865 | ret = -EIO; |
| 3866 | } |
| 3867 | |
| 3868 | if (ret == 0) |
| 3869 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3870 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3871 | return ret; |
| 3872 | } |
| 3873 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3874 | static int |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3875 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec, |
| 3876 | uint64_t exec_offset) |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3877 | { |
| 3878 | uint32_t exec_start, exec_len; |
| 3879 | |
| 3880 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
| 3881 | exec_len = (uint32_t) exec->batch_len; |
| 3882 | |
| 3883 | if ((exec_start | exec_len) & 0x7) |
| 3884 | return -EINVAL; |
| 3885 | |
| 3886 | if (!exec_start) |
| 3887 | return -EINVAL; |
| 3888 | |
| 3889 | return 0; |
| 3890 | } |
| 3891 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3892 | static int |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3893 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
| 3894 | int count) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3895 | { |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3896 | int i; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3897 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3898 | for (i = 0; i < count; i++) { |
| 3899 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; |
Chris Wilson | d1d7883 | 2010-11-21 09:23:48 +0000 | [diff] [blame] | 3900 | int length; /* limited by fault_in_pages_readable() */ |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3901 | |
Chris Wilson | d1d7883 | 2010-11-21 09:23:48 +0000 | [diff] [blame] | 3902 | /* First check for malicious input causing overflow */ |
| 3903 | if (exec[i].relocation_count > |
| 3904 | INT_MAX / sizeof(struct drm_i915_gem_relocation_entry)) |
| 3905 | return -EINVAL; |
| 3906 | |
| 3907 | length = exec[i].relocation_count * |
| 3908 | sizeof(struct drm_i915_gem_relocation_entry); |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3909 | if (!access_ok(VERIFY_READ, ptr, length)) |
| 3910 | return -EFAULT; |
| 3911 | |
Chris Wilson | b5dc608 | 2010-10-20 20:59:57 +0100 | [diff] [blame] | 3912 | /* we may also need to update the presumed offsets */ |
| 3913 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
| 3914 | return -EFAULT; |
| 3915 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3916 | if (fault_in_pages_readable(ptr, length)) |
| 3917 | return -EFAULT; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3918 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3919 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3920 | return 0; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3921 | } |
| 3922 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3923 | static int |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3924 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3925 | struct drm_file *file, |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3926 | struct drm_i915_gem_execbuffer2 *args, |
| 3927 | struct drm_i915_gem_exec_object2 *exec_list) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3928 | { |
| 3929 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3930 | struct drm_i915_gem_object **object_list = NULL; |
| 3931 | struct drm_i915_gem_object *batch_obj; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3932 | struct drm_clip_rect *cliprects = NULL; |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3933 | struct drm_i915_gem_request *request = NULL; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3934 | int ret, i, flips; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3935 | uint64_t exec_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3936 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3937 | struct intel_ring_buffer *ring = NULL; |
| 3938 | |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3939 | ret = i915_gem_check_is_wedged(dev); |
| 3940 | if (ret) |
| 3941 | return ret; |
| 3942 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3943 | ret = validate_exec_list(exec_list, args->buffer_count); |
| 3944 | if (ret) |
| 3945 | return ret; |
| 3946 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3947 | #if WATCH_EXEC |
| 3948 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3949 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3950 | #endif |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3951 | switch (args->flags & I915_EXEC_RING_MASK) { |
| 3952 | case I915_EXEC_DEFAULT: |
| 3953 | case I915_EXEC_RENDER: |
| 3954 | ring = &dev_priv->render_ring; |
| 3955 | break; |
| 3956 | case I915_EXEC_BSD: |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3957 | if (!HAS_BSD(dev)) { |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3958 | DRM_ERROR("execbuf with invalid ring (BSD)\n"); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3959 | return -EINVAL; |
| 3960 | } |
| 3961 | ring = &dev_priv->bsd_ring; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3962 | break; |
| 3963 | case I915_EXEC_BLT: |
| 3964 | if (!HAS_BLT(dev)) { |
| 3965 | DRM_ERROR("execbuf with invalid ring (BLT)\n"); |
| 3966 | return -EINVAL; |
| 3967 | } |
| 3968 | ring = &dev_priv->blt_ring; |
| 3969 | break; |
| 3970 | default: |
| 3971 | DRM_ERROR("execbuf with unknown ring: %d\n", |
| 3972 | (int)(args->flags & I915_EXEC_RING_MASK)); |
| 3973 | return -EINVAL; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3974 | } |
| 3975 | |
Eric Anholt | 4f481ed | 2008-09-10 14:22:49 -0700 | [diff] [blame] | 3976 | if (args->buffer_count < 1) { |
| 3977 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 3978 | return -EINVAL; |
| 3979 | } |
Eric Anholt | c8e0f93 | 2009-11-22 03:49:37 +0100 | [diff] [blame] | 3980 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3981 | if (object_list == NULL) { |
| 3982 | DRM_ERROR("Failed to allocate object list for %d buffers\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3983 | args->buffer_count); |
| 3984 | ret = -ENOMEM; |
| 3985 | goto pre_mutex_err; |
| 3986 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3987 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3988 | if (args->num_cliprects != 0) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3989 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
| 3990 | GFP_KERNEL); |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3991 | if (cliprects == NULL) { |
| 3992 | ret = -ENOMEM; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3993 | goto pre_mutex_err; |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3994 | } |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3995 | |
| 3996 | ret = copy_from_user(cliprects, |
| 3997 | (struct drm_clip_rect __user *) |
| 3998 | (uintptr_t) args->cliprects_ptr, |
| 3999 | sizeof(*cliprects) * args->num_cliprects); |
| 4000 | if (ret != 0) { |
| 4001 | DRM_ERROR("copy %d cliprects failed: %d\n", |
| 4002 | args->num_cliprects, ret); |
Dan Carpenter | c877cdc | 2010-06-23 19:03:01 +0200 | [diff] [blame] | 4003 | ret = -EFAULT; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 4004 | goto pre_mutex_err; |
| 4005 | } |
| 4006 | } |
| 4007 | |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 4008 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 4009 | if (request == NULL) { |
| 4010 | ret = -ENOMEM; |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 4011 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4012 | } |
| 4013 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4014 | ret = i915_mutex_lock_interruptible(dev); |
| 4015 | if (ret) |
| 4016 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4017 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4018 | if (dev_priv->mm.suspended) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4019 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 4020 | ret = -EBUSY; |
| 4021 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4022 | } |
| 4023 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 4024 | /* Look up object handles */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4025 | for (i = 0; i < args->buffer_count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4026 | struct drm_i915_gem_object *obj; |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 4027 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4028 | obj = to_intel_bo (drm_gem_object_lookup(dev, file, |
| 4029 | exec_list[i].handle)); |
| 4030 | if (obj == NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4031 | DRM_ERROR("Invalid object handle %d at index %d\n", |
| 4032 | exec_list[i].handle, i); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 4033 | /* prevent error path from reading uninitialized data */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4034 | args->buffer_count = i; |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 4035 | ret = -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4036 | goto err; |
| 4037 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4038 | object_list[i] = obj; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 4039 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4040 | if (obj->in_execbuffer) { |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 4041 | DRM_ERROR("Object %p appears more than once in object list\n", |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4042 | obj); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 4043 | /* prevent error path from reading uninitialized data */ |
| 4044 | args->buffer_count = i + 1; |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 4045 | ret = -EINVAL; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 4046 | goto err; |
| 4047 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4048 | obj->in_execbuffer = true; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 4049 | obj->pending_fenced_gpu_access = false; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4050 | } |
| 4051 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 4052 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 4053 | ret = i915_gem_execbuffer_reserve(dev, file, |
| 4054 | object_list, exec_list, |
| 4055 | args->buffer_count); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 4056 | if (ret) |
| 4057 | goto err; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 4058 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 4059 | /* The objects are in their final locations, apply the relocations. */ |
Chris Wilson | bcf50e2 | 2010-11-21 22:07:12 +0000 | [diff] [blame] | 4060 | ret = i915_gem_execbuffer_relocate(dev, file, |
| 4061 | object_list, exec_list, |
| 4062 | args->buffer_count); |
| 4063 | if (ret) { |
| 4064 | if (ret == -EFAULT) { |
| 4065 | ret = i915_gem_execbuffer_relocate_slow(dev, file, |
| 4066 | object_list, |
| 4067 | exec_list, |
| 4068 | args->buffer_count); |
| 4069 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 4070 | } |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 4071 | if (ret) |
| 4072 | goto err; |
| 4073 | } |
| 4074 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4075 | /* Set the pending read domains for the batch buffer to COMMAND */ |
| 4076 | batch_obj = object_list[args->buffer_count-1]; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4077 | if (batch_obj->base.pending_write_domain) { |
Chris Wilson | 5f26a2c | 2009-06-06 09:45:58 +0100 | [diff] [blame] | 4078 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); |
| 4079 | ret = -EINVAL; |
| 4080 | goto err; |
| 4081 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4082 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4083 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 4084 | /* Sanity check the batch buffer */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4085 | exec_offset = batch_obj->gtt_offset; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 4086 | ret = i915_gem_check_execbuffer(args, exec_offset); |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 4087 | if (ret != 0) { |
| 4088 | DRM_ERROR("execbuf with invalid offset/length\n"); |
| 4089 | goto err; |
| 4090 | } |
| 4091 | |
Chris Wilson | 13b2928 | 2010-11-01 12:22:48 +0000 | [diff] [blame] | 4092 | ret = i915_gem_execbuffer_move_to_gpu(dev, file, ring, |
| 4093 | object_list, args->buffer_count); |
| 4094 | if (ret) |
| 4095 | goto err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4096 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4097 | #if WATCH_COHERENCY |
| 4098 | for (i = 0; i < args->buffer_count; i++) { |
| 4099 | i915_gem_object_check_coherency(object_list[i], |
| 4100 | exec_list[i].handle); |
| 4101 | } |
| 4102 | #endif |
| 4103 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4104 | #if WATCH_EXEC |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 4105 | i915_gem_dump_object(batch_obj, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4106 | args->batch_len, |
| 4107 | __func__, |
| 4108 | ~0); |
| 4109 | #endif |
| 4110 | |
Chris Wilson | e59f2ba | 2010-10-07 17:28:15 +0100 | [diff] [blame] | 4111 | /* Check for any pending flips. As we only maintain a flip queue depth |
| 4112 | * of 1, we can simply insert a WAIT for the next display flip prior |
| 4113 | * to executing the batch and avoid stalling the CPU. |
| 4114 | */ |
| 4115 | flips = 0; |
| 4116 | for (i = 0; i < args->buffer_count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4117 | if (object_list[i]->base.write_domain) |
| 4118 | flips |= atomic_read(&object_list[i]->pending_flip); |
Chris Wilson | e59f2ba | 2010-10-07 17:28:15 +0100 | [diff] [blame] | 4119 | } |
| 4120 | if (flips) { |
| 4121 | int plane, flip_mask; |
| 4122 | |
| 4123 | for (plane = 0; flips >> plane; plane++) { |
| 4124 | if (((flips >> plane) & 1) == 0) |
| 4125 | continue; |
| 4126 | |
| 4127 | if (plane) |
| 4128 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 4129 | else |
| 4130 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
| 4131 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 4132 | ret = intel_ring_begin(ring, 2); |
| 4133 | if (ret) |
| 4134 | goto err; |
| 4135 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 4136 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
| 4137 | intel_ring_emit(ring, MI_NOOP); |
| 4138 | intel_ring_advance(ring); |
Chris Wilson | e59f2ba | 2010-10-07 17:28:15 +0100 | [diff] [blame] | 4139 | } |
| 4140 | } |
| 4141 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4142 | /* Exec the batchbuffer */ |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 4143 | ret = ring->dispatch_execbuffer(ring, args, cliprects, exec_offset); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4144 | if (ret) { |
| 4145 | DRM_ERROR("dispatch failed %d\n", ret); |
| 4146 | goto err; |
| 4147 | } |
| 4148 | |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 4149 | for (i = 0; i < args->buffer_count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4150 | struct drm_i915_gem_object *obj = object_list[i]; |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 4151 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4152 | obj->base.read_domains = obj->base.pending_read_domains; |
| 4153 | obj->base.write_domain = obj->base.pending_write_domain; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 4154 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 4155 | |
| 4156 | i915_gem_object_move_to_active(obj, ring); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4157 | if (obj->base.write_domain) { |
| 4158 | obj->dirty = 1; |
| 4159 | list_move_tail(&obj->gpu_write_list, |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 4160 | &ring->gpu_write_list); |
| 4161 | intel_mark_busy(dev, obj); |
| 4162 | } |
| 4163 | |
| 4164 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4165 | obj->base.read_domains, |
| 4166 | obj->base.write_domain); |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 4167 | } |
| 4168 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4169 | /* |
| 4170 | * Ensure that the commands in the batch buffer are |
| 4171 | * finished before the interrupt fires |
| 4172 | */ |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 4173 | i915_retire_commands(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4174 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 4175 | if (i915_add_request(dev, file, request, ring)) |
Chris Wilson | 5d97eb6 | 2010-11-10 20:40:02 +0000 | [diff] [blame] | 4176 | i915_gem_next_request_seqno(dev, ring); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 4177 | else |
| 4178 | request = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4179 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4180 | err: |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 4181 | for (i = 0; i < args->buffer_count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4182 | object_list[i]->in_execbuffer = false; |
| 4183 | drm_gem_object_unreference(&object_list[i]->base); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 4184 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 4185 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4186 | mutex_unlock(&dev->struct_mutex); |
| 4187 | |
Chris Wilson | 93533c2 | 2010-01-31 10:40:48 +0000 | [diff] [blame] | 4188 | pre_mutex_err: |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 4189 | drm_free_large(object_list); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4190 | kfree(cliprects); |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 4191 | kfree(request); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4192 | |
| 4193 | return ret; |
| 4194 | } |
| 4195 | |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4196 | /* |
| 4197 | * Legacy execbuffer just creates an exec2 list from the original exec object |
| 4198 | * list array and passes it to the real function. |
| 4199 | */ |
| 4200 | int |
| 4201 | i915_gem_execbuffer(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4202 | struct drm_file *file) |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4203 | { |
| 4204 | struct drm_i915_gem_execbuffer *args = data; |
| 4205 | struct drm_i915_gem_execbuffer2 exec2; |
| 4206 | struct drm_i915_gem_exec_object *exec_list = NULL; |
| 4207 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 4208 | int ret, i; |
| 4209 | |
| 4210 | #if WATCH_EXEC |
| 4211 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 4212 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 4213 | #endif |
| 4214 | |
| 4215 | if (args->buffer_count < 1) { |
| 4216 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 4217 | return -EINVAL; |
| 4218 | } |
| 4219 | |
| 4220 | /* Copy in the exec list from userland */ |
| 4221 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); |
| 4222 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 4223 | if (exec_list == NULL || exec2_list == NULL) { |
| 4224 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 4225 | args->buffer_count); |
| 4226 | drm_free_large(exec_list); |
| 4227 | drm_free_large(exec2_list); |
| 4228 | return -ENOMEM; |
| 4229 | } |
| 4230 | ret = copy_from_user(exec_list, |
| 4231 | (struct drm_i915_relocation_entry __user *) |
| 4232 | (uintptr_t) args->buffers_ptr, |
| 4233 | sizeof(*exec_list) * args->buffer_count); |
| 4234 | if (ret != 0) { |
| 4235 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 4236 | args->buffer_count, ret); |
| 4237 | drm_free_large(exec_list); |
| 4238 | drm_free_large(exec2_list); |
| 4239 | return -EFAULT; |
| 4240 | } |
| 4241 | |
| 4242 | for (i = 0; i < args->buffer_count; i++) { |
| 4243 | exec2_list[i].handle = exec_list[i].handle; |
| 4244 | exec2_list[i].relocation_count = exec_list[i].relocation_count; |
| 4245 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; |
| 4246 | exec2_list[i].alignment = exec_list[i].alignment; |
| 4247 | exec2_list[i].offset = exec_list[i].offset; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4248 | if (INTEL_INFO(dev)->gen < 4) |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4249 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
| 4250 | else |
| 4251 | exec2_list[i].flags = 0; |
| 4252 | } |
| 4253 | |
| 4254 | exec2.buffers_ptr = args->buffers_ptr; |
| 4255 | exec2.buffer_count = args->buffer_count; |
| 4256 | exec2.batch_start_offset = args->batch_start_offset; |
| 4257 | exec2.batch_len = args->batch_len; |
| 4258 | exec2.DR1 = args->DR1; |
| 4259 | exec2.DR4 = args->DR4; |
| 4260 | exec2.num_cliprects = args->num_cliprects; |
| 4261 | exec2.cliprects_ptr = args->cliprects_ptr; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4262 | exec2.flags = I915_EXEC_RENDER; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4263 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4264 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4265 | if (!ret) { |
| 4266 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 4267 | for (i = 0; i < args->buffer_count; i++) |
| 4268 | exec_list[i].offset = exec2_list[i].offset; |
| 4269 | /* ... and back out to userspace */ |
| 4270 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 4271 | (uintptr_t) args->buffers_ptr, |
| 4272 | exec_list, |
| 4273 | sizeof(*exec_list) * args->buffer_count); |
| 4274 | if (ret) { |
| 4275 | ret = -EFAULT; |
| 4276 | DRM_ERROR("failed to copy %d exec entries " |
| 4277 | "back to user (%d)\n", |
| 4278 | args->buffer_count, ret); |
| 4279 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4280 | } |
| 4281 | |
| 4282 | drm_free_large(exec_list); |
| 4283 | drm_free_large(exec2_list); |
| 4284 | return ret; |
| 4285 | } |
| 4286 | |
| 4287 | int |
| 4288 | i915_gem_execbuffer2(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4289 | struct drm_file *file) |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4290 | { |
| 4291 | struct drm_i915_gem_execbuffer2 *args = data; |
| 4292 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 4293 | int ret; |
| 4294 | |
| 4295 | #if WATCH_EXEC |
| 4296 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 4297 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 4298 | #endif |
| 4299 | |
| 4300 | if (args->buffer_count < 1) { |
| 4301 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); |
| 4302 | return -EINVAL; |
| 4303 | } |
| 4304 | |
| 4305 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 4306 | if (exec2_list == NULL) { |
| 4307 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 4308 | args->buffer_count); |
| 4309 | return -ENOMEM; |
| 4310 | } |
| 4311 | ret = copy_from_user(exec2_list, |
| 4312 | (struct drm_i915_relocation_entry __user *) |
| 4313 | (uintptr_t) args->buffers_ptr, |
| 4314 | sizeof(*exec2_list) * args->buffer_count); |
| 4315 | if (ret != 0) { |
| 4316 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 4317 | args->buffer_count, ret); |
| 4318 | drm_free_large(exec2_list); |
| 4319 | return -EFAULT; |
| 4320 | } |
| 4321 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4322 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4323 | if (!ret) { |
| 4324 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 4325 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 4326 | (uintptr_t) args->buffers_ptr, |
| 4327 | exec2_list, |
| 4328 | sizeof(*exec2_list) * args->buffer_count); |
| 4329 | if (ret) { |
| 4330 | ret = -EFAULT; |
| 4331 | DRM_ERROR("failed to copy %d exec entries " |
| 4332 | "back to user (%d)\n", |
| 4333 | args->buffer_count, ret); |
| 4334 | } |
| 4335 | } |
| 4336 | |
| 4337 | drm_free_large(exec2_list); |
| 4338 | return ret; |
| 4339 | } |
| 4340 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4341 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4342 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 4343 | uint32_t alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 4344 | bool map_and_fenceable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4345 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4346 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4347 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4348 | int ret; |
| 4349 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4350 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4351 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4352 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4353 | if (obj->gtt_space != NULL) { |
| 4354 | if ((alignment && obj->gtt_offset & (alignment - 1)) || |
| 4355 | (map_and_fenceable && !obj->map_and_fenceable)) { |
| 4356 | WARN(obj->pin_count, |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 4357 | "bo is already pinned with incorrect alignment:" |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 4358 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
| 4359 | " obj->map_and_fenceable=%d\n", |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4360 | obj->gtt_offset, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 4361 | map_and_fenceable, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4362 | obj->map_and_fenceable); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4363 | ret = i915_gem_object_unbind(obj); |
| 4364 | if (ret) |
| 4365 | return ret; |
| 4366 | } |
| 4367 | } |
| 4368 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4369 | if (obj->gtt_space == NULL) { |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 4370 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 4371 | map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 4372 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4373 | return ret; |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 4374 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4375 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4376 | if (obj->pin_count++ == 0) { |
| 4377 | i915_gem_info_add_pin(dev_priv, obj, map_and_fenceable); |
| 4378 | if (!obj->active) |
| 4379 | list_move_tail(&obj->mm_list, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4380 | &dev_priv->mm.pinned_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4381 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4382 | BUG_ON(!obj->pin_mappable && map_and_fenceable); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4383 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4384 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4385 | return 0; |
| 4386 | } |
| 4387 | |
| 4388 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4389 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4390 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4391 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4392 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4393 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4394 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4395 | BUG_ON(obj->pin_count == 0); |
| 4396 | BUG_ON(obj->gtt_space == NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4397 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4398 | if (--obj->pin_count == 0) { |
| 4399 | if (!obj->active) |
| 4400 | list_move_tail(&obj->mm_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4401 | &dev_priv->mm.inactive_list); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4402 | i915_gem_info_remove_pin(dev_priv, obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4403 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4404 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4405 | } |
| 4406 | |
| 4407 | int |
| 4408 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4409 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4410 | { |
| 4411 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4412 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4413 | int ret; |
| 4414 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4415 | ret = i915_mutex_lock_interruptible(dev); |
| 4416 | if (ret) |
| 4417 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4418 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4419 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4420 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4421 | ret = -ENOENT; |
| 4422 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4423 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4424 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4425 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4426 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4427 | ret = -EINVAL; |
| 4428 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4429 | } |
| 4430 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4431 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4432 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 4433 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4434 | ret = -EINVAL; |
| 4435 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4436 | } |
| 4437 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4438 | obj->user_pin_count++; |
| 4439 | obj->pin_filp = file; |
| 4440 | if (obj->user_pin_count == 1) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 4441 | ret = i915_gem_object_pin(obj, args->alignment, true); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4442 | if (ret) |
| 4443 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4444 | } |
| 4445 | |
| 4446 | /* XXX - flush the CPU caches for pinned objects |
| 4447 | * as the X server doesn't manage domains yet |
| 4448 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4449 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4450 | args->offset = obj->gtt_offset; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4451 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4452 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4453 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4454 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4455 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4456 | } |
| 4457 | |
| 4458 | int |
| 4459 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4460 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4461 | { |
| 4462 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4463 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4464 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4465 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4466 | ret = i915_mutex_lock_interruptible(dev); |
| 4467 | if (ret) |
| 4468 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4469 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4470 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4471 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4472 | ret = -ENOENT; |
| 4473 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4474 | } |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4475 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4476 | if (obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4477 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 4478 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4479 | ret = -EINVAL; |
| 4480 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4481 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4482 | obj->user_pin_count--; |
| 4483 | if (obj->user_pin_count == 0) { |
| 4484 | obj->pin_filp = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4485 | i915_gem_object_unpin(obj); |
| 4486 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4487 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4488 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4489 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4490 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4491 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4492 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4493 | } |
| 4494 | |
| 4495 | int |
| 4496 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4497 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4498 | { |
| 4499 | struct drm_i915_gem_busy *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4500 | struct drm_i915_gem_object *obj; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4501 | int ret; |
| 4502 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4503 | ret = i915_mutex_lock_interruptible(dev); |
| 4504 | if (ret) |
| 4505 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4506 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4507 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4508 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4509 | ret = -ENOENT; |
| 4510 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4511 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4512 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4513 | /* Count all active objects as busy, even if they are currently not used |
| 4514 | * by the gpu. Users of this interface expect objects to eventually |
| 4515 | * become non-busy without any further actions, therefore emit any |
| 4516 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 4517 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4518 | args->busy = obj->active; |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4519 | if (args->busy) { |
| 4520 | /* Unconditionally flush objects, even when the gpu still uses this |
| 4521 | * object. Userspace calling this function indicates that it wants to |
| 4522 | * use this buffer rather sooner than later, so issuing the required |
| 4523 | * flush earlier is beneficial. |
| 4524 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4525 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) |
| 4526 | i915_gem_flush_ring(dev, obj->ring, |
| 4527 | 0, obj->base.write_domain); |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4528 | |
| 4529 | /* Update the active list for the hardware's current position. |
| 4530 | * Otherwise this only updates on a delayed timer or when irqs |
| 4531 | * are actually unmasked, and our working set ends up being |
| 4532 | * larger than required. |
| 4533 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4534 | i915_gem_retire_requests_ring(dev, obj->ring); |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4535 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4536 | args->busy = obj->active; |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4537 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4538 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4539 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4540 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4541 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4542 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4543 | } |
| 4544 | |
| 4545 | int |
| 4546 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4547 | struct drm_file *file_priv) |
| 4548 | { |
| 4549 | return i915_gem_ring_throttle(dev, file_priv); |
| 4550 | } |
| 4551 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4552 | int |
| 4553 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4554 | struct drm_file *file_priv) |
| 4555 | { |
| 4556 | struct drm_i915_gem_madvise *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4557 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4558 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4559 | |
| 4560 | switch (args->madv) { |
| 4561 | case I915_MADV_DONTNEED: |
| 4562 | case I915_MADV_WILLNEED: |
| 4563 | break; |
| 4564 | default: |
| 4565 | return -EINVAL; |
| 4566 | } |
| 4567 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4568 | ret = i915_mutex_lock_interruptible(dev); |
| 4569 | if (ret) |
| 4570 | return ret; |
| 4571 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4572 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4573 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4574 | ret = -ENOENT; |
| 4575 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4576 | } |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4577 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4578 | if (obj->pin_count) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4579 | ret = -EINVAL; |
| 4580 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4581 | } |
| 4582 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4583 | if (obj->madv != __I915_MADV_PURGED) |
| 4584 | obj->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4585 | |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 4586 | /* if the object is no longer bound, discard its backing storage */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4587 | if (i915_gem_object_is_purgeable(obj) && |
| 4588 | obj->gtt_space == NULL) |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 4589 | i915_gem_object_truncate(obj); |
| 4590 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4591 | args->retained = obj->madv != __I915_MADV_PURGED; |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4592 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4593 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4594 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4595 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4596 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4597 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4598 | } |
| 4599 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4600 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 4601 | size_t size) |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4602 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4603 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4604 | struct drm_i915_gem_object *obj; |
| 4605 | |
| 4606 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
| 4607 | if (obj == NULL) |
| 4608 | return NULL; |
| 4609 | |
| 4610 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
| 4611 | kfree(obj); |
| 4612 | return NULL; |
| 4613 | } |
| 4614 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4615 | i915_gem_info_add_obj(dev_priv, size); |
| 4616 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4617 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4618 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4619 | |
| 4620 | obj->agp_type = AGP_USER_MEMORY; |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 4621 | obj->base.driver_private = NULL; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4622 | obj->fence_reg = I915_FENCE_REG_NONE; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4623 | INIT_LIST_HEAD(&obj->mm_list); |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 4624 | INIT_LIST_HEAD(&obj->gtt_list); |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4625 | INIT_LIST_HEAD(&obj->ring_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4626 | INIT_LIST_HEAD(&obj->gpu_write_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4627 | obj->madv = I915_MADV_WILLNEED; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 4628 | /* Avoid an unnecessary call to unbind on the first bind. */ |
| 4629 | obj->map_and_fenceable = true; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4630 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4631 | return obj; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4632 | } |
| 4633 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4634 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 4635 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4636 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4637 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4638 | return 0; |
| 4639 | } |
| 4640 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4641 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4642 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4643 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4644 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4645 | int ret; |
| 4646 | |
| 4647 | ret = i915_gem_object_unbind(obj); |
| 4648 | if (ret == -ERESTARTSYS) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4649 | list_move(&obj->mm_list, |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4650 | &dev_priv->mm.deferred_free_list); |
| 4651 | return; |
| 4652 | } |
| 4653 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4654 | if (obj->base.map_list.map) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4655 | i915_gem_free_mmap_offset(obj); |
| 4656 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4657 | drm_gem_object_release(&obj->base); |
| 4658 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4659 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4660 | kfree(obj->page_cpu_valid); |
| 4661 | kfree(obj->bit_17); |
| 4662 | kfree(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4663 | } |
| 4664 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4665 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4666 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4667 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
| 4668 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4669 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4670 | trace_i915_gem_object_destroy(obj); |
| 4671 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4672 | while (obj->pin_count > 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4673 | i915_gem_object_unpin(obj); |
| 4674 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4675 | if (obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4676 | i915_gem_detach_phys_object(dev, obj); |
| 4677 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4678 | i915_gem_free_object_tail(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4679 | } |
| 4680 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 4681 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4682 | i915_gem_idle(struct drm_device *dev) |
| 4683 | { |
| 4684 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4685 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4686 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4687 | mutex_lock(&dev->struct_mutex); |
| 4688 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4689 | if (dev_priv->mm.suspended) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4690 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4691 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4692 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4693 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4694 | ret = i915_gpu_idle(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4695 | if (ret) { |
| 4696 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4697 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4698 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4699 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4700 | /* Under UMS, be paranoid and evict. */ |
| 4701 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { |
Chris Wilson | 5eac3ab | 2010-10-31 08:49:47 +0000 | [diff] [blame] | 4702 | ret = i915_gem_evict_inactive(dev, false); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4703 | if (ret) { |
| 4704 | mutex_unlock(&dev->struct_mutex); |
| 4705 | return ret; |
| 4706 | } |
| 4707 | } |
| 4708 | |
| 4709 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 4710 | * We need to replace this with a semaphore, or something. |
| 4711 | * And not confound mm.suspended! |
| 4712 | */ |
| 4713 | dev_priv->mm.suspended = 1; |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 4714 | del_timer_sync(&dev_priv->hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4715 | |
| 4716 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4717 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4718 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4719 | mutex_unlock(&dev->struct_mutex); |
| 4720 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4721 | /* Cancel the retire work handler, which should be idle now. */ |
| 4722 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 4723 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4724 | return 0; |
| 4725 | } |
| 4726 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4727 | int |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4728 | i915_gem_init_ringbuffer(struct drm_device *dev) |
| 4729 | { |
| 4730 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4731 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4732 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4733 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4734 | if (ret) |
Chris Wilson | b6913e4 | 2010-11-12 10:46:37 +0000 | [diff] [blame] | 4735 | return ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4736 | |
| 4737 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4738 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4739 | if (ret) |
| 4740 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4741 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4742 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4743 | if (HAS_BLT(dev)) { |
| 4744 | ret = intel_init_blt_ring_buffer(dev); |
| 4745 | if (ret) |
| 4746 | goto cleanup_bsd_ring; |
| 4747 | } |
| 4748 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 4749 | dev_priv->next_seqno = 1; |
| 4750 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4751 | return 0; |
| 4752 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4753 | cleanup_bsd_ring: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 4754 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4755 | cleanup_render_ring: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 4756 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4757 | return ret; |
| 4758 | } |
| 4759 | |
| 4760 | void |
| 4761 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4762 | { |
| 4763 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4764 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 4765 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
| 4766 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
| 4767 | intel_cleanup_ring_buffer(&dev_priv->blt_ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4768 | } |
| 4769 | |
| 4770 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4771 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 4772 | struct drm_file *file_priv) |
| 4773 | { |
| 4774 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4775 | int ret; |
| 4776 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4777 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4778 | return 0; |
| 4779 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4780 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4781 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4782 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4783 | } |
| 4784 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4785 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4786 | dev_priv->mm.suspended = 0; |
| 4787 | |
| 4788 | ret = i915_gem_init_ringbuffer(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4789 | if (ret != 0) { |
| 4790 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4791 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4792 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4793 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4794 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4795 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4796 | BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list)); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4797 | BUG_ON(!list_empty(&dev_priv->blt_ring.active_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4798 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 4799 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4800 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4801 | BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list)); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4802 | BUG_ON(!list_empty(&dev_priv->blt_ring.request_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4803 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4804 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4805 | ret = drm_irq_install(dev); |
| 4806 | if (ret) |
| 4807 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4808 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4809 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4810 | |
| 4811 | cleanup_ringbuffer: |
| 4812 | mutex_lock(&dev->struct_mutex); |
| 4813 | i915_gem_cleanup_ringbuffer(dev); |
| 4814 | dev_priv->mm.suspended = 1; |
| 4815 | mutex_unlock(&dev->struct_mutex); |
| 4816 | |
| 4817 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4818 | } |
| 4819 | |
| 4820 | int |
| 4821 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 4822 | struct drm_file *file_priv) |
| 4823 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4824 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4825 | return 0; |
| 4826 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4827 | drm_irq_uninstall(dev); |
Linus Torvalds | e6890f6 | 2009-09-08 17:09:24 -0700 | [diff] [blame] | 4828 | return i915_gem_idle(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4829 | } |
| 4830 | |
| 4831 | void |
| 4832 | i915_gem_lastclose(struct drm_device *dev) |
| 4833 | { |
| 4834 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4835 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 4836 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4837 | return; |
| 4838 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4839 | ret = i915_gem_idle(dev); |
| 4840 | if (ret) |
| 4841 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4842 | } |
| 4843 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4844 | static void |
| 4845 | init_ring_lists(struct intel_ring_buffer *ring) |
| 4846 | { |
| 4847 | INIT_LIST_HEAD(&ring->active_list); |
| 4848 | INIT_LIST_HEAD(&ring->request_list); |
| 4849 | INIT_LIST_HEAD(&ring->gpu_write_list); |
| 4850 | } |
| 4851 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4852 | void |
| 4853 | i915_gem_load(struct drm_device *dev) |
| 4854 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4855 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4856 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4857 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4858 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4859 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
| 4860 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4861 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4862 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4863 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 4864 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4865 | init_ring_lists(&dev_priv->render_ring); |
| 4866 | init_ring_lists(&dev_priv->bsd_ring); |
| 4867 | init_ring_lists(&dev_priv->blt_ring); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 4868 | for (i = 0; i < 16; i++) |
| 4869 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4870 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 4871 | i915_gem_retire_work_handler); |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4872 | init_completion(&dev_priv->error_completion); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4873 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4874 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 4875 | if (IS_GEN3(dev)) { |
| 4876 | u32 tmp = I915_READ(MI_ARB_STATE); |
| 4877 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { |
| 4878 | /* arb state is a masked write, so set bit + bit in mask */ |
| 4879 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); |
| 4880 | I915_WRITE(MI_ARB_STATE, tmp); |
| 4881 | } |
| 4882 | } |
| 4883 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4884 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 4885 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4886 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4887 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4888 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4889 | dev_priv->num_fence_regs = 16; |
| 4890 | else |
| 4891 | dev_priv->num_fence_regs = 8; |
| 4892 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4893 | /* Initialize fence registers to zero */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4894 | switch (INTEL_INFO(dev)->gen) { |
| 4895 | case 6: |
| 4896 | for (i = 0; i < 16; i++) |
| 4897 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); |
| 4898 | break; |
| 4899 | case 5: |
| 4900 | case 4: |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4901 | for (i = 0; i < 16; i++) |
| 4902 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4903 | break; |
| 4904 | case 3: |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4905 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 4906 | for (i = 0; i < 8; i++) |
| 4907 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4908 | case 2: |
| 4909 | for (i = 0; i < 8; i++) |
| 4910 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); |
| 4911 | break; |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4912 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4913 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4914 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4915 | |
| 4916 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
| 4917 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
| 4918 | register_shrinker(&dev_priv->mm.inactive_shrinker); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4919 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4920 | |
| 4921 | /* |
| 4922 | * Create a physically contiguous memory object for this object |
| 4923 | * e.g. for cursor + overlay regs |
| 4924 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4925 | static int i915_gem_init_phys_object(struct drm_device *dev, |
| 4926 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4927 | { |
| 4928 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4929 | struct drm_i915_gem_phys_object *phys_obj; |
| 4930 | int ret; |
| 4931 | |
| 4932 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 4933 | return 0; |
| 4934 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4935 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4936 | if (!phys_obj) |
| 4937 | return -ENOMEM; |
| 4938 | |
| 4939 | phys_obj->id = id; |
| 4940 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4941 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4942 | if (!phys_obj->handle) { |
| 4943 | ret = -ENOMEM; |
| 4944 | goto kfree_obj; |
| 4945 | } |
| 4946 | #ifdef CONFIG_X86 |
| 4947 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4948 | #endif |
| 4949 | |
| 4950 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 4951 | |
| 4952 | return 0; |
| 4953 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4954 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4955 | return ret; |
| 4956 | } |
| 4957 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4958 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4959 | { |
| 4960 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4961 | struct drm_i915_gem_phys_object *phys_obj; |
| 4962 | |
| 4963 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 4964 | return; |
| 4965 | |
| 4966 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4967 | if (phys_obj->cur_obj) { |
| 4968 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 4969 | } |
| 4970 | |
| 4971 | #ifdef CONFIG_X86 |
| 4972 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4973 | #endif |
| 4974 | drm_pci_free(dev, phys_obj->handle); |
| 4975 | kfree(phys_obj); |
| 4976 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 4977 | } |
| 4978 | |
| 4979 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 4980 | { |
| 4981 | int i; |
| 4982 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 4983 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4984 | i915_gem_free_phys_object(dev, i); |
| 4985 | } |
| 4986 | |
| 4987 | void i915_gem_detach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4988 | struct drm_i915_gem_object *obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4989 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4990 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4991 | char *vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4992 | int i; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4993 | int page_count; |
| 4994 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4995 | if (!obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4996 | return; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4997 | vaddr = obj->phys_obj->handle->vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4998 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4999 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5000 | for (i = 0; i < page_count; i++) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 5001 | struct page *page = read_cache_page_gfp(mapping, i, |
| 5002 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 5003 | if (!IS_ERR(page)) { |
| 5004 | char *dst = kmap_atomic(page); |
| 5005 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); |
| 5006 | kunmap_atomic(dst); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5007 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 5008 | drm_clflush_pages(&page, 1); |
| 5009 | |
| 5010 | set_page_dirty(page); |
| 5011 | mark_page_accessed(page); |
| 5012 | page_cache_release(page); |
| 5013 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5014 | } |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 5015 | intel_gtt_chipset_flush(); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 5016 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5017 | obj->phys_obj->cur_obj = NULL; |
| 5018 | obj->phys_obj = NULL; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5019 | } |
| 5020 | |
| 5021 | int |
| 5022 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5023 | struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 5024 | int id, |
| 5025 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5026 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5027 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5028 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5029 | int ret = 0; |
| 5030 | int page_count; |
| 5031 | int i; |
| 5032 | |
| 5033 | if (id > I915_MAX_PHYS_OBJECT) |
| 5034 | return -EINVAL; |
| 5035 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5036 | if (obj->phys_obj) { |
| 5037 | if (obj->phys_obj->id == id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5038 | return 0; |
| 5039 | i915_gem_detach_phys_object(dev, obj); |
| 5040 | } |
| 5041 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5042 | /* create a new object */ |
| 5043 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 5044 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5045 | obj->base.size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5046 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5047 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
| 5048 | id, obj->base.size); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 5049 | return ret; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5050 | } |
| 5051 | } |
| 5052 | |
| 5053 | /* bind to the object */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5054 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 5055 | obj->phys_obj->cur_obj = obj; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5056 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5057 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5058 | |
| 5059 | for (i = 0; i < page_count; i++) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 5060 | struct page *page; |
| 5061 | char *dst, *src; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5062 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 5063 | page = read_cache_page_gfp(mapping, i, |
| 5064 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 5065 | if (IS_ERR(page)) |
| 5066 | return PTR_ERR(page); |
| 5067 | |
Chris Wilson | ff75b9b | 2010-10-30 22:52:31 +0100 | [diff] [blame] | 5068 | src = kmap_atomic(page); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5069 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5070 | memcpy(dst, src, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 5071 | kunmap_atomic(src); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 5072 | |
| 5073 | mark_page_accessed(page); |
| 5074 | page_cache_release(page); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5075 | } |
| 5076 | |
| 5077 | return 0; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5078 | } |
| 5079 | |
| 5080 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5081 | i915_gem_phys_pwrite(struct drm_device *dev, |
| 5082 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5083 | struct drm_i915_gem_pwrite *args, |
| 5084 | struct drm_file *file_priv) |
| 5085 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5086 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 5087 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5088 | |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 5089 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 5090 | unsigned long unwritten; |
| 5091 | |
| 5092 | /* The physical object once assigned is fixed for the lifetime |
| 5093 | * of the obj, so we can safely drop the lock and continue |
| 5094 | * to access vaddr. |
| 5095 | */ |
| 5096 | mutex_unlock(&dev->struct_mutex); |
| 5097 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 5098 | mutex_lock(&dev->struct_mutex); |
| 5099 | if (unwritten) |
| 5100 | return -EFAULT; |
| 5101 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5102 | |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 5103 | intel_gtt_chipset_flush(); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5104 | return 0; |
| 5105 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5106 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5107 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5108 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5109 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5110 | |
| 5111 | /* Clean up our request list when the client is going away, so that |
| 5112 | * later retire_requests won't dereference our soon-to-be-gone |
| 5113 | * file_priv. |
| 5114 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 5115 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5116 | while (!list_empty(&file_priv->mm.request_list)) { |
| 5117 | struct drm_i915_gem_request *request; |
| 5118 | |
| 5119 | request = list_first_entry(&file_priv->mm.request_list, |
| 5120 | struct drm_i915_gem_request, |
| 5121 | client_list); |
| 5122 | list_del(&request->client_list); |
| 5123 | request->file_priv = NULL; |
| 5124 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 5125 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5126 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5127 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5128 | static int |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5129 | i915_gpu_is_active(struct drm_device *dev) |
| 5130 | { |
| 5131 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 5132 | int lists_empty; |
| 5133 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5134 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5135 | list_empty(&dev_priv->mm.active_list); |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5136 | |
| 5137 | return !lists_empty; |
| 5138 | } |
| 5139 | |
| 5140 | static int |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5141 | i915_gem_inactive_shrink(struct shrinker *shrinker, |
| 5142 | int nr_to_scan, |
| 5143 | gfp_t gfp_mask) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5144 | { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5145 | struct drm_i915_private *dev_priv = |
| 5146 | container_of(shrinker, |
| 5147 | struct drm_i915_private, |
| 5148 | mm.inactive_shrinker); |
| 5149 | struct drm_device *dev = dev_priv->dev; |
| 5150 | struct drm_i915_gem_object *obj, *next; |
| 5151 | int cnt; |
| 5152 | |
| 5153 | if (!mutex_trylock(&dev->struct_mutex)) |
Chris Wilson | bbe2e11 | 2010-10-28 22:35:07 +0100 | [diff] [blame] | 5154 | return 0; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5155 | |
| 5156 | /* "fast-path" to count number of available objects */ |
| 5157 | if (nr_to_scan == 0) { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5158 | cnt = 0; |
| 5159 | list_for_each_entry(obj, |
| 5160 | &dev_priv->mm.inactive_list, |
| 5161 | mm_list) |
| 5162 | cnt++; |
| 5163 | mutex_unlock(&dev->struct_mutex); |
| 5164 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5165 | } |
| 5166 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5167 | rescan: |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5168 | /* first scan for clean buffers */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5169 | i915_gem_retire_requests(dev); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5170 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5171 | list_for_each_entry_safe(obj, next, |
| 5172 | &dev_priv->mm.inactive_list, |
| 5173 | mm_list) { |
| 5174 | if (i915_gem_object_is_purgeable(obj)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5175 | i915_gem_object_unbind(obj); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5176 | if (--nr_to_scan == 0) |
| 5177 | break; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5178 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5179 | } |
| 5180 | |
| 5181 | /* second pass, evict/count anything still on the inactive list */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5182 | cnt = 0; |
| 5183 | list_for_each_entry_safe(obj, next, |
| 5184 | &dev_priv->mm.inactive_list, |
| 5185 | mm_list) { |
| 5186 | if (nr_to_scan) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5187 | i915_gem_object_unbind(obj); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5188 | nr_to_scan--; |
| 5189 | } else |
| 5190 | cnt++; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5191 | } |
| 5192 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5193 | if (nr_to_scan && i915_gpu_is_active(dev)) { |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5194 | /* |
| 5195 | * We are desperate for pages, so as a last resort, wait |
| 5196 | * for the GPU to finish and discard whatever we can. |
| 5197 | * This has a dramatic impact to reduce the number of |
| 5198 | * OOM-killer events whilst running the GPU aggressively. |
| 5199 | */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5200 | if (i915_gpu_idle(dev) == 0) |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5201 | goto rescan; |
| 5202 | } |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5203 | mutex_unlock(&dev->struct_mutex); |
| 5204 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5205 | } |