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Chaithrika U Sb67f4482009-06-05 06:28:40 -04001/*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040022#include <linux/delay.h>
23#include <linux/io.h>
Peter Ujfalusiae726e92013-11-14 11:35:35 +020024#include <linux/clk.h>
Hebbar, Gururaja10884342012-08-08 20:40:32 +053025#include <linux/pm_runtime.h>
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +053026#include <linux/of.h>
27#include <linux/of_platform.h>
28#include <linux/of_device.h>
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +020029#include <linux/platform_data/davinci_asp.h>
Jyri Sarhaa75a0532015-03-20 13:31:08 +020030#include <linux/math64.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040031
Daniel Mack64792852014-03-27 11:27:40 +010032#include <sound/asoundef.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040033#include <sound/core.h>
34#include <sound/pcm.h>
35#include <sound/pcm_params.h>
36#include <sound/initval.h>
37#include <sound/soc.h>
Peter Ujfalusi453c4992013-11-14 11:35:34 +020038#include <sound/dmaengine_pcm.h>
Jyri Sarha87c19362014-05-26 11:51:14 +030039#include <sound/omap-pcm.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040040
Peter Ujfalusif3f9cfa2014-07-16 15:12:04 +030041#include "edma-pcm.h"
Chaithrika U Sb67f4482009-06-05 06:28:40 -040042#include "davinci-mcasp.h"
43
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +030044#define MCASP_MAX_AFIFO_DEPTH 64
45
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +030046static u32 context_regs[] = {
47 DAVINCI_MCASP_TXFMCTL_REG,
48 DAVINCI_MCASP_RXFMCTL_REG,
49 DAVINCI_MCASP_TXFMT_REG,
50 DAVINCI_MCASP_RXFMT_REG,
51 DAVINCI_MCASP_ACLKXCTL_REG,
52 DAVINCI_MCASP_ACLKRCTL_REG,
Peter Ujfalusif114ce62014-10-01 16:02:12 +030053 DAVINCI_MCASP_AHCLKXCTL_REG,
54 DAVINCI_MCASP_AHCLKRCTL_REG,
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +030055 DAVINCI_MCASP_PDIR_REG,
Peter Ujfalusif114ce62014-10-01 16:02:12 +030056 DAVINCI_MCASP_RXMASK_REG,
57 DAVINCI_MCASP_TXMASK_REG,
58 DAVINCI_MCASP_RXTDM_REG,
59 DAVINCI_MCASP_TXTDM_REG,
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +030060};
61
Peter Ujfalusi790bb942014-02-03 14:51:52 +020062struct davinci_mcasp_context {
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +030063 u32 config_regs[ARRAY_SIZE(context_regs)];
Peter Ujfalusif114ce62014-10-01 16:02:12 +030064 u32 afifo_regs[2]; /* for read/write fifo control registers */
65 u32 *xrsr_regs; /* for serializer configuration */
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +020066 bool pm_state;
Peter Ujfalusi790bb942014-02-03 14:51:52 +020067};
68
Jyri Sarhaa75a0532015-03-20 13:31:08 +020069struct davinci_mcasp_ruledata {
70 struct davinci_mcasp *mcasp;
71 int serializers;
72};
73
Peter Ujfalusi70091a32013-11-14 11:35:29 +020074struct davinci_mcasp {
Peter Ujfalusi453c4992013-11-14 11:35:34 +020075 struct snd_dmaengine_dai_dma_data dma_data[2];
Peter Ujfalusi21400a72013-11-14 11:35:26 +020076 void __iomem *base;
Peter Ujfalusi487dce82013-11-14 11:35:31 +020077 u32 fifo_base;
Peter Ujfalusi21400a72013-11-14 11:35:26 +020078 struct device *dev;
Misael Lopez Cruza7a33242014-11-12 16:38:05 +020079 struct snd_pcm_substream *substreams[2];
Peter Ujfalusi21400a72013-11-14 11:35:26 +020080
81 /* McASP specific data */
82 int tdm_slots;
83 u8 op_mode;
84 u8 num_serializer;
85 u8 *serial_dir;
86 u8 version;
Daniel Mack82675252014-07-16 14:04:41 +020087 u8 bclk_div;
Peter Ujfalusi21400a72013-11-14 11:35:26 +020088 u16 bclk_lrclk_ratio;
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +020089 int streams;
Misael Lopez Cruza7a33242014-11-12 16:38:05 +020090 u32 irq_request[2];
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +020091 int dma_request[2];
Peter Ujfalusi21400a72013-11-14 11:35:26 +020092
Jyri Sarhaab8b14b2014-01-27 17:37:52 +020093 int sysclk_freq;
94 bool bclk_master;
95
Peter Ujfalusi21400a72013-11-14 11:35:26 +020096 /* McASP FIFO related */
97 u8 txnumevt;
98 u8 rxnumevt;
99
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +0200100 bool dat_port;
101
Peter Ujfalusi11277832014-11-10 12:32:16 +0200102 /* Used for comstraint setting on the second stream */
103 u32 channels;
104
Peter Ujfalusi21400a72013-11-14 11:35:26 +0200105#ifdef CONFIG_PM_SLEEP
Peter Ujfalusi790bb942014-02-03 14:51:52 +0200106 struct davinci_mcasp_context context;
Peter Ujfalusi21400a72013-11-14 11:35:26 +0200107#endif
Jyri Sarhaa75a0532015-03-20 13:31:08 +0200108
109 struct davinci_mcasp_ruledata ruledata[2];
Peter Ujfalusi21400a72013-11-14 11:35:26 +0200110};
111
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200112static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
113 u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400114{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200115 void __iomem *reg = mcasp->base + offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400116 __raw_writel(__raw_readl(reg) | val, reg);
117}
118
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200119static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
120 u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400121{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200122 void __iomem *reg = mcasp->base + offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400123 __raw_writel((__raw_readl(reg) & ~(val)), reg);
124}
125
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200126static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
127 u32 val, u32 mask)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400128{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200129 void __iomem *reg = mcasp->base + offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400130 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
131}
132
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200133static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
134 u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400135{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200136 __raw_writel(val, mcasp->base + offset);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400137}
138
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200139static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400140{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200141 return (u32)__raw_readl(mcasp->base + offset);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400142}
143
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200144static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400145{
146 int i = 0;
147
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200148 mcasp_set_bits(mcasp, ctl_reg, val);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400149
150 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
151 /* loop count is to avoid the lock-up */
152 for (i = 0; i < 1000; i++) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200153 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400154 break;
155 }
156
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200157 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400158 printk(KERN_ERR "GBLCTL write error\n");
159}
160
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200161static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
162{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200163 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
164 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200165
166 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
167}
168
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200169static void mcasp_start_rx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400170{
Peter Ujfalusibb372af2014-10-29 13:55:47 +0200171 if (mcasp->rxnumevt) { /* enable FIFO */
172 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
173
174 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
175 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
176 }
177
Peter Ujfalusi44982732014-10-29 13:55:45 +0200178 /* Start clocks */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200179 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
180 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200181 /*
182 * When ASYNC == 0 the transmit and receive sections operate
183 * synchronously from the transmit clock and frame sync. We need to make
184 * sure that the TX signlas are enabled when starting reception.
185 */
186 if (mcasp_is_synchronous(mcasp)) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200187 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
188 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200189 }
190
Peter Ujfalusi44982732014-10-29 13:55:45 +0200191 /* Activate serializer(s) */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200192 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
Peter Ujfalusi44982732014-10-29 13:55:45 +0200193 /* Release RX state machine */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200194 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
Peter Ujfalusi44982732014-10-29 13:55:45 +0200195 /* Release Frame Sync generator */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200196 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200197 if (mcasp_is_synchronous(mcasp))
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200198 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
Misael Lopez Cruza7a33242014-11-12 16:38:05 +0200199
200 /* enable receive IRQs */
201 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
202 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400203}
204
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200205static void mcasp_start_tx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400206{
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400207 u32 cnt;
208
Peter Ujfalusibb372af2014-10-29 13:55:47 +0200209 if (mcasp->txnumevt) { /* enable FIFO */
210 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
211
212 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
213 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
214 }
215
Peter Ujfalusi36bcecd2014-10-29 13:55:44 +0200216 /* Start clocks */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200217 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
218 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
Peter Ujfalusi36bcecd2014-10-29 13:55:44 +0200219 /* Activate serializer(s) */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200220 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400221
Peter Ujfalusi36bcecd2014-10-29 13:55:44 +0200222 /* wait for XDATA to be cleared */
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400223 cnt = 0;
Peter Ujfalusi36bcecd2014-10-29 13:55:44 +0200224 while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) &
225 ~XRDATA) && (cnt < 100000))
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400226 cnt++;
227
Peter Ujfalusi36bcecd2014-10-29 13:55:44 +0200228 /* Release TX state machine */
229 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
230 /* Release Frame Sync generator */
231 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
Misael Lopez Cruza7a33242014-11-12 16:38:05 +0200232
233 /* enable transmit IRQs */
234 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
235 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400236}
237
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200238static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400239{
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200240 mcasp->streams++;
241
Peter Ujfalusibb372af2014-10-29 13:55:47 +0200242 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200243 mcasp_start_tx(mcasp);
Peter Ujfalusibb372af2014-10-29 13:55:47 +0200244 else
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200245 mcasp_start_rx(mcasp);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400246}
247
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200248static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400249{
Misael Lopez Cruza7a33242014-11-12 16:38:05 +0200250 /* disable IRQ sources */
251 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
252 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
253
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200254 /*
255 * In synchronous mode stop the TX clocks if no other stream is
256 * running
257 */
258 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200259 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200260
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200261 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
262 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
Peter Ujfalusi03808662014-10-29 13:55:46 +0200263
264 if (mcasp->rxnumevt) { /* disable FIFO */
265 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
266
267 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
268 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400269}
270
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200271static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400272{
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200273 u32 val = 0;
274
Misael Lopez Cruza7a33242014-11-12 16:38:05 +0200275 /* disable IRQ sources */
276 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
277 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
278
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200279 /*
280 * In synchronous mode keep TX clocks running if the capture stream is
281 * still running.
282 */
283 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
284 val = TXHCLKRST | TXCLKRST | TXFSRST;
285
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200286 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
287 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
Peter Ujfalusi03808662014-10-29 13:55:46 +0200288
289 if (mcasp->txnumevt) { /* disable FIFO */
290 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
291
292 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
293 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400294}
295
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200296static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400297{
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200298 mcasp->streams--;
299
Peter Ujfalusi03808662014-10-29 13:55:46 +0200300 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200301 mcasp_stop_tx(mcasp);
Peter Ujfalusi03808662014-10-29 13:55:46 +0200302 else
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200303 mcasp_stop_rx(mcasp);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400304}
305
Misael Lopez Cruza7a33242014-11-12 16:38:05 +0200306static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
307{
308 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
309 struct snd_pcm_substream *substream;
310 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
311 u32 handled_mask = 0;
312 u32 stat;
313
314 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
315 if (stat & XUNDRN & irq_mask) {
316 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
317 handled_mask |= XUNDRN;
318
319 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
320 if (substream) {
321 snd_pcm_stream_lock_irq(substream);
322 if (snd_pcm_running(substream))
323 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
324 snd_pcm_stream_unlock_irq(substream);
325 }
326 }
327
328 if (!handled_mask)
329 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
330 stat);
331
332 if (stat & XRERR)
333 handled_mask |= XRERR;
334
335 /* Ack the handled event only */
336 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
337
338 return IRQ_RETVAL(handled_mask);
339}
340
341static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
342{
343 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
344 struct snd_pcm_substream *substream;
345 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
346 u32 handled_mask = 0;
347 u32 stat;
348
349 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
350 if (stat & ROVRN & irq_mask) {
351 dev_warn(mcasp->dev, "Receive buffer overflow\n");
352 handled_mask |= ROVRN;
353
354 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
355 if (substream) {
356 snd_pcm_stream_lock_irq(substream);
357 if (snd_pcm_running(substream))
358 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
359 snd_pcm_stream_unlock_irq(substream);
360 }
361 }
362
363 if (!handled_mask)
364 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
365 stat);
366
367 if (stat & XRERR)
368 handled_mask |= XRERR;
369
370 /* Ack the handled event only */
371 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
372
373 return IRQ_RETVAL(handled_mask);
374}
375
Peter Ujfalusi5a1b8a82014-12-30 16:10:32 +0200376static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
377{
378 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
379 irqreturn_t ret = IRQ_NONE;
380
381 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
382 ret = davinci_mcasp_tx_irq_handler(irq, data);
383
384 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
385 ret |= davinci_mcasp_rx_irq_handler(irq, data);
386
387 return ret;
388}
389
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400390static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
391 unsigned int fmt)
392{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200393 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200394 int ret = 0;
Peter Ujfalusi6dfa9a42014-04-04 14:31:42 +0300395 u32 data_delay;
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300396 bool fs_pol_rising;
Peter Ujfalusiffd950f2014-04-04 14:31:45 +0300397 bool inv_fs = false;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400398
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200399 pm_runtime_get_sync(mcasp->dev);
Daniel Mack5296cf22012-10-04 15:08:42 +0200400 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
Peter Ujfalusi188edc52014-04-04 14:31:43 +0300401 case SND_SOC_DAIFMT_DSP_A:
402 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
403 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
Peter Ujfalusi188edc52014-04-04 14:31:43 +0300404 /* 1st data bit occur one ACLK cycle after the frame sync */
405 data_delay = 1;
406 break;
Daniel Mack5296cf22012-10-04 15:08:42 +0200407 case SND_SOC_DAIFMT_DSP_B:
408 case SND_SOC_DAIFMT_AC97:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200409 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
410 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
Peter Ujfalusi6dfa9a42014-04-04 14:31:42 +0300411 /* No delay after FS */
412 data_delay = 0;
Daniel Mack5296cf22012-10-04 15:08:42 +0200413 break;
Peter Ujfalusiffd950f2014-04-04 14:31:45 +0300414 case SND_SOC_DAIFMT_I2S:
Daniel Mack5296cf22012-10-04 15:08:42 +0200415 /* configure a full-word SYNC pulse (LRCLK) */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200416 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
417 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
Peter Ujfalusi6dfa9a42014-04-04 14:31:42 +0300418 /* 1st data bit occur one ACLK cycle after the frame sync */
419 data_delay = 1;
Peter Ujfalusiffd950f2014-04-04 14:31:45 +0300420 /* FS need to be inverted */
421 inv_fs = true;
Daniel Mack5296cf22012-10-04 15:08:42 +0200422 break;
Peter Ujfalusi423761e2014-04-04 14:31:46 +0300423 case SND_SOC_DAIFMT_LEFT_J:
424 /* configure a full-word SYNC pulse (LRCLK) */
425 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
426 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
427 /* No delay after FS */
428 data_delay = 0;
429 break;
Peter Ujfalusiffd950f2014-04-04 14:31:45 +0300430 default:
431 ret = -EINVAL;
432 goto out;
Daniel Mack5296cf22012-10-04 15:08:42 +0200433 }
434
Peter Ujfalusi6dfa9a42014-04-04 14:31:42 +0300435 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
436 FSXDLY(3));
437 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
438 FSRDLY(3));
439
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400440 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
441 case SND_SOC_DAIFMT_CBS_CFS:
442 /* codec is clock and frame slave */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200443 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
444 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400445
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200446 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
447 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400448
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200449 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
450 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200451 mcasp->bclk_master = 1;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400452 break;
Peter Ujfalusi226e2f12015-02-12 16:41:26 +0200453 case SND_SOC_DAIFMT_CBS_CFM:
454 /* codec is clock slave and frame master */
455 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
456 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
457
458 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
459 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
460
461 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
462 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
463 mcasp->bclk_master = 1;
464 break;
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400465 case SND_SOC_DAIFMT_CBM_CFS:
466 /* codec is clock master and frame slave */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200467 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
468 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400469
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200470 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
471 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400472
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200473 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
474 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200475 mcasp->bclk_master = 0;
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400476 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400477 case SND_SOC_DAIFMT_CBM_CFM:
478 /* codec is clock and frame master */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200479 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
480 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400481
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200482 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
483 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400484
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200485 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
486 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200487 mcasp->bclk_master = 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400488 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400489 default:
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200490 ret = -EINVAL;
491 goto out;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400492 }
493
494 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
495 case SND_SOC_DAIFMT_IB_NF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200496 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
Peter Ujfalusi74ddd8c2014-04-04 14:31:41 +0300497 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300498 fs_pol_rising = true;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400499 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400500 case SND_SOC_DAIFMT_NB_IF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200501 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
Peter Ujfalusi74ddd8c2014-04-04 14:31:41 +0300502 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300503 fs_pol_rising = false;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400504 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400505 case SND_SOC_DAIFMT_IB_IF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200506 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
Peter Ujfalusi74ddd8c2014-04-04 14:31:41 +0300507 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300508 fs_pol_rising = false;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400509 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400510 case SND_SOC_DAIFMT_NB_NF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200511 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200512 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300513 fs_pol_rising = true;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400514 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400515 default:
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200516 ret = -EINVAL;
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300517 goto out;
518 }
519
Peter Ujfalusiffd950f2014-04-04 14:31:45 +0300520 if (inv_fs)
521 fs_pol_rising = !fs_pol_rising;
522
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300523 if (fs_pol_rising) {
524 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
525 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
526 } else {
527 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
528 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400529 }
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200530out:
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +0200531 pm_runtime_put(mcasp->dev);
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200532 return ret;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400533}
534
Jyri Sarha88135432014-08-06 16:47:16 +0300535static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
536 int div, bool explicit)
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200537{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200538 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200539
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +0200540 pm_runtime_get_sync(mcasp->dev);
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200541 switch (div_id) {
542 case 0: /* MCLK divider */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200543 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200544 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200545 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200546 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
547 break;
548
549 case 1: /* BCLK divider */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200550 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200551 ACLKXDIV(div - 1), ACLKXDIV_MASK);
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200552 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200553 ACLKRDIV(div - 1), ACLKRDIV_MASK);
Jyri Sarha88135432014-08-06 16:47:16 +0300554 if (explicit)
555 mcasp->bclk_div = div;
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200556 break;
557
Daniel Mack1b3bc062012-12-05 18:20:38 +0100558 case 2: /* BCLK/LRCLK ratio */
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200559 mcasp->bclk_lrclk_ratio = div;
Daniel Mack1b3bc062012-12-05 18:20:38 +0100560 break;
561
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200562 default:
563 return -EINVAL;
564 }
565
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +0200566 pm_runtime_put(mcasp->dev);
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200567 return 0;
568}
569
Jyri Sarha88135432014-08-06 16:47:16 +0300570static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
571 int div)
572{
573 return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1);
574}
575
Daniel Mack5b66aa22012-10-04 15:08:41 +0200576static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
577 unsigned int freq, int dir)
578{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200579 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200580
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +0200581 pm_runtime_get_sync(mcasp->dev);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200582 if (dir == SND_SOC_CLOCK_OUT) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200583 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
584 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
585 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200586 } else {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200587 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
588 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
589 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200590 }
591
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200592 mcasp->sysclk_freq = freq;
593
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +0200594 pm_runtime_put(mcasp->dev);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200595 return 0;
596}
597
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200598static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
Daniel Mackba764b32012-12-05 18:20:37 +0100599 int word_length)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400600{
Daniel Mackba764b32012-12-05 18:20:37 +0100601 u32 fmt;
Daniel Mack79671892013-05-16 15:25:01 +0200602 u32 tx_rotate = (word_length / 4) & 0x7;
Daniel Mackba764b32012-12-05 18:20:37 +0100603 u32 mask = (1ULL << word_length) - 1;
Peter Ujfalusife0a29e2014-09-04 10:52:53 +0300604 /*
605 * For captured data we should not rotate, inversion and masking is
606 * enoguh to get the data to the right position:
607 * Format data from bus after reverse (XRBUF)
608 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
609 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
610 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
611 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
612 */
613 u32 rx_rotate = 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400614
Daniel Mack1b3bc062012-12-05 18:20:38 +0100615 /*
616 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
617 * callback, take it into account here. That allows us to for example
618 * send 32 bits per channel to the codec, while only 16 of them carry
619 * audio payload.
Michal Bachratyd486fea2013-04-19 15:28:44 +0200620 * The clock ratio is given for a full period of data (for I2S format
621 * both left and right channels), so it has to be divided by number of
622 * tdm-slots (for I2S - divided by 2).
Daniel Mack1b3bc062012-12-05 18:20:38 +0100623 */
Peter Ujfalusid742b922014-11-10 12:32:19 +0200624 if (mcasp->bclk_lrclk_ratio) {
625 u32 slot_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
626
627 /*
628 * When we have more bclk then it is needed for the data, we
629 * need to use the rotation to move the received samples to have
630 * correct alignment.
631 */
632 rx_rotate = (slot_length - word_length) / 4;
633 word_length = slot_length;
634 }
Daniel Mack1b3bc062012-12-05 18:20:38 +0100635
Daniel Mackba764b32012-12-05 18:20:37 +0100636 /* mapping of the XSSZ bit-field as described in the datasheet */
637 fmt = (word_length >> 1) - 1;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400638
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200639 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200640 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
641 RXSSZ(0x0F));
642 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
643 TXSSZ(0x0F));
644 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
645 TXROT(7));
646 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
647 RXROT(7));
648 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
Yegor Yefremovf5023af2013-04-04 16:13:20 +0200649 }
650
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200651 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
Chaithrika U S0c31cf32009-09-15 18:13:29 -0400652
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400653 return 0;
654}
655
Peter Ujfalusi662ffae2014-01-30 15:15:22 +0200656static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300657 int period_words, int channels)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400658{
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300659 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400660 int i;
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400661 u8 tx_ser = 0;
662 u8 rx_ser = 0;
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200663 u8 slots = mcasp->tdm_slots;
Michal Bachraty2952b272013-02-28 16:07:08 +0100664 u8 max_active_serializers = (channels + slots - 1) / slots;
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300665 int active_serializers, numevt, n;
Peter Ujfalusi487dce82013-11-14 11:35:31 +0200666 u32 reg;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400667 /* Default configuration */
Peter Ujfalusi40448e52014-04-04 15:56:30 +0300668 if (mcasp->version < MCASP_VERSION_3)
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200669 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400670
671 /* All PINS as McASP */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200672 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400673
674 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200675 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
676 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400677 } else {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200678 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
679 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400680 }
681
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200682 for (i = 0; i < mcasp->num_serializer; i++) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200683 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
684 mcasp->serial_dir[i]);
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200685 if (mcasp->serial_dir[i] == TX_MODE &&
Michal Bachraty2952b272013-02-28 16:07:08 +0100686 tx_ser < max_active_serializers) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200687 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400688 tx_ser++;
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200689 } else if (mcasp->serial_dir[i] == RX_MODE &&
Michal Bachraty2952b272013-02-28 16:07:08 +0100690 rx_ser < max_active_serializers) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200691 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400692 rx_ser++;
Michal Bachraty2952b272013-02-28 16:07:08 +0100693 } else {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200694 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
695 SRMOD_INACTIVE, SRMOD_MASK);
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400696 }
697 }
698
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300699 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
700 active_serializers = tx_ser;
701 numevt = mcasp->txnumevt;
702 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
703 } else {
704 active_serializers = rx_ser;
705 numevt = mcasp->rxnumevt;
706 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
707 }
Daniel Mackecf327c2013-03-08 14:19:38 +0100708
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300709 if (active_serializers < max_active_serializers) {
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200710 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300711 "enabled in mcasp (%d)\n", channels,
712 active_serializers * slots);
Daniel Mackecf327c2013-03-08 14:19:38 +0100713 return -EINVAL;
714 }
715
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300716 /* AFIFO is not in use */
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300717 if (!numevt) {
718 /* Configure the burst size for platform drivers */
Peter Ujfalusi33445642014-04-01 15:55:12 +0300719 if (active_serializers > 1) {
720 /*
721 * If more than one serializers are in use we have one
722 * DMA request to provide data for all serializers.
723 * For example if three serializers are enabled the DMA
724 * need to transfer three words per DMA request.
725 */
Peter Ujfalusi33445642014-04-01 15:55:12 +0300726 dma_data->maxburst = active_serializers;
727 } else {
Peter Ujfalusi33445642014-04-01 15:55:12 +0300728 dma_data->maxburst = 0;
729 }
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300730 return 0;
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300731 }
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400732
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300733 if (period_words % active_serializers) {
734 dev_err(mcasp->dev, "Invalid combination of period words and "
735 "active serializers: %d, %d\n", period_words,
736 active_serializers);
737 return -EINVAL;
738 }
739
740 /*
741 * Calculate the optimal AFIFO depth for platform side:
742 * The number of words for numevt need to be in steps of active
743 * serializers.
744 */
745 n = numevt % active_serializers;
746 if (n)
747 numevt += (active_serializers - n);
748 while (period_words % numevt && numevt > 0)
749 numevt -= active_serializers;
750 if (numevt <= 0)
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300751 numevt = active_serializers;
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400752
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300753 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
754 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
Michal Bachraty2952b272013-02-28 16:07:08 +0100755
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300756 /* Configure the burst size for platform drivers */
Peter Ujfalusi33445642014-04-01 15:55:12 +0300757 if (numevt == 1)
758 numevt = 0;
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300759 dma_data->maxburst = numevt;
760
Michal Bachraty2952b272013-02-28 16:07:08 +0100761 return 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400762}
763
Misael Lopez Cruz18a4f552014-11-10 12:32:17 +0200764static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
765 int channels)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400766{
767 int i, active_slots;
Misael Lopez Cruz18a4f552014-11-10 12:32:17 +0200768 int total_slots;
769 int active_serializers;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400770 u32 mask = 0;
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +0200771 u32 busel = 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400772
Misael Lopez Cruz18a4f552014-11-10 12:32:17 +0200773 total_slots = mcasp->tdm_slots;
774
775 /*
776 * If more than one serializer is needed, then use them with
777 * their specified tdm_slots count. Otherwise, one serializer
778 * can cope with the transaction using as many slots as channels
779 * in the stream, requires channels symmetry
780 */
781 active_serializers = (channels + total_slots - 1) / total_slots;
782 if (active_serializers == 1)
783 active_slots = channels;
784 else
785 active_slots = total_slots;
786
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400787 for (i = 0; i < active_slots; i++)
788 mask |= (1 << i);
789
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200790 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400791
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +0200792 if (!mcasp->dat_port)
793 busel = TXSEL;
794
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200795 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
796 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
797 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
Misael Lopez Cruz18a4f552014-11-10 12:32:17 +0200798 FSXMOD(total_slots), FSXMOD(0x1FF));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400799
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200800 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
801 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
802 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
Misael Lopez Cruz18a4f552014-11-10 12:32:17 +0200803 FSRMOD(total_slots), FSRMOD(0x1FF));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400804
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200805 return 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400806}
807
808/* S/PDIF */
Daniel Mack64792852014-03-27 11:27:40 +0100809static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
810 unsigned int rate)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400811{
Daniel Mack64792852014-03-27 11:27:40 +0100812 u32 cs_value = 0;
813 u8 *cs_bytes = (u8*) &cs_value;
814
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400815 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
816 and LSB first */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200817 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400818
819 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200820 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400821
822 /* Set the TX tdm : for all the slots */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200823 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400824
825 /* Set the TX clock controls : div = 1 and internal */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200826 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400827
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200828 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400829
830 /* Only 44100 and 48000 are valid, both have the same setting */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200831 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400832
833 /* Enable the DIT */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200834 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200835
Daniel Mack64792852014-03-27 11:27:40 +0100836 /* Set S/PDIF channel status bits */
837 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
838 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
839
840 switch (rate) {
841 case 22050:
842 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
843 break;
844 case 24000:
845 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
846 break;
847 case 32000:
848 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
849 break;
850 case 44100:
851 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
852 break;
853 case 48000:
854 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
855 break;
856 case 88200:
857 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
858 break;
859 case 96000:
860 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
861 break;
862 case 176400:
863 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
864 break;
865 case 192000:
866 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
867 break;
868 default:
869 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
870 return -EINVAL;
871 }
872
873 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
874 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
875
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200876 return 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400877}
878
Jyri Sarhaa75a0532015-03-20 13:31:08 +0200879static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
880 unsigned int bclk_freq,
881 int *error_ppm)
882{
883 int div = mcasp->sysclk_freq / bclk_freq;
884 int rem = mcasp->sysclk_freq % bclk_freq;
885
886 if (rem != 0) {
887 if (div == 0 ||
888 ((mcasp->sysclk_freq / div) - bclk_freq) >
889 (bclk_freq - (mcasp->sysclk_freq / (div+1)))) {
890 div++;
891 rem = rem - bclk_freq;
892 }
893 }
894 if (error_ppm)
895 *error_ppm =
896 (div*1000000 + (int)div64_long(1000000LL*rem,
897 (int)bclk_freq))
898 /div - 1000000;
899
900 return div;
901}
902
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400903static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
904 struct snd_pcm_hw_params *params,
905 struct snd_soc_dai *cpu_dai)
906{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200907 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400908 int word_length;
Peter Ujfalusia7e46bd2014-02-03 14:51:50 +0200909 int channels = params_channels(params);
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300910 int period_size = params_period_size(params);
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200911 int ret;
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200912
Daniel Mack82675252014-07-16 14:04:41 +0200913 /*
914 * If mcasp is BCLK master, and a BCLK divider was not provided by
915 * the machine driver, we need to calculate the ratio.
916 */
917 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
Jyri Sarhaa75a0532015-03-20 13:31:08 +0200918 int channels = params_channels(params);
919 int rate = params_rate(params);
920 int sbits = params_width(params);
921 int ppm, div;
922
923 if (channels > mcasp->tdm_slots)
924 channels = mcasp->tdm_slots;
925
926 div = davinci_mcasp_calc_clk_div(mcasp, rate*sbits*channels,
927 &ppm);
928 if (ppm)
929 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
930 ppm);
931
Jyri Sarha88135432014-08-06 16:47:16 +0300932 __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0);
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200933 }
934
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300935 ret = mcasp_common_hw_param(mcasp, substream->stream,
936 period_size * channels, channels);
Peter Ujfalusi0f7d9a62014-01-30 15:15:24 +0200937 if (ret)
938 return ret;
939
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200940 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
Daniel Mack64792852014-03-27 11:27:40 +0100941 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400942 else
Misael Lopez Cruz18a4f552014-11-10 12:32:17 +0200943 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
944 channels);
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200945
946 if (ret)
947 return ret;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400948
949 switch (params_format(params)) {
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400950 case SNDRV_PCM_FORMAT_U8:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400951 case SNDRV_PCM_FORMAT_S8:
Daniel Mackba764b32012-12-05 18:20:37 +0100952 word_length = 8;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400953 break;
954
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400955 case SNDRV_PCM_FORMAT_U16_LE:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400956 case SNDRV_PCM_FORMAT_S16_LE:
Daniel Mackba764b32012-12-05 18:20:37 +0100957 word_length = 16;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400958 break;
959
Daniel Mack21eb24d2012-10-09 09:35:16 +0200960 case SNDRV_PCM_FORMAT_U24_3LE:
961 case SNDRV_PCM_FORMAT_S24_3LE:
Daniel Mackba764b32012-12-05 18:20:37 +0100962 word_length = 24;
Daniel Mack21eb24d2012-10-09 09:35:16 +0200963 break;
964
Daniel Mack6b7fa012012-10-09 11:56:40 +0200965 case SNDRV_PCM_FORMAT_U24_LE:
966 case SNDRV_PCM_FORMAT_S24_LE:
Peter Ujfalusi182bef82014-06-26 08:09:24 +0300967 word_length = 24;
968 break;
969
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400970 case SNDRV_PCM_FORMAT_U32_LE:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400971 case SNDRV_PCM_FORMAT_S32_LE:
Daniel Mackba764b32012-12-05 18:20:37 +0100972 word_length = 32;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400973 break;
974
975 default:
976 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
977 return -EINVAL;
978 }
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400979
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200980 davinci_config_channel_size(mcasp, word_length);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400981
Peter Ujfalusi11277832014-11-10 12:32:16 +0200982 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
983 mcasp->channels = channels;
984
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400985 return 0;
986}
987
988static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
989 int cmd, struct snd_soc_dai *cpu_dai)
990{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200991 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400992 int ret = 0;
993
994 switch (cmd) {
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400995 case SNDRV_PCM_TRIGGER_RESUME:
Chaithrika U Se473b842010-01-20 17:06:33 +0530996 case SNDRV_PCM_TRIGGER_START:
997 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200998 davinci_mcasp_start(mcasp, substream->stream);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400999 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001000 case SNDRV_PCM_TRIGGER_SUSPEND:
Chaithrika U Sa47979b2009-12-03 18:56:56 +05301001 case SNDRV_PCM_TRIGGER_STOP:
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001002 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001003 davinci_mcasp_stop(mcasp, substream->stream);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001004 break;
1005
1006 default:
1007 ret = -EINVAL;
1008 }
1009
1010 return ret;
1011}
1012
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001013static const unsigned int davinci_mcasp_dai_rates[] = {
1014 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1015 88200, 96000, 176400, 192000,
1016};
1017
1018#define DAVINCI_MAX_RATE_ERROR_PPM 1000
1019
1020static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1021 struct snd_pcm_hw_rule *rule)
1022{
1023 struct davinci_mcasp_ruledata *rd = rule->private;
1024 struct snd_interval *ri =
1025 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1026 int sbits = params_width(params);
1027 int channels = params_channels(params);
1028 unsigned int list[ARRAY_SIZE(davinci_mcasp_dai_rates)];
1029 int i, count = 0;
1030
1031 if (channels > rd->mcasp->tdm_slots)
1032 channels = rd->mcasp->tdm_slots;
1033
1034 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1035 if (ri->min <= davinci_mcasp_dai_rates[i] &&
1036 ri->max >= davinci_mcasp_dai_rates[i]) {
1037 uint bclk_freq = sbits*channels*
1038 davinci_mcasp_dai_rates[i];
1039 int ppm;
1040
1041 davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
1042 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM)
1043 list[count++] = davinci_mcasp_dai_rates[i];
1044 }
1045 }
1046 dev_dbg(rd->mcasp->dev,
1047 "%d frequencies (%d-%d) for %d sbits and %d channels\n",
1048 count, ri->min, ri->max, sbits, channels);
1049
1050 return snd_interval_list(hw_param_interval(params, rule->var),
1051 count, list, 0);
1052}
1053
1054static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1055 struct snd_pcm_hw_rule *rule)
1056{
1057 struct davinci_mcasp_ruledata *rd = rule->private;
1058 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1059 struct snd_mask nfmt;
1060 int rate = params_rate(params);
1061 int channels = params_channels(params);
1062 int i, count = 0;
1063
1064 snd_mask_none(&nfmt);
1065
1066 if (channels > rd->mcasp->tdm_slots)
1067 channels = rd->mcasp->tdm_slots;
1068
1069 for (i = 0; i < SNDRV_PCM_FORMAT_LAST; i++) {
1070 if (snd_mask_test(fmt, i)) {
1071 uint bclk_freq = snd_pcm_format_width(i)*channels*rate;
1072 int ppm;
1073
1074 davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
1075 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1076 snd_mask_set(&nfmt, i);
1077 count++;
1078 }
1079 }
1080 }
1081 dev_dbg(rd->mcasp->dev,
1082 "%d possible sample format for %d Hz and %d channels\n",
1083 count, rate, channels);
1084
1085 return snd_mask_refine(fmt, &nfmt);
1086}
1087
1088static int davinci_mcasp_hw_rule_channels(struct snd_pcm_hw_params *params,
1089 struct snd_pcm_hw_rule *rule)
1090{
1091 struct davinci_mcasp_ruledata *rd = rule->private;
1092 struct snd_interval *ci =
1093 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
1094 int sbits = params_width(params);
1095 int rate = params_rate(params);
1096 int max_chan_per_wire = rd->mcasp->tdm_slots < ci->max ?
1097 rd->mcasp->tdm_slots : ci->max;
1098 unsigned int list[ci->max - ci->min + 1];
1099 int c1, c, count = 0;
1100
1101 for (c1 = ci->min; c1 <= max_chan_per_wire; c1++) {
1102 uint bclk_freq = c1*sbits*rate;
1103 int ppm;
1104
1105 davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
1106 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1107 /* If we can use all tdm_slots, we can put any
1108 amount of channels to remaining wires as
1109 long as they fit in. */
1110 if (c1 == rd->mcasp->tdm_slots) {
1111 for (c = c1; c <= rd->serializers*c1 &&
1112 c <= ci->max; c++)
1113 list[count++] = c;
1114 } else {
1115 list[count++] = c1;
1116 }
1117 }
1118 }
1119 dev_dbg(rd->mcasp->dev,
1120 "%d possible channel counts (%d-%d) for %d Hz and %d sbits\n",
1121 count, ci->min, ci->max, rate, sbits);
1122
1123 return snd_interval_list(hw_param_interval(params, rule->var),
1124 count, list, 0);
1125}
1126
Peter Ujfalusi11277832014-11-10 12:32:16 +02001127static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1128 struct snd_soc_dai *cpu_dai)
1129{
1130 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1131 u32 max_channels = 0;
1132 int i, dir;
1133
Misael Lopez Cruza7a33242014-11-12 16:38:05 +02001134 mcasp->substreams[substream->stream] = substream;
1135
Peter Ujfalusi11277832014-11-10 12:32:16 +02001136 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1137 return 0;
1138
1139 /*
1140 * Limit the maximum allowed channels for the first stream:
1141 * number of serializers for the direction * tdm slots per serializer
1142 */
1143 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1144 dir = TX_MODE;
1145 else
1146 dir = RX_MODE;
1147
1148 for (i = 0; i < mcasp->num_serializer; i++) {
1149 if (mcasp->serial_dir[i] == dir)
1150 max_channels++;
1151 }
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001152 mcasp->ruledata[dir].serializers = max_channels;
Peter Ujfalusi11277832014-11-10 12:32:16 +02001153 max_channels *= mcasp->tdm_slots;
1154 /*
1155 * If the already active stream has less channels than the calculated
1156 * limnit based on the seirializers * tdm_slots, we need to use that as
1157 * a constraint for the second stream.
1158 * Otherwise (first stream or less allowed channels) we use the
1159 * calculated constraint.
1160 */
1161 if (mcasp->channels && mcasp->channels < max_channels)
1162 max_channels = mcasp->channels;
1163
1164 snd_pcm_hw_constraint_minmax(substream->runtime,
1165 SNDRV_PCM_HW_PARAM_CHANNELS,
1166 2, max_channels);
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001167
1168 /*
1169 * If we rely on implicit BCLK divider setting we should
1170 * set constraints based on what we can provide.
1171 */
1172 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1173 int ret;
1174
1175 mcasp->ruledata[dir].mcasp = mcasp;
1176
1177 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1178 SNDRV_PCM_HW_PARAM_RATE,
1179 davinci_mcasp_hw_rule_rate,
1180 &mcasp->ruledata[dir],
1181 SNDRV_PCM_HW_PARAM_FORMAT,
1182 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
1183 if (ret)
1184 return ret;
1185 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1186 SNDRV_PCM_HW_PARAM_FORMAT,
1187 davinci_mcasp_hw_rule_format,
1188 &mcasp->ruledata[dir],
1189 SNDRV_PCM_HW_PARAM_RATE,
1190 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
1191 if (ret)
1192 return ret;
1193 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1194 SNDRV_PCM_HW_PARAM_CHANNELS,
1195 davinci_mcasp_hw_rule_channels,
1196 &mcasp->ruledata[dir],
1197 SNDRV_PCM_HW_PARAM_RATE,
1198 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1199 if (ret)
1200 return ret;
1201 }
1202
Peter Ujfalusi11277832014-11-10 12:32:16 +02001203 return 0;
1204}
1205
1206static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1207 struct snd_soc_dai *cpu_dai)
1208{
1209 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1210
Misael Lopez Cruza7a33242014-11-12 16:38:05 +02001211 mcasp->substreams[substream->stream] = NULL;
1212
Peter Ujfalusi11277832014-11-10 12:32:16 +02001213 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1214 return;
1215
1216 if (!cpu_dai->active)
1217 mcasp->channels = 0;
1218}
1219
Lars-Peter Clausen85e76522011-11-23 11:40:40 +01001220static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
Peter Ujfalusi11277832014-11-10 12:32:16 +02001221 .startup = davinci_mcasp_startup,
1222 .shutdown = davinci_mcasp_shutdown,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001223 .trigger = davinci_mcasp_trigger,
1224 .hw_params = davinci_mcasp_hw_params,
1225 .set_fmt = davinci_mcasp_set_dai_fmt,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +02001226 .set_clkdiv = davinci_mcasp_set_clkdiv,
Daniel Mack5b66aa22012-10-04 15:08:41 +02001227 .set_sysclk = davinci_mcasp_set_sysclk,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001228};
1229
Peter Ujfalusid5902f62014-04-01 15:55:07 +03001230static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1231{
1232 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1233
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001234 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1235 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
Peter Ujfalusid5902f62014-04-01 15:55:07 +03001236
1237 return 0;
1238}
1239
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001240#ifdef CONFIG_PM_SLEEP
1241static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1242{
1243 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
Peter Ujfalusi790bb942014-02-03 14:51:52 +02001244 struct davinci_mcasp_context *context = &mcasp->context;
Peter Ujfalusif114ce62014-10-01 16:02:12 +03001245 u32 reg;
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +03001246 int i;
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001247
Peter Ujfalusi66e61882015-03-06 09:07:32 +02001248 context->pm_state = pm_runtime_enabled(mcasp->dev);
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +02001249 if (!context->pm_state)
1250 pm_runtime_get_sync(mcasp->dev);
1251
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +03001252 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1253 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001254
Peter Ujfalusif114ce62014-10-01 16:02:12 +03001255 if (mcasp->txnumevt) {
1256 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1257 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1258 }
1259 if (mcasp->rxnumevt) {
1260 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1261 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1262 }
1263
1264 for (i = 0; i < mcasp->num_serializer; i++)
1265 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1266 DAVINCI_MCASP_XRSRCTL_REG(i));
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001267
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +02001268 pm_runtime_put_sync(mcasp->dev);
1269
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001270 return 0;
1271}
1272
1273static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1274{
1275 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
Peter Ujfalusi790bb942014-02-03 14:51:52 +02001276 struct davinci_mcasp_context *context = &mcasp->context;
Peter Ujfalusif114ce62014-10-01 16:02:12 +03001277 u32 reg;
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +03001278 int i;
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001279
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +02001280 pm_runtime_get_sync(mcasp->dev);
1281
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +03001282 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1283 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001284
Peter Ujfalusif114ce62014-10-01 16:02:12 +03001285 if (mcasp->txnumevt) {
1286 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1287 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1288 }
1289 if (mcasp->rxnumevt) {
1290 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1291 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1292 }
1293
1294 for (i = 0; i < mcasp->num_serializer; i++)
1295 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1296 context->xrsr_regs[i]);
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001297
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +02001298 if (!context->pm_state)
1299 pm_runtime_put_sync(mcasp->dev);
1300
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001301 return 0;
1302}
1303#else
1304#define davinci_mcasp_suspend NULL
1305#define davinci_mcasp_resume NULL
1306#endif
1307
Peter Ujfalusied29cd52013-11-14 11:35:22 +02001308#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1309
Ben Gardiner0a9d1382011-08-26 12:02:44 -04001310#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1311 SNDRV_PCM_FMTBIT_U8 | \
1312 SNDRV_PCM_FMTBIT_S16_LE | \
1313 SNDRV_PCM_FMTBIT_U16_LE | \
Daniel Mack21eb24d2012-10-09 09:35:16 +02001314 SNDRV_PCM_FMTBIT_S24_LE | \
1315 SNDRV_PCM_FMTBIT_U24_LE | \
1316 SNDRV_PCM_FMTBIT_S24_3LE | \
1317 SNDRV_PCM_FMTBIT_U24_3LE | \
Ben Gardiner0a9d1382011-08-26 12:02:44 -04001318 SNDRV_PCM_FMTBIT_S32_LE | \
1319 SNDRV_PCM_FMTBIT_U32_LE)
1320
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +00001321static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001322 {
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +00001323 .name = "davinci-mcasp.0",
Peter Ujfalusid5902f62014-04-01 15:55:07 +03001324 .probe = davinci_mcasp_dai_probe,
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001325 .suspend = davinci_mcasp_suspend,
1326 .resume = davinci_mcasp_resume,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001327 .playback = {
1328 .channels_min = 2,
Michal Bachraty2952b272013-02-28 16:07:08 +01001329 .channels_max = 32 * 16,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001330 .rates = DAVINCI_MCASP_RATES,
Ben Gardiner0a9d1382011-08-26 12:02:44 -04001331 .formats = DAVINCI_MCASP_PCM_FMTS,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001332 },
1333 .capture = {
1334 .channels_min = 2,
Michal Bachraty2952b272013-02-28 16:07:08 +01001335 .channels_max = 32 * 16,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001336 .rates = DAVINCI_MCASP_RATES,
Ben Gardiner0a9d1382011-08-26 12:02:44 -04001337 .formats = DAVINCI_MCASP_PCM_FMTS,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001338 },
1339 .ops = &davinci_mcasp_dai_ops,
1340
Peter Ujfalusid75249f2014-11-10 12:32:18 +02001341 .symmetric_samplebits = 1,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001342 },
1343 {
Peter Ujfalusi58e48d92013-11-14 11:35:24 +02001344 .name = "davinci-mcasp.1",
Peter Ujfalusid5902f62014-04-01 15:55:07 +03001345 .probe = davinci_mcasp_dai_probe,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001346 .playback = {
1347 .channels_min = 1,
1348 .channels_max = 384,
1349 .rates = DAVINCI_MCASP_RATES,
Ben Gardiner0a9d1382011-08-26 12:02:44 -04001350 .formats = DAVINCI_MCASP_PCM_FMTS,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001351 },
1352 .ops = &davinci_mcasp_dai_ops,
1353 },
1354
1355};
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001356
Kuninori Morimotoeeef0ed2013-03-21 03:31:19 -07001357static const struct snd_soc_component_driver davinci_mcasp_component = {
1358 .name = "davinci-mcasp",
1359};
1360
Jyri Sarha256ba182013-10-18 18:37:42 +03001361/* Some HW specific values and defaults. The rest is filled in from DT. */
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001362static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
Jyri Sarha256ba182013-10-18 18:37:42 +03001363 .tx_dma_offset = 0x400,
1364 .rx_dma_offset = 0x400,
Jyri Sarha256ba182013-10-18 18:37:42 +03001365 .version = MCASP_VERSION_1,
1366};
1367
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001368static struct davinci_mcasp_pdata da830_mcasp_pdata = {
Jyri Sarha256ba182013-10-18 18:37:42 +03001369 .tx_dma_offset = 0x2000,
1370 .rx_dma_offset = 0x2000,
Jyri Sarha256ba182013-10-18 18:37:42 +03001371 .version = MCASP_VERSION_2,
1372};
1373
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001374static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
Jyri Sarha256ba182013-10-18 18:37:42 +03001375 .tx_dma_offset = 0,
1376 .rx_dma_offset = 0,
Jyri Sarha256ba182013-10-18 18:37:42 +03001377 .version = MCASP_VERSION_3,
1378};
1379
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001380static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001381 .tx_dma_offset = 0x200,
1382 .rx_dma_offset = 0x284,
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001383 .version = MCASP_VERSION_4,
1384};
1385
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301386static const struct of_device_id mcasp_dt_ids[] = {
1387 {
1388 .compatible = "ti,dm646x-mcasp-audio",
Jyri Sarha256ba182013-10-18 18:37:42 +03001389 .data = &dm646x_mcasp_pdata,
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301390 },
1391 {
1392 .compatible = "ti,da830-mcasp-audio",
Jyri Sarha256ba182013-10-18 18:37:42 +03001393 .data = &da830_mcasp_pdata,
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301394 },
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +05301395 {
Jyri Sarha3af9e032013-10-18 18:37:44 +03001396 .compatible = "ti,am33xx-mcasp-audio",
Peter Ujfalusib14899d2013-11-14 11:35:37 +02001397 .data = &am33xx_mcasp_pdata,
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +05301398 },
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001399 {
1400 .compatible = "ti,dra7-mcasp-audio",
1401 .data = &dra7_mcasp_pdata,
1402 },
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301403 { /* sentinel */ }
1404};
1405MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1406
Peter Ujfalusiae726e92013-11-14 11:35:35 +02001407static int mcasp_reparent_fck(struct platform_device *pdev)
1408{
1409 struct device_node *node = pdev->dev.of_node;
1410 struct clk *gfclk, *parent_clk;
1411 const char *parent_name;
1412 int ret;
1413
1414 if (!node)
1415 return 0;
1416
1417 parent_name = of_get_property(node, "fck_parent", NULL);
1418 if (!parent_name)
1419 return 0;
1420
1421 gfclk = clk_get(&pdev->dev, "fck");
1422 if (IS_ERR(gfclk)) {
1423 dev_err(&pdev->dev, "failed to get fck\n");
1424 return PTR_ERR(gfclk);
1425 }
1426
1427 parent_clk = clk_get(NULL, parent_name);
1428 if (IS_ERR(parent_clk)) {
1429 dev_err(&pdev->dev, "failed to get parent clock\n");
1430 ret = PTR_ERR(parent_clk);
1431 goto err1;
1432 }
1433
1434 ret = clk_set_parent(gfclk, parent_clk);
1435 if (ret) {
1436 dev_err(&pdev->dev, "failed to reparent fck\n");
1437 goto err2;
1438 }
1439
1440err2:
1441 clk_put(parent_clk);
1442err1:
1443 clk_put(gfclk);
1444 return ret;
1445}
1446
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001447static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301448 struct platform_device *pdev)
1449{
1450 struct device_node *np = pdev->dev.of_node;
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001451 struct davinci_mcasp_pdata *pdata = NULL;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301452 const struct of_device_id *match =
Sachin Kamatea421eb2013-05-22 16:53:37 +05301453 of_match_device(mcasp_dt_ids, &pdev->dev);
Jyri Sarha4023fe62013-10-18 18:37:43 +03001454 struct of_phandle_args dma_spec;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301455
1456 const u32 *of_serial_dir32;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301457 u32 val;
1458 int i, ret = 0;
1459
1460 if (pdev->dev.platform_data) {
1461 pdata = pdev->dev.platform_data;
1462 return pdata;
1463 } else if (match) {
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001464 pdata = (struct davinci_mcasp_pdata*) match->data;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301465 } else {
1466 /* control shouldn't reach here. something is wrong */
1467 ret = -EINVAL;
1468 goto nodata;
1469 }
1470
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301471 ret = of_property_read_u32(np, "op-mode", &val);
1472 if (ret >= 0)
1473 pdata->op_mode = val;
1474
1475 ret = of_property_read_u32(np, "tdm-slots", &val);
Michal Bachraty2952b272013-02-28 16:07:08 +01001476 if (ret >= 0) {
1477 if (val < 2 || val > 32) {
1478 dev_err(&pdev->dev,
1479 "tdm-slots must be in rage [2-32]\n");
1480 ret = -EINVAL;
1481 goto nodata;
1482 }
1483
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301484 pdata->tdm_slots = val;
Michal Bachraty2952b272013-02-28 16:07:08 +01001485 }
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301486
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301487 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1488 val /= sizeof(u32);
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301489 if (of_serial_dir32) {
Peter Ujfalusi1427e662013-10-18 18:37:46 +03001490 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1491 (sizeof(*of_serial_dir) * val),
1492 GFP_KERNEL);
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301493 if (!of_serial_dir) {
1494 ret = -ENOMEM;
1495 goto nodata;
1496 }
1497
Peter Ujfalusi1427e662013-10-18 18:37:46 +03001498 for (i = 0; i < val; i++)
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301499 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1500
Peter Ujfalusi1427e662013-10-18 18:37:46 +03001501 pdata->num_serializer = val;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301502 pdata->serial_dir = of_serial_dir;
1503 }
1504
Jyri Sarha4023fe62013-10-18 18:37:43 +03001505 ret = of_property_match_string(np, "dma-names", "tx");
1506 if (ret < 0)
1507 goto nodata;
1508
1509 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1510 &dma_spec);
1511 if (ret < 0)
1512 goto nodata;
1513
1514 pdata->tx_dma_channel = dma_spec.args[0];
1515
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001516 /* RX is not valid in DIT mode */
1517 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1518 ret = of_property_match_string(np, "dma-names", "rx");
1519 if (ret < 0)
1520 goto nodata;
Jyri Sarha4023fe62013-10-18 18:37:43 +03001521
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001522 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1523 &dma_spec);
1524 if (ret < 0)
1525 goto nodata;
Jyri Sarha4023fe62013-10-18 18:37:43 +03001526
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001527 pdata->rx_dma_channel = dma_spec.args[0];
1528 }
Jyri Sarha4023fe62013-10-18 18:37:43 +03001529
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301530 ret = of_property_read_u32(np, "tx-num-evt", &val);
1531 if (ret >= 0)
1532 pdata->txnumevt = val;
1533
1534 ret = of_property_read_u32(np, "rx-num-evt", &val);
1535 if (ret >= 0)
1536 pdata->rxnumevt = val;
1537
1538 ret = of_property_read_u32(np, "sram-size-playback", &val);
1539 if (ret >= 0)
1540 pdata->sram_size_playback = val;
1541
1542 ret = of_property_read_u32(np, "sram-size-capture", &val);
1543 if (ret >= 0)
1544 pdata->sram_size_capture = val;
1545
1546 return pdata;
1547
1548nodata:
1549 if (ret < 0) {
1550 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1551 ret);
1552 pdata = NULL;
1553 }
1554 return pdata;
1555}
1556
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001557static int davinci_mcasp_probe(struct platform_device *pdev)
1558{
Peter Ujfalusi8de131f2014-03-14 16:42:46 +02001559 struct snd_dmaengine_dai_dma_data *dma_data;
Jyri Sarha256ba182013-10-18 18:37:42 +03001560 struct resource *mem, *ioarea, *res, *dat;
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001561 struct davinci_mcasp_pdata *pdata;
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001562 struct davinci_mcasp *mcasp;
Misael Lopez Cruza7a33242014-11-12 16:38:05 +02001563 char *irq_name;
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001564 int *dma;
Misael Lopez Cruza7a33242014-11-12 16:38:05 +02001565 int irq;
Julia Lawall96d31e22011-12-29 17:51:21 +01001566 int ret;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001567
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301568 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1569 dev_err(&pdev->dev, "No platform data supplied\n");
1570 return -EINVAL;
1571 }
1572
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001573 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
Julia Lawall96d31e22011-12-29 17:51:21 +01001574 GFP_KERNEL);
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001575 if (!mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001576 return -ENOMEM;
1577
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301578 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1579 if (!pdata) {
1580 dev_err(&pdev->dev, "no platform data\n");
1581 return -EINVAL;
1582 }
1583
Jyri Sarha256ba182013-10-18 18:37:42 +03001584 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001585 if (!mem) {
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001586 dev_warn(mcasp->dev,
Jyri Sarha256ba182013-10-18 18:37:42 +03001587 "\"mpu\" mem resource not found, using index 0\n");
1588 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1589 if (!mem) {
1590 dev_err(&pdev->dev, "no mem resource?\n");
1591 return -ENODEV;
1592 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001593 }
1594
Julia Lawall96d31e22011-12-29 17:51:21 +01001595 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
Vaibhav Bediad852f4462011-02-09 18:39:52 +05301596 resource_size(mem), pdev->name);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001597 if (!ioarea) {
1598 dev_err(&pdev->dev, "Audio region already claimed\n");
Julia Lawall96d31e22011-12-29 17:51:21 +01001599 return -EBUSY;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001600 }
1601
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301602 pm_runtime_enable(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001603
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001604 mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1605 if (!mcasp->base) {
Vaibhav Bedia4f82f022011-02-09 18:39:54 +05301606 dev_err(&pdev->dev, "ioremap failed\n");
1607 ret = -ENOMEM;
Peter Ujfalusib6bb3702014-04-22 14:03:13 +03001608 goto err;
Vaibhav Bedia4f82f022011-02-09 18:39:54 +05301609 }
1610
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001611 mcasp->op_mode = pdata->op_mode;
Peter Ujfalusi1a5923d2014-11-10 12:32:15 +02001612 /* sanity check for tdm slots parameter */
1613 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1614 if (pdata->tdm_slots < 2) {
1615 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1616 pdata->tdm_slots);
1617 mcasp->tdm_slots = 2;
1618 } else if (pdata->tdm_slots > 32) {
1619 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1620 pdata->tdm_slots);
1621 mcasp->tdm_slots = 32;
1622 } else {
1623 mcasp->tdm_slots = pdata->tdm_slots;
1624 }
1625 }
1626
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001627 mcasp->num_serializer = pdata->num_serializer;
Peter Ujfalusif114ce62014-10-01 16:02:12 +03001628#ifdef CONFIG_PM_SLEEP
1629 mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev,
1630 sizeof(u32) * mcasp->num_serializer,
1631 GFP_KERNEL);
1632#endif
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001633 mcasp->serial_dir = pdata->serial_dir;
1634 mcasp->version = pdata->version;
1635 mcasp->txnumevt = pdata->txnumevt;
1636 mcasp->rxnumevt = pdata->rxnumevt;
Peter Ujfalusi487dce82013-11-14 11:35:31 +02001637
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001638 mcasp->dev = &pdev->dev;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001639
Peter Ujfalusi5a1b8a82014-12-30 16:10:32 +02001640 irq = platform_get_irq_byname(pdev, "common");
1641 if (irq >= 0) {
1642 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common\n",
1643 dev_name(&pdev->dev));
1644 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1645 davinci_mcasp_common_irq_handler,
Peter Ujfalusi8f511ff2015-02-02 14:38:32 +02001646 IRQF_ONESHOT | IRQF_SHARED,
1647 irq_name, mcasp);
Peter Ujfalusi5a1b8a82014-12-30 16:10:32 +02001648 if (ret) {
1649 dev_err(&pdev->dev, "common IRQ request failed\n");
1650 goto err;
1651 }
1652
1653 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1654 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1655 }
1656
Misael Lopez Cruza7a33242014-11-12 16:38:05 +02001657 irq = platform_get_irq_byname(pdev, "rx");
1658 if (irq >= 0) {
1659 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx\n",
1660 dev_name(&pdev->dev));
1661 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1662 davinci_mcasp_rx_irq_handler,
1663 IRQF_ONESHOT, irq_name, mcasp);
1664 if (ret) {
1665 dev_err(&pdev->dev, "RX IRQ request failed\n");
1666 goto err;
1667 }
1668
1669 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1670 }
1671
1672 irq = platform_get_irq_byname(pdev, "tx");
1673 if (irq >= 0) {
1674 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx\n",
1675 dev_name(&pdev->dev));
1676 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1677 davinci_mcasp_tx_irq_handler,
1678 IRQF_ONESHOT, irq_name, mcasp);
1679 if (ret) {
1680 dev_err(&pdev->dev, "TX IRQ request failed\n");
1681 goto err;
1682 }
1683
1684 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1685 }
1686
Jyri Sarha256ba182013-10-18 18:37:42 +03001687 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001688 if (dat)
1689 mcasp->dat_port = true;
Jyri Sarha256ba182013-10-18 18:37:42 +03001690
Peter Ujfalusi8de131f2014-03-14 16:42:46 +02001691 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001692 if (dat)
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001693 dma_data->addr = dat->start;
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001694 else
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001695 dma_data->addr = mem->start + pdata->tx_dma_offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001696
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001697 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001698 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
Jyri Sarha4023fe62013-10-18 18:37:43 +03001699 if (res)
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001700 *dma = res->start;
Jyri Sarha4023fe62013-10-18 18:37:43 +03001701 else
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001702 *dma = pdata->tx_dma_channel;
Troy Kisky92e2a6f2009-09-11 14:29:03 -07001703
Peter Ujfalusi8de131f2014-03-14 16:42:46 +02001704 /* dmaengine filter data for DT and non-DT boot */
1705 if (pdev->dev.of_node)
1706 dma_data->filter_data = "tx";
1707 else
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001708 dma_data->filter_data = dma;
Peter Ujfalusi8de131f2014-03-14 16:42:46 +02001709
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001710 /* RX is not valid in DIT mode */
1711 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001712 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001713 if (dat)
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001714 dma_data->addr = dat->start;
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001715 else
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001716 dma_data->addr = mem->start + pdata->rx_dma_offset;
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001717
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001718 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001719 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1720 if (res)
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001721 *dma = res->start;
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001722 else
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001723 *dma = pdata->rx_dma_channel;
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001724
1725 /* dmaengine filter data for DT and non-DT boot */
1726 if (pdev->dev.of_node)
1727 dma_data->filter_data = "rx";
1728 else
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001729 dma_data->filter_data = dma;
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001730 }
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001731
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001732 if (mcasp->version < MCASP_VERSION_3) {
1733 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
Peter Ujfalusi64ebdec2014-03-07 15:03:55 +02001734 /* dma_params->dma_addr is pointing to the data port address */
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001735 mcasp->dat_port = true;
1736 } else {
1737 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1738 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001739
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001740 dev_set_drvdata(&pdev->dev, mcasp);
Peter Ujfalusiae726e92013-11-14 11:35:35 +02001741
1742 mcasp_reparent_fck(pdev);
1743
Peter Ujfalusib6bb3702014-04-22 14:03:13 +03001744 ret = devm_snd_soc_register_component(&pdev->dev,
1745 &davinci_mcasp_component,
1746 &davinci_mcasp_dai[pdata->op_mode], 1);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001747
1748 if (ret != 0)
Peter Ujfalusib6bb3702014-04-22 14:03:13 +03001749 goto err;
Hebbar, Gururajaf08095a2012-08-27 18:56:39 +05301750
Peter Ujfalusid5c6c592014-04-16 15:46:20 +03001751 switch (mcasp->version) {
Peter Ujfalusif3f9cfa2014-07-16 15:12:04 +03001752#if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
1753 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1754 IS_MODULE(CONFIG_SND_EDMA_SOC))
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001755 case MCASP_VERSION_1:
1756 case MCASP_VERSION_2:
Peter Ujfalusif3f9cfa2014-07-16 15:12:04 +03001757 case MCASP_VERSION_3:
1758 ret = edma_pcm_platform_register(&pdev->dev);
1759 break;
1760#endif
Jyri Sarha7f28f352014-06-13 12:49:59 +03001761#if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
1762 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1763 IS_MODULE(CONFIG_SND_OMAP_SOC))
Peter Ujfalusid5c6c592014-04-16 15:46:20 +03001764 case MCASP_VERSION_4:
1765 ret = omap_pcm_platform_register(&pdev->dev);
1766 break;
Jyri Sarha7f28f352014-06-13 12:49:59 +03001767#endif
Peter Ujfalusid5c6c592014-04-16 15:46:20 +03001768 default:
1769 dev_err(&pdev->dev, "Invalid McASP version: %d\n",
1770 mcasp->version);
1771 ret = -EINVAL;
1772 break;
1773 }
1774
1775 if (ret) {
1776 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
Peter Ujfalusib6bb3702014-04-22 14:03:13 +03001777 goto err;
Hebbar, Gururajaf08095a2012-08-27 18:56:39 +05301778 }
1779
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001780 return 0;
1781
Peter Ujfalusib6bb3702014-04-22 14:03:13 +03001782err:
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301783 pm_runtime_disable(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001784 return ret;
1785}
1786
1787static int davinci_mcasp_remove(struct platform_device *pdev)
1788{
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301789 pm_runtime_disable(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001790
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001791 return 0;
1792}
1793
1794static struct platform_driver davinci_mcasp_driver = {
1795 .probe = davinci_mcasp_probe,
1796 .remove = davinci_mcasp_remove,
1797 .driver = {
1798 .name = "davinci-mcasp",
Sachin Kamatea421eb2013-05-22 16:53:37 +05301799 .of_match_table = mcasp_dt_ids,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001800 },
1801};
1802
Axel Linf9b8a512011-11-25 10:09:27 +08001803module_platform_driver(davinci_mcasp_driver);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001804
1805MODULE_AUTHOR("Steve Chen");
1806MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1807MODULE_LICENSE("GPL");