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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04004 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020042#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050043#include <linux/device.h>
Tejun Heoedc93052007-10-25 14:59:16 +090044#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050046#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <linux/libata.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
49#define DRV_NAME "ahci"
Tejun Heo7d50b602007-09-23 13:19:54 +090050#define DRV_VERSION "3.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
David Milburn87943ac2008-10-13 14:38:36 -050052/* Enclosure Management Control */
53#define EM_CTRL_MSG_TYPE 0x000f0000
54
55/* Enclosure Management LED Message Type */
56#define EM_MSG_LED_HBA_PORT 0x0000000f
57#define EM_MSG_LED_PMP_SLOT 0x0000ff00
58#define EM_MSG_LED_VALUE 0xffff0000
59#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
60#define EM_MSG_LED_VALUE_OFF 0xfff80000
61#define EM_MSG_LED_VALUE_ON 0x00010000
62
Tejun Heoa22e6442008-03-10 10:25:25 +090063static int ahci_skip_host_reset;
64module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
65MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
66
Kristen Carlson Accardi31556592007-10-25 01:33:26 -040067static int ahci_enable_alpm(struct ata_port *ap,
68 enum link_pm policy);
69static void ahci_disable_alpm(struct ata_port *ap);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -070070static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
71static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
72 size_t size);
73static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
74 ssize_t size);
75#define MAX_SLOTS 8
Linus Torvalds1da177e2005-04-16 15:20:36 -070076
77enum {
78 AHCI_PCI_BAR = 5,
Tejun Heo648a88b2006-11-09 15:08:40 +090079 AHCI_MAX_PORTS = 32,
Linus Torvalds1da177e2005-04-16 15:20:36 -070080 AHCI_MAX_SG = 168, /* hardware max is 64K */
81 AHCI_DMA_BOUNDARY = 0xffffffff,
Tejun Heo12fad3f2006-05-15 21:03:55 +090082 AHCI_MAX_CMDS = 32,
Tejun Heodd410ff2006-05-15 21:03:50 +090083 AHCI_CMD_SZ = 32,
Tejun Heo12fad3f2006-05-15 21:03:55 +090084 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
Linus Torvalds1da177e2005-04-16 15:20:36 -070085 AHCI_RX_FIS_SZ = 256,
Jeff Garzika0ea7322005-06-04 01:13:15 -040086 AHCI_CMD_TBL_CDB = 0x40,
Tejun Heodd410ff2006-05-15 21:03:50 +090087 AHCI_CMD_TBL_HDR_SZ = 0x80,
88 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
89 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
90 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
Linus Torvalds1da177e2005-04-16 15:20:36 -070091 AHCI_RX_FIS_SZ,
92 AHCI_IRQ_ON_SG = (1 << 31),
93 AHCI_CMD_ATAPI = (1 << 5),
94 AHCI_CMD_WRITE = (1 << 6),
Tejun Heo4b10e552006-03-12 11:25:27 +090095 AHCI_CMD_PREFETCH = (1 << 7),
Tejun Heo22b49982006-01-23 21:38:44 +090096 AHCI_CMD_RESET = (1 << 8),
97 AHCI_CMD_CLR_BUSY = (1 << 10),
Linus Torvalds1da177e2005-04-16 15:20:36 -070098
99 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
Tejun Heo0291f952007-01-25 19:16:28 +0900100 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
Tejun Heo78cd52d2006-05-15 20:58:29 +0900101 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102
103 board_ahci = 0,
Tejun Heo7a234af2007-09-03 12:44:57 +0900104 board_ahci_vt8251 = 1,
105 board_ahci_ign_iferr = 2,
106 board_ahci_sb600 = 3,
107 board_ahci_mv = 4,
Shane Huange39fc8c2008-02-22 05:00:31 -0800108 board_ahci_sb700 = 5,
Tejun Heoe297d992008-06-10 00:13:04 +0900109 board_ahci_mcp65 = 6,
Tejun Heo9a3b1032008-06-18 20:56:58 -0400110 board_ahci_nopmp = 7,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111
112 /* global controller registers */
113 HOST_CAP = 0x00, /* host capabilities */
114 HOST_CTL = 0x04, /* global host control */
115 HOST_IRQ_STAT = 0x08, /* interrupt status */
116 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
117 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700118 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
119 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120
121 /* HOST_CTL bits */
122 HOST_RESET = (1 << 0), /* reset controller; self-clear */
123 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
124 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
125
126 /* HOST_CAP bits */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700127 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900128 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
Tejun Heo7d50b602007-09-23 13:19:54 +0900129 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
Tejun Heo22b49982006-01-23 21:38:44 +0900130 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400131 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900132 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900133 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
Tejun Heo979db802006-05-15 21:03:52 +0900134 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
Tejun Heodd410ff2006-05-15 21:03:50 +0900135 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136
137 /* registers for each SATA port */
138 PORT_LST_ADDR = 0x00, /* command list DMA addr */
139 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
140 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
141 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
142 PORT_IRQ_STAT = 0x10, /* interrupt status */
143 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
144 PORT_CMD = 0x18, /* port command */
145 PORT_TFDATA = 0x20, /* taskfile data */
146 PORT_SIG = 0x24, /* device TF signature */
147 PORT_CMD_ISSUE = 0x38, /* command issue */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
149 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
150 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
151 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900152 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153
154 /* PORT_IRQ_{STAT,MASK} bits */
155 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
156 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
157 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
158 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
159 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
160 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
161 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
162 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
163
164 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
165 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
166 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
167 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
168 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
169 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
170 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
171 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
172 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
173
Tejun Heo78cd52d2006-05-15 20:58:29 +0900174 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
175 PORT_IRQ_IF_ERR |
176 PORT_IRQ_CONNECT |
Tejun Heo42969712006-05-31 18:28:18 +0900177 PORT_IRQ_PHYRDY |
Tejun Heo7d50b602007-09-23 13:19:54 +0900178 PORT_IRQ_UNK_FIS |
179 PORT_IRQ_BAD_PMP,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900180 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
181 PORT_IRQ_TF_ERR |
182 PORT_IRQ_HBUS_DATA_ERR,
183 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
184 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
185 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186
187 /* PORT_CMD bits */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400188 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
189 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
Jeff Garzik02eaa662005-11-12 01:32:19 -0500190 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
Tejun Heo7d50b602007-09-23 13:19:54 +0900191 PORT_CMD_PMP = (1 << 17), /* PMP attached */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
193 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
194 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
Tejun Heo22b49982006-01-23 21:38:44 +0900195 PORT_CMD_CLO = (1 << 3), /* Command list override */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
197 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
198 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
199
Tejun Heo0be0aa92006-07-26 15:59:26 +0900200 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
202 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
203 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
Jeff Garzik4b0060f2005-06-04 00:50:22 -0400204
Tejun Heo417a1a62007-09-23 13:19:55 +0900205 /* hpriv->flags bits */
206 AHCI_HFLAG_NO_NCQ = (1 << 0),
207 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
208 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
209 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
210 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
211 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
Tejun Heo6949b912007-09-23 13:19:55 +0900212 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400213 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
Jeff Garzika8785392008-02-28 15:43:48 -0500214 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
Tejun Heoe297d992008-06-10 00:13:04 +0900215 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
Tejun Heo417a1a62007-09-23 13:19:55 +0900216
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200217 /* ap->flags bits */
Tejun Heo1188c0d2007-04-23 02:41:05 +0900218
219 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
220 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400221 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
222 ATA_FLAG_IPM,
Tejun Heoc4f77922007-12-06 15:09:43 +0900223
224 ICH_MAP = 0x90, /* ICH MAP register */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700225
226 /* em_ctl bits */
227 EM_CTL_RST = (1 << 9), /* Reset */
228 EM_CTL_TM = (1 << 8), /* Transmit Message */
229 EM_CTL_ALHD = (1 << 26), /* Activity LED */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230};
231
232struct ahci_cmd_hdr {
Al Viro4ca4e432007-12-30 09:32:22 +0000233 __le32 opts;
234 __le32 status;
235 __le32 tbl_addr;
236 __le32 tbl_addr_hi;
237 __le32 reserved[4];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238};
239
240struct ahci_sg {
Al Viro4ca4e432007-12-30 09:32:22 +0000241 __le32 addr;
242 __le32 addr_hi;
243 __le32 reserved;
244 __le32 flags_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245};
246
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700247struct ahci_em_priv {
248 enum sw_activity blink_policy;
249 struct timer_list timer;
250 unsigned long saved_activity;
251 unsigned long activity;
252 unsigned long led_state;
253};
254
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255struct ahci_host_priv {
Tejun Heo417a1a62007-09-23 13:19:55 +0900256 unsigned int flags; /* AHCI_HFLAG_* */
Tejun Heod447df12007-03-18 22:15:33 +0900257 u32 cap; /* cap to use */
258 u32 port_map; /* port map to use */
259 u32 saved_cap; /* saved initial cap */
260 u32 saved_port_map; /* saved initial port_map */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700261 u32 em_loc; /* enclosure management location */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262};
263
264struct ahci_port_priv {
Tejun Heo7d50b602007-09-23 13:19:54 +0900265 struct ata_link *active_link;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700266 struct ahci_cmd_hdr *cmd_slot;
267 dma_addr_t cmd_slot_dma;
268 void *cmd_tbl;
269 dma_addr_t cmd_tbl_dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270 void *rx_fis;
271 dma_addr_t rx_fis_dma;
Tejun Heo0291f952007-01-25 19:16:28 +0900272 /* for NCQ spurious interrupt analysis */
Tejun Heo0291f952007-01-25 19:16:28 +0900273 unsigned int ncq_saw_d2h:1;
274 unsigned int ncq_saw_dmas:1;
Tejun Heoafb2d552007-02-27 13:24:19 +0900275 unsigned int ncq_saw_sdb:1;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -0700276 u32 intr_mask; /* interrupts to enable */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700277 struct ahci_em_priv em_priv[MAX_SLOTS];/* enclosure management info
278 * per PM slot */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700279};
280
Tejun Heo82ef04f2008-07-31 17:02:40 +0900281static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
282static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400283static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900284static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
Tejun Heo4c9bf4e2008-04-07 22:47:20 +0900285static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700286static int ahci_port_start(struct ata_port *ap);
287static void ahci_port_stop(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288static void ahci_qc_prep(struct ata_queued_cmd *qc);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900289static void ahci_freeze(struct ata_port *ap);
290static void ahci_thaw(struct ata_port *ap);
Tejun Heo7d50b602007-09-23 13:19:54 +0900291static void ahci_pmp_attach(struct ata_port *ap);
292static void ahci_pmp_detach(struct ata_port *ap);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900293static int ahci_softreset(struct ata_link *link, unsigned int *class,
294 unsigned long deadline);
Shane Huangbd172432008-06-10 15:52:04 +0800295static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
296 unsigned long deadline);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900297static int ahci_hardreset(struct ata_link *link, unsigned int *class,
298 unsigned long deadline);
299static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
300 unsigned long deadline);
301static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
302 unsigned long deadline);
303static void ahci_postreset(struct ata_link *link, unsigned int *class);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900304static void ahci_error_handler(struct ata_port *ap);
305static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -0400306static int ahci_port_resume(struct ata_port *ap);
Jeff Garzika8785392008-02-28 15:43:48 -0500307static void ahci_dev_config(struct ata_device *dev);
Jeff Garzikdab632e2007-05-28 08:33:01 -0400308static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
309static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
310 u32 opts);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900311#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900312static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
Tejun Heoc1332872006-07-26 15:59:26 +0900313static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
314static int ahci_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900315#endif
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700316static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
317static ssize_t ahci_activity_store(struct ata_device *dev,
318 enum sw_activity val);
319static void ahci_init_sw_activity(struct ata_link *link);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320
Tony Jonesee959b02008-02-22 00:13:36 +0100321static struct device_attribute *ahci_shost_attrs[] = {
322 &dev_attr_link_power_management_policy,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700323 &dev_attr_em_message_type,
324 &dev_attr_em_message,
325 NULL
326};
327
328static struct device_attribute *ahci_sdev_attrs[] = {
329 &dev_attr_sw_activity,
Elias Oltmanns45fabbb2008-09-21 11:54:08 +0200330 &dev_attr_unload_heads,
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400331 NULL
332};
333
Jeff Garzik193515d2005-11-07 00:59:37 -0500334static struct scsi_host_template ahci_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900335 ATA_NCQ_SHT(DRV_NAME),
Tejun Heo12fad3f2006-05-15 21:03:55 +0900336 .can_queue = AHCI_MAX_CMDS - 1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337 .sg_tablesize = AHCI_MAX_SG,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338 .dma_boundary = AHCI_DMA_BOUNDARY,
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400339 .shost_attrs = ahci_shost_attrs,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700340 .sdev_attrs = ahci_sdev_attrs,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341};
342
Tejun Heo029cfd62008-03-25 12:22:49 +0900343static struct ata_port_operations ahci_ops = {
344 .inherits = &sata_pmp_port_ops,
345
Tejun Heo7d50b602007-09-23 13:19:54 +0900346 .qc_defer = sata_pmp_qc_defer_cmd_switch,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347 .qc_prep = ahci_qc_prep,
348 .qc_issue = ahci_qc_issue,
Tejun Heo4c9bf4e2008-04-07 22:47:20 +0900349 .qc_fill_rtf = ahci_qc_fill_rtf,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700350
Tejun Heo78cd52d2006-05-15 20:58:29 +0900351 .freeze = ahci_freeze,
352 .thaw = ahci_thaw,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900353 .softreset = ahci_softreset,
354 .hardreset = ahci_hardreset,
355 .postreset = ahci_postreset,
Tejun Heo071f44b2008-04-07 22:47:22 +0900356 .pmp_softreset = ahci_softreset,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900357 .error_handler = ahci_error_handler,
358 .post_internal_cmd = ahci_post_internal_cmd,
Tejun Heo029cfd62008-03-25 12:22:49 +0900359 .dev_config = ahci_dev_config,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900360
Tejun Heo029cfd62008-03-25 12:22:49 +0900361 .scr_read = ahci_scr_read,
362 .scr_write = ahci_scr_write,
Tejun Heo7d50b602007-09-23 13:19:54 +0900363 .pmp_attach = ahci_pmp_attach,
364 .pmp_detach = ahci_pmp_detach,
Tejun Heo7d50b602007-09-23 13:19:54 +0900365
Tejun Heo029cfd62008-03-25 12:22:49 +0900366 .enable_pm = ahci_enable_alpm,
367 .disable_pm = ahci_disable_alpm,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700368 .em_show = ahci_led_show,
369 .em_store = ahci_led_store,
370 .sw_activity_show = ahci_activity_show,
371 .sw_activity_store = ahci_activity_store,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900372#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900373 .port_suspend = ahci_port_suspend,
374 .port_resume = ahci_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900375#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376 .port_start = ahci_port_start,
377 .port_stop = ahci_port_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378};
379
Tejun Heo029cfd62008-03-25 12:22:49 +0900380static struct ata_port_operations ahci_vt8251_ops = {
381 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900382 .hardreset = ahci_vt8251_hardreset,
Tejun Heoad616ff2006-11-01 18:00:24 +0900383};
384
Tejun Heo029cfd62008-03-25 12:22:49 +0900385static struct ata_port_operations ahci_p5wdh_ops = {
386 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900387 .hardreset = ahci_p5wdh_hardreset,
Tejun Heoedc93052007-10-25 14:59:16 +0900388};
389
Shane Huangbd172432008-06-10 15:52:04 +0800390static struct ata_port_operations ahci_sb600_ops = {
391 .inherits = &ahci_ops,
392 .softreset = ahci_sb600_softreset,
393 .pmp_softreset = ahci_sb600_softreset,
394};
395
Tejun Heo417a1a62007-09-23 13:19:55 +0900396#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
397
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100398static const struct ata_port_info ahci_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399 /* board_ahci */
400 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900401 .flags = AHCI_FLAG_COMMON,
Brett Russ7da79312005-09-01 21:53:34 -0400402 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400403 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404 .port_ops = &ahci_ops,
405 },
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200406 /* board_ahci_vt8251 */
407 {
Tejun Heo6949b912007-09-23 13:19:55 +0900408 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
Tejun Heo417a1a62007-09-23 13:19:55 +0900409 .flags = AHCI_FLAG_COMMON,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200410 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400411 .udma_mask = ATA_UDMA6,
Tejun Heoad616ff2006-11-01 18:00:24 +0900412 .port_ops = &ahci_vt8251_ops,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200413 },
Tejun Heo41669552006-11-29 11:33:14 +0900414 /* board_ahci_ign_iferr */
415 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900416 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417 .flags = AHCI_FLAG_COMMON,
Tejun Heo41669552006-11-29 11:33:14 +0900418 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400419 .udma_mask = ATA_UDMA6,
Tejun Heo41669552006-11-29 11:33:14 +0900420 .port_ops = &ahci_ops,
421 },
Conke Hu55a61602007-03-27 18:33:05 +0800422 /* board_ahci_sb600 */
423 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900424 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
Tejun Heo22b5e7a2008-04-29 16:09:22 +0900425 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
Shane Huangbd172432008-06-10 15:52:04 +0800426 AHCI_HFLAG_SECT255),
Tejun Heo417a1a62007-09-23 13:19:55 +0900427 .flags = AHCI_FLAG_COMMON,
Conke Hu55a61602007-03-27 18:33:05 +0800428 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400429 .udma_mask = ATA_UDMA6,
Shane Huangbd172432008-06-10 15:52:04 +0800430 .port_ops = &ahci_sb600_ops,
Conke Hu55a61602007-03-27 18:33:05 +0800431 },
Jeff Garzikcd70c262007-07-08 02:29:42 -0400432 /* board_ahci_mv */
433 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900434 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
Tejun Heo17248462008-08-29 16:03:59 +0200435 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
Jeff Garzikcd70c262007-07-08 02:29:42 -0400436 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Tejun Heo417a1a62007-09-23 13:19:55 +0900437 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
Jeff Garzikcd70c262007-07-08 02:29:42 -0400438 .pio_mask = 0x1f, /* pio0-4 */
439 .udma_mask = ATA_UDMA6,
440 .port_ops = &ahci_ops,
441 },
Shane Huange39fc8c2008-02-22 05:00:31 -0800442 /* board_ahci_sb700 */
443 {
Shane Huangbd172432008-06-10 15:52:04 +0800444 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
Shane Huange39fc8c2008-02-22 05:00:31 -0800445 .flags = AHCI_FLAG_COMMON,
Shane Huange39fc8c2008-02-22 05:00:31 -0800446 .pio_mask = 0x1f, /* pio0-4 */
447 .udma_mask = ATA_UDMA6,
Shane Huangbd172432008-06-10 15:52:04 +0800448 .port_ops = &ahci_sb600_ops,
Shane Huange39fc8c2008-02-22 05:00:31 -0800449 },
Tejun Heoe297d992008-06-10 00:13:04 +0900450 /* board_ahci_mcp65 */
451 {
452 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
453 .flags = AHCI_FLAG_COMMON,
454 .pio_mask = 0x1f, /* pio0-4 */
455 .udma_mask = ATA_UDMA6,
456 .port_ops = &ahci_ops,
457 },
Tejun Heo9a3b1032008-06-18 20:56:58 -0400458 /* board_ahci_nopmp */
459 {
460 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
461 .flags = AHCI_FLAG_COMMON,
462 .pio_mask = 0x1f, /* pio0-4 */
463 .udma_mask = ATA_UDMA6,
464 .port_ops = &ahci_ops,
465 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700466};
467
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500468static const struct pci_device_id ahci_pci_tbl[] = {
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400469 /* Intel */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400470 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
471 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
472 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
473 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
474 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
Tejun Heo82490c02007-01-23 15:13:39 +0900475 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400476 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
477 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
478 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
479 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
Tejun Heo7a234af2007-09-03 12:44:57 +0900480 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
481 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
482 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
483 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
484 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
485 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
486 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
487 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
488 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
489 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
490 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
491 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
492 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
493 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
494 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
495 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
496 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
Jason Gastond4155e62007-09-20 17:35:00 -0400497 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
498 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800499 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
500 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700501 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700502 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700503 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700504 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400505
Tejun Heoe34bb372007-02-26 20:24:03 +0900506 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
507 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
508 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400509
510 /* ATI */
Conke Huc65ec1c2007-04-11 18:23:14 +0800511 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800512 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
513 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
514 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
515 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
516 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
517 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400518
519 /* VIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400520 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
Tejun Heobf335542007-04-11 17:27:14 +0900521 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400522
523 /* NVIDIA */
Tejun Heoe297d992008-06-10 00:13:04 +0900524 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
525 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
526 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
527 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
528 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
529 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
530 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
531 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
Peer Chen6fbf5ba2006-12-20 14:18:00 -0500532 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
533 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
534 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
535 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
Peer Chen895663c2006-11-02 17:59:46 -0500536 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
537 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
538 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
539 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
540 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
541 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
542 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
543 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
Peer Chen0522b282007-06-07 18:05:12 +0800544 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
545 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
546 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
547 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
548 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
549 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
550 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
551 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
552 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
553 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
554 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
555 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
556 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
557 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
558 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
559 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
560 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
561 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
562 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
563 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
564 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
565 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
566 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
567 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
peerchen6ba86952007-12-03 22:20:37 +0800568 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
569 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
570 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
571 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
Peer Chen71008192007-09-24 10:16:25 +0800572 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
573 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
574 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
575 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
576 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
577 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
578 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
579 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
peerchen70d562c2008-03-06 21:22:41 +0800580 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
581 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
582 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
583 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
584 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
585 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
586 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
587 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
peerchen3072c372008-05-19 14:44:57 +0800588 { PCI_VDEVICE(NVIDIA, 0x0bc4), board_ahci }, /* MCP7B */
589 { PCI_VDEVICE(NVIDIA, 0x0bc5), board_ahci }, /* MCP7B */
590 { PCI_VDEVICE(NVIDIA, 0x0bc6), board_ahci }, /* MCP7B */
591 { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400592
Jeff Garzik95916ed2006-07-29 04:10:14 -0400593 /* SiS */
Tejun Heo20e2de42008-08-01 12:51:43 +0900594 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
595 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
596 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
Jeff Garzik95916ed2006-07-29 04:10:14 -0400597
Jeff Garzikcd70c262007-07-08 02:29:42 -0400598 /* Marvell */
599 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100600 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
Jeff Garzikcd70c262007-07-08 02:29:42 -0400601
Mark Nelsonc77a0362008-10-23 14:08:16 +1100602 /* Promise */
603 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
604
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500605 /* Generic, PCI class code for AHCI */
606 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Conke Huc9f89472007-01-09 05:32:51 -0500607 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500608
Linus Torvalds1da177e2005-04-16 15:20:36 -0700609 { } /* terminate list */
610};
611
612
613static struct pci_driver ahci_pci_driver = {
614 .name = DRV_NAME,
615 .id_table = ahci_pci_tbl,
616 .probe = ahci_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900617 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900618#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900619 .suspend = ahci_pci_device_suspend,
620 .resume = ahci_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900621#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700622};
623
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700624static int ahci_em_messages = 1;
625module_param(ahci_em_messages, int, 0444);
626/* add other LED protocol types when they become supported */
627MODULE_PARM_DESC(ahci_em_messages,
628 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700629
Alan Cox5b66c822008-09-03 14:48:34 +0100630#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
631static int marvell_enable;
632#else
633static int marvell_enable = 1;
634#endif
635module_param(marvell_enable, int, 0644);
636MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
637
638
Tejun Heo98fa4b62006-11-02 12:17:23 +0900639static inline int ahci_nr_ports(u32 cap)
640{
641 return (cap & 0x1f) + 1;
642}
643
Jeff Garzikdab632e2007-05-28 08:33:01 -0400644static inline void __iomem *__ahci_port_base(struct ata_host *host,
645 unsigned int port_no)
646{
647 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
648
649 return mmio + 0x100 + (port_no * 0x80);
650}
651
Tejun Heo4447d352007-04-17 23:44:08 +0900652static inline void __iomem *ahci_port_base(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653{
Jeff Garzikdab632e2007-05-28 08:33:01 -0400654 return __ahci_port_base(ap->host, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655}
656
Tejun Heob710a1f2008-01-05 23:11:57 +0900657static void ahci_enable_ahci(void __iomem *mmio)
658{
Tejun Heo15fe9822008-04-23 20:52:58 +0900659 int i;
Tejun Heob710a1f2008-01-05 23:11:57 +0900660 u32 tmp;
661
662 /* turn on AHCI_EN */
663 tmp = readl(mmio + HOST_CTL);
Tejun Heo15fe9822008-04-23 20:52:58 +0900664 if (tmp & HOST_AHCI_EN)
665 return;
666
667 /* Some controllers need AHCI_EN to be written multiple times.
668 * Try a few times before giving up.
669 */
670 for (i = 0; i < 5; i++) {
Tejun Heob710a1f2008-01-05 23:11:57 +0900671 tmp |= HOST_AHCI_EN;
672 writel(tmp, mmio + HOST_CTL);
673 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
Tejun Heo15fe9822008-04-23 20:52:58 +0900674 if (tmp & HOST_AHCI_EN)
675 return;
676 msleep(10);
Tejun Heob710a1f2008-01-05 23:11:57 +0900677 }
Tejun Heo15fe9822008-04-23 20:52:58 +0900678
679 WARN_ON(1);
Tejun Heob710a1f2008-01-05 23:11:57 +0900680}
681
Tejun Heod447df12007-03-18 22:15:33 +0900682/**
683 * ahci_save_initial_config - Save and fixup initial config values
Tejun Heo4447d352007-04-17 23:44:08 +0900684 * @pdev: target PCI device
Tejun Heo4447d352007-04-17 23:44:08 +0900685 * @hpriv: host private area to store config values
Tejun Heod447df12007-03-18 22:15:33 +0900686 *
687 * Some registers containing configuration info might be setup by
688 * BIOS and might be cleared on reset. This function saves the
689 * initial values of those registers into @hpriv such that they
690 * can be restored after controller reset.
691 *
692 * If inconsistent, config values are fixed up by this function.
693 *
694 * LOCKING:
695 * None.
696 */
Tejun Heo4447d352007-04-17 23:44:08 +0900697static void ahci_save_initial_config(struct pci_dev *pdev,
Tejun Heo4447d352007-04-17 23:44:08 +0900698 struct ahci_host_priv *hpriv)
Tejun Heod447df12007-03-18 22:15:33 +0900699{
Tejun Heo4447d352007-04-17 23:44:08 +0900700 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +0900701 u32 cap, port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900702 int i;
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100703 int mv;
Tejun Heod447df12007-03-18 22:15:33 +0900704
Tejun Heob710a1f2008-01-05 23:11:57 +0900705 /* make sure AHCI mode is enabled before accessing CAP */
706 ahci_enable_ahci(mmio);
707
Tejun Heod447df12007-03-18 22:15:33 +0900708 /* Values prefixed with saved_ are written back to host after
709 * reset. Values without are used for driver operation.
710 */
711 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
712 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
713
Tejun Heo274c1fd2007-07-16 14:29:40 +0900714 /* some chips have errata preventing 64bit use */
Tejun Heo417a1a62007-09-23 13:19:55 +0900715 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
Tejun Heoc7a42152007-05-18 16:23:19 +0200716 dev_printk(KERN_INFO, &pdev->dev,
717 "controller can't do 64bit DMA, forcing 32bit\n");
718 cap &= ~HOST_CAP_64;
719 }
720
Tejun Heo417a1a62007-09-23 13:19:55 +0900721 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
Tejun Heo274c1fd2007-07-16 14:29:40 +0900722 dev_printk(KERN_INFO, &pdev->dev,
723 "controller can't do NCQ, turning off CAP_NCQ\n");
724 cap &= ~HOST_CAP_NCQ;
725 }
726
Tejun Heoe297d992008-06-10 00:13:04 +0900727 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
728 dev_printk(KERN_INFO, &pdev->dev,
729 "controller can do NCQ, turning on CAP_NCQ\n");
730 cap |= HOST_CAP_NCQ;
731 }
732
Roel Kluin258cd842008-03-09 21:42:40 +0100733 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
Tejun Heo6949b912007-09-23 13:19:55 +0900734 dev_printk(KERN_INFO, &pdev->dev,
735 "controller can't do PMP, turning off CAP_PMP\n");
736 cap &= ~HOST_CAP_PMP;
737 }
738
Tejun Heod799e082008-06-17 12:46:30 +0900739 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
740 port_map != 1) {
741 dev_printk(KERN_INFO, &pdev->dev,
742 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
743 port_map, 1);
744 port_map = 1;
745 }
746
Jeff Garzikcd70c262007-07-08 02:29:42 -0400747 /*
748 * Temporary Marvell 6145 hack: PATA port presence
749 * is asserted through the standard AHCI port
750 * presence register, as bit 4 (counting from 0)
751 */
Tejun Heo417a1a62007-09-23 13:19:55 +0900752 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100753 if (pdev->device == 0x6121)
754 mv = 0x3;
755 else
756 mv = 0xf;
Jeff Garzikcd70c262007-07-08 02:29:42 -0400757 dev_printk(KERN_ERR, &pdev->dev,
758 "MV_AHCI HACK: port_map %x -> %x\n",
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100759 port_map,
760 port_map & mv);
Alan Cox5b66c822008-09-03 14:48:34 +0100761 dev_printk(KERN_ERR, &pdev->dev,
762 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
Jeff Garzikcd70c262007-07-08 02:29:42 -0400763
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100764 port_map &= mv;
Jeff Garzikcd70c262007-07-08 02:29:42 -0400765 }
766
Tejun Heo17199b12007-03-18 22:26:53 +0900767 /* cross check port_map and cap.n_ports */
Tejun Heo7a234af2007-09-03 12:44:57 +0900768 if (port_map) {
Tejun Heo837f5f82008-02-06 15:13:51 +0900769 int map_ports = 0;
Tejun Heo17199b12007-03-18 22:26:53 +0900770
Tejun Heo837f5f82008-02-06 15:13:51 +0900771 for (i = 0; i < AHCI_MAX_PORTS; i++)
772 if (port_map & (1 << i))
773 map_ports++;
Tejun Heo17199b12007-03-18 22:26:53 +0900774
Tejun Heo837f5f82008-02-06 15:13:51 +0900775 /* If PI has more ports than n_ports, whine, clear
776 * port_map and let it be generated from n_ports.
Tejun Heo17199b12007-03-18 22:26:53 +0900777 */
Tejun Heo837f5f82008-02-06 15:13:51 +0900778 if (map_ports > ahci_nr_ports(cap)) {
Tejun Heo4447d352007-04-17 23:44:08 +0900779 dev_printk(KERN_WARNING, &pdev->dev,
Tejun Heo837f5f82008-02-06 15:13:51 +0900780 "implemented port map (0x%x) contains more "
781 "ports than nr_ports (%u), using nr_ports\n",
782 port_map, ahci_nr_ports(cap));
Tejun Heo7a234af2007-09-03 12:44:57 +0900783 port_map = 0;
784 }
785 }
786
787 /* fabricate port_map from cap.nr_ports */
788 if (!port_map) {
Tejun Heo17199b12007-03-18 22:26:53 +0900789 port_map = (1 << ahci_nr_ports(cap)) - 1;
Tejun Heo7a234af2007-09-03 12:44:57 +0900790 dev_printk(KERN_WARNING, &pdev->dev,
791 "forcing PORTS_IMPL to 0x%x\n", port_map);
792
793 /* write the fixed up value to the PI register */
794 hpriv->saved_port_map = port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900795 }
796
Tejun Heod447df12007-03-18 22:15:33 +0900797 /* record values to use during operation */
798 hpriv->cap = cap;
799 hpriv->port_map = port_map;
800}
801
802/**
803 * ahci_restore_initial_config - Restore initial config
Tejun Heo4447d352007-04-17 23:44:08 +0900804 * @host: target ATA host
Tejun Heod447df12007-03-18 22:15:33 +0900805 *
806 * Restore initial config stored by ahci_save_initial_config().
807 *
808 * LOCKING:
809 * None.
810 */
Tejun Heo4447d352007-04-17 23:44:08 +0900811static void ahci_restore_initial_config(struct ata_host *host)
Tejun Heod447df12007-03-18 22:15:33 +0900812{
Tejun Heo4447d352007-04-17 23:44:08 +0900813 struct ahci_host_priv *hpriv = host->private_data;
814 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
815
Tejun Heod447df12007-03-18 22:15:33 +0900816 writel(hpriv->saved_cap, mmio + HOST_CAP);
817 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
818 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
819}
820
Tejun Heo203ef6c2007-07-16 14:29:40 +0900821static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822{
Tejun Heo203ef6c2007-07-16 14:29:40 +0900823 static const int offset[] = {
824 [SCR_STATUS] = PORT_SCR_STAT,
825 [SCR_CONTROL] = PORT_SCR_CTL,
826 [SCR_ERROR] = PORT_SCR_ERR,
827 [SCR_ACTIVE] = PORT_SCR_ACT,
828 [SCR_NOTIFICATION] = PORT_SCR_NTF,
829 };
830 struct ahci_host_priv *hpriv = ap->host->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700831
Tejun Heo203ef6c2007-07-16 14:29:40 +0900832 if (sc_reg < ARRAY_SIZE(offset) &&
833 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
834 return offset[sc_reg];
Tejun Heoda3dbb12007-07-16 14:29:40 +0900835 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700836}
837
Tejun Heo82ef04f2008-07-31 17:02:40 +0900838static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700839{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900840 void __iomem *port_mmio = ahci_port_base(link->ap);
841 int offset = ahci_scr_offset(link->ap, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842
Tejun Heo203ef6c2007-07-16 14:29:40 +0900843 if (offset) {
844 *val = readl(port_mmio + offset);
845 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700846 }
Tejun Heo203ef6c2007-07-16 14:29:40 +0900847 return -EINVAL;
848}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700849
Tejun Heo82ef04f2008-07-31 17:02:40 +0900850static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
Tejun Heo203ef6c2007-07-16 14:29:40 +0900851{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900852 void __iomem *port_mmio = ahci_port_base(link->ap);
853 int offset = ahci_scr_offset(link->ap, sc_reg);
Tejun Heo203ef6c2007-07-16 14:29:40 +0900854
855 if (offset) {
856 writel(val, port_mmio + offset);
857 return 0;
858 }
859 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700860}
861
Tejun Heo4447d352007-04-17 23:44:08 +0900862static void ahci_start_engine(struct ata_port *ap)
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900863{
Tejun Heo4447d352007-04-17 23:44:08 +0900864 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900865 u32 tmp;
866
Tejun Heod8fcd112006-07-26 15:59:25 +0900867 /* start DMA */
Tejun Heo9f592052006-07-26 15:59:26 +0900868 tmp = readl(port_mmio + PORT_CMD);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900869 tmp |= PORT_CMD_START;
870 writel(tmp, port_mmio + PORT_CMD);
871 readl(port_mmio + PORT_CMD); /* flush */
872}
873
Tejun Heo4447d352007-04-17 23:44:08 +0900874static int ahci_stop_engine(struct ata_port *ap)
Tejun Heo254950c2006-07-26 15:59:25 +0900875{
Tejun Heo4447d352007-04-17 23:44:08 +0900876 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo254950c2006-07-26 15:59:25 +0900877 u32 tmp;
878
879 tmp = readl(port_mmio + PORT_CMD);
880
Tejun Heod8fcd112006-07-26 15:59:25 +0900881 /* check if the HBA is idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900882 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
883 return 0;
884
Tejun Heod8fcd112006-07-26 15:59:25 +0900885 /* setting HBA to idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900886 tmp &= ~PORT_CMD_START;
887 writel(tmp, port_mmio + PORT_CMD);
888
Tejun Heod8fcd112006-07-26 15:59:25 +0900889 /* wait for engine to stop. This could be as long as 500 msec */
Tejun Heo254950c2006-07-26 15:59:25 +0900890 tmp = ata_wait_register(port_mmio + PORT_CMD,
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400891 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
Tejun Heod8fcd112006-07-26 15:59:25 +0900892 if (tmp & PORT_CMD_LIST_ON)
Tejun Heo254950c2006-07-26 15:59:25 +0900893 return -EIO;
894
895 return 0;
896}
897
Tejun Heo4447d352007-04-17 23:44:08 +0900898static void ahci_start_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900899{
Tejun Heo4447d352007-04-17 23:44:08 +0900900 void __iomem *port_mmio = ahci_port_base(ap);
901 struct ahci_host_priv *hpriv = ap->host->private_data;
902 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo0be0aa92006-07-26 15:59:26 +0900903 u32 tmp;
904
905 /* set FIS registers */
Tejun Heo4447d352007-04-17 23:44:08 +0900906 if (hpriv->cap & HOST_CAP_64)
907 writel((pp->cmd_slot_dma >> 16) >> 16,
908 port_mmio + PORT_LST_ADDR_HI);
909 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900910
Tejun Heo4447d352007-04-17 23:44:08 +0900911 if (hpriv->cap & HOST_CAP_64)
912 writel((pp->rx_fis_dma >> 16) >> 16,
913 port_mmio + PORT_FIS_ADDR_HI);
914 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900915
916 /* enable FIS reception */
917 tmp = readl(port_mmio + PORT_CMD);
918 tmp |= PORT_CMD_FIS_RX;
919 writel(tmp, port_mmio + PORT_CMD);
920
921 /* flush */
922 readl(port_mmio + PORT_CMD);
923}
924
Tejun Heo4447d352007-04-17 23:44:08 +0900925static int ahci_stop_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900926{
Tejun Heo4447d352007-04-17 23:44:08 +0900927 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900928 u32 tmp;
929
930 /* disable FIS reception */
931 tmp = readl(port_mmio + PORT_CMD);
932 tmp &= ~PORT_CMD_FIS_RX;
933 writel(tmp, port_mmio + PORT_CMD);
934
935 /* wait for completion, spec says 500ms, give it 1000 */
936 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
937 PORT_CMD_FIS_ON, 10, 1000);
938 if (tmp & PORT_CMD_FIS_ON)
939 return -EBUSY;
940
941 return 0;
942}
943
Tejun Heo4447d352007-04-17 23:44:08 +0900944static void ahci_power_up(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900945{
Tejun Heo4447d352007-04-17 23:44:08 +0900946 struct ahci_host_priv *hpriv = ap->host->private_data;
947 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900948 u32 cmd;
949
950 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
951
952 /* spin up device */
Tejun Heo4447d352007-04-17 23:44:08 +0900953 if (hpriv->cap & HOST_CAP_SSS) {
Tejun Heo0be0aa92006-07-26 15:59:26 +0900954 cmd |= PORT_CMD_SPIN_UP;
955 writel(cmd, port_mmio + PORT_CMD);
956 }
957
958 /* wake up link */
959 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
960}
961
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400962static void ahci_disable_alpm(struct ata_port *ap)
963{
964 struct ahci_host_priv *hpriv = ap->host->private_data;
965 void __iomem *port_mmio = ahci_port_base(ap);
966 u32 cmd;
967 struct ahci_port_priv *pp = ap->private_data;
968
969 /* IPM bits should be disabled by libata-core */
970 /* get the existing command bits */
971 cmd = readl(port_mmio + PORT_CMD);
972
973 /* disable ALPM and ASP */
974 cmd &= ~PORT_CMD_ASP;
975 cmd &= ~PORT_CMD_ALPE;
976
977 /* force the interface back to active */
978 cmd |= PORT_CMD_ICC_ACTIVE;
979
980 /* write out new cmd value */
981 writel(cmd, port_mmio + PORT_CMD);
982 cmd = readl(port_mmio + PORT_CMD);
983
984 /* wait 10ms to be sure we've come out of any low power state */
985 msleep(10);
986
987 /* clear out any PhyRdy stuff from interrupt status */
988 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
989
990 /* go ahead and clean out PhyRdy Change from Serror too */
Tejun Heo82ef04f2008-07-31 17:02:40 +0900991 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400992
993 /*
994 * Clear flag to indicate that we should ignore all PhyRdy
995 * state changes
996 */
997 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
998
999 /*
1000 * Enable interrupts on Phy Ready.
1001 */
1002 pp->intr_mask |= PORT_IRQ_PHYRDY;
1003 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1004
1005 /*
1006 * don't change the link pm policy - we can be called
1007 * just to turn of link pm temporarily
1008 */
1009}
1010
1011static int ahci_enable_alpm(struct ata_port *ap,
1012 enum link_pm policy)
1013{
1014 struct ahci_host_priv *hpriv = ap->host->private_data;
1015 void __iomem *port_mmio = ahci_port_base(ap);
1016 u32 cmd;
1017 struct ahci_port_priv *pp = ap->private_data;
1018 u32 asp;
1019
1020 /* Make sure the host is capable of link power management */
1021 if (!(hpriv->cap & HOST_CAP_ALPM))
1022 return -EINVAL;
1023
1024 switch (policy) {
1025 case MAX_PERFORMANCE:
1026 case NOT_AVAILABLE:
1027 /*
1028 * if we came here with NOT_AVAILABLE,
1029 * it just means this is the first time we
1030 * have tried to enable - default to max performance,
1031 * and let the user go to lower power modes on request.
1032 */
1033 ahci_disable_alpm(ap);
1034 return 0;
1035 case MIN_POWER:
1036 /* configure HBA to enter SLUMBER */
1037 asp = PORT_CMD_ASP;
1038 break;
1039 case MEDIUM_POWER:
1040 /* configure HBA to enter PARTIAL */
1041 asp = 0;
1042 break;
1043 default:
1044 return -EINVAL;
1045 }
1046
1047 /*
1048 * Disable interrupts on Phy Ready. This keeps us from
1049 * getting woken up due to spurious phy ready interrupts
1050 * TBD - Hot plug should be done via polling now, is
1051 * that even supported?
1052 */
1053 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1054 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1055
1056 /*
1057 * Set a flag to indicate that we should ignore all PhyRdy
1058 * state changes since these can happen now whenever we
1059 * change link state
1060 */
1061 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1062
1063 /* get the existing command bits */
1064 cmd = readl(port_mmio + PORT_CMD);
1065
1066 /*
1067 * Set ASP based on Policy
1068 */
1069 cmd |= asp;
1070
1071 /*
1072 * Setting this bit will instruct the HBA to aggressively
1073 * enter a lower power link state when it's appropriate and
1074 * based on the value set above for ASP
1075 */
1076 cmd |= PORT_CMD_ALPE;
1077
1078 /* write out new cmd value */
1079 writel(cmd, port_mmio + PORT_CMD);
1080 cmd = readl(port_mmio + PORT_CMD);
1081
1082 /* IPM bits should be set by libata-core */
1083 return 0;
1084}
1085
Tejun Heo438ac6d2007-03-02 17:31:26 +09001086#ifdef CONFIG_PM
Tejun Heo4447d352007-04-17 23:44:08 +09001087static void ahci_power_down(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001088{
Tejun Heo4447d352007-04-17 23:44:08 +09001089 struct ahci_host_priv *hpriv = ap->host->private_data;
1090 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001091 u32 cmd, scontrol;
1092
Tejun Heo4447d352007-04-17 23:44:08 +09001093 if (!(hpriv->cap & HOST_CAP_SSS))
Tejun Heo07c53da2007-01-21 02:10:11 +09001094 return;
1095
1096 /* put device into listen mode, first set PxSCTL.DET to 0 */
1097 scontrol = readl(port_mmio + PORT_SCR_CTL);
1098 scontrol &= ~0xf;
1099 writel(scontrol, port_mmio + PORT_SCR_CTL);
1100
1101 /* then set PxCMD.SUD to 0 */
Tejun Heo0be0aa92006-07-26 15:59:26 +09001102 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
Tejun Heo07c53da2007-01-21 02:10:11 +09001103 cmd &= ~PORT_CMD_SPIN_UP;
1104 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001105}
Tejun Heo438ac6d2007-03-02 17:31:26 +09001106#endif
Tejun Heo0be0aa92006-07-26 15:59:26 +09001107
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001108static void ahci_start_port(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001109{
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001110 struct ahci_port_priv *pp = ap->private_data;
1111 struct ata_link *link;
1112 struct ahci_em_priv *emp;
1113
Tejun Heo0be0aa92006-07-26 15:59:26 +09001114 /* enable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +09001115 ahci_start_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001116
1117 /* enable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +09001118 ahci_start_engine(ap);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001119
1120 /* turn on LEDs */
1121 if (ap->flags & ATA_FLAG_EM) {
Tejun Heo1eca4362008-11-03 20:03:17 +09001122 ata_for_each_link(link, ap, EDGE) {
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001123 emp = &pp->em_priv[link->pmp];
1124 ahci_transmit_led_message(ap, emp->led_state, 4);
1125 }
1126 }
1127
1128 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
Tejun Heo1eca4362008-11-03 20:03:17 +09001129 ata_for_each_link(link, ap, EDGE)
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001130 ahci_init_sw_activity(link);
1131
Tejun Heo0be0aa92006-07-26 15:59:26 +09001132}
1133
Tejun Heo4447d352007-04-17 23:44:08 +09001134static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001135{
1136 int rc;
1137
1138 /* disable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +09001139 rc = ahci_stop_engine(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001140 if (rc) {
1141 *emsg = "failed to stop engine";
1142 return rc;
1143 }
1144
1145 /* disable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +09001146 rc = ahci_stop_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001147 if (rc) {
1148 *emsg = "failed stop FIS RX";
1149 return rc;
1150 }
1151
Tejun Heo0be0aa92006-07-26 15:59:26 +09001152 return 0;
1153}
1154
Tejun Heo4447d352007-04-17 23:44:08 +09001155static int ahci_reset_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +09001156{
Tejun Heo4447d352007-04-17 23:44:08 +09001157 struct pci_dev *pdev = to_pci_dev(host->dev);
Tejun Heo49f29092007-11-19 16:03:44 +09001158 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo4447d352007-04-17 23:44:08 +09001159 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +09001160 u32 tmp;
Tejun Heod91542c2006-07-26 15:59:26 +09001161
Jeff Garzik3cc3eb12007-09-26 00:02:41 -04001162 /* we must be in AHCI mode, before using anything
1163 * AHCI-specific, such as HOST_RESET.
1164 */
Tejun Heob710a1f2008-01-05 23:11:57 +09001165 ahci_enable_ahci(mmio);
Jeff Garzik3cc3eb12007-09-26 00:02:41 -04001166
1167 /* global controller reset */
Tejun Heoa22e6442008-03-10 10:25:25 +09001168 if (!ahci_skip_host_reset) {
1169 tmp = readl(mmio + HOST_CTL);
1170 if ((tmp & HOST_RESET) == 0) {
1171 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1172 readl(mmio + HOST_CTL); /* flush */
1173 }
Tejun Heod91542c2006-07-26 15:59:26 +09001174
Zhang Rui24920c82008-07-04 13:32:17 +08001175 /*
1176 * to perform host reset, OS should set HOST_RESET
1177 * and poll until this bit is read to be "0".
1178 * reset must complete within 1 second, or
Tejun Heoa22e6442008-03-10 10:25:25 +09001179 * the hardware should be considered fried.
1180 */
Zhang Rui24920c82008-07-04 13:32:17 +08001181 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1182 HOST_RESET, 10, 1000);
Tejun Heod91542c2006-07-26 15:59:26 +09001183
Tejun Heoa22e6442008-03-10 10:25:25 +09001184 if (tmp & HOST_RESET) {
1185 dev_printk(KERN_ERR, host->dev,
1186 "controller reset failed (0x%x)\n", tmp);
1187 return -EIO;
1188 }
Tejun Heod91542c2006-07-26 15:59:26 +09001189
Tejun Heoa22e6442008-03-10 10:25:25 +09001190 /* turn on AHCI mode */
1191 ahci_enable_ahci(mmio);
Tejun Heo98fa4b62006-11-02 12:17:23 +09001192
Tejun Heoa22e6442008-03-10 10:25:25 +09001193 /* Some registers might be cleared on reset. Restore
1194 * initial values.
1195 */
1196 ahci_restore_initial_config(host);
1197 } else
1198 dev_printk(KERN_INFO, host->dev,
1199 "skipping global host reset\n");
Tejun Heod91542c2006-07-26 15:59:26 +09001200
1201 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1202 u16 tmp16;
1203
1204 /* configure PCS */
1205 pci_read_config_word(pdev, 0x92, &tmp16);
Tejun Heo49f29092007-11-19 16:03:44 +09001206 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1207 tmp16 |= hpriv->port_map;
1208 pci_write_config_word(pdev, 0x92, tmp16);
1209 }
Tejun Heod91542c2006-07-26 15:59:26 +09001210 }
1211
1212 return 0;
1213}
1214
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001215static void ahci_sw_activity(struct ata_link *link)
1216{
1217 struct ata_port *ap = link->ap;
1218 struct ahci_port_priv *pp = ap->private_data;
1219 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1220
1221 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1222 return;
1223
1224 emp->activity++;
1225 if (!timer_pending(&emp->timer))
1226 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1227}
1228
1229static void ahci_sw_activity_blink(unsigned long arg)
1230{
1231 struct ata_link *link = (struct ata_link *)arg;
1232 struct ata_port *ap = link->ap;
1233 struct ahci_port_priv *pp = ap->private_data;
1234 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1235 unsigned long led_message = emp->led_state;
1236 u32 activity_led_state;
David Milburneb409632008-10-16 09:26:19 -05001237 unsigned long flags;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001238
David Milburn87943ac2008-10-13 14:38:36 -05001239 led_message &= EM_MSG_LED_VALUE;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001240 led_message |= ap->port_no | (link->pmp << 8);
1241
1242 /* check to see if we've had activity. If so,
1243 * toggle state of LED and reset timer. If not,
1244 * turn LED to desired idle state.
1245 */
David Milburneb409632008-10-16 09:26:19 -05001246 spin_lock_irqsave(ap->lock, flags);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001247 if (emp->saved_activity != emp->activity) {
1248 emp->saved_activity = emp->activity;
1249 /* get the current LED state */
David Milburn87943ac2008-10-13 14:38:36 -05001250 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001251
1252 if (activity_led_state)
1253 activity_led_state = 0;
1254 else
1255 activity_led_state = 1;
1256
1257 /* clear old state */
David Milburn87943ac2008-10-13 14:38:36 -05001258 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001259
1260 /* toggle state */
1261 led_message |= (activity_led_state << 16);
1262 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1263 } else {
1264 /* switch to idle */
David Milburn87943ac2008-10-13 14:38:36 -05001265 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001266 if (emp->blink_policy == BLINK_OFF)
1267 led_message |= (1 << 16);
1268 }
David Milburneb409632008-10-16 09:26:19 -05001269 spin_unlock_irqrestore(ap->lock, flags);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001270 ahci_transmit_led_message(ap, led_message, 4);
1271}
1272
1273static void ahci_init_sw_activity(struct ata_link *link)
1274{
1275 struct ata_port *ap = link->ap;
1276 struct ahci_port_priv *pp = ap->private_data;
1277 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1278
1279 /* init activity stats, setup timer */
1280 emp->saved_activity = emp->activity = 0;
1281 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1282
1283 /* check our blink policy and set flag for link if it's enabled */
1284 if (emp->blink_policy)
1285 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1286}
1287
1288static int ahci_reset_em(struct ata_host *host)
1289{
1290 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1291 u32 em_ctl;
1292
1293 em_ctl = readl(mmio + HOST_EM_CTL);
1294 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1295 return -EINVAL;
1296
1297 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1298 return 0;
1299}
1300
1301static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1302 ssize_t size)
1303{
1304 struct ahci_host_priv *hpriv = ap->host->private_data;
1305 struct ahci_port_priv *pp = ap->private_data;
1306 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1307 u32 em_ctl;
1308 u32 message[] = {0, 0};
Linus Torvalds93082f02008-07-25 10:56:36 -07001309 unsigned long flags;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001310 int pmp;
1311 struct ahci_em_priv *emp;
1312
1313 /* get the slot number from the message */
David Milburn87943ac2008-10-13 14:38:36 -05001314 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001315 if (pmp < MAX_SLOTS)
1316 emp = &pp->em_priv[pmp];
1317 else
1318 return -EINVAL;
1319
1320 spin_lock_irqsave(ap->lock, flags);
1321
1322 /*
1323 * if we are still busy transmitting a previous message,
1324 * do not allow
1325 */
1326 em_ctl = readl(mmio + HOST_EM_CTL);
1327 if (em_ctl & EM_CTL_TM) {
1328 spin_unlock_irqrestore(ap->lock, flags);
1329 return -EINVAL;
1330 }
1331
1332 /*
1333 * create message header - this is all zero except for
1334 * the message size, which is 4 bytes.
1335 */
1336 message[0] |= (4 << 8);
1337
1338 /* ignore 0:4 of byte zero, fill in port info yourself */
David Milburn87943ac2008-10-13 14:38:36 -05001339 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001340
1341 /* write message to EM_LOC */
1342 writel(message[0], mmio + hpriv->em_loc);
1343 writel(message[1], mmio + hpriv->em_loc+4);
1344
1345 /* save off new led state for port/slot */
1346 emp->led_state = message[1];
1347
1348 /*
1349 * tell hardware to transmit the message
1350 */
1351 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1352
1353 spin_unlock_irqrestore(ap->lock, flags);
1354 return size;
1355}
1356
1357static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1358{
1359 struct ahci_port_priv *pp = ap->private_data;
1360 struct ata_link *link;
1361 struct ahci_em_priv *emp;
1362 int rc = 0;
1363
Tejun Heo1eca4362008-11-03 20:03:17 +09001364 ata_for_each_link(link, ap, EDGE) {
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001365 emp = &pp->em_priv[link->pmp];
1366 rc += sprintf(buf, "%lx\n", emp->led_state);
1367 }
1368 return rc;
1369}
1370
1371static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1372 size_t size)
1373{
1374 int state;
1375 int pmp;
1376 struct ahci_port_priv *pp = ap->private_data;
1377 struct ahci_em_priv *emp;
1378
1379 state = simple_strtoul(buf, NULL, 0);
1380
1381 /* get the slot number from the message */
David Milburn87943ac2008-10-13 14:38:36 -05001382 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001383 if (pmp < MAX_SLOTS)
1384 emp = &pp->em_priv[pmp];
1385 else
1386 return -EINVAL;
1387
1388 /* mask off the activity bits if we are in sw_activity
1389 * mode, user should turn off sw_activity before setting
1390 * activity led through em_message
1391 */
1392 if (emp->blink_policy)
David Milburn87943ac2008-10-13 14:38:36 -05001393 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001394
1395 return ahci_transmit_led_message(ap, state, size);
1396}
1397
1398static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1399{
1400 struct ata_link *link = dev->link;
1401 struct ata_port *ap = link->ap;
1402 struct ahci_port_priv *pp = ap->private_data;
1403 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1404 u32 port_led_state = emp->led_state;
1405
1406 /* save the desired Activity LED behavior */
1407 if (val == OFF) {
1408 /* clear LFLAG */
1409 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1410
1411 /* set the LED to OFF */
David Milburn87943ac2008-10-13 14:38:36 -05001412 port_led_state &= EM_MSG_LED_VALUE_OFF;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001413 port_led_state |= (ap->port_no | (link->pmp << 8));
1414 ahci_transmit_led_message(ap, port_led_state, 4);
1415 } else {
1416 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1417 if (val == BLINK_OFF) {
1418 /* set LED to ON for idle */
David Milburn87943ac2008-10-13 14:38:36 -05001419 port_led_state &= EM_MSG_LED_VALUE_OFF;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001420 port_led_state |= (ap->port_no | (link->pmp << 8));
David Milburn87943ac2008-10-13 14:38:36 -05001421 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001422 ahci_transmit_led_message(ap, port_led_state, 4);
1423 }
1424 }
1425 emp->blink_policy = val;
1426 return 0;
1427}
1428
1429static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1430{
1431 struct ata_link *link = dev->link;
1432 struct ata_port *ap = link->ap;
1433 struct ahci_port_priv *pp = ap->private_data;
1434 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1435
1436 /* display the saved value of activity behavior for this
1437 * disk.
1438 */
1439 return sprintf(buf, "%d\n", emp->blink_policy);
1440}
1441
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001442static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1443 int port_no, void __iomem *mmio,
1444 void __iomem *port_mmio)
1445{
1446 const char *emsg = NULL;
1447 int rc;
1448 u32 tmp;
1449
1450 /* make sure port is not active */
1451 rc = ahci_deinit_port(ap, &emsg);
1452 if (rc)
1453 dev_printk(KERN_WARNING, &pdev->dev,
1454 "%s (%d)\n", emsg, rc);
1455
1456 /* clear SError */
1457 tmp = readl(port_mmio + PORT_SCR_ERR);
1458 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1459 writel(tmp, port_mmio + PORT_SCR_ERR);
1460
1461 /* clear port IRQ */
1462 tmp = readl(port_mmio + PORT_IRQ_STAT);
1463 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1464 if (tmp)
1465 writel(tmp, port_mmio + PORT_IRQ_STAT);
1466
1467 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1468}
1469
Tejun Heo4447d352007-04-17 23:44:08 +09001470static void ahci_init_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +09001471{
Tejun Heo417a1a62007-09-23 13:19:55 +09001472 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo4447d352007-04-17 23:44:08 +09001473 struct pci_dev *pdev = to_pci_dev(host->dev);
1474 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001475 int i;
Jeff Garzikcd70c262007-07-08 02:29:42 -04001476 void __iomem *port_mmio;
Tejun Heod91542c2006-07-26 15:59:26 +09001477 u32 tmp;
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +01001478 int mv;
Tejun Heod91542c2006-07-26 15:59:26 +09001479
Tejun Heo417a1a62007-09-23 13:19:55 +09001480 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +01001481 if (pdev->device == 0x6121)
1482 mv = 2;
1483 else
1484 mv = 4;
1485 port_mmio = __ahci_port_base(host, mv);
Jeff Garzikcd70c262007-07-08 02:29:42 -04001486
1487 writel(0, port_mmio + PORT_IRQ_MASK);
1488
1489 /* clear port IRQ */
1490 tmp = readl(port_mmio + PORT_IRQ_STAT);
1491 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1492 if (tmp)
1493 writel(tmp, port_mmio + PORT_IRQ_STAT);
1494 }
1495
Tejun Heo4447d352007-04-17 23:44:08 +09001496 for (i = 0; i < host->n_ports; i++) {
1497 struct ata_port *ap = host->ports[i];
Tejun Heod91542c2006-07-26 15:59:26 +09001498
Jeff Garzikcd70c262007-07-08 02:29:42 -04001499 port_mmio = ahci_port_base(ap);
Tejun Heo4447d352007-04-17 23:44:08 +09001500 if (ata_port_is_dummy(ap))
Tejun Heod91542c2006-07-26 15:59:26 +09001501 continue;
Tejun Heod91542c2006-07-26 15:59:26 +09001502
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001503 ahci_port_init(pdev, ap, i, mmio, port_mmio);
Tejun Heod91542c2006-07-26 15:59:26 +09001504 }
1505
1506 tmp = readl(mmio + HOST_CTL);
1507 VPRINTK("HOST_CTL 0x%x\n", tmp);
1508 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1509 tmp = readl(mmio + HOST_CTL);
1510 VPRINTK("HOST_CTL 0x%x\n", tmp);
1511}
1512
Jeff Garzika8785392008-02-28 15:43:48 -05001513static void ahci_dev_config(struct ata_device *dev)
1514{
1515 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1516
Jeff Garzik4cde32f2008-03-24 22:40:40 -04001517 if (hpriv->flags & AHCI_HFLAG_SECT255) {
Jeff Garzika8785392008-02-28 15:43:48 -05001518 dev->max_sectors = 255;
Jeff Garzik4cde32f2008-03-24 22:40:40 -04001519 ata_dev_printk(dev, KERN_INFO,
1520 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1521 }
Jeff Garzika8785392008-02-28 15:43:48 -05001522}
1523
Tejun Heo422b7592005-12-19 22:37:17 +09001524static unsigned int ahci_dev_classify(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001525{
Tejun Heo4447d352007-04-17 23:44:08 +09001526 void __iomem *port_mmio = ahci_port_base(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001527 struct ata_taskfile tf;
Tejun Heo422b7592005-12-19 22:37:17 +09001528 u32 tmp;
1529
1530 tmp = readl(port_mmio + PORT_SIG);
1531 tf.lbah = (tmp >> 24) & 0xff;
1532 tf.lbam = (tmp >> 16) & 0xff;
1533 tf.lbal = (tmp >> 8) & 0xff;
1534 tf.nsect = (tmp) & 0xff;
1535
1536 return ata_dev_classify(&tf);
1537}
1538
Tejun Heo12fad3f2006-05-15 21:03:55 +09001539static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1540 u32 opts)
Tejun Heocc9278e2006-02-10 17:25:47 +09001541{
Tejun Heo12fad3f2006-05-15 21:03:55 +09001542 dma_addr_t cmd_tbl_dma;
1543
1544 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1545
1546 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1547 pp->cmd_slot[tag].status = 0;
1548 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1549 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
Tejun Heocc9278e2006-02-10 17:25:47 +09001550}
1551
Tejun Heod2e75df2007-07-16 14:29:39 +09001552static int ahci_kick_engine(struct ata_port *ap, int force_restart)
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001553{
Tejun Heo350756f2008-04-07 22:47:21 +09001554 void __iomem *port_mmio = ahci_port_base(ap);
Jeff Garzikcca39742006-08-24 03:19:22 -04001555 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo520d06f2008-04-07 22:47:21 +09001556 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001557 u32 tmp;
Tejun Heod2e75df2007-07-16 14:29:39 +09001558 int busy, rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001559
Tejun Heod2e75df2007-07-16 14:29:39 +09001560 /* do we need to kick the port? */
Tejun Heo520d06f2008-04-07 22:47:21 +09001561 busy = status & (ATA_BUSY | ATA_DRQ);
Tejun Heod2e75df2007-07-16 14:29:39 +09001562 if (!busy && !force_restart)
1563 return 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001564
Tejun Heod2e75df2007-07-16 14:29:39 +09001565 /* stop engine */
1566 rc = ahci_stop_engine(ap);
1567 if (rc)
1568 goto out_restart;
1569
1570 /* need to do CLO? */
1571 if (!busy) {
1572 rc = 0;
1573 goto out_restart;
1574 }
1575
1576 if (!(hpriv->cap & HOST_CAP_CLO)) {
1577 rc = -EOPNOTSUPP;
1578 goto out_restart;
1579 }
1580
1581 /* perform CLO */
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001582 tmp = readl(port_mmio + PORT_CMD);
1583 tmp |= PORT_CMD_CLO;
1584 writel(tmp, port_mmio + PORT_CMD);
1585
Tejun Heod2e75df2007-07-16 14:29:39 +09001586 rc = 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001587 tmp = ata_wait_register(port_mmio + PORT_CMD,
1588 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1589 if (tmp & PORT_CMD_CLO)
Tejun Heod2e75df2007-07-16 14:29:39 +09001590 rc = -EIO;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001591
Tejun Heod2e75df2007-07-16 14:29:39 +09001592 /* restart engine */
1593 out_restart:
1594 ahci_start_engine(ap);
1595 return rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001596}
1597
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001598static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1599 struct ata_taskfile *tf, int is_cmd, u16 flags,
1600 unsigned long timeout_msec)
1601{
1602 const u32 cmd_fis_len = 5; /* five dwords */
1603 struct ahci_port_priv *pp = ap->private_data;
1604 void __iomem *port_mmio = ahci_port_base(ap);
1605 u8 *fis = pp->cmd_tbl;
1606 u32 tmp;
1607
1608 /* prep the command */
1609 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1610 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1611
1612 /* issue & wait */
1613 writel(1, port_mmio + PORT_CMD_ISSUE);
1614
1615 if (timeout_msec) {
1616 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1617 1, timeout_msec);
1618 if (tmp & 0x1) {
1619 ahci_kick_engine(ap, 1);
1620 return -EBUSY;
1621 }
1622 } else
1623 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1624
1625 return 0;
1626}
1627
Shane Huangbd172432008-06-10 15:52:04 +08001628static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1629 int pmp, unsigned long deadline,
1630 int (*check_ready)(struct ata_link *link))
Tejun Heo4658f792006-03-22 21:07:03 +09001631{
Tejun Heocc0680a2007-08-06 18:36:23 +09001632 struct ata_port *ap = link->ap;
Tejun Heo4658f792006-03-22 21:07:03 +09001633 const char *reason = NULL;
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001634 unsigned long now, msecs;
Tejun Heo4658f792006-03-22 21:07:03 +09001635 struct ata_taskfile tf;
Tejun Heo4658f792006-03-22 21:07:03 +09001636 int rc;
1637
1638 DPRINTK("ENTER\n");
1639
1640 /* prepare for SRST (AHCI-1.1 10.4.1) */
Tejun Heod2e75df2007-07-16 14:29:39 +09001641 rc = ahci_kick_engine(ap, 1);
Tejun Heo994056d2007-12-06 15:02:48 +09001642 if (rc && rc != -EOPNOTSUPP)
Tejun Heocc0680a2007-08-06 18:36:23 +09001643 ata_link_printk(link, KERN_WARNING,
Tejun Heo994056d2007-12-06 15:02:48 +09001644 "failed to reset engine (errno=%d)\n", rc);
Tejun Heo4658f792006-03-22 21:07:03 +09001645
Tejun Heocc0680a2007-08-06 18:36:23 +09001646 ata_tf_init(link->device, &tf);
Tejun Heo4658f792006-03-22 21:07:03 +09001647
1648 /* issue the first D2H Register FIS */
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001649 msecs = 0;
1650 now = jiffies;
1651 if (time_after(now, deadline))
1652 msecs = jiffies_to_msecs(deadline - now);
1653
Tejun Heo4658f792006-03-22 21:07:03 +09001654 tf.ctl |= ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001655 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001656 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
Tejun Heo4658f792006-03-22 21:07:03 +09001657 rc = -EIO;
1658 reason = "1st FIS failed";
1659 goto fail;
1660 }
1661
1662 /* spec says at least 5us, but be generous and sleep for 1ms */
1663 msleep(1);
1664
1665 /* issue the second D2H Register FIS */
Tejun Heo4658f792006-03-22 21:07:03 +09001666 tf.ctl &= ~ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001667 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
Tejun Heo4658f792006-03-22 21:07:03 +09001668
Tejun Heo705e76b2008-04-07 22:47:19 +09001669 /* wait for link to become ready */
Shane Huangbd172432008-06-10 15:52:04 +08001670 rc = ata_wait_after_reset(link, deadline, check_ready);
Tejun Heo9b893912007-02-02 16:50:52 +09001671 /* link occupied, -ENODEV too is an error */
1672 if (rc) {
1673 reason = "device not ready";
1674 goto fail;
Tejun Heo4658f792006-03-22 21:07:03 +09001675 }
Tejun Heo9b893912007-02-02 16:50:52 +09001676 *class = ahci_dev_classify(ap);
Tejun Heo4658f792006-03-22 21:07:03 +09001677
1678 DPRINTK("EXIT, class=%u\n", *class);
1679 return 0;
1680
Tejun Heo4658f792006-03-22 21:07:03 +09001681 fail:
Tejun Heocc0680a2007-08-06 18:36:23 +09001682 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
Tejun Heo4658f792006-03-22 21:07:03 +09001683 return rc;
1684}
1685
Shane Huangbd172432008-06-10 15:52:04 +08001686static int ahci_check_ready(struct ata_link *link)
1687{
1688 void __iomem *port_mmio = ahci_port_base(link->ap);
1689 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1690
1691 return ata_check_ready(status);
1692}
1693
1694static int ahci_softreset(struct ata_link *link, unsigned int *class,
1695 unsigned long deadline)
1696{
1697 int pmp = sata_srst_pmp(link);
1698
1699 DPRINTK("ENTER\n");
1700
1701 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1702}
1703
1704static int ahci_sb600_check_ready(struct ata_link *link)
1705{
1706 void __iomem *port_mmio = ahci_port_base(link->ap);
1707 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1708 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1709
1710 /*
1711 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1712 * which can save timeout delay.
1713 */
1714 if (irq_status & PORT_IRQ_BAD_PMP)
1715 return -EIO;
1716
1717 return ata_check_ready(status);
1718}
1719
1720static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1721 unsigned long deadline)
1722{
1723 struct ata_port *ap = link->ap;
1724 void __iomem *port_mmio = ahci_port_base(ap);
1725 int pmp = sata_srst_pmp(link);
1726 int rc;
1727 u32 irq_sts;
1728
1729 DPRINTK("ENTER\n");
1730
1731 rc = ahci_do_softreset(link, class, pmp, deadline,
1732 ahci_sb600_check_ready);
1733
1734 /*
1735 * Soft reset fails on some ATI chips with IPMS set when PMP
1736 * is enabled but SATA HDD/ODD is connected to SATA port,
1737 * do soft reset again to port 0.
1738 */
1739 if (rc == -EIO) {
1740 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1741 if (irq_sts & PORT_IRQ_BAD_PMP) {
1742 ata_link_printk(link, KERN_WARNING,
1743 "failed due to HW bug, retry pmp=0\n");
1744 rc = ahci_do_softreset(link, class, 0, deadline,
1745 ahci_check_ready);
1746 }
1747 }
1748
1749 return rc;
1750}
1751
Tejun Heocc0680a2007-08-06 18:36:23 +09001752static int ahci_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001753 unsigned long deadline)
Tejun Heo422b7592005-12-19 22:37:17 +09001754{
Tejun Heo9dadd452008-04-07 22:47:19 +09001755 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
Tejun Heocc0680a2007-08-06 18:36:23 +09001756 struct ata_port *ap = link->ap;
Tejun Heo42969712006-05-31 18:28:18 +09001757 struct ahci_port_priv *pp = ap->private_data;
1758 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1759 struct ata_taskfile tf;
Tejun Heo9dadd452008-04-07 22:47:19 +09001760 bool online;
Tejun Heo4bd00f62006-02-11 16:26:02 +09001761 int rc;
1762
1763 DPRINTK("ENTER\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001764
Tejun Heo4447d352007-04-17 23:44:08 +09001765 ahci_stop_engine(ap);
Tejun Heo42969712006-05-31 18:28:18 +09001766
1767 /* clear D2H reception area to properly wait for D2H FIS */
Tejun Heocc0680a2007-08-06 18:36:23 +09001768 ata_tf_init(link->device, &tf);
Tejun Heodfd7a3d2007-01-26 15:37:20 +09001769 tf.command = 0x80;
Tejun Heo99771262007-07-16 14:29:38 +09001770 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
Tejun Heo42969712006-05-31 18:28:18 +09001771
Tejun Heo9dadd452008-04-07 22:47:19 +09001772 rc = sata_link_hardreset(link, timing, deadline, &online,
1773 ahci_check_ready);
Tejun Heo42969712006-05-31 18:28:18 +09001774
Tejun Heo4447d352007-04-17 23:44:08 +09001775 ahci_start_engine(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001776
Tejun Heo9dadd452008-04-07 22:47:19 +09001777 if (online)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001778 *class = ahci_dev_classify(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001779
Tejun Heo4bd00f62006-02-11 16:26:02 +09001780 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1781 return rc;
1782}
1783
Tejun Heocc0680a2007-08-06 18:36:23 +09001784static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001785 unsigned long deadline)
Tejun Heoad616ff2006-11-01 18:00:24 +09001786{
Tejun Heocc0680a2007-08-06 18:36:23 +09001787 struct ata_port *ap = link->ap;
Tejun Heo9dadd452008-04-07 22:47:19 +09001788 bool online;
Tejun Heoad616ff2006-11-01 18:00:24 +09001789 int rc;
1790
1791 DPRINTK("ENTER\n");
1792
Tejun Heo4447d352007-04-17 23:44:08 +09001793 ahci_stop_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001794
Tejun Heocc0680a2007-08-06 18:36:23 +09001795 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +09001796 deadline, &online, NULL);
Tejun Heoad616ff2006-11-01 18:00:24 +09001797
Tejun Heo4447d352007-04-17 23:44:08 +09001798 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001799
1800 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1801
1802 /* vt8251 doesn't clear BSY on signature FIS reception,
1803 * request follow-up softreset.
1804 */
Tejun Heo9dadd452008-04-07 22:47:19 +09001805 return online ? -EAGAIN : rc;
Tejun Heoad616ff2006-11-01 18:00:24 +09001806}
1807
Tejun Heoedc93052007-10-25 14:59:16 +09001808static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1809 unsigned long deadline)
1810{
1811 struct ata_port *ap = link->ap;
1812 struct ahci_port_priv *pp = ap->private_data;
1813 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1814 struct ata_taskfile tf;
Tejun Heo9dadd452008-04-07 22:47:19 +09001815 bool online;
Tejun Heoedc93052007-10-25 14:59:16 +09001816 int rc;
1817
1818 ahci_stop_engine(ap);
1819
1820 /* clear D2H reception area to properly wait for D2H FIS */
1821 ata_tf_init(link->device, &tf);
1822 tf.command = 0x80;
1823 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1824
1825 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +09001826 deadline, &online, NULL);
Tejun Heoedc93052007-10-25 14:59:16 +09001827
1828 ahci_start_engine(ap);
1829
Tejun Heoedc93052007-10-25 14:59:16 +09001830 /* The pseudo configuration device on SIMG4726 attached to
1831 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1832 * hardreset if no device is attached to the first downstream
1833 * port && the pseudo device locks up on SRST w/ PMP==0. To
1834 * work around this, wait for !BSY only briefly. If BSY isn't
1835 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1836 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1837 *
1838 * Wait for two seconds. Devices attached to downstream port
1839 * which can't process the following IDENTIFY after this will
1840 * have to be reset again. For most cases, this should
1841 * suffice while making probing snappish enough.
1842 */
Tejun Heo9dadd452008-04-07 22:47:19 +09001843 if (online) {
1844 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1845 ahci_check_ready);
1846 if (rc)
1847 ahci_kick_engine(ap, 0);
1848 }
Tejun Heo9dadd452008-04-07 22:47:19 +09001849 return rc;
Tejun Heoedc93052007-10-25 14:59:16 +09001850}
1851
Tejun Heocc0680a2007-08-06 18:36:23 +09001852static void ahci_postreset(struct ata_link *link, unsigned int *class)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001853{
Tejun Heocc0680a2007-08-06 18:36:23 +09001854 struct ata_port *ap = link->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09001855 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001856 u32 new_tmp, tmp;
1857
Tejun Heo203c75b2008-04-07 22:47:18 +09001858 ata_std_postreset(link, class);
Jeff Garzik02eaa662005-11-12 01:32:19 -05001859
1860 /* Make sure port's ATAPI bit is set appropriately */
1861 new_tmp = tmp = readl(port_mmio + PORT_CMD);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001862 if (*class == ATA_DEV_ATAPI)
Jeff Garzik02eaa662005-11-12 01:32:19 -05001863 new_tmp |= PORT_CMD_ATAPI;
1864 else
1865 new_tmp &= ~PORT_CMD_ATAPI;
1866 if (new_tmp != tmp) {
1867 writel(new_tmp, port_mmio + PORT_CMD);
1868 readl(port_mmio + PORT_CMD); /* flush */
1869 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001870}
1871
Tejun Heo12fad3f2006-05-15 21:03:55 +09001872static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001873{
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001874 struct scatterlist *sg;
Tejun Heoff2aeb12007-12-05 16:43:11 +09001875 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1876 unsigned int si;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001877
1878 VPRINTK("ENTER\n");
1879
1880 /*
1881 * Next, the S/G list.
1882 */
Tejun Heoff2aeb12007-12-05 16:43:11 +09001883 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001884 dma_addr_t addr = sg_dma_address(sg);
1885 u32 sg_len = sg_dma_len(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001886
Tejun Heoff2aeb12007-12-05 16:43:11 +09001887 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1888 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1889 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001890 }
Jeff Garzik828d09d2005-11-12 01:27:07 -05001891
Tejun Heoff2aeb12007-12-05 16:43:11 +09001892 return si;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001893}
1894
1895static void ahci_qc_prep(struct ata_queued_cmd *qc)
1896{
Jeff Garzika0ea7322005-06-04 01:13:15 -04001897 struct ata_port *ap = qc->ap;
1898 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo405e66b2007-11-27 19:28:53 +09001899 int is_atapi = ata_is_atapi(qc->tf.protocol);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001900 void *cmd_tbl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001901 u32 opts;
1902 const u32 cmd_fis_len = 5; /* five dwords */
Jeff Garzik828d09d2005-11-12 01:27:07 -05001903 unsigned int n_elem;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001904
1905 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001906 * Fill in command table information. First, the header,
1907 * a SATA Register - Host to Device command FIS.
1908 */
Tejun Heo12fad3f2006-05-15 21:03:55 +09001909 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1910
Tejun Heo7d50b602007-09-23 13:19:54 +09001911 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
Tejun Heocc9278e2006-02-10 17:25:47 +09001912 if (is_atapi) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09001913 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1914 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
Jeff Garzika0ea7322005-06-04 01:13:15 -04001915 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001916
Tejun Heocc9278e2006-02-10 17:25:47 +09001917 n_elem = 0;
1918 if (qc->flags & ATA_QCFLAG_DMAMAP)
Tejun Heo12fad3f2006-05-15 21:03:55 +09001919 n_elem = ahci_fill_sg(qc, cmd_tbl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001920
Tejun Heocc9278e2006-02-10 17:25:47 +09001921 /*
1922 * Fill in command slot information.
1923 */
Tejun Heo7d50b602007-09-23 13:19:54 +09001924 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
Tejun Heocc9278e2006-02-10 17:25:47 +09001925 if (qc->tf.flags & ATA_TFLAG_WRITE)
1926 opts |= AHCI_CMD_WRITE;
1927 if (is_atapi)
Tejun Heo4b10e552006-03-12 11:25:27 +09001928 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
Jeff Garzik828d09d2005-11-12 01:27:07 -05001929
Tejun Heo12fad3f2006-05-15 21:03:55 +09001930 ahci_fill_cmd_slot(pp, qc->tag, opts);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001931}
1932
Tejun Heo78cd52d2006-05-15 20:58:29 +09001933static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001934{
Tejun Heo417a1a62007-09-23 13:19:55 +09001935 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001936 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09001937 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1938 struct ata_link *link = NULL;
1939 struct ata_queued_cmd *active_qc;
1940 struct ata_eh_info *active_ehi;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001941 u32 serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001942
Tejun Heo7d50b602007-09-23 13:19:54 +09001943 /* determine active link */
Tejun Heo1eca4362008-11-03 20:03:17 +09001944 ata_for_each_link(link, ap, EDGE)
Tejun Heo7d50b602007-09-23 13:19:54 +09001945 if (ata_link_active(link))
1946 break;
1947 if (!link)
1948 link = &ap->link;
1949
1950 active_qc = ata_qc_from_tag(ap, link->active_tag);
1951 active_ehi = &link->eh_info;
1952
1953 /* record irq stat */
1954 ata_ehi_clear_desc(host_ehi);
1955 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
Jeff Garzik9f68a242005-11-15 14:03:47 -05001956
Tejun Heo78cd52d2006-05-15 20:58:29 +09001957 /* AHCI needs SError cleared; otherwise, it might lock up */
Tejun Heo82ef04f2008-07-31 17:02:40 +09001958 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1959 ahci_scr_write(&ap->link, SCR_ERROR, serror);
Tejun Heo7d50b602007-09-23 13:19:54 +09001960 host_ehi->serror |= serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001961
Tejun Heo41669552006-11-29 11:33:14 +09001962 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
Tejun Heo417a1a62007-09-23 13:19:55 +09001963 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
Tejun Heo41669552006-11-29 11:33:14 +09001964 irq_stat &= ~PORT_IRQ_IF_ERR;
1965
Conke Hu55a61602007-03-27 18:33:05 +08001966 if (irq_stat & PORT_IRQ_TF_ERR) {
Tejun Heo7d50b602007-09-23 13:19:54 +09001967 /* If qc is active, charge it; otherwise, the active
1968 * link. There's no active qc on NCQ errors. It will
1969 * be determined by EH by reading log page 10h.
1970 */
1971 if (active_qc)
1972 active_qc->err_mask |= AC_ERR_DEV;
1973 else
1974 active_ehi->err_mask |= AC_ERR_DEV;
1975
Tejun Heo417a1a62007-09-23 13:19:55 +09001976 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
Tejun Heo7d50b602007-09-23 13:19:54 +09001977 host_ehi->serror &= ~SERR_INTERNAL;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001978 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001979
Tejun Heo78cd52d2006-05-15 20:58:29 +09001980 if (irq_stat & PORT_IRQ_UNK_FIS) {
1981 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001982
Tejun Heo7d50b602007-09-23 13:19:54 +09001983 active_ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09001984 active_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09001985 ata_ehi_push_desc(active_ehi,
1986 "unknown FIS %08x %08x %08x %08x" ,
Tejun Heo78cd52d2006-05-15 20:58:29 +09001987 unk[0], unk[1], unk[2], unk[3]);
1988 }
Jeff Garzikb8f61532005-08-25 22:01:20 -04001989
Tejun Heo071f44b2008-04-07 22:47:22 +09001990 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
Tejun Heo7d50b602007-09-23 13:19:54 +09001991 active_ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09001992 active_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09001993 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1994 }
Tejun Heo78cd52d2006-05-15 20:58:29 +09001995
Tejun Heo7d50b602007-09-23 13:19:54 +09001996 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1997 host_ehi->err_mask |= AC_ERR_HOST_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09001998 host_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09001999 ata_ehi_push_desc(host_ehi, "host bus error");
2000 }
2001
2002 if (irq_stat & PORT_IRQ_IF_ERR) {
2003 host_ehi->err_mask |= AC_ERR_ATA_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002004 host_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09002005 ata_ehi_push_desc(host_ehi, "interface fatal error");
2006 }
2007
2008 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
2009 ata_ehi_hotplugged(host_ehi);
2010 ata_ehi_push_desc(host_ehi, "%s",
2011 irq_stat & PORT_IRQ_CONNECT ?
2012 "connection status changed" : "PHY RDY changed");
2013 }
2014
2015 /* okay, let's hand over to EH */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002016
Tejun Heo78cd52d2006-05-15 20:58:29 +09002017 if (irq_stat & PORT_IRQ_FREEZE)
2018 ata_port_freeze(ap);
2019 else
2020 ata_port_abort(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002021}
2022
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002023static void ahci_port_intr(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002024{
Tejun Heo350756f2008-04-07 22:47:21 +09002025 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002026 struct ata_eh_info *ehi = &ap->link.eh_info;
Tejun Heo0291f952007-01-25 19:16:28 +09002027 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo5f226c62007-10-09 15:02:23 +09002028 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heob06ce3e2007-10-09 15:06:48 +09002029 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
Tejun Heo12fad3f2006-05-15 21:03:55 +09002030 u32 status, qc_active;
Tejun Heo459ad682007-12-07 12:46:23 +09002031 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002032
2033 status = readl(port_mmio + PORT_IRQ_STAT);
2034 writel(status, port_mmio + PORT_IRQ_STAT);
2035
Tejun Heob06ce3e2007-10-09 15:06:48 +09002036 /* ignore BAD_PMP while resetting */
2037 if (unlikely(resetting))
2038 status &= ~PORT_IRQ_BAD_PMP;
2039
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04002040 /* If we are getting PhyRdy, this is
2041 * just a power state change, we should
2042 * clear out this, plus the PhyRdy/Comm
2043 * Wake bits from Serror
2044 */
2045 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2046 (status & PORT_IRQ_PHYRDY)) {
2047 status &= ~PORT_IRQ_PHYRDY;
Tejun Heo82ef04f2008-07-31 17:02:40 +09002048 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04002049 }
2050
Tejun Heo78cd52d2006-05-15 20:58:29 +09002051 if (unlikely(status & PORT_IRQ_ERROR)) {
2052 ahci_error_intr(ap, status);
2053 return;
2054 }
2055
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04002056 if (status & PORT_IRQ_SDB_FIS) {
Tejun Heo5f226c62007-10-09 15:02:23 +09002057 /* If SNotification is available, leave notification
2058 * handling to sata_async_notification(). If not,
2059 * emulate it by snooping SDB FIS RX area.
2060 *
2061 * Snooping FIS RX area is probably cheaper than
2062 * poking SNotification but some constrollers which
2063 * implement SNotification, ICH9 for example, don't
2064 * store AN SDB FIS into receive area.
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04002065 */
Tejun Heo5f226c62007-10-09 15:02:23 +09002066 if (hpriv->cap & HOST_CAP_SNTF)
Tejun Heo7d77b242007-09-23 13:14:13 +09002067 sata_async_notification(ap);
Tejun Heo5f226c62007-10-09 15:02:23 +09002068 else {
2069 /* If the 'N' bit in word 0 of the FIS is set,
2070 * we just received asynchronous notification.
2071 * Tell libata about it.
2072 */
2073 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2074 u32 f0 = le32_to_cpu(f[0]);
2075
2076 if (f0 & (1 << 15))
2077 sata_async_notification(ap);
2078 }
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04002079 }
2080
Tejun Heo7d50b602007-09-23 13:19:54 +09002081 /* pp->active_link is valid iff any command is in flight */
2082 if (ap->qc_active && pp->active_link->sactive)
Tejun Heo12fad3f2006-05-15 21:03:55 +09002083 qc_active = readl(port_mmio + PORT_SCR_ACT);
2084 else
2085 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2086
Tejun Heo79f97da2008-04-07 22:47:20 +09002087 rc = ata_qc_complete_multiple(ap, qc_active);
Tejun Heob06ce3e2007-10-09 15:06:48 +09002088
Tejun Heo459ad682007-12-07 12:46:23 +09002089 /* while resetting, invalid completions are expected */
2090 if (unlikely(rc < 0 && !resetting)) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09002091 ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09002092 ehi->action |= ATA_EH_RESET;
Tejun Heo12fad3f2006-05-15 21:03:55 +09002093 ata_port_freeze(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002094 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002095}
2096
David Howells7d12e782006-10-05 14:55:46 +01002097static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002098{
Jeff Garzikcca39742006-08-24 03:19:22 -04002099 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002100 struct ahci_host_priv *hpriv;
2101 unsigned int i, handled = 0;
Jeff Garzikea6ba102005-08-30 05:18:18 -04002102 void __iomem *mmio;
Tejun Heod28f87a2008-07-05 13:10:50 +09002103 u32 irq_stat, irq_masked;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002104
2105 VPRINTK("ENTER\n");
2106
Jeff Garzikcca39742006-08-24 03:19:22 -04002107 hpriv = host->private_data;
Tejun Heo0d5ff562007-02-01 15:06:36 +09002108 mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002109
2110 /* sigh. 0xffffffff is a valid return from h/w */
2111 irq_stat = readl(mmio + HOST_IRQ_STAT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002112 if (!irq_stat)
2113 return IRQ_NONE;
2114
Tejun Heod28f87a2008-07-05 13:10:50 +09002115 irq_masked = irq_stat & hpriv->port_map;
2116
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002117 spin_lock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002118
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002119 for (i = 0; i < host->n_ports; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002120 struct ata_port *ap;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002121
Tejun Heod28f87a2008-07-05 13:10:50 +09002122 if (!(irq_masked & (1 << i)))
Jeff Garzik67846b32005-10-05 02:58:32 -04002123 continue;
2124
Jeff Garzikcca39742006-08-24 03:19:22 -04002125 ap = host->ports[i];
Jeff Garzik67846b32005-10-05 02:58:32 -04002126 if (ap) {
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002127 ahci_port_intr(ap);
Jeff Garzik67846b32005-10-05 02:58:32 -04002128 VPRINTK("port %u\n", i);
2129 } else {
2130 VPRINTK("port %u (no irq)\n", i);
Tejun Heo6971ed12006-03-11 12:47:54 +09002131 if (ata_ratelimit())
Jeff Garzikcca39742006-08-24 03:19:22 -04002132 dev_printk(KERN_WARNING, host->dev,
Jeff Garzika9524a72005-10-30 14:39:11 -05002133 "interrupt on disabled port %u\n", i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002134 }
Jeff Garzik67846b32005-10-05 02:58:32 -04002135
Linus Torvalds1da177e2005-04-16 15:20:36 -07002136 handled = 1;
2137 }
2138
Tejun Heod28f87a2008-07-05 13:10:50 +09002139 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2140 * it should be cleared after all the port events are cleared;
2141 * otherwise, it will raise a spurious interrupt after each
2142 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2143 * information.
2144 *
2145 * Also, use the unmasked value to clear interrupt as spurious
2146 * pending event on a dummy port might cause screaming IRQ.
2147 */
Tejun Heoea0c62f2008-06-28 01:49:02 +09002148 writel(irq_stat, mmio + HOST_IRQ_STAT);
2149
Jeff Garzikcca39742006-08-24 03:19:22 -04002150 spin_unlock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002151
2152 VPRINTK("EXIT\n");
2153
2154 return IRQ_RETVAL(handled);
2155}
2156
Tejun Heo9a3d9eb2006-01-23 13:09:36 +09002157static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002158{
2159 struct ata_port *ap = qc->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09002160 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7d50b602007-09-23 13:19:54 +09002161 struct ahci_port_priv *pp = ap->private_data;
2162
2163 /* Keep track of the currently active link. It will be used
2164 * in completion path to determine whether NCQ phase is in
2165 * progress.
2166 */
2167 pp->active_link = qc->dev->link;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002168
Tejun Heo12fad3f2006-05-15 21:03:55 +09002169 if (qc->tf.protocol == ATA_PROT_NCQ)
2170 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2171 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002172
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002173 ahci_sw_activity(qc->dev->link);
2174
Linus Torvalds1da177e2005-04-16 15:20:36 -07002175 return 0;
2176}
2177
Tejun Heo4c9bf4e2008-04-07 22:47:20 +09002178static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2179{
2180 struct ahci_port_priv *pp = qc->ap->private_data;
2181 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2182
2183 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2184 return true;
2185}
2186
Tejun Heo78cd52d2006-05-15 20:58:29 +09002187static void ahci_freeze(struct ata_port *ap)
2188{
Tejun Heo4447d352007-04-17 23:44:08 +09002189 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002190
2191 /* turn IRQ off */
2192 writel(0, port_mmio + PORT_IRQ_MASK);
2193}
2194
2195static void ahci_thaw(struct ata_port *ap)
2196{
Tejun Heo0d5ff562007-02-01 15:06:36 +09002197 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
Tejun Heo4447d352007-04-17 23:44:08 +09002198 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002199 u32 tmp;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002200 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09002201
2202 /* clear IRQ */
2203 tmp = readl(port_mmio + PORT_IRQ_STAT);
2204 writel(tmp, port_mmio + PORT_IRQ_STAT);
Tejun Heoa7187282007-01-27 11:04:26 +09002205 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002206
Tejun Heo1c954a42007-10-09 15:01:37 +09002207 /* turn IRQ back on */
2208 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002209}
2210
2211static void ahci_error_handler(struct ata_port *ap)
2212{
Tejun Heob51e9e52006-06-29 01:29:30 +09002213 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
Tejun Heo78cd52d2006-05-15 20:58:29 +09002214 /* restart engine */
Tejun Heo4447d352007-04-17 23:44:08 +09002215 ahci_stop_engine(ap);
2216 ahci_start_engine(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002217 }
2218
Tejun Heoa1efdab2008-03-25 12:22:50 +09002219 sata_pmp_error_handler(ap);
Tejun Heoedc93052007-10-25 14:59:16 +09002220}
2221
Tejun Heo78cd52d2006-05-15 20:58:29 +09002222static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2223{
2224 struct ata_port *ap = qc->ap;
2225
Tejun Heod2e75df2007-07-16 14:29:39 +09002226 /* make DMA engine forget about the failed command */
2227 if (qc->flags & ATA_QCFLAG_FAILED)
2228 ahci_kick_engine(ap, 1);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002229}
2230
Tejun Heo7d50b602007-09-23 13:19:54 +09002231static void ahci_pmp_attach(struct ata_port *ap)
2232{
2233 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo1c954a42007-10-09 15:01:37 +09002234 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09002235 u32 cmd;
2236
2237 cmd = readl(port_mmio + PORT_CMD);
2238 cmd |= PORT_CMD_PMP;
2239 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo1c954a42007-10-09 15:01:37 +09002240
2241 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2242 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo7d50b602007-09-23 13:19:54 +09002243}
2244
2245static void ahci_pmp_detach(struct ata_port *ap)
2246{
2247 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo1c954a42007-10-09 15:01:37 +09002248 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09002249 u32 cmd;
2250
2251 cmd = readl(port_mmio + PORT_CMD);
2252 cmd &= ~PORT_CMD_PMP;
2253 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo1c954a42007-10-09 15:01:37 +09002254
2255 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2256 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo7d50b602007-09-23 13:19:54 +09002257}
2258
Alexey Dobriyan028a2592007-07-17 23:48:48 +04002259static int ahci_port_resume(struct ata_port *ap)
2260{
2261 ahci_power_up(ap);
2262 ahci_start_port(ap);
2263
Tejun Heo071f44b2008-04-07 22:47:22 +09002264 if (sata_pmp_attached(ap))
Tejun Heo7d50b602007-09-23 13:19:54 +09002265 ahci_pmp_attach(ap);
2266 else
2267 ahci_pmp_detach(ap);
2268
Alexey Dobriyan028a2592007-07-17 23:48:48 +04002269 return 0;
2270}
2271
Tejun Heo438ac6d2007-03-02 17:31:26 +09002272#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +09002273static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2274{
Tejun Heoc1332872006-07-26 15:59:26 +09002275 const char *emsg = NULL;
2276 int rc;
2277
Tejun Heo4447d352007-04-17 23:44:08 +09002278 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo8e16f942006-11-20 15:42:36 +09002279 if (rc == 0)
Tejun Heo4447d352007-04-17 23:44:08 +09002280 ahci_power_down(ap);
Tejun Heo8e16f942006-11-20 15:42:36 +09002281 else {
Tejun Heoc1332872006-07-26 15:59:26 +09002282 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002283 ahci_start_port(ap);
Tejun Heoc1332872006-07-26 15:59:26 +09002284 }
2285
2286 return rc;
2287}
2288
Tejun Heoc1332872006-07-26 15:59:26 +09002289static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2290{
Jeff Garzikcca39742006-08-24 03:19:22 -04002291 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09002292 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heoc1332872006-07-26 15:59:26 +09002293 u32 ctl;
2294
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +01002295 if (mesg.event & PM_EVENT_SLEEP) {
Tejun Heoc1332872006-07-26 15:59:26 +09002296 /* AHCI spec rev1.1 section 8.3.3:
2297 * Software must disable interrupts prior to requesting a
2298 * transition of the HBA to D3 state.
2299 */
2300 ctl = readl(mmio + HOST_CTL);
2301 ctl &= ~HOST_IRQ_EN;
2302 writel(ctl, mmio + HOST_CTL);
2303 readl(mmio + HOST_CTL); /* flush */
2304 }
2305
2306 return ata_pci_device_suspend(pdev, mesg);
2307}
2308
2309static int ahci_pci_device_resume(struct pci_dev *pdev)
2310{
Jeff Garzikcca39742006-08-24 03:19:22 -04002311 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heoc1332872006-07-26 15:59:26 +09002312 int rc;
2313
Tejun Heo553c4aa2006-12-26 19:39:50 +09002314 rc = ata_pci_device_do_resume(pdev);
2315 if (rc)
2316 return rc;
Tejun Heoc1332872006-07-26 15:59:26 +09002317
2318 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Tejun Heo4447d352007-04-17 23:44:08 +09002319 rc = ahci_reset_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002320 if (rc)
2321 return rc;
2322
Tejun Heo4447d352007-04-17 23:44:08 +09002323 ahci_init_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002324 }
2325
Jeff Garzikcca39742006-08-24 03:19:22 -04002326 ata_host_resume(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002327
2328 return 0;
2329}
Tejun Heo438ac6d2007-03-02 17:31:26 +09002330#endif
Tejun Heoc1332872006-07-26 15:59:26 +09002331
Tejun Heo254950c2006-07-26 15:59:25 +09002332static int ahci_port_start(struct ata_port *ap)
2333{
Jeff Garzikcca39742006-08-24 03:19:22 -04002334 struct device *dev = ap->host->dev;
Tejun Heo254950c2006-07-26 15:59:25 +09002335 struct ahci_port_priv *pp;
Tejun Heo254950c2006-07-26 15:59:25 +09002336 void *mem;
2337 dma_addr_t mem_dma;
Tejun Heo254950c2006-07-26 15:59:25 +09002338
Tejun Heo24dc5f32007-01-20 16:00:28 +09002339 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Tejun Heo254950c2006-07-26 15:59:25 +09002340 if (!pp)
2341 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09002342
Tejun Heo24dc5f32007-01-20 16:00:28 +09002343 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2344 GFP_KERNEL);
2345 if (!mem)
Tejun Heo254950c2006-07-26 15:59:25 +09002346 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09002347 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2348
2349 /*
2350 * First item in chunk of DMA memory: 32-slot command table,
2351 * 32 bytes each in size
2352 */
2353 pp->cmd_slot = mem;
2354 pp->cmd_slot_dma = mem_dma;
2355
2356 mem += AHCI_CMD_SLOT_SZ;
2357 mem_dma += AHCI_CMD_SLOT_SZ;
2358
2359 /*
2360 * Second item: Received-FIS area
2361 */
2362 pp->rx_fis = mem;
2363 pp->rx_fis_dma = mem_dma;
2364
2365 mem += AHCI_RX_FIS_SZ;
2366 mem_dma += AHCI_RX_FIS_SZ;
2367
2368 /*
2369 * Third item: data area for storing a single command
2370 * and its scatter-gather table
2371 */
2372 pp->cmd_tbl = mem;
2373 pp->cmd_tbl_dma = mem_dma;
2374
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002375 /*
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002376 * Save off initial list of interrupts to be enabled.
2377 * This could be changed later
2378 */
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002379 pp->intr_mask = DEF_PORT_IRQ;
2380
Tejun Heo254950c2006-07-26 15:59:25 +09002381 ap->private_data = pp;
2382
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002383 /* engage engines, captain */
2384 return ahci_port_resume(ap);
Tejun Heo254950c2006-07-26 15:59:25 +09002385}
2386
2387static void ahci_port_stop(struct ata_port *ap)
2388{
Tejun Heo0be0aa92006-07-26 15:59:26 +09002389 const char *emsg = NULL;
2390 int rc;
Tejun Heo254950c2006-07-26 15:59:25 +09002391
Tejun Heo0be0aa92006-07-26 15:59:26 +09002392 /* de-initialize port */
Tejun Heo4447d352007-04-17 23:44:08 +09002393 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo0be0aa92006-07-26 15:59:26 +09002394 if (rc)
2395 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
Tejun Heo254950c2006-07-26 15:59:25 +09002396}
2397
Tejun Heo4447d352007-04-17 23:44:08 +09002398static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002399{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002400 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002401
Linus Torvalds1da177e2005-04-16 15:20:36 -07002402 if (using_dac &&
2403 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2404 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2405 if (rc) {
2406 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2407 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002408 dev_printk(KERN_ERR, &pdev->dev,
2409 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002410 return rc;
2411 }
2412 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002413 } else {
2414 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2415 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002416 dev_printk(KERN_ERR, &pdev->dev,
2417 "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002418 return rc;
2419 }
2420 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2421 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002422 dev_printk(KERN_ERR, &pdev->dev,
2423 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002424 return rc;
2425 }
2426 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002427 return 0;
2428}
2429
Tejun Heo4447d352007-04-17 23:44:08 +09002430static void ahci_print_info(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002431{
Tejun Heo4447d352007-04-17 23:44:08 +09002432 struct ahci_host_priv *hpriv = host->private_data;
2433 struct pci_dev *pdev = to_pci_dev(host->dev);
2434 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002435 u32 vers, cap, impl, speed;
2436 const char *speed_s;
2437 u16 cc;
2438 const char *scc_s;
2439
2440 vers = readl(mmio + HOST_VERSION);
2441 cap = hpriv->cap;
2442 impl = hpriv->port_map;
2443
2444 speed = (cap >> 20) & 0xf;
2445 if (speed == 1)
2446 speed_s = "1.5";
2447 else if (speed == 2)
2448 speed_s = "3";
2449 else
2450 speed_s = "?";
2451
2452 pci_read_config_word(pdev, 0x0a, &cc);
Conke Huc9f89472007-01-09 05:32:51 -05002453 if (cc == PCI_CLASS_STORAGE_IDE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002454 scc_s = "IDE";
Conke Huc9f89472007-01-09 05:32:51 -05002455 else if (cc == PCI_CLASS_STORAGE_SATA)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002456 scc_s = "SATA";
Conke Huc9f89472007-01-09 05:32:51 -05002457 else if (cc == PCI_CLASS_STORAGE_RAID)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002458 scc_s = "RAID";
2459 else
2460 scc_s = "unknown";
2461
Jeff Garzika9524a72005-10-30 14:39:11 -05002462 dev_printk(KERN_INFO, &pdev->dev,
2463 "AHCI %02x%02x.%02x%02x "
Linus Torvalds1da177e2005-04-16 15:20:36 -07002464 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002465 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002466
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002467 (vers >> 24) & 0xff,
2468 (vers >> 16) & 0xff,
2469 (vers >> 8) & 0xff,
2470 vers & 0xff,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002471
2472 ((cap >> 8) & 0x1f) + 1,
2473 (cap & 0x1f) + 1,
2474 speed_s,
2475 impl,
2476 scc_s);
2477
Jeff Garzika9524a72005-10-30 14:39:11 -05002478 dev_printk(KERN_INFO, &pdev->dev,
2479 "flags: "
Tejun Heo203ef6c2007-07-16 14:29:40 +09002480 "%s%s%s%s%s%s%s"
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002481 "%s%s%s%s%s%s%s"
2482 "%s\n"
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002483 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002484
2485 cap & (1 << 31) ? "64bit " : "",
2486 cap & (1 << 30) ? "ncq " : "",
Tejun Heo203ef6c2007-07-16 14:29:40 +09002487 cap & (1 << 29) ? "sntf " : "",
Linus Torvalds1da177e2005-04-16 15:20:36 -07002488 cap & (1 << 28) ? "ilck " : "",
2489 cap & (1 << 27) ? "stag " : "",
2490 cap & (1 << 26) ? "pm " : "",
2491 cap & (1 << 25) ? "led " : "",
2492
2493 cap & (1 << 24) ? "clo " : "",
2494 cap & (1 << 19) ? "nz " : "",
2495 cap & (1 << 18) ? "only " : "",
2496 cap & (1 << 17) ? "pmp " : "",
2497 cap & (1 << 15) ? "pio " : "",
2498 cap & (1 << 14) ? "slum " : "",
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002499 cap & (1 << 13) ? "part " : "",
2500 cap & (1 << 6) ? "ems ": ""
Linus Torvalds1da177e2005-04-16 15:20:36 -07002501 );
2502}
2503
Tejun Heoedc93052007-10-25 14:59:16 +09002504/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2505 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2506 * support PMP and the 4726 either directly exports the device
2507 * attached to the first downstream port or acts as a hardware storage
2508 * controller and emulate a single ATA device (can be RAID 0/1 or some
2509 * other configuration).
2510 *
2511 * When there's no device attached to the first downstream port of the
2512 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2513 * configure the 4726. However, ATA emulation of the device is very
2514 * lame. It doesn't send signature D2H Reg FIS after the initial
2515 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2516 *
2517 * The following function works around the problem by always using
2518 * hardreset on the port and not depending on receiving signature FIS
2519 * afterward. If signature FIS isn't received soon, ATA class is
2520 * assumed without follow-up softreset.
2521 */
2522static void ahci_p5wdh_workaround(struct ata_host *host)
2523{
2524 static struct dmi_system_id sysids[] = {
2525 {
2526 .ident = "P5W DH Deluxe",
2527 .matches = {
2528 DMI_MATCH(DMI_SYS_VENDOR,
2529 "ASUSTEK COMPUTER INC"),
2530 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2531 },
2532 },
2533 { }
2534 };
2535 struct pci_dev *pdev = to_pci_dev(host->dev);
2536
2537 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2538 dmi_check_system(sysids)) {
2539 struct ata_port *ap = host->ports[1];
2540
2541 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2542 "Deluxe on-board SIMG4726 workaround\n");
2543
2544 ap->ops = &ahci_p5wdh_ops;
2545 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2546 }
2547}
2548
Tejun Heo24dc5f32007-01-20 16:00:28 +09002549static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002550{
2551 static int printed_version;
Tejun Heoe297d992008-06-10 00:13:04 +09002552 unsigned int board_id = ent->driver_data;
2553 struct ata_port_info pi = ahci_port_info[board_id];
Tejun Heo4447d352007-04-17 23:44:08 +09002554 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo24dc5f32007-01-20 16:00:28 +09002555 struct device *dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002556 struct ahci_host_priv *hpriv;
Tejun Heo4447d352007-04-17 23:44:08 +09002557 struct ata_host *host;
Tejun Heo837f5f82008-02-06 15:13:51 +09002558 int n_ports, i, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002559
2560 VPRINTK("ENTER\n");
2561
Tejun Heo12fad3f2006-05-15 21:03:55 +09002562 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2563
Linus Torvalds1da177e2005-04-16 15:20:36 -07002564 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05002565 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002566
Alan Cox5b66c822008-09-03 14:48:34 +01002567 /* The AHCI driver can only drive the SATA ports, the PATA driver
2568 can drive them all so if both drivers are selected make sure
2569 AHCI stays out of the way */
2570 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
2571 return -ENODEV;
2572
Tejun Heo4447d352007-04-17 23:44:08 +09002573 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09002574 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002575 if (rc)
2576 return rc;
2577
Tejun Heodea55132008-03-11 19:52:31 +09002578 /* AHCI controllers often implement SFF compatible interface.
2579 * Grab all PCI BARs just in case.
2580 */
2581 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
Tejun Heo0d5ff562007-02-01 15:06:36 +09002582 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002583 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09002584 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002585 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002586
Tejun Heoc4f77922007-12-06 15:09:43 +09002587 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2588 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2589 u8 map;
2590
2591 /* ICH6s share the same PCI ID for both piix and ahci
2592 * modes. Enabling ahci mode while MAP indicates
2593 * combined mode is a bad idea. Yield to ata_piix.
2594 */
2595 pci_read_config_byte(pdev, ICH_MAP, &map);
2596 if (map & 0x3) {
2597 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2598 "combined mode, can't enable AHCI mode\n");
2599 return -ENODEV;
2600 }
2601 }
2602
Tejun Heo24dc5f32007-01-20 16:00:28 +09002603 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2604 if (!hpriv)
2605 return -ENOMEM;
Tejun Heo417a1a62007-09-23 13:19:55 +09002606 hpriv->flags |= (unsigned long)pi.private_data;
2607
Tejun Heoe297d992008-06-10 00:13:04 +09002608 /* MCP65 revision A1 and A2 can't do MSI */
2609 if (board_id == board_ahci_mcp65 &&
2610 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2611 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2612
Tejun Heo417a1a62007-09-23 13:19:55 +09002613 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2614 pci_intx(pdev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002615
Tejun Heo4447d352007-04-17 23:44:08 +09002616 /* save initial config */
Tejun Heo417a1a62007-09-23 13:19:55 +09002617 ahci_save_initial_config(pdev, hpriv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002618
Tejun Heo4447d352007-04-17 23:44:08 +09002619 /* prepare host */
Tejun Heo274c1fd2007-07-16 14:29:40 +09002620 if (hpriv->cap & HOST_CAP_NCQ)
Tejun Heo4447d352007-04-17 23:44:08 +09002621 pi.flags |= ATA_FLAG_NCQ;
2622
Tejun Heo7d50b602007-09-23 13:19:54 +09002623 if (hpriv->cap & HOST_CAP_PMP)
2624 pi.flags |= ATA_FLAG_PMP;
2625
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002626 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
2627 u8 messages;
2628 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
2629 u32 em_loc = readl(mmio + HOST_EM_LOC);
2630 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2631
David Milburn87943ac2008-10-13 14:38:36 -05002632 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002633
2634 /* we only support LED message type right now */
2635 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2636 /* store em_loc */
2637 hpriv->em_loc = ((em_loc >> 16) * 4);
2638 pi.flags |= ATA_FLAG_EM;
2639 if (!(em_ctl & EM_CTL_ALHD))
2640 pi.flags |= ATA_FLAG_SW_ACTIVITY;
2641 }
2642 }
2643
Tejun Heo837f5f82008-02-06 15:13:51 +09002644 /* CAP.NP sometimes indicate the index of the last enabled
2645 * port, at other times, that of the last possible port, so
2646 * determining the maximum port number requires looking at
2647 * both CAP.NP and port_map.
2648 */
2649 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2650
2651 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
Tejun Heo4447d352007-04-17 23:44:08 +09002652 if (!host)
2653 return -ENOMEM;
2654 host->iomap = pcim_iomap_table(pdev);
2655 host->private_data = hpriv;
2656
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002657 if (pi.flags & ATA_FLAG_EM)
2658 ahci_reset_em(host);
2659
Tejun Heo4447d352007-04-17 23:44:08 +09002660 for (i = 0; i < host->n_ports; i++) {
Jeff Garzikdab632e2007-05-28 08:33:01 -04002661 struct ata_port *ap = host->ports[i];
Tejun Heo4447d352007-04-17 23:44:08 +09002662
Tejun Heocbcdd872007-08-18 13:14:55 +09002663 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2664 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2665 0x100 + ap->port_no * 0x80, "port");
2666
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04002667 /* set initial link pm policy */
2668 ap->pm_policy = NOT_AVAILABLE;
2669
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002670 /* set enclosure management message type */
2671 if (ap->flags & ATA_FLAG_EM)
2672 ap->em_message_type = ahci_em_messages;
2673
2674
Jeff Garzikdab632e2007-05-28 08:33:01 -04002675 /* disabled/not-implemented port */
Tejun Heo350756f2008-04-07 22:47:21 +09002676 if (!(hpriv->port_map & (1 << i)))
Jeff Garzikdab632e2007-05-28 08:33:01 -04002677 ap->ops = &ata_dummy_port_ops;
Tejun Heo4447d352007-04-17 23:44:08 +09002678 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002679
Tejun Heoedc93052007-10-25 14:59:16 +09002680 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2681 ahci_p5wdh_workaround(host);
2682
Linus Torvalds1da177e2005-04-16 15:20:36 -07002683 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09002684 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002685 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002686 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002687
Tejun Heo4447d352007-04-17 23:44:08 +09002688 rc = ahci_reset_controller(host);
2689 if (rc)
2690 return rc;
Tejun Heo12fad3f2006-05-15 21:03:55 +09002691
Tejun Heo4447d352007-04-17 23:44:08 +09002692 ahci_init_controller(host);
2693 ahci_print_info(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002694
Tejun Heo4447d352007-04-17 23:44:08 +09002695 pci_set_master(pdev);
2696 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2697 &ahci_sht);
Jeff Garzik907f4672005-05-12 15:03:42 -04002698}
Linus Torvalds1da177e2005-04-16 15:20:36 -07002699
2700static int __init ahci_init(void)
2701{
Pavel Roskinb7887192006-08-10 18:13:18 +09002702 return pci_register_driver(&ahci_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002703}
2704
Linus Torvalds1da177e2005-04-16 15:20:36 -07002705static void __exit ahci_exit(void)
2706{
2707 pci_unregister_driver(&ahci_pci_driver);
2708}
2709
2710
2711MODULE_AUTHOR("Jeff Garzik");
2712MODULE_DESCRIPTION("AHCI SATA low-level driver");
2713MODULE_LICENSE("GPL");
2714MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04002715MODULE_VERSION(DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002716
2717module_init(ahci_init);
2718module_exit(ahci_exit);