Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 1 | //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 10 | // This file implements the PPCISelLowering class. |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Chris Lattner | 16e71f2 | 2005-10-14 23:59:06 +0000 | [diff] [blame] | 14 | #include "PPCISelLowering.h" |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 15 | #include "PPCMachineFunctionInfo.h" |
Chris Lattner | df4ed63 | 2006-11-17 22:10:59 +0000 | [diff] [blame] | 16 | #include "PPCPredicates.h" |
Chris Lattner | 16e71f2 | 2005-10-14 23:59:06 +0000 | [diff] [blame] | 17 | #include "PPCTargetMachine.h" |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 18 | #include "PPCPerfectShuffle.h" |
Owen Anderson | 718cb66 | 2007-09-07 04:06:50 +0000 | [diff] [blame] | 19 | #include "llvm/ADT/STLExtras.h" |
Nate Begeman | 750ac1b | 2006-02-01 07:19:44 +0000 | [diff] [blame] | 20 | #include "llvm/ADT/VectorExtras.h" |
Evan Cheng | c4c6257 | 2006-03-13 23:20:37 +0000 | [diff] [blame] | 21 | #include "llvm/Analysis/ScalarEvolutionExpressions.h" |
Chris Lattner | b9a7bea | 2007-03-06 00:59:59 +0000 | [diff] [blame] | 22 | #include "llvm/CodeGen/CallingConvLower.h" |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 23 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 24 | #include "llvm/CodeGen/MachineFunction.h" |
Chris Lattner | 8a2d3ca | 2005-08-26 21:23:58 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 26 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 27 | #include "llvm/CodeGen/PseudoSourceValue.h" |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 28 | #include "llvm/CodeGen/SelectionDAG.h" |
Chris Lattner | 0b1e4e5 | 2005-08-26 17:36:52 +0000 | [diff] [blame] | 29 | #include "llvm/Constants.h" |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 30 | #include "llvm/Function.h" |
Chris Lattner | 6d92cad | 2006-03-26 10:06:40 +0000 | [diff] [blame] | 31 | #include "llvm/Intrinsics.h" |
Nate Begeman | 750ac1b | 2006-02-01 07:19:44 +0000 | [diff] [blame] | 32 | #include "llvm/Support/MathExtras.h" |
Evan Cheng | d2ee218 | 2006-02-18 00:08:58 +0000 | [diff] [blame] | 33 | #include "llvm/Target/TargetOptions.h" |
Chris Lattner | 4eab714 | 2006-11-10 02:08:47 +0000 | [diff] [blame] | 34 | #include "llvm/Support/CommandLine.h" |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 35 | using namespace llvm; |
| 36 | |
Chris Lattner | 3ee7740 | 2007-06-19 05:46:06 +0000 | [diff] [blame] | 37 | static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", |
| 38 | cl::desc("enable preincrement load/store generation on PPC (experimental)"), |
| 39 | cl::Hidden); |
Chris Lattner | 4eab714 | 2006-11-10 02:08:47 +0000 | [diff] [blame] | 40 | |
Chris Lattner | 331d1bc | 2006-11-02 01:44:04 +0000 | [diff] [blame] | 41 | PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) |
Evan Cheng | 54fc97d | 2008-04-19 01:30:48 +0000 | [diff] [blame] | 42 | : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()), |
| 43 | PPCAtomicLabelIndex(0) { |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 44 | |
Nate Begeman | 405e3ec | 2005-10-21 00:02:42 +0000 | [diff] [blame] | 45 | setPow2DivIsCheap(); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 46 | |
Chris Lattner | d145a61 | 2005-09-27 22:18:25 +0000 | [diff] [blame] | 47 | // Use _setjmp/_longjmp instead of setjmp/longjmp. |
Anton Korobeynikov | d27a258 | 2006-12-10 23:12:42 +0000 | [diff] [blame] | 48 | setUseUnderscoreSetJmp(true); |
| 49 | setUseUnderscoreLongJmp(true); |
Chris Lattner | d145a61 | 2005-09-27 22:18:25 +0000 | [diff] [blame] | 50 | |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 51 | // Set up the register classes. |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 52 | addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); |
| 53 | addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); |
| 54 | addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 55 | |
Evan Cheng | c548428 | 2006-10-04 00:56:09 +0000 | [diff] [blame] | 56 | // PowerPC has an i16 but no i8 (or i1) SEXTLOAD |
Duncan Sands | f9c98e6 | 2008-01-23 20:39:46 +0000 | [diff] [blame] | 57 | setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); |
Evan Cheng | c548428 | 2006-10-04 00:56:09 +0000 | [diff] [blame] | 58 | setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); |
Duncan Sands | f9c98e6 | 2008-01-23 20:39:46 +0000 | [diff] [blame] | 59 | |
Chris Lattner | ddf8956 | 2008-01-17 19:59:44 +0000 | [diff] [blame] | 60 | setTruncStoreAction(MVT::f64, MVT::f32, Expand); |
| 61 | |
Chris Lattner | 94e509c | 2006-11-10 23:58:45 +0000 | [diff] [blame] | 62 | // PowerPC has pre-inc load and store's. |
| 63 | setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); |
| 64 | setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); |
| 65 | setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); |
Evan Cheng | cd63319 | 2006-11-09 19:11:50 +0000 | [diff] [blame] | 66 | setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); |
| 67 | setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); |
Chris Lattner | 94e509c | 2006-11-10 23:58:45 +0000 | [diff] [blame] | 68 | setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); |
| 69 | setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); |
| 70 | setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); |
Evan Cheng | cd63319 | 2006-11-09 19:11:50 +0000 | [diff] [blame] | 71 | setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); |
| 72 | setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); |
| 73 | |
Dale Johannesen | 638ccd5 | 2007-10-06 01:24:11 +0000 | [diff] [blame] | 74 | // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg) |
| 75 | setConvertAction(MVT::ppcf128, MVT::f64, Expand); |
| 76 | setConvertAction(MVT::ppcf128, MVT::f32, Expand); |
Dale Johannesen | 6eaeff2 | 2007-10-10 01:01:31 +0000 | [diff] [blame] | 77 | // This is used in the ppcf128->int sequence. Note it has different semantics |
| 78 | // from FP_ROUND: that rounds to nearest, this rounds to zero. |
| 79 | setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); |
Dale Johannesen | 638ccd5 | 2007-10-06 01:24:11 +0000 | [diff] [blame] | 80 | |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 81 | // PowerPC has no intrinsics for these particular operations |
Andrew Lenharth | d497d9f | 2008-02-16 14:46:26 +0000 | [diff] [blame] | 82 | setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); |
| 83 | |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 84 | // PowerPC has no SREM/UREM instructions |
| 85 | setOperationAction(ISD::SREM, MVT::i32, Expand); |
| 86 | setOperationAction(ISD::UREM, MVT::i32, Expand); |
Chris Lattner | 563ecfb | 2006-06-27 18:18:41 +0000 | [diff] [blame] | 87 | setOperationAction(ISD::SREM, MVT::i64, Expand); |
| 88 | setOperationAction(ISD::UREM, MVT::i64, Expand); |
Dan Gohman | 3ce990d | 2007-10-08 17:28:24 +0000 | [diff] [blame] | 89 | |
| 90 | // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. |
| 91 | setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); |
| 92 | setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); |
| 93 | setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); |
| 94 | setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); |
| 95 | setOperationAction(ISD::UDIVREM, MVT::i32, Expand); |
| 96 | setOperationAction(ISD::SDIVREM, MVT::i32, Expand); |
| 97 | setOperationAction(ISD::UDIVREM, MVT::i64, Expand); |
| 98 | setOperationAction(ISD::SDIVREM, MVT::i64, Expand); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 99 | |
Dan Gohman | f96e4de | 2007-10-11 23:21:31 +0000 | [diff] [blame] | 100 | // We don't support sin/cos/sqrt/fmod/pow |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 101 | setOperationAction(ISD::FSIN , MVT::f64, Expand); |
| 102 | setOperationAction(ISD::FCOS , MVT::f64, Expand); |
Chris Lattner | 615c2d0 | 2005-09-28 22:29:58 +0000 | [diff] [blame] | 103 | setOperationAction(ISD::FREM , MVT::f64, Expand); |
Dan Gohman | f96e4de | 2007-10-11 23:21:31 +0000 | [diff] [blame] | 104 | setOperationAction(ISD::FPOW , MVT::f64, Expand); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 105 | setOperationAction(ISD::FSIN , MVT::f32, Expand); |
| 106 | setOperationAction(ISD::FCOS , MVT::f32, Expand); |
Chris Lattner | 615c2d0 | 2005-09-28 22:29:58 +0000 | [diff] [blame] | 107 | setOperationAction(ISD::FREM , MVT::f32, Expand); |
Dan Gohman | f96e4de | 2007-10-11 23:21:31 +0000 | [diff] [blame] | 108 | setOperationAction(ISD::FPOW , MVT::f32, Expand); |
Dale Johannesen | 5c5eb80 | 2008-01-18 19:55:37 +0000 | [diff] [blame] | 109 | |
Dan Gohman | 1a02486 | 2008-01-31 00:41:03 +0000 | [diff] [blame] | 110 | setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 111 | |
| 112 | // If we're enabling GP optimizations, use hardware square root |
Chris Lattner | 1e9de3e | 2005-09-02 18:33:05 +0000 | [diff] [blame] | 113 | if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 114 | setOperationAction(ISD::FSQRT, MVT::f64, Expand); |
| 115 | setOperationAction(ISD::FSQRT, MVT::f32, Expand); |
| 116 | } |
| 117 | |
Chris Lattner | 9601a86 | 2006-03-05 05:08:37 +0000 | [diff] [blame] | 118 | setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); |
| 119 | setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); |
| 120 | |
Nate Begeman | d88fc03 | 2006-01-14 03:14:10 +0000 | [diff] [blame] | 121 | // PowerPC does not have BSWAP, CTPOP or CTTZ |
| 122 | setOperationAction(ISD::BSWAP, MVT::i32 , Expand); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 123 | setOperationAction(ISD::CTPOP, MVT::i32 , Expand); |
| 124 | setOperationAction(ISD::CTTZ , MVT::i32 , Expand); |
Chris Lattner | f89437d | 2006-06-27 20:14:52 +0000 | [diff] [blame] | 125 | setOperationAction(ISD::BSWAP, MVT::i64 , Expand); |
| 126 | setOperationAction(ISD::CTPOP, MVT::i64 , Expand); |
| 127 | setOperationAction(ISD::CTTZ , MVT::i64 , Expand); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 128 | |
Nate Begeman | 35ef913 | 2006-01-11 21:21:00 +0000 | [diff] [blame] | 129 | // PowerPC does not have ROTR |
| 130 | setOperationAction(ISD::ROTR, MVT::i32 , Expand); |
| 131 | |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 132 | // PowerPC does not have Select |
| 133 | setOperationAction(ISD::SELECT, MVT::i32, Expand); |
Chris Lattner | f89437d | 2006-06-27 20:14:52 +0000 | [diff] [blame] | 134 | setOperationAction(ISD::SELECT, MVT::i64, Expand); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 135 | setOperationAction(ISD::SELECT, MVT::f32, Expand); |
| 136 | setOperationAction(ISD::SELECT, MVT::f64, Expand); |
Chris Lattner | e4bc9ea | 2005-08-26 00:52:45 +0000 | [diff] [blame] | 137 | |
Chris Lattner | 0b1e4e5 | 2005-08-26 17:36:52 +0000 | [diff] [blame] | 138 | // PowerPC wants to turn select_cc of FP into fsel when possible. |
| 139 | setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); |
| 140 | setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); |
Nate Begeman | 4477590 | 2006-01-31 08:17:29 +0000 | [diff] [blame] | 141 | |
Nate Begeman | 750ac1b | 2006-02-01 07:19:44 +0000 | [diff] [blame] | 142 | // PowerPC wants to optimize integer setcc a bit |
Nate Begeman | 4477590 | 2006-01-31 08:17:29 +0000 | [diff] [blame] | 143 | setOperationAction(ISD::SETCC, MVT::i32, Custom); |
Chris Lattner | eb9b62e | 2005-08-31 19:09:57 +0000 | [diff] [blame] | 144 | |
Nate Begeman | 81e8097 | 2006-03-17 01:40:33 +0000 | [diff] [blame] | 145 | // PowerPC does not have BRCOND which requires SetCC |
| 146 | setOperationAction(ISD::BRCOND, MVT::Other, Expand); |
Evan Cheng | c35497f | 2006-10-30 08:02:39 +0000 | [diff] [blame] | 147 | |
| 148 | setOperationAction(ISD::BR_JT, MVT::Other, Expand); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 149 | |
Chris Lattner | f760532 | 2005-08-31 21:09:52 +0000 | [diff] [blame] | 150 | // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. |
| 151 | setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); |
Nate Begeman | c09eeec | 2005-09-06 22:03:27 +0000 | [diff] [blame] | 152 | |
Jim Laskey | ad23c9d | 2005-08-17 00:40:22 +0000 | [diff] [blame] | 153 | // PowerPC does not have [U|S]INT_TO_FP |
| 154 | setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); |
| 155 | setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); |
| 156 | |
Chris Lattner | 53e8845 | 2005-12-23 05:13:35 +0000 | [diff] [blame] | 157 | setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); |
| 158 | setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); |
Chris Lattner | 5f9faea | 2006-06-27 18:40:08 +0000 | [diff] [blame] | 159 | setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); |
| 160 | setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); |
Chris Lattner | 53e8845 | 2005-12-23 05:13:35 +0000 | [diff] [blame] | 161 | |
Chris Lattner | 25b8b8c | 2006-04-28 21:56:10 +0000 | [diff] [blame] | 162 | // We cannot sextinreg(i1). Expand to shifts. |
| 163 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); |
Jim Laskey | 2ad9f17 | 2007-02-22 14:56:36 +0000 | [diff] [blame] | 164 | |
Jim Laskey | abf6d17 | 2006-01-05 01:25:28 +0000 | [diff] [blame] | 165 | // Support label based line numbers. |
Chris Lattner | f73bae1 | 2005-11-29 06:16:21 +0000 | [diff] [blame] | 166 | setOperationAction(ISD::LOCATION, MVT::Other, Expand); |
Jim Laskey | e0bce71 | 2006-01-05 01:47:43 +0000 | [diff] [blame] | 167 | setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); |
Nicolas Geoffray | 616585b | 2007-12-21 12:19:44 +0000 | [diff] [blame] | 168 | |
| 169 | setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); |
| 170 | setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); |
| 171 | setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); |
| 172 | setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); |
| 173 | |
Chris Lattner | e6ec9f2 | 2005-09-10 00:21:06 +0000 | [diff] [blame] | 174 | |
Nate Begeman | 28a6b02 | 2005-12-10 02:36:00 +0000 | [diff] [blame] | 175 | // We want to legalize GlobalAddress and ConstantPool nodes into the |
| 176 | // appropriate instructions to materialize the address. |
Chris Lattner | 3eef4e3 | 2005-11-17 18:26:56 +0000 | [diff] [blame] | 177 | setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); |
Lauro Ramos Venancio | 75ce010 | 2007-07-11 17:19:51 +0000 | [diff] [blame] | 178 | setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); |
Nate Begeman | 28a6b02 | 2005-12-10 02:36:00 +0000 | [diff] [blame] | 179 | setOperationAction(ISD::ConstantPool, MVT::i32, Custom); |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 180 | setOperationAction(ISD::JumpTable, MVT::i32, Custom); |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 181 | setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); |
Lauro Ramos Venancio | 75ce010 | 2007-07-11 17:19:51 +0000 | [diff] [blame] | 182 | setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 183 | setOperationAction(ISD::ConstantPool, MVT::i64, Custom); |
| 184 | setOperationAction(ISD::JumpTable, MVT::i64, Custom); |
| 185 | |
Nate Begeman | ee62557 | 2006-01-27 21:09:22 +0000 | [diff] [blame] | 186 | // RET must be custom lowered, to meet ABI requirements |
| 187 | setOperationAction(ISD::RET , MVT::Other, Custom); |
Duncan Sands | 36397f5 | 2007-07-27 12:58:54 +0000 | [diff] [blame] | 188 | |
Nate Begeman | acc398c | 2006-01-25 18:21:52 +0000 | [diff] [blame] | 189 | // VASTART needs to be custom lowered to use the VarArgsFrameIndex |
| 190 | setOperationAction(ISD::VASTART , MVT::Other, Custom); |
| 191 | |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 192 | // VAARG is custom lowered with ELF 32 ABI |
| 193 | if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI()) |
| 194 | setOperationAction(ISD::VAARG, MVT::Other, Custom); |
| 195 | else |
| 196 | setOperationAction(ISD::VAARG, MVT::Other, Expand); |
| 197 | |
Chris Lattner | b22c08b | 2006-01-15 09:02:48 +0000 | [diff] [blame] | 198 | // Use the default implementation. |
Nate Begeman | acc398c | 2006-01-25 18:21:52 +0000 | [diff] [blame] | 199 | setOperationAction(ISD::VACOPY , MVT::Other, Expand); |
| 200 | setOperationAction(ISD::VAEND , MVT::Other, Expand); |
Chris Lattner | b22c08b | 2006-01-15 09:02:48 +0000 | [diff] [blame] | 201 | setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); |
Jim Laskey | efc7e52 | 2006-12-04 22:04:42 +0000 | [diff] [blame] | 202 | setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 203 | setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); |
| 204 | setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); |
Chris Lattner | 56a752e | 2006-10-18 01:18:48 +0000 | [diff] [blame] | 205 | |
Evan Cheng | 54fc97d | 2008-04-19 01:30:48 +0000 | [diff] [blame] | 206 | setOperationAction(ISD::ATOMIC_LAS , MVT::i32 , Custom); |
| 207 | setOperationAction(ISD::ATOMIC_LCS , MVT::i32 , Custom); |
| 208 | setOperationAction(ISD::ATOMIC_SWAP , MVT::i32 , Custom); |
| 209 | |
Chris Lattner | 6d92cad | 2006-03-26 10:06:40 +0000 | [diff] [blame] | 210 | // We want to custom lower some of our intrinsics. |
Chris Lattner | 48b61a7 | 2006-03-28 00:40:33 +0000 | [diff] [blame] | 211 | setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); |
Chris Lattner | 6d92cad | 2006-03-26 10:06:40 +0000 | [diff] [blame] | 212 | |
Chris Lattner | a7a5854 | 2006-06-16 17:34:12 +0000 | [diff] [blame] | 213 | if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 214 | // They also have instructions for converting between i64 and fp. |
Nate Begeman | c09eeec | 2005-09-06 22:03:27 +0000 | [diff] [blame] | 215 | setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); |
Jim Laskey | ca367b4 | 2006-12-15 14:32:57 +0000 | [diff] [blame] | 216 | setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); |
Nate Begeman | c09eeec | 2005-09-06 22:03:27 +0000 | [diff] [blame] | 217 | setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); |
Chris Lattner | 85c671b | 2006-12-07 01:24:16 +0000 | [diff] [blame] | 218 | setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); |
Jim Laskey | ca367b4 | 2006-12-15 14:32:57 +0000 | [diff] [blame] | 219 | setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); |
| 220 | |
Chris Lattner | 7fbcef7 | 2006-03-24 07:53:47 +0000 | [diff] [blame] | 221 | // FIXME: disable this lowered code. This generates 64-bit register values, |
| 222 | // and we don't model the fact that the top part is clobbered by calls. We |
| 223 | // need to flag these together so that the value isn't live across a call. |
| 224 | //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); |
| 225 | |
Nate Begeman | ae749a9 | 2005-10-25 23:48:36 +0000 | [diff] [blame] | 226 | // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT |
| 227 | setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); |
| 228 | } else { |
Chris Lattner | 860e886 | 2005-11-17 07:30:41 +0000 | [diff] [blame] | 229 | // PowerPC does not have FP_TO_UINT on 32-bit implementations. |
Nate Begeman | ae749a9 | 2005-10-25 23:48:36 +0000 | [diff] [blame] | 230 | setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); |
Nate Begeman | 9d2b817 | 2005-10-18 00:56:42 +0000 | [diff] [blame] | 231 | } |
| 232 | |
Chris Lattner | a7a5854 | 2006-06-16 17:34:12 +0000 | [diff] [blame] | 233 | if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { |
Chris Lattner | 26cb286 | 2007-10-19 04:08:28 +0000 | [diff] [blame] | 234 | // 64-bit PowerPC implementations can support i64 types directly |
Nate Begeman | 9d2b817 | 2005-10-18 00:56:42 +0000 | [diff] [blame] | 235 | addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 236 | // BUILD_PAIR can't be handled natively, and should be expanded to shl/or |
| 237 | setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); |
Dan Gohman | 9ed06db | 2008-03-07 20:36:53 +0000 | [diff] [blame] | 238 | // 64-bit PowerPC wants to expand i128 shifts itself. |
| 239 | setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); |
| 240 | setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); |
| 241 | setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 242 | } else { |
Chris Lattner | 26cb286 | 2007-10-19 04:08:28 +0000 | [diff] [blame] | 243 | // 32-bit PowerPC wants to expand i64 shifts itself. |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 244 | setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); |
| 245 | setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); |
| 246 | setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); |
Nate Begeman | c09eeec | 2005-09-06 22:03:27 +0000 | [diff] [blame] | 247 | } |
Evan Cheng | d30bf01 | 2006-03-01 01:11:20 +0000 | [diff] [blame] | 248 | |
Nate Begeman | 425a969 | 2005-11-29 08:17:20 +0000 | [diff] [blame] | 249 | if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { |
Chris Lattner | e3fea5a | 2006-03-31 19:52:36 +0000 | [diff] [blame] | 250 | // First set operation action for all vector types to expand. Then we |
| 251 | // will selectively turn on ones that can be effectively codegen'd. |
| 252 | for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; |
Dan Gohman | f5135be | 2007-05-18 23:21:46 +0000 | [diff] [blame] | 253 | VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { |
Chris Lattner | f3f69de | 2006-04-16 01:37:57 +0000 | [diff] [blame] | 254 | // add/sub are legal for all supported vector VT's. |
Chris Lattner | e3fea5a | 2006-03-31 19:52:36 +0000 | [diff] [blame] | 255 | setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal); |
| 256 | setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal); |
Chris Lattner | e3fea5a | 2006-03-31 19:52:36 +0000 | [diff] [blame] | 257 | |
Chris Lattner | 7ff7e67 | 2006-04-04 17:25:31 +0000 | [diff] [blame] | 258 | // We promote all shuffles to v16i8. |
| 259 | setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); |
Chris Lattner | f3f69de | 2006-04-16 01:37:57 +0000 | [diff] [blame] | 260 | AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8); |
| 261 | |
| 262 | // We promote all non-typed operations to v4i32. |
| 263 | setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote); |
| 264 | AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32); |
| 265 | setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote); |
| 266 | AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32); |
| 267 | setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote); |
| 268 | AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32); |
| 269 | setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote); |
| 270 | AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32); |
| 271 | setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); |
| 272 | AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32); |
| 273 | setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote); |
| 274 | AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32); |
Chris Lattner | e3fea5a | 2006-03-31 19:52:36 +0000 | [diff] [blame] | 275 | |
Chris Lattner | f3f69de | 2006-04-16 01:37:57 +0000 | [diff] [blame] | 276 | // No other operations are legal. |
Chris Lattner | e3fea5a | 2006-03-31 19:52:36 +0000 | [diff] [blame] | 277 | setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); |
| 278 | setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); |
| 279 | setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); |
| 280 | setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); |
| 281 | setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); |
Chris Lattner | 2ef5e89 | 2006-05-24 00:15:25 +0000 | [diff] [blame] | 282 | setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); |
Evan Cheng | 66ffe6b | 2007-07-30 07:51:22 +0000 | [diff] [blame] | 283 | setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand); |
Chris Lattner | e3fea5a | 2006-03-31 19:52:36 +0000 | [diff] [blame] | 284 | setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); |
| 285 | setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); |
| 286 | setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); |
Dan Gohman | 3ce990d | 2007-10-08 17:28:24 +0000 | [diff] [blame] | 287 | setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand); |
| 288 | setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand); |
| 289 | setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand); |
| 290 | setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand); |
Chris Lattner | 01cae07 | 2006-04-03 23:55:43 +0000 | [diff] [blame] | 291 | setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); |
Dan Gohman | a3f269f | 2007-10-12 14:08:57 +0000 | [diff] [blame] | 292 | setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand); |
| 293 | setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand); |
| 294 | setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand); |
| 295 | setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand); |
Chris Lattner | e3fea5a | 2006-03-31 19:52:36 +0000 | [diff] [blame] | 296 | } |
| 297 | |
Chris Lattner | 7ff7e67 | 2006-04-04 17:25:31 +0000 | [diff] [blame] | 298 | // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle |
| 299 | // with merges, splats, etc. |
| 300 | setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); |
| 301 | |
Chris Lattner | f3f69de | 2006-04-16 01:37:57 +0000 | [diff] [blame] | 302 | setOperationAction(ISD::AND , MVT::v4i32, Legal); |
| 303 | setOperationAction(ISD::OR , MVT::v4i32, Legal); |
| 304 | setOperationAction(ISD::XOR , MVT::v4i32, Legal); |
| 305 | setOperationAction(ISD::LOAD , MVT::v4i32, Legal); |
| 306 | setOperationAction(ISD::SELECT, MVT::v4i32, Expand); |
| 307 | setOperationAction(ISD::STORE , MVT::v4i32, Legal); |
| 308 | |
Nate Begeman | 425a969 | 2005-11-29 08:17:20 +0000 | [diff] [blame] | 309 | addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); |
Nate Begeman | 7fd1edd | 2005-12-19 23:25:09 +0000 | [diff] [blame] | 310 | addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); |
Chris Lattner | 8d052bc | 2006-03-25 07:39:07 +0000 | [diff] [blame] | 311 | addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); |
| 312 | addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); |
Chris Lattner | ec4a0c7 | 2006-01-29 06:32:58 +0000 | [diff] [blame] | 313 | |
Chris Lattner | e3fea5a | 2006-03-31 19:52:36 +0000 | [diff] [blame] | 314 | setOperationAction(ISD::MUL, MVT::v4f32, Legal); |
Chris Lattner | e7c768e | 2006-04-18 03:24:30 +0000 | [diff] [blame] | 315 | setOperationAction(ISD::MUL, MVT::v4i32, Custom); |
Chris Lattner | 72dd9bd | 2006-04-18 03:43:48 +0000 | [diff] [blame] | 316 | setOperationAction(ISD::MUL, MVT::v8i16, Custom); |
Chris Lattner | 19a8152 | 2006-04-18 03:57:35 +0000 | [diff] [blame] | 317 | setOperationAction(ISD::MUL, MVT::v16i8, Custom); |
Chris Lattner | f1d0b2b | 2006-03-20 01:53:53 +0000 | [diff] [blame] | 318 | |
Chris Lattner | b2177b9 | 2006-03-19 06:55:52 +0000 | [diff] [blame] | 319 | setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); |
| 320 | setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); |
Chris Lattner | 64b3a08 | 2006-03-24 07:48:08 +0000 | [diff] [blame] | 321 | |
Chris Lattner | 541f91b | 2006-04-02 00:43:36 +0000 | [diff] [blame] | 322 | setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); |
| 323 | setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); |
Chris Lattner | 64b3a08 | 2006-03-24 07:48:08 +0000 | [diff] [blame] | 324 | setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); |
| 325 | setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); |
Nate Begeman | 425a969 | 2005-11-29 08:17:20 +0000 | [diff] [blame] | 326 | } |
| 327 | |
Chris Lattner | 7b0c58c | 2006-06-27 17:34:57 +0000 | [diff] [blame] | 328 | setShiftAmountType(MVT::i32); |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 329 | setSetCCResultContents(ZeroOrOneSetCCResult); |
Chris Lattner | 10da957 | 2006-10-18 01:20:43 +0000 | [diff] [blame] | 330 | |
Jim Laskey | 2ad9f17 | 2007-02-22 14:56:36 +0000 | [diff] [blame] | 331 | if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { |
Chris Lattner | 10da957 | 2006-10-18 01:20:43 +0000 | [diff] [blame] | 332 | setStackPointerRegisterToSaveRestore(PPC::X1); |
Jim Laskey | 2ad9f17 | 2007-02-22 14:56:36 +0000 | [diff] [blame] | 333 | setExceptionPointerRegister(PPC::X3); |
| 334 | setExceptionSelectorRegister(PPC::X4); |
| 335 | } else { |
Chris Lattner | 10da957 | 2006-10-18 01:20:43 +0000 | [diff] [blame] | 336 | setStackPointerRegisterToSaveRestore(PPC::R1); |
Jim Laskey | 2ad9f17 | 2007-02-22 14:56:36 +0000 | [diff] [blame] | 337 | setExceptionPointerRegister(PPC::R3); |
| 338 | setExceptionSelectorRegister(PPC::R4); |
| 339 | } |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 340 | |
Chris Lattner | 8c13d0a | 2006-03-01 04:57:39 +0000 | [diff] [blame] | 341 | // We have target-specific dag combine patterns for the following nodes: |
| 342 | setTargetDAGCombine(ISD::SINT_TO_FP); |
Chris Lattner | 5126984 | 2006-03-01 05:50:56 +0000 | [diff] [blame] | 343 | setTargetDAGCombine(ISD::STORE); |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 344 | setTargetDAGCombine(ISD::BR_CC); |
Chris Lattner | d998938 | 2006-07-10 20:56:58 +0000 | [diff] [blame] | 345 | setTargetDAGCombine(ISD::BSWAP); |
Chris Lattner | 8c13d0a | 2006-03-01 04:57:39 +0000 | [diff] [blame] | 346 | |
Dale Johannesen | fabd32d | 2007-10-19 00:59:18 +0000 | [diff] [blame] | 347 | // Darwin long double math library functions have $LDBL128 appended. |
| 348 | if (TM.getSubtarget<PPCSubtarget>().isDarwin()) { |
Duncan Sands | 007f984 | 2008-01-10 10:28:30 +0000 | [diff] [blame] | 349 | setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); |
Dale Johannesen | fabd32d | 2007-10-19 00:59:18 +0000 | [diff] [blame] | 350 | setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); |
| 351 | setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); |
Duncan Sands | 007f984 | 2008-01-10 10:28:30 +0000 | [diff] [blame] | 352 | setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); |
| 353 | setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); |
Dale Johannesen | fabd32d | 2007-10-19 00:59:18 +0000 | [diff] [blame] | 354 | } |
| 355 | |
Chris Lattner | 7c5a3d3 | 2005-08-16 17:14:42 +0000 | [diff] [blame] | 356 | computeRegisterProperties(); |
| 357 | } |
| 358 | |
Dale Johannesen | 28d08fd | 2008-02-28 22:31:51 +0000 | [diff] [blame] | 359 | /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate |
| 360 | /// function arguments in the caller parameter area. |
| 361 | unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const { |
| 362 | TargetMachine &TM = getTargetMachine(); |
| 363 | // Darwin passes everything on 4 byte boundary. |
| 364 | if (TM.getSubtarget<PPCSubtarget>().isDarwin()) |
| 365 | return 4; |
| 366 | // FIXME Elf TBD |
| 367 | return 4; |
| 368 | } |
| 369 | |
Chris Lattner | da6d20f | 2006-01-09 23:52:17 +0000 | [diff] [blame] | 370 | const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { |
| 371 | switch (Opcode) { |
| 372 | default: return 0; |
| 373 | case PPCISD::FSEL: return "PPCISD::FSEL"; |
| 374 | case PPCISD::FCFID: return "PPCISD::FCFID"; |
| 375 | case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; |
| 376 | case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; |
Chris Lattner | 5126984 | 2006-03-01 05:50:56 +0000 | [diff] [blame] | 377 | case PPCISD::STFIWX: return "PPCISD::STFIWX"; |
Chris Lattner | da6d20f | 2006-01-09 23:52:17 +0000 | [diff] [blame] | 378 | case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; |
| 379 | case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; |
Chris Lattner | f1d0b2b | 2006-03-20 01:53:53 +0000 | [diff] [blame] | 380 | case PPCISD::VPERM: return "PPCISD::VPERM"; |
Chris Lattner | da6d20f | 2006-01-09 23:52:17 +0000 | [diff] [blame] | 381 | case PPCISD::Hi: return "PPCISD::Hi"; |
| 382 | case PPCISD::Lo: return "PPCISD::Lo"; |
Jim Laskey | 2060a82 | 2006-12-11 18:45:56 +0000 | [diff] [blame] | 383 | case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; |
Chris Lattner | da6d20f | 2006-01-09 23:52:17 +0000 | [diff] [blame] | 384 | case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; |
| 385 | case PPCISD::SRL: return "PPCISD::SRL"; |
| 386 | case PPCISD::SRA: return "PPCISD::SRA"; |
| 387 | case PPCISD::SHL: return "PPCISD::SHL"; |
Chris Lattner | ecfe55e | 2006-03-22 05:30:33 +0000 | [diff] [blame] | 388 | case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; |
| 389 | case PPCISD::STD_32: return "PPCISD::STD_32"; |
Nicolas Geoffray | 63f8fb1 | 2007-02-27 13:01:19 +0000 | [diff] [blame] | 390 | case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF"; |
| 391 | case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho"; |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 392 | case PPCISD::MTCTR: return "PPCISD::MTCTR"; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 393 | case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho"; |
| 394 | case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF"; |
Chris Lattner | da6d20f | 2006-01-09 23:52:17 +0000 | [diff] [blame] | 395 | case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; |
Chris Lattner | 6d92cad | 2006-03-26 10:06:40 +0000 | [diff] [blame] | 396 | case PPCISD::MFCR: return "PPCISD::MFCR"; |
Chris Lattner | a17b155 | 2006-03-31 05:13:27 +0000 | [diff] [blame] | 397 | case PPCISD::VCMP: return "PPCISD::VCMP"; |
Chris Lattner | 6d92cad | 2006-03-26 10:06:40 +0000 | [diff] [blame] | 398 | case PPCISD::VCMPo: return "PPCISD::VCMPo"; |
Chris Lattner | d998938 | 2006-07-10 20:56:58 +0000 | [diff] [blame] | 399 | case PPCISD::LBRX: return "PPCISD::LBRX"; |
| 400 | case PPCISD::STBRX: return "PPCISD::STBRX"; |
Evan Cheng | 54fc97d | 2008-04-19 01:30:48 +0000 | [diff] [blame] | 401 | case PPCISD::LWARX: return "PPCISD::LWARX"; |
| 402 | case PPCISD::STWCX: return "PPCISD::STWCX"; |
| 403 | case PPCISD::CMP_UNRESERVE: return "PPCISD::CMP_UNRESERVE"; |
Chris Lattner | f70f8d9 | 2006-04-18 18:05:58 +0000 | [diff] [blame] | 404 | case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; |
Chris Lattner | ef97c67 | 2008-01-18 18:51:16 +0000 | [diff] [blame] | 405 | case PPCISD::MFFS: return "PPCISD::MFFS"; |
| 406 | case PPCISD::MTFSB0: return "PPCISD::MTFSB0"; |
| 407 | case PPCISD::MTFSB1: return "PPCISD::MTFSB1"; |
| 408 | case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; |
| 409 | case PPCISD::MTFSF: return "PPCISD::MTFSF"; |
Chris Lattner | da6d20f | 2006-01-09 23:52:17 +0000 | [diff] [blame] | 410 | } |
| 411 | } |
| 412 | |
Scott Michel | 5b8f82e | 2008-03-10 15:42:14 +0000 | [diff] [blame] | 413 | |
| 414 | MVT::ValueType |
| 415 | PPCTargetLowering::getSetCCResultType(const SDOperand &) const { |
| 416 | return MVT::i32; |
| 417 | } |
| 418 | |
| 419 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 420 | //===----------------------------------------------------------------------===// |
| 421 | // Node matching predicates, for use by the tblgen matching code. |
| 422 | //===----------------------------------------------------------------------===// |
| 423 | |
Chris Lattner | 0b1e4e5 | 2005-08-26 17:36:52 +0000 | [diff] [blame] | 424 | /// isFloatingPointZero - Return true if this is 0.0 or -0.0. |
| 425 | static bool isFloatingPointZero(SDOperand Op) { |
| 426 | if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) |
Dale Johannesen | eaf0894 | 2007-08-31 04:03:46 +0000 | [diff] [blame] | 427 | return CFP->getValueAPF().isZero(); |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 428 | else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { |
Chris Lattner | 0b1e4e5 | 2005-08-26 17:36:52 +0000 | [diff] [blame] | 429 | // Maybe this has already been legalized into the constant pool? |
| 430 | if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) |
Evan Cheng | c356a57 | 2006-09-12 21:04:05 +0000 | [diff] [blame] | 431 | if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) |
Dale Johannesen | eaf0894 | 2007-08-31 04:03:46 +0000 | [diff] [blame] | 432 | return CFP->getValueAPF().isZero(); |
Chris Lattner | 0b1e4e5 | 2005-08-26 17:36:52 +0000 | [diff] [blame] | 433 | } |
| 434 | return false; |
| 435 | } |
| 436 | |
Chris Lattner | ddb739e | 2006-04-06 17:23:16 +0000 | [diff] [blame] | 437 | /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return |
| 438 | /// true if Op is undef or if it matches the specified value. |
| 439 | static bool isConstantOrUndef(SDOperand Op, unsigned Val) { |
| 440 | return Op.getOpcode() == ISD::UNDEF || |
| 441 | cast<ConstantSDNode>(Op)->getValue() == Val; |
| 442 | } |
| 443 | |
| 444 | /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a |
| 445 | /// VPKUHUM instruction. |
Chris Lattner | f24380e | 2006-04-06 22:28:36 +0000 | [diff] [blame] | 446 | bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) { |
| 447 | if (!isUnary) { |
| 448 | for (unsigned i = 0; i != 16; ++i) |
| 449 | if (!isConstantOrUndef(N->getOperand(i), i*2+1)) |
| 450 | return false; |
| 451 | } else { |
| 452 | for (unsigned i = 0; i != 8; ++i) |
| 453 | if (!isConstantOrUndef(N->getOperand(i), i*2+1) || |
| 454 | !isConstantOrUndef(N->getOperand(i+8), i*2+1)) |
| 455 | return false; |
| 456 | } |
Chris Lattner | d0608e1 | 2006-04-06 18:26:28 +0000 | [diff] [blame] | 457 | return true; |
Chris Lattner | ddb739e | 2006-04-06 17:23:16 +0000 | [diff] [blame] | 458 | } |
| 459 | |
| 460 | /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a |
| 461 | /// VPKUWUM instruction. |
Chris Lattner | f24380e | 2006-04-06 22:28:36 +0000 | [diff] [blame] | 462 | bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) { |
| 463 | if (!isUnary) { |
| 464 | for (unsigned i = 0; i != 16; i += 2) |
| 465 | if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || |
| 466 | !isConstantOrUndef(N->getOperand(i+1), i*2+3)) |
| 467 | return false; |
| 468 | } else { |
| 469 | for (unsigned i = 0; i != 8; i += 2) |
| 470 | if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || |
| 471 | !isConstantOrUndef(N->getOperand(i+1), i*2+3) || |
| 472 | !isConstantOrUndef(N->getOperand(i+8), i*2+2) || |
| 473 | !isConstantOrUndef(N->getOperand(i+9), i*2+3)) |
| 474 | return false; |
| 475 | } |
Chris Lattner | d0608e1 | 2006-04-06 18:26:28 +0000 | [diff] [blame] | 476 | return true; |
Chris Lattner | ddb739e | 2006-04-06 17:23:16 +0000 | [diff] [blame] | 477 | } |
| 478 | |
Chris Lattner | caad163 | 2006-04-06 22:02:42 +0000 | [diff] [blame] | 479 | /// isVMerge - Common function, used to match vmrg* shuffles. |
| 480 | /// |
| 481 | static bool isVMerge(SDNode *N, unsigned UnitSize, |
| 482 | unsigned LHSStart, unsigned RHSStart) { |
Chris Lattner | 116cc48 | 2006-04-06 21:11:54 +0000 | [diff] [blame] | 483 | assert(N->getOpcode() == ISD::BUILD_VECTOR && |
| 484 | N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); |
| 485 | assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && |
| 486 | "Unsupported merge size!"); |
| 487 | |
| 488 | for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units |
| 489 | for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit |
| 490 | if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), |
Chris Lattner | caad163 | 2006-04-06 22:02:42 +0000 | [diff] [blame] | 491 | LHSStart+j+i*UnitSize) || |
Chris Lattner | 116cc48 | 2006-04-06 21:11:54 +0000 | [diff] [blame] | 492 | !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), |
Chris Lattner | caad163 | 2006-04-06 22:02:42 +0000 | [diff] [blame] | 493 | RHSStart+j+i*UnitSize)) |
Chris Lattner | 116cc48 | 2006-04-06 21:11:54 +0000 | [diff] [blame] | 494 | return false; |
| 495 | } |
Chris Lattner | caad163 | 2006-04-06 22:02:42 +0000 | [diff] [blame] | 496 | return true; |
| 497 | } |
| 498 | |
| 499 | /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for |
| 500 | /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). |
| 501 | bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { |
| 502 | if (!isUnary) |
| 503 | return isVMerge(N, UnitSize, 8, 24); |
| 504 | return isVMerge(N, UnitSize, 8, 8); |
Chris Lattner | 116cc48 | 2006-04-06 21:11:54 +0000 | [diff] [blame] | 505 | } |
| 506 | |
| 507 | /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for |
| 508 | /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). |
Chris Lattner | caad163 | 2006-04-06 22:02:42 +0000 | [diff] [blame] | 509 | bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { |
| 510 | if (!isUnary) |
| 511 | return isVMerge(N, UnitSize, 0, 16); |
| 512 | return isVMerge(N, UnitSize, 0, 0); |
Chris Lattner | 116cc48 | 2006-04-06 21:11:54 +0000 | [diff] [blame] | 513 | } |
| 514 | |
| 515 | |
Chris Lattner | d0608e1 | 2006-04-06 18:26:28 +0000 | [diff] [blame] | 516 | /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift |
| 517 | /// amount, otherwise return -1. |
Chris Lattner | f24380e | 2006-04-06 22:28:36 +0000 | [diff] [blame] | 518 | int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { |
Chris Lattner | 116cc48 | 2006-04-06 21:11:54 +0000 | [diff] [blame] | 519 | assert(N->getOpcode() == ISD::BUILD_VECTOR && |
| 520 | N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); |
Chris Lattner | d0608e1 | 2006-04-06 18:26:28 +0000 | [diff] [blame] | 521 | // Find the first non-undef value in the shuffle mask. |
| 522 | unsigned i; |
| 523 | for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) |
| 524 | /*search*/; |
| 525 | |
| 526 | if (i == 16) return -1; // all undef. |
| 527 | |
| 528 | // Otherwise, check to see if the rest of the elements are consequtively |
| 529 | // numbered from this value. |
| 530 | unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue(); |
| 531 | if (ShiftAmt < i) return -1; |
| 532 | ShiftAmt -= i; |
Chris Lattner | ddb739e | 2006-04-06 17:23:16 +0000 | [diff] [blame] | 533 | |
Chris Lattner | f24380e | 2006-04-06 22:28:36 +0000 | [diff] [blame] | 534 | if (!isUnary) { |
| 535 | // Check the rest of the elements to see if they are consequtive. |
| 536 | for (++i; i != 16; ++i) |
| 537 | if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) |
| 538 | return -1; |
| 539 | } else { |
| 540 | // Check the rest of the elements to see if they are consequtive. |
| 541 | for (++i; i != 16; ++i) |
| 542 | if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) |
| 543 | return -1; |
| 544 | } |
Chris Lattner | d0608e1 | 2006-04-06 18:26:28 +0000 | [diff] [blame] | 545 | |
| 546 | return ShiftAmt; |
| 547 | } |
Chris Lattner | ef819f8 | 2006-03-20 06:33:01 +0000 | [diff] [blame] | 548 | |
| 549 | /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand |
| 550 | /// specifies a splat of a single element that is suitable for input to |
| 551 | /// VSPLTB/VSPLTH/VSPLTW. |
Chris Lattner | 7ff7e67 | 2006-04-04 17:25:31 +0000 | [diff] [blame] | 552 | bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { |
| 553 | assert(N->getOpcode() == ISD::BUILD_VECTOR && |
| 554 | N->getNumOperands() == 16 && |
| 555 | (EltSize == 1 || EltSize == 2 || EltSize == 4)); |
Chris Lattner | dd4d2d0 | 2006-03-20 06:51:10 +0000 | [diff] [blame] | 556 | |
Chris Lattner | 88a99ef | 2006-03-20 06:37:44 +0000 | [diff] [blame] | 557 | // This is a splat operation if each element of the permute is the same, and |
| 558 | // if the value doesn't reference the second vector. |
Chris Lattner | 7ff7e67 | 2006-04-04 17:25:31 +0000 | [diff] [blame] | 559 | unsigned ElementBase = 0; |
Chris Lattner | 88a99ef | 2006-03-20 06:37:44 +0000 | [diff] [blame] | 560 | SDOperand Elt = N->getOperand(0); |
Chris Lattner | 7ff7e67 | 2006-04-04 17:25:31 +0000 | [diff] [blame] | 561 | if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) |
| 562 | ElementBase = EltV->getValue(); |
| 563 | else |
| 564 | return false; // FIXME: Handle UNDEF elements too! |
| 565 | |
| 566 | if (cast<ConstantSDNode>(Elt)->getValue() >= 16) |
| 567 | return false; |
| 568 | |
| 569 | // Check that they are consequtive. |
| 570 | for (unsigned i = 1; i != EltSize; ++i) { |
| 571 | if (!isa<ConstantSDNode>(N->getOperand(i)) || |
| 572 | cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase) |
| 573 | return false; |
| 574 | } |
| 575 | |
Chris Lattner | 88a99ef | 2006-03-20 06:37:44 +0000 | [diff] [blame] | 576 | assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!"); |
Chris Lattner | 7ff7e67 | 2006-04-04 17:25:31 +0000 | [diff] [blame] | 577 | for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { |
Chris Lattner | b097aa9 | 2006-04-14 23:19:08 +0000 | [diff] [blame] | 578 | if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; |
Chris Lattner | 88a99ef | 2006-03-20 06:37:44 +0000 | [diff] [blame] | 579 | assert(isa<ConstantSDNode>(N->getOperand(i)) && |
| 580 | "Invalid VECTOR_SHUFFLE mask!"); |
Chris Lattner | 7ff7e67 | 2006-04-04 17:25:31 +0000 | [diff] [blame] | 581 | for (unsigned j = 0; j != EltSize; ++j) |
| 582 | if (N->getOperand(i+j) != N->getOperand(j)) |
| 583 | return false; |
Chris Lattner | 88a99ef | 2006-03-20 06:37:44 +0000 | [diff] [blame] | 584 | } |
| 585 | |
Chris Lattner | 7ff7e67 | 2006-04-04 17:25:31 +0000 | [diff] [blame] | 586 | return true; |
Chris Lattner | ef819f8 | 2006-03-20 06:33:01 +0000 | [diff] [blame] | 587 | } |
| 588 | |
Evan Cheng | 66ffe6b | 2007-07-30 07:51:22 +0000 | [diff] [blame] | 589 | /// isAllNegativeZeroVector - Returns true if all elements of build_vector |
| 590 | /// are -0.0. |
| 591 | bool PPC::isAllNegativeZeroVector(SDNode *N) { |
| 592 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
| 593 | if (PPC::isSplatShuffleMask(N, N->getNumOperands())) |
| 594 | if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N)) |
Dale Johannesen | eaf0894 | 2007-08-31 04:03:46 +0000 | [diff] [blame] | 595 | return CFP->getValueAPF().isNegZero(); |
Evan Cheng | 66ffe6b | 2007-07-30 07:51:22 +0000 | [diff] [blame] | 596 | return false; |
| 597 | } |
| 598 | |
Chris Lattner | ef819f8 | 2006-03-20 06:33:01 +0000 | [diff] [blame] | 599 | /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the |
| 600 | /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. |
Chris Lattner | 7ff7e67 | 2006-04-04 17:25:31 +0000 | [diff] [blame] | 601 | unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { |
| 602 | assert(isSplatShuffleMask(N, EltSize)); |
| 603 | return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize; |
Chris Lattner | ef819f8 | 2006-03-20 06:33:01 +0000 | [diff] [blame] | 604 | } |
| 605 | |
Chris Lattner | e87192a | 2006-04-12 17:37:20 +0000 | [diff] [blame] | 606 | /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed |
Chris Lattner | 140a58f | 2006-04-08 06:46:53 +0000 | [diff] [blame] | 607 | /// by using a vspltis[bhw] instruction of the specified element size, return |
| 608 | /// the constant being splatted. The ByteSize field indicates the number of |
| 609 | /// bytes of each element [124] -> [bhw]. |
Chris Lattner | e87192a | 2006-04-12 17:37:20 +0000 | [diff] [blame] | 610 | SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 611 | SDOperand OpVal(0, 0); |
Chris Lattner | 79d9a88 | 2006-04-08 07:14:26 +0000 | [diff] [blame] | 612 | |
| 613 | // If ByteSize of the splat is bigger than the element size of the |
| 614 | // build_vector, then we have a case where we are checking for a splat where |
| 615 | // multiple elements of the buildvector are folded together into a single |
| 616 | // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). |
| 617 | unsigned EltSize = 16/N->getNumOperands(); |
| 618 | if (EltSize < ByteSize) { |
| 619 | unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. |
| 620 | SDOperand UniquedVals[4]; |
| 621 | assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); |
| 622 | |
| 623 | // See if all of the elements in the buildvector agree across. |
| 624 | for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { |
| 625 | if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; |
| 626 | // If the element isn't a constant, bail fully out. |
| 627 | if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand(); |
| 628 | |
| 629 | |
| 630 | if (UniquedVals[i&(Multiple-1)].Val == 0) |
| 631 | UniquedVals[i&(Multiple-1)] = N->getOperand(i); |
| 632 | else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) |
| 633 | return SDOperand(); // no match. |
| 634 | } |
| 635 | |
| 636 | // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains |
| 637 | // either constant or undef values that are identical for each chunk. See |
| 638 | // if these chunks can form into a larger vspltis*. |
| 639 | |
| 640 | // Check to see if all of the leading entries are either 0 or -1. If |
| 641 | // neither, then this won't fit into the immediate field. |
| 642 | bool LeadingZero = true; |
| 643 | bool LeadingOnes = true; |
| 644 | for (unsigned i = 0; i != Multiple-1; ++i) { |
| 645 | if (UniquedVals[i].Val == 0) continue; // Must have been undefs. |
| 646 | |
| 647 | LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); |
| 648 | LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); |
| 649 | } |
| 650 | // Finally, check the least significant entry. |
| 651 | if (LeadingZero) { |
| 652 | if (UniquedVals[Multiple-1].Val == 0) |
| 653 | return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef |
| 654 | int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue(); |
| 655 | if (Val < 16) |
| 656 | return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) |
| 657 | } |
| 658 | if (LeadingOnes) { |
| 659 | if (UniquedVals[Multiple-1].Val == 0) |
| 660 | return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef |
| 661 | int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended(); |
| 662 | if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) |
| 663 | return DAG.getTargetConstant(Val, MVT::i32); |
| 664 | } |
| 665 | |
| 666 | return SDOperand(); |
| 667 | } |
| 668 | |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 669 | // Check to see if this buildvec has a single non-undef value in its elements. |
| 670 | for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { |
| 671 | if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; |
| 672 | if (OpVal.Val == 0) |
| 673 | OpVal = N->getOperand(i); |
| 674 | else if (OpVal != N->getOperand(i)) |
Chris Lattner | 140a58f | 2006-04-08 06:46:53 +0000 | [diff] [blame] | 675 | return SDOperand(); |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 676 | } |
| 677 | |
Chris Lattner | 140a58f | 2006-04-08 06:46:53 +0000 | [diff] [blame] | 678 | if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def. |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 679 | |
Nate Begeman | 98e70cc | 2006-03-28 04:15:58 +0000 | [diff] [blame] | 680 | unsigned ValSizeInBytes = 0; |
| 681 | uint64_t Value = 0; |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 682 | if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { |
| 683 | Value = CN->getValue(); |
| 684 | ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8; |
| 685 | } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { |
| 686 | assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); |
Dale Johannesen | eaf0894 | 2007-08-31 04:03:46 +0000 | [diff] [blame] | 687 | Value = FloatToBits(CN->getValueAPF().convertToFloat()); |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 688 | ValSizeInBytes = 4; |
| 689 | } |
| 690 | |
| 691 | // If the splat value is larger than the element value, then we can never do |
| 692 | // this splat. The only case that we could fit the replicated bits into our |
| 693 | // immediate field for would be zero, and we prefer to use vxor for it. |
Chris Lattner | 140a58f | 2006-04-08 06:46:53 +0000 | [diff] [blame] | 694 | if (ValSizeInBytes < ByteSize) return SDOperand(); |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 695 | |
| 696 | // If the element value is larger than the splat value, cut it in half and |
| 697 | // check to see if the two halves are equal. Continue doing this until we |
| 698 | // get to ByteSize. This allows us to handle 0x01010101 as 0x01. |
| 699 | while (ValSizeInBytes > ByteSize) { |
| 700 | ValSizeInBytes >>= 1; |
| 701 | |
| 702 | // If the top half equals the bottom half, we're still ok. |
Chris Lattner | 9b42bdd | 2006-04-05 17:39:25 +0000 | [diff] [blame] | 703 | if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != |
| 704 | (Value & ((1 << (8*ValSizeInBytes))-1))) |
Chris Lattner | 140a58f | 2006-04-08 06:46:53 +0000 | [diff] [blame] | 705 | return SDOperand(); |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 706 | } |
| 707 | |
| 708 | // Properly sign extend the value. |
| 709 | int ShAmt = (4-ByteSize)*8; |
| 710 | int MaskVal = ((int)Value << ShAmt) >> ShAmt; |
| 711 | |
Evan Cheng | 5b6a01b | 2006-03-26 09:52:32 +0000 | [diff] [blame] | 712 | // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. |
Chris Lattner | 140a58f | 2006-04-08 06:46:53 +0000 | [diff] [blame] | 713 | if (MaskVal == 0) return SDOperand(); |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 714 | |
Chris Lattner | 140a58f | 2006-04-08 06:46:53 +0000 | [diff] [blame] | 715 | // Finally, if this value fits in a 5 bit sext field, return it |
| 716 | if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) |
| 717 | return DAG.getTargetConstant(MaskVal, MVT::i32); |
| 718 | return SDOperand(); |
Chris Lattner | 9c61dcf | 2006-03-25 06:12:06 +0000 | [diff] [blame] | 719 | } |
| 720 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 721 | //===----------------------------------------------------------------------===// |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 722 | // Addressing Mode Selection |
| 723 | //===----------------------------------------------------------------------===// |
| 724 | |
| 725 | /// isIntS16Immediate - This method tests to see if the node is either a 32-bit |
| 726 | /// or 64-bit immediate, and if the value can be accurately represented as a |
| 727 | /// sign extension from a 16-bit value. If so, this returns true and the |
| 728 | /// immediate. |
| 729 | static bool isIntS16Immediate(SDNode *N, short &Imm) { |
| 730 | if (N->getOpcode() != ISD::Constant) |
| 731 | return false; |
| 732 | |
| 733 | Imm = (short)cast<ConstantSDNode>(N)->getValue(); |
| 734 | if (N->getValueType(0) == MVT::i32) |
| 735 | return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue(); |
| 736 | else |
| 737 | return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue(); |
| 738 | } |
| 739 | static bool isIntS16Immediate(SDOperand Op, short &Imm) { |
| 740 | return isIntS16Immediate(Op.Val, Imm); |
| 741 | } |
| 742 | |
| 743 | |
| 744 | /// SelectAddressRegReg - Given the specified addressed, check to see if it |
| 745 | /// can be represented as an indexed [r+r] operation. Returns false if it |
| 746 | /// can be more efficiently represented with [r+imm]. |
| 747 | bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base, |
| 748 | SDOperand &Index, |
| 749 | SelectionDAG &DAG) { |
| 750 | short imm = 0; |
| 751 | if (N.getOpcode() == ISD::ADD) { |
| 752 | if (isIntS16Immediate(N.getOperand(1), imm)) |
| 753 | return false; // r+i |
| 754 | if (N.getOperand(1).getOpcode() == PPCISD::Lo) |
| 755 | return false; // r+i |
| 756 | |
| 757 | Base = N.getOperand(0); |
| 758 | Index = N.getOperand(1); |
| 759 | return true; |
| 760 | } else if (N.getOpcode() == ISD::OR) { |
| 761 | if (isIntS16Immediate(N.getOperand(1), imm)) |
| 762 | return false; // r+i can fold it if we can. |
| 763 | |
| 764 | // If this is an or of disjoint bitfields, we can codegen this as an add |
| 765 | // (for better address arithmetic) if the LHS and RHS of the OR are provably |
| 766 | // disjoint. |
Dan Gohman | b3564aa | 2008-02-27 01:23:58 +0000 | [diff] [blame] | 767 | APInt LHSKnownZero, LHSKnownOne; |
| 768 | APInt RHSKnownZero, RHSKnownOne; |
| 769 | DAG.ComputeMaskedBits(N.getOperand(0), |
Dan Gohman | ec59b95 | 2008-02-27 21:12:32 +0000 | [diff] [blame] | 770 | APInt::getAllOnesValue(N.getOperand(0) |
| 771 | .getValueSizeInBits()), |
Dan Gohman | b3564aa | 2008-02-27 01:23:58 +0000 | [diff] [blame] | 772 | LHSKnownZero, LHSKnownOne); |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 773 | |
Dan Gohman | b3564aa | 2008-02-27 01:23:58 +0000 | [diff] [blame] | 774 | if (LHSKnownZero.getBoolValue()) { |
| 775 | DAG.ComputeMaskedBits(N.getOperand(1), |
Dan Gohman | ec59b95 | 2008-02-27 21:12:32 +0000 | [diff] [blame] | 776 | APInt::getAllOnesValue(N.getOperand(1) |
| 777 | .getValueSizeInBits()), |
Dan Gohman | b3564aa | 2008-02-27 01:23:58 +0000 | [diff] [blame] | 778 | RHSKnownZero, RHSKnownOne); |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 779 | // If all of the bits are known zero on the LHS or RHS, the add won't |
| 780 | // carry. |
Dan Gohman | ec59b95 | 2008-02-27 21:12:32 +0000 | [diff] [blame] | 781 | if (~(LHSKnownZero | RHSKnownZero) == 0) { |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 782 | Base = N.getOperand(0); |
| 783 | Index = N.getOperand(1); |
| 784 | return true; |
| 785 | } |
| 786 | } |
| 787 | } |
| 788 | |
| 789 | return false; |
| 790 | } |
| 791 | |
| 792 | /// Returns true if the address N can be represented by a base register plus |
| 793 | /// a signed 16-bit displacement [r+imm], and if it is not better |
| 794 | /// represented as reg+reg. |
| 795 | bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp, |
| 796 | SDOperand &Base, SelectionDAG &DAG){ |
| 797 | // If this can be more profitably realized as r+r, fail. |
| 798 | if (SelectAddressRegReg(N, Disp, Base, DAG)) |
| 799 | return false; |
| 800 | |
| 801 | if (N.getOpcode() == ISD::ADD) { |
| 802 | short imm = 0; |
| 803 | if (isIntS16Immediate(N.getOperand(1), imm)) { |
| 804 | Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); |
| 805 | if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { |
| 806 | Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); |
| 807 | } else { |
| 808 | Base = N.getOperand(0); |
| 809 | } |
| 810 | return true; // [r+i] |
| 811 | } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { |
| 812 | // Match LOAD (ADD (X, Lo(G))). |
| 813 | assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() |
| 814 | && "Cannot handle constant offsets yet!"); |
| 815 | Disp = N.getOperand(1).getOperand(0); // The global address. |
| 816 | assert(Disp.getOpcode() == ISD::TargetGlobalAddress || |
| 817 | Disp.getOpcode() == ISD::TargetConstantPool || |
| 818 | Disp.getOpcode() == ISD::TargetJumpTable); |
| 819 | Base = N.getOperand(0); |
| 820 | return true; // [&g+r] |
| 821 | } |
| 822 | } else if (N.getOpcode() == ISD::OR) { |
| 823 | short imm = 0; |
| 824 | if (isIntS16Immediate(N.getOperand(1), imm)) { |
| 825 | // If this is an or of disjoint bitfields, we can codegen this as an add |
| 826 | // (for better address arithmetic) if the LHS and RHS of the OR are |
| 827 | // provably disjoint. |
Dan Gohman | b3564aa | 2008-02-27 01:23:58 +0000 | [diff] [blame] | 828 | APInt LHSKnownZero, LHSKnownOne; |
| 829 | DAG.ComputeMaskedBits(N.getOperand(0), |
Bill Wendling | 3e98c30 | 2008-03-24 23:16:37 +0000 | [diff] [blame] | 830 | APInt::getAllOnesValue(N.getOperand(0) |
| 831 | .getValueSizeInBits()), |
Dan Gohman | b3564aa | 2008-02-27 01:23:58 +0000 | [diff] [blame] | 832 | LHSKnownZero, LHSKnownOne); |
Bill Wendling | 3e98c30 | 2008-03-24 23:16:37 +0000 | [diff] [blame] | 833 | |
Dan Gohman | b3564aa | 2008-02-27 01:23:58 +0000 | [diff] [blame] | 834 | if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 835 | // If all of the bits are known zero on the LHS or RHS, the add won't |
| 836 | // carry. |
| 837 | Base = N.getOperand(0); |
| 838 | Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); |
| 839 | return true; |
| 840 | } |
| 841 | } |
| 842 | } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { |
| 843 | // Loading from a constant address. |
| 844 | |
| 845 | // If this address fits entirely in a 16-bit sext immediate field, codegen |
| 846 | // this as "d, 0" |
| 847 | short Imm; |
| 848 | if (isIntS16Immediate(CN, Imm)) { |
| 849 | Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); |
| 850 | Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); |
| 851 | return true; |
| 852 | } |
Chris Lattner | bc681d6 | 2007-02-17 06:44:03 +0000 | [diff] [blame] | 853 | |
| 854 | // Handle 32-bit sext immediates with LIS + addr mode. |
| 855 | if (CN->getValueType(0) == MVT::i32 || |
| 856 | (int64_t)CN->getValue() == (int)CN->getValue()) { |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 857 | int Addr = (int)CN->getValue(); |
| 858 | |
| 859 | // Otherwise, break this down into an LIS + disp. |
Chris Lattner | bc681d6 | 2007-02-17 06:44:03 +0000 | [diff] [blame] | 860 | Disp = DAG.getTargetConstant((short)Addr, MVT::i32); |
| 861 | |
| 862 | Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); |
| 863 | unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; |
| 864 | Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 865 | return true; |
| 866 | } |
| 867 | } |
| 868 | |
| 869 | Disp = DAG.getTargetConstant(0, getPointerTy()); |
| 870 | if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) |
| 871 | Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); |
| 872 | else |
| 873 | Base = N; |
| 874 | return true; // [r+0] |
| 875 | } |
| 876 | |
| 877 | /// SelectAddressRegRegOnly - Given the specified addressed, force it to be |
| 878 | /// represented as an indexed [r+r] operation. |
| 879 | bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, |
| 880 | SDOperand &Index, |
| 881 | SelectionDAG &DAG) { |
| 882 | // Check to see if we can easily represent this as an [r+r] address. This |
| 883 | // will fail if it thinks that the address is more profitably represented as |
| 884 | // reg+imm, e.g. where imm = 0. |
| 885 | if (SelectAddressRegReg(N, Base, Index, DAG)) |
| 886 | return true; |
| 887 | |
| 888 | // If the operand is an addition, always emit this as [r+r], since this is |
| 889 | // better (for code size, and execution, as the memop does the add for free) |
| 890 | // than emitting an explicit add. |
| 891 | if (N.getOpcode() == ISD::ADD) { |
| 892 | Base = N.getOperand(0); |
| 893 | Index = N.getOperand(1); |
| 894 | return true; |
| 895 | } |
| 896 | |
| 897 | // Otherwise, do it the hard way, using R0 as the base register. |
| 898 | Base = DAG.getRegister(PPC::R0, N.getValueType()); |
| 899 | Index = N; |
| 900 | return true; |
| 901 | } |
| 902 | |
| 903 | /// SelectAddressRegImmShift - Returns true if the address N can be |
| 904 | /// represented by a base register plus a signed 14-bit displacement |
| 905 | /// [r+imm*4]. Suitable for use by STD and friends. |
| 906 | bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, |
| 907 | SDOperand &Base, |
| 908 | SelectionDAG &DAG) { |
| 909 | // If this can be more profitably realized as r+r, fail. |
| 910 | if (SelectAddressRegReg(N, Disp, Base, DAG)) |
| 911 | return false; |
| 912 | |
| 913 | if (N.getOpcode() == ISD::ADD) { |
| 914 | short imm = 0; |
| 915 | if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { |
| 916 | Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); |
| 917 | if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { |
| 918 | Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); |
| 919 | } else { |
| 920 | Base = N.getOperand(0); |
| 921 | } |
| 922 | return true; // [r+i] |
| 923 | } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { |
| 924 | // Match LOAD (ADD (X, Lo(G))). |
| 925 | assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() |
| 926 | && "Cannot handle constant offsets yet!"); |
| 927 | Disp = N.getOperand(1).getOperand(0); // The global address. |
| 928 | assert(Disp.getOpcode() == ISD::TargetGlobalAddress || |
| 929 | Disp.getOpcode() == ISD::TargetConstantPool || |
| 930 | Disp.getOpcode() == ISD::TargetJumpTable); |
| 931 | Base = N.getOperand(0); |
| 932 | return true; // [&g+r] |
| 933 | } |
| 934 | } else if (N.getOpcode() == ISD::OR) { |
| 935 | short imm = 0; |
| 936 | if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { |
| 937 | // If this is an or of disjoint bitfields, we can codegen this as an add |
| 938 | // (for better address arithmetic) if the LHS and RHS of the OR are |
| 939 | // provably disjoint. |
Dan Gohman | b3564aa | 2008-02-27 01:23:58 +0000 | [diff] [blame] | 940 | APInt LHSKnownZero, LHSKnownOne; |
| 941 | DAG.ComputeMaskedBits(N.getOperand(0), |
Bill Wendling | 3e98c30 | 2008-03-24 23:16:37 +0000 | [diff] [blame] | 942 | APInt::getAllOnesValue(N.getOperand(0) |
| 943 | .getValueSizeInBits()), |
Dan Gohman | b3564aa | 2008-02-27 01:23:58 +0000 | [diff] [blame] | 944 | LHSKnownZero, LHSKnownOne); |
| 945 | if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 946 | // If all of the bits are known zero on the LHS or RHS, the add won't |
| 947 | // carry. |
| 948 | Base = N.getOperand(0); |
| 949 | Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); |
| 950 | return true; |
| 951 | } |
| 952 | } |
| 953 | } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { |
Chris Lattner | dee5a5a | 2007-02-17 06:57:26 +0000 | [diff] [blame] | 954 | // Loading from a constant address. Verify low two bits are clear. |
| 955 | if ((CN->getValue() & 3) == 0) { |
| 956 | // If this address fits entirely in a 14-bit sext immediate field, codegen |
| 957 | // this as "d, 0" |
| 958 | short Imm; |
| 959 | if (isIntS16Immediate(CN, Imm)) { |
| 960 | Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); |
| 961 | Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); |
| 962 | return true; |
| 963 | } |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 964 | |
Chris Lattner | dee5a5a | 2007-02-17 06:57:26 +0000 | [diff] [blame] | 965 | // Fold the low-part of 32-bit absolute addresses into addr mode. |
| 966 | if (CN->getValueType(0) == MVT::i32 || |
| 967 | (int64_t)CN->getValue() == (int)CN->getValue()) { |
| 968 | int Addr = (int)CN->getValue(); |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 969 | |
Chris Lattner | dee5a5a | 2007-02-17 06:57:26 +0000 | [diff] [blame] | 970 | // Otherwise, break this down into an LIS + disp. |
| 971 | Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); |
| 972 | |
| 973 | Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); |
| 974 | unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; |
| 975 | Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); |
| 976 | return true; |
| 977 | } |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 978 | } |
| 979 | } |
| 980 | |
| 981 | Disp = DAG.getTargetConstant(0, getPointerTy()); |
| 982 | if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) |
| 983 | Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); |
| 984 | else |
| 985 | Base = N; |
| 986 | return true; // [r+0] |
| 987 | } |
| 988 | |
| 989 | |
| 990 | /// getPreIndexedAddressParts - returns true by value, base pointer and |
| 991 | /// offset pointer and addressing mode by reference if the node's address |
| 992 | /// can be legally represented as pre-indexed load / store address. |
| 993 | bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, |
| 994 | SDOperand &Offset, |
Evan Cheng | 144d8f0 | 2006-11-09 17:55:04 +0000 | [diff] [blame] | 995 | ISD::MemIndexedMode &AM, |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 996 | SelectionDAG &DAG) { |
Chris Lattner | 4eab714 | 2006-11-10 02:08:47 +0000 | [diff] [blame] | 997 | // Disabled by default for now. |
| 998 | if (!EnablePPCPreinc) return false; |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 999 | |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 1000 | SDOperand Ptr; |
Chris Lattner | 2fe4bf4 | 2006-11-14 01:38:31 +0000 | [diff] [blame] | 1001 | MVT::ValueType VT; |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 1002 | if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { |
| 1003 | Ptr = LD->getBasePtr(); |
Dan Gohman | b625f2f | 2008-01-30 00:15:11 +0000 | [diff] [blame] | 1004 | VT = LD->getMemoryVT(); |
Chris Lattner | 0851b4f | 2006-11-15 19:55:13 +0000 | [diff] [blame] | 1005 | |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 1006 | } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { |
Chris Lattner | 4eab714 | 2006-11-10 02:08:47 +0000 | [diff] [blame] | 1007 | ST = ST; |
Chris Lattner | 2fe4bf4 | 2006-11-14 01:38:31 +0000 | [diff] [blame] | 1008 | Ptr = ST->getBasePtr(); |
Dan Gohman | b625f2f | 2008-01-30 00:15:11 +0000 | [diff] [blame] | 1009 | VT = ST->getMemoryVT(); |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 1010 | } else |
| 1011 | return false; |
| 1012 | |
Chris Lattner | 2fe4bf4 | 2006-11-14 01:38:31 +0000 | [diff] [blame] | 1013 | // PowerPC doesn't have preinc load/store instructions for vectors. |
| 1014 | if (MVT::isVector(VT)) |
| 1015 | return false; |
| 1016 | |
Chris Lattner | 0851b4f | 2006-11-15 19:55:13 +0000 | [diff] [blame] | 1017 | // TODO: Check reg+reg first. |
| 1018 | |
| 1019 | // LDU/STU use reg+imm*4, others use reg+imm. |
| 1020 | if (VT != MVT::i64) { |
| 1021 | // reg + imm |
| 1022 | if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) |
| 1023 | return false; |
| 1024 | } else { |
| 1025 | // reg + imm * 4. |
| 1026 | if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) |
| 1027 | return false; |
| 1028 | } |
Chris Lattner | f6edf4d | 2006-11-11 00:08:42 +0000 | [diff] [blame] | 1029 | |
Chris Lattner | f6edf4d | 2006-11-11 00:08:42 +0000 | [diff] [blame] | 1030 | if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { |
Chris Lattner | 0851b4f | 2006-11-15 19:55:13 +0000 | [diff] [blame] | 1031 | // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of |
| 1032 | // sext i32 to i64 when addr mode is r+i. |
Dan Gohman | b625f2f | 2008-01-30 00:15:11 +0000 | [diff] [blame] | 1033 | if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && |
Chris Lattner | f6edf4d | 2006-11-11 00:08:42 +0000 | [diff] [blame] | 1034 | LD->getExtensionType() == ISD::SEXTLOAD && |
| 1035 | isa<ConstantSDNode>(Offset)) |
| 1036 | return false; |
Chris Lattner | 0851b4f | 2006-11-15 19:55:13 +0000 | [diff] [blame] | 1037 | } |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 1038 | |
Chris Lattner | 4eab714 | 2006-11-10 02:08:47 +0000 | [diff] [blame] | 1039 | AM = ISD::PRE_INC; |
| 1040 | return true; |
Chris Lattner | fc5b1ab | 2006-11-08 02:15:41 +0000 | [diff] [blame] | 1041 | } |
| 1042 | |
| 1043 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1044 | // LowerOperation implementation |
| 1045 | //===----------------------------------------------------------------------===// |
| 1046 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 1047 | SDOperand PPCTargetLowering::LowerConstantPool(SDOperand Op, |
| 1048 | SelectionDAG &DAG) { |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1049 | MVT::ValueType PtrVT = Op.getValueType(); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1050 | ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); |
Evan Cheng | c356a57 | 2006-09-12 21:04:05 +0000 | [diff] [blame] | 1051 | Constant *C = CP->getConstVal(); |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1052 | SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); |
| 1053 | SDOperand Zero = DAG.getConstant(0, PtrVT); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1054 | |
| 1055 | const TargetMachine &TM = DAG.getTarget(); |
| 1056 | |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1057 | SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); |
| 1058 | SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); |
| 1059 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1060 | // If this is a non-darwin platform, we don't support non-static relo models |
| 1061 | // yet. |
| 1062 | if (TM.getRelocationModel() == Reloc::Static || |
| 1063 | !TM.getSubtarget<PPCSubtarget>().isDarwin()) { |
| 1064 | // Generate non-pic code that has direct accesses to the constant pool. |
| 1065 | // The address of the global is just (hi(&g)+lo(&g)). |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1066 | return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1067 | } |
| 1068 | |
Chris Lattner | 35d86fe | 2006-07-26 21:12:04 +0000 | [diff] [blame] | 1069 | if (TM.getRelocationModel() == Reloc::PIC_) { |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1070 | // With PIC, the first instruction is actually "GR+hi(&G)". |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1071 | Hi = DAG.getNode(ISD::ADD, PtrVT, |
| 1072 | DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1073 | } |
| 1074 | |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1075 | Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1076 | return Lo; |
| 1077 | } |
| 1078 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 1079 | SDOperand PPCTargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1080 | MVT::ValueType PtrVT = Op.getValueType(); |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 1081 | JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1082 | SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); |
| 1083 | SDOperand Zero = DAG.getConstant(0, PtrVT); |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 1084 | |
| 1085 | const TargetMachine &TM = DAG.getTarget(); |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1086 | |
| 1087 | SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); |
| 1088 | SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); |
| 1089 | |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 1090 | // If this is a non-darwin platform, we don't support non-static relo models |
| 1091 | // yet. |
| 1092 | if (TM.getRelocationModel() == Reloc::Static || |
| 1093 | !TM.getSubtarget<PPCSubtarget>().isDarwin()) { |
| 1094 | // Generate non-pic code that has direct accesses to the constant pool. |
| 1095 | // The address of the global is just (hi(&g)+lo(&g)). |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1096 | return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 1097 | } |
| 1098 | |
Chris Lattner | 35d86fe | 2006-07-26 21:12:04 +0000 | [diff] [blame] | 1099 | if (TM.getRelocationModel() == Reloc::PIC_) { |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 1100 | // With PIC, the first instruction is actually "GR+hi(&G)". |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1101 | Hi = DAG.getNode(ISD::ADD, PtrVT, |
Chris Lattner | 0d72a20 | 2006-07-28 16:45:47 +0000 | [diff] [blame] | 1102 | DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 1103 | } |
| 1104 | |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1105 | Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 1106 | return Lo; |
| 1107 | } |
| 1108 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 1109 | SDOperand PPCTargetLowering::LowerGlobalTLSAddress(SDOperand Op, |
| 1110 | SelectionDAG &DAG) { |
Lauro Ramos Venancio | 75ce010 | 2007-07-11 17:19:51 +0000 | [diff] [blame] | 1111 | assert(0 && "TLS not implemented for PPC."); |
Chris Lattner | d27c991 | 2008-03-30 18:22:13 +0000 | [diff] [blame] | 1112 | return SDOperand(); // Not reached |
Lauro Ramos Venancio | 75ce010 | 2007-07-11 17:19:51 +0000 | [diff] [blame] | 1113 | } |
| 1114 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 1115 | SDOperand PPCTargetLowering::LowerGlobalAddress(SDOperand Op, |
| 1116 | SelectionDAG &DAG) { |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1117 | MVT::ValueType PtrVT = Op.getValueType(); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1118 | GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); |
| 1119 | GlobalValue *GV = GSDN->getGlobal(); |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1120 | SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); |
Evan Cheng | fcf5d4f | 2008-02-02 05:06:29 +0000 | [diff] [blame] | 1121 | // If it's a debug information descriptor, don't mess with it. |
| 1122 | if (DAG.isVerifiedDebugInfoDesc(Op)) |
| 1123 | return GA; |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1124 | SDOperand Zero = DAG.getConstant(0, PtrVT); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1125 | |
| 1126 | const TargetMachine &TM = DAG.getTarget(); |
| 1127 | |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1128 | SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); |
| 1129 | SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); |
| 1130 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1131 | // If this is a non-darwin platform, we don't support non-static relo models |
| 1132 | // yet. |
| 1133 | if (TM.getRelocationModel() == Reloc::Static || |
| 1134 | !TM.getSubtarget<PPCSubtarget>().isDarwin()) { |
| 1135 | // Generate non-pic code that has direct accesses to globals. |
| 1136 | // The address of the global is just (hi(&g)+lo(&g)). |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1137 | return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1138 | } |
| 1139 | |
Chris Lattner | 35d86fe | 2006-07-26 21:12:04 +0000 | [diff] [blame] | 1140 | if (TM.getRelocationModel() == Reloc::PIC_) { |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1141 | // With PIC, the first instruction is actually "GR+hi(&G)". |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1142 | Hi = DAG.getNode(ISD::ADD, PtrVT, |
| 1143 | DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1144 | } |
| 1145 | |
Chris Lattner | 059ca0f | 2006-06-16 21:01:35 +0000 | [diff] [blame] | 1146 | Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1147 | |
Chris Lattner | 57fc62c | 2006-12-11 23:22:45 +0000 | [diff] [blame] | 1148 | if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV)) |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1149 | return Lo; |
| 1150 | |
| 1151 | // If the global is weak or external, we have to go through the lazy |
| 1152 | // resolution stub. |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 1153 | return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1154 | } |
| 1155 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 1156 | SDOperand PPCTargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) { |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1157 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); |
| 1158 | |
| 1159 | // If we're comparing for equality to zero, expose the fact that this is |
| 1160 | // implented as a ctlz/srl pair on ppc, so that the dag combiner can |
| 1161 | // fold the new nodes. |
| 1162 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { |
| 1163 | if (C->isNullValue() && CC == ISD::SETEQ) { |
| 1164 | MVT::ValueType VT = Op.getOperand(0).getValueType(); |
| 1165 | SDOperand Zext = Op.getOperand(0); |
| 1166 | if (VT < MVT::i32) { |
| 1167 | VT = MVT::i32; |
| 1168 | Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); |
| 1169 | } |
| 1170 | unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); |
| 1171 | SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); |
| 1172 | SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, |
| 1173 | DAG.getConstant(Log2b, MVT::i32)); |
| 1174 | return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); |
| 1175 | } |
| 1176 | // Leave comparisons against 0 and -1 alone for now, since they're usually |
| 1177 | // optimized. FIXME: revisit this when we can custom lower all setcc |
| 1178 | // optimizations. |
| 1179 | if (C->isAllOnesValue() || C->isNullValue()) |
| 1180 | return SDOperand(); |
| 1181 | } |
| 1182 | |
| 1183 | // If we have an integer seteq/setne, turn it into a compare against zero |
Chris Lattner | ac011bc | 2006-11-14 05:28:08 +0000 | [diff] [blame] | 1184 | // by xor'ing the rhs with the lhs, which is faster than setting a |
| 1185 | // condition register, reading it back out, and masking the correct bit. The |
| 1186 | // normal approach here uses sub to do this instead of xor. Using xor exposes |
| 1187 | // the result to other bit-twiddling opportunities. |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1188 | MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); |
| 1189 | if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { |
| 1190 | MVT::ValueType VT = Op.getValueType(); |
Chris Lattner | ac011bc | 2006-11-14 05:28:08 +0000 | [diff] [blame] | 1191 | SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1192 | Op.getOperand(1)); |
| 1193 | return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); |
| 1194 | } |
| 1195 | return SDOperand(); |
| 1196 | } |
| 1197 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 1198 | SDOperand PPCTargetLowering::LowerVAARG(SDOperand Op, SelectionDAG &DAG, |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1199 | int VarArgsFrameIndex, |
| 1200 | int VarArgsStackOffset, |
| 1201 | unsigned VarArgsNumGPR, |
| 1202 | unsigned VarArgsNumFPR, |
| 1203 | const PPCSubtarget &Subtarget) { |
| 1204 | |
| 1205 | assert(0 && "VAARG in ELF32 ABI not implemented yet!"); |
Chris Lattner | d27c991 | 2008-03-30 18:22:13 +0000 | [diff] [blame] | 1206 | return SDOperand(); // Not reached |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1207 | } |
| 1208 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 1209 | SDOperand PPCTargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG, |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1210 | int VarArgsFrameIndex, |
| 1211 | int VarArgsStackOffset, |
| 1212 | unsigned VarArgsNumGPR, |
| 1213 | unsigned VarArgsNumFPR, |
| 1214 | const PPCSubtarget &Subtarget) { |
| 1215 | |
| 1216 | if (Subtarget.isMachoABI()) { |
| 1217 | // vastart just stores the address of the VarArgsFrameIndex slot into the |
| 1218 | // memory location argument. |
| 1219 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
| 1220 | SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 1221 | const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); |
| 1222 | return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1223 | } |
| 1224 | |
| 1225 | // For ELF 32 ABI we follow the layout of the va_list struct. |
| 1226 | // We suppose the given va_list is already allocated. |
| 1227 | // |
| 1228 | // typedef struct { |
| 1229 | // char gpr; /* index into the array of 8 GPRs |
| 1230 | // * stored in the register save area |
| 1231 | // * gpr=0 corresponds to r3, |
| 1232 | // * gpr=1 to r4, etc. |
| 1233 | // */ |
| 1234 | // char fpr; /* index into the array of 8 FPRs |
| 1235 | // * stored in the register save area |
| 1236 | // * fpr=0 corresponds to f1, |
| 1237 | // * fpr=1 to f2, etc. |
| 1238 | // */ |
| 1239 | // char *overflow_arg_area; |
| 1240 | // /* location on stack that holds |
| 1241 | // * the next overflow argument |
| 1242 | // */ |
| 1243 | // char *reg_save_area; |
| 1244 | // /* where r3:r10 and f1:f8 (if saved) |
| 1245 | // * are stored |
| 1246 | // */ |
| 1247 | // } va_list[1]; |
| 1248 | |
| 1249 | |
| 1250 | SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8); |
| 1251 | SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8); |
| 1252 | |
| 1253 | |
Chris Lattner | 0d72a20 | 2006-07-28 16:45:47 +0000 | [diff] [blame] | 1254 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1255 | |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 1256 | SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); |
Chris Lattner | 0d72a20 | 2006-07-28 16:45:47 +0000 | [diff] [blame] | 1257 | SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1258 | |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 1259 | uint64_t FrameOffset = MVT::getSizeInBits(PtrVT)/8; |
| 1260 | SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); |
| 1261 | |
| 1262 | uint64_t StackOffset = MVT::getSizeInBits(PtrVT)/8 - 1; |
| 1263 | SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); |
| 1264 | |
| 1265 | uint64_t FPROffset = 1; |
| 1266 | SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1267 | |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 1268 | const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1269 | |
| 1270 | // Store first byte : number of int regs |
| 1271 | SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 1272 | Op.getOperand(1), SV, 0); |
| 1273 | uint64_t nextOffset = FPROffset; |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1274 | SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), |
| 1275 | ConstFPROffset); |
| 1276 | |
| 1277 | // Store second byte : number of float regs |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 1278 | SDOperand secondStore = |
| 1279 | DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset); |
| 1280 | nextOffset += StackOffset; |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1281 | nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset); |
| 1282 | |
| 1283 | // Store second word : arguments given on stack |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 1284 | SDOperand thirdStore = |
| 1285 | DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset); |
| 1286 | nextOffset += FrameOffset; |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1287 | nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset); |
| 1288 | |
| 1289 | // Store third word : arguments given in registers |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 1290 | return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset); |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1291 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 1292 | } |
| 1293 | |
Chris Lattner | b9a7bea | 2007-03-06 00:59:59 +0000 | [diff] [blame] | 1294 | #include "PPCGenCallingConv.inc" |
| 1295 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1296 | /// GetFPR - Get the set of FP registers that should be allocated for arguments, |
| 1297 | /// depending on which subtarget is selected. |
| 1298 | static const unsigned *GetFPR(const PPCSubtarget &Subtarget) { |
| 1299 | if (Subtarget.isMachoABI()) { |
| 1300 | static const unsigned FPR[] = { |
| 1301 | PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, |
| 1302 | PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 |
| 1303 | }; |
| 1304 | return FPR; |
| 1305 | } |
| 1306 | |
| 1307 | |
| 1308 | static const unsigned FPR[] = { |
| 1309 | PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, |
Nicolas Geoffray | ef3c030 | 2007-04-03 10:27:07 +0000 | [diff] [blame] | 1310 | PPC::F8 |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1311 | }; |
| 1312 | return FPR; |
| 1313 | } |
| 1314 | |
Bill Wendling | 5f5bf3a | 2008-03-07 20:49:02 +0000 | [diff] [blame] | 1315 | SDOperand |
| 1316 | PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, |
| 1317 | SelectionDAG &DAG, |
| 1318 | int &VarArgsFrameIndex, |
| 1319 | int &VarArgsStackOffset, |
| 1320 | unsigned &VarArgsNumGPR, |
| 1321 | unsigned &VarArgsNumFPR, |
| 1322 | const PPCSubtarget &Subtarget) { |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1323 | // TODO: add description of PPC stack frame format, or at least some docs. |
| 1324 | // |
| 1325 | MachineFunction &MF = DAG.getMachineFunction(); |
| 1326 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 1327 | MachineRegisterInfo &RegInfo = MF.getRegInfo(); |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 1328 | SmallVector<SDOperand, 8> ArgValues; |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1329 | SDOperand Root = Op.getOperand(0); |
Dale Johannesen | 75092de | 2008-03-12 00:22:17 +0000 | [diff] [blame] | 1330 | bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1331 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1332 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
| 1333 | bool isPPC64 = PtrVT == MVT::i64; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1334 | bool isMachoABI = Subtarget.isMachoABI(); |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 1335 | bool isELF32_ABI = Subtarget.isELF32_ABI(); |
Jim Laskey | e9bd7b2 | 2006-11-28 14:53:52 +0000 | [diff] [blame] | 1336 | unsigned PtrByteSize = isPPC64 ? 8 : 4; |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1337 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1338 | unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1339 | |
| 1340 | static const unsigned GPR_32[] = { // 32-bit registers. |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1341 | PPC::R3, PPC::R4, PPC::R5, PPC::R6, |
| 1342 | PPC::R7, PPC::R8, PPC::R9, PPC::R10, |
| 1343 | }; |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1344 | static const unsigned GPR_64[] = { // 64-bit registers. |
| 1345 | PPC::X3, PPC::X4, PPC::X5, PPC::X6, |
| 1346 | PPC::X7, PPC::X8, PPC::X9, PPC::X10, |
| 1347 | }; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1348 | |
| 1349 | static const unsigned *FPR = GetFPR(Subtarget); |
| 1350 | |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1351 | static const unsigned VR[] = { |
| 1352 | PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, |
| 1353 | PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 |
| 1354 | }; |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1355 | |
Owen Anderson | 718cb66 | 2007-09-07 04:06:50 +0000 | [diff] [blame] | 1356 | const unsigned Num_GPR_Regs = array_lengthof(GPR_32); |
Nicolas Geoffray | ef3c030 | 2007-04-03 10:27:07 +0000 | [diff] [blame] | 1357 | const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8; |
Owen Anderson | 718cb66 | 2007-09-07 04:06:50 +0000 | [diff] [blame] | 1358 | const unsigned Num_VR_Regs = array_lengthof( VR); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1359 | |
| 1360 | unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; |
| 1361 | |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1362 | const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1363 | |
Dale Johannesen | 8f5422c | 2008-03-14 17:41:26 +0000 | [diff] [blame] | 1364 | // In 32-bit non-varargs functions, the stack space for vectors is after the |
| 1365 | // stack space for non-vectors. We do not use this space unless we have |
| 1366 | // too many vectors to fit in registers, something that only occurs in |
| 1367 | // constructed examples:), but we have to walk the arglist to figure |
| 1368 | // that out...for the pathological case, compute VecArgOffset as the |
| 1369 | // start of the vector parameter area. Computing VecArgOffset is the |
| 1370 | // entire point of the following loop. |
| 1371 | // Altivec is not mentioned in the ppc32 Elf Supplement, so I'm not trying |
| 1372 | // to handle Elf here. |
| 1373 | unsigned VecArgOffset = ArgOffset; |
| 1374 | if (!isVarArg && !isPPC64) { |
| 1375 | for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; |
| 1376 | ++ArgNo) { |
| 1377 | MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); |
| 1378 | unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1379 | ISD::ArgFlagsTy Flags = |
| 1380 | cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags(); |
Dale Johannesen | 8f5422c | 2008-03-14 17:41:26 +0000 | [diff] [blame] | 1381 | |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1382 | if (Flags.isByVal()) { |
Dale Johannesen | 8f5422c | 2008-03-14 17:41:26 +0000 | [diff] [blame] | 1383 | // ObjSize is the true size, ArgSize rounded up to multiple of regs. |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1384 | ObjSize = Flags.getByValSize(); |
Dale Johannesen | 8f5422c | 2008-03-14 17:41:26 +0000 | [diff] [blame] | 1385 | unsigned ArgSize = |
| 1386 | ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; |
| 1387 | VecArgOffset += ArgSize; |
| 1388 | continue; |
| 1389 | } |
| 1390 | |
| 1391 | switch(ObjectVT) { |
| 1392 | default: assert(0 && "Unhandled argument type!"); |
| 1393 | case MVT::i32: |
| 1394 | case MVT::f32: |
| 1395 | VecArgOffset += isPPC64 ? 8 : 4; |
| 1396 | break; |
| 1397 | case MVT::i64: // PPC64 |
| 1398 | case MVT::f64: |
| 1399 | VecArgOffset += 8; |
| 1400 | break; |
| 1401 | case MVT::v4f32: |
| 1402 | case MVT::v4i32: |
| 1403 | case MVT::v8i16: |
| 1404 | case MVT::v16i8: |
| 1405 | // Nothing to do, we're only looking at Nonvector args here. |
| 1406 | break; |
| 1407 | } |
| 1408 | } |
| 1409 | } |
| 1410 | // We've found where the vector parameter area in memory is. Skip the |
| 1411 | // first 12 parameters; these don't use that memory. |
| 1412 | VecArgOffset = ((VecArgOffset+15)/16)*16; |
| 1413 | VecArgOffset += 12*16; |
| 1414 | |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1415 | // Add DAG nodes to load the arguments or copy them out of registers. On |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1416 | // entry to a function on PPC, the arguments start after the linkage area, |
| 1417 | // although the first ones are often in registers. |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1418 | // |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 1419 | // In the ELF 32 ABI, GPRs and stack are double word align: an argument |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1420 | // represented with two words (long long or double) must be copied to an |
Nicolas Geoffray | c0cb28f | 2008-04-13 13:40:22 +0000 | [diff] [blame] | 1421 | // even GPR_idx value or to an even ArgOffset value. |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1422 | |
Dale Johannesen | 8419dd6 | 2008-03-07 20:27:40 +0000 | [diff] [blame] | 1423 | SmallVector<SDOperand, 8> MemOps; |
| 1424 | |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1425 | for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { |
| 1426 | SDOperand ArgVal; |
| 1427 | bool needsLoad = false; |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1428 | MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); |
| 1429 | unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; |
Jim Laskey | 619965d | 2006-11-29 13:37:09 +0000 | [diff] [blame] | 1430 | unsigned ArgSize = ObjSize; |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1431 | ISD::ArgFlagsTy Flags = |
| 1432 | cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags(); |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1433 | // See if next argument requires stack alignment in ELF |
Nicolas Geoffray | 6ccbbd8 | 2008-04-15 08:08:50 +0000 | [diff] [blame] | 1434 | bool Align = Flags.isSplit(); |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1435 | |
Chris Lattner | be4849a | 2006-05-16 18:51:52 +0000 | [diff] [blame] | 1436 | unsigned CurArgOffset = ArgOffset; |
Dale Johannesen | 8419dd6 | 2008-03-07 20:27:40 +0000 | [diff] [blame] | 1437 | |
| 1438 | // FIXME alignment for ELF may not be right |
| 1439 | // FIXME the codegen can be much improved in some cases. |
| 1440 | // We do not have to keep everything in memory. |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1441 | if (Flags.isByVal()) { |
Dale Johannesen | 8419dd6 | 2008-03-07 20:27:40 +0000 | [diff] [blame] | 1442 | // ObjSize is the true size, ArgSize rounded up to multiple of registers. |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1443 | ObjSize = Flags.getByValSize(); |
Dale Johannesen | 8419dd6 | 2008-03-07 20:27:40 +0000 | [diff] [blame] | 1444 | ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; |
Dale Johannesen | 7f96f39 | 2008-03-08 01:41:42 +0000 | [diff] [blame] | 1445 | // Double word align in ELF |
Nicolas Geoffray | c0cb28f | 2008-04-13 13:40:22 +0000 | [diff] [blame] | 1446 | if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2); |
Dale Johannesen | 7f96f39 | 2008-03-08 01:41:42 +0000 | [diff] [blame] | 1447 | // Objects of size 1 and 2 are right justified, everything else is |
| 1448 | // left justified. This means the memory address is adjusted forwards. |
| 1449 | if (ObjSize==1 || ObjSize==2) { |
| 1450 | CurArgOffset = CurArgOffset + (4 - ObjSize); |
| 1451 | } |
Dale Johannesen | 8419dd6 | 2008-03-07 20:27:40 +0000 | [diff] [blame] | 1452 | // The value of the object is its address. |
| 1453 | int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset); |
| 1454 | SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); |
| 1455 | ArgValues.push_back(FIN); |
Dale Johannesen | 7f96f39 | 2008-03-08 01:41:42 +0000 | [diff] [blame] | 1456 | if (ObjSize==1 || ObjSize==2) { |
| 1457 | if (GPR_idx != Num_GPR_Regs) { |
| 1458 | unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); |
| 1459 | RegInfo.addLiveIn(GPR[GPR_idx], VReg); |
| 1460 | SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); |
| 1461 | SDOperand Store = DAG.getTruncStore(Val.getValue(1), Val, FIN, |
| 1462 | NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 ); |
| 1463 | MemOps.push_back(Store); |
| 1464 | ++GPR_idx; |
| 1465 | if (isMachoABI) ArgOffset += PtrByteSize; |
| 1466 | } else { |
| 1467 | ArgOffset += PtrByteSize; |
| 1468 | } |
| 1469 | continue; |
| 1470 | } |
Dale Johannesen | 8419dd6 | 2008-03-07 20:27:40 +0000 | [diff] [blame] | 1471 | for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { |
| 1472 | // Store whatever pieces of the object are in registers |
| 1473 | // to memory. ArgVal will be address of the beginning of |
| 1474 | // the object. |
| 1475 | if (GPR_idx != Num_GPR_Regs) { |
| 1476 | unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); |
| 1477 | RegInfo.addLiveIn(GPR[GPR_idx], VReg); |
| 1478 | int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset); |
| 1479 | SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); |
| 1480 | SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); |
| 1481 | SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); |
| 1482 | MemOps.push_back(Store); |
| 1483 | ++GPR_idx; |
| 1484 | if (isMachoABI) ArgOffset += PtrByteSize; |
| 1485 | } else { |
| 1486 | ArgOffset += ArgSize - (ArgOffset-CurArgOffset); |
| 1487 | break; |
| 1488 | } |
| 1489 | } |
| 1490 | continue; |
| 1491 | } |
| 1492 | |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1493 | switch (ObjectVT) { |
| 1494 | default: assert(0 && "Unhandled argument type!"); |
| 1495 | case MVT::i32: |
Bill Wendling | 5f5bf3a | 2008-03-07 20:49:02 +0000 | [diff] [blame] | 1496 | if (!isPPC64) { |
| 1497 | // Double word align in ELF |
Nicolas Geoffray | c0cb28f | 2008-04-13 13:40:22 +0000 | [diff] [blame] | 1498 | if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2); |
Bill Wendling | 5f5bf3a | 2008-03-07 20:49:02 +0000 | [diff] [blame] | 1499 | |
| 1500 | if (GPR_idx != Num_GPR_Regs) { |
| 1501 | unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); |
| 1502 | RegInfo.addLiveIn(GPR[GPR_idx], VReg); |
| 1503 | ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); |
| 1504 | ++GPR_idx; |
| 1505 | } else { |
| 1506 | needsLoad = true; |
| 1507 | ArgSize = PtrByteSize; |
| 1508 | } |
| 1509 | // Stack align in ELF |
Nicolas Geoffray | c0cb28f | 2008-04-13 13:40:22 +0000 | [diff] [blame] | 1510 | if (needsLoad && Align && isELF32_ABI) |
Bill Wendling | 5f5bf3a | 2008-03-07 20:49:02 +0000 | [diff] [blame] | 1511 | ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; |
| 1512 | // All int arguments reserve stack space in Macho ABI. |
| 1513 | if (isMachoABI || needsLoad) ArgOffset += PtrByteSize; |
| 1514 | break; |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1515 | } |
Bill Wendling | 5f5bf3a | 2008-03-07 20:49:02 +0000 | [diff] [blame] | 1516 | // FALLTHROUGH |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1517 | case MVT::i64: // PPC64 |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1518 | if (GPR_idx != Num_GPR_Regs) { |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 1519 | unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); |
| 1520 | RegInfo.addLiveIn(GPR[GPR_idx], VReg); |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1521 | ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); |
Bill Wendling | 5f5bf3a | 2008-03-07 20:49:02 +0000 | [diff] [blame] | 1522 | |
| 1523 | if (ObjectVT == MVT::i32) { |
| 1524 | // PPC64 passes i8, i16, and i32 values in i64 registers. Promote |
| 1525 | // value to MVT::i64 and then truncate to the correct register size. |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1526 | if (Flags.isSExt()) |
Bill Wendling | 5f5bf3a | 2008-03-07 20:49:02 +0000 | [diff] [blame] | 1527 | ArgVal = DAG.getNode(ISD::AssertSext, MVT::i64, ArgVal, |
| 1528 | DAG.getValueType(ObjectVT)); |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1529 | else if (Flags.isZExt()) |
Bill Wendling | 5f5bf3a | 2008-03-07 20:49:02 +0000 | [diff] [blame] | 1530 | ArgVal = DAG.getNode(ISD::AssertZext, MVT::i64, ArgVal, |
| 1531 | DAG.getValueType(ObjectVT)); |
| 1532 | |
| 1533 | ArgVal = DAG.getNode(ISD::TRUNCATE, MVT::i32, ArgVal); |
| 1534 | } |
| 1535 | |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1536 | ++GPR_idx; |
| 1537 | } else { |
| 1538 | needsLoad = true; |
| 1539 | } |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1540 | // All int arguments reserve stack space in Macho ABI. |
| 1541 | if (isMachoABI || needsLoad) ArgOffset += 8; |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1542 | break; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1543 | |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1544 | case MVT::f32: |
| 1545 | case MVT::f64: |
Chris Lattner | be4849a | 2006-05-16 18:51:52 +0000 | [diff] [blame] | 1546 | // Every 4 bytes of argument space consumes one of the GPRs available for |
| 1547 | // argument passing. |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1548 | if (GPR_idx != Num_GPR_Regs && isMachoABI) { |
Chris Lattner | af4ec0c | 2006-05-16 18:58:15 +0000 | [diff] [blame] | 1549 | ++GPR_idx; |
Chris Lattner | b1eb987 | 2006-11-18 01:57:19 +0000 | [diff] [blame] | 1550 | if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) |
Chris Lattner | af4ec0c | 2006-05-16 18:58:15 +0000 | [diff] [blame] | 1551 | ++GPR_idx; |
Chris Lattner | be4849a | 2006-05-16 18:51:52 +0000 | [diff] [blame] | 1552 | } |
Chris Lattner | af4ec0c | 2006-05-16 18:58:15 +0000 | [diff] [blame] | 1553 | if (FPR_idx != Num_FPR_Regs) { |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1554 | unsigned VReg; |
| 1555 | if (ObjectVT == MVT::f32) |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 1556 | VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass); |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1557 | else |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 1558 | VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); |
| 1559 | RegInfo.addLiveIn(FPR[FPR_idx], VReg); |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1560 | ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1561 | ++FPR_idx; |
| 1562 | } else { |
| 1563 | needsLoad = true; |
| 1564 | } |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1565 | |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1566 | // Stack align in ELF |
Nicolas Geoffray | c0cb28f | 2008-04-13 13:40:22 +0000 | [diff] [blame] | 1567 | if (needsLoad && Align && isELF32_ABI) |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1568 | ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1569 | // All FP arguments reserve stack space in Macho ABI. |
| 1570 | if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize; |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1571 | break; |
| 1572 | case MVT::v4f32: |
| 1573 | case MVT::v4i32: |
| 1574 | case MVT::v8i16: |
| 1575 | case MVT::v16i8: |
Dale Johannesen | 75092de | 2008-03-12 00:22:17 +0000 | [diff] [blame] | 1576 | // Note that vector arguments in registers don't reserve stack space, |
| 1577 | // except in varargs functions. |
Chris Lattner | af4ec0c | 2006-05-16 18:58:15 +0000 | [diff] [blame] | 1578 | if (VR_idx != Num_VR_Regs) { |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 1579 | unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass); |
| 1580 | RegInfo.addLiveIn(VR[VR_idx], VReg); |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1581 | ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); |
Dale Johannesen | 75092de | 2008-03-12 00:22:17 +0000 | [diff] [blame] | 1582 | if (isVarArg) { |
| 1583 | while ((ArgOffset % 16) != 0) { |
| 1584 | ArgOffset += PtrByteSize; |
| 1585 | if (GPR_idx != Num_GPR_Regs) |
| 1586 | GPR_idx++; |
| 1587 | } |
| 1588 | ArgOffset += 16; |
| 1589 | GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); |
| 1590 | } |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1591 | ++VR_idx; |
| 1592 | } else { |
Dale Johannesen | 8f5422c | 2008-03-14 17:41:26 +0000 | [diff] [blame] | 1593 | if (!isVarArg && !isPPC64) { |
| 1594 | // Vectors go after all the nonvectors. |
| 1595 | CurArgOffset = VecArgOffset; |
| 1596 | VecArgOffset += 16; |
| 1597 | } else { |
| 1598 | // Vectors are aligned. |
| 1599 | ArgOffset = ((ArgOffset+15)/16)*16; |
| 1600 | CurArgOffset = ArgOffset; |
| 1601 | ArgOffset += 16; |
Dale Johannesen | 404d990 | 2008-03-12 00:49:20 +0000 | [diff] [blame] | 1602 | } |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1603 | needsLoad = true; |
| 1604 | } |
| 1605 | break; |
| 1606 | } |
| 1607 | |
| 1608 | // We need to load the argument to a virtual register if we determined above |
Chris Lattner | 9f72d1a | 2008-02-13 07:35:30 +0000 | [diff] [blame] | 1609 | // that we ran out of physical registers of the appropriate type. |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1610 | if (needsLoad) { |
Chris Lattner | 9f72d1a | 2008-02-13 07:35:30 +0000 | [diff] [blame] | 1611 | int FI = MFI->CreateFixedObject(ObjSize, |
| 1612 | CurArgOffset + (ArgSize - ObjSize)); |
| 1613 | SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); |
| 1614 | ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1615 | } |
| 1616 | |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1617 | ArgValues.push_back(ArgVal); |
| 1618 | } |
Dale Johannesen | 8419dd6 | 2008-03-07 20:27:40 +0000 | [diff] [blame] | 1619 | |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1620 | // If the function takes variable number of arguments, make a frame index for |
| 1621 | // the start of the first vararg value... for expansion of llvm.va_start. |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1622 | if (isVarArg) { |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1623 | |
| 1624 | int depth; |
| 1625 | if (isELF32_ABI) { |
| 1626 | VarArgsNumGPR = GPR_idx; |
| 1627 | VarArgsNumFPR = FPR_idx; |
| 1628 | |
| 1629 | // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame |
| 1630 | // pointer. |
| 1631 | depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 + |
| 1632 | Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 + |
| 1633 | MVT::getSizeInBits(PtrVT)/8); |
| 1634 | |
| 1635 | VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, |
| 1636 | ArgOffset); |
| 1637 | |
| 1638 | } |
| 1639 | else |
| 1640 | depth = ArgOffset; |
| 1641 | |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1642 | VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1643 | depth); |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1644 | SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1645 | |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1646 | // In ELF 32 ABI, the fixed integer arguments of a variadic function are |
| 1647 | // stored to the VarArgsFrameIndex on the stack. |
| 1648 | if (isELF32_ABI) { |
| 1649 | for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) { |
| 1650 | SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT); |
| 1651 | SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); |
| 1652 | MemOps.push_back(Store); |
| 1653 | // Increment the address by four for the next argument to store |
| 1654 | SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); |
| 1655 | FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); |
| 1656 | } |
| 1657 | } |
| 1658 | |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1659 | // If this function is vararg, store any remaining integer argument regs |
| 1660 | // to their spots on the stack so that they may be loaded by deferencing the |
| 1661 | // result of va_next. |
Chris Lattner | af4ec0c | 2006-05-16 18:58:15 +0000 | [diff] [blame] | 1662 | for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { |
Chris Lattner | b1eb987 | 2006-11-18 01:57:19 +0000 | [diff] [blame] | 1663 | unsigned VReg; |
| 1664 | if (isPPC64) |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 1665 | VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); |
Chris Lattner | b1eb987 | 2006-11-18 01:57:19 +0000 | [diff] [blame] | 1666 | else |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 1667 | VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); |
Chris Lattner | b1eb987 | 2006-11-18 01:57:19 +0000 | [diff] [blame] | 1668 | |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 1669 | RegInfo.addLiveIn(GPR[GPR_idx], VReg); |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1670 | SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); |
Evan Cheng | 8b2794a | 2006-10-13 21:14:26 +0000 | [diff] [blame] | 1671 | SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1672 | MemOps.push_back(Store); |
| 1673 | // Increment the address by four for the next argument to store |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1674 | SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); |
| 1675 | FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1676 | } |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1677 | |
| 1678 | // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex |
| 1679 | // on the stack. |
| 1680 | if (isELF32_ABI) { |
| 1681 | for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) { |
| 1682 | SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64); |
| 1683 | SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); |
| 1684 | MemOps.push_back(Store); |
| 1685 | // Increment the address by eight for the next argument to store |
| 1686 | SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, |
| 1687 | PtrVT); |
| 1688 | FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); |
| 1689 | } |
| 1690 | |
| 1691 | for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) { |
| 1692 | unsigned VReg; |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 1693 | VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1694 | |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 1695 | RegInfo.addLiveIn(FPR[FPR_idx], VReg); |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 1696 | SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64); |
| 1697 | SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); |
| 1698 | MemOps.push_back(Store); |
| 1699 | // Increment the address by eight for the next argument to store |
| 1700 | SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, |
| 1701 | PtrVT); |
| 1702 | FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); |
| 1703 | } |
| 1704 | } |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1705 | } |
| 1706 | |
Dale Johannesen | 8419dd6 | 2008-03-07 20:27:40 +0000 | [diff] [blame] | 1707 | if (!MemOps.empty()) |
| 1708 | Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); |
| 1709 | |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1710 | ArgValues.push_back(Root); |
| 1711 | |
| 1712 | // Return the new list of results. |
| 1713 | std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), |
| 1714 | Op.Val->value_end()); |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 1715 | return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); |
Chris Lattner | 8ab5fe5 | 2006-05-16 18:18:50 +0000 | [diff] [blame] | 1716 | } |
| 1717 | |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 1718 | /// isCallCompatibleAddress - Return the immediate to use if the specified |
| 1719 | /// 32-bit value is representable in the immediate field of a BxA instruction. |
| 1720 | static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) { |
| 1721 | ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); |
| 1722 | if (!C) return 0; |
| 1723 | |
| 1724 | int Addr = C->getValue(); |
| 1725 | if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. |
| 1726 | (Addr << 6 >> 6) != Addr) |
| 1727 | return 0; // Top 6 bits have to be sext of immediate. |
| 1728 | |
Evan Cheng | 3311876 | 2007-10-22 19:46:19 +0000 | [diff] [blame] | 1729 | return DAG.getConstant((int)C->getValue() >> 2, |
| 1730 | DAG.getTargetLoweringInfo().getPointerTy()).Val; |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 1731 | } |
| 1732 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 1733 | /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified |
| 1734 | /// by "Src" to address "Dst" of size "Size". Alignment information is |
| 1735 | /// specified by the specific parameter attribute. The copy will be passed as |
| 1736 | /// a byval function parameter. |
| 1737 | /// Sometimes what we are copying is the end of a larger object, the part that |
| 1738 | /// does not fit in registers. |
| 1739 | static SDOperand |
| 1740 | CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain, |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1741 | ISD::ArgFlagsTy Flags, SelectionDAG &DAG, |
| 1742 | unsigned Size) { |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 1743 | SDOperand SizeNode = DAG.getConstant(Size, MVT::i32); |
| 1744 | return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(), false, |
| 1745 | NULL, 0, NULL, 0); |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 1746 | } |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1747 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 1748 | SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, |
Dan Gohman | 7925ed0 | 2008-03-19 21:39:28 +0000 | [diff] [blame] | 1749 | const PPCSubtarget &Subtarget, |
| 1750 | TargetMachine &TM) { |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1751 | SDOperand Chain = Op.getOperand(0); |
| 1752 | bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; |
| 1753 | SDOperand Callee = Op.getOperand(4); |
| 1754 | unsigned NumOps = (Op.getNumOperands() - 5) / 2; |
| 1755 | |
| 1756 | bool isMachoABI = Subtarget.isMachoABI(); |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 1757 | bool isELF32_ABI = Subtarget.isELF32_ABI(); |
Evan Cheng | 4360bdc | 2006-05-25 00:57:32 +0000 | [diff] [blame] | 1758 | |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1759 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
| 1760 | bool isPPC64 = PtrVT == MVT::i64; |
| 1761 | unsigned PtrByteSize = isPPC64 ? 8 : 4; |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1762 | |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 1763 | // args_to_use will accumulate outgoing args for the PPCISD::CALL case in |
| 1764 | // SelectExpr to use to put the arguments in the appropriate registers. |
| 1765 | std::vector<SDOperand> args_to_use; |
| 1766 | |
| 1767 | // Count how many bytes are to be pushed on the stack, including the linkage |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1768 | // area, and parameter passing area. We start with 24/48 bytes, which is |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1769 | // prereserved space for [SP][CR][LR][3 x unused]. |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1770 | unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); |
Dale Johannesen | 75092de | 2008-03-12 00:22:17 +0000 | [diff] [blame] | 1771 | |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1772 | // Add up all the space actually used. |
Dale Johannesen | 8f5422c | 2008-03-14 17:41:26 +0000 | [diff] [blame] | 1773 | // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually |
| 1774 | // they all go in registers, but we must reserve stack space for them for |
| 1775 | // possible use by the caller. In varargs or 64-bit calls, parameters are |
| 1776 | // assigned stack space in order, with padding so Altivec parameters are |
| 1777 | // 16-byte aligned. |
| 1778 | unsigned nAltivecParamsAtEnd = 0; |
Jim Laskey | e9bd7b2 | 2006-11-28 14:53:52 +0000 | [diff] [blame] | 1779 | for (unsigned i = 0; i != NumOps; ++i) { |
Dale Johannesen | 75092de | 2008-03-12 00:22:17 +0000 | [diff] [blame] | 1780 | SDOperand Arg = Op.getOperand(5+2*i); |
| 1781 | MVT::ValueType ArgVT = Arg.getValueType(); |
Dale Johannesen | 8f5422c | 2008-03-14 17:41:26 +0000 | [diff] [blame] | 1782 | if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || |
| 1783 | ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { |
| 1784 | if (!isVarArg && !isPPC64) { |
| 1785 | // Non-varargs Altivec parameters go after all the non-Altivec parameters; |
| 1786 | // do those last so we know how much padding we need. |
| 1787 | nAltivecParamsAtEnd++; |
| 1788 | continue; |
| 1789 | } else { |
| 1790 | // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. |
| 1791 | NumBytes = ((NumBytes+15)/16)*16; |
| 1792 | } |
| 1793 | } |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1794 | ISD::ArgFlagsTy Flags = |
| 1795 | cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags(); |
Jim Laskey | e9bd7b2 | 2006-11-28 14:53:52 +0000 | [diff] [blame] | 1796 | unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8; |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1797 | if (Flags.isByVal()) |
| 1798 | ArgSize = Flags.getByValSize(); |
Dale Johannesen | 7f96f39 | 2008-03-08 01:41:42 +0000 | [diff] [blame] | 1799 | ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; |
Jim Laskey | e9bd7b2 | 2006-11-28 14:53:52 +0000 | [diff] [blame] | 1800 | NumBytes += ArgSize; |
| 1801 | } |
Dale Johannesen | 8f5422c | 2008-03-14 17:41:26 +0000 | [diff] [blame] | 1802 | // Allow for Altivec parameters at the end, if needed. |
| 1803 | if (nAltivecParamsAtEnd) { |
| 1804 | NumBytes = ((NumBytes+15)/16)*16; |
| 1805 | NumBytes += 16*nAltivecParamsAtEnd; |
| 1806 | } |
Chris Lattner | c04ba7a | 2006-05-16 23:54:25 +0000 | [diff] [blame] | 1807 | |
Chris Lattner | 7b05350 | 2006-05-30 21:21:04 +0000 | [diff] [blame] | 1808 | // The prolog code of the callee may store up to 8 GPR argument registers to |
| 1809 | // the stack, allowing va_start to index over them in memory if its varargs. |
| 1810 | // Because we cannot tell if this is needed on the caller side, we have to |
| 1811 | // conservatively assume that it is needed. As such, make sure we have at |
| 1812 | // least enough stack space for the caller to store the 8 GPRs. |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1813 | NumBytes = std::max(NumBytes, |
| 1814 | PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI)); |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1815 | |
| 1816 | // Adjust the stack pointer for the new arguments... |
| 1817 | // These operations are automatically eliminated by the prolog/epilog pass |
| 1818 | Chain = DAG.getCALLSEQ_START(Chain, |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1819 | DAG.getConstant(NumBytes, PtrVT)); |
Dale Johannesen | 1f797a3 | 2008-03-05 23:31:27 +0000 | [diff] [blame] | 1820 | SDOperand CallSeqStart = Chain; |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1821 | |
| 1822 | // Set up a copy of the stack pointer for use loading and storing any |
| 1823 | // arguments that may not fit in the registers available for argument |
| 1824 | // passing. |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1825 | SDOperand StackPtr; |
| 1826 | if (isPPC64) |
| 1827 | StackPtr = DAG.getRegister(PPC::X1, MVT::i64); |
| 1828 | else |
| 1829 | StackPtr = DAG.getRegister(PPC::R1, MVT::i32); |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1830 | |
| 1831 | // Figure out which arguments are going to go in registers, and which in |
| 1832 | // memory. Also, if this is a vararg function, floating point operations |
| 1833 | // must be stored to our stack, and loaded into integer regs as well, if |
| 1834 | // any integer regs are available for argument passing. |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1835 | unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1836 | unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1837 | |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1838 | static const unsigned GPR_32[] = { // 32-bit registers. |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1839 | PPC::R3, PPC::R4, PPC::R5, PPC::R6, |
| 1840 | PPC::R7, PPC::R8, PPC::R9, PPC::R10, |
| 1841 | }; |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1842 | static const unsigned GPR_64[] = { // 64-bit registers. |
| 1843 | PPC::X3, PPC::X4, PPC::X5, PPC::X6, |
| 1844 | PPC::X7, PPC::X8, PPC::X9, PPC::X10, |
| 1845 | }; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1846 | static const unsigned *FPR = GetFPR(Subtarget); |
| 1847 | |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1848 | static const unsigned VR[] = { |
| 1849 | PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, |
| 1850 | PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 |
| 1851 | }; |
Owen Anderson | 718cb66 | 2007-09-07 04:06:50 +0000 | [diff] [blame] | 1852 | const unsigned NumGPRs = array_lengthof(GPR_32); |
Nicolas Geoffray | ef3c030 | 2007-04-03 10:27:07 +0000 | [diff] [blame] | 1853 | const unsigned NumFPRs = isMachoABI ? 13 : 8; |
Owen Anderson | 718cb66 | 2007-09-07 04:06:50 +0000 | [diff] [blame] | 1854 | const unsigned NumVRs = array_lengthof( VR); |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1855 | |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1856 | const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; |
| 1857 | |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1858 | std::vector<std::pair<unsigned, SDOperand> > RegsToPass; |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 1859 | SmallVector<SDOperand, 8> MemOpChains; |
Evan Cheng | 4360bdc | 2006-05-25 00:57:32 +0000 | [diff] [blame] | 1860 | for (unsigned i = 0; i != NumOps; ++i) { |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1861 | bool inMem = false; |
Evan Cheng | 4360bdc | 2006-05-25 00:57:32 +0000 | [diff] [blame] | 1862 | SDOperand Arg = Op.getOperand(5+2*i); |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1863 | ISD::ArgFlagsTy Flags = |
| 1864 | cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags(); |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1865 | // See if next argument requires stack alignment in ELF |
Nicolas Geoffray | 6ccbbd8 | 2008-04-15 08:08:50 +0000 | [diff] [blame] | 1866 | bool Align = Flags.isSplit(); |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1867 | |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1868 | // PtrOff will be used to store the current argument to the stack if a |
| 1869 | // register cannot be found for it. |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1870 | SDOperand PtrOff; |
| 1871 | |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 1872 | // Stack align in ELF 32 |
Nicolas Geoffray | c0cb28f | 2008-04-13 13:40:22 +0000 | [diff] [blame] | 1873 | if (isELF32_ABI && Align) |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1874 | PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize, |
| 1875 | StackPtr.getValueType()); |
| 1876 | else |
| 1877 | PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); |
| 1878 | |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1879 | PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); |
| 1880 | |
| 1881 | // On PPC64, promote integers to 64-bit values. |
| 1882 | if (isPPC64 && Arg.getValueType() == MVT::i32) { |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1883 | // FIXME: Should this use ANY_EXTEND if neither sext nor zext? |
| 1884 | unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1885 | Arg = DAG.getNode(ExtOp, MVT::i64, Arg); |
| 1886 | } |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 1887 | |
| 1888 | // FIXME Elf untested, what are alignment rules? |
Dale Johannesen | 8419dd6 | 2008-03-07 20:27:40 +0000 | [diff] [blame] | 1889 | // FIXME memcpy is used way more than necessary. Correctness first. |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1890 | if (Flags.isByVal()) { |
| 1891 | unsigned Size = Flags.getByValSize(); |
Nicolas Geoffray | c0cb28f | 2008-04-13 13:40:22 +0000 | [diff] [blame] | 1892 | if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2); |
Dale Johannesen | 8419dd6 | 2008-03-07 20:27:40 +0000 | [diff] [blame] | 1893 | if (Size==1 || Size==2) { |
| 1894 | // Very small objects are passed right-justified. |
| 1895 | // Everything else is passed left-justified. |
| 1896 | MVT::ValueType VT = (Size==1) ? MVT::i8 : MVT::i16; |
| 1897 | if (GPR_idx != NumGPRs) { |
| 1898 | SDOperand Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg, |
| 1899 | NULL, 0, VT); |
| 1900 | MemOpChains.push_back(Load.getValue(1)); |
| 1901 | RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); |
| 1902 | if (isMachoABI) |
| 1903 | ArgOffset += PtrByteSize; |
| 1904 | } else { |
| 1905 | SDOperand Const = DAG.getConstant(4 - Size, PtrOff.getValueType()); |
| 1906 | SDOperand AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const); |
| 1907 | SDOperand MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, |
| 1908 | CallSeqStart.Val->getOperand(0), |
| 1909 | Flags, DAG, Size); |
| 1910 | // This must go outside the CALLSEQ_START..END. |
| 1911 | SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, |
| 1912 | CallSeqStart.Val->getOperand(1)); |
| 1913 | DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val); |
| 1914 | Chain = CallSeqStart = NewCallSeqStart; |
| 1915 | ArgOffset += PtrByteSize; |
| 1916 | } |
| 1917 | continue; |
| 1918 | } |
Dale Johannesen | fdd3ade | 2008-03-17 02:13:43 +0000 | [diff] [blame] | 1919 | // Copy entire object into memory. There are cases where gcc-generated |
| 1920 | // code assumes it is there, even if it could be put entirely into |
| 1921 | // registers. (This is not what the doc says.) |
| 1922 | SDOperand MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, |
| 1923 | CallSeqStart.Val->getOperand(0), |
| 1924 | Flags, DAG, Size); |
| 1925 | // This must go outside the CALLSEQ_START..END. |
| 1926 | SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, |
| 1927 | CallSeqStart.Val->getOperand(1)); |
| 1928 | DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val); |
| 1929 | Chain = CallSeqStart = NewCallSeqStart; |
| 1930 | // And copy the pieces of it that fit into registers. |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 1931 | for (unsigned j=0; j<Size; j+=PtrByteSize) { |
| 1932 | SDOperand Const = DAG.getConstant(j, PtrOff.getValueType()); |
| 1933 | SDOperand AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const); |
| 1934 | if (GPR_idx != NumGPRs) { |
| 1935 | SDOperand Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0); |
Dale Johannesen | 1f797a3 | 2008-03-05 23:31:27 +0000 | [diff] [blame] | 1936 | MemOpChains.push_back(Load.getValue(1)); |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 1937 | RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); |
| 1938 | if (isMachoABI) |
| 1939 | ArgOffset += PtrByteSize; |
| 1940 | } else { |
Dale Johannesen | fdd3ade | 2008-03-17 02:13:43 +0000 | [diff] [blame] | 1941 | ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; |
Dale Johannesen | 8419dd6 | 2008-03-07 20:27:40 +0000 | [diff] [blame] | 1942 | break; |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 1943 | } |
| 1944 | } |
| 1945 | continue; |
| 1946 | } |
| 1947 | |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1948 | switch (Arg.getValueType()) { |
| 1949 | default: assert(0 && "Unexpected ValueType for argument!"); |
| 1950 | case MVT::i32: |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1951 | case MVT::i64: |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1952 | // Double word align in ELF |
Nicolas Geoffray | c0cb28f | 2008-04-13 13:40:22 +0000 | [diff] [blame] | 1953 | if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2); |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1954 | if (GPR_idx != NumGPRs) { |
| 1955 | RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1956 | } else { |
Evan Cheng | 8b2794a | 2006-10-13 21:14:26 +0000 | [diff] [blame] | 1957 | MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1958 | inMem = true; |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1959 | } |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1960 | if (inMem || isMachoABI) { |
| 1961 | // Stack align in ELF |
Nicolas Geoffray | c0cb28f | 2008-04-13 13:40:22 +0000 | [diff] [blame] | 1962 | if (isELF32_ABI && Align) |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 1963 | ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; |
| 1964 | |
| 1965 | ArgOffset += PtrByteSize; |
| 1966 | } |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1967 | break; |
| 1968 | case MVT::f32: |
| 1969 | case MVT::f64: |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1970 | if (FPR_idx != NumFPRs) { |
| 1971 | RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); |
| 1972 | |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1973 | if (isVarArg) { |
Evan Cheng | 8b2794a | 2006-10-13 21:14:26 +0000 | [diff] [blame] | 1974 | SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1975 | MemOpChains.push_back(Store); |
| 1976 | |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1977 | // Float varargs are always shadowed in available integer registers |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1978 | if (GPR_idx != NumGPRs) { |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 1979 | SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1980 | MemOpChains.push_back(Load.getValue(1)); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1981 | if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], |
| 1982 | Load)); |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1983 | } |
Jim Laskey | fbb74e6 | 2006-12-01 16:30:47 +0000 | [diff] [blame] | 1984 | if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1985 | SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); |
Chris Lattner | c91a475 | 2006-06-26 22:48:35 +0000 | [diff] [blame] | 1986 | PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour); |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 1987 | SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 1988 | MemOpChains.push_back(Load.getValue(1)); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1989 | if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], |
| 1990 | Load)); |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 1991 | } |
| 1992 | } else { |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 1993 | // If we have any FPRs remaining, we may also have GPRs remaining. |
| 1994 | // Args passed in FPRs consume either 1 (f32) or 2 (f64) available |
| 1995 | // GPRs. |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1996 | if (isMachoABI) { |
| 1997 | if (GPR_idx != NumGPRs) |
| 1998 | ++GPR_idx; |
| 1999 | if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && |
| 2000 | !isPPC64) // PPC64 has 64-bit GPR's obviously :) |
| 2001 | ++GPR_idx; |
| 2002 | } |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 2003 | } |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 2004 | } else { |
Evan Cheng | 8b2794a | 2006-10-13 21:14:26 +0000 | [diff] [blame] | 2005 | MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 2006 | inMem = true; |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 2007 | } |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 2008 | if (inMem || isMachoABI) { |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 2009 | // Stack align in ELF |
Nicolas Geoffray | c0cb28f | 2008-04-13 13:40:22 +0000 | [diff] [blame] | 2010 | if (isELF32_ABI && Align) |
Nicolas Geoffray | b2ec1cc | 2007-03-13 15:02:46 +0000 | [diff] [blame] | 2011 | ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 2012 | if (isPPC64) |
| 2013 | ArgOffset += 8; |
| 2014 | else |
| 2015 | ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; |
| 2016 | } |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 2017 | break; |
| 2018 | case MVT::v4f32: |
| 2019 | case MVT::v4i32: |
| 2020 | case MVT::v8i16: |
| 2021 | case MVT::v16i8: |
Dale Johannesen | 75092de | 2008-03-12 00:22:17 +0000 | [diff] [blame] | 2022 | if (isVarArg) { |
| 2023 | // These go aligned on the stack, or in the corresponding R registers |
| 2024 | // when within range. The Darwin PPC ABI doc claims they also go in |
| 2025 | // V registers; in fact gcc does this only for arguments that are |
| 2026 | // prototyped, not for those that match the ... We do it for all |
| 2027 | // arguments, seems to work. |
| 2028 | while (ArgOffset % 16 !=0) { |
| 2029 | ArgOffset += PtrByteSize; |
| 2030 | if (GPR_idx != NumGPRs) |
| 2031 | GPR_idx++; |
| 2032 | } |
| 2033 | // We could elide this store in the case where the object fits |
| 2034 | // entirely in R registers. Maybe later. |
| 2035 | PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, |
| 2036 | DAG.getConstant(ArgOffset, PtrVT)); |
| 2037 | SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); |
| 2038 | MemOpChains.push_back(Store); |
| 2039 | if (VR_idx != NumVRs) { |
| 2040 | SDOperand Load = DAG.getLoad(MVT::v4f32, Store, PtrOff, NULL, 0); |
| 2041 | MemOpChains.push_back(Load.getValue(1)); |
| 2042 | RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); |
| 2043 | } |
| 2044 | ArgOffset += 16; |
| 2045 | for (unsigned i=0; i<16; i+=PtrByteSize) { |
| 2046 | if (GPR_idx == NumGPRs) |
| 2047 | break; |
| 2048 | SDOperand Ix = DAG.getNode(ISD::ADD, PtrVT, PtrOff, |
| 2049 | DAG.getConstant(i, PtrVT)); |
| 2050 | SDOperand Load = DAG.getLoad(PtrVT, Store, Ix, NULL, 0); |
| 2051 | MemOpChains.push_back(Load.getValue(1)); |
| 2052 | RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); |
| 2053 | } |
| 2054 | break; |
| 2055 | } |
Dale Johannesen | 8f5422c | 2008-03-14 17:41:26 +0000 | [diff] [blame] | 2056 | // Non-varargs Altivec params generally go in registers, but have |
| 2057 | // stack space allocated at the end. |
| 2058 | if (VR_idx != NumVRs) { |
| 2059 | // Doesn't have GPR space allocated. |
| 2060 | RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); |
| 2061 | } else if (nAltivecParamsAtEnd==0) { |
| 2062 | // We are emitting Altivec params in order. |
Dale Johannesen | 75092de | 2008-03-12 00:22:17 +0000 | [diff] [blame] | 2063 | PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, |
| 2064 | DAG.getConstant(ArgOffset, PtrVT)); |
| 2065 | SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); |
| 2066 | MemOpChains.push_back(Store); |
| 2067 | ArgOffset += 16; |
Dale Johannesen | 75092de | 2008-03-12 00:22:17 +0000 | [diff] [blame] | 2068 | } |
Chris Lattner | c8b682c | 2006-05-17 00:15:40 +0000 | [diff] [blame] | 2069 | break; |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 2070 | } |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 2071 | } |
Dale Johannesen | 8f5422c | 2008-03-14 17:41:26 +0000 | [diff] [blame] | 2072 | // If all Altivec parameters fit in registers, as they usually do, |
| 2073 | // they get stack space following the non-Altivec parameters. We |
| 2074 | // don't track this here because nobody below needs it. |
| 2075 | // If there are more Altivec parameters than fit in registers emit |
| 2076 | // the stores here. |
| 2077 | if (!isVarArg && nAltivecParamsAtEnd > NumVRs) { |
| 2078 | unsigned j = 0; |
| 2079 | // Offset is aligned; skip 1st 12 params which go in V registers. |
| 2080 | ArgOffset = ((ArgOffset+15)/16)*16; |
| 2081 | ArgOffset += 12*16; |
| 2082 | for (unsigned i = 0; i != NumOps; ++i) { |
| 2083 | SDOperand Arg = Op.getOperand(5+2*i); |
| 2084 | MVT::ValueType ArgType = Arg.getValueType(); |
| 2085 | if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || |
| 2086 | ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { |
| 2087 | if (++j > NumVRs) { |
| 2088 | SDOperand PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, |
| 2089 | DAG.getConstant(ArgOffset, PtrVT)); |
| 2090 | SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); |
| 2091 | MemOpChains.push_back(Store); |
| 2092 | ArgOffset += 16; |
| 2093 | } |
| 2094 | } |
| 2095 | } |
| 2096 | } |
| 2097 | |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 2098 | if (!MemOpChains.empty()) |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 2099 | Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, |
| 2100 | &MemOpChains[0], MemOpChains.size()); |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 2101 | |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 2102 | // Build a sequence of copy-to-reg nodes chained together with token chain |
| 2103 | // and flag operands which copy the outgoing args into the appropriate regs. |
| 2104 | SDOperand InFlag; |
| 2105 | for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { |
| 2106 | Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, |
| 2107 | InFlag); |
| 2108 | InFlag = Chain.getValue(1); |
| 2109 | } |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 2110 | |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 2111 | // With the ELF 32 ABI, set CR6 to true if this is a vararg call. |
| 2112 | if (isVarArg && isELF32_ABI) { |
Nicolas Geoffray | 0404cd9 | 2008-03-10 14:12:10 +0000 | [diff] [blame] | 2113 | SDOperand SetCR(DAG.getTargetNode(PPC::CRSET, MVT::i32), 0); |
| 2114 | Chain = DAG.getCopyToReg(Chain, PPC::CR1EQ, SetCR, InFlag); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 2115 | InFlag = Chain.getValue(1); |
| 2116 | } |
| 2117 | |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 2118 | std::vector<MVT::ValueType> NodeTys; |
Chris Lattner | 4a45abf | 2006-06-10 01:14:28 +0000 | [diff] [blame] | 2119 | NodeTys.push_back(MVT::Other); // Returns a chain |
| 2120 | NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. |
| 2121 | |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 2122 | SmallVector<SDOperand, 8> Ops; |
Nicolas Geoffray | 63f8fb1 | 2007-02-27 13:01:19 +0000 | [diff] [blame] | 2123 | unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF; |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 2124 | |
| 2125 | // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every |
| 2126 | // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol |
| 2127 | // node so that legalize doesn't hack it. |
Nicolas Geoffray | 5a6c91a | 2007-12-21 12:22:29 +0000 | [diff] [blame] | 2128 | if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) |
| 2129 | Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); |
| 2130 | else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 2131 | Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); |
| 2132 | else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) |
| 2133 | // If this is an absolute destination address, use the munged value. |
| 2134 | Callee = SDOperand(Dest, 0); |
| 2135 | else { |
| 2136 | // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair |
| 2137 | // to do the call, we can't use PPCISD::CALL. |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 2138 | SDOperand MTCTROps[] = {Chain, Callee, InFlag}; |
| 2139 | Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0)); |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 2140 | InFlag = Chain.getValue(1); |
| 2141 | |
Chris Lattner | dc9971a | 2008-03-09 20:49:33 +0000 | [diff] [blame] | 2142 | // Copy the callee address into R12/X12 on darwin. |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 2143 | if (isMachoABI) { |
Chris Lattner | dc9971a | 2008-03-09 20:49:33 +0000 | [diff] [blame] | 2144 | unsigned Reg = Callee.getValueType() == MVT::i32 ? PPC::R12 : PPC::X12; |
| 2145 | Chain = DAG.getCopyToReg(Chain, Reg, Callee, InFlag); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 2146 | InFlag = Chain.getValue(1); |
| 2147 | } |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 2148 | |
| 2149 | NodeTys.clear(); |
| 2150 | NodeTys.push_back(MVT::Other); |
| 2151 | NodeTys.push_back(MVT::Flag); |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 2152 | Ops.push_back(Chain); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 2153 | CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF; |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 2154 | Callee.Val = 0; |
| 2155 | } |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 2156 | |
Chris Lattner | 4a45abf | 2006-06-10 01:14:28 +0000 | [diff] [blame] | 2157 | // If this is a direct call, pass the chain and the callee. |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 2158 | if (Callee.Val) { |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 2159 | Ops.push_back(Chain); |
| 2160 | Ops.push_back(Callee); |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 2161 | } |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 2162 | |
Chris Lattner | 4a45abf | 2006-06-10 01:14:28 +0000 | [diff] [blame] | 2163 | // Add argument registers to the end of the list so that they are known live |
| 2164 | // into the call. |
| 2165 | for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) |
| 2166 | Ops.push_back(DAG.getRegister(RegsToPass[i].first, |
| 2167 | RegsToPass[i].second.getValueType())); |
| 2168 | |
| 2169 | if (InFlag.Val) |
| 2170 | Ops.push_back(InFlag); |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 2171 | Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); |
Chris Lattner | 4a45abf | 2006-06-10 01:14:28 +0000 | [diff] [blame] | 2172 | InFlag = Chain.getValue(1); |
| 2173 | |
Bill Wendling | 0f8d9c0 | 2007-11-13 00:44:25 +0000 | [diff] [blame] | 2174 | Chain = DAG.getCALLSEQ_END(Chain, |
| 2175 | DAG.getConstant(NumBytes, PtrVT), |
| 2176 | DAG.getConstant(0, PtrVT), |
| 2177 | InFlag); |
| 2178 | if (Op.Val->getValueType(0) != MVT::Other) |
| 2179 | InFlag = Chain.getValue(1); |
| 2180 | |
Dan Gohman | 7925ed0 | 2008-03-19 21:39:28 +0000 | [diff] [blame] | 2181 | SmallVector<SDOperand, 16> ResultVals; |
| 2182 | SmallVector<CCValAssign, 16> RVLocs; |
| 2183 | unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); |
| 2184 | CCState CCInfo(CC, isVarArg, TM, RVLocs); |
| 2185 | CCInfo.AnalyzeCallResult(Op.Val, RetCC_PPC); |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 2186 | |
Dan Gohman | 7925ed0 | 2008-03-19 21:39:28 +0000 | [diff] [blame] | 2187 | // Copy all of the result registers out of their specified physreg. |
| 2188 | for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { |
| 2189 | CCValAssign &VA = RVLocs[i]; |
| 2190 | MVT::ValueType VT = VA.getValVT(); |
| 2191 | assert(VA.isRegLoc() && "Can only return in registers!"); |
| 2192 | Chain = DAG.getCopyFromReg(Chain, VA.getLocReg(), VT, InFlag).getValue(1); |
| 2193 | ResultVals.push_back(Chain.getValue(0)); |
| 2194 | InFlag = Chain.getValue(2); |
Chris Lattner | 9a2a497 | 2006-05-17 06:01:33 +0000 | [diff] [blame] | 2195 | } |
Dan Gohman | 7925ed0 | 2008-03-19 21:39:28 +0000 | [diff] [blame] | 2196 | |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 2197 | // If the function returns void, just return the chain. |
Dan Gohman | 7925ed0 | 2008-03-19 21:39:28 +0000 | [diff] [blame] | 2198 | if (RVLocs.empty()) |
Chris Lattner | c703a8f | 2006-05-17 19:00:46 +0000 | [diff] [blame] | 2199 | return Chain; |
| 2200 | |
| 2201 | // Otherwise, merge everything together with a MERGE_VALUES node. |
Dan Gohman | 7925ed0 | 2008-03-19 21:39:28 +0000 | [diff] [blame] | 2202 | ResultVals.push_back(Chain); |
| 2203 | SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), |
| 2204 | &ResultVals[0], ResultVals.size()); |
Chris Lattner | abde460 | 2006-05-16 22:56:08 +0000 | [diff] [blame] | 2205 | return Res.getValue(Op.ResNo); |
| 2206 | } |
| 2207 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 2208 | SDOperand PPCTargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG, |
| 2209 | TargetMachine &TM) { |
Chris Lattner | b9a7bea | 2007-03-06 00:59:59 +0000 | [diff] [blame] | 2210 | SmallVector<CCValAssign, 16> RVLocs; |
| 2211 | unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); |
Chris Lattner | 52387be | 2007-06-19 00:13:10 +0000 | [diff] [blame] | 2212 | bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); |
| 2213 | CCState CCInfo(CC, isVarArg, TM, RVLocs); |
Chris Lattner | b9a7bea | 2007-03-06 00:59:59 +0000 | [diff] [blame] | 2214 | CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC); |
| 2215 | |
| 2216 | // If this is the first return lowered for this function, add the regs to the |
| 2217 | // liveout set for the function. |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 2218 | if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { |
Chris Lattner | b9a7bea | 2007-03-06 00:59:59 +0000 | [diff] [blame] | 2219 | for (unsigned i = 0; i != RVLocs.size(); ++i) |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 2220 | DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); |
Chris Lattner | b9a7bea | 2007-03-06 00:59:59 +0000 | [diff] [blame] | 2221 | } |
| 2222 | |
Chris Lattner | caddd44 | 2007-02-26 19:44:02 +0000 | [diff] [blame] | 2223 | SDOperand Chain = Op.getOperand(0); |
Chris Lattner | b9a7bea | 2007-03-06 00:59:59 +0000 | [diff] [blame] | 2224 | SDOperand Flag; |
| 2225 | |
| 2226 | // Copy the result values into the output registers. |
| 2227 | for (unsigned i = 0; i != RVLocs.size(); ++i) { |
| 2228 | CCValAssign &VA = RVLocs[i]; |
| 2229 | assert(VA.isRegLoc() && "Can only return in registers!"); |
| 2230 | Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); |
| 2231 | Flag = Chain.getValue(1); |
| 2232 | } |
| 2233 | |
| 2234 | if (Flag.Val) |
| 2235 | return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag); |
| 2236 | else |
Chris Lattner | caddd44 | 2007-02-26 19:44:02 +0000 | [diff] [blame] | 2237 | return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2238 | } |
| 2239 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 2240 | SDOperand PPCTargetLowering::LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG, |
Jim Laskey | efc7e52 | 2006-12-04 22:04:42 +0000 | [diff] [blame] | 2241 | const PPCSubtarget &Subtarget) { |
| 2242 | // When we pop the dynamic allocation we need to restore the SP link. |
| 2243 | |
| 2244 | // Get the corect type for pointers. |
| 2245 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
| 2246 | |
| 2247 | // Construct the stack pointer operand. |
| 2248 | bool IsPPC64 = Subtarget.isPPC64(); |
| 2249 | unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1; |
| 2250 | SDOperand StackPtr = DAG.getRegister(SP, PtrVT); |
| 2251 | |
| 2252 | // Get the operands for the STACKRESTORE. |
| 2253 | SDOperand Chain = Op.getOperand(0); |
| 2254 | SDOperand SaveSP = Op.getOperand(1); |
| 2255 | |
| 2256 | // Load the old link SP. |
| 2257 | SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0); |
| 2258 | |
| 2259 | // Restore the stack pointer. |
| 2260 | Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP); |
| 2261 | |
| 2262 | // Store the old link SP. |
| 2263 | return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0); |
| 2264 | } |
| 2265 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 2266 | SDOperand PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op, |
| 2267 | SelectionDAG &DAG, |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 2268 | const PPCSubtarget &Subtarget) { |
| 2269 | MachineFunction &MF = DAG.getMachineFunction(); |
| 2270 | bool IsPPC64 = Subtarget.isPPC64(); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 2271 | bool isMachoABI = Subtarget.isMachoABI(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 2272 | |
| 2273 | // Get current frame pointer save index. The users of this index will be |
| 2274 | // primarily DYNALLOC instructions. |
| 2275 | PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); |
| 2276 | int FPSI = FI->getFramePointerSaveIndex(); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 2277 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 2278 | // If the frame pointer save index hasn't been defined yet. |
| 2279 | if (!FPSI) { |
| 2280 | // Find out what the fix offset of the frame pointer save area. |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 2281 | int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI); |
| 2282 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 2283 | // Allocate the frame index for frame pointer save area. |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 2284 | FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 2285 | // Save the result. |
| 2286 | FI->setFramePointerSaveIndex(FPSI); |
| 2287 | } |
| 2288 | |
| 2289 | // Get the inputs. |
| 2290 | SDOperand Chain = Op.getOperand(0); |
| 2291 | SDOperand Size = Op.getOperand(1); |
| 2292 | |
| 2293 | // Get the corect type for pointers. |
| 2294 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
| 2295 | // Negate the size. |
| 2296 | SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT, |
| 2297 | DAG.getConstant(0, PtrVT), Size); |
| 2298 | // Construct a node for the frame pointer save index. |
| 2299 | SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT); |
| 2300 | // Build a DYNALLOC node. |
| 2301 | SDOperand Ops[3] = { Chain, NegSize, FPSIdx }; |
| 2302 | SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); |
| 2303 | return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3); |
| 2304 | } |
| 2305 | |
Evan Cheng | 54fc97d | 2008-04-19 01:30:48 +0000 | [diff] [blame] | 2306 | SDOperand PPCTargetLowering::LowerAtomicLAS(SDOperand Op, SelectionDAG &DAG) { |
| 2307 | MVT::ValueType VT = Op.getValueType(); |
| 2308 | SDOperand Chain = Op.getOperand(0); |
| 2309 | SDOperand Ptr = Op.getOperand(1); |
| 2310 | SDOperand Incr = Op.getOperand(2); |
| 2311 | |
| 2312 | // Issue a "load and reserve". |
| 2313 | std::vector<MVT::ValueType> VTs; |
| 2314 | VTs.push_back(VT); |
| 2315 | VTs.push_back(MVT::Other); |
| 2316 | |
| 2317 | SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32); |
| 2318 | SDOperand Ops[] = { |
| 2319 | Chain, // Chain |
| 2320 | Ptr, // Ptr |
| 2321 | Label, // Label |
| 2322 | }; |
| 2323 | SDOperand Load = DAG.getNode(PPCISD::LWARX, VTs, Ops, 3); |
| 2324 | Chain = Load.getValue(1); |
| 2325 | |
| 2326 | // Compute new value. |
| 2327 | SDOperand NewVal = DAG.getNode(ISD::ADD, VT, Load, Incr); |
| 2328 | |
| 2329 | // Issue a "store and check". |
| 2330 | SDOperand Ops2[] = { |
| 2331 | Chain, // Chain |
| 2332 | NewVal, // Value |
| 2333 | Ptr, // Ptr |
| 2334 | Label, // Label |
| 2335 | }; |
| 2336 | SDOperand Store = DAG.getNode(PPCISD::STWCX, MVT::Other, Ops2, 4); |
| 2337 | SDOperand OutOps[] = { Load, Store }; |
| 2338 | return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), |
| 2339 | OutOps, 2); |
| 2340 | } |
| 2341 | |
| 2342 | SDOperand PPCTargetLowering::LowerAtomicLCS(SDOperand Op, SelectionDAG &DAG) { |
| 2343 | MVT::ValueType VT = Op.getValueType(); |
| 2344 | SDOperand Chain = Op.getOperand(0); |
| 2345 | SDOperand Ptr = Op.getOperand(1); |
| 2346 | SDOperand NewVal = Op.getOperand(2); |
| 2347 | SDOperand OldVal = Op.getOperand(3); |
| 2348 | |
| 2349 | // Issue a "load and reserve". |
| 2350 | std::vector<MVT::ValueType> VTs; |
| 2351 | VTs.push_back(VT); |
| 2352 | VTs.push_back(MVT::Other); |
| 2353 | |
| 2354 | SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32); |
| 2355 | SDOperand Ops[] = { |
| 2356 | Chain, // Chain |
| 2357 | Ptr, // Ptr |
| 2358 | Label, // Label |
| 2359 | }; |
| 2360 | SDOperand Load = DAG.getNode(PPCISD::LWARX, VTs, Ops, 3); |
| 2361 | Chain = Load.getValue(1); |
| 2362 | |
| 2363 | // Compare and unreserve if not equal. |
| 2364 | SDOperand Ops2[] = { |
| 2365 | Chain, // Chain |
| 2366 | OldVal, // Old value |
| 2367 | Load, // Value in memory |
| 2368 | Label, // Label |
| 2369 | }; |
| 2370 | Chain = DAG.getNode(PPCISD::CMP_UNRESERVE, MVT::Other, Ops2, 4); |
| 2371 | |
| 2372 | // Issue a "store and check". |
| 2373 | SDOperand Ops3[] = { |
| 2374 | Chain, // Chain |
| 2375 | NewVal, // Value |
| 2376 | Ptr, // Ptr |
| 2377 | Label, // Label |
| 2378 | }; |
| 2379 | SDOperand Store = DAG.getNode(PPCISD::STWCX, MVT::Other, Ops3, 4); |
| 2380 | SDOperand OutOps[] = { Load, Store }; |
| 2381 | return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), |
| 2382 | OutOps, 2); |
| 2383 | } |
| 2384 | |
| 2385 | SDOperand PPCTargetLowering::LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG) { |
| 2386 | MVT::ValueType VT = Op.getValueType(); |
| 2387 | SDOperand Chain = Op.getOperand(0); |
| 2388 | SDOperand Ptr = Op.getOperand(1); |
| 2389 | SDOperand NewVal = Op.getOperand(2); |
| 2390 | |
| 2391 | // Issue a "load and reserve". |
| 2392 | std::vector<MVT::ValueType> VTs; |
| 2393 | VTs.push_back(VT); |
| 2394 | VTs.push_back(MVT::Other); |
| 2395 | |
| 2396 | SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32); |
| 2397 | SDOperand Ops[] = { |
| 2398 | Chain, // Chain |
| 2399 | Ptr, // Ptr |
| 2400 | Label, // Label |
| 2401 | }; |
| 2402 | SDOperand Load = DAG.getNode(PPCISD::LWARX, VTs, Ops, 3); |
| 2403 | Chain = Load.getValue(1); |
| 2404 | |
| 2405 | // Issue a "store and check". |
| 2406 | SDOperand Ops2[] = { |
| 2407 | Chain, // Chain |
| 2408 | NewVal, // Value |
| 2409 | Ptr, // Ptr |
| 2410 | Label, // Label |
| 2411 | }; |
| 2412 | SDOperand Store = DAG.getNode(PPCISD::STWCX, MVT::Other, Ops2, 4); |
| 2413 | SDOperand OutOps[] = { Load, Store }; |
| 2414 | return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), |
| 2415 | OutOps, 2); |
| 2416 | } |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 2417 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2418 | /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when |
| 2419 | /// possible. |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 2420 | SDOperand PPCTargetLowering::LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2421 | // Not FP? Not a fsel. |
| 2422 | if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || |
| 2423 | !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) |
| 2424 | return SDOperand(); |
| 2425 | |
| 2426 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); |
| 2427 | |
| 2428 | // Cannot handle SETEQ/SETNE. |
| 2429 | if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand(); |
| 2430 | |
| 2431 | MVT::ValueType ResVT = Op.getValueType(); |
| 2432 | MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); |
| 2433 | SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); |
| 2434 | SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); |
| 2435 | |
| 2436 | // If the RHS of the comparison is a 0.0, we don't need to do the |
| 2437 | // subtraction at all. |
| 2438 | if (isFloatingPointZero(RHS)) |
| 2439 | switch (CC) { |
| 2440 | default: break; // SETUO etc aren't handled by fsel. |
| 2441 | case ISD::SETULT: |
Chris Lattner | 5734012 | 2006-05-24 00:06:44 +0000 | [diff] [blame] | 2442 | case ISD::SETOLT: |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2443 | case ISD::SETLT: |
| 2444 | std::swap(TV, FV); // fsel is natively setge, swap operands for setlt |
| 2445 | case ISD::SETUGE: |
Chris Lattner | 5734012 | 2006-05-24 00:06:44 +0000 | [diff] [blame] | 2446 | case ISD::SETOGE: |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2447 | case ISD::SETGE: |
| 2448 | if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits |
| 2449 | LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); |
| 2450 | return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); |
| 2451 | case ISD::SETUGT: |
Chris Lattner | 5734012 | 2006-05-24 00:06:44 +0000 | [diff] [blame] | 2452 | case ISD::SETOGT: |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2453 | case ISD::SETGT: |
| 2454 | std::swap(TV, FV); // fsel is natively setge, swap operands for setlt |
| 2455 | case ISD::SETULE: |
Chris Lattner | 5734012 | 2006-05-24 00:06:44 +0000 | [diff] [blame] | 2456 | case ISD::SETOLE: |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2457 | case ISD::SETLE: |
| 2458 | if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits |
| 2459 | LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); |
| 2460 | return DAG.getNode(PPCISD::FSEL, ResVT, |
| 2461 | DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); |
| 2462 | } |
| 2463 | |
Chris Lattner | 1de7c1d | 2007-10-15 20:14:52 +0000 | [diff] [blame] | 2464 | SDOperand Cmp; |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2465 | switch (CC) { |
| 2466 | default: break; // SETUO etc aren't handled by fsel. |
| 2467 | case ISD::SETULT: |
Chris Lattner | 5734012 | 2006-05-24 00:06:44 +0000 | [diff] [blame] | 2468 | case ISD::SETOLT: |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2469 | case ISD::SETLT: |
| 2470 | Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); |
| 2471 | if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits |
| 2472 | Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); |
| 2473 | return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); |
| 2474 | case ISD::SETUGE: |
Chris Lattner | 5734012 | 2006-05-24 00:06:44 +0000 | [diff] [blame] | 2475 | case ISD::SETOGE: |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2476 | case ISD::SETGE: |
| 2477 | Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); |
| 2478 | if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits |
| 2479 | Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); |
| 2480 | return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); |
| 2481 | case ISD::SETUGT: |
Chris Lattner | 5734012 | 2006-05-24 00:06:44 +0000 | [diff] [blame] | 2482 | case ISD::SETOGT: |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2483 | case ISD::SETGT: |
| 2484 | Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); |
| 2485 | if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits |
| 2486 | Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); |
| 2487 | return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); |
| 2488 | case ISD::SETULE: |
Chris Lattner | 5734012 | 2006-05-24 00:06:44 +0000 | [diff] [blame] | 2489 | case ISD::SETOLE: |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2490 | case ISD::SETLE: |
| 2491 | Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); |
| 2492 | if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits |
| 2493 | Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); |
| 2494 | return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); |
| 2495 | } |
| 2496 | return SDOperand(); |
| 2497 | } |
| 2498 | |
Chris Lattner | 1f87300 | 2007-11-28 18:44:47 +0000 | [diff] [blame] | 2499 | // FIXME: Split this code up when LegalizeDAGTypes lands. |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 2500 | SDOperand PPCTargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2501 | assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); |
| 2502 | SDOperand Src = Op.getOperand(0); |
| 2503 | if (Src.getValueType() == MVT::f32) |
| 2504 | Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); |
| 2505 | |
| 2506 | SDOperand Tmp; |
| 2507 | switch (Op.getValueType()) { |
| 2508 | default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); |
| 2509 | case MVT::i32: |
| 2510 | Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); |
| 2511 | break; |
| 2512 | case MVT::i64: |
| 2513 | Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); |
| 2514 | break; |
| 2515 | } |
| 2516 | |
| 2517 | // Convert the FP value to an int value through memory. |
Chris Lattner | 1de7c1d | 2007-10-15 20:14:52 +0000 | [diff] [blame] | 2518 | SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64); |
| 2519 | |
| 2520 | // Emit a store to the stack slot. |
| 2521 | SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0); |
| 2522 | |
| 2523 | // Result is a load from the stack slot. If loading 4 bytes, make sure to |
| 2524 | // add in a bias. |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2525 | if (Op.getValueType() == MVT::i32) |
Chris Lattner | 1de7c1d | 2007-10-15 20:14:52 +0000 | [diff] [blame] | 2526 | FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, |
| 2527 | DAG.getConstant(4, FIPtr.getValueType())); |
| 2528 | return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2529 | } |
| 2530 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 2531 | SDOperand PPCTargetLowering::LowerFP_ROUND_INREG(SDOperand Op, |
| 2532 | SelectionDAG &DAG) { |
Dale Johannesen | 6eaeff2 | 2007-10-10 01:01:31 +0000 | [diff] [blame] | 2533 | assert(Op.getValueType() == MVT::ppcf128); |
| 2534 | SDNode *Node = Op.Val; |
| 2535 | assert(Node->getOperand(0).getValueType() == MVT::ppcf128); |
Chris Lattner | 26cb286 | 2007-10-19 04:08:28 +0000 | [diff] [blame] | 2536 | assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR); |
Dale Johannesen | 6eaeff2 | 2007-10-10 01:01:31 +0000 | [diff] [blame] | 2537 | SDOperand Lo = Node->getOperand(0).Val->getOperand(0); |
| 2538 | SDOperand Hi = Node->getOperand(0).Val->getOperand(1); |
| 2539 | |
| 2540 | // This sequence changes FPSCR to do round-to-zero, adds the two halves |
| 2541 | // of the long double, and puts FPSCR back the way it was. We do not |
| 2542 | // actually model FPSCR. |
| 2543 | std::vector<MVT::ValueType> NodeTys; |
| 2544 | SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg; |
| 2545 | |
| 2546 | NodeTys.push_back(MVT::f64); // Return register |
| 2547 | NodeTys.push_back(MVT::Flag); // Returns a flag for later insns |
| 2548 | Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); |
| 2549 | MFFSreg = Result.getValue(0); |
| 2550 | InFlag = Result.getValue(1); |
| 2551 | |
| 2552 | NodeTys.clear(); |
| 2553 | NodeTys.push_back(MVT::Flag); // Returns a flag |
| 2554 | Ops[0] = DAG.getConstant(31, MVT::i32); |
| 2555 | Ops[1] = InFlag; |
| 2556 | Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2); |
| 2557 | InFlag = Result.getValue(0); |
| 2558 | |
| 2559 | NodeTys.clear(); |
| 2560 | NodeTys.push_back(MVT::Flag); // Returns a flag |
| 2561 | Ops[0] = DAG.getConstant(30, MVT::i32); |
| 2562 | Ops[1] = InFlag; |
| 2563 | Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2); |
| 2564 | InFlag = Result.getValue(0); |
| 2565 | |
| 2566 | NodeTys.clear(); |
| 2567 | NodeTys.push_back(MVT::f64); // result of add |
| 2568 | NodeTys.push_back(MVT::Flag); // Returns a flag |
| 2569 | Ops[0] = Lo; |
| 2570 | Ops[1] = Hi; |
| 2571 | Ops[2] = InFlag; |
| 2572 | Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3); |
| 2573 | FPreg = Result.getValue(0); |
| 2574 | InFlag = Result.getValue(1); |
| 2575 | |
| 2576 | NodeTys.clear(); |
| 2577 | NodeTys.push_back(MVT::f64); |
| 2578 | Ops[0] = DAG.getConstant(1, MVT::i32); |
| 2579 | Ops[1] = MFFSreg; |
| 2580 | Ops[2] = FPreg; |
| 2581 | Ops[3] = InFlag; |
| 2582 | Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4); |
| 2583 | FPreg = Result.getValue(0); |
| 2584 | |
| 2585 | // We know the low half is about to be thrown away, so just use something |
| 2586 | // convenient. |
| 2587 | return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg); |
| 2588 | } |
| 2589 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 2590 | SDOperand PPCTargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { |
Dan Gohman | 034f60e | 2008-03-11 01:59:03 +0000 | [diff] [blame] | 2591 | // Don't handle ppc_fp128 here; let it be lowered to a libcall. |
| 2592 | if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) |
| 2593 | return SDOperand(); |
| 2594 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2595 | if (Op.getOperand(0).getValueType() == MVT::i64) { |
| 2596 | SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); |
| 2597 | SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); |
| 2598 | if (Op.getValueType() == MVT::f32) |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 2599 | FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2600 | return FP; |
| 2601 | } |
| 2602 | |
| 2603 | assert(Op.getOperand(0).getValueType() == MVT::i32 && |
| 2604 | "Unhandled SINT_TO_FP type in custom expander!"); |
| 2605 | // Since we only generate this in 64-bit mode, we can take advantage of |
| 2606 | // 64-bit registers. In particular, sign extend the input value into the |
| 2607 | // 64-bit register with extsw, store the WHOLE 64-bit value into the stack |
| 2608 | // then lfd it and fcfid it. |
| 2609 | MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); |
| 2610 | int FrameIdx = FrameInfo->CreateStackObject(8, 8); |
Chris Lattner | 0d72a20 | 2006-07-28 16:45:47 +0000 | [diff] [blame] | 2611 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
| 2612 | SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2613 | |
| 2614 | SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, |
| 2615 | Op.getOperand(0)); |
| 2616 | |
| 2617 | // STD the extended value into the stack slot. |
Dan Gohman | 36b5c13 | 2008-04-07 19:35:22 +0000 | [diff] [blame] | 2618 | MachineMemOperand MO(PseudoSourceValue::getFixedStack(), |
| 2619 | MachineMemOperand::MOStore, FrameIdx, 8, 8); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2620 | SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, |
| 2621 | DAG.getEntryNode(), Ext64, FIdx, |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 2622 | DAG.getMemOperand(MO)); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2623 | // Load the value as a double. |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 2624 | SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2625 | |
| 2626 | // FCFID it and return it. |
| 2627 | SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); |
| 2628 | if (Op.getValueType() == MVT::f32) |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 2629 | FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2630 | return FP; |
| 2631 | } |
| 2632 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 2633 | SDOperand PPCTargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) { |
Dale Johannesen | 5c5eb80 | 2008-01-18 19:55:37 +0000 | [diff] [blame] | 2634 | /* |
| 2635 | The rounding mode is in bits 30:31 of FPSR, and has the following |
| 2636 | settings: |
| 2637 | 00 Round to nearest |
| 2638 | 01 Round to 0 |
| 2639 | 10 Round to +inf |
| 2640 | 11 Round to -inf |
| 2641 | |
| 2642 | FLT_ROUNDS, on the other hand, expects the following: |
| 2643 | -1 Undefined |
| 2644 | 0 Round to 0 |
| 2645 | 1 Round to nearest |
| 2646 | 2 Round to +inf |
| 2647 | 3 Round to -inf |
| 2648 | |
| 2649 | To perform the conversion, we do: |
| 2650 | ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) |
| 2651 | */ |
| 2652 | |
| 2653 | MachineFunction &MF = DAG.getMachineFunction(); |
| 2654 | MVT::ValueType VT = Op.getValueType(); |
| 2655 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
| 2656 | std::vector<MVT::ValueType> NodeTys; |
| 2657 | SDOperand MFFSreg, InFlag; |
| 2658 | |
| 2659 | // Save FP Control Word to register |
| 2660 | NodeTys.push_back(MVT::f64); // return register |
| 2661 | NodeTys.push_back(MVT::Flag); // unused in this context |
| 2662 | SDOperand Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); |
| 2663 | |
| 2664 | // Save FP register to stack slot |
| 2665 | int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); |
| 2666 | SDOperand StackSlot = DAG.getFrameIndex(SSFI, PtrVT); |
| 2667 | SDOperand Store = DAG.getStore(DAG.getEntryNode(), Chain, |
| 2668 | StackSlot, NULL, 0); |
| 2669 | |
| 2670 | // Load FP Control Word from low 32 bits of stack slot. |
| 2671 | SDOperand Four = DAG.getConstant(4, PtrVT); |
| 2672 | SDOperand Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four); |
| 2673 | SDOperand CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0); |
| 2674 | |
| 2675 | // Transform as necessary |
| 2676 | SDOperand CWD1 = |
| 2677 | DAG.getNode(ISD::AND, MVT::i32, |
| 2678 | CWD, DAG.getConstant(3, MVT::i32)); |
| 2679 | SDOperand CWD2 = |
| 2680 | DAG.getNode(ISD::SRL, MVT::i32, |
| 2681 | DAG.getNode(ISD::AND, MVT::i32, |
| 2682 | DAG.getNode(ISD::XOR, MVT::i32, |
| 2683 | CWD, DAG.getConstant(3, MVT::i32)), |
| 2684 | DAG.getConstant(3, MVT::i32)), |
| 2685 | DAG.getConstant(1, MVT::i8)); |
| 2686 | |
| 2687 | SDOperand RetVal = |
| 2688 | DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2); |
| 2689 | |
| 2690 | return DAG.getNode((MVT::getSizeInBits(VT) < 16 ? |
| 2691 | ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal); |
| 2692 | } |
| 2693 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 2694 | SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { |
Dan Gohman | 9ed06db | 2008-03-07 20:36:53 +0000 | [diff] [blame] | 2695 | MVT::ValueType VT = Op.getValueType(); |
| 2696 | unsigned BitWidth = MVT::getSizeInBits(VT); |
| 2697 | assert(Op.getNumOperands() == 3 && |
| 2698 | VT == Op.getOperand(1).getValueType() && |
| 2699 | "Unexpected SHL!"); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2700 | |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2701 | // Expand into a bunch of logical ops. Note that these ops |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2702 | // depend on the PPC behavior for oversized shift amounts. |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2703 | SDOperand Lo = Op.getOperand(0); |
| 2704 | SDOperand Hi = Op.getOperand(1); |
| 2705 | SDOperand Amt = Op.getOperand(2); |
Dan Gohman | 9ed06db | 2008-03-07 20:36:53 +0000 | [diff] [blame] | 2706 | MVT::ValueType AmtVT = Amt.getValueType(); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2707 | |
Dan Gohman | 9ed06db | 2008-03-07 20:36:53 +0000 | [diff] [blame] | 2708 | SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT, |
| 2709 | DAG.getConstant(BitWidth, AmtVT), Amt); |
| 2710 | SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt); |
| 2711 | SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1); |
| 2712 | SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); |
| 2713 | SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, |
| 2714 | DAG.getConstant(-BitWidth, AmtVT)); |
| 2715 | SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5); |
| 2716 | SDOperand OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); |
| 2717 | SDOperand OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt); |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2718 | SDOperand OutOps[] = { OutLo, OutHi }; |
Dan Gohman | 9ed06db | 2008-03-07 20:36:53 +0000 | [diff] [blame] | 2719 | return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT), |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2720 | OutOps, 2); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2721 | } |
| 2722 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 2723 | SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { |
Dan Gohman | 9ed06db | 2008-03-07 20:36:53 +0000 | [diff] [blame] | 2724 | MVT::ValueType VT = Op.getValueType(); |
| 2725 | unsigned BitWidth = MVT::getSizeInBits(VT); |
| 2726 | assert(Op.getNumOperands() == 3 && |
| 2727 | VT == Op.getOperand(1).getValueType() && |
| 2728 | "Unexpected SRL!"); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2729 | |
Dan Gohman | 9ed06db | 2008-03-07 20:36:53 +0000 | [diff] [blame] | 2730 | // Expand into a bunch of logical ops. Note that these ops |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2731 | // depend on the PPC behavior for oversized shift amounts. |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2732 | SDOperand Lo = Op.getOperand(0); |
| 2733 | SDOperand Hi = Op.getOperand(1); |
| 2734 | SDOperand Amt = Op.getOperand(2); |
Dan Gohman | 9ed06db | 2008-03-07 20:36:53 +0000 | [diff] [blame] | 2735 | MVT::ValueType AmtVT = Amt.getValueType(); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2736 | |
Dan Gohman | 9ed06db | 2008-03-07 20:36:53 +0000 | [diff] [blame] | 2737 | SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT, |
| 2738 | DAG.getConstant(BitWidth, AmtVT), Amt); |
| 2739 | SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt); |
| 2740 | SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1); |
| 2741 | SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); |
| 2742 | SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, |
| 2743 | DAG.getConstant(-BitWidth, AmtVT)); |
| 2744 | SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5); |
| 2745 | SDOperand OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); |
| 2746 | SDOperand OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt); |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2747 | SDOperand OutOps[] = { OutLo, OutHi }; |
Dan Gohman | 9ed06db | 2008-03-07 20:36:53 +0000 | [diff] [blame] | 2748 | return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT), |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2749 | OutOps, 2); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2750 | } |
| 2751 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 2752 | SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { |
Dan Gohman | 9ed06db | 2008-03-07 20:36:53 +0000 | [diff] [blame] | 2753 | MVT::ValueType VT = Op.getValueType(); |
| 2754 | unsigned BitWidth = MVT::getSizeInBits(VT); |
| 2755 | assert(Op.getNumOperands() == 3 && |
| 2756 | VT == Op.getOperand(1).getValueType() && |
| 2757 | "Unexpected SRA!"); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2758 | |
Dan Gohman | 9ed06db | 2008-03-07 20:36:53 +0000 | [diff] [blame] | 2759 | // Expand into a bunch of logical ops, followed by a select_cc. |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2760 | SDOperand Lo = Op.getOperand(0); |
| 2761 | SDOperand Hi = Op.getOperand(1); |
| 2762 | SDOperand Amt = Op.getOperand(2); |
Dan Gohman | 9ed06db | 2008-03-07 20:36:53 +0000 | [diff] [blame] | 2763 | MVT::ValueType AmtVT = Amt.getValueType(); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2764 | |
Dan Gohman | 9ed06db | 2008-03-07 20:36:53 +0000 | [diff] [blame] | 2765 | SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT, |
| 2766 | DAG.getConstant(BitWidth, AmtVT), Amt); |
| 2767 | SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt); |
| 2768 | SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1); |
| 2769 | SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); |
| 2770 | SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, |
| 2771 | DAG.getConstant(-BitWidth, AmtVT)); |
| 2772 | SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5); |
| 2773 | SDOperand OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt); |
| 2774 | SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT), |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2775 | Tmp4, Tmp6, ISD::SETLE); |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2776 | SDOperand OutOps[] = { OutLo, OutHi }; |
Dan Gohman | 9ed06db | 2008-03-07 20:36:53 +0000 | [diff] [blame] | 2777 | return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT), |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 2778 | OutOps, 2); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 2779 | } |
| 2780 | |
| 2781 | //===----------------------------------------------------------------------===// |
| 2782 | // Vector related lowering. |
| 2783 | // |
| 2784 | |
Chris Lattner | ac225ca | 2006-04-12 19:07:14 +0000 | [diff] [blame] | 2785 | // If this is a vector of constants or undefs, get the bits. A bit in |
| 2786 | // UndefBits is set if the corresponding element of the vector is an |
| 2787 | // ISD::UNDEF value. For undefs, the corresponding VectorBits values are |
| 2788 | // zero. Return true if this is not an array of constants, false if it is. |
| 2789 | // |
Chris Lattner | ac225ca | 2006-04-12 19:07:14 +0000 | [diff] [blame] | 2790 | static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], |
| 2791 | uint64_t UndefBits[2]) { |
| 2792 | // Start with zero'd results. |
| 2793 | VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; |
| 2794 | |
| 2795 | unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType()); |
| 2796 | for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { |
| 2797 | SDOperand OpVal = BV->getOperand(i); |
| 2798 | |
| 2799 | unsigned PartNo = i >= e/2; // In the upper 128 bits? |
Chris Lattner | b17f167 | 2006-04-16 01:01:29 +0000 | [diff] [blame] | 2800 | unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. |
Chris Lattner | ac225ca | 2006-04-12 19:07:14 +0000 | [diff] [blame] | 2801 | |
| 2802 | uint64_t EltBits = 0; |
| 2803 | if (OpVal.getOpcode() == ISD::UNDEF) { |
| 2804 | uint64_t EltUndefBits = ~0U >> (32-EltBitSize); |
| 2805 | UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize); |
| 2806 | continue; |
| 2807 | } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { |
| 2808 | EltBits = CN->getValue() & (~0U >> (32-EltBitSize)); |
| 2809 | } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { |
| 2810 | assert(CN->getValueType(0) == MVT::f32 && |
| 2811 | "Only one legal FP vector type!"); |
Dale Johannesen | eaf0894 | 2007-08-31 04:03:46 +0000 | [diff] [blame] | 2812 | EltBits = FloatToBits(CN->getValueAPF().convertToFloat()); |
Chris Lattner | ac225ca | 2006-04-12 19:07:14 +0000 | [diff] [blame] | 2813 | } else { |
| 2814 | // Nonconstant element. |
| 2815 | return true; |
| 2816 | } |
| 2817 | |
| 2818 | VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize); |
| 2819 | } |
| 2820 | |
| 2821 | //printf("%llx %llx %llx %llx\n", |
| 2822 | // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]); |
| 2823 | return false; |
| 2824 | } |
Chris Lattner | ef819f8 | 2006-03-20 06:33:01 +0000 | [diff] [blame] | 2825 | |
Chris Lattner | b17f167 | 2006-04-16 01:01:29 +0000 | [diff] [blame] | 2826 | // If this is a splat (repetition) of a value across the whole vector, return |
| 2827 | // the smallest size that splats it. For example, "0x01010101010101..." is a |
| 2828 | // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and |
| 2829 | // SplatSize = 1 byte. |
| 2830 | static bool isConstantSplat(const uint64_t Bits128[2], |
| 2831 | const uint64_t Undef128[2], |
| 2832 | unsigned &SplatBits, unsigned &SplatUndef, |
| 2833 | unsigned &SplatSize) { |
| 2834 | |
| 2835 | // Don't let undefs prevent splats from matching. See if the top 64-bits are |
| 2836 | // the same as the lower 64-bits, ignoring undefs. |
| 2837 | if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0])) |
| 2838 | return false; // Can't be a splat if two pieces don't match. |
| 2839 | |
| 2840 | uint64_t Bits64 = Bits128[0] | Bits128[1]; |
| 2841 | uint64_t Undef64 = Undef128[0] & Undef128[1]; |
| 2842 | |
| 2843 | // Check that the top 32-bits are the same as the lower 32-bits, ignoring |
| 2844 | // undefs. |
| 2845 | if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64)) |
| 2846 | return false; // Can't be a splat if two pieces don't match. |
| 2847 | |
| 2848 | uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32); |
| 2849 | uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32); |
| 2850 | |
| 2851 | // If the top 16-bits are different than the lower 16-bits, ignoring |
| 2852 | // undefs, we have an i32 splat. |
| 2853 | if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) { |
| 2854 | SplatBits = Bits32; |
| 2855 | SplatUndef = Undef32; |
| 2856 | SplatSize = 4; |
| 2857 | return true; |
| 2858 | } |
| 2859 | |
| 2860 | uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16); |
| 2861 | uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16); |
| 2862 | |
| 2863 | // If the top 8-bits are different than the lower 8-bits, ignoring |
| 2864 | // undefs, we have an i16 splat. |
| 2865 | if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) { |
| 2866 | SplatBits = Bits16; |
| 2867 | SplatUndef = Undef16; |
| 2868 | SplatSize = 2; |
| 2869 | return true; |
| 2870 | } |
| 2871 | |
| 2872 | // Otherwise, we have an 8-bit splat. |
| 2873 | SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8); |
| 2874 | SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8); |
| 2875 | SplatSize = 1; |
| 2876 | return true; |
| 2877 | } |
| 2878 | |
Chris Lattner | 4a998b9 | 2006-04-17 06:00:21 +0000 | [diff] [blame] | 2879 | /// BuildSplatI - Build a canonical splati of Val with an element size of |
| 2880 | /// SplatSize. Cast the result to VT. |
| 2881 | static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT, |
| 2882 | SelectionDAG &DAG) { |
| 2883 | assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); |
Chris Lattner | 70fa493 | 2006-12-01 01:45:39 +0000 | [diff] [blame] | 2884 | |
Chris Lattner | 4a998b9 | 2006-04-17 06:00:21 +0000 | [diff] [blame] | 2885 | static const MVT::ValueType VTys[] = { // canonical VT to use for each size. |
| 2886 | MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 |
| 2887 | }; |
Chris Lattner | 70fa493 | 2006-12-01 01:45:39 +0000 | [diff] [blame] | 2888 | |
| 2889 | MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; |
| 2890 | |
| 2891 | // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. |
| 2892 | if (Val == -1) |
| 2893 | SplatSize = 1; |
| 2894 | |
Chris Lattner | 4a998b9 | 2006-04-17 06:00:21 +0000 | [diff] [blame] | 2895 | MVT::ValueType CanonicalVT = VTys[SplatSize-1]; |
| 2896 | |
| 2897 | // Build a canonical splat for this value. |
Dan Gohman | 51eaa86 | 2007-06-14 22:58:02 +0000 | [diff] [blame] | 2898 | SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT)); |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 2899 | SmallVector<SDOperand, 8> Ops; |
| 2900 | Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt); |
| 2901 | SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, |
| 2902 | &Ops[0], Ops.size()); |
Chris Lattner | 70fa493 | 2006-12-01 01:45:39 +0000 | [diff] [blame] | 2903 | return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res); |
Chris Lattner | 4a998b9 | 2006-04-17 06:00:21 +0000 | [diff] [blame] | 2904 | } |
| 2905 | |
Chris Lattner | e7c768e | 2006-04-18 03:24:30 +0000 | [diff] [blame] | 2906 | /// BuildIntrinsicOp - Return a binary operator intrinsic node with the |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 2907 | /// specified intrinsic ID. |
Chris Lattner | e7c768e | 2006-04-18 03:24:30 +0000 | [diff] [blame] | 2908 | static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS, |
| 2909 | SelectionDAG &DAG, |
| 2910 | MVT::ValueType DestVT = MVT::Other) { |
| 2911 | if (DestVT == MVT::Other) DestVT = LHS.getValueType(); |
| 2912 | return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 2913 | DAG.getConstant(IID, MVT::i32), LHS, RHS); |
| 2914 | } |
| 2915 | |
Chris Lattner | e7c768e | 2006-04-18 03:24:30 +0000 | [diff] [blame] | 2916 | /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the |
| 2917 | /// specified intrinsic ID. |
| 2918 | static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1, |
| 2919 | SDOperand Op2, SelectionDAG &DAG, |
| 2920 | MVT::ValueType DestVT = MVT::Other) { |
| 2921 | if (DestVT == MVT::Other) DestVT = Op0.getValueType(); |
| 2922 | return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, |
| 2923 | DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); |
| 2924 | } |
| 2925 | |
| 2926 | |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 2927 | /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified |
| 2928 | /// amount. The result has the specified value type. |
| 2929 | static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt, |
| 2930 | MVT::ValueType VT, SelectionDAG &DAG) { |
| 2931 | // Force LHS/RHS to be the right type. |
| 2932 | LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); |
| 2933 | RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); |
| 2934 | |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 2935 | SDOperand Ops[16]; |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 2936 | for (unsigned i = 0; i != 16; ++i) |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 2937 | Ops[i] = DAG.getConstant(i+Amt, MVT::i32); |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 2938 | SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 2939 | DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16)); |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 2940 | return DAG.getNode(ISD::BIT_CONVERT, VT, T); |
| 2941 | } |
| 2942 | |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 2943 | // If this is a case we can't handle, return null and let the default |
| 2944 | // expansion code take care of it. If we CAN select this case, and if it |
| 2945 | // selects to a single instruction, return Op. Otherwise, if we can codegen |
| 2946 | // this case more efficiently than a constant pool load, lower it to the |
| 2947 | // sequence of ops that should be used. |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 2948 | SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op, |
| 2949 | SelectionDAG &DAG) { |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 2950 | // If this is a vector of constants or undefs, get the bits. A bit in |
| 2951 | // UndefBits is set if the corresponding element of the vector is an |
| 2952 | // ISD::UNDEF value. For undefs, the corresponding VectorBits values are |
| 2953 | // zero. |
| 2954 | uint64_t VectorBits[2]; |
| 2955 | uint64_t UndefBits[2]; |
| 2956 | if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) |
| 2957 | return SDOperand(); // Not a constant vector. |
| 2958 | |
Chris Lattner | b17f167 | 2006-04-16 01:01:29 +0000 | [diff] [blame] | 2959 | // If this is a splat (repetition) of a value across the whole vector, return |
| 2960 | // the smallest size that splats it. For example, "0x01010101010101..." is a |
| 2961 | // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and |
| 2962 | // SplatSize = 1 byte. |
| 2963 | unsigned SplatBits, SplatUndef, SplatSize; |
| 2964 | if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){ |
| 2965 | bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0; |
| 2966 | |
| 2967 | // First, handle single instruction cases. |
| 2968 | |
| 2969 | // All zeros? |
| 2970 | if (SplatBits == 0) { |
| 2971 | // Canonicalize all zero vectors to be v4i32. |
| 2972 | if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { |
| 2973 | SDOperand Z = DAG.getConstant(0, MVT::i32); |
| 2974 | Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); |
| 2975 | Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); |
| 2976 | } |
| 2977 | return Op; |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 2978 | } |
Chris Lattner | b17f167 | 2006-04-16 01:01:29 +0000 | [diff] [blame] | 2979 | |
| 2980 | // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. |
| 2981 | int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize); |
Chris Lattner | 4a998b9 | 2006-04-17 06:00:21 +0000 | [diff] [blame] | 2982 | if (SextVal >= -16 && SextVal <= 15) |
| 2983 | return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG); |
Chris Lattner | b17f167 | 2006-04-16 01:01:29 +0000 | [diff] [blame] | 2984 | |
Chris Lattner | dbce85d | 2006-04-17 18:09:22 +0000 | [diff] [blame] | 2985 | |
| 2986 | // Two instruction sequences. |
| 2987 | |
Chris Lattner | 4a998b9 | 2006-04-17 06:00:21 +0000 | [diff] [blame] | 2988 | // If this value is in the range [-32,30] and is even, use: |
| 2989 | // tmp = VSPLTI[bhw], result = add tmp, tmp |
| 2990 | if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { |
| 2991 | Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG); |
| 2992 | return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op); |
| 2993 | } |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 2994 | |
| 2995 | // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is |
| 2996 | // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important |
| 2997 | // for fneg/fabs. |
| 2998 | if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { |
| 2999 | // Make -1 and vspltisw -1: |
| 3000 | SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG); |
| 3001 | |
| 3002 | // Make the VSLW intrinsic, computing 0x8000_0000. |
Chris Lattner | e7c768e | 2006-04-18 03:24:30 +0000 | [diff] [blame] | 3003 | SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, |
| 3004 | OnesV, DAG); |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 3005 | |
| 3006 | // xor by OnesV to invert it. |
| 3007 | Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); |
| 3008 | return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); |
| 3009 | } |
| 3010 | |
| 3011 | // Check to see if this is a wide variety of vsplti*, binop self cases. |
| 3012 | unsigned SplatBitSize = SplatSize*8; |
Lauro Ramos Venancio | 1baa197 | 2007-03-27 16:33:08 +0000 | [diff] [blame] | 3013 | static const signed char SplatCsts[] = { |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 3014 | -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, |
Chris Lattner | dbce85d | 2006-04-17 18:09:22 +0000 | [diff] [blame] | 3015 | -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 3016 | }; |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 3017 | |
Owen Anderson | 718cb66 | 2007-09-07 04:06:50 +0000 | [diff] [blame] | 3018 | for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 3019 | // Indirect through the SplatCsts array so that we favor 'vsplti -1' for |
| 3020 | // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' |
| 3021 | int i = SplatCsts[idx]; |
| 3022 | |
| 3023 | // Figure out what shift amount will be used by altivec if shifted by i in |
| 3024 | // this splat size. |
| 3025 | unsigned TypeShiftAmt = i & (SplatBitSize-1); |
| 3026 | |
| 3027 | // vsplti + shl self. |
| 3028 | if (SextVal == (i << (int)TypeShiftAmt)) { |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 3029 | SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 3030 | static const unsigned IIDs[] = { // Intrinsic to use for each size. |
| 3031 | Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, |
| 3032 | Intrinsic::ppc_altivec_vslw |
| 3033 | }; |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 3034 | Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); |
| 3035 | return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 3036 | } |
| 3037 | |
| 3038 | // vsplti + srl self. |
| 3039 | if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 3040 | SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 3041 | static const unsigned IIDs[] = { // Intrinsic to use for each size. |
| 3042 | Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, |
| 3043 | Intrinsic::ppc_altivec_vsrw |
| 3044 | }; |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 3045 | Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); |
| 3046 | return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 3047 | } |
| 3048 | |
| 3049 | // vsplti + sra self. |
| 3050 | if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 3051 | SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 3052 | static const unsigned IIDs[] = { // Intrinsic to use for each size. |
| 3053 | Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, |
| 3054 | Intrinsic::ppc_altivec_vsraw |
| 3055 | }; |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 3056 | Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); |
| 3057 | return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 3058 | } |
| 3059 | |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 3060 | // vsplti + rol self. |
| 3061 | if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | |
| 3062 | ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 3063 | SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 3064 | static const unsigned IIDs[] = { // Intrinsic to use for each size. |
| 3065 | Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, |
| 3066 | Intrinsic::ppc_altivec_vrlw |
| 3067 | }; |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 3068 | Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); |
| 3069 | return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 3070 | } |
| 3071 | |
| 3072 | // t = vsplti c, result = vsldoi t, t, 1 |
| 3073 | if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { |
| 3074 | SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); |
| 3075 | return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG); |
| 3076 | } |
| 3077 | // t = vsplti c, result = vsldoi t, t, 2 |
| 3078 | if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { |
| 3079 | SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); |
| 3080 | return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG); |
| 3081 | } |
| 3082 | // t = vsplti c, result = vsldoi t, t, 3 |
| 3083 | if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { |
| 3084 | SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); |
| 3085 | return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG); |
| 3086 | } |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 3087 | } |
| 3088 | |
Chris Lattner | 6876e66 | 2006-04-17 06:58:41 +0000 | [diff] [blame] | 3089 | // Three instruction sequences. |
| 3090 | |
Chris Lattner | dbce85d | 2006-04-17 18:09:22 +0000 | [diff] [blame] | 3091 | // Odd, in range [17,31]: (vsplti C)-(vsplti -16). |
| 3092 | if (SextVal >= 0 && SextVal <= 31) { |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 3093 | SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG); |
| 3094 | SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); |
Dale Johannesen | 296c176 | 2007-10-14 01:58:32 +0000 | [diff] [blame] | 3095 | LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS); |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 3096 | return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); |
Chris Lattner | dbce85d | 2006-04-17 18:09:22 +0000 | [diff] [blame] | 3097 | } |
| 3098 | // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). |
| 3099 | if (SextVal >= -31 && SextVal <= 0) { |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 3100 | SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG); |
| 3101 | SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); |
Dale Johannesen | 296c176 | 2007-10-14 01:58:32 +0000 | [diff] [blame] | 3102 | LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS); |
Chris Lattner | 15eb329 | 2006-11-29 19:58:49 +0000 | [diff] [blame] | 3103 | return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 3104 | } |
| 3105 | } |
Chris Lattner | b17f167 | 2006-04-16 01:01:29 +0000 | [diff] [blame] | 3106 | |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 3107 | return SDOperand(); |
| 3108 | } |
| 3109 | |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 3110 | /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit |
| 3111 | /// the specified operations to build the shuffle. |
| 3112 | static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, |
| 3113 | SDOperand RHS, SelectionDAG &DAG) { |
| 3114 | unsigned OpNum = (PFEntry >> 26) & 0x0F; |
| 3115 | unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); |
| 3116 | unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); |
| 3117 | |
| 3118 | enum { |
Chris Lattner | 00402c7 | 2006-05-16 04:20:24 +0000 | [diff] [blame] | 3119 | OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 3120 | OP_VMRGHW, |
| 3121 | OP_VMRGLW, |
| 3122 | OP_VSPLTISW0, |
| 3123 | OP_VSPLTISW1, |
| 3124 | OP_VSPLTISW2, |
| 3125 | OP_VSPLTISW3, |
| 3126 | OP_VSLDOI4, |
| 3127 | OP_VSLDOI8, |
Chris Lattner | d74ea2b | 2006-05-24 17:04:05 +0000 | [diff] [blame] | 3128 | OP_VSLDOI12 |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 3129 | }; |
| 3130 | |
| 3131 | if (OpNum == OP_COPY) { |
| 3132 | if (LHSID == (1*9+2)*9+3) return LHS; |
| 3133 | assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); |
| 3134 | return RHS; |
| 3135 | } |
| 3136 | |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 3137 | SDOperand OpLHS, OpRHS; |
| 3138 | OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG); |
| 3139 | OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG); |
| 3140 | |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 3141 | unsigned ShufIdxs[16]; |
| 3142 | switch (OpNum) { |
| 3143 | default: assert(0 && "Unknown i32 permute!"); |
| 3144 | case OP_VMRGHW: |
| 3145 | ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; |
| 3146 | ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; |
| 3147 | ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; |
| 3148 | ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; |
| 3149 | break; |
| 3150 | case OP_VMRGLW: |
| 3151 | ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; |
| 3152 | ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; |
| 3153 | ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; |
| 3154 | ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; |
| 3155 | break; |
| 3156 | case OP_VSPLTISW0: |
| 3157 | for (unsigned i = 0; i != 16; ++i) |
| 3158 | ShufIdxs[i] = (i&3)+0; |
| 3159 | break; |
| 3160 | case OP_VSPLTISW1: |
| 3161 | for (unsigned i = 0; i != 16; ++i) |
| 3162 | ShufIdxs[i] = (i&3)+4; |
| 3163 | break; |
| 3164 | case OP_VSPLTISW2: |
| 3165 | for (unsigned i = 0; i != 16; ++i) |
| 3166 | ShufIdxs[i] = (i&3)+8; |
| 3167 | break; |
| 3168 | case OP_VSPLTISW3: |
| 3169 | for (unsigned i = 0; i != 16; ++i) |
| 3170 | ShufIdxs[i] = (i&3)+12; |
| 3171 | break; |
| 3172 | case OP_VSLDOI4: |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 3173 | return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG); |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 3174 | case OP_VSLDOI8: |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 3175 | return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG); |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 3176 | case OP_VSLDOI12: |
Chris Lattner | bdd558c | 2006-04-17 17:55:10 +0000 | [diff] [blame] | 3177 | return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG); |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 3178 | } |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 3179 | SDOperand Ops[16]; |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 3180 | for (unsigned i = 0; i != 16; ++i) |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 3181 | Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32); |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 3182 | |
| 3183 | return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS, |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 3184 | DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 3185 | } |
| 3186 | |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 3187 | /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this |
| 3188 | /// is a shuffle we can handle in a single instruction, return it. Otherwise, |
| 3189 | /// return the code it can be lowered into. Worst case, it can always be |
| 3190 | /// lowered into a vperm. |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 3191 | SDOperand PPCTargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, |
| 3192 | SelectionDAG &DAG) { |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 3193 | SDOperand V1 = Op.getOperand(0); |
| 3194 | SDOperand V2 = Op.getOperand(1); |
| 3195 | SDOperand PermMask = Op.getOperand(2); |
| 3196 | |
| 3197 | // Cases that are handled by instructions that take permute immediates |
| 3198 | // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be |
| 3199 | // selected by the instruction selector. |
| 3200 | if (V2.getOpcode() == ISD::UNDEF) { |
| 3201 | if (PPC::isSplatShuffleMask(PermMask.Val, 1) || |
| 3202 | PPC::isSplatShuffleMask(PermMask.Val, 2) || |
| 3203 | PPC::isSplatShuffleMask(PermMask.Val, 4) || |
| 3204 | PPC::isVPKUWUMShuffleMask(PermMask.Val, true) || |
| 3205 | PPC::isVPKUHUMShuffleMask(PermMask.Val, true) || |
| 3206 | PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 || |
| 3207 | PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || |
| 3208 | PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || |
| 3209 | PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || |
| 3210 | PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) || |
| 3211 | PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) || |
| 3212 | PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) { |
| 3213 | return Op; |
| 3214 | } |
| 3215 | } |
| 3216 | |
| 3217 | // Altivec has a variety of "shuffle immediates" that take two vector inputs |
| 3218 | // and produce a fixed permutation. If any of these match, do not lower to |
| 3219 | // VPERM. |
| 3220 | if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) || |
| 3221 | PPC::isVPKUHUMShuffleMask(PermMask.Val, false) || |
| 3222 | PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 || |
| 3223 | PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || |
| 3224 | PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || |
| 3225 | PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || |
| 3226 | PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) || |
| 3227 | PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) || |
| 3228 | PPC::isVMRGHShuffleMask(PermMask.Val, 4, false)) |
| 3229 | return Op; |
| 3230 | |
Chris Lattner | 5913810 | 2006-04-17 05:28:54 +0000 | [diff] [blame] | 3231 | // Check to see if this is a shuffle of 4-byte values. If so, we can use our |
| 3232 | // perfect shuffle table to emit an optimal matching sequence. |
| 3233 | unsigned PFIndexes[4]; |
| 3234 | bool isFourElementShuffle = true; |
| 3235 | for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number |
| 3236 | unsigned EltNo = 8; // Start out undef. |
| 3237 | for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. |
| 3238 | if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF) |
| 3239 | continue; // Undef, ignore it. |
| 3240 | |
| 3241 | unsigned ByteSource = |
| 3242 | cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue(); |
| 3243 | if ((ByteSource & 3) != j) { |
| 3244 | isFourElementShuffle = false; |
| 3245 | break; |
| 3246 | } |
| 3247 | |
| 3248 | if (EltNo == 8) { |
| 3249 | EltNo = ByteSource/4; |
| 3250 | } else if (EltNo != ByteSource/4) { |
| 3251 | isFourElementShuffle = false; |
| 3252 | break; |
| 3253 | } |
| 3254 | } |
| 3255 | PFIndexes[i] = EltNo; |
| 3256 | } |
| 3257 | |
| 3258 | // If this shuffle can be expressed as a shuffle of 4-byte elements, use the |
| 3259 | // perfect shuffle vector to determine if it is cost effective to do this as |
| 3260 | // discrete instructions, or whether we should use a vperm. |
| 3261 | if (isFourElementShuffle) { |
| 3262 | // Compute the index in the perfect shuffle table. |
| 3263 | unsigned PFTableIndex = |
| 3264 | PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; |
| 3265 | |
| 3266 | unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; |
| 3267 | unsigned Cost = (PFEntry >> 30); |
| 3268 | |
| 3269 | // Determining when to avoid vperm is tricky. Many things affect the cost |
| 3270 | // of vperm, particularly how many times the perm mask needs to be computed. |
| 3271 | // For example, if the perm mask can be hoisted out of a loop or is already |
| 3272 | // used (perhaps because there are multiple permutes with the same shuffle |
| 3273 | // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of |
| 3274 | // the loop requires an extra register. |
| 3275 | // |
| 3276 | // As a compromise, we only emit discrete instructions if the shuffle can be |
| 3277 | // generated in 3 or fewer operations. When we have loop information |
| 3278 | // available, if this block is within a loop, we should avoid using vperm |
| 3279 | // for 3-operation perms and use a constant pool load instead. |
| 3280 | if (Cost < 3) |
| 3281 | return GeneratePerfectShuffle(PFEntry, V1, V2, DAG); |
| 3282 | } |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 3283 | |
| 3284 | // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant |
| 3285 | // vector that will get spilled to the constant pool. |
| 3286 | if (V2.getOpcode() == ISD::UNDEF) V2 = V1; |
| 3287 | |
| 3288 | // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except |
| 3289 | // that it is in input element units, not in bytes. Convert now. |
Dan Gohman | 51eaa86 | 2007-06-14 22:58:02 +0000 | [diff] [blame] | 3290 | MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType()); |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 3291 | unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; |
| 3292 | |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 3293 | SmallVector<SDOperand, 16> ResultMask; |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 3294 | for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { |
Chris Lattner | 730b456 | 2006-04-15 23:48:05 +0000 | [diff] [blame] | 3295 | unsigned SrcElt; |
| 3296 | if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) |
| 3297 | SrcElt = 0; |
| 3298 | else |
| 3299 | SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue(); |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 3300 | |
| 3301 | for (unsigned j = 0; j != BytesPerElement; ++j) |
| 3302 | ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, |
| 3303 | MVT::i8)); |
| 3304 | } |
| 3305 | |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 3306 | SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, |
| 3307 | &ResultMask[0], ResultMask.size()); |
Chris Lattner | f1b4708 | 2006-04-14 05:19:18 +0000 | [diff] [blame] | 3308 | return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); |
| 3309 | } |
| 3310 | |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3311 | /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an |
| 3312 | /// altivec comparison. If it is, return true and fill in Opc/isDot with |
| 3313 | /// information about the intrinsic. |
| 3314 | static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc, |
| 3315 | bool &isDot) { |
| 3316 | unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue(); |
| 3317 | CompareOpc = -1; |
| 3318 | isDot = false; |
| 3319 | switch (IntrinsicID) { |
| 3320 | default: return false; |
| 3321 | // Comparison predicates. |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3322 | case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; |
| 3323 | case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; |
| 3324 | case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; |
| 3325 | case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; |
| 3326 | case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; |
| 3327 | case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; |
| 3328 | case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; |
| 3329 | case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; |
| 3330 | case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; |
| 3331 | case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; |
| 3332 | case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; |
| 3333 | case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; |
| 3334 | case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; |
| 3335 | |
| 3336 | // Normal Comparisons. |
| 3337 | case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; |
| 3338 | case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; |
| 3339 | case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; |
| 3340 | case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; |
| 3341 | case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; |
| 3342 | case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; |
| 3343 | case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; |
| 3344 | case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; |
| 3345 | case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; |
| 3346 | case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; |
| 3347 | case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; |
| 3348 | case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; |
| 3349 | case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; |
| 3350 | } |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3351 | return true; |
| 3352 | } |
| 3353 | |
| 3354 | /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom |
| 3355 | /// lower, do it, otherwise return null. |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 3356 | SDOperand PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, |
| 3357 | SelectionDAG &DAG) { |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3358 | // If this is a lowered altivec predicate compare, CompareOpc is set to the |
| 3359 | // opcode number of the comparison. |
| 3360 | int CompareOpc; |
| 3361 | bool isDot; |
| 3362 | if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) |
| 3363 | return SDOperand(); // Don't custom lower most intrinsics. |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3364 | |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3365 | // If this is a non-dot comparison, make the VCMP node and we are done. |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3366 | if (!isDot) { |
| 3367 | SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), |
| 3368 | Op.getOperand(1), Op.getOperand(2), |
| 3369 | DAG.getConstant(CompareOpc, MVT::i32)); |
| 3370 | return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); |
| 3371 | } |
| 3372 | |
| 3373 | // Create the PPCISD altivec 'dot' comparison node. |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 3374 | SDOperand Ops[] = { |
| 3375 | Op.getOperand(2), // LHS |
| 3376 | Op.getOperand(3), // RHS |
| 3377 | DAG.getConstant(CompareOpc, MVT::i32) |
| 3378 | }; |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3379 | std::vector<MVT::ValueType> VTs; |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3380 | VTs.push_back(Op.getOperand(2).getValueType()); |
| 3381 | VTs.push_back(MVT::Flag); |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 3382 | SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3383 | |
| 3384 | // Now that we have the comparison, emit a copy from the CR to a GPR. |
| 3385 | // This is flagged to the above dot comparison. |
| 3386 | SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, |
| 3387 | DAG.getRegister(PPC::CR6, MVT::i32), |
| 3388 | CompNode.getValue(1)); |
| 3389 | |
| 3390 | // Unpack the result based on how the target uses it. |
| 3391 | unsigned BitNo; // Bit # of CR6. |
| 3392 | bool InvertBit; // Invert result? |
| 3393 | switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { |
| 3394 | default: // Can't happen, don't crash on invalid number though. |
| 3395 | case 0: // Return the value of the EQ bit of CR6. |
| 3396 | BitNo = 0; InvertBit = false; |
| 3397 | break; |
| 3398 | case 1: // Return the inverted value of the EQ bit of CR6. |
| 3399 | BitNo = 0; InvertBit = true; |
| 3400 | break; |
| 3401 | case 2: // Return the value of the LT bit of CR6. |
| 3402 | BitNo = 2; InvertBit = false; |
| 3403 | break; |
| 3404 | case 3: // Return the inverted value of the LT bit of CR6. |
| 3405 | BitNo = 2; InvertBit = true; |
| 3406 | break; |
| 3407 | } |
| 3408 | |
| 3409 | // Shift the bit into the low position. |
| 3410 | Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, |
| 3411 | DAG.getConstant(8-(3-BitNo), MVT::i32)); |
| 3412 | // Isolate the bit. |
| 3413 | Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, |
| 3414 | DAG.getConstant(1, MVT::i32)); |
| 3415 | |
| 3416 | // If we are supposed to, toggle the bit. |
| 3417 | if (InvertBit) |
| 3418 | Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, |
| 3419 | DAG.getConstant(1, MVT::i32)); |
| 3420 | return Flags; |
| 3421 | } |
| 3422 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 3423 | SDOperand PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, |
| 3424 | SelectionDAG &DAG) { |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3425 | // Create a stack slot that is 16-byte aligned. |
| 3426 | MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); |
| 3427 | int FrameIdx = FrameInfo->CreateStackObject(16, 16); |
Chris Lattner | 0d72a20 | 2006-07-28 16:45:47 +0000 | [diff] [blame] | 3428 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
| 3429 | SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3430 | |
| 3431 | // Store the input value into Value#0 of the stack slot. |
Evan Cheng | 786225a | 2006-10-05 23:01:46 +0000 | [diff] [blame] | 3432 | SDOperand Store = DAG.getStore(DAG.getEntryNode(), |
Evan Cheng | 8b2794a | 2006-10-13 21:14:26 +0000 | [diff] [blame] | 3433 | Op.getOperand(0), FIdx, NULL, 0); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3434 | // Load it out. |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 3435 | return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3436 | } |
| 3437 | |
Dale Johannesen | 5b3b695 | 2008-03-04 23:17:14 +0000 | [diff] [blame] | 3438 | SDOperand PPCTargetLowering::LowerMUL(SDOperand Op, SelectionDAG &DAG) { |
Chris Lattner | 72dd9bd | 2006-04-18 03:43:48 +0000 | [diff] [blame] | 3439 | if (Op.getValueType() == MVT::v4i32) { |
| 3440 | SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); |
| 3441 | |
| 3442 | SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG); |
| 3443 | SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt. |
| 3444 | |
| 3445 | SDOperand RHSSwap = // = vrlw RHS, 16 |
| 3446 | BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG); |
| 3447 | |
| 3448 | // Shrinkify inputs to v8i16. |
| 3449 | LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS); |
| 3450 | RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS); |
| 3451 | RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap); |
| 3452 | |
| 3453 | // Low parts multiplied together, generating 32-bit results (we ignore the |
| 3454 | // top parts). |
| 3455 | SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, |
| 3456 | LHS, RHS, DAG, MVT::v4i32); |
| 3457 | |
| 3458 | SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, |
| 3459 | LHS, RHSSwap, Zero, DAG, MVT::v4i32); |
| 3460 | // Shift the high parts up 16 bits. |
| 3461 | HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG); |
| 3462 | return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd); |
| 3463 | } else if (Op.getValueType() == MVT::v8i16) { |
| 3464 | SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); |
| 3465 | |
Chris Lattner | cea2aa7 | 2006-04-18 04:28:57 +0000 | [diff] [blame] | 3466 | SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG); |
Chris Lattner | 72dd9bd | 2006-04-18 03:43:48 +0000 | [diff] [blame] | 3467 | |
Chris Lattner | cea2aa7 | 2006-04-18 04:28:57 +0000 | [diff] [blame] | 3468 | return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, |
| 3469 | LHS, RHS, Zero, DAG); |
Chris Lattner | 19a8152 | 2006-04-18 03:57:35 +0000 | [diff] [blame] | 3470 | } else if (Op.getValueType() == MVT::v16i8) { |
| 3471 | SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); |
| 3472 | |
| 3473 | // Multiply the even 8-bit parts, producing 16-bit sums. |
| 3474 | SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, |
| 3475 | LHS, RHS, DAG, MVT::v8i16); |
| 3476 | EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts); |
| 3477 | |
| 3478 | // Multiply the odd 8-bit parts, producing 16-bit sums. |
| 3479 | SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, |
| 3480 | LHS, RHS, DAG, MVT::v8i16); |
| 3481 | OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts); |
| 3482 | |
| 3483 | // Merge the results together. |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 3484 | SDOperand Ops[16]; |
Chris Lattner | 19a8152 | 2006-04-18 03:57:35 +0000 | [diff] [blame] | 3485 | for (unsigned i = 0; i != 8; ++i) { |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 3486 | Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8); |
| 3487 | Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8); |
Chris Lattner | 19a8152 | 2006-04-18 03:57:35 +0000 | [diff] [blame] | 3488 | } |
Chris Lattner | 19a8152 | 2006-04-18 03:57:35 +0000 | [diff] [blame] | 3489 | return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts, |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 3490 | DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); |
Chris Lattner | 72dd9bd | 2006-04-18 03:43:48 +0000 | [diff] [blame] | 3491 | } else { |
| 3492 | assert(0 && "Unknown mul to lower!"); |
| 3493 | abort(); |
| 3494 | } |
Chris Lattner | e7c768e | 2006-04-18 03:24:30 +0000 | [diff] [blame] | 3495 | } |
| 3496 | |
Chris Lattner | e4bc9ea | 2005-08-26 00:52:45 +0000 | [diff] [blame] | 3497 | /// LowerOperation - Provide custom lowering hooks for some operations. |
| 3498 | /// |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 3499 | SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { |
Chris Lattner | e4bc9ea | 2005-08-26 00:52:45 +0000 | [diff] [blame] | 3500 | switch (Op.getOpcode()) { |
| 3501 | default: assert(0 && "Wasn't expecting to be able to lower this!"); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3502 | case ISD::ConstantPool: return LowerConstantPool(Op, DAG); |
| 3503 | case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); |
Lauro Ramos Venancio | 75ce010 | 2007-07-11 17:19:51 +0000 | [diff] [blame] | 3504 | case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 3505 | case ISD::JumpTable: return LowerJumpTable(Op, DAG); |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3506 | case ISD::SETCC: return LowerSETCC(Op, DAG); |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 3507 | case ISD::VASTART: |
| 3508 | return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, |
| 3509 | VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); |
| 3510 | |
| 3511 | case ISD::VAARG: |
| 3512 | return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, |
| 3513 | VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); |
| 3514 | |
Chris Lattner | ef95710 | 2006-06-21 00:34:03 +0000 | [diff] [blame] | 3515 | case ISD::FORMAL_ARGUMENTS: |
Nicolas Geoffray | 0111999 | 2007-04-03 13:59:52 +0000 | [diff] [blame] | 3516 | return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex, |
| 3517 | VarArgsStackOffset, VarArgsNumGPR, |
| 3518 | VarArgsNumFPR, PPCSubTarget); |
| 3519 | |
Dan Gohman | 7925ed0 | 2008-03-19 21:39:28 +0000 | [diff] [blame] | 3520 | case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget, |
| 3521 | getTargetMachine()); |
Chris Lattner | b9a7bea | 2007-03-06 00:59:59 +0000 | [diff] [blame] | 3522 | case ISD::RET: return LowerRET(Op, DAG, getTargetMachine()); |
Jim Laskey | efc7e52 | 2006-12-04 22:04:42 +0000 | [diff] [blame] | 3523 | case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 3524 | case ISD::DYNAMIC_STACKALLOC: |
| 3525 | return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); |
Evan Cheng | 54fc97d | 2008-04-19 01:30:48 +0000 | [diff] [blame] | 3526 | |
| 3527 | case ISD::ATOMIC_LAS: return LowerAtomicLAS(Op, DAG); |
| 3528 | case ISD::ATOMIC_LCS: return LowerAtomicLCS(Op, DAG); |
| 3529 | case ISD::ATOMIC_SWAP: return LowerAtomicSWAP(Op, DAG); |
Chris Lattner | 7c0d664 | 2005-10-02 06:37:13 +0000 | [diff] [blame] | 3530 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3531 | case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); |
| 3532 | case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); |
| 3533 | case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); |
Dale Johannesen | 6eaeff2 | 2007-10-10 01:01:31 +0000 | [diff] [blame] | 3534 | case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG); |
Dan Gohman | 1a02486 | 2008-01-31 00:41:03 +0000 | [diff] [blame] | 3535 | case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); |
Chris Lattner | ecfe55e | 2006-03-22 05:30:33 +0000 | [diff] [blame] | 3536 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3537 | // Lower 64-bit shifts. |
Chris Lattner | 3fe6c1d | 2006-09-20 03:47:40 +0000 | [diff] [blame] | 3538 | case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); |
| 3539 | case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); |
| 3540 | case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); |
Chris Lattner | ecfe55e | 2006-03-22 05:30:33 +0000 | [diff] [blame] | 3541 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3542 | // Vector-related lowering. |
| 3543 | case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); |
| 3544 | case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); |
| 3545 | case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); |
| 3546 | case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); |
Chris Lattner | e7c768e | 2006-04-18 03:24:30 +0000 | [diff] [blame] | 3547 | case ISD::MUL: return LowerMUL(Op, DAG); |
Nate Begeman | bcc5f36 | 2007-01-29 22:58:52 +0000 | [diff] [blame] | 3548 | |
Chris Lattner | 3fc027d | 2007-12-08 06:59:59 +0000 | [diff] [blame] | 3549 | // Frame & Return address. |
| 3550 | case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); |
Nicolas Geoffray | 43c6e7c | 2007-03-01 13:11:38 +0000 | [diff] [blame] | 3551 | case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); |
Chris Lattner | bc11c34 | 2005-08-31 20:23:54 +0000 | [diff] [blame] | 3552 | } |
Chris Lattner | e4bc9ea | 2005-08-26 00:52:45 +0000 | [diff] [blame] | 3553 | return SDOperand(); |
| 3554 | } |
| 3555 | |
Chris Lattner | 1f87300 | 2007-11-28 18:44:47 +0000 | [diff] [blame] | 3556 | SDNode *PPCTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) { |
| 3557 | switch (N->getOpcode()) { |
| 3558 | default: assert(0 && "Wasn't expecting to be able to lower this!"); |
| 3559 | case ISD::FP_TO_SINT: return LowerFP_TO_SINT(SDOperand(N, 0), DAG).Val; |
| 3560 | } |
| 3561 | } |
| 3562 | |
| 3563 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3564 | //===----------------------------------------------------------------------===// |
| 3565 | // Other Lowering Code |
| 3566 | //===----------------------------------------------------------------------===// |
| 3567 | |
Chris Lattner | 8a2d3ca | 2005-08-26 21:23:58 +0000 | [diff] [blame] | 3568 | MachineBasicBlock * |
Evan Cheng | ff9b373 | 2008-01-30 18:18:23 +0000 | [diff] [blame] | 3569 | PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, |
| 3570 | MachineBasicBlock *BB) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 3571 | const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); |
Chris Lattner | c08f902 | 2006-06-27 00:04:13 +0000 | [diff] [blame] | 3572 | assert((MI->getOpcode() == PPC::SELECT_CC_I4 || |
| 3573 | MI->getOpcode() == PPC::SELECT_CC_I8 || |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 3574 | MI->getOpcode() == PPC::SELECT_CC_F4 || |
Chris Lattner | 710ff32 | 2006-04-08 22:45:08 +0000 | [diff] [blame] | 3575 | MI->getOpcode() == PPC::SELECT_CC_F8 || |
| 3576 | MI->getOpcode() == PPC::SELECT_CC_VRRC) && |
Chris Lattner | 8a2d3ca | 2005-08-26 21:23:58 +0000 | [diff] [blame] | 3577 | "Unexpected instr type to insert"); |
| 3578 | |
| 3579 | // To "insert" a SELECT_CC instruction, we actually have to insert the diamond |
| 3580 | // control-flow pattern. The incoming instruction knows the destination vreg |
| 3581 | // to set, the condition code register to branch on, the true/false values to |
| 3582 | // select between, and a branch opcode to use. |
| 3583 | const BasicBlock *LLVM_BB = BB->getBasicBlock(); |
| 3584 | ilist<MachineBasicBlock>::iterator It = BB; |
| 3585 | ++It; |
| 3586 | |
| 3587 | // thisMBB: |
| 3588 | // ... |
| 3589 | // TrueVal = ... |
| 3590 | // cmpTY ccX, r1, r2 |
| 3591 | // bCC copy1MBB |
| 3592 | // fallthrough --> copy0MBB |
| 3593 | MachineBasicBlock *thisMBB = BB; |
| 3594 | MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); |
| 3595 | MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); |
Chris Lattner | df4ed63 | 2006-11-17 22:10:59 +0000 | [diff] [blame] | 3596 | unsigned SelectPred = MI->getOperand(4).getImm(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 3597 | BuildMI(BB, TII->get(PPC::BCC)) |
Chris Lattner | 18258c6 | 2006-11-17 22:37:34 +0000 | [diff] [blame] | 3598 | .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); |
Chris Lattner | 8a2d3ca | 2005-08-26 21:23:58 +0000 | [diff] [blame] | 3599 | MachineFunction *F = BB->getParent(); |
| 3600 | F->getBasicBlockList().insert(It, copy0MBB); |
| 3601 | F->getBasicBlockList().insert(It, sinkMBB); |
Nate Begeman | f15485a | 2006-03-27 01:32:24 +0000 | [diff] [blame] | 3602 | // Update machine-CFG edges by first adding all successors of the current |
| 3603 | // block to the new block which will contain the Phi node for the select. |
| 3604 | for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), |
| 3605 | e = BB->succ_end(); i != e; ++i) |
| 3606 | sinkMBB->addSuccessor(*i); |
| 3607 | // Next, remove all successors of the current block, and add the true |
| 3608 | // and fallthrough blocks as its successors. |
| 3609 | while(!BB->succ_empty()) |
| 3610 | BB->removeSuccessor(BB->succ_begin()); |
Chris Lattner | 8a2d3ca | 2005-08-26 21:23:58 +0000 | [diff] [blame] | 3611 | BB->addSuccessor(copy0MBB); |
| 3612 | BB->addSuccessor(sinkMBB); |
| 3613 | |
| 3614 | // copy0MBB: |
| 3615 | // %FalseValue = ... |
| 3616 | // # fallthrough to sinkMBB |
| 3617 | BB = copy0MBB; |
| 3618 | |
| 3619 | // Update machine-CFG edges |
| 3620 | BB->addSuccessor(sinkMBB); |
| 3621 | |
| 3622 | // sinkMBB: |
| 3623 | // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] |
| 3624 | // ... |
| 3625 | BB = sinkMBB; |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 3626 | BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg()) |
Chris Lattner | 8a2d3ca | 2005-08-26 21:23:58 +0000 | [diff] [blame] | 3627 | .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) |
| 3628 | .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); |
| 3629 | |
| 3630 | delete MI; // The pseudo instruction is gone now. |
| 3631 | return BB; |
| 3632 | } |
| 3633 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3634 | //===----------------------------------------------------------------------===// |
| 3635 | // Target Optimization Hooks |
| 3636 | //===----------------------------------------------------------------------===// |
| 3637 | |
Chris Lattner | 8c13d0a | 2006-03-01 04:57:39 +0000 | [diff] [blame] | 3638 | SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, |
| 3639 | DAGCombinerInfo &DCI) const { |
| 3640 | TargetMachine &TM = getTargetMachine(); |
| 3641 | SelectionDAG &DAG = DCI.DAG; |
| 3642 | switch (N->getOpcode()) { |
| 3643 | default: break; |
Chris Lattner | cf9d0ac | 2006-09-19 05:22:59 +0000 | [diff] [blame] | 3644 | case PPCISD::SHL: |
| 3645 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { |
| 3646 | if (C->getValue() == 0) // 0 << V -> 0. |
| 3647 | return N->getOperand(0); |
| 3648 | } |
| 3649 | break; |
| 3650 | case PPCISD::SRL: |
| 3651 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { |
| 3652 | if (C->getValue() == 0) // 0 >>u V -> 0. |
| 3653 | return N->getOperand(0); |
| 3654 | } |
| 3655 | break; |
| 3656 | case PPCISD::SRA: |
| 3657 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { |
| 3658 | if (C->getValue() == 0 || // 0 >>s V -> 0. |
| 3659 | C->isAllOnesValue()) // -1 >>s V -> -1. |
| 3660 | return N->getOperand(0); |
| 3661 | } |
| 3662 | break; |
| 3663 | |
Chris Lattner | 8c13d0a | 2006-03-01 04:57:39 +0000 | [diff] [blame] | 3664 | case ISD::SINT_TO_FP: |
Chris Lattner | a7a5854 | 2006-06-16 17:34:12 +0000 | [diff] [blame] | 3665 | if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { |
Chris Lattner | ecfe55e | 2006-03-22 05:30:33 +0000 | [diff] [blame] | 3666 | if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { |
| 3667 | // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. |
| 3668 | // We allow the src/dst to be either f32/f64, but the intermediate |
| 3669 | // type must be i64. |
Dale Johannesen | 7921706 | 2007-10-23 23:20:14 +0000 | [diff] [blame] | 3670 | if (N->getOperand(0).getValueType() == MVT::i64 && |
| 3671 | N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { |
Chris Lattner | ecfe55e | 2006-03-22 05:30:33 +0000 | [diff] [blame] | 3672 | SDOperand Val = N->getOperand(0).getOperand(0); |
| 3673 | if (Val.getValueType() == MVT::f32) { |
| 3674 | Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); |
| 3675 | DCI.AddToWorklist(Val.Val); |
| 3676 | } |
| 3677 | |
| 3678 | Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); |
Chris Lattner | 8c13d0a | 2006-03-01 04:57:39 +0000 | [diff] [blame] | 3679 | DCI.AddToWorklist(Val.Val); |
Chris Lattner | ecfe55e | 2006-03-22 05:30:33 +0000 | [diff] [blame] | 3680 | Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); |
Chris Lattner | 8c13d0a | 2006-03-01 04:57:39 +0000 | [diff] [blame] | 3681 | DCI.AddToWorklist(Val.Val); |
Chris Lattner | ecfe55e | 2006-03-22 05:30:33 +0000 | [diff] [blame] | 3682 | if (N->getValueType(0) == MVT::f32) { |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 3683 | Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val, |
| 3684 | DAG.getIntPtrConstant(0)); |
Chris Lattner | ecfe55e | 2006-03-22 05:30:33 +0000 | [diff] [blame] | 3685 | DCI.AddToWorklist(Val.Val); |
| 3686 | } |
| 3687 | return Val; |
| 3688 | } else if (N->getOperand(0).getValueType() == MVT::i32) { |
| 3689 | // If the intermediate type is i32, we can avoid the load/store here |
| 3690 | // too. |
Chris Lattner | 8c13d0a | 2006-03-01 04:57:39 +0000 | [diff] [blame] | 3691 | } |
Chris Lattner | 8c13d0a | 2006-03-01 04:57:39 +0000 | [diff] [blame] | 3692 | } |
| 3693 | } |
| 3694 | break; |
Chris Lattner | 5126984 | 2006-03-01 05:50:56 +0000 | [diff] [blame] | 3695 | case ISD::STORE: |
| 3696 | // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). |
| 3697 | if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && |
Chris Lattner | a7a02fb | 2008-01-18 16:54:56 +0000 | [diff] [blame] | 3698 | !cast<StoreSDNode>(N)->isTruncatingStore() && |
Chris Lattner | 5126984 | 2006-03-01 05:50:56 +0000 | [diff] [blame] | 3699 | N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && |
Dale Johannesen | 7921706 | 2007-10-23 23:20:14 +0000 | [diff] [blame] | 3700 | N->getOperand(1).getValueType() == MVT::i32 && |
| 3701 | N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { |
Chris Lattner | 5126984 | 2006-03-01 05:50:56 +0000 | [diff] [blame] | 3702 | SDOperand Val = N->getOperand(1).getOperand(0); |
| 3703 | if (Val.getValueType() == MVT::f32) { |
| 3704 | Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); |
| 3705 | DCI.AddToWorklist(Val.Val); |
| 3706 | } |
| 3707 | Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); |
| 3708 | DCI.AddToWorklist(Val.Val); |
| 3709 | |
| 3710 | Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, |
| 3711 | N->getOperand(2), N->getOperand(3)); |
| 3712 | DCI.AddToWorklist(Val.Val); |
| 3713 | return Val; |
| 3714 | } |
Chris Lattner | d998938 | 2006-07-10 20:56:58 +0000 | [diff] [blame] | 3715 | |
| 3716 | // Turn STORE (BSWAP) -> sthbrx/stwbrx. |
| 3717 | if (N->getOperand(1).getOpcode() == ISD::BSWAP && |
| 3718 | N->getOperand(1).Val->hasOneUse() && |
| 3719 | (N->getOperand(1).getValueType() == MVT::i32 || |
| 3720 | N->getOperand(1).getValueType() == MVT::i16)) { |
| 3721 | SDOperand BSwapOp = N->getOperand(1).getOperand(0); |
| 3722 | // Do an any-extend to 32-bits if this is a half-word input. |
| 3723 | if (BSwapOp.getValueType() == MVT::i16) |
| 3724 | BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp); |
| 3725 | |
| 3726 | return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp, |
| 3727 | N->getOperand(2), N->getOperand(3), |
| 3728 | DAG.getValueType(N->getOperand(1).getValueType())); |
| 3729 | } |
| 3730 | break; |
| 3731 | case ISD::BSWAP: |
| 3732 | // Turn BSWAP (LOAD) -> lhbrx/lwbrx. |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 3733 | if (ISD::isNON_EXTLoad(N->getOperand(0).Val) && |
Chris Lattner | d998938 | 2006-07-10 20:56:58 +0000 | [diff] [blame] | 3734 | N->getOperand(0).hasOneUse() && |
| 3735 | (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { |
| 3736 | SDOperand Load = N->getOperand(0); |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 3737 | LoadSDNode *LD = cast<LoadSDNode>(Load); |
Chris Lattner | d998938 | 2006-07-10 20:56:58 +0000 | [diff] [blame] | 3738 | // Create the byte-swapping load. |
| 3739 | std::vector<MVT::ValueType> VTs; |
| 3740 | VTs.push_back(MVT::i32); |
| 3741 | VTs.push_back(MVT::Other); |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 3742 | SDOperand MO = DAG.getMemOperand(LD->getMemOperand()); |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 3743 | SDOperand Ops[] = { |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 3744 | LD->getChain(), // Chain |
| 3745 | LD->getBasePtr(), // Ptr |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 3746 | MO, // MemOperand |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 3747 | DAG.getValueType(N->getValueType(0)) // VT |
| 3748 | }; |
| 3749 | SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); |
Chris Lattner | d998938 | 2006-07-10 20:56:58 +0000 | [diff] [blame] | 3750 | |
| 3751 | // If this is an i16 load, insert the truncate. |
| 3752 | SDOperand ResVal = BSLoad; |
| 3753 | if (N->getValueType(0) == MVT::i16) |
| 3754 | ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad); |
| 3755 | |
| 3756 | // First, combine the bswap away. This makes the value produced by the |
| 3757 | // load dead. |
| 3758 | DCI.CombineTo(N, ResVal); |
| 3759 | |
| 3760 | // Next, combine the load away, we give it a bogus result value but a real |
| 3761 | // chain result. The result value is dead because the bswap is dead. |
| 3762 | DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1)); |
| 3763 | |
| 3764 | // Return N so it doesn't get rechecked! |
| 3765 | return SDOperand(N, 0); |
| 3766 | } |
| 3767 | |
Chris Lattner | 5126984 | 2006-03-01 05:50:56 +0000 | [diff] [blame] | 3768 | break; |
Chris Lattner | 4468c22 | 2006-03-31 06:02:07 +0000 | [diff] [blame] | 3769 | case PPCISD::VCMP: { |
| 3770 | // If a VCMPo node already exists with exactly the same operands as this |
| 3771 | // node, use its result instead of this node (VCMPo computes both a CR6 and |
| 3772 | // a normal output). |
| 3773 | // |
| 3774 | if (!N->getOperand(0).hasOneUse() && |
| 3775 | !N->getOperand(1).hasOneUse() && |
| 3776 | !N->getOperand(2).hasOneUse()) { |
| 3777 | |
| 3778 | // Scan all of the users of the LHS, looking for VCMPo's that match. |
| 3779 | SDNode *VCMPoNode = 0; |
| 3780 | |
| 3781 | SDNode *LHSN = N->getOperand(0).Val; |
| 3782 | for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); |
| 3783 | UI != E; ++UI) |
Roman Levenstein | dc1adac | 2008-04-07 10:06:32 +0000 | [diff] [blame] | 3784 | if ((*UI).getUser()->getOpcode() == PPCISD::VCMPo && |
| 3785 | (*UI).getUser()->getOperand(1) == N->getOperand(1) && |
| 3786 | (*UI).getUser()->getOperand(2) == N->getOperand(2) && |
| 3787 | (*UI).getUser()->getOperand(0) == N->getOperand(0)) { |
| 3788 | VCMPoNode = UI->getUser(); |
Chris Lattner | 4468c22 | 2006-03-31 06:02:07 +0000 | [diff] [blame] | 3789 | break; |
| 3790 | } |
| 3791 | |
Chris Lattner | 0090120 | 2006-04-18 18:28:22 +0000 | [diff] [blame] | 3792 | // If there is no VCMPo node, or if the flag value has a single use, don't |
| 3793 | // transform this. |
| 3794 | if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) |
| 3795 | break; |
| 3796 | |
| 3797 | // Look at the (necessarily single) use of the flag value. If it has a |
| 3798 | // chain, this transformation is more complex. Note that multiple things |
| 3799 | // could use the value result, which we should ignore. |
| 3800 | SDNode *FlagUser = 0; |
| 3801 | for (SDNode::use_iterator UI = VCMPoNode->use_begin(); |
| 3802 | FlagUser == 0; ++UI) { |
| 3803 | assert(UI != VCMPoNode->use_end() && "Didn't find user!"); |
Roman Levenstein | dc1adac | 2008-04-07 10:06:32 +0000 | [diff] [blame] | 3804 | SDNode *User = UI->getUser(); |
Chris Lattner | 0090120 | 2006-04-18 18:28:22 +0000 | [diff] [blame] | 3805 | for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { |
| 3806 | if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) { |
| 3807 | FlagUser = User; |
| 3808 | break; |
| 3809 | } |
| 3810 | } |
| 3811 | } |
| 3812 | |
| 3813 | // If the user is a MFCR instruction, we know this is safe. Otherwise we |
| 3814 | // give up for right now. |
| 3815 | if (FlagUser->getOpcode() == PPCISD::MFCR) |
Chris Lattner | 4468c22 | 2006-03-31 06:02:07 +0000 | [diff] [blame] | 3816 | return SDOperand(VCMPoNode, 0); |
| 3817 | } |
| 3818 | break; |
| 3819 | } |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3820 | case ISD::BR_CC: { |
| 3821 | // If this is a branch on an altivec predicate comparison, lower this so |
| 3822 | // that we don't have to do a MFCR: instead, branch directly on CR6. This |
| 3823 | // lowering is done pre-legalize, because the legalizer lowers the predicate |
| 3824 | // compare down to code that is difficult to reassemble. |
| 3825 | ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); |
| 3826 | SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3); |
| 3827 | int CompareOpc; |
| 3828 | bool isDot; |
| 3829 | |
| 3830 | if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && |
| 3831 | isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && |
| 3832 | getAltivecCompareInfo(LHS, CompareOpc, isDot)) { |
| 3833 | assert(isDot && "Can't compare against a vector result!"); |
| 3834 | |
| 3835 | // If this is a comparison against something other than 0/1, then we know |
| 3836 | // that the condition is never/always true. |
| 3837 | unsigned Val = cast<ConstantSDNode>(RHS)->getValue(); |
| 3838 | if (Val != 0 && Val != 1) { |
| 3839 | if (CC == ISD::SETEQ) // Cond never true, remove branch. |
| 3840 | return N->getOperand(0); |
| 3841 | // Always !=, turn it into an unconditional branch. |
| 3842 | return DAG.getNode(ISD::BR, MVT::Other, |
| 3843 | N->getOperand(0), N->getOperand(4)); |
| 3844 | } |
| 3845 | |
| 3846 | bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); |
| 3847 | |
| 3848 | // Create the PPCISD altivec 'dot' comparison node. |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3849 | std::vector<MVT::ValueType> VTs; |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 3850 | SDOperand Ops[] = { |
| 3851 | LHS.getOperand(2), // LHS of compare |
| 3852 | LHS.getOperand(3), // RHS of compare |
| 3853 | DAG.getConstant(CompareOpc, MVT::i32) |
| 3854 | }; |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3855 | VTs.push_back(LHS.getOperand(2).getValueType()); |
| 3856 | VTs.push_back(MVT::Flag); |
Chris Lattner | 79e490a | 2006-08-11 17:18:05 +0000 | [diff] [blame] | 3857 | SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3858 | |
| 3859 | // Unpack the result based on how the target uses it. |
Chris Lattner | df4ed63 | 2006-11-17 22:10:59 +0000 | [diff] [blame] | 3860 | PPC::Predicate CompOpc; |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3861 | switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) { |
| 3862 | default: // Can't happen, don't crash on invalid number though. |
| 3863 | case 0: // Branch on the value of the EQ bit of CR6. |
Chris Lattner | df4ed63 | 2006-11-17 22:10:59 +0000 | [diff] [blame] | 3864 | CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3865 | break; |
| 3866 | case 1: // Branch on the inverted value of the EQ bit of CR6. |
Chris Lattner | df4ed63 | 2006-11-17 22:10:59 +0000 | [diff] [blame] | 3867 | CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3868 | break; |
| 3869 | case 2: // Branch on the value of the LT bit of CR6. |
Chris Lattner | df4ed63 | 2006-11-17 22:10:59 +0000 | [diff] [blame] | 3870 | CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3871 | break; |
| 3872 | case 3: // Branch on the inverted value of the LT bit of CR6. |
Chris Lattner | df4ed63 | 2006-11-17 22:10:59 +0000 | [diff] [blame] | 3873 | CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3874 | break; |
| 3875 | } |
| 3876 | |
| 3877 | return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0), |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3878 | DAG.getConstant(CompOpc, MVT::i32), |
Chris Lattner | 18258c6 | 2006-11-17 22:37:34 +0000 | [diff] [blame] | 3879 | DAG.getRegister(PPC::CR6, MVT::i32), |
Chris Lattner | 90564f2 | 2006-04-18 17:59:36 +0000 | [diff] [blame] | 3880 | N->getOperand(4), CompNode.getValue(1)); |
| 3881 | } |
| 3882 | break; |
| 3883 | } |
Chris Lattner | 8c13d0a | 2006-03-01 04:57:39 +0000 | [diff] [blame] | 3884 | } |
| 3885 | |
| 3886 | return SDOperand(); |
| 3887 | } |
| 3888 | |
Chris Lattner | 1a635d6 | 2006-04-14 06:01:58 +0000 | [diff] [blame] | 3889 | //===----------------------------------------------------------------------===// |
| 3890 | // Inline Assembly Support |
| 3891 | //===----------------------------------------------------------------------===// |
| 3892 | |
Chris Lattner | bbe77de | 2006-04-02 06:26:07 +0000 | [diff] [blame] | 3893 | void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, |
Dan Gohman | 977a76f | 2008-02-13 22:28:48 +0000 | [diff] [blame] | 3894 | const APInt &Mask, |
Dan Gohman | fd29e0e | 2008-02-13 00:35:47 +0000 | [diff] [blame] | 3895 | APInt &KnownZero, |
| 3896 | APInt &KnownOne, |
Dan Gohman | ea859be | 2007-06-22 14:59:07 +0000 | [diff] [blame] | 3897 | const SelectionDAG &DAG, |
Chris Lattner | bbe77de | 2006-04-02 06:26:07 +0000 | [diff] [blame] | 3898 | unsigned Depth) const { |
Dan Gohman | fd29e0e | 2008-02-13 00:35:47 +0000 | [diff] [blame] | 3899 | KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); |
Chris Lattner | bbe77de | 2006-04-02 06:26:07 +0000 | [diff] [blame] | 3900 | switch (Op.getOpcode()) { |
| 3901 | default: break; |
Chris Lattner | d998938 | 2006-07-10 20:56:58 +0000 | [diff] [blame] | 3902 | case PPCISD::LBRX: { |
| 3903 | // lhbrx is known to have the top bits cleared out. |
| 3904 | if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16) |
| 3905 | KnownZero = 0xFFFF0000; |
| 3906 | break; |
| 3907 | } |
Chris Lattner | bbe77de | 2006-04-02 06:26:07 +0000 | [diff] [blame] | 3908 | case ISD::INTRINSIC_WO_CHAIN: { |
| 3909 | switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) { |
| 3910 | default: break; |
| 3911 | case Intrinsic::ppc_altivec_vcmpbfp_p: |
| 3912 | case Intrinsic::ppc_altivec_vcmpeqfp_p: |
| 3913 | case Intrinsic::ppc_altivec_vcmpequb_p: |
| 3914 | case Intrinsic::ppc_altivec_vcmpequh_p: |
| 3915 | case Intrinsic::ppc_altivec_vcmpequw_p: |
| 3916 | case Intrinsic::ppc_altivec_vcmpgefp_p: |
| 3917 | case Intrinsic::ppc_altivec_vcmpgtfp_p: |
| 3918 | case Intrinsic::ppc_altivec_vcmpgtsb_p: |
| 3919 | case Intrinsic::ppc_altivec_vcmpgtsh_p: |
| 3920 | case Intrinsic::ppc_altivec_vcmpgtsw_p: |
| 3921 | case Intrinsic::ppc_altivec_vcmpgtub_p: |
| 3922 | case Intrinsic::ppc_altivec_vcmpgtuh_p: |
| 3923 | case Intrinsic::ppc_altivec_vcmpgtuw_p: |
| 3924 | KnownZero = ~1U; // All bits but the low one are known to be zero. |
| 3925 | break; |
| 3926 | } |
| 3927 | } |
| 3928 | } |
| 3929 | } |
| 3930 | |
| 3931 | |
Chris Lattner | 4234f57 | 2007-03-25 02:14:49 +0000 | [diff] [blame] | 3932 | /// getConstraintType - Given a constraint, return the type of |
Chris Lattner | ad3bc8d | 2006-02-07 20:16:30 +0000 | [diff] [blame] | 3933 | /// constraint it is for this target. |
| 3934 | PPCTargetLowering::ConstraintType |
Chris Lattner | 4234f57 | 2007-03-25 02:14:49 +0000 | [diff] [blame] | 3935 | PPCTargetLowering::getConstraintType(const std::string &Constraint) const { |
| 3936 | if (Constraint.size() == 1) { |
| 3937 | switch (Constraint[0]) { |
| 3938 | default: break; |
| 3939 | case 'b': |
| 3940 | case 'r': |
| 3941 | case 'f': |
| 3942 | case 'v': |
| 3943 | case 'y': |
| 3944 | return C_RegisterClass; |
| 3945 | } |
| 3946 | } |
| 3947 | return TargetLowering::getConstraintType(Constraint); |
Chris Lattner | ad3bc8d | 2006-02-07 20:16:30 +0000 | [diff] [blame] | 3948 | } |
| 3949 | |
Chris Lattner | 331d1bc | 2006-11-02 01:44:04 +0000 | [diff] [blame] | 3950 | std::pair<unsigned, const TargetRegisterClass*> |
| 3951 | PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, |
| 3952 | MVT::ValueType VT) const { |
Chris Lattner | ddc787d | 2006-01-31 19:20:21 +0000 | [diff] [blame] | 3953 | if (Constraint.size() == 1) { |
Chris Lattner | 331d1bc | 2006-11-02 01:44:04 +0000 | [diff] [blame] | 3954 | // GCC RS6000 Constraint Letters |
| 3955 | switch (Constraint[0]) { |
| 3956 | case 'b': // R1-R31 |
| 3957 | case 'r': // R0-R31 |
| 3958 | if (VT == MVT::i64 && PPCSubTarget.isPPC64()) |
| 3959 | return std::make_pair(0U, PPC::G8RCRegisterClass); |
| 3960 | return std::make_pair(0U, PPC::GPRCRegisterClass); |
| 3961 | case 'f': |
| 3962 | if (VT == MVT::f32) |
| 3963 | return std::make_pair(0U, PPC::F4RCRegisterClass); |
| 3964 | else if (VT == MVT::f64) |
| 3965 | return std::make_pair(0U, PPC::F8RCRegisterClass); |
| 3966 | break; |
Chris Lattner | ddc787d | 2006-01-31 19:20:21 +0000 | [diff] [blame] | 3967 | case 'v': |
Chris Lattner | 331d1bc | 2006-11-02 01:44:04 +0000 | [diff] [blame] | 3968 | return std::make_pair(0U, PPC::VRRCRegisterClass); |
| 3969 | case 'y': // crrc |
| 3970 | return std::make_pair(0U, PPC::CRRCRegisterClass); |
Chris Lattner | ddc787d | 2006-01-31 19:20:21 +0000 | [diff] [blame] | 3971 | } |
| 3972 | } |
| 3973 | |
Chris Lattner | 331d1bc | 2006-11-02 01:44:04 +0000 | [diff] [blame] | 3974 | return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); |
Chris Lattner | ddc787d | 2006-01-31 19:20:21 +0000 | [diff] [blame] | 3975 | } |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 3976 | |
Chris Lattner | 331d1bc | 2006-11-02 01:44:04 +0000 | [diff] [blame] | 3977 | |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 3978 | /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops |
| 3979 | /// vector. If it is invalid, don't add anything to Ops. |
| 3980 | void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter, |
| 3981 | std::vector<SDOperand>&Ops, |
| 3982 | SelectionDAG &DAG) { |
| 3983 | SDOperand Result(0,0); |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 3984 | switch (Letter) { |
| 3985 | default: break; |
| 3986 | case 'I': |
| 3987 | case 'J': |
| 3988 | case 'K': |
| 3989 | case 'L': |
| 3990 | case 'M': |
| 3991 | case 'N': |
| 3992 | case 'O': |
| 3993 | case 'P': { |
Chris Lattner | 9f5d578 | 2007-05-15 01:31:05 +0000 | [diff] [blame] | 3994 | ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 3995 | if (!CST) return; // Must be an immediate to match. |
Chris Lattner | 9f5d578 | 2007-05-15 01:31:05 +0000 | [diff] [blame] | 3996 | unsigned Value = CST->getValue(); |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 3997 | switch (Letter) { |
| 3998 | default: assert(0 && "Unknown constraint letter!"); |
| 3999 | case 'I': // "I" is a signed 16-bit constant. |
Chris Lattner | 9f5d578 | 2007-05-15 01:31:05 +0000 | [diff] [blame] | 4000 | if ((short)Value == (int)Value) |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 4001 | Result = DAG.getTargetConstant(Value, Op.getValueType()); |
Chris Lattner | dba1aee | 2006-10-31 19:40:43 +0000 | [diff] [blame] | 4002 | break; |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 4003 | case 'J': // "J" is a constant with only the high-order 16 bits nonzero. |
| 4004 | case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. |
Chris Lattner | 9f5d578 | 2007-05-15 01:31:05 +0000 | [diff] [blame] | 4005 | if ((short)Value == 0) |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 4006 | Result = DAG.getTargetConstant(Value, Op.getValueType()); |
Chris Lattner | dba1aee | 2006-10-31 19:40:43 +0000 | [diff] [blame] | 4007 | break; |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 4008 | case 'K': // "K" is a constant with only the low-order 16 bits nonzero. |
Chris Lattner | 9f5d578 | 2007-05-15 01:31:05 +0000 | [diff] [blame] | 4009 | if ((Value >> 16) == 0) |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 4010 | Result = DAG.getTargetConstant(Value, Op.getValueType()); |
Chris Lattner | dba1aee | 2006-10-31 19:40:43 +0000 | [diff] [blame] | 4011 | break; |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 4012 | case 'M': // "M" is a constant that is greater than 31. |
Chris Lattner | 9f5d578 | 2007-05-15 01:31:05 +0000 | [diff] [blame] | 4013 | if (Value > 31) |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 4014 | Result = DAG.getTargetConstant(Value, Op.getValueType()); |
Chris Lattner | dba1aee | 2006-10-31 19:40:43 +0000 | [diff] [blame] | 4015 | break; |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 4016 | case 'N': // "N" is a positive constant that is an exact power of two. |
Chris Lattner | 9f5d578 | 2007-05-15 01:31:05 +0000 | [diff] [blame] | 4017 | if ((int)Value > 0 && isPowerOf2_32(Value)) |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 4018 | Result = DAG.getTargetConstant(Value, Op.getValueType()); |
Chris Lattner | dba1aee | 2006-10-31 19:40:43 +0000 | [diff] [blame] | 4019 | break; |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 4020 | case 'O': // "O" is the constant zero. |
Chris Lattner | 9f5d578 | 2007-05-15 01:31:05 +0000 | [diff] [blame] | 4021 | if (Value == 0) |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 4022 | Result = DAG.getTargetConstant(Value, Op.getValueType()); |
Chris Lattner | dba1aee | 2006-10-31 19:40:43 +0000 | [diff] [blame] | 4023 | break; |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 4024 | case 'P': // "P" is a constant whose negation is a signed 16-bit constant. |
Chris Lattner | 9f5d578 | 2007-05-15 01:31:05 +0000 | [diff] [blame] | 4025 | if ((short)-Value == (int)-Value) |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 4026 | Result = DAG.getTargetConstant(Value, Op.getValueType()); |
Chris Lattner | dba1aee | 2006-10-31 19:40:43 +0000 | [diff] [blame] | 4027 | break; |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 4028 | } |
| 4029 | break; |
| 4030 | } |
| 4031 | } |
| 4032 | |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 4033 | if (Result.Val) { |
| 4034 | Ops.push_back(Result); |
| 4035 | return; |
| 4036 | } |
| 4037 | |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 4038 | // Handle standard constraint letters. |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 4039 | TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG); |
Chris Lattner | 763317d | 2006-02-07 00:47:13 +0000 | [diff] [blame] | 4040 | } |
Evan Cheng | c4c6257 | 2006-03-13 23:20:37 +0000 | [diff] [blame] | 4041 | |
Chris Lattner | c9addb7 | 2007-03-30 23:15:24 +0000 | [diff] [blame] | 4042 | // isLegalAddressingMode - Return true if the addressing mode represented |
| 4043 | // by AM is legal for this target, for a load/store of the specified type. |
| 4044 | bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, |
| 4045 | const Type *Ty) const { |
| 4046 | // FIXME: PPC does not allow r+i addressing modes for vectors! |
| 4047 | |
| 4048 | // PPC allows a sign-extended 16-bit immediate field. |
| 4049 | if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) |
| 4050 | return false; |
| 4051 | |
| 4052 | // No global is ever allowed as a base. |
| 4053 | if (AM.BaseGV) |
| 4054 | return false; |
| 4055 | |
| 4056 | // PPC only support r+r, |
| 4057 | switch (AM.Scale) { |
| 4058 | case 0: // "r+i" or just "i", depending on HasBaseReg. |
| 4059 | break; |
| 4060 | case 1: |
| 4061 | if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. |
| 4062 | return false; |
| 4063 | // Otherwise we have r+r or r+i. |
| 4064 | break; |
| 4065 | case 2: |
| 4066 | if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. |
| 4067 | return false; |
| 4068 | // Allow 2*r as r+r. |
| 4069 | break; |
Chris Lattner | 7c7ba9d | 2007-04-09 22:10:05 +0000 | [diff] [blame] | 4070 | default: |
| 4071 | // No other scales are supported. |
| 4072 | return false; |
Chris Lattner | c9addb7 | 2007-03-30 23:15:24 +0000 | [diff] [blame] | 4073 | } |
| 4074 | |
| 4075 | return true; |
| 4076 | } |
| 4077 | |
Evan Cheng | c4c6257 | 2006-03-13 23:20:37 +0000 | [diff] [blame] | 4078 | /// isLegalAddressImmediate - Return true if the integer value can be used |
Evan Cheng | 8619391 | 2007-03-12 23:29:01 +0000 | [diff] [blame] | 4079 | /// as the offset of the target addressing mode for load / store of the |
| 4080 | /// given type. |
| 4081 | bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{ |
Evan Cheng | c4c6257 | 2006-03-13 23:20:37 +0000 | [diff] [blame] | 4082 | // PPC allows a sign-extended 16-bit immediate field. |
| 4083 | return (V > -(1 << 16) && V < (1 << 16)-1); |
| 4084 | } |
Reid Spencer | 3a9ec24 | 2006-08-28 01:02:49 +0000 | [diff] [blame] | 4085 | |
| 4086 | bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { |
Chris Lattner | c9addb7 | 2007-03-30 23:15:24 +0000 | [diff] [blame] | 4087 | return false; |
Reid Spencer | 3a9ec24 | 2006-08-28 01:02:49 +0000 | [diff] [blame] | 4088 | } |
Nicolas Geoffray | 43c6e7c | 2007-03-01 13:11:38 +0000 | [diff] [blame] | 4089 | |
Chris Lattner | 3fc027d | 2007-12-08 06:59:59 +0000 | [diff] [blame] | 4090 | SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) { |
| 4091 | // Depths > 0 not supported yet! |
| 4092 | if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) |
| 4093 | return SDOperand(); |
| 4094 | |
| 4095 | MachineFunction &MF = DAG.getMachineFunction(); |
| 4096 | PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); |
| 4097 | int RAIdx = FuncInfo->getReturnAddrSaveIndex(); |
| 4098 | if (RAIdx == 0) { |
| 4099 | bool isPPC64 = PPCSubTarget.isPPC64(); |
| 4100 | int Offset = |
| 4101 | PPCFrameInfo::getReturnSaveOffset(isPPC64, PPCSubTarget.isMachoABI()); |
| 4102 | |
| 4103 | // Set up a frame object for the return address. |
| 4104 | RAIdx = MF.getFrameInfo()->CreateFixedObject(isPPC64 ? 8 : 4, Offset); |
| 4105 | |
| 4106 | // Remember it for next time. |
| 4107 | FuncInfo->setReturnAddrSaveIndex(RAIdx); |
| 4108 | |
| 4109 | // Make sure the function really does not optimize away the store of the RA |
| 4110 | // to the stack. |
| 4111 | FuncInfo->setLRStoreRequired(); |
| 4112 | } |
| 4113 | |
| 4114 | // Just load the return address off the stack. |
| 4115 | SDOperand RetAddrFI = DAG.getFrameIndex(RAIdx, getPointerTy()); |
| 4116 | return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); |
| 4117 | } |
| 4118 | |
| 4119 | SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) { |
Nicolas Geoffray | 43c6e7c | 2007-03-01 13:11:38 +0000 | [diff] [blame] | 4120 | // Depths > 0 not supported yet! |
| 4121 | if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) |
| 4122 | return SDOperand(); |
| 4123 | |
| 4124 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
| 4125 | bool isPPC64 = PtrVT == MVT::i64; |
| 4126 | |
| 4127 | MachineFunction &MF = DAG.getMachineFunction(); |
| 4128 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 4129 | bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects()) |
| 4130 | && MFI->getStackSize(); |
| 4131 | |
| 4132 | if (isPPC64) |
| 4133 | return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1, |
Bill Wendling | b8a80f0 | 2007-08-30 00:59:19 +0000 | [diff] [blame] | 4134 | MVT::i64); |
Nicolas Geoffray | 43c6e7c | 2007-03-01 13:11:38 +0000 | [diff] [blame] | 4135 | else |
| 4136 | return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1, |
| 4137 | MVT::i32); |
| 4138 | } |