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Chaithrika U Sb67f4482009-06-05 06:28:40 -04001/*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040022#include <linux/delay.h>
23#include <linux/io.h>
Peter Ujfalusiae726e92013-11-14 11:35:35 +020024#include <linux/clk.h>
Hebbar, Gururaja10884342012-08-08 20:40:32 +053025#include <linux/pm_runtime.h>
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +053026#include <linux/of.h>
27#include <linux/of_platform.h>
28#include <linux/of_device.h>
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +020029#include <linux/platform_data/davinci_asp.h>
Jyri Sarhaa75a0532015-03-20 13:31:08 +020030#include <linux/math64.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040031
Daniel Mack64792852014-03-27 11:27:40 +010032#include <sound/asoundef.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040033#include <sound/core.h>
34#include <sound/pcm.h>
35#include <sound/pcm_params.h>
36#include <sound/initval.h>
37#include <sound/soc.h>
Peter Ujfalusi453c4992013-11-14 11:35:34 +020038#include <sound/dmaengine_pcm.h>
Jyri Sarha87c19362014-05-26 11:51:14 +030039#include <sound/omap-pcm.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040040
Peter Ujfalusif3f9cfa2014-07-16 15:12:04 +030041#include "edma-pcm.h"
Chaithrika U Sb67f4482009-06-05 06:28:40 -040042#include "davinci-mcasp.h"
43
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +030044#define MCASP_MAX_AFIFO_DEPTH 64
45
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +030046static u32 context_regs[] = {
47 DAVINCI_MCASP_TXFMCTL_REG,
48 DAVINCI_MCASP_RXFMCTL_REG,
49 DAVINCI_MCASP_TXFMT_REG,
50 DAVINCI_MCASP_RXFMT_REG,
51 DAVINCI_MCASP_ACLKXCTL_REG,
52 DAVINCI_MCASP_ACLKRCTL_REG,
Peter Ujfalusif114ce62014-10-01 16:02:12 +030053 DAVINCI_MCASP_AHCLKXCTL_REG,
54 DAVINCI_MCASP_AHCLKRCTL_REG,
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +030055 DAVINCI_MCASP_PDIR_REG,
Peter Ujfalusif114ce62014-10-01 16:02:12 +030056 DAVINCI_MCASP_RXMASK_REG,
57 DAVINCI_MCASP_TXMASK_REG,
58 DAVINCI_MCASP_RXTDM_REG,
59 DAVINCI_MCASP_TXTDM_REG,
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +030060};
61
Peter Ujfalusi790bb942014-02-03 14:51:52 +020062struct davinci_mcasp_context {
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +030063 u32 config_regs[ARRAY_SIZE(context_regs)];
Peter Ujfalusif114ce62014-10-01 16:02:12 +030064 u32 afifo_regs[2]; /* for read/write fifo control registers */
65 u32 *xrsr_regs; /* for serializer configuration */
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +020066 bool pm_state;
Peter Ujfalusi790bb942014-02-03 14:51:52 +020067};
68
Jyri Sarhaa75a0532015-03-20 13:31:08 +020069struct davinci_mcasp_ruledata {
70 struct davinci_mcasp *mcasp;
71 int serializers;
72};
73
Peter Ujfalusi70091a32013-11-14 11:35:29 +020074struct davinci_mcasp {
Peter Ujfalusi453c4992013-11-14 11:35:34 +020075 struct snd_dmaengine_dai_dma_data dma_data[2];
Peter Ujfalusi21400a72013-11-14 11:35:26 +020076 void __iomem *base;
Peter Ujfalusi487dce82013-11-14 11:35:31 +020077 u32 fifo_base;
Peter Ujfalusi21400a72013-11-14 11:35:26 +020078 struct device *dev;
Misael Lopez Cruza7a33242014-11-12 16:38:05 +020079 struct snd_pcm_substream *substreams[2];
Peter Ujfalusi21400a72013-11-14 11:35:26 +020080
81 /* McASP specific data */
82 int tdm_slots;
83 u8 op_mode;
84 u8 num_serializer;
85 u8 *serial_dir;
86 u8 version;
Daniel Mack82675252014-07-16 14:04:41 +020087 u8 bclk_div;
Peter Ujfalusi21400a72013-11-14 11:35:26 +020088 u16 bclk_lrclk_ratio;
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +020089 int streams;
Misael Lopez Cruza7a33242014-11-12 16:38:05 +020090 u32 irq_request[2];
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +020091 int dma_request[2];
Peter Ujfalusi21400a72013-11-14 11:35:26 +020092
Jyri Sarhaab8b14b2014-01-27 17:37:52 +020093 int sysclk_freq;
94 bool bclk_master;
95
Peter Ujfalusi21400a72013-11-14 11:35:26 +020096 /* McASP FIFO related */
97 u8 txnumevt;
98 u8 rxnumevt;
99
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +0200100 bool dat_port;
101
Peter Ujfalusi11277832014-11-10 12:32:16 +0200102 /* Used for comstraint setting on the second stream */
103 u32 channels;
104
Peter Ujfalusi21400a72013-11-14 11:35:26 +0200105#ifdef CONFIG_PM_SLEEP
Peter Ujfalusi790bb942014-02-03 14:51:52 +0200106 struct davinci_mcasp_context context;
Peter Ujfalusi21400a72013-11-14 11:35:26 +0200107#endif
Jyri Sarhaa75a0532015-03-20 13:31:08 +0200108
109 struct davinci_mcasp_ruledata ruledata[2];
Jyri Sarha5935a052015-04-23 16:16:05 +0300110 struct snd_pcm_hw_constraint_list chconstr[2];
Peter Ujfalusi21400a72013-11-14 11:35:26 +0200111};
112
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200113static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
114 u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400115{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200116 void __iomem *reg = mcasp->base + offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400117 __raw_writel(__raw_readl(reg) | val, reg);
118}
119
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200120static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
121 u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400122{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200123 void __iomem *reg = mcasp->base + offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400124 __raw_writel((__raw_readl(reg) & ~(val)), reg);
125}
126
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200127static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
128 u32 val, u32 mask)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400129{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200130 void __iomem *reg = mcasp->base + offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400131 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
132}
133
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200134static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
135 u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400136{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200137 __raw_writel(val, mcasp->base + offset);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400138}
139
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200140static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400141{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200142 return (u32)__raw_readl(mcasp->base + offset);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400143}
144
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200145static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400146{
147 int i = 0;
148
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200149 mcasp_set_bits(mcasp, ctl_reg, val);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400150
151 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
152 /* loop count is to avoid the lock-up */
153 for (i = 0; i < 1000; i++) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200154 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400155 break;
156 }
157
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200158 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400159 printk(KERN_ERR "GBLCTL write error\n");
160}
161
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200162static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
163{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200164 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
165 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200166
167 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
168}
169
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200170static void mcasp_start_rx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400171{
Peter Ujfalusibb372af2014-10-29 13:55:47 +0200172 if (mcasp->rxnumevt) { /* enable FIFO */
173 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
174
175 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
176 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
177 }
178
Peter Ujfalusi44982732014-10-29 13:55:45 +0200179 /* Start clocks */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200180 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
181 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200182 /*
183 * When ASYNC == 0 the transmit and receive sections operate
184 * synchronously from the transmit clock and frame sync. We need to make
185 * sure that the TX signlas are enabled when starting reception.
186 */
187 if (mcasp_is_synchronous(mcasp)) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200188 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
189 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200190 }
191
Peter Ujfalusi44982732014-10-29 13:55:45 +0200192 /* Activate serializer(s) */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200193 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
Peter Ujfalusi44982732014-10-29 13:55:45 +0200194 /* Release RX state machine */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200195 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
Peter Ujfalusi44982732014-10-29 13:55:45 +0200196 /* Release Frame Sync generator */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200197 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200198 if (mcasp_is_synchronous(mcasp))
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200199 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
Misael Lopez Cruza7a33242014-11-12 16:38:05 +0200200
201 /* enable receive IRQs */
202 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
203 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400204}
205
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200206static void mcasp_start_tx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400207{
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400208 u32 cnt;
209
Peter Ujfalusibb372af2014-10-29 13:55:47 +0200210 if (mcasp->txnumevt) { /* enable FIFO */
211 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
212
213 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
214 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
215 }
216
Peter Ujfalusi36bcecd2014-10-29 13:55:44 +0200217 /* Start clocks */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200218 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
219 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
Peter Ujfalusi36bcecd2014-10-29 13:55:44 +0200220 /* Activate serializer(s) */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200221 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400222
Peter Ujfalusi36bcecd2014-10-29 13:55:44 +0200223 /* wait for XDATA to be cleared */
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400224 cnt = 0;
Peter Ujfalusi36bcecd2014-10-29 13:55:44 +0200225 while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) &
226 ~XRDATA) && (cnt < 100000))
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400227 cnt++;
228
Peter Ujfalusi36bcecd2014-10-29 13:55:44 +0200229 /* Release TX state machine */
230 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
231 /* Release Frame Sync generator */
232 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
Misael Lopez Cruza7a33242014-11-12 16:38:05 +0200233
234 /* enable transmit IRQs */
235 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
236 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400237}
238
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200239static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400240{
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200241 mcasp->streams++;
242
Peter Ujfalusibb372af2014-10-29 13:55:47 +0200243 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200244 mcasp_start_tx(mcasp);
Peter Ujfalusibb372af2014-10-29 13:55:47 +0200245 else
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200246 mcasp_start_rx(mcasp);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400247}
248
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200249static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400250{
Misael Lopez Cruza7a33242014-11-12 16:38:05 +0200251 /* disable IRQ sources */
252 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
253 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
254
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200255 /*
256 * In synchronous mode stop the TX clocks if no other stream is
257 * running
258 */
259 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200260 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200261
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200262 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
263 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
Peter Ujfalusi03808662014-10-29 13:55:46 +0200264
265 if (mcasp->rxnumevt) { /* disable FIFO */
266 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
267
268 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
269 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400270}
271
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200272static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400273{
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200274 u32 val = 0;
275
Misael Lopez Cruza7a33242014-11-12 16:38:05 +0200276 /* disable IRQ sources */
277 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
278 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
279
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200280 /*
281 * In synchronous mode keep TX clocks running if the capture stream is
282 * still running.
283 */
284 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
285 val = TXHCLKRST | TXCLKRST | TXFSRST;
286
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200287 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
288 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
Peter Ujfalusi03808662014-10-29 13:55:46 +0200289
290 if (mcasp->txnumevt) { /* disable FIFO */
291 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
292
293 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
294 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400295}
296
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200297static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400298{
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200299 mcasp->streams--;
300
Peter Ujfalusi03808662014-10-29 13:55:46 +0200301 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200302 mcasp_stop_tx(mcasp);
Peter Ujfalusi03808662014-10-29 13:55:46 +0200303 else
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200304 mcasp_stop_rx(mcasp);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400305}
306
Misael Lopez Cruza7a33242014-11-12 16:38:05 +0200307static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
308{
309 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
310 struct snd_pcm_substream *substream;
311 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
312 u32 handled_mask = 0;
313 u32 stat;
314
315 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
316 if (stat & XUNDRN & irq_mask) {
317 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
318 handled_mask |= XUNDRN;
319
320 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
321 if (substream) {
322 snd_pcm_stream_lock_irq(substream);
323 if (snd_pcm_running(substream))
324 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
325 snd_pcm_stream_unlock_irq(substream);
326 }
327 }
328
329 if (!handled_mask)
330 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
331 stat);
332
333 if (stat & XRERR)
334 handled_mask |= XRERR;
335
336 /* Ack the handled event only */
337 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
338
339 return IRQ_RETVAL(handled_mask);
340}
341
342static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
343{
344 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
345 struct snd_pcm_substream *substream;
346 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
347 u32 handled_mask = 0;
348 u32 stat;
349
350 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
351 if (stat & ROVRN & irq_mask) {
352 dev_warn(mcasp->dev, "Receive buffer overflow\n");
353 handled_mask |= ROVRN;
354
355 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
356 if (substream) {
357 snd_pcm_stream_lock_irq(substream);
358 if (snd_pcm_running(substream))
359 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
360 snd_pcm_stream_unlock_irq(substream);
361 }
362 }
363
364 if (!handled_mask)
365 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
366 stat);
367
368 if (stat & XRERR)
369 handled_mask |= XRERR;
370
371 /* Ack the handled event only */
372 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
373
374 return IRQ_RETVAL(handled_mask);
375}
376
Peter Ujfalusi5a1b8a82014-12-30 16:10:32 +0200377static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
378{
379 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
380 irqreturn_t ret = IRQ_NONE;
381
382 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
383 ret = davinci_mcasp_tx_irq_handler(irq, data);
384
385 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
386 ret |= davinci_mcasp_rx_irq_handler(irq, data);
387
388 return ret;
389}
390
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400391static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
392 unsigned int fmt)
393{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200394 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200395 int ret = 0;
Peter Ujfalusi6dfa9a42014-04-04 14:31:42 +0300396 u32 data_delay;
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300397 bool fs_pol_rising;
Peter Ujfalusiffd950f2014-04-04 14:31:45 +0300398 bool inv_fs = false;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400399
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200400 pm_runtime_get_sync(mcasp->dev);
Daniel Mack5296cf22012-10-04 15:08:42 +0200401 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
Peter Ujfalusi188edc52014-04-04 14:31:43 +0300402 case SND_SOC_DAIFMT_DSP_A:
403 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
404 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
Peter Ujfalusi188edc52014-04-04 14:31:43 +0300405 /* 1st data bit occur one ACLK cycle after the frame sync */
406 data_delay = 1;
407 break;
Daniel Mack5296cf22012-10-04 15:08:42 +0200408 case SND_SOC_DAIFMT_DSP_B:
409 case SND_SOC_DAIFMT_AC97:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200410 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
411 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
Peter Ujfalusi6dfa9a42014-04-04 14:31:42 +0300412 /* No delay after FS */
413 data_delay = 0;
Daniel Mack5296cf22012-10-04 15:08:42 +0200414 break;
Peter Ujfalusiffd950f2014-04-04 14:31:45 +0300415 case SND_SOC_DAIFMT_I2S:
Daniel Mack5296cf22012-10-04 15:08:42 +0200416 /* configure a full-word SYNC pulse (LRCLK) */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200417 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
418 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
Peter Ujfalusi6dfa9a42014-04-04 14:31:42 +0300419 /* 1st data bit occur one ACLK cycle after the frame sync */
420 data_delay = 1;
Peter Ujfalusiffd950f2014-04-04 14:31:45 +0300421 /* FS need to be inverted */
422 inv_fs = true;
Daniel Mack5296cf22012-10-04 15:08:42 +0200423 break;
Peter Ujfalusi423761e2014-04-04 14:31:46 +0300424 case SND_SOC_DAIFMT_LEFT_J:
425 /* configure a full-word SYNC pulse (LRCLK) */
426 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
427 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
428 /* No delay after FS */
429 data_delay = 0;
430 break;
Peter Ujfalusiffd950f2014-04-04 14:31:45 +0300431 default:
432 ret = -EINVAL;
433 goto out;
Daniel Mack5296cf22012-10-04 15:08:42 +0200434 }
435
Peter Ujfalusi6dfa9a42014-04-04 14:31:42 +0300436 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
437 FSXDLY(3));
438 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
439 FSRDLY(3));
440
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400441 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
442 case SND_SOC_DAIFMT_CBS_CFS:
443 /* codec is clock and frame slave */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200444 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
445 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400446
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200447 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
448 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400449
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200450 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
451 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200452 mcasp->bclk_master = 1;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400453 break;
Peter Ujfalusi226e2f12015-02-12 16:41:26 +0200454 case SND_SOC_DAIFMT_CBS_CFM:
455 /* codec is clock slave and frame master */
456 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
457 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
458
459 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
460 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
461
462 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
463 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
464 mcasp->bclk_master = 1;
465 break;
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400466 case SND_SOC_DAIFMT_CBM_CFS:
467 /* codec is clock master and frame slave */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200468 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
469 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400470
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200471 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
472 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400473
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200474 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
475 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200476 mcasp->bclk_master = 0;
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400477 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400478 case SND_SOC_DAIFMT_CBM_CFM:
479 /* codec is clock and frame master */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200480 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
481 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400482
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200483 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
484 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400485
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200486 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
487 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200488 mcasp->bclk_master = 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400489 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400490 default:
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200491 ret = -EINVAL;
492 goto out;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400493 }
494
495 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
496 case SND_SOC_DAIFMT_IB_NF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200497 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
Peter Ujfalusi74ddd8c2014-04-04 14:31:41 +0300498 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300499 fs_pol_rising = true;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400500 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400501 case SND_SOC_DAIFMT_NB_IF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200502 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
Peter Ujfalusi74ddd8c2014-04-04 14:31:41 +0300503 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300504 fs_pol_rising = false;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400505 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400506 case SND_SOC_DAIFMT_IB_IF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200507 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
Peter Ujfalusi74ddd8c2014-04-04 14:31:41 +0300508 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300509 fs_pol_rising = false;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400510 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400511 case SND_SOC_DAIFMT_NB_NF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200512 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200513 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300514 fs_pol_rising = true;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400515 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400516 default:
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200517 ret = -EINVAL;
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300518 goto out;
519 }
520
Peter Ujfalusiffd950f2014-04-04 14:31:45 +0300521 if (inv_fs)
522 fs_pol_rising = !fs_pol_rising;
523
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300524 if (fs_pol_rising) {
525 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
526 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
527 } else {
528 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
529 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400530 }
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200531out:
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +0200532 pm_runtime_put(mcasp->dev);
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200533 return ret;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400534}
535
Jyri Sarha88135432014-08-06 16:47:16 +0300536static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
537 int div, bool explicit)
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200538{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200539 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200540
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +0200541 pm_runtime_get_sync(mcasp->dev);
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200542 switch (div_id) {
543 case 0: /* MCLK divider */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200544 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200545 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200546 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200547 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
548 break;
549
550 case 1: /* BCLK divider */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200551 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200552 ACLKXDIV(div - 1), ACLKXDIV_MASK);
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200553 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200554 ACLKRDIV(div - 1), ACLKRDIV_MASK);
Jyri Sarha88135432014-08-06 16:47:16 +0300555 if (explicit)
556 mcasp->bclk_div = div;
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200557 break;
558
Daniel Mack1b3bc062012-12-05 18:20:38 +0100559 case 2: /* BCLK/LRCLK ratio */
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200560 mcasp->bclk_lrclk_ratio = div;
Daniel Mack1b3bc062012-12-05 18:20:38 +0100561 break;
562
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200563 default:
564 return -EINVAL;
565 }
566
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +0200567 pm_runtime_put(mcasp->dev);
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200568 return 0;
569}
570
Jyri Sarha88135432014-08-06 16:47:16 +0300571static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
572 int div)
573{
574 return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1);
575}
576
Daniel Mack5b66aa22012-10-04 15:08:41 +0200577static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
578 unsigned int freq, int dir)
579{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200580 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200581
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +0200582 pm_runtime_get_sync(mcasp->dev);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200583 if (dir == SND_SOC_CLOCK_OUT) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200584 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
585 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
586 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200587 } else {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200588 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
589 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
590 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200591 }
592
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200593 mcasp->sysclk_freq = freq;
594
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +0200595 pm_runtime_put(mcasp->dev);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200596 return 0;
597}
598
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200599static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
Daniel Mackba764b32012-12-05 18:20:37 +0100600 int word_length)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400601{
Daniel Mackba764b32012-12-05 18:20:37 +0100602 u32 fmt;
Daniel Mack79671892013-05-16 15:25:01 +0200603 u32 tx_rotate = (word_length / 4) & 0x7;
Daniel Mackba764b32012-12-05 18:20:37 +0100604 u32 mask = (1ULL << word_length) - 1;
Peter Ujfalusife0a29e2014-09-04 10:52:53 +0300605 /*
606 * For captured data we should not rotate, inversion and masking is
607 * enoguh to get the data to the right position:
608 * Format data from bus after reverse (XRBUF)
609 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
610 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
611 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
612 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
613 */
614 u32 rx_rotate = 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400615
Daniel Mack1b3bc062012-12-05 18:20:38 +0100616 /*
617 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
618 * callback, take it into account here. That allows us to for example
619 * send 32 bits per channel to the codec, while only 16 of them carry
620 * audio payload.
Michal Bachratyd486fea2013-04-19 15:28:44 +0200621 * The clock ratio is given for a full period of data (for I2S format
622 * both left and right channels), so it has to be divided by number of
623 * tdm-slots (for I2S - divided by 2).
Daniel Mack1b3bc062012-12-05 18:20:38 +0100624 */
Peter Ujfalusid742b922014-11-10 12:32:19 +0200625 if (mcasp->bclk_lrclk_ratio) {
626 u32 slot_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
627
628 /*
629 * When we have more bclk then it is needed for the data, we
630 * need to use the rotation to move the received samples to have
631 * correct alignment.
632 */
633 rx_rotate = (slot_length - word_length) / 4;
634 word_length = slot_length;
635 }
Daniel Mack1b3bc062012-12-05 18:20:38 +0100636
Daniel Mackba764b32012-12-05 18:20:37 +0100637 /* mapping of the XSSZ bit-field as described in the datasheet */
638 fmt = (word_length >> 1) - 1;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400639
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200640 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200641 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
642 RXSSZ(0x0F));
643 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
644 TXSSZ(0x0F));
645 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
646 TXROT(7));
647 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
648 RXROT(7));
649 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
Yegor Yefremovf5023af2013-04-04 16:13:20 +0200650 }
651
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200652 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
Chaithrika U S0c31cf32009-09-15 18:13:29 -0400653
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400654 return 0;
655}
656
Peter Ujfalusi662ffae2014-01-30 15:15:22 +0200657static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300658 int period_words, int channels)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400659{
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300660 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400661 int i;
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400662 u8 tx_ser = 0;
663 u8 rx_ser = 0;
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200664 u8 slots = mcasp->tdm_slots;
Michal Bachraty2952b272013-02-28 16:07:08 +0100665 u8 max_active_serializers = (channels + slots - 1) / slots;
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300666 int active_serializers, numevt, n;
Peter Ujfalusi487dce82013-11-14 11:35:31 +0200667 u32 reg;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400668 /* Default configuration */
Peter Ujfalusi40448e52014-04-04 15:56:30 +0300669 if (mcasp->version < MCASP_VERSION_3)
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200670 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400671
672 /* All PINS as McASP */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200673 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400674
675 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200676 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
677 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400678 } else {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200679 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
680 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400681 }
682
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200683 for (i = 0; i < mcasp->num_serializer; i++) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200684 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
685 mcasp->serial_dir[i]);
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200686 if (mcasp->serial_dir[i] == TX_MODE &&
Michal Bachraty2952b272013-02-28 16:07:08 +0100687 tx_ser < max_active_serializers) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200688 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400689 tx_ser++;
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200690 } else if (mcasp->serial_dir[i] == RX_MODE &&
Michal Bachraty2952b272013-02-28 16:07:08 +0100691 rx_ser < max_active_serializers) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200692 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400693 rx_ser++;
Michal Bachraty2952b272013-02-28 16:07:08 +0100694 } else {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200695 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
696 SRMOD_INACTIVE, SRMOD_MASK);
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400697 }
698 }
699
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300700 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
701 active_serializers = tx_ser;
702 numevt = mcasp->txnumevt;
703 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
704 } else {
705 active_serializers = rx_ser;
706 numevt = mcasp->rxnumevt;
707 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
708 }
Daniel Mackecf327c2013-03-08 14:19:38 +0100709
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300710 if (active_serializers < max_active_serializers) {
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200711 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300712 "enabled in mcasp (%d)\n", channels,
713 active_serializers * slots);
Daniel Mackecf327c2013-03-08 14:19:38 +0100714 return -EINVAL;
715 }
716
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300717 /* AFIFO is not in use */
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300718 if (!numevt) {
719 /* Configure the burst size for platform drivers */
Peter Ujfalusi33445642014-04-01 15:55:12 +0300720 if (active_serializers > 1) {
721 /*
722 * If more than one serializers are in use we have one
723 * DMA request to provide data for all serializers.
724 * For example if three serializers are enabled the DMA
725 * need to transfer three words per DMA request.
726 */
Peter Ujfalusi33445642014-04-01 15:55:12 +0300727 dma_data->maxburst = active_serializers;
728 } else {
Peter Ujfalusi33445642014-04-01 15:55:12 +0300729 dma_data->maxburst = 0;
730 }
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300731 return 0;
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300732 }
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400733
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300734 if (period_words % active_serializers) {
735 dev_err(mcasp->dev, "Invalid combination of period words and "
736 "active serializers: %d, %d\n", period_words,
737 active_serializers);
738 return -EINVAL;
739 }
740
741 /*
742 * Calculate the optimal AFIFO depth for platform side:
743 * The number of words for numevt need to be in steps of active
744 * serializers.
745 */
746 n = numevt % active_serializers;
747 if (n)
748 numevt += (active_serializers - n);
749 while (period_words % numevt && numevt > 0)
750 numevt -= active_serializers;
751 if (numevt <= 0)
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300752 numevt = active_serializers;
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400753
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300754 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
755 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
Michal Bachraty2952b272013-02-28 16:07:08 +0100756
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300757 /* Configure the burst size for platform drivers */
Peter Ujfalusi33445642014-04-01 15:55:12 +0300758 if (numevt == 1)
759 numevt = 0;
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300760 dma_data->maxburst = numevt;
761
Michal Bachraty2952b272013-02-28 16:07:08 +0100762 return 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400763}
764
Misael Lopez Cruz18a4f552014-11-10 12:32:17 +0200765static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
766 int channels)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400767{
768 int i, active_slots;
Misael Lopez Cruz18a4f552014-11-10 12:32:17 +0200769 int total_slots;
770 int active_serializers;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400771 u32 mask = 0;
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +0200772 u32 busel = 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400773
Misael Lopez Cruz18a4f552014-11-10 12:32:17 +0200774 total_slots = mcasp->tdm_slots;
775
776 /*
777 * If more than one serializer is needed, then use them with
778 * their specified tdm_slots count. Otherwise, one serializer
779 * can cope with the transaction using as many slots as channels
780 * in the stream, requires channels symmetry
781 */
782 active_serializers = (channels + total_slots - 1) / total_slots;
783 if (active_serializers == 1)
784 active_slots = channels;
785 else
786 active_slots = total_slots;
787
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400788 for (i = 0; i < active_slots; i++)
789 mask |= (1 << i);
790
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200791 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400792
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +0200793 if (!mcasp->dat_port)
794 busel = TXSEL;
795
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200796 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
797 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
798 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
Misael Lopez Cruz18a4f552014-11-10 12:32:17 +0200799 FSXMOD(total_slots), FSXMOD(0x1FF));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400800
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200801 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
802 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
803 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
Misael Lopez Cruz18a4f552014-11-10 12:32:17 +0200804 FSRMOD(total_slots), FSRMOD(0x1FF));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400805
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200806 return 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400807}
808
809/* S/PDIF */
Daniel Mack64792852014-03-27 11:27:40 +0100810static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
811 unsigned int rate)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400812{
Daniel Mack64792852014-03-27 11:27:40 +0100813 u32 cs_value = 0;
814 u8 *cs_bytes = (u8*) &cs_value;
815
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400816 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
817 and LSB first */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200818 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400819
820 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200821 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400822
823 /* Set the TX tdm : for all the slots */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200824 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400825
826 /* Set the TX clock controls : div = 1 and internal */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200827 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400828
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200829 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400830
831 /* Only 44100 and 48000 are valid, both have the same setting */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200832 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400833
834 /* Enable the DIT */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200835 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200836
Daniel Mack64792852014-03-27 11:27:40 +0100837 /* Set S/PDIF channel status bits */
838 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
839 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
840
841 switch (rate) {
842 case 22050:
843 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
844 break;
845 case 24000:
846 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
847 break;
848 case 32000:
849 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
850 break;
851 case 44100:
852 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
853 break;
854 case 48000:
855 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
856 break;
857 case 88200:
858 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
859 break;
860 case 96000:
861 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
862 break;
863 case 176400:
864 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
865 break;
866 case 192000:
867 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
868 break;
869 default:
870 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
871 return -EINVAL;
872 }
873
874 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
875 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
876
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200877 return 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400878}
879
Jyri Sarhaa75a0532015-03-20 13:31:08 +0200880static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
881 unsigned int bclk_freq,
882 int *error_ppm)
883{
884 int div = mcasp->sysclk_freq / bclk_freq;
885 int rem = mcasp->sysclk_freq % bclk_freq;
886
887 if (rem != 0) {
888 if (div == 0 ||
889 ((mcasp->sysclk_freq / div) - bclk_freq) >
890 (bclk_freq - (mcasp->sysclk_freq / (div+1)))) {
891 div++;
892 rem = rem - bclk_freq;
893 }
894 }
895 if (error_ppm)
896 *error_ppm =
897 (div*1000000 + (int)div64_long(1000000LL*rem,
898 (int)bclk_freq))
899 /div - 1000000;
900
901 return div;
902}
903
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400904static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
905 struct snd_pcm_hw_params *params,
906 struct snd_soc_dai *cpu_dai)
907{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200908 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400909 int word_length;
Peter Ujfalusia7e46bd2014-02-03 14:51:50 +0200910 int channels = params_channels(params);
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300911 int period_size = params_period_size(params);
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200912 int ret;
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200913
Daniel Mack82675252014-07-16 14:04:41 +0200914 /*
915 * If mcasp is BCLK master, and a BCLK divider was not provided by
916 * the machine driver, we need to calculate the ratio.
917 */
918 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
Jyri Sarha1f114f72015-04-23 16:16:04 +0300919 int slots = mcasp->tdm_slots;
Jyri Sarhaa75a0532015-03-20 13:31:08 +0200920 int rate = params_rate(params);
921 int sbits = params_width(params);
922 int ppm, div;
923
Jyri Sarha1f114f72015-04-23 16:16:04 +0300924 div = davinci_mcasp_calc_clk_div(mcasp, rate*sbits*slots,
Jyri Sarhaa75a0532015-03-20 13:31:08 +0200925 &ppm);
926 if (ppm)
927 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
928 ppm);
929
Jyri Sarha88135432014-08-06 16:47:16 +0300930 __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0);
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200931 }
932
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300933 ret = mcasp_common_hw_param(mcasp, substream->stream,
934 period_size * channels, channels);
Peter Ujfalusi0f7d9a62014-01-30 15:15:24 +0200935 if (ret)
936 return ret;
937
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200938 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
Daniel Mack64792852014-03-27 11:27:40 +0100939 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400940 else
Misael Lopez Cruz18a4f552014-11-10 12:32:17 +0200941 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
942 channels);
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200943
944 if (ret)
945 return ret;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400946
947 switch (params_format(params)) {
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400948 case SNDRV_PCM_FORMAT_U8:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400949 case SNDRV_PCM_FORMAT_S8:
Daniel Mackba764b32012-12-05 18:20:37 +0100950 word_length = 8;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400951 break;
952
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400953 case SNDRV_PCM_FORMAT_U16_LE:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400954 case SNDRV_PCM_FORMAT_S16_LE:
Daniel Mackba764b32012-12-05 18:20:37 +0100955 word_length = 16;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400956 break;
957
Daniel Mack21eb24d2012-10-09 09:35:16 +0200958 case SNDRV_PCM_FORMAT_U24_3LE:
959 case SNDRV_PCM_FORMAT_S24_3LE:
Daniel Mackba764b32012-12-05 18:20:37 +0100960 word_length = 24;
Daniel Mack21eb24d2012-10-09 09:35:16 +0200961 break;
962
Daniel Mack6b7fa012012-10-09 11:56:40 +0200963 case SNDRV_PCM_FORMAT_U24_LE:
964 case SNDRV_PCM_FORMAT_S24_LE:
Peter Ujfalusi182bef82014-06-26 08:09:24 +0300965 word_length = 24;
966 break;
967
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400968 case SNDRV_PCM_FORMAT_U32_LE:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400969 case SNDRV_PCM_FORMAT_S32_LE:
Daniel Mackba764b32012-12-05 18:20:37 +0100970 word_length = 32;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400971 break;
972
973 default:
974 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
975 return -EINVAL;
976 }
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400977
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200978 davinci_config_channel_size(mcasp, word_length);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400979
Peter Ujfalusi11277832014-11-10 12:32:16 +0200980 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
981 mcasp->channels = channels;
982
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400983 return 0;
984}
985
986static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
987 int cmd, struct snd_soc_dai *cpu_dai)
988{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200989 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400990 int ret = 0;
991
992 switch (cmd) {
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400993 case SNDRV_PCM_TRIGGER_RESUME:
Chaithrika U Se473b842010-01-20 17:06:33 +0530994 case SNDRV_PCM_TRIGGER_START:
995 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200996 davinci_mcasp_start(mcasp, substream->stream);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400997 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400998 case SNDRV_PCM_TRIGGER_SUSPEND:
Chaithrika U Sa47979b2009-12-03 18:56:56 +0530999 case SNDRV_PCM_TRIGGER_STOP:
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001000 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001001 davinci_mcasp_stop(mcasp, substream->stream);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001002 break;
1003
1004 default:
1005 ret = -EINVAL;
1006 }
1007
1008 return ret;
1009}
1010
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001011static const unsigned int davinci_mcasp_dai_rates[] = {
1012 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1013 88200, 96000, 176400, 192000,
1014};
1015
1016#define DAVINCI_MAX_RATE_ERROR_PPM 1000
1017
1018static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1019 struct snd_pcm_hw_rule *rule)
1020{
1021 struct davinci_mcasp_ruledata *rd = rule->private;
1022 struct snd_interval *ri =
1023 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1024 int sbits = params_width(params);
Jyri Sarha1f114f72015-04-23 16:16:04 +03001025 int slots = rd->mcasp->tdm_slots;
Jyri Sarha518f6ba2015-04-23 16:16:06 +03001026 struct snd_interval range;
1027 int i;
1028
1029 snd_interval_any(&range);
1030 range.empty = 1;
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001031
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001032 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
Jyri Sarha518f6ba2015-04-23 16:16:06 +03001033 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
Jyri Sarha1f114f72015-04-23 16:16:04 +03001034 uint bclk_freq = sbits*slots*
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001035 davinci_mcasp_dai_rates[i];
1036 int ppm;
1037
1038 davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
Jyri Sarha518f6ba2015-04-23 16:16:06 +03001039 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1040 if (range.empty) {
1041 range.min = davinci_mcasp_dai_rates[i];
1042 range.empty = 0;
1043 }
1044 range.max = davinci_mcasp_dai_rates[i];
1045 }
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001046 }
1047 }
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001048
Jyri Sarha518f6ba2015-04-23 16:16:06 +03001049 dev_dbg(rd->mcasp->dev,
1050 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1051 ri->min, ri->max, range.min, range.max, sbits, slots);
1052
1053 return snd_interval_refine(hw_param_interval(params, rule->var),
1054 &range);
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001055}
1056
1057static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1058 struct snd_pcm_hw_rule *rule)
1059{
1060 struct davinci_mcasp_ruledata *rd = rule->private;
1061 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1062 struct snd_mask nfmt;
1063 int rate = params_rate(params);
Jyri Sarha1f114f72015-04-23 16:16:04 +03001064 int slots = rd->mcasp->tdm_slots;
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001065 int i, count = 0;
1066
1067 snd_mask_none(&nfmt);
1068
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001069 for (i = 0; i < SNDRV_PCM_FORMAT_LAST; i++) {
1070 if (snd_mask_test(fmt, i)) {
Jyri Sarha1f114f72015-04-23 16:16:04 +03001071 uint bclk_freq = snd_pcm_format_width(i)*slots*rate;
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001072 int ppm;
1073
1074 davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
1075 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1076 snd_mask_set(&nfmt, i);
1077 count++;
1078 }
1079 }
1080 }
1081 dev_dbg(rd->mcasp->dev,
Jyri Sarha1f114f72015-04-23 16:16:04 +03001082 "%d possible sample format for %d Hz and %d tdm slots\n",
1083 count, rate, slots);
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001084
1085 return snd_mask_refine(fmt, &nfmt);
1086}
1087
Peter Ujfalusi11277832014-11-10 12:32:16 +02001088static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1089 struct snd_soc_dai *cpu_dai)
1090{
1091 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
Peter Ujfalusi4cd9db02015-04-07 14:03:53 +03001092 struct davinci_mcasp_ruledata *ruledata =
1093 &mcasp->ruledata[substream->stream];
Peter Ujfalusi11277832014-11-10 12:32:16 +02001094 u32 max_channels = 0;
1095 int i, dir;
1096
Misael Lopez Cruza7a33242014-11-12 16:38:05 +02001097 mcasp->substreams[substream->stream] = substream;
1098
Peter Ujfalusi11277832014-11-10 12:32:16 +02001099 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1100 return 0;
1101
1102 /*
1103 * Limit the maximum allowed channels for the first stream:
1104 * number of serializers for the direction * tdm slots per serializer
1105 */
1106 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1107 dir = TX_MODE;
1108 else
1109 dir = RX_MODE;
1110
1111 for (i = 0; i < mcasp->num_serializer; i++) {
1112 if (mcasp->serial_dir[i] == dir)
1113 max_channels++;
1114 }
Peter Ujfalusi4cd9db02015-04-07 14:03:53 +03001115 ruledata->serializers = max_channels;
Peter Ujfalusi11277832014-11-10 12:32:16 +02001116 max_channels *= mcasp->tdm_slots;
1117 /*
1118 * If the already active stream has less channels than the calculated
1119 * limnit based on the seirializers * tdm_slots, we need to use that as
1120 * a constraint for the second stream.
1121 * Otherwise (first stream or less allowed channels) we use the
1122 * calculated constraint.
1123 */
1124 if (mcasp->channels && mcasp->channels < max_channels)
1125 max_channels = mcasp->channels;
1126
1127 snd_pcm_hw_constraint_minmax(substream->runtime,
1128 SNDRV_PCM_HW_PARAM_CHANNELS,
1129 2, max_channels);
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001130
Jyri Sarha5935a052015-04-23 16:16:05 +03001131 if (mcasp->chconstr[substream->stream].count)
1132 snd_pcm_hw_constraint_list(substream->runtime,
1133 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1134 &mcasp->chconstr[substream->stream]);
1135
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001136 /*
1137 * If we rely on implicit BCLK divider setting we should
1138 * set constraints based on what we can provide.
1139 */
1140 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1141 int ret;
1142
Peter Ujfalusi4cd9db02015-04-07 14:03:53 +03001143 ruledata->mcasp = mcasp;
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001144
1145 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1146 SNDRV_PCM_HW_PARAM_RATE,
1147 davinci_mcasp_hw_rule_rate,
Peter Ujfalusi4cd9db02015-04-07 14:03:53 +03001148 ruledata,
Jyri Sarha1f114f72015-04-23 16:16:04 +03001149 SNDRV_PCM_HW_PARAM_FORMAT, -1);
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001150 if (ret)
1151 return ret;
1152 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1153 SNDRV_PCM_HW_PARAM_FORMAT,
1154 davinci_mcasp_hw_rule_format,
Peter Ujfalusi4cd9db02015-04-07 14:03:53 +03001155 ruledata,
Jyri Sarha1f114f72015-04-23 16:16:04 +03001156 SNDRV_PCM_HW_PARAM_RATE, -1);
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001157 if (ret)
1158 return ret;
1159 }
1160
Peter Ujfalusi11277832014-11-10 12:32:16 +02001161 return 0;
1162}
1163
1164static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1165 struct snd_soc_dai *cpu_dai)
1166{
1167 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1168
Misael Lopez Cruza7a33242014-11-12 16:38:05 +02001169 mcasp->substreams[substream->stream] = NULL;
1170
Peter Ujfalusi11277832014-11-10 12:32:16 +02001171 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1172 return;
1173
1174 if (!cpu_dai->active)
1175 mcasp->channels = 0;
1176}
1177
Lars-Peter Clausen85e76522011-11-23 11:40:40 +01001178static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
Peter Ujfalusi11277832014-11-10 12:32:16 +02001179 .startup = davinci_mcasp_startup,
1180 .shutdown = davinci_mcasp_shutdown,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001181 .trigger = davinci_mcasp_trigger,
1182 .hw_params = davinci_mcasp_hw_params,
1183 .set_fmt = davinci_mcasp_set_dai_fmt,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +02001184 .set_clkdiv = davinci_mcasp_set_clkdiv,
Daniel Mack5b66aa22012-10-04 15:08:41 +02001185 .set_sysclk = davinci_mcasp_set_sysclk,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001186};
1187
Peter Ujfalusid5902f62014-04-01 15:55:07 +03001188static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1189{
1190 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1191
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001192 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1193 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
Peter Ujfalusid5902f62014-04-01 15:55:07 +03001194
1195 return 0;
1196}
1197
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001198#ifdef CONFIG_PM_SLEEP
1199static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1200{
1201 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
Peter Ujfalusi790bb942014-02-03 14:51:52 +02001202 struct davinci_mcasp_context *context = &mcasp->context;
Peter Ujfalusif114ce62014-10-01 16:02:12 +03001203 u32 reg;
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +03001204 int i;
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001205
Peter Ujfalusi66e61882015-03-06 09:07:32 +02001206 context->pm_state = pm_runtime_enabled(mcasp->dev);
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +02001207 if (!context->pm_state)
1208 pm_runtime_get_sync(mcasp->dev);
1209
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +03001210 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1211 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001212
Peter Ujfalusif114ce62014-10-01 16:02:12 +03001213 if (mcasp->txnumevt) {
1214 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1215 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1216 }
1217 if (mcasp->rxnumevt) {
1218 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1219 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1220 }
1221
1222 for (i = 0; i < mcasp->num_serializer; i++)
1223 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1224 DAVINCI_MCASP_XRSRCTL_REG(i));
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001225
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +02001226 pm_runtime_put_sync(mcasp->dev);
1227
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001228 return 0;
1229}
1230
1231static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1232{
1233 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
Peter Ujfalusi790bb942014-02-03 14:51:52 +02001234 struct davinci_mcasp_context *context = &mcasp->context;
Peter Ujfalusif114ce62014-10-01 16:02:12 +03001235 u32 reg;
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +03001236 int i;
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001237
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +02001238 pm_runtime_get_sync(mcasp->dev);
1239
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +03001240 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1241 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001242
Peter Ujfalusif114ce62014-10-01 16:02:12 +03001243 if (mcasp->txnumevt) {
1244 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1245 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1246 }
1247 if (mcasp->rxnumevt) {
1248 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1249 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1250 }
1251
1252 for (i = 0; i < mcasp->num_serializer; i++)
1253 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1254 context->xrsr_regs[i]);
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001255
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +02001256 if (!context->pm_state)
1257 pm_runtime_put_sync(mcasp->dev);
1258
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001259 return 0;
1260}
1261#else
1262#define davinci_mcasp_suspend NULL
1263#define davinci_mcasp_resume NULL
1264#endif
1265
Peter Ujfalusied29cd52013-11-14 11:35:22 +02001266#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1267
Ben Gardiner0a9d1382011-08-26 12:02:44 -04001268#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1269 SNDRV_PCM_FMTBIT_U8 | \
1270 SNDRV_PCM_FMTBIT_S16_LE | \
1271 SNDRV_PCM_FMTBIT_U16_LE | \
Daniel Mack21eb24d2012-10-09 09:35:16 +02001272 SNDRV_PCM_FMTBIT_S24_LE | \
1273 SNDRV_PCM_FMTBIT_U24_LE | \
1274 SNDRV_PCM_FMTBIT_S24_3LE | \
1275 SNDRV_PCM_FMTBIT_U24_3LE | \
Ben Gardiner0a9d1382011-08-26 12:02:44 -04001276 SNDRV_PCM_FMTBIT_S32_LE | \
1277 SNDRV_PCM_FMTBIT_U32_LE)
1278
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +00001279static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001280 {
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +00001281 .name = "davinci-mcasp.0",
Peter Ujfalusid5902f62014-04-01 15:55:07 +03001282 .probe = davinci_mcasp_dai_probe,
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001283 .suspend = davinci_mcasp_suspend,
1284 .resume = davinci_mcasp_resume,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001285 .playback = {
1286 .channels_min = 2,
Michal Bachraty2952b272013-02-28 16:07:08 +01001287 .channels_max = 32 * 16,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001288 .rates = DAVINCI_MCASP_RATES,
Ben Gardiner0a9d1382011-08-26 12:02:44 -04001289 .formats = DAVINCI_MCASP_PCM_FMTS,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001290 },
1291 .capture = {
1292 .channels_min = 2,
Michal Bachraty2952b272013-02-28 16:07:08 +01001293 .channels_max = 32 * 16,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001294 .rates = DAVINCI_MCASP_RATES,
Ben Gardiner0a9d1382011-08-26 12:02:44 -04001295 .formats = DAVINCI_MCASP_PCM_FMTS,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001296 },
1297 .ops = &davinci_mcasp_dai_ops,
1298
Peter Ujfalusid75249f2014-11-10 12:32:18 +02001299 .symmetric_samplebits = 1,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001300 },
1301 {
Peter Ujfalusi58e48d92013-11-14 11:35:24 +02001302 .name = "davinci-mcasp.1",
Peter Ujfalusid5902f62014-04-01 15:55:07 +03001303 .probe = davinci_mcasp_dai_probe,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001304 .playback = {
1305 .channels_min = 1,
1306 .channels_max = 384,
1307 .rates = DAVINCI_MCASP_RATES,
Ben Gardiner0a9d1382011-08-26 12:02:44 -04001308 .formats = DAVINCI_MCASP_PCM_FMTS,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001309 },
1310 .ops = &davinci_mcasp_dai_ops,
1311 },
1312
1313};
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001314
Kuninori Morimotoeeef0ed2013-03-21 03:31:19 -07001315static const struct snd_soc_component_driver davinci_mcasp_component = {
1316 .name = "davinci-mcasp",
1317};
1318
Jyri Sarha256ba182013-10-18 18:37:42 +03001319/* Some HW specific values and defaults. The rest is filled in from DT. */
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001320static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
Jyri Sarha256ba182013-10-18 18:37:42 +03001321 .tx_dma_offset = 0x400,
1322 .rx_dma_offset = 0x400,
Jyri Sarha256ba182013-10-18 18:37:42 +03001323 .version = MCASP_VERSION_1,
1324};
1325
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001326static struct davinci_mcasp_pdata da830_mcasp_pdata = {
Jyri Sarha256ba182013-10-18 18:37:42 +03001327 .tx_dma_offset = 0x2000,
1328 .rx_dma_offset = 0x2000,
Jyri Sarha256ba182013-10-18 18:37:42 +03001329 .version = MCASP_VERSION_2,
1330};
1331
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001332static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
Jyri Sarha256ba182013-10-18 18:37:42 +03001333 .tx_dma_offset = 0,
1334 .rx_dma_offset = 0,
Jyri Sarha256ba182013-10-18 18:37:42 +03001335 .version = MCASP_VERSION_3,
1336};
1337
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001338static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001339 .tx_dma_offset = 0x200,
1340 .rx_dma_offset = 0x284,
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001341 .version = MCASP_VERSION_4,
1342};
1343
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301344static const struct of_device_id mcasp_dt_ids[] = {
1345 {
1346 .compatible = "ti,dm646x-mcasp-audio",
Jyri Sarha256ba182013-10-18 18:37:42 +03001347 .data = &dm646x_mcasp_pdata,
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301348 },
1349 {
1350 .compatible = "ti,da830-mcasp-audio",
Jyri Sarha256ba182013-10-18 18:37:42 +03001351 .data = &da830_mcasp_pdata,
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301352 },
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +05301353 {
Jyri Sarha3af9e032013-10-18 18:37:44 +03001354 .compatible = "ti,am33xx-mcasp-audio",
Peter Ujfalusib14899d2013-11-14 11:35:37 +02001355 .data = &am33xx_mcasp_pdata,
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +05301356 },
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001357 {
1358 .compatible = "ti,dra7-mcasp-audio",
1359 .data = &dra7_mcasp_pdata,
1360 },
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301361 { /* sentinel */ }
1362};
1363MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1364
Peter Ujfalusiae726e92013-11-14 11:35:35 +02001365static int mcasp_reparent_fck(struct platform_device *pdev)
1366{
1367 struct device_node *node = pdev->dev.of_node;
1368 struct clk *gfclk, *parent_clk;
1369 const char *parent_name;
1370 int ret;
1371
1372 if (!node)
1373 return 0;
1374
1375 parent_name = of_get_property(node, "fck_parent", NULL);
1376 if (!parent_name)
1377 return 0;
1378
1379 gfclk = clk_get(&pdev->dev, "fck");
1380 if (IS_ERR(gfclk)) {
1381 dev_err(&pdev->dev, "failed to get fck\n");
1382 return PTR_ERR(gfclk);
1383 }
1384
1385 parent_clk = clk_get(NULL, parent_name);
1386 if (IS_ERR(parent_clk)) {
1387 dev_err(&pdev->dev, "failed to get parent clock\n");
1388 ret = PTR_ERR(parent_clk);
1389 goto err1;
1390 }
1391
1392 ret = clk_set_parent(gfclk, parent_clk);
1393 if (ret) {
1394 dev_err(&pdev->dev, "failed to reparent fck\n");
1395 goto err2;
1396 }
1397
1398err2:
1399 clk_put(parent_clk);
1400err1:
1401 clk_put(gfclk);
1402 return ret;
1403}
1404
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001405static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301406 struct platform_device *pdev)
1407{
1408 struct device_node *np = pdev->dev.of_node;
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001409 struct davinci_mcasp_pdata *pdata = NULL;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301410 const struct of_device_id *match =
Sachin Kamatea421eb2013-05-22 16:53:37 +05301411 of_match_device(mcasp_dt_ids, &pdev->dev);
Jyri Sarha4023fe62013-10-18 18:37:43 +03001412 struct of_phandle_args dma_spec;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301413
1414 const u32 *of_serial_dir32;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301415 u32 val;
1416 int i, ret = 0;
1417
1418 if (pdev->dev.platform_data) {
1419 pdata = pdev->dev.platform_data;
1420 return pdata;
1421 } else if (match) {
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001422 pdata = (struct davinci_mcasp_pdata*) match->data;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301423 } else {
1424 /* control shouldn't reach here. something is wrong */
1425 ret = -EINVAL;
1426 goto nodata;
1427 }
1428
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301429 ret = of_property_read_u32(np, "op-mode", &val);
1430 if (ret >= 0)
1431 pdata->op_mode = val;
1432
1433 ret = of_property_read_u32(np, "tdm-slots", &val);
Michal Bachraty2952b272013-02-28 16:07:08 +01001434 if (ret >= 0) {
1435 if (val < 2 || val > 32) {
1436 dev_err(&pdev->dev,
1437 "tdm-slots must be in rage [2-32]\n");
1438 ret = -EINVAL;
1439 goto nodata;
1440 }
1441
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301442 pdata->tdm_slots = val;
Michal Bachraty2952b272013-02-28 16:07:08 +01001443 }
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301444
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301445 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1446 val /= sizeof(u32);
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301447 if (of_serial_dir32) {
Peter Ujfalusi1427e662013-10-18 18:37:46 +03001448 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1449 (sizeof(*of_serial_dir) * val),
1450 GFP_KERNEL);
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301451 if (!of_serial_dir) {
1452 ret = -ENOMEM;
1453 goto nodata;
1454 }
1455
Peter Ujfalusi1427e662013-10-18 18:37:46 +03001456 for (i = 0; i < val; i++)
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301457 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1458
Peter Ujfalusi1427e662013-10-18 18:37:46 +03001459 pdata->num_serializer = val;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301460 pdata->serial_dir = of_serial_dir;
1461 }
1462
Jyri Sarha4023fe62013-10-18 18:37:43 +03001463 ret = of_property_match_string(np, "dma-names", "tx");
1464 if (ret < 0)
1465 goto nodata;
1466
1467 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1468 &dma_spec);
1469 if (ret < 0)
1470 goto nodata;
1471
1472 pdata->tx_dma_channel = dma_spec.args[0];
1473
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001474 /* RX is not valid in DIT mode */
1475 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1476 ret = of_property_match_string(np, "dma-names", "rx");
1477 if (ret < 0)
1478 goto nodata;
Jyri Sarha4023fe62013-10-18 18:37:43 +03001479
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001480 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1481 &dma_spec);
1482 if (ret < 0)
1483 goto nodata;
Jyri Sarha4023fe62013-10-18 18:37:43 +03001484
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001485 pdata->rx_dma_channel = dma_spec.args[0];
1486 }
Jyri Sarha4023fe62013-10-18 18:37:43 +03001487
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301488 ret = of_property_read_u32(np, "tx-num-evt", &val);
1489 if (ret >= 0)
1490 pdata->txnumevt = val;
1491
1492 ret = of_property_read_u32(np, "rx-num-evt", &val);
1493 if (ret >= 0)
1494 pdata->rxnumevt = val;
1495
1496 ret = of_property_read_u32(np, "sram-size-playback", &val);
1497 if (ret >= 0)
1498 pdata->sram_size_playback = val;
1499
1500 ret = of_property_read_u32(np, "sram-size-capture", &val);
1501 if (ret >= 0)
1502 pdata->sram_size_capture = val;
1503
1504 return pdata;
1505
1506nodata:
1507 if (ret < 0) {
1508 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1509 ret);
1510 pdata = NULL;
1511 }
1512 return pdata;
1513}
1514
Jyri Sarha5935a052015-04-23 16:16:05 +03001515/* All serializers must have equal number of channels */
1516static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp,
1517 struct snd_pcm_hw_constraint_list *cl,
1518 int serializers)
1519{
1520 unsigned int *list;
1521 int i, count = 0;
1522
1523 if (serializers <= 1)
1524 return 0;
1525
1526 list = devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
1527 (mcasp->tdm_slots + serializers - 2),
1528 GFP_KERNEL);
1529 if (!list)
1530 return -ENOMEM;
1531
1532 for (i = 2; i <= mcasp->tdm_slots; i++)
1533 list[count++] = i;
1534
1535 for (i = 2; i <= serializers; i++)
1536 list[count++] = i*mcasp->tdm_slots;
1537
1538 cl->count = count;
1539 cl->list = list;
1540
1541 return 0;
1542}
1543
1544
1545static int davinci_mcasp_init_ch_constraints(struct davinci_mcasp *mcasp)
1546{
1547 int rx_serializers = 0, tx_serializers = 0, ret, i;
1548
1549 for (i = 0; i < mcasp->num_serializer; i++)
1550 if (mcasp->serial_dir[i] == TX_MODE)
1551 tx_serializers++;
1552 else if (mcasp->serial_dir[i] == RX_MODE)
1553 rx_serializers++;
1554
1555 ret = davinci_mcasp_ch_constraint(mcasp, &mcasp->chconstr[
1556 SNDRV_PCM_STREAM_PLAYBACK],
1557 tx_serializers);
1558 if (ret)
1559 return ret;
1560
1561 ret = davinci_mcasp_ch_constraint(mcasp, &mcasp->chconstr[
1562 SNDRV_PCM_STREAM_CAPTURE],
1563 rx_serializers);
1564
1565 return ret;
1566}
1567
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001568static int davinci_mcasp_probe(struct platform_device *pdev)
1569{
Peter Ujfalusi8de131f2014-03-14 16:42:46 +02001570 struct snd_dmaengine_dai_dma_data *dma_data;
Jyri Sarha256ba182013-10-18 18:37:42 +03001571 struct resource *mem, *ioarea, *res, *dat;
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001572 struct davinci_mcasp_pdata *pdata;
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001573 struct davinci_mcasp *mcasp;
Misael Lopez Cruza7a33242014-11-12 16:38:05 +02001574 char *irq_name;
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001575 int *dma;
Misael Lopez Cruza7a33242014-11-12 16:38:05 +02001576 int irq;
Julia Lawall96d31e22011-12-29 17:51:21 +01001577 int ret;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001578
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301579 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1580 dev_err(&pdev->dev, "No platform data supplied\n");
1581 return -EINVAL;
1582 }
1583
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001584 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
Julia Lawall96d31e22011-12-29 17:51:21 +01001585 GFP_KERNEL);
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001586 if (!mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001587 return -ENOMEM;
1588
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301589 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1590 if (!pdata) {
1591 dev_err(&pdev->dev, "no platform data\n");
1592 return -EINVAL;
1593 }
1594
Jyri Sarha256ba182013-10-18 18:37:42 +03001595 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001596 if (!mem) {
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001597 dev_warn(mcasp->dev,
Jyri Sarha256ba182013-10-18 18:37:42 +03001598 "\"mpu\" mem resource not found, using index 0\n");
1599 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1600 if (!mem) {
1601 dev_err(&pdev->dev, "no mem resource?\n");
1602 return -ENODEV;
1603 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001604 }
1605
Julia Lawall96d31e22011-12-29 17:51:21 +01001606 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
Vaibhav Bediad852f4462011-02-09 18:39:52 +05301607 resource_size(mem), pdev->name);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001608 if (!ioarea) {
1609 dev_err(&pdev->dev, "Audio region already claimed\n");
Julia Lawall96d31e22011-12-29 17:51:21 +01001610 return -EBUSY;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001611 }
1612
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301613 pm_runtime_enable(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001614
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001615 mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1616 if (!mcasp->base) {
Vaibhav Bedia4f82f022011-02-09 18:39:54 +05301617 dev_err(&pdev->dev, "ioremap failed\n");
1618 ret = -ENOMEM;
Peter Ujfalusib6bb3702014-04-22 14:03:13 +03001619 goto err;
Vaibhav Bedia4f82f022011-02-09 18:39:54 +05301620 }
1621
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001622 mcasp->op_mode = pdata->op_mode;
Peter Ujfalusi1a5923d2014-11-10 12:32:15 +02001623 /* sanity check for tdm slots parameter */
1624 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1625 if (pdata->tdm_slots < 2) {
1626 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1627 pdata->tdm_slots);
1628 mcasp->tdm_slots = 2;
1629 } else if (pdata->tdm_slots > 32) {
1630 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1631 pdata->tdm_slots);
1632 mcasp->tdm_slots = 32;
1633 } else {
1634 mcasp->tdm_slots = pdata->tdm_slots;
1635 }
1636 }
1637
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001638 mcasp->num_serializer = pdata->num_serializer;
Peter Ujfalusif114ce62014-10-01 16:02:12 +03001639#ifdef CONFIG_PM_SLEEP
1640 mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev,
1641 sizeof(u32) * mcasp->num_serializer,
1642 GFP_KERNEL);
1643#endif
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001644 mcasp->serial_dir = pdata->serial_dir;
1645 mcasp->version = pdata->version;
1646 mcasp->txnumevt = pdata->txnumevt;
1647 mcasp->rxnumevt = pdata->rxnumevt;
Peter Ujfalusi487dce82013-11-14 11:35:31 +02001648
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001649 mcasp->dev = &pdev->dev;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001650
Peter Ujfalusi5a1b8a82014-12-30 16:10:32 +02001651 irq = platform_get_irq_byname(pdev, "common");
1652 if (irq >= 0) {
1653 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common\n",
1654 dev_name(&pdev->dev));
1655 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1656 davinci_mcasp_common_irq_handler,
Peter Ujfalusi8f511ff2015-02-02 14:38:32 +02001657 IRQF_ONESHOT | IRQF_SHARED,
1658 irq_name, mcasp);
Peter Ujfalusi5a1b8a82014-12-30 16:10:32 +02001659 if (ret) {
1660 dev_err(&pdev->dev, "common IRQ request failed\n");
1661 goto err;
1662 }
1663
1664 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1665 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1666 }
1667
Misael Lopez Cruza7a33242014-11-12 16:38:05 +02001668 irq = platform_get_irq_byname(pdev, "rx");
1669 if (irq >= 0) {
1670 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx\n",
1671 dev_name(&pdev->dev));
1672 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1673 davinci_mcasp_rx_irq_handler,
1674 IRQF_ONESHOT, irq_name, mcasp);
1675 if (ret) {
1676 dev_err(&pdev->dev, "RX IRQ request failed\n");
1677 goto err;
1678 }
1679
1680 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1681 }
1682
1683 irq = platform_get_irq_byname(pdev, "tx");
1684 if (irq >= 0) {
1685 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx\n",
1686 dev_name(&pdev->dev));
1687 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1688 davinci_mcasp_tx_irq_handler,
1689 IRQF_ONESHOT, irq_name, mcasp);
1690 if (ret) {
1691 dev_err(&pdev->dev, "TX IRQ request failed\n");
1692 goto err;
1693 }
1694
1695 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1696 }
1697
Jyri Sarha256ba182013-10-18 18:37:42 +03001698 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001699 if (dat)
1700 mcasp->dat_port = true;
Jyri Sarha256ba182013-10-18 18:37:42 +03001701
Peter Ujfalusi8de131f2014-03-14 16:42:46 +02001702 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001703 if (dat)
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001704 dma_data->addr = dat->start;
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001705 else
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001706 dma_data->addr = mem->start + pdata->tx_dma_offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001707
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001708 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001709 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
Jyri Sarha4023fe62013-10-18 18:37:43 +03001710 if (res)
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001711 *dma = res->start;
Jyri Sarha4023fe62013-10-18 18:37:43 +03001712 else
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001713 *dma = pdata->tx_dma_channel;
Troy Kisky92e2a6f2009-09-11 14:29:03 -07001714
Peter Ujfalusi8de131f2014-03-14 16:42:46 +02001715 /* dmaengine filter data for DT and non-DT boot */
1716 if (pdev->dev.of_node)
1717 dma_data->filter_data = "tx";
1718 else
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001719 dma_data->filter_data = dma;
Peter Ujfalusi8de131f2014-03-14 16:42:46 +02001720
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001721 /* RX is not valid in DIT mode */
1722 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001723 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001724 if (dat)
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001725 dma_data->addr = dat->start;
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001726 else
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001727 dma_data->addr = mem->start + pdata->rx_dma_offset;
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001728
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001729 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001730 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1731 if (res)
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001732 *dma = res->start;
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001733 else
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001734 *dma = pdata->rx_dma_channel;
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001735
1736 /* dmaengine filter data for DT and non-DT boot */
1737 if (pdev->dev.of_node)
1738 dma_data->filter_data = "rx";
1739 else
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001740 dma_data->filter_data = dma;
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001741 }
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001742
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001743 if (mcasp->version < MCASP_VERSION_3) {
1744 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
Peter Ujfalusi64ebdec2014-03-07 15:03:55 +02001745 /* dma_params->dma_addr is pointing to the data port address */
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001746 mcasp->dat_port = true;
1747 } else {
1748 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1749 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001750
Jyri Sarha5935a052015-04-23 16:16:05 +03001751 ret = davinci_mcasp_init_ch_constraints(mcasp);
1752 if (ret)
1753 goto err;
1754
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001755 dev_set_drvdata(&pdev->dev, mcasp);
Peter Ujfalusiae726e92013-11-14 11:35:35 +02001756
1757 mcasp_reparent_fck(pdev);
1758
Peter Ujfalusib6bb3702014-04-22 14:03:13 +03001759 ret = devm_snd_soc_register_component(&pdev->dev,
1760 &davinci_mcasp_component,
1761 &davinci_mcasp_dai[pdata->op_mode], 1);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001762
1763 if (ret != 0)
Peter Ujfalusib6bb3702014-04-22 14:03:13 +03001764 goto err;
Hebbar, Gururajaf08095a2012-08-27 18:56:39 +05301765
Peter Ujfalusid5c6c592014-04-16 15:46:20 +03001766 switch (mcasp->version) {
Peter Ujfalusif3f9cfa2014-07-16 15:12:04 +03001767#if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
1768 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1769 IS_MODULE(CONFIG_SND_EDMA_SOC))
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001770 case MCASP_VERSION_1:
1771 case MCASP_VERSION_2:
Peter Ujfalusif3f9cfa2014-07-16 15:12:04 +03001772 case MCASP_VERSION_3:
1773 ret = edma_pcm_platform_register(&pdev->dev);
1774 break;
1775#endif
Jyri Sarha7f28f352014-06-13 12:49:59 +03001776#if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
1777 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1778 IS_MODULE(CONFIG_SND_OMAP_SOC))
Peter Ujfalusid5c6c592014-04-16 15:46:20 +03001779 case MCASP_VERSION_4:
1780 ret = omap_pcm_platform_register(&pdev->dev);
1781 break;
Jyri Sarha7f28f352014-06-13 12:49:59 +03001782#endif
Peter Ujfalusid5c6c592014-04-16 15:46:20 +03001783 default:
1784 dev_err(&pdev->dev, "Invalid McASP version: %d\n",
1785 mcasp->version);
1786 ret = -EINVAL;
1787 break;
1788 }
1789
1790 if (ret) {
1791 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
Peter Ujfalusib6bb3702014-04-22 14:03:13 +03001792 goto err;
Hebbar, Gururajaf08095a2012-08-27 18:56:39 +05301793 }
1794
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001795 return 0;
1796
Peter Ujfalusib6bb3702014-04-22 14:03:13 +03001797err:
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301798 pm_runtime_disable(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001799 return ret;
1800}
1801
1802static int davinci_mcasp_remove(struct platform_device *pdev)
1803{
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301804 pm_runtime_disable(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001805
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001806 return 0;
1807}
1808
1809static struct platform_driver davinci_mcasp_driver = {
1810 .probe = davinci_mcasp_probe,
1811 .remove = davinci_mcasp_remove,
1812 .driver = {
1813 .name = "davinci-mcasp",
Sachin Kamatea421eb2013-05-22 16:53:37 +05301814 .of_match_table = mcasp_dt_ids,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001815 },
1816};
1817
Axel Linf9b8a512011-11-25 10:09:27 +08001818module_platform_driver(davinci_mcasp_driver);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001819
1820MODULE_AUTHOR("Steve Chen");
1821MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1822MODULE_LICENSE("GPL");