blob: bbe48917dcada768c5399f7db410480640a87c32 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Jiri Pirko22a67762017-02-03 10:29:07 +01003 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +020056#include <linux/netlink.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020057#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020058#include <net/pkt_cls.h>
59#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020060#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010061#include <net/tc_act/tc_sample.h>
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +020062#include <net/addrconf.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020063
64#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020065#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020066#include "core.h"
67#include "reg.h"
68#include "port.h"
69#include "trap.h"
70#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010071#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020072#include "spectrum_dpipe.h"
Yotam Gigid3b939b2017-09-19 10:00:09 +020073#include "spectrum_acl_flex_actions.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020074#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020075
Yotam Gigi6b742192017-05-23 21:56:29 +020076#define MLXSW_FWREV_MAJOR 13
Shalom Toledo2f53fbd2017-11-12 09:01:24 +010077#define MLXSW_FWREV_MINOR 1530
78#define MLXSW_FWREV_SUBMINOR 152
Yotam Gigi6b742192017-05-23 21:56:29 +020079
80static const struct mlxsw_fw_rev mlxsw_sp_supported_fw_rev = {
81 .major = MLXSW_FWREV_MAJOR,
82 .minor = MLXSW_FWREV_MINOR,
83 .subminor = MLXSW_FWREV_SUBMINOR
84};
85
86#define MLXSW_SP_FW_FILENAME \
Yotam Gigia4e1ce22017-06-04 16:49:58 +020087 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
Yotam Gigi6b742192017-05-23 21:56:29 +020088 "." __stringify(MLXSW_FWREV_MINOR) \
89 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
90
Jiri Pirko56ade8f2015-10-16 14:01:37 +020091static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
92static const char mlxsw_sp_driver_version[] = "1.0";
93
94/* tx_hdr_version
95 * Tx header version.
96 * Must be set to 1.
97 */
98MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
99
100/* tx_hdr_ctl
101 * Packet control type.
102 * 0 - Ethernet control (e.g. EMADs, LACP)
103 * 1 - Ethernet data
104 */
105MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
106
107/* tx_hdr_proto
108 * Packet protocol type. Must be set to 1 (Ethernet).
109 */
110MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
111
112/* tx_hdr_rx_is_router
113 * Packet is sent from the router. Valid for data packets only.
114 */
115MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
116
117/* tx_hdr_fid_valid
118 * Indicates if the 'fid' field is valid and should be used for
119 * forwarding lookup. Valid for data packets only.
120 */
121MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
122
123/* tx_hdr_swid
124 * Switch partition ID. Must be set to 0.
125 */
126MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
127
128/* tx_hdr_control_tclass
129 * Indicates if the packet should use the control TClass and not one
130 * of the data TClasses.
131 */
132MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
133
134/* tx_hdr_etclass
135 * Egress TClass to be used on the egress device on the egress port.
136 */
137MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
138
139/* tx_hdr_port_mid
140 * Destination local port for unicast packets.
141 * Destination multicast ID for multicast packets.
142 *
143 * Control packets are directed to a specific egress port, while data
144 * packets are transmitted through the CPU port (0) into the switch partition,
145 * where forwarding rules are applied.
146 */
147MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
148
149/* tx_hdr_fid
150 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
151 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
152 * Valid for data packets only.
153 */
154MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
155
156/* tx_hdr_type
157 * 0 - Data packets
158 * 6 - Control packets
159 */
160MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
161
Yotam Gigie5e5c882017-05-23 21:56:27 +0200162struct mlxsw_sp_mlxfw_dev {
163 struct mlxfw_dev mlxfw_dev;
164 struct mlxsw_sp *mlxsw_sp;
165};
166
167static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
168 u16 component_index, u32 *p_max_size,
169 u8 *p_align_bits, u16 *p_max_write_size)
170{
171 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
172 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
173 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
174 char mcqi_pl[MLXSW_REG_MCQI_LEN];
175 int err;
176
177 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
178 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
179 if (err)
180 return err;
181 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
182 p_max_write_size);
183
184 *p_align_bits = max_t(u8, *p_align_bits, 2);
185 *p_max_write_size = min_t(u16, *p_max_write_size,
186 MLXSW_REG_MCDA_MAX_DATA_LEN);
187 return 0;
188}
189
190static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
191{
192 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
193 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
194 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
195 char mcc_pl[MLXSW_REG_MCC_LEN];
196 u8 control_state;
197 int err;
198
199 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
200 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
201 if (err)
202 return err;
203
204 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
205 if (control_state != MLXFW_FSM_STATE_IDLE)
206 return -EBUSY;
207
208 mlxsw_reg_mcc_pack(mcc_pl,
209 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
210 0, *fwhandle, 0);
211 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
212}
213
214static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
215 u32 fwhandle, u16 component_index,
216 u32 component_size)
217{
218 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
219 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
220 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
221 char mcc_pl[MLXSW_REG_MCC_LEN];
222
223 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
224 component_index, fwhandle, component_size);
225 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
226}
227
228static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
229 u32 fwhandle, u8 *data, u16 size,
230 u32 offset)
231{
232 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
233 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
234 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
235 char mcda_pl[MLXSW_REG_MCDA_LEN];
236
237 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
238 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
239}
240
241static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
242 u32 fwhandle, u16 component_index)
243{
244 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
245 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
246 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
247 char mcc_pl[MLXSW_REG_MCC_LEN];
248
249 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
250 component_index, fwhandle, 0);
251 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
252}
253
254static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
255{
256 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
257 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
258 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
259 char mcc_pl[MLXSW_REG_MCC_LEN];
260
261 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
262 fwhandle, 0);
263 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
264}
265
266static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
267 enum mlxfw_fsm_state *fsm_state,
268 enum mlxfw_fsm_state_err *fsm_state_err)
269{
270 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
271 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
272 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
273 char mcc_pl[MLXSW_REG_MCC_LEN];
274 u8 control_state;
275 u8 error_code;
276 int err;
277
278 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
279 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
280 if (err)
281 return err;
282
283 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
284 *fsm_state = control_state;
285 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
286 MLXFW_FSM_STATE_ERR_MAX);
287 return 0;
288}
289
290static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
291{
292 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
293 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
294 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
295 char mcc_pl[MLXSW_REG_MCC_LEN];
296
297 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
298 fwhandle, 0);
299 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
300}
301
302static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
303{
304 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
305 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
306 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
307 char mcc_pl[MLXSW_REG_MCC_LEN];
308
309 mlxsw_reg_mcc_pack(mcc_pl,
310 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
311 fwhandle, 0);
312 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
313}
314
315static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
316 .component_query = mlxsw_sp_component_query,
317 .fsm_lock = mlxsw_sp_fsm_lock,
318 .fsm_component_update = mlxsw_sp_fsm_component_update,
319 .fsm_block_download = mlxsw_sp_fsm_block_download,
320 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
321 .fsm_activate = mlxsw_sp_fsm_activate,
322 .fsm_query_state = mlxsw_sp_fsm_query_state,
323 .fsm_cancel = mlxsw_sp_fsm_cancel,
324 .fsm_release = mlxsw_sp_fsm_release
325};
326
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300327static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
328 const struct firmware *firmware)
329{
330 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
331 .mlxfw_dev = {
332 .ops = &mlxsw_sp_mlxfw_dev_ops,
333 .psid = mlxsw_sp->bus_info->psid,
334 .psid_size = strlen(mlxsw_sp->bus_info->psid),
335 },
336 .mlxsw_sp = mlxsw_sp
337 };
338
339 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
340}
341
Yotam Gigi6b742192017-05-23 21:56:29 +0200342static bool mlxsw_sp_fw_rev_ge(const struct mlxsw_fw_rev *a,
343 const struct mlxsw_fw_rev *b)
344{
345 if (a->major != b->major)
346 return a->major > b->major;
347 if (a->minor != b->minor)
348 return a->minor > b->minor;
349 return a->subminor >= b->subminor;
350}
351
352static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
353{
354 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
Yotam Gigi6b742192017-05-23 21:56:29 +0200355 const struct firmware *firmware;
356 int err;
357
358 if (mlxsw_sp_fw_rev_ge(rev, &mlxsw_sp_supported_fw_rev))
359 return 0;
360
Ido Schimmeld016e132018-01-10 14:56:54 +0100361 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is out of date\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200362 rev->major, rev->minor, rev->subminor);
363 dev_info(mlxsw_sp->bus_info->dev, "Upgrading firmware using file %s\n",
364 MLXSW_SP_FW_FILENAME);
365
366 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
367 mlxsw_sp->bus_info->dev);
368 if (err) {
369 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
370 MLXSW_SP_FW_FILENAME);
371 return err;
372 }
373
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300374 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
Yotam Gigi6b742192017-05-23 21:56:29 +0200375 release_firmware(firmware);
376 return err;
377}
378
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100379int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
380 unsigned int counter_index, u64 *packets,
381 u64 *bytes)
382{
383 char mgpc_pl[MLXSW_REG_MGPC_LEN];
384 int err;
385
386 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200387 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100388 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
389 if (err)
390 return err;
Arkadi Sharshevsky7cfcbc72017-08-24 08:40:08 +0200391 if (packets)
392 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
393 if (bytes)
394 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100395 return 0;
396}
397
398static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
399 unsigned int counter_index)
400{
401 char mgpc_pl[MLXSW_REG_MGPC_LEN];
402
403 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200404 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100405 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
406}
407
408int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
409 unsigned int *p_counter_index)
410{
411 int err;
412
413 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
414 p_counter_index);
415 if (err)
416 return err;
417 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
418 if (err)
419 goto err_counter_clear;
420 return 0;
421
422err_counter_clear:
423 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
424 *p_counter_index);
425 return err;
426}
427
428void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
429 unsigned int counter_index)
430{
431 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
432 counter_index);
433}
434
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200435static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
436 const struct mlxsw_tx_info *tx_info)
437{
438 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
439
440 memset(txhdr, 0, MLXSW_TXHDR_LEN);
441
442 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
443 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
444 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
445 mlxsw_tx_hdr_swid_set(txhdr, 0);
446 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
447 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
448 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
449}
450
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200451int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
452 u8 state)
453{
454 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
455 enum mlxsw_reg_spms_state spms_state;
456 char *spms_pl;
457 int err;
458
459 switch (state) {
460 case BR_STATE_FORWARDING:
461 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
462 break;
463 case BR_STATE_LEARNING:
464 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
465 break;
466 case BR_STATE_LISTENING: /* fall-through */
467 case BR_STATE_DISABLED: /* fall-through */
468 case BR_STATE_BLOCKING:
469 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
470 break;
471 default:
472 BUG();
473 }
474
475 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
476 if (!spms_pl)
477 return -ENOMEM;
478 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
479 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
480
481 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
482 kfree(spms_pl);
483 return err;
484}
485
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200486static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
487{
Elad Raz5b090742016-10-28 21:35:46 +0200488 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200489 int err;
490
491 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
492 if (err)
493 return err;
494 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
495 return 0;
496}
497
Yotam Gigi763b4b72016-07-21 12:03:17 +0200498static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
499{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200500 int i;
501
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200502 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
Yotam Gigi763b4b72016-07-21 12:03:17 +0200503 return -EIO;
504
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200505 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
506 MAX_SPAN);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200507 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
508 sizeof(struct mlxsw_sp_span_entry),
509 GFP_KERNEL);
510 if (!mlxsw_sp->span.entries)
511 return -ENOMEM;
512
513 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
514 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
515
516 return 0;
517}
518
519static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
520{
521 int i;
522
523 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
524 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
525
526 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
527 }
528 kfree(mlxsw_sp->span.entries);
529}
530
531static struct mlxsw_sp_span_entry *
532mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
533{
534 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
535 struct mlxsw_sp_span_entry *span_entry;
536 char mpat_pl[MLXSW_REG_MPAT_LEN];
537 u8 local_port = port->local_port;
538 int index;
539 int i;
540 int err;
541
542 /* find a free entry to use */
543 index = -1;
544 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
545 if (!mlxsw_sp->span.entries[i].used) {
546 index = i;
547 span_entry = &mlxsw_sp->span.entries[i];
548 break;
549 }
550 }
551 if (index < 0)
552 return NULL;
553
554 /* create a new port analayzer entry for local_port */
555 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
556 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
557 if (err)
558 return NULL;
559
560 span_entry->used = true;
561 span_entry->id = index;
Yotam Gigi2d644d42016-11-11 16:34:25 +0100562 span_entry->ref_count = 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200563 span_entry->local_port = local_port;
564 return span_entry;
565}
566
567static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
568 struct mlxsw_sp_span_entry *span_entry)
569{
570 u8 local_port = span_entry->local_port;
571 char mpat_pl[MLXSW_REG_MPAT_LEN];
572 int pa_id = span_entry->id;
573
574 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
575 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
576 span_entry->used = false;
577}
578
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200579static struct mlxsw_sp_span_entry *
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200580mlxsw_sp_span_entry_find(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200581{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200582 int i;
583
584 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
585 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
586
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200587 if (curr->used && curr->local_port == local_port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200588 return curr;
589 }
590 return NULL;
591}
592
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200593static struct mlxsw_sp_span_entry
594*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200595{
596 struct mlxsw_sp_span_entry *span_entry;
597
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200598 span_entry = mlxsw_sp_span_entry_find(port->mlxsw_sp,
599 port->local_port);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200600 if (span_entry) {
Yotam Gigi2d644d42016-11-11 16:34:25 +0100601 /* Already exists, just take a reference */
Yotam Gigi763b4b72016-07-21 12:03:17 +0200602 span_entry->ref_count++;
603 return span_entry;
604 }
605
606 return mlxsw_sp_span_entry_create(port);
607}
608
609static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
610 struct mlxsw_sp_span_entry *span_entry)
611{
Yotam Gigi2d644d42016-11-11 16:34:25 +0100612 WARN_ON(!span_entry->ref_count);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200613 if (--span_entry->ref_count == 0)
614 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
615 return 0;
616}
617
618static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
619{
620 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
621 struct mlxsw_sp_span_inspected_port *p;
622 int i;
623
624 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
625 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
626
627 list_for_each_entry(p, &curr->bound_ports_list, list)
628 if (p->local_port == port->local_port &&
629 p->type == MLXSW_SP_SPAN_EGRESS)
630 return true;
631 }
632
633 return false;
634}
635
Ido Schimmel18281f22017-03-24 08:02:51 +0100636static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
637 int mtu)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200638{
Ido Schimmel18281f22017-03-24 08:02:51 +0100639 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200640}
641
642static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
643{
644 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
645 char sbib_pl[MLXSW_REG_SBIB_LEN];
646 int err;
647
648 /* If port is egress mirrored, the shared buffer size should be
649 * updated according to the mtu value
650 */
651 if (mlxsw_sp_span_is_egress_mirror(port)) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100652 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
653
654 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200655 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
656 if (err) {
657 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
658 return err;
659 }
660 }
661
662 return 0;
663}
664
665static struct mlxsw_sp_span_inspected_port *
666mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
667 struct mlxsw_sp_span_entry *span_entry)
668{
669 struct mlxsw_sp_span_inspected_port *p;
670
671 list_for_each_entry(p, &span_entry->bound_ports_list, list)
672 if (port->local_port == p->local_port)
673 return p;
674 return NULL;
675}
676
677static int
678mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
679 struct mlxsw_sp_span_entry *span_entry,
680 enum mlxsw_sp_span_type type)
681{
682 struct mlxsw_sp_span_inspected_port *inspected_port;
683 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
684 char mpar_pl[MLXSW_REG_MPAR_LEN];
685 char sbib_pl[MLXSW_REG_SBIB_LEN];
686 int pa_id = span_entry->id;
687 int err;
688
689 /* if it is an egress SPAN, bind a shared buffer to it */
690 if (type == MLXSW_SP_SPAN_EGRESS) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100691 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
692 port->dev->mtu);
693
694 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200695 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
696 if (err) {
697 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
698 return err;
699 }
700 }
701
702 /* bind the port to the SPAN entry */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200703 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
704 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200705 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
706 if (err)
707 goto err_mpar_reg_write;
708
709 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
710 if (!inspected_port) {
711 err = -ENOMEM;
712 goto err_inspected_port_alloc;
713 }
714 inspected_port->local_port = port->local_port;
715 inspected_port->type = type;
716 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
717
718 return 0;
719
720err_mpar_reg_write:
721err_inspected_port_alloc:
722 if (type == MLXSW_SP_SPAN_EGRESS) {
723 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
724 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
725 }
726 return err;
727}
728
729static void
730mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
731 struct mlxsw_sp_span_entry *span_entry,
732 enum mlxsw_sp_span_type type)
733{
734 struct mlxsw_sp_span_inspected_port *inspected_port;
735 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
736 char mpar_pl[MLXSW_REG_MPAR_LEN];
737 char sbib_pl[MLXSW_REG_SBIB_LEN];
738 int pa_id = span_entry->id;
739
740 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
741 if (!inspected_port)
742 return;
743
744 /* remove the inspected port */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200745 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
746 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200747 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
748
749 /* remove the SBIB buffer if it was egress SPAN */
750 if (type == MLXSW_SP_SPAN_EGRESS) {
751 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
752 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
753 }
754
755 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
756
757 list_del(&inspected_port->list);
758 kfree(inspected_port);
759}
760
761static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
762 struct mlxsw_sp_port *to,
763 enum mlxsw_sp_span_type type)
764{
765 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
766 struct mlxsw_sp_span_entry *span_entry;
767 int err;
768
769 span_entry = mlxsw_sp_span_entry_get(to);
770 if (!span_entry)
771 return -ENOENT;
772
773 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
774 span_entry->id);
775
776 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
777 if (err)
778 goto err_port_bind;
779
780 return 0;
781
782err_port_bind:
783 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
784 return err;
785}
786
787static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200788 u8 destination_port,
Yotam Gigi763b4b72016-07-21 12:03:17 +0200789 enum mlxsw_sp_span_type type)
790{
791 struct mlxsw_sp_span_entry *span_entry;
792
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200793 span_entry = mlxsw_sp_span_entry_find(from->mlxsw_sp,
794 destination_port);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200795 if (!span_entry) {
796 netdev_err(from->dev, "no span entry found\n");
797 return;
798 }
799
800 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
801 span_entry->id);
802 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
803}
804
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100805static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
806 bool enable, u32 rate)
807{
808 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
809 char mpsc_pl[MLXSW_REG_MPSC_LEN];
810
811 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
812 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
813}
814
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200815static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
816 bool is_up)
817{
818 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
819 char paos_pl[MLXSW_REG_PAOS_LEN];
820
821 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
822 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
823 MLXSW_PORT_ADMIN_STATUS_DOWN);
824 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
825}
826
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200827static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
828 unsigned char *addr)
829{
830 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
831 char ppad_pl[MLXSW_REG_PPAD_LEN];
832
833 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
834 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
835 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
836}
837
838static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
839{
840 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
841 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
842
843 ether_addr_copy(addr, mlxsw_sp->base_mac);
844 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
845 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
846}
847
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200848static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
849{
850 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
851 char pmtu_pl[MLXSW_REG_PMTU_LEN];
852 int max_mtu;
853 int err;
854
855 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
856 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
857 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
858 if (err)
859 return err;
860 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
861
862 if (mtu > max_mtu)
863 return -EINVAL;
864
865 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
866 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
867}
868
869static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
870{
871 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel5b153852017-06-08 08:47:44 +0200872 char pspa_pl[MLXSW_REG_PSPA_LEN];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200873
Ido Schimmel5b153852017-06-08 08:47:44 +0200874 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
875 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200876}
877
Ido Schimmela1107482017-05-26 08:37:39 +0200878int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200879{
880 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
881 char svpe_pl[MLXSW_REG_SVPE_LEN];
882
883 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
884 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
885}
886
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200887int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
888 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200889{
890 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
891 char *spvmlr_pl;
892 int err;
893
894 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
895 if (!spvmlr_pl)
896 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200897 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
898 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200899 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
900 kfree(spvmlr_pl);
901 return err;
902}
903
Ido Schimmelb02eae92017-05-16 19:38:34 +0200904static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
905 u16 vid)
906{
907 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
908 char spvid_pl[MLXSW_REG_SPVID_LEN];
909
910 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
911 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
912}
913
914static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
915 bool allow)
916{
917 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
918 char spaft_pl[MLXSW_REG_SPAFT_LEN];
919
920 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
921 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
922}
923
924int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
925{
926 int err;
927
928 if (!vid) {
929 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
930 if (err)
931 return err;
932 } else {
933 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
934 if (err)
935 return err;
936 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
937 if (err)
938 goto err_port_allow_untagged_set;
939 }
940
941 mlxsw_sp_port->pvid = vid;
942 return 0;
943
944err_port_allow_untagged_set:
945 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
946 return err;
947}
948
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200949static int
950mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
951{
952 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
953 char sspr_pl[MLXSW_REG_SSPR_LEN];
954
955 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
956 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
957}
958
Ido Schimmeld664b412016-06-09 09:51:40 +0200959static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
960 u8 local_port, u8 *p_module,
961 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200962{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200963 char pmlp_pl[MLXSW_REG_PMLP_LEN];
964 int err;
965
Ido Schimmel558c2d52016-02-26 17:32:29 +0100966 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200967 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
968 if (err)
969 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100970 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
971 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200972 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200973 return 0;
974}
975
Ido Schimmel2e915e02017-06-08 08:47:45 +0200976static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100977 u8 module, u8 width, u8 lane)
978{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200979 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel18f1e702016-02-26 17:32:31 +0100980 char pmlp_pl[MLXSW_REG_PMLP_LEN];
981 int i;
982
Ido Schimmel2e915e02017-06-08 08:47:45 +0200983 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel18f1e702016-02-26 17:32:31 +0100984 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
985 for (i = 0; i < width; i++) {
986 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
987 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
988 }
989
990 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
991}
992
Ido Schimmel2e915e02017-06-08 08:47:45 +0200993static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100994{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200995 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100996 char pmlp_pl[MLXSW_REG_PMLP_LEN];
997
Ido Schimmel2e915e02017-06-08 08:47:45 +0200998 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100999 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
1000 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
1001}
1002
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001003static int mlxsw_sp_port_open(struct net_device *dev)
1004{
1005 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1006 int err;
1007
1008 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1009 if (err)
1010 return err;
1011 netif_start_queue(dev);
1012 return 0;
1013}
1014
1015static int mlxsw_sp_port_stop(struct net_device *dev)
1016{
1017 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1018
1019 netif_stop_queue(dev);
1020 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1021}
1022
1023static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
1024 struct net_device *dev)
1025{
1026 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1027 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1028 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
1029 const struct mlxsw_tx_info tx_info = {
1030 .local_port = mlxsw_sp_port->local_port,
1031 .is_emad = false,
1032 };
1033 u64 len;
1034 int err;
1035
Jiri Pirko307c2432016-04-08 19:11:22 +02001036 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001037 return NETDEV_TX_BUSY;
1038
1039 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
1040 struct sk_buff *skb_orig = skb;
1041
1042 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
1043 if (!skb) {
1044 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1045 dev_kfree_skb_any(skb_orig);
1046 return NETDEV_TX_OK;
1047 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +01001048 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001049 }
1050
1051 if (eth_skb_pad(skb)) {
1052 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1053 return NETDEV_TX_OK;
1054 }
1055
1056 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +02001057 /* TX header is consumed by HW on the way so we shouldn't count its
1058 * bytes as being sent.
1059 */
1060 len = skb->len - MLXSW_TXHDR_LEN;
1061
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001062 /* Due to a race we might fail here because of a full queue. In that
1063 * unlikely case we simply drop the packet.
1064 */
Jiri Pirko307c2432016-04-08 19:11:22 +02001065 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001066
1067 if (!err) {
1068 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
1069 u64_stats_update_begin(&pcpu_stats->syncp);
1070 pcpu_stats->tx_packets++;
1071 pcpu_stats->tx_bytes += len;
1072 u64_stats_update_end(&pcpu_stats->syncp);
1073 } else {
1074 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1075 dev_kfree_skb_any(skb);
1076 }
1077 return NETDEV_TX_OK;
1078}
1079
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001080static void mlxsw_sp_set_rx_mode(struct net_device *dev)
1081{
1082}
1083
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001084static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
1085{
1086 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1087 struct sockaddr *addr = p;
1088 int err;
1089
1090 if (!is_valid_ether_addr(addr->sa_data))
1091 return -EADDRNOTAVAIL;
1092
1093 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
1094 if (err)
1095 return err;
1096 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1097 return 0;
1098}
1099
Ido Schimmel18281f22017-03-24 08:02:51 +01001100static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
1101 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001102{
Ido Schimmel18281f22017-03-24 08:02:51 +01001103 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001104}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001105
Ido Schimmelf417f042017-03-24 08:02:50 +01001106#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +01001107
1108static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1109 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +01001110{
Ido Schimmel18281f22017-03-24 08:02:51 +01001111 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
1112 BITS_PER_BYTE));
1113 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
1114 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001115}
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001116
Ido Schimmel18281f22017-03-24 08:02:51 +01001117/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +01001118 * Assumes 100m cable and maximum MTU.
1119 */
Ido Schimmel18281f22017-03-24 08:02:51 +01001120#define MLXSW_SP_PAUSE_DELAY 58752
1121
1122static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1123 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +01001124{
1125 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +01001126 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +01001127 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +01001128 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001129 else
Ido Schimmelf417f042017-03-24 08:02:50 +01001130 return 0;
1131}
1132
1133static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
1134 bool lossy)
1135{
1136 if (lossy)
1137 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
1138 else
1139 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
1140 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001141}
1142
1143int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001144 u8 *prio_tc, bool pause_en,
1145 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +02001146{
1147 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001148 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
1149 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001150 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001151 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001152
1153 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
1154 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1155 if (err)
1156 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001157
1158 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1159 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001160 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +01001161 bool lossy;
1162 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001163
1164 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
1165 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001166 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001167 configure = true;
1168 break;
1169 }
1170 }
1171
1172 if (!configure)
1173 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +01001174
1175 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +01001176 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
1177 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
1178 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +01001179 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001180 }
1181
Ido Schimmelff6551e2016-04-06 17:10:03 +02001182 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1183}
1184
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001185static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001186 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001187{
1188 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
1189 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001190 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001191 u8 *prio_tc;
1192
1193 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001194 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001195
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001196 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001197 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001198}
1199
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001200static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
1201{
1202 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001203 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001204 int err;
1205
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001206 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001207 if (err)
1208 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001209 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1210 if (err)
1211 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001212 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1213 if (err)
1214 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001215 dev->mtu = mtu;
1216 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001217
1218err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001219 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1220err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001221 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +02001222 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001223}
1224
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001225static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001226mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1227 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001228{
1229 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1230 struct mlxsw_sp_port_pcpu_stats *p;
1231 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1232 u32 tx_dropped = 0;
1233 unsigned int start;
1234 int i;
1235
1236 for_each_possible_cpu(i) {
1237 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1238 do {
1239 start = u64_stats_fetch_begin_irq(&p->syncp);
1240 rx_packets = p->rx_packets;
1241 rx_bytes = p->rx_bytes;
1242 tx_packets = p->tx_packets;
1243 tx_bytes = p->tx_bytes;
1244 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1245
1246 stats->rx_packets += rx_packets;
1247 stats->rx_bytes += rx_bytes;
1248 stats->tx_packets += tx_packets;
1249 stats->tx_bytes += tx_bytes;
1250 /* tx_dropped is u32, updated without syncp protection. */
1251 tx_dropped += p->tx_dropped;
1252 }
1253 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001254 return 0;
1255}
1256
Or Gerlitz3df5b3c2016-11-22 23:09:54 +02001257static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001258{
1259 switch (attr_id) {
1260 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1261 return true;
1262 }
1263
1264 return false;
1265}
1266
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001267static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1268 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001269{
1270 switch (attr_id) {
1271 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1272 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1273 }
1274
1275 return -EINVAL;
1276}
1277
1278static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1279 int prio, char *ppcnt_pl)
1280{
1281 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1282 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1283
1284 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1285 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1286}
1287
1288static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1289 struct rtnl_link_stats64 *stats)
1290{
1291 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1292 int err;
1293
1294 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1295 0, ppcnt_pl);
1296 if (err)
1297 goto out;
1298
1299 stats->tx_packets =
1300 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1301 stats->rx_packets =
1302 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1303 stats->tx_bytes =
1304 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1305 stats->rx_bytes =
1306 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1307 stats->multicast =
1308 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1309
1310 stats->rx_crc_errors =
1311 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1312 stats->rx_frame_errors =
1313 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1314
1315 stats->rx_length_errors = (
1316 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1317 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1318 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1319
1320 stats->rx_errors = (stats->rx_crc_errors +
1321 stats->rx_frame_errors + stats->rx_length_errors);
1322
1323out:
1324 return err;
1325}
1326
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001327static void
1328mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1329 struct mlxsw_sp_port_xstats *xstats)
1330{
1331 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1332 int err, i;
1333
1334 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1335 ppcnt_pl);
1336 if (!err)
1337 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1338
1339 for (i = 0; i < TC_MAX_QUEUE; i++) {
1340 err = mlxsw_sp_port_get_stats_raw(dev,
1341 MLXSW_REG_PPCNT_TC_CONG_TC,
1342 i, ppcnt_pl);
1343 if (!err)
1344 xstats->wred_drop[i] =
1345 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1346
1347 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1348 i, ppcnt_pl);
1349 if (err)
1350 continue;
1351
1352 xstats->backlog[i] =
1353 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1354 xstats->tail_drop[i] =
1355 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1356 }
1357}
1358
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001359static void update_stats_cache(struct work_struct *work)
1360{
1361 struct mlxsw_sp_port *mlxsw_sp_port =
1362 container_of(work, struct mlxsw_sp_port,
Nogah Frankel9deef432017-10-26 10:55:32 +02001363 periodic_hw_stats.update_dw.work);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001364
1365 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1366 goto out;
1367
1368 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
Nogah Frankel9deef432017-10-26 10:55:32 +02001369 &mlxsw_sp_port->periodic_hw_stats.stats);
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001370 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1371 &mlxsw_sp_port->periodic_hw_stats.xstats);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001372
1373out:
Nogah Frankel9deef432017-10-26 10:55:32 +02001374 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001375 MLXSW_HW_STATS_UPDATE_TIME);
1376}
1377
1378/* Return the stats from a cache that is updated periodically,
1379 * as this function might get called in an atomic context.
1380 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001381static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001382mlxsw_sp_port_get_stats64(struct net_device *dev,
1383 struct rtnl_link_stats64 *stats)
1384{
1385 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1386
Nogah Frankel9deef432017-10-26 10:55:32 +02001387 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001388}
1389
Jiri Pirko93cd0812017-04-18 16:55:35 +02001390static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1391 u16 vid_begin, u16 vid_end,
1392 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001393{
1394 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1395 char *spvm_pl;
1396 int err;
1397
1398 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1399 if (!spvm_pl)
1400 return -ENOMEM;
1401
1402 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1403 vid_end, is_member, untagged);
1404 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1405 kfree(spvm_pl);
1406 return err;
1407}
1408
Jiri Pirko93cd0812017-04-18 16:55:35 +02001409int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1410 u16 vid_end, bool is_member, bool untagged)
1411{
1412 u16 vid, vid_e;
1413 int err;
1414
1415 for (vid = vid_begin; vid <= vid_end;
1416 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1417 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1418 vid_end);
1419
1420 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1421 is_member, untagged);
1422 if (err)
1423 return err;
1424 }
1425
1426 return 0;
1427}
1428
Ido Schimmelc57529e2017-05-26 08:37:31 +02001429static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001430{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001431 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001432
Ido Schimmelc57529e2017-05-26 08:37:31 +02001433 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1434 &mlxsw_sp_port->vlans_list, list)
1435 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001436}
1437
Ido Schimmel31a08a52017-05-26 08:37:26 +02001438static struct mlxsw_sp_port_vlan *
1439mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1440{
1441 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001442 bool untagged = vid == 1;
1443 int err;
1444
1445 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1446 if (err)
1447 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001448
1449 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001450 if (!mlxsw_sp_port_vlan) {
1451 err = -ENOMEM;
1452 goto err_port_vlan_alloc;
1453 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02001454
1455 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1456 mlxsw_sp_port_vlan->vid = vid;
1457 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1458
1459 return mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001460
1461err_port_vlan_alloc:
1462 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1463 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001464}
1465
1466static void
1467mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1468{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001469 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1470 u16 vid = mlxsw_sp_port_vlan->vid;
Ido Schimmel7cbecf22017-05-26 08:37:28 +02001471
Ido Schimmel31a08a52017-05-26 08:37:26 +02001472 list_del(&mlxsw_sp_port_vlan->list);
1473 kfree(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001474 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1475}
1476
1477struct mlxsw_sp_port_vlan *
1478mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1479{
1480 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1481
1482 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1483 if (mlxsw_sp_port_vlan)
1484 return mlxsw_sp_port_vlan;
1485
1486 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1487}
1488
1489void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1490{
Ido Schimmela1107482017-05-26 08:37:39 +02001491 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1492
Ido Schimmelc57529e2017-05-26 08:37:31 +02001493 if (mlxsw_sp_port_vlan->bridge_port)
1494 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
Ido Schimmela1107482017-05-26 08:37:39 +02001495 else if (fid)
1496 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001497
1498 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001499}
1500
Ido Schimmel05978482016-08-17 16:39:30 +02001501static int mlxsw_sp_port_add_vid(struct net_device *dev,
1502 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001503{
1504 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001505
1506 /* VLAN 0 is added to HW filter when device goes up, but it is
1507 * reserved in our case, so simply return.
1508 */
1509 if (!vid)
1510 return 0;
1511
Ido Schimmelc57529e2017-05-26 08:37:31 +02001512 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001513}
1514
Ido Schimmel32d863f2016-07-02 11:00:10 +02001515static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1516 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001517{
1518 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001519 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001520
1521 /* VLAN 0 is removed from HW filter when device goes down, but
1522 * it is reserved in our case, so simply return.
1523 */
1524 if (!vid)
1525 return 0;
1526
Ido Schimmel31a08a52017-05-26 08:37:26 +02001527 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001528 if (!mlxsw_sp_port_vlan)
Ido Schimmel31a08a52017-05-26 08:37:26 +02001529 return 0;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001530 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001531
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001532 return 0;
1533}
1534
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001535static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1536 size_t len)
1537{
1538 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +02001539 u8 module = mlxsw_sp_port->mapping.module;
1540 u8 width = mlxsw_sp_port->mapping.width;
1541 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001542 int err;
1543
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001544 if (!mlxsw_sp_port->split)
1545 err = snprintf(name, len, "p%d", module + 1);
1546 else
1547 err = snprintf(name, len, "p%ds%d", module + 1,
1548 lane / width);
1549
1550 if (err >= len)
1551 return -EINVAL;
1552
1553 return 0;
1554}
1555
Yotam Gigi763b4b72016-07-21 12:03:17 +02001556static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001557mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1558 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001559 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1560
1561 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1562 if (mall_tc_entry->cookie == cookie)
1563 return mall_tc_entry;
1564
1565 return NULL;
1566}
1567
1568static int
1569mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001570 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001571 const struct tc_action *a,
1572 bool ingress)
1573{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001574 enum mlxsw_sp_span_type span_type;
1575 struct mlxsw_sp_port *to_port;
1576 struct net_device *to_dev;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001577
Cong Wang9f8a7392017-12-05 16:17:26 -08001578 to_dev = tcf_mirred_dev(a);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001579 if (!to_dev) {
1580 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1581 return -EINVAL;
1582 }
1583
1584 if (!mlxsw_sp_port_dev_check(to_dev)) {
1585 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
Yotam Gigie915ac62017-01-09 11:25:48 +01001586 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001587 }
1588 to_port = netdev_priv(to_dev);
1589
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001590 mirror->to_local_port = to_port->local_port;
1591 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001592 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001593 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1594}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001595
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001596static void
1597mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1598 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1599{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001600 enum mlxsw_sp_span_type span_type;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001601
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001602 span_type = mirror->ingress ?
1603 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Yuval Mintz6399ebc2017-09-12 08:50:53 +02001604 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, mirror->to_local_port,
1605 span_type);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001606}
1607
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001608static int
1609mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1610 struct tc_cls_matchall_offload *cls,
1611 const struct tc_action *a,
1612 bool ingress)
1613{
1614 int err;
1615
1616 if (!mlxsw_sp_port->sample)
1617 return -EOPNOTSUPP;
1618 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1619 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1620 return -EEXIST;
1621 }
1622 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1623 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1624 return -EOPNOTSUPP;
1625 }
1626
1627 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1628 tcf_sample_psample_group(a));
1629 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1630 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1631 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1632
1633 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1634 if (err)
1635 goto err_port_sample_set;
1636 return 0;
1637
1638err_port_sample_set:
1639 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1640 return err;
1641}
1642
1643static void
1644mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1645{
1646 if (!mlxsw_sp_port->sample)
1647 return;
1648
1649 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1650 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1651}
1652
Yotam Gigi763b4b72016-07-21 12:03:17 +02001653static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001654 struct tc_cls_matchall_offload *f,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001655 bool ingress)
1656{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001657 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001658 __be16 protocol = f->common.protocol;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001659 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001660 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001661 int err;
1662
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001663 if (!tcf_exts_has_one_action(f->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001664 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001665 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001666 }
1667
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001668 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1669 if (!mall_tc_entry)
1670 return -ENOMEM;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001671 mall_tc_entry->cookie = f->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001672
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001673 tcf_exts_to_list(f->exts, &actions);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001674 a = list_first_entry(&actions, struct tc_action, list);
1675
1676 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1677 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1678
1679 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1680 mirror = &mall_tc_entry->mirror;
1681 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1682 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001683 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1684 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001685 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001686 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001687 } else {
1688 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001689 }
1690
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001691 if (err)
1692 goto err_add_action;
1693
1694 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001695 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001696
1697err_add_action:
1698 kfree(mall_tc_entry);
1699 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001700}
1701
1702static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001703 struct tc_cls_matchall_offload *f)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001704{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001705 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001706
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001707 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001708 f->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001709 if (!mall_tc_entry) {
1710 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1711 return;
1712 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001713 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001714
1715 switch (mall_tc_entry->type) {
1716 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001717 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1718 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001719 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001720 case MLXSW_SP_PORT_MALL_SAMPLE:
1721 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1722 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001723 default:
1724 WARN_ON(1);
1725 }
1726
Yotam Gigi763b4b72016-07-21 12:03:17 +02001727 kfree(mall_tc_entry);
1728}
1729
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001730static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001731 struct tc_cls_matchall_offload *f,
1732 bool ingress)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001733{
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001734 if (f->common.chain_index)
Jiri Pirkoa5fcf8a2017-06-06 17:00:16 +02001735 return -EOPNOTSUPP;
1736
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001737 switch (f->command) {
1738 case TC_CLSMATCHALL_REPLACE:
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001739 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001740 ingress);
1741 case TC_CLSMATCHALL_DESTROY:
1742 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1743 return 0;
1744 default:
1745 return -EOPNOTSUPP;
1746 }
1747}
1748
1749static int
Jiri Pirko3aaff322018-01-17 11:46:56 +01001750mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1751 struct tc_cls_flower_offload *f)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001752{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001753 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1754
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001755 switch (f->command) {
1756 case TC_CLSFLOWER_REPLACE:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001757 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001758 case TC_CLSFLOWER_DESTROY:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001759 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001760 return 0;
1761 case TC_CLSFLOWER_STATS:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001762 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001763 default:
1764 return -EOPNOTSUPP;
1765 }
1766}
1767
Jiri Pirko3aaff322018-01-17 11:46:56 +01001768static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1769 void *type_data,
1770 void *cb_priv, bool ingress)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001771{
1772 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1773
1774 switch (type) {
1775 case TC_SETUP_CLSMATCHALL:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001776 if (!tc_can_offload(mlxsw_sp_port->dev))
1777 return -EOPNOTSUPP;
1778
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001779 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1780 ingress);
1781 case TC_SETUP_CLSFLOWER:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001782 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001783 default:
1784 return -EOPNOTSUPP;
1785 }
1786}
1787
Jiri Pirko3aaff322018-01-17 11:46:56 +01001788static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1789 void *type_data,
1790 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001791{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001792 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1793 cb_priv, true);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001794}
1795
Jiri Pirko3aaff322018-01-17 11:46:56 +01001796static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1797 void *type_data,
1798 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001799{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001800 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1801 cb_priv, false);
1802}
1803
1804static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1805 void *type_data, void *cb_priv)
1806{
1807 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1808
1809 switch (type) {
1810 case TC_SETUP_CLSMATCHALL:
1811 return 0;
1812 case TC_SETUP_CLSFLOWER:
1813 if (mlxsw_sp_acl_block_disabled(acl_block))
1814 return -EOPNOTSUPP;
1815
1816 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1817 default:
1818 return -EOPNOTSUPP;
1819 }
1820}
1821
1822static int
1823mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1824 struct tcf_block *block, bool ingress)
1825{
1826 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1827 struct mlxsw_sp_acl_block *acl_block;
1828 struct tcf_block_cb *block_cb;
1829 int err;
1830
1831 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1832 mlxsw_sp);
1833 if (!block_cb) {
1834 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1835 if (!acl_block)
1836 return -ENOMEM;
1837 block_cb = __tcf_block_cb_register(block,
1838 mlxsw_sp_setup_tc_block_cb_flower,
1839 mlxsw_sp, acl_block);
1840 if (IS_ERR(block_cb)) {
1841 err = PTR_ERR(block_cb);
1842 goto err_cb_register;
1843 }
1844 } else {
1845 acl_block = tcf_block_cb_priv(block_cb);
1846 }
1847 tcf_block_cb_incref(block_cb);
1848 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1849 mlxsw_sp_port, ingress);
1850 if (err)
1851 goto err_block_bind;
1852
1853 if (ingress)
1854 mlxsw_sp_port->ing_acl_block = acl_block;
1855 else
1856 mlxsw_sp_port->eg_acl_block = acl_block;
1857
1858 return 0;
1859
1860err_block_bind:
1861 if (!tcf_block_cb_decref(block_cb)) {
1862 __tcf_block_cb_unregister(block_cb);
1863err_cb_register:
1864 mlxsw_sp_acl_block_destroy(acl_block);
1865 }
1866 return err;
1867}
1868
1869static void
1870mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1871 struct tcf_block *block, bool ingress)
1872{
1873 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1874 struct mlxsw_sp_acl_block *acl_block;
1875 struct tcf_block_cb *block_cb;
1876 int err;
1877
1878 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1879 mlxsw_sp);
1880 if (!block_cb)
1881 return;
1882
1883 if (ingress)
1884 mlxsw_sp_port->ing_acl_block = NULL;
1885 else
1886 mlxsw_sp_port->eg_acl_block = NULL;
1887
1888 acl_block = tcf_block_cb_priv(block_cb);
1889 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1890 mlxsw_sp_port, ingress);
1891 if (!err && !tcf_block_cb_decref(block_cb)) {
1892 __tcf_block_cb_unregister(block_cb);
1893 mlxsw_sp_acl_block_destroy(acl_block);
1894 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001895}
1896
1897static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1898 struct tc_block_offload *f)
1899{
1900 tc_setup_cb_t *cb;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001901 bool ingress;
1902 int err;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001903
Jiri Pirko3aaff322018-01-17 11:46:56 +01001904 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1905 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1906 ingress = true;
1907 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1908 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1909 ingress = false;
1910 } else {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001911 return -EOPNOTSUPP;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001912 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001913
1914 switch (f->command) {
1915 case TC_BLOCK_BIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001916 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1917 mlxsw_sp_port);
1918 if (err)
1919 return err;
1920 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
1921 f->block, ingress);
1922 if (err) {
1923 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1924 return err;
1925 }
1926 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001927 case TC_BLOCK_UNBIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001928 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1929 f->block, ingress);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001930 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1931 return 0;
1932 default:
1933 return -EOPNOTSUPP;
1934 }
1935}
1936
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001937static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
Jiri Pirkode4784c2017-08-07 10:15:32 +02001938 void *type_data)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001939{
1940 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1941
Jiri Pirko2572ac52017-08-07 10:15:17 +02001942 switch (type) {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001943 case TC_SETUP_BLOCK:
1944 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
Nogah Frankel96f17e02017-11-06 07:23:45 +01001945 case TC_SETUP_QDISC_RED:
1946 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
Nogah Frankel46a36152018-01-14 12:33:16 +01001947 case TC_SETUP_QDISC_PRIO:
1948 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
Jiri Pirko2572ac52017-08-07 10:15:17 +02001949 default:
1950 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001951 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001952}
1953
Jiri Pirko9454d932017-12-06 09:41:12 +01001954
1955static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1956{
1957 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1958
Jiri Pirko3aaff322018-01-17 11:46:56 +01001959 if (!enable) {
1960 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1961 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1962 !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1963 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1964 return -EINVAL;
1965 }
1966 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1967 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1968 } else {
1969 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1970 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
Jiri Pirko9454d932017-12-06 09:41:12 +01001971 }
1972 return 0;
1973}
1974
1975typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1976
1977static int mlxsw_sp_handle_feature(struct net_device *dev,
1978 netdev_features_t wanted_features,
1979 netdev_features_t feature,
1980 mlxsw_sp_feature_handler feature_handler)
1981{
1982 netdev_features_t changes = wanted_features ^ dev->features;
1983 bool enable = !!(wanted_features & feature);
1984 int err;
1985
1986 if (!(changes & feature))
1987 return 0;
1988
1989 err = feature_handler(dev, enable);
1990 if (err) {
1991 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1992 enable ? "Enable" : "Disable", &feature, err);
1993 return err;
1994 }
1995
1996 if (enable)
1997 dev->features |= feature;
1998 else
1999 dev->features &= ~feature;
2000
2001 return 0;
2002}
2003static int mlxsw_sp_set_features(struct net_device *dev,
2004 netdev_features_t features)
2005{
2006 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
2007 mlxsw_sp_feature_hw_tc);
2008}
2009
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002010static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
2011 .ndo_open = mlxsw_sp_port_open,
2012 .ndo_stop = mlxsw_sp_port_stop,
2013 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02002014 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01002015 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002016 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
2017 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
2018 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002019 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
2020 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002021 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
2022 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02002023 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko9454d932017-12-06 09:41:12 +01002024 .ndo_set_features = mlxsw_sp_set_features,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002025};
2026
2027static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
2028 struct ethtool_drvinfo *drvinfo)
2029{
2030 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2031 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2032
2033 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
2034 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
2035 sizeof(drvinfo->version));
2036 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
2037 "%d.%d.%d",
2038 mlxsw_sp->bus_info->fw_rev.major,
2039 mlxsw_sp->bus_info->fw_rev.minor,
2040 mlxsw_sp->bus_info->fw_rev.subminor);
2041 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
2042 sizeof(drvinfo->bus_info));
2043}
2044
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002045static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
2046 struct ethtool_pauseparam *pause)
2047{
2048 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2049
2050 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
2051 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
2052}
2053
2054static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
2055 struct ethtool_pauseparam *pause)
2056{
2057 char pfcc_pl[MLXSW_REG_PFCC_LEN];
2058
2059 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
2060 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
2061 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
2062
2063 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
2064 pfcc_pl);
2065}
2066
2067static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
2068 struct ethtool_pauseparam *pause)
2069{
2070 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2071 bool pause_en = pause->tx_pause || pause->rx_pause;
2072 int err;
2073
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02002074 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
2075 netdev_err(dev, "PFC already enabled on port\n");
2076 return -EINVAL;
2077 }
2078
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002079 if (pause->autoneg) {
2080 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
2081 return -EINVAL;
2082 }
2083
2084 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
2085 if (err) {
2086 netdev_err(dev, "Failed to configure port's headroom\n");
2087 return err;
2088 }
2089
2090 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
2091 if (err) {
2092 netdev_err(dev, "Failed to set PAUSE parameters\n");
2093 goto err_port_pause_configure;
2094 }
2095
2096 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
2097 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
2098
2099 return 0;
2100
2101err_port_pause_configure:
2102 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
2103 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
2104 return err;
2105}
2106
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002107struct mlxsw_sp_port_hw_stats {
2108 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02002109 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01002110 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002111};
2112
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002113static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002114 {
2115 .str = "a_frames_transmitted_ok",
2116 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
2117 },
2118 {
2119 .str = "a_frames_received_ok",
2120 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
2121 },
2122 {
2123 .str = "a_frame_check_sequence_errors",
2124 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
2125 },
2126 {
2127 .str = "a_alignment_errors",
2128 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
2129 },
2130 {
2131 .str = "a_octets_transmitted_ok",
2132 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
2133 },
2134 {
2135 .str = "a_octets_received_ok",
2136 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
2137 },
2138 {
2139 .str = "a_multicast_frames_xmitted_ok",
2140 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
2141 },
2142 {
2143 .str = "a_broadcast_frames_xmitted_ok",
2144 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
2145 },
2146 {
2147 .str = "a_multicast_frames_received_ok",
2148 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
2149 },
2150 {
2151 .str = "a_broadcast_frames_received_ok",
2152 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
2153 },
2154 {
2155 .str = "a_in_range_length_errors",
2156 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
2157 },
2158 {
2159 .str = "a_out_of_range_length_field",
2160 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
2161 },
2162 {
2163 .str = "a_frame_too_long_errors",
2164 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
2165 },
2166 {
2167 .str = "a_symbol_error_during_carrier",
2168 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
2169 },
2170 {
2171 .str = "a_mac_control_frames_transmitted",
2172 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
2173 },
2174 {
2175 .str = "a_mac_control_frames_received",
2176 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
2177 },
2178 {
2179 .str = "a_unsupported_opcodes_received",
2180 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
2181 },
2182 {
2183 .str = "a_pause_mac_ctrl_frames_received",
2184 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
2185 },
2186 {
2187 .str = "a_pause_mac_ctrl_frames_xmitted",
2188 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
2189 },
2190};
2191
2192#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
2193
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002194static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
2195 {
2196 .str = "rx_octets_prio",
2197 .getter = mlxsw_reg_ppcnt_rx_octets_get,
2198 },
2199 {
2200 .str = "rx_frames_prio",
2201 .getter = mlxsw_reg_ppcnt_rx_frames_get,
2202 },
2203 {
2204 .str = "tx_octets_prio",
2205 .getter = mlxsw_reg_ppcnt_tx_octets_get,
2206 },
2207 {
2208 .str = "tx_frames_prio",
2209 .getter = mlxsw_reg_ppcnt_tx_frames_get,
2210 },
2211 {
2212 .str = "rx_pause_prio",
2213 .getter = mlxsw_reg_ppcnt_rx_pause_get,
2214 },
2215 {
2216 .str = "rx_pause_duration_prio",
2217 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2218 },
2219 {
2220 .str = "tx_pause_prio",
2221 .getter = mlxsw_reg_ppcnt_tx_pause_get,
2222 },
2223 {
2224 .str = "tx_pause_duration_prio",
2225 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2226 },
2227};
2228
2229#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2230
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002231static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2232 {
2233 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01002234 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2235 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002236 },
2237 {
2238 .str = "tc_no_buffer_discard_uc_tc",
2239 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2240 },
2241};
2242
2243#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2244
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002245#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002246 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
2247 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002248 IEEE_8021QAZ_MAX_TCS)
2249
2250static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2251{
2252 int i;
2253
2254 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2255 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2256 mlxsw_sp_port_hw_prio_stats[i].str, prio);
2257 *p += ETH_GSTRING_LEN;
2258 }
2259}
2260
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002261static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2262{
2263 int i;
2264
2265 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2266 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2267 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2268 *p += ETH_GSTRING_LEN;
2269 }
2270}
2271
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002272static void mlxsw_sp_port_get_strings(struct net_device *dev,
2273 u32 stringset, u8 *data)
2274{
2275 u8 *p = data;
2276 int i;
2277
2278 switch (stringset) {
2279 case ETH_SS_STATS:
2280 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2281 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2282 ETH_GSTRING_LEN);
2283 p += ETH_GSTRING_LEN;
2284 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002285
2286 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2287 mlxsw_sp_port_get_prio_strings(&p, i);
2288
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002289 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2290 mlxsw_sp_port_get_tc_strings(&p, i);
2291
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002292 break;
2293 }
2294}
2295
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002296static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2297 enum ethtool_phys_id_state state)
2298{
2299 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2300 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2301 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2302 bool active;
2303
2304 switch (state) {
2305 case ETHTOOL_ID_ACTIVE:
2306 active = true;
2307 break;
2308 case ETHTOOL_ID_INACTIVE:
2309 active = false;
2310 break;
2311 default:
2312 return -EOPNOTSUPP;
2313 }
2314
2315 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2316 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2317}
2318
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002319static int
2320mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2321 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2322{
2323 switch (grp) {
2324 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2325 *p_hw_stats = mlxsw_sp_port_hw_stats;
2326 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2327 break;
2328 case MLXSW_REG_PPCNT_PRIO_CNT:
2329 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2330 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2331 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002332 case MLXSW_REG_PPCNT_TC_CNT:
2333 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2334 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2335 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002336 default:
2337 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002338 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002339 }
2340 return 0;
2341}
2342
2343static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2344 enum mlxsw_reg_ppcnt_grp grp, int prio,
2345 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002346{
Ido Schimmel18281f22017-03-24 08:02:51 +01002347 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2348 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002349 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002350 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002351 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002352 int err;
2353
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002354 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2355 if (err)
2356 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002357 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002358 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002359 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002360 if (!hw_stats[i].cells_bytes)
2361 continue;
2362 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2363 data[data_index + i]);
2364 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002365}
2366
2367static void mlxsw_sp_port_get_stats(struct net_device *dev,
2368 struct ethtool_stats *stats, u64 *data)
2369{
2370 int i, data_index = 0;
2371
2372 /* IEEE 802.3 Counters */
2373 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2374 data, data_index);
2375 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2376
2377 /* Per-Priority Counters */
2378 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2379 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2380 data, data_index);
2381 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2382 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002383
2384 /* Per-TC Counters */
2385 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2386 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2387 data, data_index);
2388 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2389 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002390}
2391
2392static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2393{
2394 switch (sset) {
2395 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002396 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002397 default:
2398 return -EOPNOTSUPP;
2399 }
2400}
2401
2402struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002403 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002404 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002405 u32 speed;
2406};
2407
2408static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2409 {
2410 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002411 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2412 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002413 },
2414 {
2415 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2416 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002417 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2418 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002419 },
2420 {
2421 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002422 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2423 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002424 },
2425 {
2426 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2427 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002428 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2429 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002430 },
2431 {
2432 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2433 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2434 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2435 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002436 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2437 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002438 },
2439 {
2440 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002441 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2442 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002443 },
2444 {
2445 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002446 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2447 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002448 },
2449 {
2450 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002451 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2452 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002453 },
2454 {
2455 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002456 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2457 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002458 },
2459 {
2460 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002461 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2462 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002463 },
2464 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002465 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2466 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2467 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002468 },
2469 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002470 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2471 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2472 .speed = SPEED_25000,
2473 },
2474 {
2475 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2476 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2477 .speed = SPEED_25000,
2478 },
2479 {
2480 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2481 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2482 .speed = SPEED_25000,
2483 },
2484 {
2485 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2486 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2487 .speed = SPEED_50000,
2488 },
2489 {
2490 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2491 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2492 .speed = SPEED_50000,
2493 },
2494 {
2495 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2496 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2497 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002498 },
2499 {
2500 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002501 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2502 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002503 },
2504 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002505 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2506 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2507 .speed = SPEED_56000,
2508 },
2509 {
2510 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2511 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2512 .speed = SPEED_56000,
2513 },
2514 {
2515 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2516 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2517 .speed = SPEED_56000,
2518 },
2519 {
2520 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2521 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2522 .speed = SPEED_100000,
2523 },
2524 {
2525 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2526 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2527 .speed = SPEED_100000,
2528 },
2529 {
2530 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2531 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2532 .speed = SPEED_100000,
2533 },
2534 {
2535 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2536 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2537 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002538 },
2539};
2540
2541#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2542
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002543static void
2544mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2545 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002546{
2547 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2548 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2549 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2550 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2551 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2552 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002553 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002554
2555 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2556 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2557 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2558 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2559 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002560 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002561}
2562
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002563static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002564{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002565 int i;
2566
2567 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2568 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002569 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2570 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002571 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002572}
2573
2574static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002575 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002576{
2577 u32 speed = SPEED_UNKNOWN;
2578 u8 duplex = DUPLEX_UNKNOWN;
2579 int i;
2580
2581 if (!carrier_ok)
2582 goto out;
2583
2584 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2585 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2586 speed = mlxsw_sp_port_link_mode[i].speed;
2587 duplex = DUPLEX_FULL;
2588 break;
2589 }
2590 }
2591out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002592 cmd->base.speed = speed;
2593 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002594}
2595
2596static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2597{
2598 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2599 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2600 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2601 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2602 return PORT_FIBRE;
2603
2604 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2605 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2606 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2607 return PORT_DA;
2608
2609 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2610 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2611 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2612 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2613 return PORT_NONE;
2614
2615 return PORT_OTHER;
2616}
2617
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002618static u32
2619mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002620{
2621 u32 ptys_proto = 0;
2622 int i;
2623
2624 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002625 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2626 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002627 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2628 }
2629 return ptys_proto;
2630}
2631
2632static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2633{
2634 u32 ptys_proto = 0;
2635 int i;
2636
2637 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2638 if (speed == mlxsw_sp_port_link_mode[i].speed)
2639 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2640 }
2641 return ptys_proto;
2642}
2643
Ido Schimmel18f1e702016-02-26 17:32:31 +01002644static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2645{
2646 u32 ptys_proto = 0;
2647 int i;
2648
2649 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2650 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2651 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2652 }
2653 return ptys_proto;
2654}
2655
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002656static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2657 struct ethtool_link_ksettings *cmd)
2658{
2659 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2660 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2661 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2662
2663 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2664 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2665}
2666
2667static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2668 struct ethtool_link_ksettings *cmd)
2669{
2670 if (!autoneg)
2671 return;
2672
2673 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2674 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2675}
2676
2677static void
2678mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2679 struct ethtool_link_ksettings *cmd)
2680{
2681 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2682 return;
2683
2684 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2685 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2686}
2687
2688static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2689 struct ethtool_link_ksettings *cmd)
2690{
2691 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2692 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2693 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2694 char ptys_pl[MLXSW_REG_PTYS_LEN];
2695 u8 autoneg_status;
2696 bool autoneg;
2697 int err;
2698
2699 autoneg = mlxsw_sp_port->link.autoneg;
Elad Raz401c8b42016-10-28 21:35:52 +02002700 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002701 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2702 if (err)
2703 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002704 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2705 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002706
2707 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2708
2709 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2710
2711 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2712 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2713 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2714
2715 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2716 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2717 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2718 cmd);
2719
2720 return 0;
2721}
2722
2723static int
2724mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2725 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002726{
2727 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2728 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2729 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002730 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002731 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002732 int err;
2733
Elad Raz401c8b42016-10-28 21:35:52 +02002734 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002735 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002736 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002737 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002738 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002739
2740 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2741 eth_proto_new = autoneg ?
2742 mlxsw_sp_to_ptys_advert_link(cmd) :
2743 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002744
2745 eth_proto_new = eth_proto_new & eth_proto_cap;
2746 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002747 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002748 return -EINVAL;
2749 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002750
Elad Raz401c8b42016-10-28 21:35:52 +02002751 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2752 eth_proto_new);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002753 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002754 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002755 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002756
Ido Schimmel6277d462016-07-15 11:14:58 +02002757 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002758 return 0;
2759
Ido Schimmel0c83f882016-09-12 13:26:23 +02002760 mlxsw_sp_port->link.autoneg = autoneg;
2761
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002762 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2763 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002764
2765 return 0;
2766}
2767
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002768static int mlxsw_sp_flash_device(struct net_device *dev,
2769 struct ethtool_flash *flash)
2770{
2771 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2772 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2773 const struct firmware *firmware;
2774 int err;
2775
2776 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2777 return -EOPNOTSUPP;
2778
2779 dev_hold(dev);
2780 rtnl_unlock();
2781
2782 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2783 if (err)
2784 goto out;
2785 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2786 release_firmware(firmware);
2787out:
2788 rtnl_lock();
2789 dev_put(dev);
2790 return err;
2791}
2792
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002793#define MLXSW_SP_I2C_ADDR_LOW 0x50
2794#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2795#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002796
2797static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2798 u16 offset, u16 size, void *data,
2799 unsigned int *p_read_size)
2800{
2801 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2802 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2803 char mcia_pl[MLXSW_REG_MCIA_LEN];
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002804 u16 i2c_addr;
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002805 int status;
2806 int err;
2807
2808 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002809
2810 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2811 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2812 /* Cross pages read, read until offset 256 in low page */
2813 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2814
2815 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2816 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2817 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2818 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2819 }
2820
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002821 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002822 0, 0, offset, size, i2c_addr);
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002823
2824 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2825 if (err)
2826 return err;
2827
2828 status = mlxsw_reg_mcia_status_get(mcia_pl);
2829 if (status)
2830 return -EIO;
2831
2832 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2833 memcpy(data, eeprom_tmp, size);
2834 *p_read_size = size;
2835
2836 return 0;
2837}
2838
2839enum mlxsw_sp_eeprom_module_info_rev_id {
2840 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2841 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2842 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2843};
2844
2845enum mlxsw_sp_eeprom_module_info_id {
2846 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2847 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2848 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2849 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2850};
2851
2852enum mlxsw_sp_eeprom_module_info {
2853 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2854 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2855 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2856};
2857
2858static int mlxsw_sp_get_module_info(struct net_device *netdev,
2859 struct ethtool_modinfo *modinfo)
2860{
2861 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2862 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2863 u8 module_rev_id, module_id;
2864 unsigned int read_size;
2865 int err;
2866
2867 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2868 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2869 module_info, &read_size);
2870 if (err)
2871 return err;
2872
2873 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2874 return -EIO;
2875
2876 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2877 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2878
2879 switch (module_id) {
2880 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2881 modinfo->type = ETH_MODULE_SFF_8436;
2882 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2883 break;
2884 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2885 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2886 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2887 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2888 modinfo->type = ETH_MODULE_SFF_8636;
2889 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2890 } else {
2891 modinfo->type = ETH_MODULE_SFF_8436;
2892 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2893 }
2894 break;
2895 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2896 modinfo->type = ETH_MODULE_SFF_8472;
2897 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2898 break;
2899 default:
2900 return -EINVAL;
2901 }
2902
2903 return 0;
2904}
2905
2906static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2907 struct ethtool_eeprom *ee,
2908 u8 *data)
2909{
2910 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2911 int offset = ee->offset;
2912 unsigned int read_size;
2913 int i = 0;
2914 int err;
2915
2916 if (!ee->len)
2917 return -EINVAL;
2918
2919 memset(data, 0, ee->len);
2920
2921 while (i < ee->len) {
2922 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2923 ee->len - i, data + i,
2924 &read_size);
2925 if (err) {
2926 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2927 return err;
2928 }
2929
2930 i += read_size;
2931 offset += read_size;
2932 }
2933
2934 return 0;
2935}
2936
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002937static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2938 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2939 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002940 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2941 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002942 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002943 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002944 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2945 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002946 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2947 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002948 .flash_device = mlxsw_sp_flash_device,
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002949 .get_module_info = mlxsw_sp_get_module_info,
2950 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002951};
2952
Ido Schimmel18f1e702016-02-26 17:32:31 +01002953static int
2954mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2955{
2956 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2957 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2958 char ptys_pl[MLXSW_REG_PTYS_LEN];
2959 u32 eth_proto_admin;
2960
2961 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002962 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2963 eth_proto_admin);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002964 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2965}
2966
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002967int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2968 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2969 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002970{
2971 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2972 char qeec_pl[MLXSW_REG_QEEC_LEN];
2973
2974 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2975 next_index);
2976 mlxsw_reg_qeec_de_set(qeec_pl, true);
2977 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2978 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2979 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2980}
2981
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002982int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2983 enum mlxsw_reg_qeec_hr hr, u8 index,
2984 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002985{
2986 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2987 char qeec_pl[MLXSW_REG_QEEC_LEN];
2988
2989 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2990 next_index);
2991 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2992 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2993 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2994}
2995
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002996int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2997 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002998{
2999 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3000 char qtct_pl[MLXSW_REG_QTCT_LEN];
3001
3002 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
3003 tclass);
3004 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
3005}
3006
3007static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
3008{
3009 int err, i;
3010
3011 /* Setup the elements hierarcy, so that each TC is linked to
3012 * one subgroup, which are all member in the same group.
3013 */
3014 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3015 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
3016 0);
3017 if (err)
3018 return err;
3019 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3020 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3021 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
3022 0, false, 0);
3023 if (err)
3024 return err;
3025 }
3026 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3027 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3028 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
3029 false, 0);
3030 if (err)
3031 return err;
3032 }
3033
3034 /* Make sure the max shaper is disabled in all hierarcies that
3035 * support it.
3036 */
3037 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3038 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
3039 MLXSW_REG_QEEC_MAS_DIS);
3040 if (err)
3041 return err;
3042 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3043 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3044 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3045 i, 0,
3046 MLXSW_REG_QEEC_MAS_DIS);
3047 if (err)
3048 return err;
3049 }
3050 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3051 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3052 MLXSW_REG_QEEC_HIERARCY_TC,
3053 i, i,
3054 MLXSW_REG_QEEC_MAS_DIS);
3055 if (err)
3056 return err;
3057 }
3058
3059 /* Map all priorities to traffic class 0. */
3060 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3061 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
3062 if (err)
3063 return err;
3064 }
3065
3066 return 0;
3067}
3068
Ido Schimmel5b153852017-06-08 08:47:44 +02003069static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
3070 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003071{
Ido Schimmelc57529e2017-05-26 08:37:31 +02003072 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003073 struct mlxsw_sp_port *mlxsw_sp_port;
3074 struct net_device *dev;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003075 int err;
3076
Ido Schimmel5b153852017-06-08 08:47:44 +02003077 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
3078 if (err) {
3079 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
3080 local_port);
3081 return err;
3082 }
3083
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003084 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
Ido Schimmel5b153852017-06-08 08:47:44 +02003085 if (!dev) {
3086 err = -ENOMEM;
3087 goto err_alloc_etherdev;
3088 }
Jiri Pirkof20a91f2016-10-27 15:13:00 +02003089 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003090 mlxsw_sp_port = netdev_priv(dev);
3091 mlxsw_sp_port->dev = dev;
3092 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
3093 mlxsw_sp_port->local_port = local_port;
Ido Schimmelc57529e2017-05-26 08:37:31 +02003094 mlxsw_sp_port->pvid = 1;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003095 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02003096 mlxsw_sp_port->mapping.module = module;
3097 mlxsw_sp_port->mapping.width = width;
3098 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02003099 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02003100 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02003101 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003102
3103 mlxsw_sp_port->pcpu_stats =
3104 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
3105 if (!mlxsw_sp_port->pcpu_stats) {
3106 err = -ENOMEM;
3107 goto err_alloc_stats;
3108 }
3109
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003110 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
3111 GFP_KERNEL);
3112 if (!mlxsw_sp_port->sample) {
3113 err = -ENOMEM;
3114 goto err_alloc_sample;
3115 }
3116
Nogah Frankel9deef432017-10-26 10:55:32 +02003117 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02003118 &update_stats_cache);
3119
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003120 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
3121 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
3122
Ido Schimmel2e915e02017-06-08 08:47:45 +02003123 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
Ido Schimmel5b153852017-06-08 08:47:44 +02003124 if (err) {
3125 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
3126 mlxsw_sp_port->local_port);
3127 goto err_port_module_map;
3128 }
3129
Ido Schimmel3247ff22016-09-08 08:16:02 +02003130 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
3131 if (err) {
3132 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
3133 mlxsw_sp_port->local_port);
3134 goto err_port_swid_set;
3135 }
3136
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003137 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
3138 if (err) {
3139 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
3140 mlxsw_sp_port->local_port);
3141 goto err_dev_addr_init;
3142 }
3143
3144 netif_carrier_off(dev);
3145
3146 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02003147 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
3148 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003149
Jarod Wilsond894be52016-10-20 13:55:16 -04003150 dev->min_mtu = 0;
3151 dev->max_mtu = ETH_MAX_MTU;
3152
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003153 /* Each packet needs to have a Tx header (metadata) on top all other
3154 * headers.
3155 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02003156 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003157
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003158 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
3159 if (err) {
3160 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
3161 mlxsw_sp_port->local_port);
3162 goto err_port_system_port_mapping_set;
3163 }
3164
Ido Schimmel18f1e702016-02-26 17:32:31 +01003165 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
3166 if (err) {
3167 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
3168 mlxsw_sp_port->local_port);
3169 goto err_port_speed_by_width_set;
3170 }
3171
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003172 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
3173 if (err) {
3174 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
3175 mlxsw_sp_port->local_port);
3176 goto err_port_mtu_set;
3177 }
3178
3179 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3180 if (err)
3181 goto err_port_admin_status_set;
3182
3183 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
3184 if (err) {
3185 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
3186 mlxsw_sp_port->local_port);
3187 goto err_port_buffers_init;
3188 }
3189
Ido Schimmel90183b92016-04-06 17:10:08 +02003190 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
3191 if (err) {
3192 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
3193 mlxsw_sp_port->local_port);
3194 goto err_port_ets_init;
3195 }
3196
Ido Schimmelf00817d2016-04-06 17:10:09 +02003197 /* ETS and buffers must be initialized before DCB. */
3198 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
3199 if (err) {
3200 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
3201 mlxsw_sp_port->local_port);
3202 goto err_port_dcb_init;
3203 }
3204
Ido Schimmela1107482017-05-26 08:37:39 +02003205 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
Ido Schimmel45a4a162017-05-16 19:38:35 +02003206 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003207 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
Ido Schimmel45a4a162017-05-16 19:38:35 +02003208 mlxsw_sp_port->local_port);
Ido Schimmela1107482017-05-26 08:37:39 +02003209 goto err_port_fids_init;
Ido Schimmel45a4a162017-05-16 19:38:35 +02003210 }
3211
Nogah Frankel371b4372018-01-10 14:59:57 +01003212 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
3213 if (err) {
3214 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
3215 mlxsw_sp_port->local_port);
3216 goto err_port_qdiscs_init;
3217 }
3218
Ido Schimmelc57529e2017-05-26 08:37:31 +02003219 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
3220 if (IS_ERR(mlxsw_sp_port_vlan)) {
3221 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
Ido Schimmel05978482016-08-17 16:39:30 +02003222 mlxsw_sp_port->local_port);
Wei Yongjund86fd112017-11-06 11:11:28 +00003223 err = PTR_ERR(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003224 goto err_port_vlan_get;
Ido Schimmel05978482016-08-17 16:39:30 +02003225 }
3226
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003227 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02003228 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003229 err = register_netdev(dev);
3230 if (err) {
3231 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3232 mlxsw_sp_port->local_port);
3233 goto err_register_netdev;
3234 }
3235
Elad Razd808c7e2016-10-28 21:35:57 +02003236 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3237 mlxsw_sp_port, dev, mlxsw_sp_port->split,
3238 module);
Nogah Frankel9deef432017-10-26 10:55:32 +02003239 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003240 return 0;
3241
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003242err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02003243 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02003244 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003245 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
3246err_port_vlan_get:
Nogah Frankel371b4372018-01-10 14:59:57 +01003247 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3248err_port_qdiscs_init:
Ido Schimmela1107482017-05-26 08:37:39 +02003249 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3250err_port_fids_init:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03003251 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02003252err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02003253err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003254err_port_buffers_init:
3255err_port_admin_status_set:
3256err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01003257err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003258err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003259err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02003260 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3261err_port_swid_set:
Ido Schimmel2e915e02017-06-08 08:47:45 +02003262 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Ido Schimmel5b153852017-06-08 08:47:44 +02003263err_port_module_map:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003264 kfree(mlxsw_sp_port->sample);
3265err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003266 free_percpu(mlxsw_sp_port->pcpu_stats);
3267err_alloc_stats:
3268 free_netdev(dev);
Ido Schimmel5b153852017-06-08 08:47:44 +02003269err_alloc_etherdev:
Jiri Pirko67963a32016-10-28 21:35:55 +02003270 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3271 return err;
3272}
3273
Ido Schimmel5b153852017-06-08 08:47:44 +02003274static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003275{
3276 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3277
Nogah Frankel9deef432017-10-26 10:55:32 +02003278 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02003279 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003280 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02003281 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02003282 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003283 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Nogah Frankel371b4372018-01-10 14:59:57 +01003284 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
Ido Schimmela1107482017-05-26 08:37:39 +02003285 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02003286 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01003287 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
Ido Schimmel2e915e02017-06-08 08:47:45 +02003288 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003289 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01003290 free_percpu(mlxsw_sp_port->pcpu_stats);
Ido Schimmel31a08a52017-05-26 08:37:26 +02003291 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003292 free_netdev(mlxsw_sp_port->dev);
Jiri Pirko67963a32016-10-28 21:35:55 +02003293 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3294}
3295
Jiri Pirkof83e2102016-10-28 21:35:49 +02003296static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3297{
3298 return mlxsw_sp->ports[local_port] != NULL;
3299}
3300
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003301static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3302{
3303 int i;
3304
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003305 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003306 if (mlxsw_sp_port_created(mlxsw_sp, i))
3307 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003308 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003309 kfree(mlxsw_sp->ports);
3310}
3311
3312static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3313{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003314 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02003315 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003316 size_t alloc_size;
3317 int i;
3318 int err;
3319
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003320 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003321 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3322 if (!mlxsw_sp->ports)
3323 return -ENOMEM;
3324
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003325 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3326 GFP_KERNEL);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003327 if (!mlxsw_sp->port_to_module) {
3328 err = -ENOMEM;
3329 goto err_port_to_module_alloc;
3330 }
3331
3332 for (i = 1; i < max_ports; i++) {
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003333 /* Mark as invalid */
3334 mlxsw_sp->port_to_module[i] = -1;
3335
Ido Schimmel558c2d52016-02-26 17:32:29 +01003336 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003337 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01003338 if (err)
3339 goto err_port_module_info_get;
3340 if (!width)
3341 continue;
3342 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02003343 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3344 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003345 if (err)
3346 goto err_port_create;
3347 }
3348 return 0;
3349
3350err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01003351err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003352 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003353 if (mlxsw_sp_port_created(mlxsw_sp, i))
3354 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003355 kfree(mlxsw_sp->port_to_module);
3356err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003357 kfree(mlxsw_sp->ports);
3358 return err;
3359}
3360
Ido Schimmel18f1e702016-02-26 17:32:31 +01003361static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3362{
3363 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3364
3365 return local_port - offset;
3366}
3367
Ido Schimmelbe945352016-06-09 09:51:39 +02003368static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3369 u8 module, unsigned int count)
3370{
3371 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3372 int err, i;
3373
3374 for (i = 0; i < count; i++) {
Ido Schimmelbe945352016-06-09 09:51:39 +02003375 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02003376 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02003377 if (err)
3378 goto err_port_create;
3379 }
3380
3381 return 0;
3382
3383err_port_create:
3384 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003385 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3386 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02003387 return err;
3388}
3389
3390static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3391 u8 base_port, unsigned int count)
3392{
3393 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3394 int i;
3395
3396 /* Split by four means we need to re-create two ports, otherwise
3397 * only one.
3398 */
3399 count = count / 2;
3400
3401 for (i = 0; i < count; i++) {
3402 local_port = base_port + i * 2;
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003403 if (mlxsw_sp->port_to_module[local_port] < 0)
3404 continue;
Ido Schimmelbe945352016-06-09 09:51:39 +02003405 module = mlxsw_sp->port_to_module[local_port];
3406
Ido Schimmelbe945352016-06-09 09:51:39 +02003407 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003408 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003409 }
3410}
3411
Jiri Pirkob2f10572016-04-08 19:11:23 +02003412static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3413 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003414{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003415 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003416 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003417 u8 module, cur_width, base_port;
3418 int i;
3419 int err;
3420
3421 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3422 if (!mlxsw_sp_port) {
3423 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3424 local_port);
3425 return -EINVAL;
3426 }
3427
Ido Schimmeld664b412016-06-09 09:51:40 +02003428 module = mlxsw_sp_port->mapping.module;
3429 cur_width = mlxsw_sp_port->mapping.width;
3430
Ido Schimmel18f1e702016-02-26 17:32:31 +01003431 if (count != 2 && count != 4) {
3432 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3433 return -EINVAL;
3434 }
3435
Ido Schimmel18f1e702016-02-26 17:32:31 +01003436 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3437 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3438 return -EINVAL;
3439 }
3440
3441 /* Make sure we have enough slave (even) ports for the split. */
3442 if (count == 2) {
3443 base_port = local_port;
3444 if (mlxsw_sp->ports[base_port + 1]) {
3445 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3446 return -EINVAL;
3447 }
3448 } else {
3449 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3450 if (mlxsw_sp->ports[base_port + 1] ||
3451 mlxsw_sp->ports[base_port + 3]) {
3452 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3453 return -EINVAL;
3454 }
3455 }
3456
3457 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003458 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3459 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003460
Ido Schimmelbe945352016-06-09 09:51:39 +02003461 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3462 if (err) {
3463 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3464 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003465 }
3466
3467 return 0;
3468
Ido Schimmelbe945352016-06-09 09:51:39 +02003469err_port_split_create:
3470 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003471 return err;
3472}
3473
Jiri Pirkob2f10572016-04-08 19:11:23 +02003474static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003475{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003476 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003477 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003478 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003479 unsigned int count;
3480 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003481
3482 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3483 if (!mlxsw_sp_port) {
3484 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3485 local_port);
3486 return -EINVAL;
3487 }
3488
3489 if (!mlxsw_sp_port->split) {
3490 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3491 return -EINVAL;
3492 }
3493
Ido Schimmeld664b412016-06-09 09:51:40 +02003494 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003495 count = cur_width == 1 ? 4 : 2;
3496
3497 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3498
3499 /* Determine which ports to remove. */
3500 if (count == 2 && local_port >= base_port + 2)
3501 base_port = base_port + 2;
3502
3503 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003504 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3505 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003506
Ido Schimmelbe945352016-06-09 09:51:39 +02003507 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003508
3509 return 0;
3510}
3511
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003512static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3513 char *pude_pl, void *priv)
3514{
3515 struct mlxsw_sp *mlxsw_sp = priv;
3516 struct mlxsw_sp_port *mlxsw_sp_port;
3517 enum mlxsw_reg_pude_oper_status status;
3518 u8 local_port;
3519
3520 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3521 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003522 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003523 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003524
3525 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3526 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3527 netdev_info(mlxsw_sp_port->dev, "link up\n");
3528 netif_carrier_on(mlxsw_sp_port->dev);
3529 } else {
3530 netdev_info(mlxsw_sp_port->dev, "link down\n");
3531 netif_carrier_off(mlxsw_sp_port->dev);
3532 }
3533}
3534
Nogah Frankel14eeda92016-11-25 10:33:32 +01003535static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3536 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003537{
3538 struct mlxsw_sp *mlxsw_sp = priv;
3539 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3540 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3541
3542 if (unlikely(!mlxsw_sp_port)) {
3543 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3544 local_port);
3545 return;
3546 }
3547
3548 skb->dev = mlxsw_sp_port->dev;
3549
3550 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3551 u64_stats_update_begin(&pcpu_stats->syncp);
3552 pcpu_stats->rx_packets++;
3553 pcpu_stats->rx_bytes += skb->len;
3554 u64_stats_update_end(&pcpu_stats->syncp);
3555
3556 skb->protocol = eth_type_trans(skb, skb->dev);
3557 netif_receive_skb(skb);
3558}
3559
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003560static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3561 void *priv)
3562{
3563 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003564 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003565}
3566
Yotam Gigia0040c82017-10-03 09:58:10 +02003567static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3568 u8 local_port, void *priv)
3569{
3570 skb->offload_mr_fwd_mark = 1;
3571 skb->offload_fwd_mark = 1;
3572 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3573}
3574
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003575static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3576 void *priv)
3577{
3578 struct mlxsw_sp *mlxsw_sp = priv;
3579 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3580 struct psample_group *psample_group;
3581 u32 size;
3582
3583 if (unlikely(!mlxsw_sp_port)) {
3584 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3585 local_port);
3586 goto out;
3587 }
3588 if (unlikely(!mlxsw_sp_port->sample)) {
3589 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3590 local_port);
3591 goto out;
3592 }
3593
3594 size = mlxsw_sp_port->sample->truncate ?
3595 mlxsw_sp_port->sample->trunc_size : skb->len;
3596
3597 rcu_read_lock();
3598 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3599 if (!psample_group)
3600 goto out_unlock;
3601 psample_sample_packet(psample_group, skb, size,
3602 mlxsw_sp_port->dev->ifindex, 0,
3603 mlxsw_sp_port->sample->rate);
3604out_unlock:
3605 rcu_read_unlock();
3606out:
3607 consume_skb(skb);
3608}
3609
Nogah Frankel117b0da2016-11-25 10:33:44 +01003610#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003611 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003612 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003613
Nogah Frankel117b0da2016-11-25 10:33:44 +01003614#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003615 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003616 _is_ctrl, SP_##_trap_group, DISCARD)
3617
Yotam Gigia0040c82017-10-03 09:58:10 +02003618#define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3619 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3620 _is_ctrl, SP_##_trap_group, DISCARD)
3621
Nogah Frankel117b0da2016-11-25 10:33:44 +01003622#define MLXSW_SP_EVENTL(_func, _trap_id) \
3623 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003624
Nogah Frankel45449132016-11-25 10:33:35 +01003625static const struct mlxsw_listener mlxsw_sp_listener[] = {
3626 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003627 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003628 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003629 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3630 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3631 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3632 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3633 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3634 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3635 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3636 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3637 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3638 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3639 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003640 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003641 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3642 false),
3643 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3644 false),
3645 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3646 false),
3647 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3648 false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003649 /* L3 traps */
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003650 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3651 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3652 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003653 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003654 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3655 false),
3656 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3657 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3658 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3659 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3660 false),
3661 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3662 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3663 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003664 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003665 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3666 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3667 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3668 false),
3669 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3670 false),
3671 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3672 false),
3673 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3674 false),
3675 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3676 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3677 false),
3678 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3679 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
Ido Schimmel7607dd32017-07-17 14:15:30 +02003680 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003681 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
Petr Machata86484de2017-09-02 23:49:27 +02003682 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003683 /* PKT Sample trap */
3684 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
Jiri Pirko0db7b382017-06-06 14:12:05 +02003685 false, SP_IP2ME, DISCARD),
3686 /* ACL trap */
3687 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
Yotam Gigib48cfc82017-09-19 10:00:20 +02003688 /* Multicast Router Traps */
3689 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3690 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3691 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
Yotam Gigia0040c82017-10-03 09:58:10 +02003692 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003693};
3694
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003695static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3696{
3697 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3698 enum mlxsw_reg_qpcr_ir_units ir_units;
3699 int max_cpu_policers;
3700 bool is_bytes;
3701 u8 burst_size;
3702 u32 rate;
3703 int i, err;
3704
3705 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3706 return -EIO;
3707
3708 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3709
3710 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3711 for (i = 0; i < max_cpu_policers; i++) {
3712 is_bytes = false;
3713 switch (i) {
3714 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3715 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3716 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3717 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003718 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3719 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003720 rate = 128;
3721 burst_size = 7;
3722 break;
3723 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003724 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003725 rate = 16 * 1024;
3726 burst_size = 10;
3727 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003728 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003729 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3730 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003731 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003732 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3733 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003734 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003735 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003736 rate = 1024;
3737 burst_size = 7;
3738 break;
3739 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3740 is_bytes = true;
3741 rate = 4 * 1024;
3742 burst_size = 4;
3743 break;
3744 default:
3745 continue;
3746 }
3747
3748 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3749 burst_size);
3750 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3751 if (err)
3752 return err;
3753 }
3754
3755 return 0;
3756}
3757
Nogah Frankel579c82e2016-11-25 10:33:42 +01003758static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003759{
3760 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003761 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003762 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003763 int max_trap_groups;
3764 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003765 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003766 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003767
3768 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3769 return -EIO;
3770
3771 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003772 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003773
3774 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003775 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003776 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003777 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3778 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3779 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3780 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003781 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003782 priority = 5;
3783 tc = 5;
3784 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003785 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003786 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3787 priority = 4;
3788 tc = 4;
3789 break;
3790 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3791 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003792 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003793 priority = 3;
3794 tc = 3;
3795 break;
3796 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003797 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003798 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003799 priority = 2;
3800 tc = 2;
3801 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003802 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003803 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3804 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003805 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003806 priority = 1;
3807 tc = 1;
3808 break;
3809 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003810 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3811 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003812 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003813 break;
3814 default:
3815 continue;
3816 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003817
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003818 if (max_cpu_policers <= policer_id &&
3819 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3820 return -EIO;
3821
3822 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003823 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3824 if (err)
3825 return err;
3826 }
3827
3828 return 0;
3829}
3830
3831static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3832{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003833 int i;
3834 int err;
3835
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003836 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3837 if (err)
3838 return err;
3839
Nogah Frankel579c82e2016-11-25 10:33:42 +01003840 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003841 if (err)
3842 return err;
3843
Nogah Frankel45449132016-11-25 10:33:35 +01003844 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003845 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003846 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003847 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003848 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003849 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003850
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003851 }
3852 return 0;
3853
Nogah Frankel45449132016-11-25 10:33:35 +01003854err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003855 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003856 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003857 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003858 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003859 }
3860 return err;
3861}
3862
3863static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3864{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003865 int i;
3866
Nogah Frankel45449132016-11-25 10:33:35 +01003867 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003868 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003869 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003870 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003871 }
3872}
3873
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003874static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3875{
3876 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003877 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003878
3879 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3880 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3881 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3882 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3883 MLXSW_REG_SLCR_LAG_HASH_SIP |
3884 MLXSW_REG_SLCR_LAG_HASH_DIP |
3885 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3886 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3887 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003888 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3889 if (err)
3890 return err;
3891
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003892 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3893 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003894 return -EIO;
3895
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003896 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003897 sizeof(struct mlxsw_sp_upper),
3898 GFP_KERNEL);
3899 if (!mlxsw_sp->lags)
3900 return -ENOMEM;
3901
3902 return 0;
3903}
3904
3905static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3906{
3907 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003908}
3909
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003910static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3911{
3912 char htgt_pl[MLXSW_REG_HTGT_LEN];
3913
Nogah Frankel579c82e2016-11-25 10:33:42 +01003914 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3915 MLXSW_REG_HTGT_INVALID_POLICER,
3916 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3917 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003918 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3919}
3920
Petr Machatac30f5d02017-10-16 16:26:35 +02003921static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3922 unsigned long event, void *ptr);
3923
Jiri Pirkob2f10572016-04-08 19:11:23 +02003924static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003925 const struct mlxsw_bus_info *mlxsw_bus_info)
3926{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003927 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003928 int err;
3929
3930 mlxsw_sp->core = mlxsw_core;
3931 mlxsw_sp->bus_info = mlxsw_bus_info;
3932
Yotam Gigi6b742192017-05-23 21:56:29 +02003933 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3934 if (err) {
3935 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3936 return err;
3937 }
3938
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003939 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3940 if (err) {
3941 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3942 return err;
3943 }
3944
Ido Schimmela875a2e2017-10-22 23:11:44 +02003945 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3946 if (err) {
3947 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3948 return err;
3949 }
3950
Ido Schimmela1107482017-05-26 08:37:39 +02003951 err = mlxsw_sp_fids_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003952 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003953 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
Ido Schimmela875a2e2017-10-22 23:11:44 +02003954 goto err_fids_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003955 }
3956
Ido Schimmela1107482017-05-26 08:37:39 +02003957 err = mlxsw_sp_traps_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003958 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003959 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3960 goto err_traps_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003961 }
3962
3963 err = mlxsw_sp_buffers_init(mlxsw_sp);
3964 if (err) {
3965 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3966 goto err_buffers_init;
3967 }
3968
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003969 err = mlxsw_sp_lag_init(mlxsw_sp);
3970 if (err) {
3971 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3972 goto err_lag_init;
3973 }
3974
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003975 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3976 if (err) {
3977 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3978 goto err_switchdev_init;
3979 }
3980
Yotam Gigie2b2d352017-09-19 10:00:08 +02003981 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3982 if (err) {
3983 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3984 goto err_counter_pool_init;
3985 }
3986
Yotam Gigid3b939b2017-09-19 10:00:09 +02003987 err = mlxsw_sp_afa_init(mlxsw_sp);
3988 if (err) {
3989 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3990 goto err_afa_init;
3991 }
3992
Ido Schimmel464dce12016-07-02 11:00:15 +02003993 err = mlxsw_sp_router_init(mlxsw_sp);
3994 if (err) {
3995 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3996 goto err_router_init;
3997 }
3998
Petr Machatac30f5d02017-10-16 16:26:35 +02003999 /* Initialize netdevice notifier after router is initialized, so that
4000 * the event handler can use router structures.
4001 */
4002 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
4003 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4004 if (err) {
4005 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
4006 goto err_netdev_notifier;
4007 }
4008
Yotam Gigi763b4b72016-07-21 12:03:17 +02004009 err = mlxsw_sp_span_init(mlxsw_sp);
4010 if (err) {
4011 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
4012 goto err_span_init;
4013 }
4014
Jiri Pirko22a67762017-02-03 10:29:07 +01004015 err = mlxsw_sp_acl_init(mlxsw_sp);
4016 if (err) {
4017 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
4018 goto err_acl_init;
4019 }
4020
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02004021 err = mlxsw_sp_dpipe_init(mlxsw_sp);
4022 if (err) {
4023 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
4024 goto err_dpipe_init;
4025 }
4026
Ido Schimmelbbf2a472016-07-02 11:00:14 +02004027 err = mlxsw_sp_ports_create(mlxsw_sp);
4028 if (err) {
4029 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
4030 goto err_ports_create;
4031 }
4032
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004033 return 0;
4034
Ido Schimmelbbf2a472016-07-02 11:00:14 +02004035err_ports_create:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02004036 mlxsw_sp_dpipe_fini(mlxsw_sp);
4037err_dpipe_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01004038 mlxsw_sp_acl_fini(mlxsw_sp);
4039err_acl_init:
Yotam Gigi763b4b72016-07-21 12:03:17 +02004040 mlxsw_sp_span_fini(mlxsw_sp);
4041err_span_init:
Petr Machatac30f5d02017-10-16 16:26:35 +02004042 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4043err_netdev_notifier:
Ido Schimmel464dce12016-07-02 11:00:15 +02004044 mlxsw_sp_router_fini(mlxsw_sp);
4045err_router_init:
Yotam Gigid3b939b2017-09-19 10:00:09 +02004046 mlxsw_sp_afa_fini(mlxsw_sp);
4047err_afa_init:
Yotam Gigie2b2d352017-09-19 10:00:08 +02004048 mlxsw_sp_counter_pool_fini(mlxsw_sp);
4049err_counter_pool_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02004050 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004051err_switchdev_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02004052 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004053err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02004054 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004055err_buffers_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004056 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02004057err_traps_init:
4058 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02004059err_fids_init:
4060 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004061 return err;
4062}
4063
Jiri Pirkob2f10572016-04-08 19:11:23 +02004064static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004065{
Jiri Pirkob2f10572016-04-08 19:11:23 +02004066 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004067
Ido Schimmelbbf2a472016-07-02 11:00:14 +02004068 mlxsw_sp_ports_remove(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02004069 mlxsw_sp_dpipe_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01004070 mlxsw_sp_acl_fini(mlxsw_sp);
Yotam Gigi763b4b72016-07-21 12:03:17 +02004071 mlxsw_sp_span_fini(mlxsw_sp);
Petr Machatac30f5d02017-10-16 16:26:35 +02004072 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
Ido Schimmel464dce12016-07-02 11:00:15 +02004073 mlxsw_sp_router_fini(mlxsw_sp);
Yotam Gigid3b939b2017-09-19 10:00:09 +02004074 mlxsw_sp_afa_fini(mlxsw_sp);
Yotam Gigie2b2d352017-09-19 10:00:08 +02004075 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004076 mlxsw_sp_switchdev_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02004077 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02004078 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004079 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02004080 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02004081 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004082}
4083
Bhumika Goyal159fe882017-08-11 19:10:42 +05304084static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004085 .used_max_vepa_channels = 1,
4086 .max_vepa_channels = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004087 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01004088 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004089 .used_max_pgt = 1,
4090 .max_pgt = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004091 .used_flood_tables = 1,
4092 .used_flood_mode = 1,
4093 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01004094 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004095 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01004096 .max_fid_flood_tables = 3,
Ido Schimmela1107482017-05-26 08:37:39 +02004097 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004098 .used_max_ib_mc = 1,
4099 .max_ib_mc = 0,
4100 .used_max_pkey = 1,
4101 .max_pkey = 0,
Nogah Frankel403547d2016-09-20 11:16:52 +02004102 .used_kvd_split_data = 1,
4103 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
Ido Schimmelf11fbaf2017-10-22 23:11:49 +02004104 .kvd_hash_single_parts = 59,
4105 .kvd_hash_double_parts = 41,
Jiri Pirkoc6022422016-07-05 11:27:46 +02004106 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004107 .swid_config = {
4108 {
4109 .used_type = 1,
4110 .type = MLXSW_PORT_SWID_TYPE_ETH,
4111 }
4112 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02004113 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004114};
4115
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004116static bool
4117mlxsw_sp_resource_kvd_granularity_validate(struct netlink_ext_ack *extack,
4118 u64 size)
4119{
4120 const struct mlxsw_config_profile *profile;
4121
4122 profile = &mlxsw_sp_config_profile;
4123 if (size % profile->kvd_hash_granularity) {
4124 NL_SET_ERR_MSG_MOD(extack, "resource set with wrong granularity");
4125 return false;
4126 }
4127 return true;
4128}
4129
4130static int
4131mlxsw_sp_resource_kvd_size_validate(struct devlink *devlink, u64 size,
4132 struct netlink_ext_ack *extack)
4133{
4134 NL_SET_ERR_MSG_MOD(extack, "kvd size cannot be changed");
4135 return -EINVAL;
4136}
4137
4138static int
4139mlxsw_sp_resource_kvd_linear_size_validate(struct devlink *devlink, u64 size,
4140 struct netlink_ext_ack *extack)
4141{
4142 if (!mlxsw_sp_resource_kvd_granularity_validate(extack, size))
4143 return -EINVAL;
4144
4145 return 0;
4146}
4147
4148static int
4149mlxsw_sp_resource_kvd_hash_single_size_validate(struct devlink *devlink, u64 size,
4150 struct netlink_ext_ack *extack)
4151{
4152 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
4153
4154 if (!mlxsw_sp_resource_kvd_granularity_validate(extack, size))
4155 return -EINVAL;
4156
4157 if (size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE)) {
4158 NL_SET_ERR_MSG_MOD(extack, "hash single size is smaller than minimum");
4159 return -EINVAL;
4160 }
4161 return 0;
4162}
4163
4164static int
4165mlxsw_sp_resource_kvd_hash_double_size_validate(struct devlink *devlink, u64 size,
4166 struct netlink_ext_ack *extack)
4167{
4168 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
4169
4170 if (!mlxsw_sp_resource_kvd_granularity_validate(extack, size))
4171 return -EINVAL;
4172
4173 if (size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE)) {
4174 NL_SET_ERR_MSG_MOD(extack, "hash double size is smaller than minimum");
4175 return -EINVAL;
4176 }
4177 return 0;
4178}
4179
Arkadi Sharshevskyafadc262018-01-15 08:59:09 +01004180static u64 mlxsw_sp_resource_kvd_linear_occ_get(struct devlink *devlink)
4181{
4182 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
4183 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4184
4185 return mlxsw_sp_kvdl_occ_get(mlxsw_sp);
4186}
4187
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004188static struct devlink_resource_ops mlxsw_sp_resource_kvd_ops = {
4189 .size_validate = mlxsw_sp_resource_kvd_size_validate,
4190};
4191
4192static struct devlink_resource_ops mlxsw_sp_resource_kvd_linear_ops = {
4193 .size_validate = mlxsw_sp_resource_kvd_linear_size_validate,
Arkadi Sharshevskyafadc262018-01-15 08:59:09 +01004194 .occ_get = mlxsw_sp_resource_kvd_linear_occ_get,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004195};
4196
4197static struct devlink_resource_ops mlxsw_sp_resource_kvd_hash_single_ops = {
4198 .size_validate = mlxsw_sp_resource_kvd_hash_single_size_validate,
4199};
4200
4201static struct devlink_resource_ops mlxsw_sp_resource_kvd_hash_double_ops = {
4202 .size_validate = mlxsw_sp_resource_kvd_hash_double_size_validate,
4203};
4204
4205static struct devlink_resource_size_params mlxsw_sp_kvd_size_params;
4206static struct devlink_resource_size_params mlxsw_sp_linear_size_params;
4207static struct devlink_resource_size_params mlxsw_sp_hash_single_size_params;
4208static struct devlink_resource_size_params mlxsw_sp_hash_double_size_params;
4209
4210static void
4211mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core)
4212{
4213 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
4214 KVD_SINGLE_MIN_SIZE);
4215 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
4216 KVD_DOUBLE_MIN_SIZE);
4217 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4218 u32 linear_size_min = 0;
4219
4220 /* KVD top resource */
4221 mlxsw_sp_kvd_size_params.size_min = kvd_size;
4222 mlxsw_sp_kvd_size_params.size_max = kvd_size;
4223 mlxsw_sp_kvd_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
4224 mlxsw_sp_kvd_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
4225
4226 /* Linear part init */
4227 mlxsw_sp_linear_size_params.size_min = linear_size_min;
4228 mlxsw_sp_linear_size_params.size_max = kvd_size - single_size_min -
4229 double_size_min;
4230 mlxsw_sp_linear_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
4231 mlxsw_sp_linear_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
4232
4233 /* Hash double part init */
4234 mlxsw_sp_hash_double_size_params.size_min = double_size_min;
4235 mlxsw_sp_hash_double_size_params.size_max = kvd_size - single_size_min -
4236 linear_size_min;
4237 mlxsw_sp_hash_double_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
4238 mlxsw_sp_hash_double_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
4239
4240 /* Hash single part init */
4241 mlxsw_sp_hash_single_size_params.size_min = single_size_min;
4242 mlxsw_sp_hash_single_size_params.size_max = kvd_size - double_size_min -
4243 linear_size_min;
4244 mlxsw_sp_hash_single_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
4245 mlxsw_sp_hash_single_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
4246}
4247
4248static int mlxsw_sp_resources_register(struct mlxsw_core *mlxsw_core)
4249{
4250 struct devlink *devlink = priv_to_devlink(mlxsw_core);
4251 u32 kvd_size, single_size, double_size, linear_size;
4252 const struct mlxsw_config_profile *profile;
4253 int err;
4254
4255 profile = &mlxsw_sp_config_profile;
4256 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
4257 return -EIO;
4258
4259 mlxsw_sp_resource_size_params_prepare(mlxsw_core);
4260 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4261 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
4262 true, kvd_size,
4263 MLXSW_SP_RESOURCE_KVD,
4264 DEVLINK_RESOURCE_ID_PARENT_TOP,
4265 &mlxsw_sp_kvd_size_params,
4266 &mlxsw_sp_resource_kvd_ops);
4267 if (err)
4268 return err;
4269
4270 linear_size = profile->kvd_linear_size;
4271 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
4272 false, linear_size,
4273 MLXSW_SP_RESOURCE_KVD_LINEAR,
4274 MLXSW_SP_RESOURCE_KVD,
4275 &mlxsw_sp_linear_size_params,
4276 &mlxsw_sp_resource_kvd_linear_ops);
4277 if (err)
4278 return err;
4279
4280 double_size = kvd_size - linear_size;
4281 double_size *= profile->kvd_hash_double_parts;
4282 double_size /= profile->kvd_hash_double_parts +
4283 profile->kvd_hash_single_parts;
4284 double_size = rounddown(double_size, profile->kvd_hash_granularity);
4285 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
4286 false, double_size,
4287 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4288 MLXSW_SP_RESOURCE_KVD,
4289 &mlxsw_sp_hash_double_size_params,
4290 &mlxsw_sp_resource_kvd_hash_double_ops);
4291 if (err)
4292 return err;
4293
4294 single_size = kvd_size - double_size - linear_size;
4295 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
4296 false, single_size,
4297 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4298 MLXSW_SP_RESOURCE_KVD,
4299 &mlxsw_sp_hash_single_size_params,
4300 &mlxsw_sp_resource_kvd_hash_single_ops);
4301 if (err)
4302 return err;
4303
4304 return 0;
4305}
4306
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01004307static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
4308 const struct mlxsw_config_profile *profile,
4309 u64 *p_single_size, u64 *p_double_size,
4310 u64 *p_linear_size)
4311{
4312 struct devlink *devlink = priv_to_devlink(mlxsw_core);
4313 u32 double_size;
4314 int err;
4315
4316 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4317 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
4318 !profile->used_kvd_split_data)
4319 return -EIO;
4320
4321 /* The hash part is what left of the kvd without the
4322 * linear part. It is split to the single size and
4323 * double size by the parts ratio from the profile.
4324 * Both sizes must be a multiplications of the
4325 * granularity from the profile. In case the user
4326 * provided the sizes they are obtained via devlink.
4327 */
4328 err = devlink_resource_size_get(devlink,
4329 MLXSW_SP_RESOURCE_KVD_LINEAR,
4330 p_linear_size);
4331 if (err)
4332 *p_linear_size = profile->kvd_linear_size;
4333
4334 err = devlink_resource_size_get(devlink,
4335 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4336 p_double_size);
4337 if (err) {
4338 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4339 *p_linear_size;
4340 double_size *= profile->kvd_hash_double_parts;
4341 double_size /= profile->kvd_hash_double_parts +
4342 profile->kvd_hash_single_parts;
4343 *p_double_size = rounddown(double_size,
4344 profile->kvd_hash_granularity);
4345 }
4346
4347 err = devlink_resource_size_get(devlink,
4348 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4349 p_single_size);
4350 if (err)
4351 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4352 *p_double_size - *p_linear_size;
4353
4354 /* Check results are legal. */
4355 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4356 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
4357 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
4358 return -EIO;
4359
4360 return 0;
4361}
4362
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004363static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02004364 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02004365 .priv_size = sizeof(struct mlxsw_sp),
4366 .init = mlxsw_sp_init,
4367 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01004368 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02004369 .port_split = mlxsw_sp_port_split,
4370 .port_unsplit = mlxsw_sp_port_unsplit,
4371 .sb_pool_get = mlxsw_sp_sb_pool_get,
4372 .sb_pool_set = mlxsw_sp_sb_pool_set,
4373 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
4374 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
4375 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
4376 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4377 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4378 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4379 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4380 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4381 .txhdr_construct = mlxsw_sp_txhdr_construct,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004382 .resources_register = mlxsw_sp_resources_register,
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01004383 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02004384 .txhdr_len = MLXSW_TXHDR_LEN,
4385 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004386};
4387
Jiri Pirko22a67762017-02-03 10:29:07 +01004388bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004389{
4390 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4391}
4392
Jiri Pirko1182e532017-03-06 21:25:20 +01004393static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07004394{
Jiri Pirko1182e532017-03-06 21:25:20 +01004395 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07004396 int ret = 0;
4397
4398 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01004399 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07004400 ret = 1;
4401 }
4402
4403 return ret;
4404}
4405
Ido Schimmelc57529e2017-05-26 08:37:31 +02004406struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004407{
Jiri Pirko1182e532017-03-06 21:25:20 +01004408 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004409
4410 if (mlxsw_sp_port_dev_check(dev))
4411 return netdev_priv(dev);
4412
Jiri Pirko1182e532017-03-06 21:25:20 +01004413 mlxsw_sp_port = NULL;
4414 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004415
Jiri Pirko1182e532017-03-06 21:25:20 +01004416 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004417}
4418
Ido Schimmel4724ba562017-03-10 08:53:39 +01004419struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004420{
4421 struct mlxsw_sp_port *mlxsw_sp_port;
4422
4423 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4424 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4425}
4426
Arkadi Sharshevskyaf0613782017-06-08 08:44:20 +02004427struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004428{
Jiri Pirko1182e532017-03-06 21:25:20 +01004429 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004430
4431 if (mlxsw_sp_port_dev_check(dev))
4432 return netdev_priv(dev);
4433
Jiri Pirko1182e532017-03-06 21:25:20 +01004434 mlxsw_sp_port = NULL;
4435 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4436 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004437
Jiri Pirko1182e532017-03-06 21:25:20 +01004438 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004439}
4440
4441struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4442{
4443 struct mlxsw_sp_port *mlxsw_sp_port;
4444
4445 rcu_read_lock();
4446 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4447 if (mlxsw_sp_port)
4448 dev_hold(mlxsw_sp_port->dev);
4449 rcu_read_unlock();
4450 return mlxsw_sp_port;
4451}
4452
4453void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4454{
4455 dev_put(mlxsw_sp_port->dev);
4456}
4457
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004458static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004459{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004460 char sldr_pl[MLXSW_REG_SLDR_LEN];
4461
4462 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4463 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4464}
4465
4466static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4467{
4468 char sldr_pl[MLXSW_REG_SLDR_LEN];
4469
4470 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4471 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4472}
4473
4474static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4475 u16 lag_id, u8 port_index)
4476{
4477 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4478 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4479
4480 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4481 lag_id, port_index);
4482 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4483}
4484
4485static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4486 u16 lag_id)
4487{
4488 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4489 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4490
4491 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4492 lag_id);
4493 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4494}
4495
4496static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4497 u16 lag_id)
4498{
4499 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4500 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4501
4502 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4503 lag_id);
4504 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4505}
4506
4507static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4508 u16 lag_id)
4509{
4510 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4511 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4512
4513 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4514 lag_id);
4515 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4516}
4517
4518static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4519 struct net_device *lag_dev,
4520 u16 *p_lag_id)
4521{
4522 struct mlxsw_sp_upper *lag;
4523 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004524 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004525 int i;
4526
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004527 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4528 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004529 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4530 if (lag->ref_count) {
4531 if (lag->dev == lag_dev) {
4532 *p_lag_id = i;
4533 return 0;
4534 }
4535 } else if (free_lag_id < 0) {
4536 free_lag_id = i;
4537 }
4538 }
4539 if (free_lag_id < 0)
4540 return -EBUSY;
4541 *p_lag_id = free_lag_id;
4542 return 0;
4543}
4544
4545static bool
4546mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4547 struct net_device *lag_dev,
David Aherne58376e2017-10-04 17:48:51 -07004548 struct netdev_lag_upper_info *lag_upper_info,
4549 struct netlink_ext_ack *extack)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004550{
4551 u16 lag_id;
4552
David Aherne58376e2017-10-04 17:48:51 -07004553 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
4554 NL_SET_ERR_MSG(extack,
4555 "spectrum: Exceeded number of supported LAG devices");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004556 return false;
David Aherne58376e2017-10-04 17:48:51 -07004557 }
4558 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
4559 NL_SET_ERR_MSG(extack,
4560 "spectrum: LAG device using unsupported Tx type");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004561 return false;
David Aherne58376e2017-10-04 17:48:51 -07004562 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004563 return true;
4564}
4565
4566static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4567 u16 lag_id, u8 *p_port_index)
4568{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004569 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004570 int i;
4571
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004572 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4573 MAX_LAG_MEMBERS);
4574 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004575 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4576 *p_port_index = i;
4577 return 0;
4578 }
4579 }
4580 return -EBUSY;
4581}
4582
4583static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4584 struct net_device *lag_dev)
4585{
4586 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004587 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004588 struct mlxsw_sp_upper *lag;
4589 u16 lag_id;
4590 u8 port_index;
4591 int err;
4592
4593 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4594 if (err)
4595 return err;
4596 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4597 if (!lag->ref_count) {
4598 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4599 if (err)
4600 return err;
4601 lag->dev = lag_dev;
4602 }
4603
4604 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4605 if (err)
4606 return err;
4607 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4608 if (err)
4609 goto err_col_port_add;
4610 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4611 if (err)
4612 goto err_col_port_enable;
4613
4614 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4615 mlxsw_sp_port->local_port);
4616 mlxsw_sp_port->lag_id = lag_id;
4617 mlxsw_sp_port->lagged = 1;
4618 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004619
Ido Schimmelc57529e2017-05-26 08:37:31 +02004620 /* Port is no longer usable as a router interface */
4621 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4622 if (mlxsw_sp_port_vlan->fid)
Ido Schimmela1107482017-05-26 08:37:39 +02004623 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004624
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004625 return 0;
4626
Ido Schimmel51554db2016-05-06 22:18:39 +02004627err_col_port_enable:
4628 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004629err_col_port_add:
4630 if (!lag->ref_count)
4631 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004632 return err;
4633}
4634
Ido Schimmel82e6db02016-06-20 23:04:04 +02004635static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4636 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004637{
4638 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004639 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004640 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004641
4642 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004643 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004644 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4645 WARN_ON(lag->ref_count == 0);
4646
Ido Schimmel82e6db02016-06-20 23:04:04 +02004647 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4648 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004649
Ido Schimmelc57529e2017-05-26 08:37:31 +02004650 /* Any VLANs configured on the port are no longer valid */
4651 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004652
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004653 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004654 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004655
4656 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4657 mlxsw_sp_port->local_port);
4658 mlxsw_sp_port->lagged = 0;
4659 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004660
Ido Schimmelc57529e2017-05-26 08:37:31 +02004661 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4662 /* Make sure untagged frames are allowed to ingress */
4663 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004664}
4665
Jiri Pirko74581202015-12-03 12:12:30 +01004666static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4667 u16 lag_id)
4668{
4669 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4670 char sldr_pl[MLXSW_REG_SLDR_LEN];
4671
4672 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4673 mlxsw_sp_port->local_port);
4674 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4675}
4676
4677static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4678 u16 lag_id)
4679{
4680 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4681 char sldr_pl[MLXSW_REG_SLDR_LEN];
4682
4683 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4684 mlxsw_sp_port->local_port);
4685 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4686}
4687
4688static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4689 bool lag_tx_enabled)
4690{
4691 if (lag_tx_enabled)
4692 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4693 mlxsw_sp_port->lag_id);
4694 else
4695 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4696 mlxsw_sp_port->lag_id);
4697}
4698
4699static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4700 struct netdev_lag_lower_state_info *info)
4701{
4702 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4703}
4704
Jiri Pirko2b94e582017-04-18 16:55:37 +02004705static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4706 bool enable)
4707{
4708 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4709 enum mlxsw_reg_spms_state spms_state;
4710 char *spms_pl;
4711 u16 vid;
4712 int err;
4713
4714 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4715 MLXSW_REG_SPMS_STATE_DISCARDING;
4716
4717 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4718 if (!spms_pl)
4719 return -ENOMEM;
4720 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4721
4722 for (vid = 0; vid < VLAN_N_VID; vid++)
4723 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4724
4725 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4726 kfree(spms_pl);
4727 return err;
4728}
4729
4730static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4731{
Yuval Mintzfccff082017-12-15 08:44:21 +01004732 u16 vid = 1;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004733 int err;
4734
Ido Schimmel4aafc362017-05-26 08:37:25 +02004735 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004736 if (err)
4737 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02004738 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4739 if (err)
4740 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004741 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4742 true, false);
4743 if (err)
4744 goto err_port_vlan_set;
Yuval Mintzfccff082017-12-15 08:44:21 +01004745
4746 for (; vid <= VLAN_N_VID - 1; vid++) {
4747 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4748 vid, false);
4749 if (err)
4750 goto err_vid_learning_set;
4751 }
4752
Jiri Pirko2b94e582017-04-18 16:55:37 +02004753 return 0;
4754
Yuval Mintzfccff082017-12-15 08:44:21 +01004755err_vid_learning_set:
4756 for (vid--; vid >= 1; vid--)
4757 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004758err_port_vlan_set:
4759 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004760err_port_stp_set:
4761 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004762 return err;
4763}
4764
4765static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4766{
Yuval Mintzfccff082017-12-15 08:44:21 +01004767 u16 vid;
4768
4769 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4770 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4771 vid, true);
4772
Jiri Pirko2b94e582017-04-18 16:55:37 +02004773 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4774 false, false);
4775 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004776 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004777}
4778
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004779static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4780 struct net_device *dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004781 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004782{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004783 struct netdev_notifier_changeupper_info *info;
4784 struct mlxsw_sp_port *mlxsw_sp_port;
David Aherne58376e2017-10-04 17:48:51 -07004785 struct netlink_ext_ack *extack;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004786 struct net_device *upper_dev;
4787 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004788 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004789
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004790 mlxsw_sp_port = netdev_priv(dev);
4791 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4792 info = ptr;
David Aherne58376e2017-10-04 17:48:51 -07004793 extack = netdev_notifier_info_to_extack(&info->info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004794
4795 switch (event) {
4796 case NETDEV_PRECHANGEUPPER:
4797 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004798 if (!is_vlan_dev(upper_dev) &&
4799 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004800 !netif_is_bridge_master(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004801 !netif_is_ovs_master(upper_dev)) {
4802 NL_SET_ERR_MSG(extack,
4803 "spectrum: Unknown upper device type");
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004804 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004805 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004806 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004807 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004808 if (netdev_has_any_upper_dev(upper_dev) &&
4809 (!netif_is_bridge_master(upper_dev) ||
4810 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4811 upper_dev))) {
David Aherne58376e2017-10-04 17:48:51 -07004812 NL_SET_ERR_MSG(extack,
4813 "spectrum: Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004814 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004815 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004816 if (netif_is_lag_master(upper_dev) &&
4817 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
David Aherne58376e2017-10-04 17:48:51 -07004818 info->upper_info, extack))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004819 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004820 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
4821 NL_SET_ERR_MSG(extack,
4822 "spectrum: Master device is a LAG master and this device has a VLAN");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004823 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004824 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004825 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004826 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
4827 NL_SET_ERR_MSG(extack,
4828 "spectrum: Can not put a VLAN on a LAG port");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004829 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004830 }
4831 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
4832 NL_SET_ERR_MSG(extack,
4833 "spectrum: Master device is an OVS master and this device has a VLAN");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004834 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004835 }
4836 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
4837 NL_SET_ERR_MSG(extack,
4838 "spectrum: Can not put a VLAN on an OVS port");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004839 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004840 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004841 break;
4842 case NETDEV_CHANGEUPPER:
4843 upper_dev = info->upper_dev;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004844 if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004845 if (info->linking)
4846 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004847 lower_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004848 upper_dev,
4849 extack);
Ido Schimmel7117a572016-06-20 23:04:06 +02004850 else
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004851 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4852 lower_dev,
4853 upper_dev);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004854 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004855 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004856 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4857 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004858 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004859 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4860 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004861 } else if (netif_is_ovs_master(upper_dev)) {
4862 if (info->linking)
4863 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4864 else
4865 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004866 }
4867 break;
4868 }
4869
Ido Schimmel80bedf12016-06-20 23:03:59 +02004870 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004871}
4872
Jiri Pirko74581202015-12-03 12:12:30 +01004873static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4874 unsigned long event, void *ptr)
4875{
4876 struct netdev_notifier_changelowerstate_info *info;
4877 struct mlxsw_sp_port *mlxsw_sp_port;
4878 int err;
4879
4880 mlxsw_sp_port = netdev_priv(dev);
4881 info = ptr;
4882
4883 switch (event) {
4884 case NETDEV_CHANGELOWERSTATE:
4885 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4886 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4887 info->lower_state_info);
4888 if (err)
4889 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4890 }
4891 break;
4892 }
4893
Ido Schimmel80bedf12016-06-20 23:03:59 +02004894 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004895}
4896
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004897static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4898 struct net_device *port_dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004899 unsigned long event, void *ptr)
4900{
4901 switch (event) {
4902 case NETDEV_PRECHANGEUPPER:
4903 case NETDEV_CHANGEUPPER:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004904 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4905 event, ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004906 case NETDEV_CHANGELOWERSTATE:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004907 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4908 ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004909 }
4910
Ido Schimmel80bedf12016-06-20 23:03:59 +02004911 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004912}
4913
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004914static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4915 unsigned long event, void *ptr)
4916{
4917 struct net_device *dev;
4918 struct list_head *iter;
4919 int ret;
4920
4921 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4922 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004923 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4924 ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004925 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004926 return ret;
4927 }
4928 }
4929
Ido Schimmel80bedf12016-06-20 23:03:59 +02004930 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004931}
4932
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004933static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4934 struct net_device *dev,
4935 unsigned long event, void *ptr,
4936 u16 vid)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004937{
4938 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel90045fc2017-12-25 09:05:33 +01004939 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004940 struct netdev_notifier_changeupper_info *info = ptr;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004941 struct netlink_ext_ack *extack;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004942 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004943 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004944
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004945 extack = netdev_notifier_info_to_extack(&info->info);
4946
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004947 switch (event) {
4948 case NETDEV_PRECHANGEUPPER:
4949 upper_dev = info->upper_dev;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004950 if (!netif_is_bridge_master(upper_dev)) {
4951 NL_SET_ERR_MSG(extack, "spectrum: VLAN devices only support bridge and VRF uppers");
Ido Schimmel80bedf12016-06-20 23:03:59 +02004952 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004953 }
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004954 if (!info->linking)
4955 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004956 if (netdev_has_any_upper_dev(upper_dev) &&
4957 (!netif_is_bridge_master(upper_dev) ||
4958 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4959 upper_dev))) {
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004960 NL_SET_ERR_MSG(extack, "spectrum: Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004961 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004962 }
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004963 break;
4964 case NETDEV_CHANGEUPPER:
4965 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004966 if (netif_is_bridge_master(upper_dev)) {
4967 if (info->linking)
Ido Schimmelc57529e2017-05-26 08:37:31 +02004968 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4969 vlan_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004970 upper_dev,
4971 extack);
Ido Schimmel1f880612017-03-10 08:53:35 +01004972 else
Ido Schimmelc57529e2017-05-26 08:37:31 +02004973 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4974 vlan_dev,
4975 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004976 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004977 err = -EINVAL;
4978 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004979 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004980 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004981 }
4982
Ido Schimmel80bedf12016-06-20 23:03:59 +02004983 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004984}
4985
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004986static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4987 struct net_device *lag_dev,
4988 unsigned long event,
4989 void *ptr, u16 vid)
Ido Schimmel272c4472015-12-15 16:03:47 +01004990{
4991 struct net_device *dev;
4992 struct list_head *iter;
4993 int ret;
4994
4995 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4996 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004997 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4998 event, ptr,
4999 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02005000 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01005001 return ret;
5002 }
5003 }
5004
Ido Schimmel80bedf12016-06-20 23:03:59 +02005005 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01005006}
5007
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01005008static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
5009 unsigned long event, void *ptr)
5010{
5011 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
5012 u16 vid = vlan_dev_vlan_id(vlan_dev);
5013
Ido Schimmel272c4472015-12-15 16:03:47 +01005014 if (mlxsw_sp_port_dev_check(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02005015 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
5016 event, ptr, vid);
Ido Schimmel272c4472015-12-15 16:03:47 +01005017 else if (netif_is_lag_master(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02005018 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
5019 real_dev, event,
5020 ptr, vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01005021
Ido Schimmel80bedf12016-06-20 23:03:59 +02005022 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01005023}
5024
Ido Schimmelb1e45522017-04-30 19:47:14 +03005025static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
5026{
5027 struct netdev_notifier_changeupper_info *info = ptr;
5028
5029 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
5030 return false;
5031 return netif_is_l3_master(info->upper_dev);
5032}
5033
Petr Machata00635872017-10-16 16:26:37 +02005034static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005035 unsigned long event, void *ptr)
5036{
5037 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Petr Machata00635872017-10-16 16:26:37 +02005038 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02005039 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005040
Petr Machata00635872017-10-16 16:26:37 +02005041 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
Petr Machata796ec772017-11-03 10:03:29 +01005042 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
5043 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
5044 event, ptr);
Petr Machata61481f22017-11-03 10:03:41 +01005045 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
5046 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
5047 event, ptr);
Petr Machata00635872017-10-16 16:26:37 +02005048 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
Ido Schimmel6e095fd2016-07-04 08:23:13 +02005049 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03005050 else if (mlxsw_sp_is_vrf_event(event, ptr))
5051 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02005052 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02005053 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02005054 else if (netif_is_lag_master(dev))
5055 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
5056 else if (is_vlan_dev(dev))
5057 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005058
Ido Schimmel80bedf12016-06-20 23:03:59 +02005059 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005060}
5061
David Ahern89d5dd22017-10-18 09:56:55 -07005062static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
5063 .notifier_call = mlxsw_sp_inetaddr_valid_event,
5064};
5065
Ido Schimmel99724c12016-07-04 08:23:14 +02005066static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
5067 .notifier_call = mlxsw_sp_inetaddr_event,
David Ahern89d5dd22017-10-18 09:56:55 -07005068};
5069
5070static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
5071 .notifier_call = mlxsw_sp_inet6addr_valid_event,
Ido Schimmel99724c12016-07-04 08:23:14 +02005072};
5073
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005074static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
5075 .notifier_call = mlxsw_sp_inet6addr_event,
5076};
5077
Jiri Pirko1d20d232016-10-27 15:12:59 +02005078static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
5079 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
5080 {0, },
5081};
5082
5083static struct pci_driver mlxsw_sp_pci_driver = {
5084 .name = mlxsw_sp_driver_name,
5085 .id_table = mlxsw_sp_pci_id_table,
5086};
5087
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005088static int __init mlxsw_sp_module_init(void)
5089{
5090 int err;
5091
David Ahern89d5dd22017-10-18 09:56:55 -07005092 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02005093 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005094 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005095 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02005096
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005097 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
5098 if (err)
5099 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02005100
5101 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
5102 if (err)
5103 goto err_pci_driver_register;
5104
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005105 return 0;
5106
Jiri Pirko1d20d232016-10-27 15:12:59 +02005107err_pci_driver_register:
5108 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005109err_core_driver_register:
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005110 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005111 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02005112 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005113 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005114 return err;
5115}
5116
5117static void __exit mlxsw_sp_module_exit(void)
5118{
Jiri Pirko1d20d232016-10-27 15:12:59 +02005119 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005120 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005121 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005122 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02005123 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005124 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005125}
5126
5127module_init(mlxsw_sp_module_init);
5128module_exit(mlxsw_sp_module_exit);
5129
5130MODULE_LICENSE("Dual BSD/GPL");
5131MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
5132MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02005133MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Yotam Gigi6b742192017-05-23 21:56:29 +02005134MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);