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Chaithrika U Sb67f4482009-06-05 06:28:40 -04001/*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040022#include <linux/delay.h>
23#include <linux/io.h>
Peter Ujfalusiae726e92013-11-14 11:35:35 +020024#include <linux/clk.h>
Hebbar, Gururaja10884342012-08-08 20:40:32 +053025#include <linux/pm_runtime.h>
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +053026#include <linux/of.h>
27#include <linux/of_platform.h>
28#include <linux/of_device.h>
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +020029#include <linux/platform_data/davinci_asp.h>
Jyri Sarhaa75a0532015-03-20 13:31:08 +020030#include <linux/math64.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040031
Daniel Mack64792852014-03-27 11:27:40 +010032#include <sound/asoundef.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040033#include <sound/core.h>
34#include <sound/pcm.h>
35#include <sound/pcm_params.h>
36#include <sound/initval.h>
37#include <sound/soc.h>
Peter Ujfalusi453c4992013-11-14 11:35:34 +020038#include <sound/dmaengine_pcm.h>
Jyri Sarha87c19362014-05-26 11:51:14 +030039#include <sound/omap-pcm.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040040
Peter Ujfalusif3f9cfa2014-07-16 15:12:04 +030041#include "edma-pcm.h"
Chaithrika U Sb67f4482009-06-05 06:28:40 -040042#include "davinci-mcasp.h"
43
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +030044#define MCASP_MAX_AFIFO_DEPTH 64
45
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +030046static u32 context_regs[] = {
47 DAVINCI_MCASP_TXFMCTL_REG,
48 DAVINCI_MCASP_RXFMCTL_REG,
49 DAVINCI_MCASP_TXFMT_REG,
50 DAVINCI_MCASP_RXFMT_REG,
51 DAVINCI_MCASP_ACLKXCTL_REG,
52 DAVINCI_MCASP_ACLKRCTL_REG,
Peter Ujfalusif114ce62014-10-01 16:02:12 +030053 DAVINCI_MCASP_AHCLKXCTL_REG,
54 DAVINCI_MCASP_AHCLKRCTL_REG,
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +030055 DAVINCI_MCASP_PDIR_REG,
Peter Ujfalusif114ce62014-10-01 16:02:12 +030056 DAVINCI_MCASP_RXMASK_REG,
57 DAVINCI_MCASP_TXMASK_REG,
58 DAVINCI_MCASP_RXTDM_REG,
59 DAVINCI_MCASP_TXTDM_REG,
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +030060};
61
Peter Ujfalusi790bb942014-02-03 14:51:52 +020062struct davinci_mcasp_context {
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +030063 u32 config_regs[ARRAY_SIZE(context_regs)];
Peter Ujfalusif114ce62014-10-01 16:02:12 +030064 u32 afifo_regs[2]; /* for read/write fifo control registers */
65 u32 *xrsr_regs; /* for serializer configuration */
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +020066 bool pm_state;
Peter Ujfalusi790bb942014-02-03 14:51:52 +020067};
68
Jyri Sarhaa75a0532015-03-20 13:31:08 +020069struct davinci_mcasp_ruledata {
70 struct davinci_mcasp *mcasp;
71 int serializers;
72};
73
Peter Ujfalusi70091a32013-11-14 11:35:29 +020074struct davinci_mcasp {
Peter Ujfalusi453c4992013-11-14 11:35:34 +020075 struct snd_dmaengine_dai_dma_data dma_data[2];
Peter Ujfalusi21400a72013-11-14 11:35:26 +020076 void __iomem *base;
Peter Ujfalusi487dce82013-11-14 11:35:31 +020077 u32 fifo_base;
Peter Ujfalusi21400a72013-11-14 11:35:26 +020078 struct device *dev;
Misael Lopez Cruza7a33242014-11-12 16:38:05 +020079 struct snd_pcm_substream *substreams[2];
Peter Ujfalusi21400a72013-11-14 11:35:26 +020080
81 /* McASP specific data */
82 int tdm_slots;
83 u8 op_mode;
84 u8 num_serializer;
85 u8 *serial_dir;
86 u8 version;
Daniel Mack82675252014-07-16 14:04:41 +020087 u8 bclk_div;
Peter Ujfalusi21400a72013-11-14 11:35:26 +020088 u16 bclk_lrclk_ratio;
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +020089 int streams;
Misael Lopez Cruza7a33242014-11-12 16:38:05 +020090 u32 irq_request[2];
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +020091 int dma_request[2];
Peter Ujfalusi21400a72013-11-14 11:35:26 +020092
Jyri Sarhaab8b14b2014-01-27 17:37:52 +020093 int sysclk_freq;
94 bool bclk_master;
95
Peter Ujfalusi21400a72013-11-14 11:35:26 +020096 /* McASP FIFO related */
97 u8 txnumevt;
98 u8 rxnumevt;
99
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +0200100 bool dat_port;
101
Peter Ujfalusi11277832014-11-10 12:32:16 +0200102 /* Used for comstraint setting on the second stream */
103 u32 channels;
104
Peter Ujfalusi21400a72013-11-14 11:35:26 +0200105#ifdef CONFIG_PM_SLEEP
Peter Ujfalusi790bb942014-02-03 14:51:52 +0200106 struct davinci_mcasp_context context;
Peter Ujfalusi21400a72013-11-14 11:35:26 +0200107#endif
Jyri Sarhaa75a0532015-03-20 13:31:08 +0200108
109 struct davinci_mcasp_ruledata ruledata[2];
Jyri Sarha5935a052015-04-23 16:16:05 +0300110 struct snd_pcm_hw_constraint_list chconstr[2];
Peter Ujfalusi21400a72013-11-14 11:35:26 +0200111};
112
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200113static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
114 u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400115{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200116 void __iomem *reg = mcasp->base + offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400117 __raw_writel(__raw_readl(reg) | val, reg);
118}
119
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200120static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
121 u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400122{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200123 void __iomem *reg = mcasp->base + offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400124 __raw_writel((__raw_readl(reg) & ~(val)), reg);
125}
126
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200127static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
128 u32 val, u32 mask)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400129{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200130 void __iomem *reg = mcasp->base + offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400131 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
132}
133
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200134static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
135 u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400136{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200137 __raw_writel(val, mcasp->base + offset);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400138}
139
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200140static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400141{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200142 return (u32)__raw_readl(mcasp->base + offset);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400143}
144
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200145static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400146{
147 int i = 0;
148
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200149 mcasp_set_bits(mcasp, ctl_reg, val);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400150
151 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
152 /* loop count is to avoid the lock-up */
153 for (i = 0; i < 1000; i++) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200154 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400155 break;
156 }
157
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200158 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400159 printk(KERN_ERR "GBLCTL write error\n");
160}
161
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200162static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
163{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200164 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
165 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200166
167 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
168}
169
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200170static void mcasp_start_rx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400171{
Peter Ujfalusibb372af2014-10-29 13:55:47 +0200172 if (mcasp->rxnumevt) { /* enable FIFO */
173 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
174
175 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
176 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
177 }
178
Peter Ujfalusi44982732014-10-29 13:55:45 +0200179 /* Start clocks */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200180 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
181 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200182 /*
183 * When ASYNC == 0 the transmit and receive sections operate
184 * synchronously from the transmit clock and frame sync. We need to make
185 * sure that the TX signlas are enabled when starting reception.
186 */
187 if (mcasp_is_synchronous(mcasp)) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200188 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
189 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200190 }
191
Peter Ujfalusi44982732014-10-29 13:55:45 +0200192 /* Activate serializer(s) */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200193 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
Peter Ujfalusi44982732014-10-29 13:55:45 +0200194 /* Release RX state machine */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200195 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
Peter Ujfalusi44982732014-10-29 13:55:45 +0200196 /* Release Frame Sync generator */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200197 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200198 if (mcasp_is_synchronous(mcasp))
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200199 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
Misael Lopez Cruza7a33242014-11-12 16:38:05 +0200200
201 /* enable receive IRQs */
202 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
203 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400204}
205
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200206static void mcasp_start_tx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400207{
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400208 u32 cnt;
209
Peter Ujfalusibb372af2014-10-29 13:55:47 +0200210 if (mcasp->txnumevt) { /* enable FIFO */
211 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
212
213 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
214 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
215 }
216
Peter Ujfalusi36bcecd2014-10-29 13:55:44 +0200217 /* Start clocks */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200218 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
219 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
Peter Ujfalusi36bcecd2014-10-29 13:55:44 +0200220 /* Activate serializer(s) */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200221 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400222
Peter Ujfalusi36bcecd2014-10-29 13:55:44 +0200223 /* wait for XDATA to be cleared */
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400224 cnt = 0;
Peter Ujfalusi36bcecd2014-10-29 13:55:44 +0200225 while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) &
226 ~XRDATA) && (cnt < 100000))
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400227 cnt++;
228
Peter Ujfalusi36bcecd2014-10-29 13:55:44 +0200229 /* Release TX state machine */
230 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
231 /* Release Frame Sync generator */
232 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
Misael Lopez Cruza7a33242014-11-12 16:38:05 +0200233
234 /* enable transmit IRQs */
235 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
236 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400237}
238
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200239static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400240{
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200241 mcasp->streams++;
242
Peter Ujfalusibb372af2014-10-29 13:55:47 +0200243 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200244 mcasp_start_tx(mcasp);
Peter Ujfalusibb372af2014-10-29 13:55:47 +0200245 else
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200246 mcasp_start_rx(mcasp);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400247}
248
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200249static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400250{
Misael Lopez Cruza7a33242014-11-12 16:38:05 +0200251 /* disable IRQ sources */
252 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
253 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
254
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200255 /*
256 * In synchronous mode stop the TX clocks if no other stream is
257 * running
258 */
259 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200260 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200261
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200262 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
263 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
Peter Ujfalusi03808662014-10-29 13:55:46 +0200264
265 if (mcasp->rxnumevt) { /* disable FIFO */
266 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
267
268 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
269 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400270}
271
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200272static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400273{
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200274 u32 val = 0;
275
Misael Lopez Cruza7a33242014-11-12 16:38:05 +0200276 /* disable IRQ sources */
277 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
278 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
279
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200280 /*
281 * In synchronous mode keep TX clocks running if the capture stream is
282 * still running.
283 */
284 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
285 val = TXHCLKRST | TXCLKRST | TXFSRST;
286
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200287 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
288 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
Peter Ujfalusi03808662014-10-29 13:55:46 +0200289
290 if (mcasp->txnumevt) { /* disable FIFO */
291 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
292
293 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
294 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400295}
296
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200297static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400298{
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200299 mcasp->streams--;
300
Peter Ujfalusi03808662014-10-29 13:55:46 +0200301 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200302 mcasp_stop_tx(mcasp);
Peter Ujfalusi03808662014-10-29 13:55:46 +0200303 else
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200304 mcasp_stop_rx(mcasp);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400305}
306
Misael Lopez Cruza7a33242014-11-12 16:38:05 +0200307static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
308{
309 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
310 struct snd_pcm_substream *substream;
311 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
312 u32 handled_mask = 0;
313 u32 stat;
314
315 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
316 if (stat & XUNDRN & irq_mask) {
317 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
318 handled_mask |= XUNDRN;
319
320 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
321 if (substream) {
322 snd_pcm_stream_lock_irq(substream);
323 if (snd_pcm_running(substream))
324 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
325 snd_pcm_stream_unlock_irq(substream);
326 }
327 }
328
329 if (!handled_mask)
330 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
331 stat);
332
333 if (stat & XRERR)
334 handled_mask |= XRERR;
335
336 /* Ack the handled event only */
337 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
338
339 return IRQ_RETVAL(handled_mask);
340}
341
342static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
343{
344 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
345 struct snd_pcm_substream *substream;
346 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
347 u32 handled_mask = 0;
348 u32 stat;
349
350 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
351 if (stat & ROVRN & irq_mask) {
352 dev_warn(mcasp->dev, "Receive buffer overflow\n");
353 handled_mask |= ROVRN;
354
355 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
356 if (substream) {
357 snd_pcm_stream_lock_irq(substream);
358 if (snd_pcm_running(substream))
359 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
360 snd_pcm_stream_unlock_irq(substream);
361 }
362 }
363
364 if (!handled_mask)
365 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
366 stat);
367
368 if (stat & XRERR)
369 handled_mask |= XRERR;
370
371 /* Ack the handled event only */
372 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
373
374 return IRQ_RETVAL(handled_mask);
375}
376
Peter Ujfalusi5a1b8a82014-12-30 16:10:32 +0200377static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
378{
379 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
380 irqreturn_t ret = IRQ_NONE;
381
382 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
383 ret = davinci_mcasp_tx_irq_handler(irq, data);
384
385 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
386 ret |= davinci_mcasp_rx_irq_handler(irq, data);
387
388 return ret;
389}
390
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400391static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
392 unsigned int fmt)
393{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200394 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200395 int ret = 0;
Peter Ujfalusi6dfa9a42014-04-04 14:31:42 +0300396 u32 data_delay;
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300397 bool fs_pol_rising;
Peter Ujfalusiffd950f2014-04-04 14:31:45 +0300398 bool inv_fs = false;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400399
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200400 pm_runtime_get_sync(mcasp->dev);
Daniel Mack5296cf22012-10-04 15:08:42 +0200401 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
Peter Ujfalusi188edc52014-04-04 14:31:43 +0300402 case SND_SOC_DAIFMT_DSP_A:
403 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
404 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
Peter Ujfalusi188edc52014-04-04 14:31:43 +0300405 /* 1st data bit occur one ACLK cycle after the frame sync */
406 data_delay = 1;
407 break;
Daniel Mack5296cf22012-10-04 15:08:42 +0200408 case SND_SOC_DAIFMT_DSP_B:
409 case SND_SOC_DAIFMT_AC97:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200410 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
411 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
Peter Ujfalusi6dfa9a42014-04-04 14:31:42 +0300412 /* No delay after FS */
413 data_delay = 0;
Daniel Mack5296cf22012-10-04 15:08:42 +0200414 break;
Peter Ujfalusiffd950f2014-04-04 14:31:45 +0300415 case SND_SOC_DAIFMT_I2S:
Daniel Mack5296cf22012-10-04 15:08:42 +0200416 /* configure a full-word SYNC pulse (LRCLK) */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200417 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
418 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
Peter Ujfalusi6dfa9a42014-04-04 14:31:42 +0300419 /* 1st data bit occur one ACLK cycle after the frame sync */
420 data_delay = 1;
Peter Ujfalusiffd950f2014-04-04 14:31:45 +0300421 /* FS need to be inverted */
422 inv_fs = true;
Daniel Mack5296cf22012-10-04 15:08:42 +0200423 break;
Peter Ujfalusi423761e2014-04-04 14:31:46 +0300424 case SND_SOC_DAIFMT_LEFT_J:
425 /* configure a full-word SYNC pulse (LRCLK) */
426 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
427 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
428 /* No delay after FS */
429 data_delay = 0;
430 break;
Peter Ujfalusiffd950f2014-04-04 14:31:45 +0300431 default:
432 ret = -EINVAL;
433 goto out;
Daniel Mack5296cf22012-10-04 15:08:42 +0200434 }
435
Peter Ujfalusi6dfa9a42014-04-04 14:31:42 +0300436 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
437 FSXDLY(3));
438 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
439 FSRDLY(3));
440
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400441 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
442 case SND_SOC_DAIFMT_CBS_CFS:
443 /* codec is clock and frame slave */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200444 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
445 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400446
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200447 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
448 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400449
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200450 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
451 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200452 mcasp->bclk_master = 1;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400453 break;
Peter Ujfalusi226e2f12015-02-12 16:41:26 +0200454 case SND_SOC_DAIFMT_CBS_CFM:
455 /* codec is clock slave and frame master */
456 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
457 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
458
459 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
460 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
461
462 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
463 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
464 mcasp->bclk_master = 1;
465 break;
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400466 case SND_SOC_DAIFMT_CBM_CFS:
467 /* codec is clock master and frame slave */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200468 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
469 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400470
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200471 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
472 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400473
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200474 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
475 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200476 mcasp->bclk_master = 0;
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400477 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400478 case SND_SOC_DAIFMT_CBM_CFM:
479 /* codec is clock and frame master */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200480 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
481 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400482
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200483 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
484 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400485
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200486 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
487 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200488 mcasp->bclk_master = 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400489 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400490 default:
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200491 ret = -EINVAL;
492 goto out;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400493 }
494
495 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
496 case SND_SOC_DAIFMT_IB_NF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200497 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
Peter Ujfalusi74ddd8c2014-04-04 14:31:41 +0300498 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300499 fs_pol_rising = true;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400500 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400501 case SND_SOC_DAIFMT_NB_IF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200502 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
Peter Ujfalusi74ddd8c2014-04-04 14:31:41 +0300503 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300504 fs_pol_rising = false;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400505 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400506 case SND_SOC_DAIFMT_IB_IF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200507 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
Peter Ujfalusi74ddd8c2014-04-04 14:31:41 +0300508 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300509 fs_pol_rising = false;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400510 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400511 case SND_SOC_DAIFMT_NB_NF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200512 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200513 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300514 fs_pol_rising = true;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400515 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400516 default:
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200517 ret = -EINVAL;
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300518 goto out;
519 }
520
Peter Ujfalusiffd950f2014-04-04 14:31:45 +0300521 if (inv_fs)
522 fs_pol_rising = !fs_pol_rising;
523
Peter Ujfalusi83f12502014-04-04 14:31:44 +0300524 if (fs_pol_rising) {
525 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
526 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
527 } else {
528 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
529 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400530 }
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200531out:
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +0200532 pm_runtime_put(mcasp->dev);
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200533 return ret;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400534}
535
Jyri Sarha88135432014-08-06 16:47:16 +0300536static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
537 int div, bool explicit)
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200538{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200539 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200540
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +0200541 pm_runtime_get_sync(mcasp->dev);
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200542 switch (div_id) {
543 case 0: /* MCLK divider */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200544 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200545 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200546 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200547 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
548 break;
549
550 case 1: /* BCLK divider */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200551 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200552 ACLKXDIV(div - 1), ACLKXDIV_MASK);
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200553 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200554 ACLKRDIV(div - 1), ACLKRDIV_MASK);
Jyri Sarha88135432014-08-06 16:47:16 +0300555 if (explicit)
556 mcasp->bclk_div = div;
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200557 break;
558
Daniel Mack1b3bc062012-12-05 18:20:38 +0100559 case 2: /* BCLK/LRCLK ratio */
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200560 mcasp->bclk_lrclk_ratio = div;
Daniel Mack1b3bc062012-12-05 18:20:38 +0100561 break;
562
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200563 default:
564 return -EINVAL;
565 }
566
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +0200567 pm_runtime_put(mcasp->dev);
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200568 return 0;
569}
570
Jyri Sarha88135432014-08-06 16:47:16 +0300571static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
572 int div)
573{
574 return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1);
575}
576
Daniel Mack5b66aa22012-10-04 15:08:41 +0200577static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
578 unsigned int freq, int dir)
579{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200580 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200581
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +0200582 pm_runtime_get_sync(mcasp->dev);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200583 if (dir == SND_SOC_CLOCK_OUT) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200584 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
585 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
586 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200587 } else {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200588 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
589 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
590 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200591 }
592
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200593 mcasp->sysclk_freq = freq;
594
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +0200595 pm_runtime_put(mcasp->dev);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200596 return 0;
597}
598
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200599static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
Daniel Mackba764b32012-12-05 18:20:37 +0100600 int word_length)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400601{
Daniel Mackba764b32012-12-05 18:20:37 +0100602 u32 fmt;
Daniel Mack79671892013-05-16 15:25:01 +0200603 u32 tx_rotate = (word_length / 4) & 0x7;
Daniel Mackba764b32012-12-05 18:20:37 +0100604 u32 mask = (1ULL << word_length) - 1;
Peter Ujfalusife0a29e2014-09-04 10:52:53 +0300605 /*
606 * For captured data we should not rotate, inversion and masking is
607 * enoguh to get the data to the right position:
608 * Format data from bus after reverse (XRBUF)
609 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
610 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
611 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
612 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
613 */
614 u32 rx_rotate = 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400615
Daniel Mack1b3bc062012-12-05 18:20:38 +0100616 /*
617 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
618 * callback, take it into account here. That allows us to for example
619 * send 32 bits per channel to the codec, while only 16 of them carry
620 * audio payload.
Michal Bachratyd486fea2013-04-19 15:28:44 +0200621 * The clock ratio is given for a full period of data (for I2S format
622 * both left and right channels), so it has to be divided by number of
623 * tdm-slots (for I2S - divided by 2).
Daniel Mack1b3bc062012-12-05 18:20:38 +0100624 */
Peter Ujfalusid742b922014-11-10 12:32:19 +0200625 if (mcasp->bclk_lrclk_ratio) {
626 u32 slot_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
627
628 /*
629 * When we have more bclk then it is needed for the data, we
630 * need to use the rotation to move the received samples to have
631 * correct alignment.
632 */
633 rx_rotate = (slot_length - word_length) / 4;
634 word_length = slot_length;
635 }
Daniel Mack1b3bc062012-12-05 18:20:38 +0100636
Daniel Mackba764b32012-12-05 18:20:37 +0100637 /* mapping of the XSSZ bit-field as described in the datasheet */
638 fmt = (word_length >> 1) - 1;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400639
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200640 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200641 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
642 RXSSZ(0x0F));
643 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
644 TXSSZ(0x0F));
645 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
646 TXROT(7));
647 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
648 RXROT(7));
649 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
Yegor Yefremovf5023af2013-04-04 16:13:20 +0200650 }
651
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200652 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
Chaithrika U S0c31cf32009-09-15 18:13:29 -0400653
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400654 return 0;
655}
656
Peter Ujfalusi662ffae2014-01-30 15:15:22 +0200657static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300658 int period_words, int channels)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400659{
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300660 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400661 int i;
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400662 u8 tx_ser = 0;
663 u8 rx_ser = 0;
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200664 u8 slots = mcasp->tdm_slots;
Michal Bachraty2952b272013-02-28 16:07:08 +0100665 u8 max_active_serializers = (channels + slots - 1) / slots;
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300666 int active_serializers, numevt, n;
Peter Ujfalusi487dce82013-11-14 11:35:31 +0200667 u32 reg;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400668 /* Default configuration */
Peter Ujfalusi40448e52014-04-04 15:56:30 +0300669 if (mcasp->version < MCASP_VERSION_3)
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200670 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400671
672 /* All PINS as McASP */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200673 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400674
675 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200676 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
677 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400678 } else {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200679 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
680 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400681 }
682
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200683 for (i = 0; i < mcasp->num_serializer; i++) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200684 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
685 mcasp->serial_dir[i]);
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200686 if (mcasp->serial_dir[i] == TX_MODE &&
Michal Bachraty2952b272013-02-28 16:07:08 +0100687 tx_ser < max_active_serializers) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200688 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
Misael Lopez Cruz19db62e2015-06-08 16:03:47 +0300689 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
690 DISMOD_LOW, DISMOD_MASK);
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400691 tx_ser++;
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200692 } else if (mcasp->serial_dir[i] == RX_MODE &&
Michal Bachraty2952b272013-02-28 16:07:08 +0100693 rx_ser < max_active_serializers) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200694 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400695 rx_ser++;
Michal Bachraty2952b272013-02-28 16:07:08 +0100696 } else {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200697 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
698 SRMOD_INACTIVE, SRMOD_MASK);
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400699 }
700 }
701
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300702 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
703 active_serializers = tx_ser;
704 numevt = mcasp->txnumevt;
705 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
706 } else {
707 active_serializers = rx_ser;
708 numevt = mcasp->rxnumevt;
709 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
710 }
Daniel Mackecf327c2013-03-08 14:19:38 +0100711
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300712 if (active_serializers < max_active_serializers) {
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200713 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300714 "enabled in mcasp (%d)\n", channels,
715 active_serializers * slots);
Daniel Mackecf327c2013-03-08 14:19:38 +0100716 return -EINVAL;
717 }
718
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300719 /* AFIFO is not in use */
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300720 if (!numevt) {
721 /* Configure the burst size for platform drivers */
Peter Ujfalusi33445642014-04-01 15:55:12 +0300722 if (active_serializers > 1) {
723 /*
724 * If more than one serializers are in use we have one
725 * DMA request to provide data for all serializers.
726 * For example if three serializers are enabled the DMA
727 * need to transfer three words per DMA request.
728 */
Peter Ujfalusi33445642014-04-01 15:55:12 +0300729 dma_data->maxburst = active_serializers;
730 } else {
Peter Ujfalusi33445642014-04-01 15:55:12 +0300731 dma_data->maxburst = 0;
732 }
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300733 return 0;
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300734 }
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400735
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300736 if (period_words % active_serializers) {
737 dev_err(mcasp->dev, "Invalid combination of period words and "
738 "active serializers: %d, %d\n", period_words,
739 active_serializers);
740 return -EINVAL;
741 }
742
743 /*
744 * Calculate the optimal AFIFO depth for platform side:
745 * The number of words for numevt need to be in steps of active
746 * serializers.
747 */
748 n = numevt % active_serializers;
749 if (n)
750 numevt += (active_serializers - n);
751 while (period_words % numevt && numevt > 0)
752 numevt -= active_serializers;
753 if (numevt <= 0)
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300754 numevt = active_serializers;
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400755
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300756 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
757 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
Michal Bachraty2952b272013-02-28 16:07:08 +0100758
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300759 /* Configure the burst size for platform drivers */
Peter Ujfalusi33445642014-04-01 15:55:12 +0300760 if (numevt == 1)
761 numevt = 0;
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300762 dma_data->maxburst = numevt;
763
Michal Bachraty2952b272013-02-28 16:07:08 +0100764 return 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400765}
766
Misael Lopez Cruz18a4f552014-11-10 12:32:17 +0200767static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
768 int channels)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400769{
770 int i, active_slots;
Misael Lopez Cruz18a4f552014-11-10 12:32:17 +0200771 int total_slots;
772 int active_serializers;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400773 u32 mask = 0;
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +0200774 u32 busel = 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400775
Misael Lopez Cruz18a4f552014-11-10 12:32:17 +0200776 total_slots = mcasp->tdm_slots;
777
778 /*
779 * If more than one serializer is needed, then use them with
780 * their specified tdm_slots count. Otherwise, one serializer
781 * can cope with the transaction using as many slots as channels
782 * in the stream, requires channels symmetry
783 */
784 active_serializers = (channels + total_slots - 1) / total_slots;
785 if (active_serializers == 1)
786 active_slots = channels;
787 else
788 active_slots = total_slots;
789
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400790 for (i = 0; i < active_slots; i++)
791 mask |= (1 << i);
792
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200793 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400794
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +0200795 if (!mcasp->dat_port)
796 busel = TXSEL;
797
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200798 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
799 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
800 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
Misael Lopez Cruz18a4f552014-11-10 12:32:17 +0200801 FSXMOD(total_slots), FSXMOD(0x1FF));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400802
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200803 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
804 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
805 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
Misael Lopez Cruz18a4f552014-11-10 12:32:17 +0200806 FSRMOD(total_slots), FSRMOD(0x1FF));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400807
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200808 return 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400809}
810
811/* S/PDIF */
Daniel Mack64792852014-03-27 11:27:40 +0100812static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
813 unsigned int rate)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400814{
Daniel Mack64792852014-03-27 11:27:40 +0100815 u32 cs_value = 0;
816 u8 *cs_bytes = (u8*) &cs_value;
817
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400818 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
819 and LSB first */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200820 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400821
822 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200823 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400824
825 /* Set the TX tdm : for all the slots */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200826 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400827
828 /* Set the TX clock controls : div = 1 and internal */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200829 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400830
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200831 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400832
833 /* Only 44100 and 48000 are valid, both have the same setting */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200834 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400835
836 /* Enable the DIT */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200837 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200838
Daniel Mack64792852014-03-27 11:27:40 +0100839 /* Set S/PDIF channel status bits */
840 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
841 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
842
843 switch (rate) {
844 case 22050:
845 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
846 break;
847 case 24000:
848 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
849 break;
850 case 32000:
851 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
852 break;
853 case 44100:
854 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
855 break;
856 case 48000:
857 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
858 break;
859 case 88200:
860 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
861 break;
862 case 96000:
863 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
864 break;
865 case 176400:
866 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
867 break;
868 case 192000:
869 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
870 break;
871 default:
872 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
873 return -EINVAL;
874 }
875
876 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
877 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
878
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200879 return 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400880}
881
Jyri Sarhaa75a0532015-03-20 13:31:08 +0200882static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
883 unsigned int bclk_freq,
884 int *error_ppm)
885{
886 int div = mcasp->sysclk_freq / bclk_freq;
887 int rem = mcasp->sysclk_freq % bclk_freq;
888
889 if (rem != 0) {
890 if (div == 0 ||
891 ((mcasp->sysclk_freq / div) - bclk_freq) >
892 (bclk_freq - (mcasp->sysclk_freq / (div+1)))) {
893 div++;
894 rem = rem - bclk_freq;
895 }
896 }
897 if (error_ppm)
898 *error_ppm =
899 (div*1000000 + (int)div64_long(1000000LL*rem,
900 (int)bclk_freq))
901 /div - 1000000;
902
903 return div;
904}
905
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400906static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
907 struct snd_pcm_hw_params *params,
908 struct snd_soc_dai *cpu_dai)
909{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200910 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400911 int word_length;
Peter Ujfalusia7e46bd2014-02-03 14:51:50 +0200912 int channels = params_channels(params);
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300913 int period_size = params_period_size(params);
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200914 int ret;
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200915
Daniel Mack82675252014-07-16 14:04:41 +0200916 /*
917 * If mcasp is BCLK master, and a BCLK divider was not provided by
918 * the machine driver, we need to calculate the ratio.
919 */
920 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
Jyri Sarha1f114f72015-04-23 16:16:04 +0300921 int slots = mcasp->tdm_slots;
Jyri Sarhaa75a0532015-03-20 13:31:08 +0200922 int rate = params_rate(params);
923 int sbits = params_width(params);
924 int ppm, div;
925
Jyri Sarha1f114f72015-04-23 16:16:04 +0300926 div = davinci_mcasp_calc_clk_div(mcasp, rate*sbits*slots,
Jyri Sarhaa75a0532015-03-20 13:31:08 +0200927 &ppm);
928 if (ppm)
929 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
930 ppm);
931
Jyri Sarha88135432014-08-06 16:47:16 +0300932 __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0);
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200933 }
934
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300935 ret = mcasp_common_hw_param(mcasp, substream->stream,
936 period_size * channels, channels);
Peter Ujfalusi0f7d9a62014-01-30 15:15:24 +0200937 if (ret)
938 return ret;
939
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200940 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
Daniel Mack64792852014-03-27 11:27:40 +0100941 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400942 else
Misael Lopez Cruz18a4f552014-11-10 12:32:17 +0200943 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
944 channels);
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200945
946 if (ret)
947 return ret;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400948
949 switch (params_format(params)) {
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400950 case SNDRV_PCM_FORMAT_U8:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400951 case SNDRV_PCM_FORMAT_S8:
Daniel Mackba764b32012-12-05 18:20:37 +0100952 word_length = 8;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400953 break;
954
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400955 case SNDRV_PCM_FORMAT_U16_LE:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400956 case SNDRV_PCM_FORMAT_S16_LE:
Daniel Mackba764b32012-12-05 18:20:37 +0100957 word_length = 16;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400958 break;
959
Daniel Mack21eb24d2012-10-09 09:35:16 +0200960 case SNDRV_PCM_FORMAT_U24_3LE:
961 case SNDRV_PCM_FORMAT_S24_3LE:
Daniel Mackba764b32012-12-05 18:20:37 +0100962 word_length = 24;
Daniel Mack21eb24d2012-10-09 09:35:16 +0200963 break;
964
Daniel Mack6b7fa012012-10-09 11:56:40 +0200965 case SNDRV_PCM_FORMAT_U24_LE:
966 case SNDRV_PCM_FORMAT_S24_LE:
Peter Ujfalusi182bef82014-06-26 08:09:24 +0300967 word_length = 24;
968 break;
969
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400970 case SNDRV_PCM_FORMAT_U32_LE:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400971 case SNDRV_PCM_FORMAT_S32_LE:
Daniel Mackba764b32012-12-05 18:20:37 +0100972 word_length = 32;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400973 break;
974
975 default:
976 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
977 return -EINVAL;
978 }
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400979
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200980 davinci_config_channel_size(mcasp, word_length);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400981
Peter Ujfalusi11277832014-11-10 12:32:16 +0200982 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
983 mcasp->channels = channels;
984
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400985 return 0;
986}
987
988static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
989 int cmd, struct snd_soc_dai *cpu_dai)
990{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200991 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400992 int ret = 0;
993
994 switch (cmd) {
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400995 case SNDRV_PCM_TRIGGER_RESUME:
Chaithrika U Se473b842010-01-20 17:06:33 +0530996 case SNDRV_PCM_TRIGGER_START:
997 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200998 davinci_mcasp_start(mcasp, substream->stream);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400999 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001000 case SNDRV_PCM_TRIGGER_SUSPEND:
Chaithrika U Sa47979b2009-12-03 18:56:56 +05301001 case SNDRV_PCM_TRIGGER_STOP:
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001002 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001003 davinci_mcasp_stop(mcasp, substream->stream);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001004 break;
1005
1006 default:
1007 ret = -EINVAL;
1008 }
1009
1010 return ret;
1011}
1012
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001013static const unsigned int davinci_mcasp_dai_rates[] = {
1014 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1015 88200, 96000, 176400, 192000,
1016};
1017
1018#define DAVINCI_MAX_RATE_ERROR_PPM 1000
1019
1020static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1021 struct snd_pcm_hw_rule *rule)
1022{
1023 struct davinci_mcasp_ruledata *rd = rule->private;
1024 struct snd_interval *ri =
1025 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1026 int sbits = params_width(params);
Jyri Sarha1f114f72015-04-23 16:16:04 +03001027 int slots = rd->mcasp->tdm_slots;
Jyri Sarha518f6ba2015-04-23 16:16:06 +03001028 struct snd_interval range;
1029 int i;
1030
1031 snd_interval_any(&range);
1032 range.empty = 1;
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001033
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001034 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
Jyri Sarha518f6ba2015-04-23 16:16:06 +03001035 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
Jyri Sarha1f114f72015-04-23 16:16:04 +03001036 uint bclk_freq = sbits*slots*
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001037 davinci_mcasp_dai_rates[i];
1038 int ppm;
1039
1040 davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
Jyri Sarha518f6ba2015-04-23 16:16:06 +03001041 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1042 if (range.empty) {
1043 range.min = davinci_mcasp_dai_rates[i];
1044 range.empty = 0;
1045 }
1046 range.max = davinci_mcasp_dai_rates[i];
1047 }
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001048 }
1049 }
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001050
Jyri Sarha518f6ba2015-04-23 16:16:06 +03001051 dev_dbg(rd->mcasp->dev,
1052 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1053 ri->min, ri->max, range.min, range.max, sbits, slots);
1054
1055 return snd_interval_refine(hw_param_interval(params, rule->var),
1056 &range);
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001057}
1058
1059static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1060 struct snd_pcm_hw_rule *rule)
1061{
1062 struct davinci_mcasp_ruledata *rd = rule->private;
1063 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1064 struct snd_mask nfmt;
1065 int rate = params_rate(params);
Jyri Sarha1f114f72015-04-23 16:16:04 +03001066 int slots = rd->mcasp->tdm_slots;
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001067 int i, count = 0;
1068
1069 snd_mask_none(&nfmt);
1070
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001071 for (i = 0; i < SNDRV_PCM_FORMAT_LAST; i++) {
1072 if (snd_mask_test(fmt, i)) {
Jyri Sarha1f114f72015-04-23 16:16:04 +03001073 uint bclk_freq = snd_pcm_format_width(i)*slots*rate;
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001074 int ppm;
1075
1076 davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
1077 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1078 snd_mask_set(&nfmt, i);
1079 count++;
1080 }
1081 }
1082 }
1083 dev_dbg(rd->mcasp->dev,
Jyri Sarha1f114f72015-04-23 16:16:04 +03001084 "%d possible sample format for %d Hz and %d tdm slots\n",
1085 count, rate, slots);
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001086
1087 return snd_mask_refine(fmt, &nfmt);
1088}
1089
Peter Ujfalusi11277832014-11-10 12:32:16 +02001090static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1091 struct snd_soc_dai *cpu_dai)
1092{
1093 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
Peter Ujfalusi4cd9db02015-04-07 14:03:53 +03001094 struct davinci_mcasp_ruledata *ruledata =
1095 &mcasp->ruledata[substream->stream];
Peter Ujfalusi11277832014-11-10 12:32:16 +02001096 u32 max_channels = 0;
1097 int i, dir;
1098
Misael Lopez Cruza7a33242014-11-12 16:38:05 +02001099 mcasp->substreams[substream->stream] = substream;
1100
Peter Ujfalusi11277832014-11-10 12:32:16 +02001101 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1102 return 0;
1103
1104 /*
1105 * Limit the maximum allowed channels for the first stream:
1106 * number of serializers for the direction * tdm slots per serializer
1107 */
1108 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1109 dir = TX_MODE;
1110 else
1111 dir = RX_MODE;
1112
1113 for (i = 0; i < mcasp->num_serializer; i++) {
1114 if (mcasp->serial_dir[i] == dir)
1115 max_channels++;
1116 }
Peter Ujfalusi4cd9db02015-04-07 14:03:53 +03001117 ruledata->serializers = max_channels;
Peter Ujfalusi11277832014-11-10 12:32:16 +02001118 max_channels *= mcasp->tdm_slots;
1119 /*
1120 * If the already active stream has less channels than the calculated
1121 * limnit based on the seirializers * tdm_slots, we need to use that as
1122 * a constraint for the second stream.
1123 * Otherwise (first stream or less allowed channels) we use the
1124 * calculated constraint.
1125 */
1126 if (mcasp->channels && mcasp->channels < max_channels)
1127 max_channels = mcasp->channels;
1128
1129 snd_pcm_hw_constraint_minmax(substream->runtime,
1130 SNDRV_PCM_HW_PARAM_CHANNELS,
1131 2, max_channels);
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001132
Jyri Sarha5935a052015-04-23 16:16:05 +03001133 if (mcasp->chconstr[substream->stream].count)
1134 snd_pcm_hw_constraint_list(substream->runtime,
1135 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1136 &mcasp->chconstr[substream->stream]);
1137
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001138 /*
1139 * If we rely on implicit BCLK divider setting we should
1140 * set constraints based on what we can provide.
1141 */
1142 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1143 int ret;
1144
Peter Ujfalusi4cd9db02015-04-07 14:03:53 +03001145 ruledata->mcasp = mcasp;
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001146
1147 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1148 SNDRV_PCM_HW_PARAM_RATE,
1149 davinci_mcasp_hw_rule_rate,
Peter Ujfalusi4cd9db02015-04-07 14:03:53 +03001150 ruledata,
Jyri Sarha1f114f72015-04-23 16:16:04 +03001151 SNDRV_PCM_HW_PARAM_FORMAT, -1);
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001152 if (ret)
1153 return ret;
1154 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1155 SNDRV_PCM_HW_PARAM_FORMAT,
1156 davinci_mcasp_hw_rule_format,
Peter Ujfalusi4cd9db02015-04-07 14:03:53 +03001157 ruledata,
Jyri Sarha1f114f72015-04-23 16:16:04 +03001158 SNDRV_PCM_HW_PARAM_RATE, -1);
Jyri Sarhaa75a0532015-03-20 13:31:08 +02001159 if (ret)
1160 return ret;
1161 }
1162
Peter Ujfalusi11277832014-11-10 12:32:16 +02001163 return 0;
1164}
1165
1166static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1167 struct snd_soc_dai *cpu_dai)
1168{
1169 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1170
Misael Lopez Cruza7a33242014-11-12 16:38:05 +02001171 mcasp->substreams[substream->stream] = NULL;
1172
Peter Ujfalusi11277832014-11-10 12:32:16 +02001173 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1174 return;
1175
1176 if (!cpu_dai->active)
1177 mcasp->channels = 0;
1178}
1179
Lars-Peter Clausen85e76522011-11-23 11:40:40 +01001180static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
Peter Ujfalusi11277832014-11-10 12:32:16 +02001181 .startup = davinci_mcasp_startup,
1182 .shutdown = davinci_mcasp_shutdown,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001183 .trigger = davinci_mcasp_trigger,
1184 .hw_params = davinci_mcasp_hw_params,
1185 .set_fmt = davinci_mcasp_set_dai_fmt,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +02001186 .set_clkdiv = davinci_mcasp_set_clkdiv,
Daniel Mack5b66aa22012-10-04 15:08:41 +02001187 .set_sysclk = davinci_mcasp_set_sysclk,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001188};
1189
Peter Ujfalusid5902f62014-04-01 15:55:07 +03001190static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1191{
1192 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1193
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001194 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1195 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
Peter Ujfalusid5902f62014-04-01 15:55:07 +03001196
1197 return 0;
1198}
1199
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001200#ifdef CONFIG_PM_SLEEP
1201static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1202{
1203 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
Peter Ujfalusi790bb942014-02-03 14:51:52 +02001204 struct davinci_mcasp_context *context = &mcasp->context;
Peter Ujfalusif114ce62014-10-01 16:02:12 +03001205 u32 reg;
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +03001206 int i;
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001207
Peter Ujfalusi66e61882015-03-06 09:07:32 +02001208 context->pm_state = pm_runtime_enabled(mcasp->dev);
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +02001209 if (!context->pm_state)
1210 pm_runtime_get_sync(mcasp->dev);
1211
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +03001212 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1213 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001214
Peter Ujfalusif114ce62014-10-01 16:02:12 +03001215 if (mcasp->txnumevt) {
1216 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1217 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1218 }
1219 if (mcasp->rxnumevt) {
1220 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1221 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1222 }
1223
1224 for (i = 0; i < mcasp->num_serializer; i++)
1225 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1226 DAVINCI_MCASP_XRSRCTL_REG(i));
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001227
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +02001228 pm_runtime_put_sync(mcasp->dev);
1229
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001230 return 0;
1231}
1232
1233static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1234{
1235 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
Peter Ujfalusi790bb942014-02-03 14:51:52 +02001236 struct davinci_mcasp_context *context = &mcasp->context;
Peter Ujfalusif114ce62014-10-01 16:02:12 +03001237 u32 reg;
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +03001238 int i;
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001239
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +02001240 pm_runtime_get_sync(mcasp->dev);
1241
Peter Ujfalusi1cc0c052014-10-01 16:02:11 +03001242 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1243 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001244
Peter Ujfalusif114ce62014-10-01 16:02:12 +03001245 if (mcasp->txnumevt) {
1246 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1247 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1248 }
1249 if (mcasp->rxnumevt) {
1250 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1251 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1252 }
1253
1254 for (i = 0; i < mcasp->num_serializer; i++)
1255 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1256 context->xrsr_regs[i]);
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001257
Peter Ujfalusi6afda7f2015-03-05 16:55:21 +02001258 if (!context->pm_state)
1259 pm_runtime_put_sync(mcasp->dev);
1260
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001261 return 0;
1262}
1263#else
1264#define davinci_mcasp_suspend NULL
1265#define davinci_mcasp_resume NULL
1266#endif
1267
Peter Ujfalusied29cd52013-11-14 11:35:22 +02001268#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1269
Ben Gardiner0a9d1382011-08-26 12:02:44 -04001270#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1271 SNDRV_PCM_FMTBIT_U8 | \
1272 SNDRV_PCM_FMTBIT_S16_LE | \
1273 SNDRV_PCM_FMTBIT_U16_LE | \
Daniel Mack21eb24d2012-10-09 09:35:16 +02001274 SNDRV_PCM_FMTBIT_S24_LE | \
1275 SNDRV_PCM_FMTBIT_U24_LE | \
1276 SNDRV_PCM_FMTBIT_S24_3LE | \
1277 SNDRV_PCM_FMTBIT_U24_3LE | \
Ben Gardiner0a9d1382011-08-26 12:02:44 -04001278 SNDRV_PCM_FMTBIT_S32_LE | \
1279 SNDRV_PCM_FMTBIT_U32_LE)
1280
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +00001281static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001282 {
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +00001283 .name = "davinci-mcasp.0",
Peter Ujfalusid5902f62014-04-01 15:55:07 +03001284 .probe = davinci_mcasp_dai_probe,
Peter Ujfalusi135014a2014-01-30 15:21:32 +02001285 .suspend = davinci_mcasp_suspend,
1286 .resume = davinci_mcasp_resume,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001287 .playback = {
1288 .channels_min = 2,
Michal Bachraty2952b272013-02-28 16:07:08 +01001289 .channels_max = 32 * 16,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001290 .rates = DAVINCI_MCASP_RATES,
Ben Gardiner0a9d1382011-08-26 12:02:44 -04001291 .formats = DAVINCI_MCASP_PCM_FMTS,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001292 },
1293 .capture = {
1294 .channels_min = 2,
Michal Bachraty2952b272013-02-28 16:07:08 +01001295 .channels_max = 32 * 16,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001296 .rates = DAVINCI_MCASP_RATES,
Ben Gardiner0a9d1382011-08-26 12:02:44 -04001297 .formats = DAVINCI_MCASP_PCM_FMTS,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001298 },
1299 .ops = &davinci_mcasp_dai_ops,
1300
Peter Ujfalusid75249f2014-11-10 12:32:18 +02001301 .symmetric_samplebits = 1,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001302 },
1303 {
Peter Ujfalusi58e48d92013-11-14 11:35:24 +02001304 .name = "davinci-mcasp.1",
Peter Ujfalusid5902f62014-04-01 15:55:07 +03001305 .probe = davinci_mcasp_dai_probe,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001306 .playback = {
1307 .channels_min = 1,
1308 .channels_max = 384,
1309 .rates = DAVINCI_MCASP_RATES,
Ben Gardiner0a9d1382011-08-26 12:02:44 -04001310 .formats = DAVINCI_MCASP_PCM_FMTS,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001311 },
1312 .ops = &davinci_mcasp_dai_ops,
1313 },
1314
1315};
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001316
Kuninori Morimotoeeef0ed2013-03-21 03:31:19 -07001317static const struct snd_soc_component_driver davinci_mcasp_component = {
1318 .name = "davinci-mcasp",
1319};
1320
Jyri Sarha256ba182013-10-18 18:37:42 +03001321/* Some HW specific values and defaults. The rest is filled in from DT. */
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001322static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
Jyri Sarha256ba182013-10-18 18:37:42 +03001323 .tx_dma_offset = 0x400,
1324 .rx_dma_offset = 0x400,
Jyri Sarha256ba182013-10-18 18:37:42 +03001325 .version = MCASP_VERSION_1,
1326};
1327
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001328static struct davinci_mcasp_pdata da830_mcasp_pdata = {
Jyri Sarha256ba182013-10-18 18:37:42 +03001329 .tx_dma_offset = 0x2000,
1330 .rx_dma_offset = 0x2000,
Jyri Sarha256ba182013-10-18 18:37:42 +03001331 .version = MCASP_VERSION_2,
1332};
1333
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001334static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
Jyri Sarha256ba182013-10-18 18:37:42 +03001335 .tx_dma_offset = 0,
1336 .rx_dma_offset = 0,
Jyri Sarha256ba182013-10-18 18:37:42 +03001337 .version = MCASP_VERSION_3,
1338};
1339
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001340static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001341 .tx_dma_offset = 0x200,
1342 .rx_dma_offset = 0x284,
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001343 .version = MCASP_VERSION_4,
1344};
1345
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301346static const struct of_device_id mcasp_dt_ids[] = {
1347 {
1348 .compatible = "ti,dm646x-mcasp-audio",
Jyri Sarha256ba182013-10-18 18:37:42 +03001349 .data = &dm646x_mcasp_pdata,
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301350 },
1351 {
1352 .compatible = "ti,da830-mcasp-audio",
Jyri Sarha256ba182013-10-18 18:37:42 +03001353 .data = &da830_mcasp_pdata,
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301354 },
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +05301355 {
Jyri Sarha3af9e032013-10-18 18:37:44 +03001356 .compatible = "ti,am33xx-mcasp-audio",
Peter Ujfalusib14899d2013-11-14 11:35:37 +02001357 .data = &am33xx_mcasp_pdata,
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +05301358 },
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001359 {
1360 .compatible = "ti,dra7-mcasp-audio",
1361 .data = &dra7_mcasp_pdata,
1362 },
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301363 { /* sentinel */ }
1364};
1365MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1366
Peter Ujfalusiae726e92013-11-14 11:35:35 +02001367static int mcasp_reparent_fck(struct platform_device *pdev)
1368{
1369 struct device_node *node = pdev->dev.of_node;
1370 struct clk *gfclk, *parent_clk;
1371 const char *parent_name;
1372 int ret;
1373
1374 if (!node)
1375 return 0;
1376
1377 parent_name = of_get_property(node, "fck_parent", NULL);
1378 if (!parent_name)
1379 return 0;
1380
1381 gfclk = clk_get(&pdev->dev, "fck");
1382 if (IS_ERR(gfclk)) {
1383 dev_err(&pdev->dev, "failed to get fck\n");
1384 return PTR_ERR(gfclk);
1385 }
1386
1387 parent_clk = clk_get(NULL, parent_name);
1388 if (IS_ERR(parent_clk)) {
1389 dev_err(&pdev->dev, "failed to get parent clock\n");
1390 ret = PTR_ERR(parent_clk);
1391 goto err1;
1392 }
1393
1394 ret = clk_set_parent(gfclk, parent_clk);
1395 if (ret) {
1396 dev_err(&pdev->dev, "failed to reparent fck\n");
1397 goto err2;
1398 }
1399
1400err2:
1401 clk_put(parent_clk);
1402err1:
1403 clk_put(gfclk);
1404 return ret;
1405}
1406
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001407static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301408 struct platform_device *pdev)
1409{
1410 struct device_node *np = pdev->dev.of_node;
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001411 struct davinci_mcasp_pdata *pdata = NULL;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301412 const struct of_device_id *match =
Sachin Kamatea421eb2013-05-22 16:53:37 +05301413 of_match_device(mcasp_dt_ids, &pdev->dev);
Jyri Sarha4023fe62013-10-18 18:37:43 +03001414 struct of_phandle_args dma_spec;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301415
1416 const u32 *of_serial_dir32;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301417 u32 val;
1418 int i, ret = 0;
1419
1420 if (pdev->dev.platform_data) {
1421 pdata = pdev->dev.platform_data;
1422 return pdata;
1423 } else if (match) {
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001424 pdata = (struct davinci_mcasp_pdata*) match->data;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301425 } else {
1426 /* control shouldn't reach here. something is wrong */
1427 ret = -EINVAL;
1428 goto nodata;
1429 }
1430
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301431 ret = of_property_read_u32(np, "op-mode", &val);
1432 if (ret >= 0)
1433 pdata->op_mode = val;
1434
1435 ret = of_property_read_u32(np, "tdm-slots", &val);
Michal Bachraty2952b272013-02-28 16:07:08 +01001436 if (ret >= 0) {
1437 if (val < 2 || val > 32) {
1438 dev_err(&pdev->dev,
1439 "tdm-slots must be in rage [2-32]\n");
1440 ret = -EINVAL;
1441 goto nodata;
1442 }
1443
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301444 pdata->tdm_slots = val;
Michal Bachraty2952b272013-02-28 16:07:08 +01001445 }
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301446
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301447 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1448 val /= sizeof(u32);
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301449 if (of_serial_dir32) {
Peter Ujfalusi1427e662013-10-18 18:37:46 +03001450 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1451 (sizeof(*of_serial_dir) * val),
1452 GFP_KERNEL);
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301453 if (!of_serial_dir) {
1454 ret = -ENOMEM;
1455 goto nodata;
1456 }
1457
Peter Ujfalusi1427e662013-10-18 18:37:46 +03001458 for (i = 0; i < val; i++)
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301459 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1460
Peter Ujfalusi1427e662013-10-18 18:37:46 +03001461 pdata->num_serializer = val;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301462 pdata->serial_dir = of_serial_dir;
1463 }
1464
Jyri Sarha4023fe62013-10-18 18:37:43 +03001465 ret = of_property_match_string(np, "dma-names", "tx");
1466 if (ret < 0)
1467 goto nodata;
1468
1469 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1470 &dma_spec);
1471 if (ret < 0)
1472 goto nodata;
1473
1474 pdata->tx_dma_channel = dma_spec.args[0];
1475
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001476 /* RX is not valid in DIT mode */
1477 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1478 ret = of_property_match_string(np, "dma-names", "rx");
1479 if (ret < 0)
1480 goto nodata;
Jyri Sarha4023fe62013-10-18 18:37:43 +03001481
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001482 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1483 &dma_spec);
1484 if (ret < 0)
1485 goto nodata;
Jyri Sarha4023fe62013-10-18 18:37:43 +03001486
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001487 pdata->rx_dma_channel = dma_spec.args[0];
1488 }
Jyri Sarha4023fe62013-10-18 18:37:43 +03001489
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301490 ret = of_property_read_u32(np, "tx-num-evt", &val);
1491 if (ret >= 0)
1492 pdata->txnumevt = val;
1493
1494 ret = of_property_read_u32(np, "rx-num-evt", &val);
1495 if (ret >= 0)
1496 pdata->rxnumevt = val;
1497
1498 ret = of_property_read_u32(np, "sram-size-playback", &val);
1499 if (ret >= 0)
1500 pdata->sram_size_playback = val;
1501
1502 ret = of_property_read_u32(np, "sram-size-capture", &val);
1503 if (ret >= 0)
1504 pdata->sram_size_capture = val;
1505
1506 return pdata;
1507
1508nodata:
1509 if (ret < 0) {
1510 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1511 ret);
1512 pdata = NULL;
1513 }
1514 return pdata;
1515}
1516
Jyri Sarha5935a052015-04-23 16:16:05 +03001517/* All serializers must have equal number of channels */
1518static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp,
1519 struct snd_pcm_hw_constraint_list *cl,
1520 int serializers)
1521{
1522 unsigned int *list;
1523 int i, count = 0;
1524
1525 if (serializers <= 1)
1526 return 0;
1527
1528 list = devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
1529 (mcasp->tdm_slots + serializers - 2),
1530 GFP_KERNEL);
1531 if (!list)
1532 return -ENOMEM;
1533
1534 for (i = 2; i <= mcasp->tdm_slots; i++)
1535 list[count++] = i;
1536
1537 for (i = 2; i <= serializers; i++)
1538 list[count++] = i*mcasp->tdm_slots;
1539
1540 cl->count = count;
1541 cl->list = list;
1542
1543 return 0;
1544}
1545
1546
1547static int davinci_mcasp_init_ch_constraints(struct davinci_mcasp *mcasp)
1548{
1549 int rx_serializers = 0, tx_serializers = 0, ret, i;
1550
1551 for (i = 0; i < mcasp->num_serializer; i++)
1552 if (mcasp->serial_dir[i] == TX_MODE)
1553 tx_serializers++;
1554 else if (mcasp->serial_dir[i] == RX_MODE)
1555 rx_serializers++;
1556
1557 ret = davinci_mcasp_ch_constraint(mcasp, &mcasp->chconstr[
1558 SNDRV_PCM_STREAM_PLAYBACK],
1559 tx_serializers);
1560 if (ret)
1561 return ret;
1562
1563 ret = davinci_mcasp_ch_constraint(mcasp, &mcasp->chconstr[
1564 SNDRV_PCM_STREAM_CAPTURE],
1565 rx_serializers);
1566
1567 return ret;
1568}
1569
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001570static int davinci_mcasp_probe(struct platform_device *pdev)
1571{
Peter Ujfalusi8de131f2014-03-14 16:42:46 +02001572 struct snd_dmaengine_dai_dma_data *dma_data;
Jyri Sarha256ba182013-10-18 18:37:42 +03001573 struct resource *mem, *ioarea, *res, *dat;
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001574 struct davinci_mcasp_pdata *pdata;
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001575 struct davinci_mcasp *mcasp;
Misael Lopez Cruza7a33242014-11-12 16:38:05 +02001576 char *irq_name;
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001577 int *dma;
Misael Lopez Cruza7a33242014-11-12 16:38:05 +02001578 int irq;
Julia Lawall96d31e22011-12-29 17:51:21 +01001579 int ret;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001580
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301581 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1582 dev_err(&pdev->dev, "No platform data supplied\n");
1583 return -EINVAL;
1584 }
1585
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001586 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
Julia Lawall96d31e22011-12-29 17:51:21 +01001587 GFP_KERNEL);
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001588 if (!mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001589 return -ENOMEM;
1590
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301591 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1592 if (!pdata) {
1593 dev_err(&pdev->dev, "no platform data\n");
1594 return -EINVAL;
1595 }
1596
Jyri Sarha256ba182013-10-18 18:37:42 +03001597 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001598 if (!mem) {
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001599 dev_warn(mcasp->dev,
Jyri Sarha256ba182013-10-18 18:37:42 +03001600 "\"mpu\" mem resource not found, using index 0\n");
1601 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1602 if (!mem) {
1603 dev_err(&pdev->dev, "no mem resource?\n");
1604 return -ENODEV;
1605 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001606 }
1607
Julia Lawall96d31e22011-12-29 17:51:21 +01001608 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
Vaibhav Bediad852f4462011-02-09 18:39:52 +05301609 resource_size(mem), pdev->name);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001610 if (!ioarea) {
1611 dev_err(&pdev->dev, "Audio region already claimed\n");
Julia Lawall96d31e22011-12-29 17:51:21 +01001612 return -EBUSY;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001613 }
1614
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301615 pm_runtime_enable(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001616
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001617 mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1618 if (!mcasp->base) {
Vaibhav Bedia4f82f022011-02-09 18:39:54 +05301619 dev_err(&pdev->dev, "ioremap failed\n");
1620 ret = -ENOMEM;
Peter Ujfalusib6bb3702014-04-22 14:03:13 +03001621 goto err;
Vaibhav Bedia4f82f022011-02-09 18:39:54 +05301622 }
1623
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001624 mcasp->op_mode = pdata->op_mode;
Peter Ujfalusi1a5923d2014-11-10 12:32:15 +02001625 /* sanity check for tdm slots parameter */
1626 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1627 if (pdata->tdm_slots < 2) {
1628 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1629 pdata->tdm_slots);
1630 mcasp->tdm_slots = 2;
1631 } else if (pdata->tdm_slots > 32) {
1632 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1633 pdata->tdm_slots);
1634 mcasp->tdm_slots = 32;
1635 } else {
1636 mcasp->tdm_slots = pdata->tdm_slots;
1637 }
1638 }
1639
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001640 mcasp->num_serializer = pdata->num_serializer;
Peter Ujfalusif114ce62014-10-01 16:02:12 +03001641#ifdef CONFIG_PM_SLEEP
1642 mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev,
1643 sizeof(u32) * mcasp->num_serializer,
1644 GFP_KERNEL);
1645#endif
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001646 mcasp->serial_dir = pdata->serial_dir;
1647 mcasp->version = pdata->version;
1648 mcasp->txnumevt = pdata->txnumevt;
1649 mcasp->rxnumevt = pdata->rxnumevt;
Peter Ujfalusi487dce82013-11-14 11:35:31 +02001650
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001651 mcasp->dev = &pdev->dev;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001652
Peter Ujfalusi5a1b8a82014-12-30 16:10:32 +02001653 irq = platform_get_irq_byname(pdev, "common");
1654 if (irq >= 0) {
1655 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common\n",
1656 dev_name(&pdev->dev));
1657 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1658 davinci_mcasp_common_irq_handler,
Peter Ujfalusi8f511ff2015-02-02 14:38:32 +02001659 IRQF_ONESHOT | IRQF_SHARED,
1660 irq_name, mcasp);
Peter Ujfalusi5a1b8a82014-12-30 16:10:32 +02001661 if (ret) {
1662 dev_err(&pdev->dev, "common IRQ request failed\n");
1663 goto err;
1664 }
1665
1666 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1667 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1668 }
1669
Misael Lopez Cruza7a33242014-11-12 16:38:05 +02001670 irq = platform_get_irq_byname(pdev, "rx");
1671 if (irq >= 0) {
1672 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx\n",
1673 dev_name(&pdev->dev));
1674 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1675 davinci_mcasp_rx_irq_handler,
1676 IRQF_ONESHOT, irq_name, mcasp);
1677 if (ret) {
1678 dev_err(&pdev->dev, "RX IRQ request failed\n");
1679 goto err;
1680 }
1681
1682 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1683 }
1684
1685 irq = platform_get_irq_byname(pdev, "tx");
1686 if (irq >= 0) {
1687 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx\n",
1688 dev_name(&pdev->dev));
1689 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1690 davinci_mcasp_tx_irq_handler,
1691 IRQF_ONESHOT, irq_name, mcasp);
1692 if (ret) {
1693 dev_err(&pdev->dev, "TX IRQ request failed\n");
1694 goto err;
1695 }
1696
1697 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1698 }
1699
Jyri Sarha256ba182013-10-18 18:37:42 +03001700 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001701 if (dat)
1702 mcasp->dat_port = true;
Jyri Sarha256ba182013-10-18 18:37:42 +03001703
Peter Ujfalusi8de131f2014-03-14 16:42:46 +02001704 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001705 if (dat)
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001706 dma_data->addr = dat->start;
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001707 else
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001708 dma_data->addr = mem->start + pdata->tx_dma_offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001709
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001710 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001711 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
Jyri Sarha4023fe62013-10-18 18:37:43 +03001712 if (res)
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001713 *dma = res->start;
Jyri Sarha4023fe62013-10-18 18:37:43 +03001714 else
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001715 *dma = pdata->tx_dma_channel;
Troy Kisky92e2a6f2009-09-11 14:29:03 -07001716
Peter Ujfalusi8de131f2014-03-14 16:42:46 +02001717 /* dmaengine filter data for DT and non-DT boot */
1718 if (pdev->dev.of_node)
1719 dma_data->filter_data = "tx";
1720 else
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001721 dma_data->filter_data = dma;
Peter Ujfalusi8de131f2014-03-14 16:42:46 +02001722
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001723 /* RX is not valid in DIT mode */
1724 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001725 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001726 if (dat)
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001727 dma_data->addr = dat->start;
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001728 else
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001729 dma_data->addr = mem->start + pdata->rx_dma_offset;
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001730
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001731 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001732 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1733 if (res)
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001734 *dma = res->start;
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001735 else
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001736 *dma = pdata->rx_dma_channel;
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001737
1738 /* dmaengine filter data for DT and non-DT boot */
1739 if (pdev->dev.of_node)
1740 dma_data->filter_data = "rx";
1741 else
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001742 dma_data->filter_data = dma;
Peter Ujfalusicaa1d792015-02-02 14:38:33 +02001743 }
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001744
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001745 if (mcasp->version < MCASP_VERSION_3) {
1746 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
Peter Ujfalusi64ebdec2014-03-07 15:03:55 +02001747 /* dma_params->dma_addr is pointing to the data port address */
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001748 mcasp->dat_port = true;
1749 } else {
1750 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1751 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001752
Jyri Sarha5935a052015-04-23 16:16:05 +03001753 ret = davinci_mcasp_init_ch_constraints(mcasp);
1754 if (ret)
1755 goto err;
1756
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001757 dev_set_drvdata(&pdev->dev, mcasp);
Peter Ujfalusiae726e92013-11-14 11:35:35 +02001758
1759 mcasp_reparent_fck(pdev);
1760
Peter Ujfalusib6bb3702014-04-22 14:03:13 +03001761 ret = devm_snd_soc_register_component(&pdev->dev,
1762 &davinci_mcasp_component,
1763 &davinci_mcasp_dai[pdata->op_mode], 1);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001764
1765 if (ret != 0)
Peter Ujfalusib6bb3702014-04-22 14:03:13 +03001766 goto err;
Hebbar, Gururajaf08095a2012-08-27 18:56:39 +05301767
Peter Ujfalusid5c6c592014-04-16 15:46:20 +03001768 switch (mcasp->version) {
Peter Ujfalusif3f9cfa2014-07-16 15:12:04 +03001769#if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
1770 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1771 IS_MODULE(CONFIG_SND_EDMA_SOC))
Peter Ujfalusi9759e7e2015-03-03 16:45:20 +02001772 case MCASP_VERSION_1:
1773 case MCASP_VERSION_2:
Peter Ujfalusif3f9cfa2014-07-16 15:12:04 +03001774 case MCASP_VERSION_3:
1775 ret = edma_pcm_platform_register(&pdev->dev);
1776 break;
1777#endif
Jyri Sarha7f28f352014-06-13 12:49:59 +03001778#if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
1779 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1780 IS_MODULE(CONFIG_SND_OMAP_SOC))
Peter Ujfalusid5c6c592014-04-16 15:46:20 +03001781 case MCASP_VERSION_4:
1782 ret = omap_pcm_platform_register(&pdev->dev);
1783 break;
Jyri Sarha7f28f352014-06-13 12:49:59 +03001784#endif
Peter Ujfalusid5c6c592014-04-16 15:46:20 +03001785 default:
1786 dev_err(&pdev->dev, "Invalid McASP version: %d\n",
1787 mcasp->version);
1788 ret = -EINVAL;
1789 break;
1790 }
1791
1792 if (ret) {
1793 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
Peter Ujfalusib6bb3702014-04-22 14:03:13 +03001794 goto err;
Hebbar, Gururajaf08095a2012-08-27 18:56:39 +05301795 }
1796
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001797 return 0;
1798
Peter Ujfalusib6bb3702014-04-22 14:03:13 +03001799err:
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301800 pm_runtime_disable(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001801 return ret;
1802}
1803
1804static int davinci_mcasp_remove(struct platform_device *pdev)
1805{
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301806 pm_runtime_disable(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001807
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001808 return 0;
1809}
1810
1811static struct platform_driver davinci_mcasp_driver = {
1812 .probe = davinci_mcasp_probe,
1813 .remove = davinci_mcasp_remove,
1814 .driver = {
1815 .name = "davinci-mcasp",
Sachin Kamatea421eb2013-05-22 16:53:37 +05301816 .of_match_table = mcasp_dt_ids,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001817 },
1818};
1819
Axel Linf9b8a512011-11-25 10:09:27 +08001820module_platform_driver(davinci_mcasp_driver);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001821
1822MODULE_AUTHOR("Steve Chen");
1823MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1824MODULE_LICENSE("GPL");