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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Jesse Barnes5669fca2009-02-17 15:13:31 -080030#include <linux/device.h>
David Howells760285e2012-10-02 18:01:07 +010031#include <drm/drmP.h>
32#include <drm/i915_drm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070033#include "i915_drv.h"
Chris Wilson990bbda2012-07-02 11:51:02 -030034#include "i915_trace.h"
Kenneth Graunkef49f0582010-09-11 01:19:14 -070035#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070036
Jesse Barnes79e53942008-11-07 14:24:08 -080037#include <linux/console.h>
Paul Gortmakere0cd3602011-08-30 11:04:30 -040038#include <linux/module.h>
David Howells760285e2012-10-02 18:01:07 +010039#include <drm/drm_crtc_helper.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080040
Ben Widawskya35d9d32011-07-13 14:38:17 -070041static int i915_modeset __read_mostly = -1;
Jesse Barnes79e53942008-11-07 14:24:08 -080042module_param_named(modeset, i915_modeset, int, 0400);
Ben Widawsky6e96e772011-07-13 14:38:18 -070043MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
Jesse Barnes79e53942008-11-07 14:24:08 -080046
Ben Widawskya35d9d32011-07-13 14:38:17 -070047unsigned int i915_fbpercrtc __always_unused = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -080048module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
Linus Torvalds1da177e2005-04-16 15:20:36 -070049
Daniel Vettera7269152012-11-20 14:50:08 +010050int i915_panel_ignore_lid __read_mostly = 1;
Chris Wilsonfca87402011-02-17 13:44:48 +000051module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -070052MODULE_PARM_DESC(panel_ignore_lid,
Daniel Vettera7269152012-11-20 14:50:08 +010053 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
54 "-1=force lid closed, -2=force lid open)");
Chris Wilsonfca87402011-02-17 13:44:48 +000055
Ben Widawskya35d9d32011-07-13 14:38:17 -070056unsigned int i915_powersave __read_mostly = 1;
Chris Wilson0aa99272010-11-02 09:20:50 +000057module_param_named(powersave, i915_powersave, int, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -070058MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
Jesse Barnes652c3932009-08-17 13:31:43 -070060
Eugeni Dodonovf45b5552011-12-09 17:16:37 -080061int i915_semaphores __read_mostly = -1;
Chris Wilsona1656b92011-03-04 18:48:03 +000062module_param_named(semaphores, i915_semaphores, int, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -070063MODULE_PARM_DESC(semaphores,
Eugeni Dodonovf45b5552011-12-09 17:16:37 -080064 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
Chris Wilsona1656b92011-03-04 18:48:03 +000065
Keith Packardc0f372b32011-11-16 22:24:52 -080066int i915_enable_rc6 __read_mostly = -1;
Jesse Barnesf57f9c12012-04-11 09:39:02 -070067module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
Ben Widawsky6e96e772011-07-13 14:38:18 -070068MODULE_PARM_DESC(i915_enable_rc6,
Eugeni Dodonov83b7f9a2012-03-23 11:57:18 -030069 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
Chris Wilsonac668082011-02-09 16:15:32 +000074
Keith Packard4415e632011-11-09 09:57:50 -080075int i915_enable_fbc __read_mostly = -1;
Jesse Barnesc1a9f042011-05-05 15:24:21 -070076module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -070077MODULE_PARM_DESC(i915_enable_fbc,
78 "Enable frame buffer compression for power savings "
Keith Packardcd0de032011-09-19 21:34:19 -070079 "(default: -1 (use per-chip default))");
Jesse Barnesc1a9f042011-05-05 15:24:21 -070080
Ben Widawskya35d9d32011-07-13 14:38:17 -070081unsigned int i915_lvds_downclock __read_mostly = 0;
Jesse Barnes33814342010-01-14 20:48:02 +000082module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
Ben Widawsky6e96e772011-07-13 14:38:18 -070083MODULE_PARM_DESC(lvds_downclock,
84 "Use panel (LVDS/eDP) downclocking for power savings "
85 "(default: false)");
Jesse Barnes33814342010-01-14 20:48:02 +000086
Takashi Iwai121d5272012-03-20 13:07:06 +010087int i915_lvds_channel_mode __read_mostly;
88module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
89MODULE_PARM_DESC(lvds_channel_mode,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
92
Keith Packard4415e632011-11-09 09:57:50 -080093int i915_panel_use_ssc __read_mostly = -1;
Chris Wilsona7615032011-01-12 17:04:08 +000094module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -070095MODULE_PARM_DESC(lvds_use_ssc,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
Keith Packard72bbe582011-09-26 16:09:45 -070097 "(default: auto from VBT)");
Chris Wilsona7615032011-01-12 17:04:08 +000098
Ben Widawskya35d9d32011-07-13 14:38:17 -070099int i915_vbt_sdvo_panel_type __read_mostly = -1;
Chris Wilson5a1e5b62011-01-29 16:50:25 +0000100module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -0700101MODULE_PARM_DESC(vbt_sdvo_panel_type,
Mathias Fröhlichc10e4082012-03-01 06:44:35 +0100102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
Chris Wilson5a1e5b62011-01-29 16:50:25 +0000104
Ben Widawskya35d9d32011-07-13 14:38:17 -0700105static bool i915_try_reset __read_mostly = true;
Chris Wilsond78cb502010-12-23 13:33:15 +0000106module_param_named(reset, i915_try_reset, bool, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -0700107MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
Chris Wilsond78cb502010-12-23 13:33:15 +0000108
Ben Widawskya35d9d32011-07-13 14:38:17 -0700109bool i915_enable_hangcheck __read_mostly = true;
Ben Widawsky3e0dc6b2011-06-29 10:26:42 -0700110module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
Ben Widawsky6e96e772011-07-13 14:38:18 -0700111MODULE_PARM_DESC(enable_hangcheck,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
114 "(default: true)");
Ben Widawsky3e0dc6b2011-06-29 10:26:42 -0700115
Daniel Vetter650dc072012-04-02 10:08:35 +0200116int i915_enable_ppgtt __read_mostly = -1;
117module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
Daniel Vettere21af882012-02-09 20:53:27 +0100118MODULE_PARM_DESC(i915_enable_ppgtt,
119 "Enable PPGTT (default: true)");
120
Rodrigo Vivi0a3af262012-10-15 17:16:23 -0300121unsigned int i915_preliminary_hw_support __read_mostly = 0;
122module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
123MODULE_PARM_DESC(preliminary_hw_support,
124 "Enable preliminary hardware support. "
125 "Enable Haswell and ValleyView Support. "
126 "(default: false)");
127
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500128static struct drm_driver driver;
Zhenyu Wang1f7a6e32010-02-23 14:05:24 +0800129extern int intel_agp_enabled;
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500130
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500131#define INTEL_VGA_DEVICE(id, info) { \
Daniel Vetter80a29012011-10-11 10:59:05 +0200132 .class = PCI_BASE_CLASS_DISPLAY << 16, \
Chris Wilson934f9922011-01-20 13:09:12 +0000133 .class_mask = 0xff0000, \
Kristian Høgsberg49ae35f2009-12-16 15:16:15 -0500134 .vendor = 0x8086, \
135 .device = id, \
136 .subvendor = PCI_ANY_ID, \
137 .subdevice = PCI_ANY_ID, \
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500138 .driver_data = (unsigned long) info }
Kristian Høgsberg49ae35f2009-12-16 15:16:15 -0500139
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200140static const struct intel_device_info intel_i830_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100141 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100142 .has_overlay = 1, .overlay_needs_physical = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500143};
144
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200145static const struct intel_device_info intel_845g_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100146 .gen = 2,
Chris Wilson315781482010-08-12 09:42:51 +0100147 .has_overlay = 1, .overlay_needs_physical = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500148};
149
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200150static const struct intel_device_info intel_i85x_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100151 .gen = 2, .is_i85x = 1, .is_mobile = 1,
Adam Jackson5ce8ba72010-04-15 14:03:30 -0400152 .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100153 .has_overlay = 1, .overlay_needs_physical = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500154};
155
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200156static const struct intel_device_info intel_i865g_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100157 .gen = 2,
Chris Wilson315781482010-08-12 09:42:51 +0100158 .has_overlay = 1, .overlay_needs_physical = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500159};
160
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200161static const struct intel_device_info intel_i915g_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100162 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100163 .has_overlay = 1, .overlay_needs_physical = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500164};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200165static const struct intel_device_info intel_i915gm_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100166 .gen = 3, .is_mobile = 1,
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -0500167 .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100168 .has_overlay = 1, .overlay_needs_physical = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100169 .supports_tv = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500170};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200171static const struct intel_device_info intel_i945g_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100172 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100173 .has_overlay = 1, .overlay_needs_physical = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500174};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200175static const struct intel_device_info intel_i945gm_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100176 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -0500177 .has_hotplug = 1, .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100178 .has_overlay = 1, .overlay_needs_physical = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100179 .supports_tv = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500180};
181
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200182static const struct intel_device_info intel_i965g_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100183 .gen = 4, .is_broadwater = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100184 .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100185 .has_overlay = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500186};
187
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200188static const struct intel_device_info intel_i965gm_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100189 .gen = 4, .is_crestline = 1,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000190 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100191 .has_overlay = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100192 .supports_tv = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500193};
194
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200195static const struct intel_device_info intel_g33_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100196 .gen = 3, .is_g33 = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100197 .need_gfx_hws = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100198 .has_overlay = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500199};
200
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200201static const struct intel_device_info intel_g45_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100202 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100203 .has_pipe_cxsr = 1, .has_hotplug = 1,
Xiang, Haihao92f49d92010-09-16 10:43:10 +0800204 .has_bsd_ring = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500205};
206
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200207static const struct intel_device_info intel_gm45_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100208 .gen = 4, .is_g4x = 1,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000209 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100210 .has_pipe_cxsr = 1, .has_hotplug = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100211 .supports_tv = 1,
Xiang, Haihao92f49d92010-09-16 10:43:10 +0800212 .has_bsd_ring = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500213};
214
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200215static const struct intel_device_info intel_pineview_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100216 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100217 .need_gfx_hws = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100218 .has_overlay = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500219};
220
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200221static const struct intel_device_info intel_ironlake_d_info = {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +0100222 .gen = 5,
Eugeni Dodonov5a117db2012-01-05 09:34:29 -0200223 .need_gfx_hws = 1, .has_hotplug = 1,
Xiang, Haihao92f49d92010-09-16 10:43:10 +0800224 .has_bsd_ring = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500225};
226
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200227static const struct intel_device_info intel_ironlake_m_info = {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +0100228 .gen = 5, .is_mobile = 1,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000229 .need_gfx_hws = 1, .has_hotplug = 1,
Jesse Barnesc1a9f042011-05-05 15:24:21 -0700230 .has_fbc = 1,
Xiang, Haihao92f49d92010-09-16 10:43:10 +0800231 .has_bsd_ring = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500232};
233
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200234static const struct intel_device_info intel_sandybridge_d_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100235 .gen = 6,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100236 .need_gfx_hws = 1, .has_hotplug = 1,
Xiang, Haihao881f47b2010-09-19 14:40:43 +0100237 .has_bsd_ring = 1,
Chris Wilson549f7362010-10-19 11:19:32 +0100238 .has_blt_ring = 1,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200239 .has_llc = 1,
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200240 .has_force_wake = 1,
Eric Anholtf6e450a2009-11-02 12:08:22 -0800241};
242
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200243static const struct intel_device_info intel_sandybridge_m_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100244 .gen = 6, .is_mobile = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100245 .need_gfx_hws = 1, .has_hotplug = 1,
Yuanhan Liu9c04f012010-12-15 15:42:32 +0800246 .has_fbc = 1,
Xiang, Haihao881f47b2010-09-19 14:40:43 +0100247 .has_bsd_ring = 1,
Chris Wilson549f7362010-10-19 11:19:32 +0100248 .has_blt_ring = 1,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200249 .has_llc = 1,
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200250 .has_force_wake = 1,
Eric Anholta13e4092010-01-07 15:08:18 -0800251};
252
Jesse Barnesc76b6152011-04-28 14:32:07 -0700253static const struct intel_device_info intel_ivybridge_d_info = {
254 .is_ivybridge = 1, .gen = 7,
255 .need_gfx_hws = 1, .has_hotplug = 1,
256 .has_bsd_ring = 1,
257 .has_blt_ring = 1,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200258 .has_llc = 1,
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200259 .has_force_wake = 1,
Jesse Barnesc76b6152011-04-28 14:32:07 -0700260};
261
262static const struct intel_device_info intel_ivybridge_m_info = {
263 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
264 .need_gfx_hws = 1, .has_hotplug = 1,
265 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
266 .has_bsd_ring = 1,
267 .has_blt_ring = 1,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200268 .has_llc = 1,
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200269 .has_force_wake = 1,
Jesse Barnesc76b6152011-04-28 14:32:07 -0700270};
271
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700272static const struct intel_device_info intel_valleyview_m_info = {
273 .gen = 7, .is_mobile = 1,
274 .need_gfx_hws = 1, .has_hotplug = 1,
275 .has_fbc = 0,
276 .has_bsd_ring = 1,
277 .has_blt_ring = 1,
278 .is_valleyview = 1,
279};
280
281static const struct intel_device_info intel_valleyview_d_info = {
282 .gen = 7,
283 .need_gfx_hws = 1, .has_hotplug = 1,
284 .has_fbc = 0,
285 .has_bsd_ring = 1,
286 .has_blt_ring = 1,
287 .is_valleyview = 1,
288};
289
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -0300290static const struct intel_device_info intel_haswell_d_info = {
291 .is_haswell = 1, .gen = 7,
292 .need_gfx_hws = 1, .has_hotplug = 1,
293 .has_bsd_ring = 1,
294 .has_blt_ring = 1,
295 .has_llc = 1,
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200296 .has_force_wake = 1,
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -0300297};
298
299static const struct intel_device_info intel_haswell_m_info = {
300 .is_haswell = 1, .gen = 7, .is_mobile = 1,
301 .need_gfx_hws = 1, .has_hotplug = 1,
302 .has_bsd_ring = 1,
303 .has_blt_ring = 1,
304 .has_llc = 1,
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200305 .has_force_wake = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500306};
307
Chris Wilson6103da02010-07-05 18:01:47 +0100308static const struct pci_device_id pciidlist[] = { /* aka */
309 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
310 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
311 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
Adam Jackson5ce8ba72010-04-15 14:03:30 -0400312 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
Chris Wilson6103da02010-07-05 18:01:47 +0100313 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
314 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
315 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
316 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
317 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
318 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
319 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
320 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
321 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
322 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
323 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
324 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
325 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
326 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
327 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
328 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
329 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
330 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
331 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
332 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
333 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
334 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
Chris Wilson41a51422010-09-17 08:22:30 +0100335 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500336 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
337 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
338 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
339 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
Eric Anholtf6e450a2009-11-02 12:08:22 -0800340 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
Zhenyu Wang85540482010-09-07 13:45:32 +0800341 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
342 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
Eric Anholta13e4092010-01-07 15:08:18 -0800343 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
Zhenyu Wang85540482010-09-07 13:45:32 +0800344 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
Zhenyu Wang4fefe432010-08-19 09:46:16 +0800345 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
Zhenyu Wang85540482010-09-07 13:45:32 +0800346 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
Jesse Barnesc76b6152011-04-28 14:32:07 -0700347 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
348 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
349 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
350 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
351 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
Eugeni Dodonovcc22a932012-03-29 20:55:48 -0300352 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
Eugeni Dodonovc14f5282012-05-09 15:37:32 -0300353 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
354 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
Paulo Zanonida612d82012-08-06 18:45:01 -0300355 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
Eugeni Dodonovc14f5282012-05-09 15:37:32 -0300356 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
357 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
Paulo Zanonida612d82012-08-06 18:45:01 -0300358 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
Eugeni Dodonovc14f5282012-05-09 15:37:32 -0300359 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
360 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
Paulo Zanonida612d82012-08-06 18:45:01 -0300361 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
362 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
363 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
364 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
365 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
366 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
367 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
368 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
369 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
370 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
371 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
372 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
373 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
374 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
375 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
376 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
377 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
378 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
379 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
380 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
381 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
382 INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
383 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
384 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
385 INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
386 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
387 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
388 INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
Jesse Barnesff049b62012-06-20 10:53:13 -0700389 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
390 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
391 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
Kristian Høgsberg49ae35f2009-12-16 15:16:15 -0500392 {0, 0, 0}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700393};
394
Jesse Barnes79e53942008-11-07 14:24:08 -0800395#if defined(CONFIG_DRM_I915_KMS)
396MODULE_DEVICE_TABLE(pci, pciidlist);
397#endif
398
Akshay Joshi0206e352011-08-16 15:34:10 -0400399void intel_detect_pch(struct drm_device *dev)
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800400{
401 struct drm_i915_private *dev_priv = dev->dev_private;
402 struct pci_dev *pch;
403
404 /*
405 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
406 * make graphics device passthrough work easy for VMM, that only
407 * need to expose ISA bridge to let driver know the real hardware
408 * underneath. This is a requirement from virtualization team.
409 */
410 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
411 if (pch) {
412 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
Paulo Zanoni17a303e2012-11-20 15:12:07 -0200413 unsigned short id;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800414 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
Paulo Zanoni17a303e2012-11-20 15:12:07 -0200415 dev_priv->pch_id = id;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800416
Jesse Barnes90711d52011-04-28 14:48:02 -0700417 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
418 dev_priv->pch_type = PCH_IBX;
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100419 dev_priv->num_pch_pll = 2;
Jesse Barnes90711d52011-04-28 14:48:02 -0700420 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100421 WARN_ON(!IS_GEN5(dev));
Jesse Barnes90711d52011-04-28 14:48:02 -0700422 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800423 dev_priv->pch_type = PCH_CPT;
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100424 dev_priv->num_pch_pll = 2;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800425 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100426 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
Jesse Barnesc7925132011-04-07 12:33:56 -0700427 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
428 /* PantherPoint is CPT compatible */
429 dev_priv->pch_type = PCH_CPT;
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100430 dev_priv->num_pch_pll = 2;
Jesse Barnesc7925132011-04-07 12:33:56 -0700431 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100432 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300433 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
434 dev_priv->pch_type = PCH_LPT;
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100435 dev_priv->num_pch_pll = 0;
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300436 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100437 WARN_ON(!IS_HASWELL(dev));
Wei Shun Changae6935d2012-11-12 18:54:13 -0200438 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
439 dev_priv->pch_type = PCH_LPT;
440 dev_priv->num_pch_pll = 0;
441 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
442 WARN_ON(!IS_HASWELL(dev));
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800443 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100444 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800445 }
446 pci_dev_put(pch);
447 }
448}
449
Ben Widawsky2911a352012-04-05 14:47:36 -0700450bool i915_semaphore_is_enabled(struct drm_device *dev)
451{
452 if (INTEL_INFO(dev)->gen < 6)
453 return 0;
454
455 if (i915_semaphores >= 0)
456 return i915_semaphores;
457
Daniel Vetter59de3292012-04-02 20:48:43 +0200458#ifdef CONFIG_INTEL_IOMMU
Ben Widawsky2911a352012-04-05 14:47:36 -0700459 /* Enable semaphores on SNB when IO remapping is off */
Daniel Vetter59de3292012-04-02 20:48:43 +0200460 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
461 return false;
462#endif
Ben Widawsky2911a352012-04-05 14:47:36 -0700463
464 return 1;
465}
466
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100467static int i915_drm_freeze(struct drm_device *dev)
468{
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100469 struct drm_i915_private *dev_priv = dev->dev_private;
470
Dave Airlie5bcf7192010-12-07 09:20:40 +1000471 drm_kms_helper_poll_disable(dev);
472
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100473 pci_save_state(dev->pdev);
474
475 /* If KMS is active, we do the leavevt stuff here */
476 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
477 int error = i915_gem_idle(dev);
478 if (error) {
479 dev_err(&dev->pdev->dev,
480 "GEM idle failed, resume might fail\n");
481 return error;
482 }
Daniel Vettera261b242012-07-26 19:21:47 +0200483
Jesse Barnes1a01ab32012-11-02 11:14:00 -0700484 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
485
Daniel Vettera261b242012-07-26 19:21:47 +0200486 intel_modeset_disable(dev);
487
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100488 drm_irq_uninstall(dev);
489 }
490
491 i915_save_state(dev);
492
Chris Wilson44834a62010-08-19 16:09:23 +0100493 intel_opregion_fini(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100494
495 /* Modeset on resume, not lid events */
496 dev_priv->modeset_on_lid = 0;
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100497
Dave Airlie3fa016a2012-03-28 10:48:49 +0100498 console_lock();
499 intel_fbdev_set_suspend(dev, 1);
500 console_unlock();
501
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100502 return 0;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100503}
504
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000505int i915_suspend(struct drm_device *dev, pm_message_t state)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100506{
507 int error;
508
509 if (!dev || !dev->dev_private) {
510 DRM_ERROR("dev: %p\n", dev);
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700511 DRM_ERROR("DRM not initialized, aborting suspend.\n");
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000512 return -ENODEV;
513 }
514
Dave Airlieb932ccb2008-02-20 10:02:20 +1000515 if (state.event == PM_EVENT_PRETHAW)
516 return 0;
517
Dave Airlie5bcf7192010-12-07 09:20:40 +1000518
519 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
520 return 0;
Chris Wilson6eecba32010-09-08 09:45:11 +0100521
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100522 error = i915_drm_freeze(dev);
523 if (error)
524 return error;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000525
Dave Airlieb932ccb2008-02-20 10:02:20 +1000526 if (state.event == PM_EVENT_SUSPEND) {
527 /* Shut down the device */
528 pci_disable_device(dev->pdev);
529 pci_set_power_state(dev->pdev, PCI_D3hot);
530 }
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000531
532 return 0;
533}
534
Jesse Barnes073f34d2012-11-02 11:13:59 -0700535void intel_console_resume(struct work_struct *work)
536{
537 struct drm_i915_private *dev_priv =
538 container_of(work, struct drm_i915_private,
539 console_resume_work);
540 struct drm_device *dev = dev_priv->dev;
541
542 console_lock();
543 intel_fbdev_set_suspend(dev, 0);
544 console_unlock();
545}
546
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700547static int __i915_drm_thaw(struct drm_device *dev)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000548{
Jesse Barnes5669fca2009-02-17 15:13:31 -0800549 struct drm_i915_private *dev_priv = dev->dev_private;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100550 int error = 0;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100551
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100552 i915_restore_state(dev);
Chris Wilson44834a62010-08-19 16:09:23 +0100553 intel_opregion_setup(dev);
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100554
Jesse Barnes5669fca2009-02-17 15:13:31 -0800555 /* KMS EnterVT equivalent */
556 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
Paulo Zanoni40579ab2012-07-03 15:57:33 -0300557 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
Chris Wilson1833b132012-05-09 11:56:28 +0100558 ironlake_init_pch_refclk(dev);
559
Jesse Barnes5669fca2009-02-17 15:13:31 -0800560 mutex_lock(&dev->struct_mutex);
561 dev_priv->mm.suspended = 0;
562
Daniel Vetterf691e2f2012-02-02 09:58:12 +0100563 error = i915_gem_init_hw(dev);
Jesse Barnes5669fca2009-02-17 15:13:31 -0800564 mutex_unlock(&dev->struct_mutex);
Jesse Barnes226485e2009-02-23 15:41:09 -0800565
Chris Wilson1833b132012-05-09 11:56:28 +0100566 intel_modeset_init_hw(dev);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +0100567 intel_modeset_setup_hw_state(dev, false);
Jesse Barnes226485e2009-02-23 15:41:09 -0800568 drm_irq_install(dev);
Jesse Barnesd5bb0812011-01-05 12:01:26 -0800569 }
Jesse Barnes1daed3f2011-01-05 12:01:25 -0800570
Chris Wilson44834a62010-08-19 16:09:23 +0100571 intel_opregion_init(dev);
572
Linus Torvaldsc9354c82009-11-02 09:29:55 -0800573 dev_priv->modeset_on_lid = 0;
Jesse Barnes06891e22009-09-14 10:58:48 -0700574
Jesse Barnes073f34d2012-11-02 11:13:59 -0700575 /*
576 * The console lock can be pretty contented on resume due
577 * to all the printk activity. Try to keep it out of the hot
578 * path of resume if possible.
579 */
580 if (console_trylock()) {
581 intel_fbdev_set_suspend(dev, 0);
582 console_unlock();
583 } else {
584 schedule_work(&dev_priv->console_resume_work);
585 }
586
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100587 return error;
588}
589
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700590static int i915_drm_thaw(struct drm_device *dev)
591{
592 int error = 0;
593
594 intel_gt_reset(dev);
595
596 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
597 mutex_lock(&dev->struct_mutex);
598 i915_gem_restore_gtt_mappings(dev);
599 mutex_unlock(&dev->struct_mutex);
600 }
601
602 __i915_drm_thaw(dev);
603
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100604 return error;
605}
606
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000607int i915_resume(struct drm_device *dev)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100608{
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700609 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson6eecba32010-09-08 09:45:11 +0100610 int ret;
611
Dave Airlie5bcf7192010-12-07 09:20:40 +1000612 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
613 return 0;
614
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100615 if (pci_enable_device(dev->pdev))
616 return -EIO;
617
618 pci_set_master(dev->pdev);
619
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700620 intel_gt_reset(dev);
621
622 /*
623 * Platforms with opregion should have sane BIOS, older ones (gen3 and
624 * earlier) need this since the BIOS might clear all our scratch PTEs.
625 */
626 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
627 !dev_priv->opregion.header) {
628 mutex_lock(&dev->struct_mutex);
629 i915_gem_restore_gtt_mappings(dev);
630 mutex_unlock(&dev->struct_mutex);
631 }
632
633 ret = __i915_drm_thaw(dev);
Chris Wilson6eecba32010-09-08 09:45:11 +0100634 if (ret)
635 return ret;
636
637 drm_kms_helper_poll_enable(dev);
638 return 0;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000639}
640
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200641static int i8xx_do_reset(struct drm_device *dev)
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100642{
643 struct drm_i915_private *dev_priv = dev->dev_private;
644
645 if (IS_I85X(dev))
646 return -ENODEV;
647
648 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
649 POSTING_READ(D_STATE);
650
651 if (IS_I830(dev) || IS_845G(dev)) {
652 I915_WRITE(DEBUG_RESET_I830,
653 DEBUG_RESET_DISPLAY |
654 DEBUG_RESET_RENDER |
655 DEBUG_RESET_FULL);
656 POSTING_READ(DEBUG_RESET_I830);
657 msleep(1);
658
659 I915_WRITE(DEBUG_RESET_I830, 0);
660 POSTING_READ(DEBUG_RESET_I830);
661 }
662
663 msleep(1);
664
665 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
666 POSTING_READ(D_STATE);
667
668 return 0;
669}
670
Kenneth Graunkef49f0582010-09-11 01:19:14 -0700671static int i965_reset_complete(struct drm_device *dev)
672{
673 u8 gdrst;
Kenneth Graunkeeeccdca2010-09-11 01:24:50 -0700674 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
Daniel Vetter5fe9fe82012-05-02 21:33:52 +0200675 return (gdrst & GRDOM_RESET_ENABLE) == 0;
Kenneth Graunkef49f0582010-09-11 01:19:14 -0700676}
677
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200678static int i965_do_reset(struct drm_device *dev)
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700679{
Daniel Vetter5ccce182012-04-27 15:17:45 +0200680 int ret;
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700681 u8 gdrst;
682
Chris Wilsonae681d92010-10-01 14:57:56 +0100683 /*
684 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
685 * well as the reset bit (GR/bit 0). Setting the GR bit
686 * triggers the reset; when done, the hardware will clear it.
687 */
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700688 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200689 pci_write_config_byte(dev->pdev, I965_GDRST,
Daniel Vetter5ccce182012-04-27 15:17:45 +0200690 gdrst | GRDOM_RENDER |
691 GRDOM_RESET_ENABLE);
692 ret = wait_for(i965_reset_complete(dev), 500);
693 if (ret)
694 return ret;
695
696 /* We can't reset render&media without also resetting display ... */
697 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
698 pci_write_config_byte(dev->pdev, I965_GDRST,
699 gdrst | GRDOM_MEDIA |
700 GRDOM_RESET_ENABLE);
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700701
702 return wait_for(i965_reset_complete(dev), 500);
703}
704
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200705static int ironlake_do_reset(struct drm_device *dev)
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700706{
707 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter5ccce182012-04-27 15:17:45 +0200708 u32 gdrst;
709 int ret;
710
711 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200712 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
Daniel Vetter5ccce182012-04-27 15:17:45 +0200713 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
714 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
715 if (ret)
716 return ret;
717
718 /* We can't reset render&media without also resetting display ... */
719 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
720 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
721 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700722 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700723}
724
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200725static int gen6_do_reset(struct drm_device *dev)
Eric Anholtcff458c2010-11-18 09:31:14 +0800726{
727 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packardb6e45f82012-01-06 11:34:04 -0800728 int ret;
729 unsigned long irqflags;
Eric Anholtcff458c2010-11-18 09:31:14 +0800730
Keith Packard286fed42012-01-06 11:44:11 -0800731 /* Hold gt_lock across reset to prevent any register access
732 * with forcewake not set correctly
733 */
Keith Packardb6e45f82012-01-06 11:34:04 -0800734 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
Keith Packard286fed42012-01-06 11:44:11 -0800735
736 /* Reset the chip */
737
738 /* GEN6_GDRST is not in the gt power well, no need to check
739 * for fifo space for the write or forcewake the chip for
740 * the read
741 */
742 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
743
744 /* Spin waiting for the device to ack the reset request */
745 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
746
747 /* If reset with a user forcewake, try to restore, otherwise turn it off */
Keith Packardb6e45f82012-01-06 11:34:04 -0800748 if (dev_priv->forcewake_count)
Chris Wilson990bbda2012-07-02 11:51:02 -0300749 dev_priv->gt.force_wake_get(dev_priv);
Keith Packard286fed42012-01-06 11:44:11 -0800750 else
Chris Wilson990bbda2012-07-02 11:51:02 -0300751 dev_priv->gt.force_wake_put(dev_priv);
Keith Packard286fed42012-01-06 11:44:11 -0800752
753 /* Restore fifo count */
754 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
755
Keith Packardb6e45f82012-01-06 11:34:04 -0800756 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
757 return ret;
Eric Anholtcff458c2010-11-18 09:31:14 +0800758}
759
Ben Widawsky8e96d9c2012-06-04 14:42:56 -0700760int intel_gpu_reset(struct drm_device *dev)
Daniel Vetter350d2702012-04-27 15:17:42 +0200761{
Daniel Vetter2b9dc9a2012-04-27 15:17:43 +0200762 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter350d2702012-04-27 15:17:42 +0200763 int ret = -ENODEV;
764
765 switch (INTEL_INFO(dev)->gen) {
766 case 7:
767 case 6:
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200768 ret = gen6_do_reset(dev);
Daniel Vetter350d2702012-04-27 15:17:42 +0200769 break;
770 case 5:
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200771 ret = ironlake_do_reset(dev);
Daniel Vetter350d2702012-04-27 15:17:42 +0200772 break;
773 case 4:
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200774 ret = i965_do_reset(dev);
Daniel Vetter350d2702012-04-27 15:17:42 +0200775 break;
776 case 2:
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200777 ret = i8xx_do_reset(dev);
Daniel Vetter350d2702012-04-27 15:17:42 +0200778 break;
779 }
780
Daniel Vetter2b9dc9a2012-04-27 15:17:43 +0200781 /* Also reset the gpu hangman. */
782 if (dev_priv->stop_rings) {
783 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
784 dev_priv->stop_rings = 0;
785 if (ret == -ENODEV) {
786 DRM_ERROR("Reset not implemented, but ignoring "
787 "error for simulated gpu hangs\n");
788 ret = 0;
789 }
790 }
791
Daniel Vetter350d2702012-04-27 15:17:42 +0200792 return ret;
793}
794
Ben Gamari11ed50e2009-09-14 17:48:45 -0400795/**
Eugeni Dodonovf3953dc2011-11-28 16:15:17 -0200796 * i915_reset - reset chip after a hang
Ben Gamari11ed50e2009-09-14 17:48:45 -0400797 * @dev: drm device to reset
Ben Gamari11ed50e2009-09-14 17:48:45 -0400798 *
799 * Reset the chip. Useful if a hang is detected. Returns zero on successful
800 * reset or otherwise an error code.
801 *
802 * Procedure is fairly simple:
803 * - reset the chip using the reset reg
804 * - re-init context state
805 * - re-init hardware status page
806 * - re-init ring buffer
807 * - re-init interrupt state
808 * - re-init display
809 */
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200810int i915_reset(struct drm_device *dev)
Ben Gamari11ed50e2009-09-14 17:48:45 -0400811{
812 drm_i915_private_t *dev_priv = dev->dev_private;
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700813 int ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400814
Chris Wilsond78cb502010-12-23 13:33:15 +0000815 if (!i915_try_reset)
816 return 0;
817
Daniel Vetterd54a02c2012-07-04 22:18:39 +0200818 mutex_lock(&dev->struct_mutex);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400819
Chris Wilson069efc12010-09-30 16:53:18 +0100820 i915_gem_reset(dev);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400821
Chris Wilsonf803aa52010-09-19 12:38:26 +0100822 ret = -ENODEV;
Daniel Vetter350d2702012-04-27 15:17:42 +0200823 if (get_seconds() - dev_priv->last_gpu_reset < 5)
Chris Wilsonae681d92010-10-01 14:57:56 +0100824 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
Daniel Vetter350d2702012-04-27 15:17:42 +0200825 else
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200826 ret = intel_gpu_reset(dev);
Daniel Vetter350d2702012-04-27 15:17:42 +0200827
Chris Wilsonae681d92010-10-01 14:57:56 +0100828 dev_priv->last_gpu_reset = get_seconds();
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700829 if (ret) {
Chris Wilsonf803aa52010-09-19 12:38:26 +0100830 DRM_ERROR("Failed to reset chip.\n");
Daniel J Bluemanf953c932010-05-17 14:23:52 +0100831 mutex_unlock(&dev->struct_mutex);
Chris Wilsonf803aa52010-09-19 12:38:26 +0100832 return ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400833 }
834
835 /* Ok, now get things going again... */
836
837 /*
838 * Everything depends on having the GTT running, so we need to start
839 * there. Fortunately we don't need to do this unless we reset the
840 * chip at a PCI level.
841 *
842 * Next we need to restore the context, but we don't use those
843 * yet either...
844 *
845 * Ring buffer needs to be re-initialized in the KMS case, or if X
846 * was running at the time of the reset (i.e. we weren't VT
847 * switched away).
848 */
849 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800850 !dev_priv->mm.suspended) {
Chris Wilsonb4519512012-05-11 14:29:30 +0100851 struct intel_ring_buffer *ring;
852 int i;
853
Ben Gamari11ed50e2009-09-14 17:48:45 -0400854 dev_priv->mm.suspended = 0;
Eric Anholt75a68982010-11-18 09:31:13 +0800855
Daniel Vetterf691e2f2012-02-02 09:58:12 +0100856 i915_gem_init_swizzling(dev);
857
Chris Wilsonb4519512012-05-11 14:29:30 +0100858 for_each_ring(ring, dev_priv, i)
859 ring->init(ring);
Eric Anholt75a68982010-11-18 09:31:13 +0800860
Ben Widawsky254f9652012-06-04 14:42:42 -0700861 i915_gem_context_init(dev);
Daniel Vettere21af882012-02-09 20:53:27 +0100862 i915_gem_init_ppgtt(dev);
863
Daniel Vetter8e88a2b2012-06-19 18:40:00 +0200864 /*
865 * It would make sense to re-init all the other hw state, at
866 * least the rps/rc6/emon init done within modeset_init_hw. For
867 * some unknown reason, this blows up my ilk, so don't.
868 */
Daniel Vetterf8175862012-04-10 15:50:11 +0200869
Daniel Vetter8e88a2b2012-06-19 18:40:00 +0200870 mutex_unlock(&dev->struct_mutex);
Daniel Vetterf8175862012-04-10 15:50:11 +0200871
Ben Gamari11ed50e2009-09-14 17:48:45 -0400872 drm_irq_uninstall(dev);
873 drm_irq_install(dev);
Daniel Vetterbcbc3242012-04-27 15:17:41 +0200874 } else {
875 mutex_unlock(&dev->struct_mutex);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400876 }
877
Ben Gamari11ed50e2009-09-14 17:48:45 -0400878 return 0;
879}
880
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500881static int __devinit
882i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
883{
Daniel Vetter01a06852012-06-25 15:58:49 +0200884 struct intel_device_info *intel_info =
885 (struct intel_device_info *) ent->driver_data;
886
Paulo Zanoni70b12bb2012-11-20 13:32:30 -0200887 if (intel_info->is_valleyview)
Rodrigo Vivi0a3af262012-10-15 17:16:23 -0300888 if(!i915_preliminary_hw_support) {
889 DRM_ERROR("Preliminary hardware support disabled\n");
890 return -ENODEV;
891 }
892
Chris Wilson5fe49d82011-02-01 19:43:02 +0000893 /* Only bind to function 0 of the device. Early generations
894 * used function 1 as a placeholder for multi-head. This causes
895 * us confusion instead, especially on the systems where both
896 * functions have the same PCI-ID!
897 */
898 if (PCI_FUNC(pdev->devfn))
899 return -ENODEV;
900
Daniel Vetter01a06852012-06-25 15:58:49 +0200901 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
902 * implementation for gen3 (and only gen3) that used legacy drm maps
903 * (gasp!) to share buffers between X and the client. Hence we need to
904 * keep around the fake agp stuff for gen3, even when kms is enabled. */
905 if (intel_info->gen != 3) {
906 driver.driver_features &=
907 ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
908 } else if (!intel_agp_enabled) {
909 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
910 return -ENODEV;
911 }
912
Jordan Crousedcdb1672010-05-27 13:40:25 -0600913 return drm_get_pci_dev(pdev, ent, &driver);
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500914}
915
916static void
917i915_pci_remove(struct pci_dev *pdev)
918{
919 struct drm_device *dev = pci_get_drvdata(pdev);
920
921 drm_put_dev(dev);
922}
923
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100924static int i915_pm_suspend(struct device *dev)
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500925{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100926 struct pci_dev *pdev = to_pci_dev(dev);
927 struct drm_device *drm_dev = pci_get_drvdata(pdev);
928 int error;
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500929
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100930 if (!drm_dev || !drm_dev->dev_private) {
931 dev_err(dev, "DRM not initialized, aborting suspend.\n");
932 return -ENODEV;
933 }
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500934
Dave Airlie5bcf7192010-12-07 09:20:40 +1000935 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
936 return 0;
937
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100938 error = i915_drm_freeze(drm_dev);
939 if (error)
940 return error;
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500941
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100942 pci_disable_device(pdev);
943 pci_set_power_state(pdev, PCI_D3hot);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800944
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800945 return 0;
946}
947
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100948static int i915_pm_resume(struct device *dev)
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800949{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100950 struct pci_dev *pdev = to_pci_dev(dev);
951 struct drm_device *drm_dev = pci_get_drvdata(pdev);
952
953 return i915_resume(drm_dev);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800954}
955
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100956static int i915_pm_freeze(struct device *dev)
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800957{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100958 struct pci_dev *pdev = to_pci_dev(dev);
959 struct drm_device *drm_dev = pci_get_drvdata(pdev);
960
961 if (!drm_dev || !drm_dev->dev_private) {
962 dev_err(dev, "DRM not initialized, aborting suspend.\n");
963 return -ENODEV;
964 }
965
966 return i915_drm_freeze(drm_dev);
967}
968
969static int i915_pm_thaw(struct device *dev)
970{
971 struct pci_dev *pdev = to_pci_dev(dev);
972 struct drm_device *drm_dev = pci_get_drvdata(pdev);
973
974 return i915_drm_thaw(drm_dev);
975}
976
977static int i915_pm_poweroff(struct device *dev)
978{
979 struct pci_dev *pdev = to_pci_dev(dev);
980 struct drm_device *drm_dev = pci_get_drvdata(pdev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100981
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100982 return i915_drm_freeze(drm_dev);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800983}
984
Chris Wilsonb4b78d12010-06-06 15:40:20 +0100985static const struct dev_pm_ops i915_pm_ops = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400986 .suspend = i915_pm_suspend,
987 .resume = i915_pm_resume,
988 .freeze = i915_pm_freeze,
989 .thaw = i915_pm_thaw,
990 .poweroff = i915_pm_poweroff,
991 .restore = i915_pm_resume,
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800992};
993
Laurent Pinchart78b68552012-05-17 13:27:22 +0200994static const struct vm_operations_struct i915_gem_vm_ops = {
Jesse Barnesde151cf2008-11-12 10:03:55 -0800995 .fault = i915_gem_fault,
Jesse Barnesab00b3e2009-02-11 14:01:46 -0800996 .open = drm_gem_vm_open,
997 .close = drm_gem_vm_close,
Jesse Barnesde151cf2008-11-12 10:03:55 -0800998};
999
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001000static const struct file_operations i915_driver_fops = {
1001 .owner = THIS_MODULE,
1002 .open = drm_open,
1003 .release = drm_release,
1004 .unlocked_ioctl = drm_ioctl,
1005 .mmap = drm_gem_mmap,
1006 .poll = drm_poll,
1007 .fasync = drm_fasync,
1008 .read = drm_read,
1009#ifdef CONFIG_COMPAT
1010 .compat_ioctl = i915_compat_ioctl,
1011#endif
1012 .llseek = noop_llseek,
1013};
1014
Linus Torvalds1da177e2005-04-16 15:20:36 -07001015static struct drm_driver driver = {
Michael Witten0c547812011-08-25 17:55:54 +00001016 /* Don't use MTRRs here; the Xserver or userspace app should
1017 * deal with them for Intel hardware.
Dave Airlie792d2b92005-11-11 23:30:27 +11001018 */
Eric Anholt673a3942008-07-30 12:06:12 -07001019 .driver_features =
1020 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
Daniel Vetter1286ff72012-05-10 15:25:09 +02001021 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
Dave Airlie22eae942005-11-10 22:16:34 +11001022 .load = i915_driver_load,
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001023 .unload = i915_driver_unload,
Eric Anholt673a3942008-07-30 12:06:12 -07001024 .open = i915_driver_open,
Dave Airlie22eae942005-11-10 22:16:34 +11001025 .lastclose = i915_driver_lastclose,
1026 .preclose = i915_driver_preclose,
Eric Anholt673a3942008-07-30 12:06:12 -07001027 .postclose = i915_driver_postclose,
Rafael J. Wysockid8e29202010-01-09 00:45:33 +01001028
1029 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1030 .suspend = i915_suspend,
1031 .resume = i915_resume,
1032
Dave Airliecda17382005-07-10 17:31:26 +10001033 .device_is_agp = i915_driver_device_is_agp,
Dave Airlie7c1c2872008-11-28 14:22:24 +10001034 .master_create = i915_master_create,
1035 .master_destroy = i915_master_destroy,
Ben Gamari955b12d2009-02-17 20:08:49 -05001036#if defined(CONFIG_DEBUG_FS)
Ben Gamari27c202a2009-07-01 22:26:52 -04001037 .debugfs_init = i915_debugfs_init,
1038 .debugfs_cleanup = i915_debugfs_cleanup,
Ben Gamari955b12d2009-02-17 20:08:49 -05001039#endif
Eric Anholt673a3942008-07-30 12:06:12 -07001040 .gem_init_object = i915_gem_init_object,
1041 .gem_free_object = i915_gem_free_object,
Jesse Barnesde151cf2008-11-12 10:03:55 -08001042 .gem_vm_ops = &i915_gem_vm_ops,
Daniel Vetter1286ff72012-05-10 15:25:09 +02001043
1044 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1045 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1046 .gem_prime_export = i915_gem_prime_export,
1047 .gem_prime_import = i915_gem_prime_import,
1048
Dave Airlieff72145b2011-02-07 12:16:14 +10001049 .dumb_create = i915_gem_dumb_create,
1050 .dumb_map_offset = i915_gem_mmap_gtt,
1051 .dumb_destroy = i915_gem_dumb_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001052 .ioctls = i915_ioctls,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001053 .fops = &i915_driver_fops,
Dave Airlie22eae942005-11-10 22:16:34 +11001054 .name = DRIVER_NAME,
1055 .desc = DRIVER_DESC,
1056 .date = DRIVER_DATE,
1057 .major = DRIVER_MAJOR,
1058 .minor = DRIVER_MINOR,
1059 .patchlevel = DRIVER_PATCHLEVEL,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001060};
1061
Dave Airlie8410ea32010-12-15 03:16:38 +10001062static struct pci_driver i915_pci_driver = {
1063 .name = DRIVER_NAME,
1064 .id_table = pciidlist,
1065 .probe = i915_pci_probe,
1066 .remove = i915_pci_remove,
1067 .driver.pm = &i915_pm_ops,
1068};
1069
Linus Torvalds1da177e2005-04-16 15:20:36 -07001070static int __init i915_init(void)
1071{
1072 driver.num_ioctls = i915_max_ioctl;
Jesse Barnes79e53942008-11-07 14:24:08 -08001073
1074 /*
1075 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1076 * explicitly disabled with the module pararmeter.
1077 *
1078 * Otherwise, just follow the parameter (defaulting to off).
1079 *
1080 * Allow optional vga_text_mode_force boot option to override
1081 * the default behavior.
1082 */
1083#if defined(CONFIG_DRM_I915_KMS)
1084 if (i915_modeset != 0)
1085 driver.driver_features |= DRIVER_MODESET;
1086#endif
1087 if (i915_modeset == 1)
1088 driver.driver_features |= DRIVER_MODESET;
1089
1090#ifdef CONFIG_VGA_CONSOLE
1091 if (vgacon_text_force() && i915_modeset == -1)
1092 driver.driver_features &= ~DRIVER_MODESET;
1093#endif
1094
Chris Wilson3885c6b2011-01-23 10:45:14 +00001095 if (!(driver.driver_features & DRIVER_MODESET))
1096 driver.get_vblank_timestamp = NULL;
1097
Dave Airlie8410ea32010-12-15 03:16:38 +10001098 return drm_pci_init(&driver, &i915_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001099}
1100
1101static void __exit i915_exit(void)
1102{
Dave Airlie8410ea32010-12-15 03:16:38 +10001103 drm_pci_exit(&driver, &i915_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001104}
1105
1106module_init(i915_init);
1107module_exit(i915_exit);
1108
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001109MODULE_AUTHOR(DRIVER_AUTHOR);
1110MODULE_DESCRIPTION(DRIVER_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001111MODULE_LICENSE("GPL and additional rights");
Andi Kleenf7000882011-10-13 16:08:51 -07001112
Jesse Barnesb7d84092012-03-22 14:38:43 -07001113/* We give fast paths for the really cool registers */
1114#define NEEDS_FORCE_WAKE(dev_priv, reg) \
Daniel Vetterb7884eb2012-06-04 11:18:15 +02001115 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1116 ((reg) < 0x40000) && \
1117 ((reg) != FORCEWAKE))
Jesse Barnesb7d84092012-03-22 14:38:43 -07001118
Jesse Barnesf7dff0c2012-06-15 11:55:17 -07001119static bool IS_DISPLAYREG(u32 reg)
1120{
1121 /*
1122 * This should make it easier to transition modules over to the
1123 * new register block scheme, since we can do it incrementally.
1124 */
Daniel Vettera7e806d2012-07-11 16:27:55 +02001125 if (reg >= VLV_DISPLAY_BASE)
Jesse Barnesf7dff0c2012-06-15 11:55:17 -07001126 return false;
1127
1128 if (reg >= RENDER_RING_BASE &&
1129 reg < RENDER_RING_BASE + 0xff)
1130 return false;
1131 if (reg >= GEN6_BSD_RING_BASE &&
1132 reg < GEN6_BSD_RING_BASE + 0xff)
1133 return false;
1134 if (reg >= BLT_RING_BASE &&
1135 reg < BLT_RING_BASE + 0xff)
1136 return false;
1137
1138 if (reg == PGTBL_ER)
1139 return false;
1140
1141 if (reg >= IPEIR_I965 &&
1142 reg < HWSTAM)
1143 return false;
1144
1145 if (reg == MI_MODE)
1146 return false;
1147
1148 if (reg == GFX_MODE_GEN7)
1149 return false;
1150
1151 if (reg == RENDER_HWS_PGA_GEN7 ||
1152 reg == BSD_HWS_PGA_GEN7 ||
1153 reg == BLT_HWS_PGA_GEN7)
1154 return false;
1155
1156 if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
1157 reg == GEN6_BSD_RNCID)
1158 return false;
1159
1160 if (reg == GEN6_BLITTER_ECOSKPD)
1161 return false;
1162
1163 if (reg >= 0x4000c &&
1164 reg <= 0x4002c)
1165 return false;
1166
1167 if (reg >= 0x4f000 &&
1168 reg <= 0x4f08f)
1169 return false;
1170
1171 if (reg >= 0x4f100 &&
1172 reg <= 0x4f11f)
1173 return false;
1174
1175 if (reg >= VLV_MASTER_IER &&
1176 reg <= GEN6_PMIER)
1177 return false;
1178
1179 if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
1180 reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
1181 return false;
1182
1183 if (reg >= VLV_IIR_RW &&
1184 reg <= VLV_ISR)
1185 return false;
1186
1187 if (reg == FORCEWAKE_VLV ||
1188 reg == FORCEWAKE_ACK_VLV)
1189 return false;
1190
1191 if (reg == GEN6_GDRST)
1192 return false;
1193
Jesse Barnes8ab43972012-10-25 12:15:42 -07001194 switch (reg) {
Jesse Barnes310c53a2012-10-25 12:15:48 -07001195 case _3D_CHICKEN3:
1196 case IVB_CHICKEN3:
1197 case GEN7_COMMON_SLICE_CHICKEN1:
1198 case GEN7_L3CNTLREG1:
1199 case GEN7_L3_CHICKEN_MODE_REGISTER:
Jesse Barnes8ab43972012-10-25 12:15:42 -07001200 case GEN7_ROW_CHICKEN2:
Jesse Barnes310c53a2012-10-25 12:15:48 -07001201 case GEN7_L3SQCREG4:
1202 case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
Jesse Barnes12f33822012-10-25 12:15:45 -07001203 case GEN7_HALF_SLICE_CHICKEN1:
Jesse Barnes310c53a2012-10-25 12:15:48 -07001204 case GEN6_MBCTL:
1205 case GEN6_UCGCTL2:
Jesse Barnes8ab43972012-10-25 12:15:42 -07001206 return false;
1207 default:
1208 break;
1209 }
1210
Jesse Barnesf7dff0c2012-06-15 11:55:17 -07001211 return true;
1212}
1213
Daniel Vettera8b13972012-10-18 14:16:09 +02001214static void
1215ilk_dummy_write(struct drm_i915_private *dev_priv)
1216{
1217 /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
1218 * chip from rc6 before touching it for real. MI_MODE is masked, hence
1219 * harmless to write 0 into. */
1220 I915_WRITE_NOTRACE(MI_MODE, 0);
1221}
1222
Andi Kleenf7000882011-10-13 16:08:51 -07001223#define __i915_read(x, y) \
1224u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1225 u##x val = 0; \
Daniel Vettera8b13972012-10-18 14:16:09 +02001226 if (IS_GEN5(dev_priv->dev)) \
1227 ilk_dummy_write(dev_priv); \
Andi Kleenf7000882011-10-13 16:08:51 -07001228 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
Keith Packardc9375042012-01-06 11:48:38 -08001229 unsigned long irqflags; \
1230 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1231 if (dev_priv->forcewake_count == 0) \
Chris Wilson990bbda2012-07-02 11:51:02 -03001232 dev_priv->gt.force_wake_get(dev_priv); \
Andi Kleenf7000882011-10-13 16:08:51 -07001233 val = read##y(dev_priv->regs + reg); \
Keith Packardc9375042012-01-06 11:48:38 -08001234 if (dev_priv->forcewake_count == 0) \
Chris Wilson990bbda2012-07-02 11:51:02 -03001235 dev_priv->gt.force_wake_put(dev_priv); \
Keith Packardc9375042012-01-06 11:48:38 -08001236 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
Jesse Barnesf7dff0c2012-06-15 11:55:17 -07001237 } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1238 val = read##y(dev_priv->regs + reg + 0x180000); \
Andi Kleenf7000882011-10-13 16:08:51 -07001239 } else { \
1240 val = read##y(dev_priv->regs + reg); \
1241 } \
1242 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1243 return val; \
1244}
1245
1246__i915_read(8, b)
1247__i915_read(16, w)
1248__i915_read(32, l)
1249__i915_read(64, q)
1250#undef __i915_read
1251
1252#define __i915_write(x, y) \
1253void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
Ben Widawsky67a37442012-02-09 10:15:20 +01001254 u32 __fifo_ret = 0; \
Andi Kleenf7000882011-10-13 16:08:51 -07001255 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1256 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
Ben Widawsky67a37442012-02-09 10:15:20 +01001257 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
Andi Kleenf7000882011-10-13 16:08:51 -07001258 } \
Daniel Vettera8b13972012-10-18 14:16:09 +02001259 if (IS_GEN5(dev_priv->dev)) \
1260 ilk_dummy_write(dev_priv); \
Paulo Zanonic54e5902012-11-20 13:27:38 -02001261 if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1262 DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
1263 I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
1264 } \
Jesse Barnesf7dff0c2012-06-15 11:55:17 -07001265 if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1266 write##y(val, dev_priv->regs + reg + 0x180000); \
1267 } else { \
1268 write##y(val, dev_priv->regs + reg); \
1269 } \
Ben Widawsky67a37442012-02-09 10:15:20 +01001270 if (unlikely(__fifo_ret)) { \
1271 gen6_gt_check_fifodbg(dev_priv); \
1272 } \
Ben Widawskyb4c145c2012-08-20 16:15:14 -07001273 if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1274 DRM_ERROR("Unclaimed write to %x\n", reg); \
1275 writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT); \
1276 } \
Andi Kleenf7000882011-10-13 16:08:51 -07001277}
1278__i915_write(8, b)
1279__i915_write(16, w)
1280__i915_write(32, l)
1281__i915_write(64, q)
1282#undef __i915_write
Ben Widawskyc0c7bab2012-07-12 11:01:05 -07001283
1284static const struct register_whitelist {
1285 uint64_t offset;
1286 uint32_t size;
1287 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1288} whitelist[] = {
1289 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1290};
1291
1292int i915_reg_read_ioctl(struct drm_device *dev,
1293 void *data, struct drm_file *file)
1294{
1295 struct drm_i915_private *dev_priv = dev->dev_private;
1296 struct drm_i915_reg_read *reg = data;
1297 struct register_whitelist const *entry = whitelist;
1298 int i;
1299
1300 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1301 if (entry->offset == reg->offset &&
1302 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1303 break;
1304 }
1305
1306 if (i == ARRAY_SIZE(whitelist))
1307 return -EINVAL;
1308
1309 switch (entry->size) {
1310 case 8:
1311 reg->val = I915_READ64(reg->offset);
1312 break;
1313 case 4:
1314 reg->val = I915_READ(reg->offset);
1315 break;
1316 case 2:
1317 reg->val = I915_READ16(reg->offset);
1318 break;
1319 case 1:
1320 reg->val = I915_READ8(reg->offset);
1321 break;
1322 default:
1323 WARN_ON(1);
1324 return -EINVAL;
1325 }
1326
1327 return 0;
1328}