Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008-2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Zou Nan hai <nanhai.zou@intel.com> |
| 26 | * Xiang Hai hao<haihao.xiang@intel.com> |
| 27 | * |
| 28 | */ |
| 29 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/drmP.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 31 | #include "i915_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 32 | #include <drm/i915_drm.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 33 | #include "i915_trace.h" |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 34 | #include "intel_drv.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 35 | |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 36 | /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill, |
| 37 | * but keeps the logic simple. Indeed, the whole purpose of this macro is just |
| 38 | * to give some inclination as to some of the magic values used in the various |
| 39 | * workarounds! |
| 40 | */ |
| 41 | #define CACHELINE_BYTES 64 |
| 42 | |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 43 | static inline int ring_space(struct intel_ring_buffer *ring) |
| 44 | { |
Ville Syrjälä | 633cf8f | 2012-12-03 18:43:32 +0200 | [diff] [blame] | 45 | int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE); |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 46 | if (space < 0) |
| 47 | space += ring->size; |
| 48 | return space; |
| 49 | } |
| 50 | |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 51 | static bool intel_ring_stopped(struct intel_ring_buffer *ring) |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 52 | { |
| 53 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 54 | return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring); |
| 55 | } |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 56 | |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 57 | void __intel_ring_advance(struct intel_ring_buffer *ring) |
| 58 | { |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 59 | ring->tail &= ring->size - 1; |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 60 | if (intel_ring_stopped(ring)) |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 61 | return; |
| 62 | ring->write_tail(ring, ring->tail); |
| 63 | } |
| 64 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 65 | static int |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 66 | gen2_render_ring_flush(struct intel_ring_buffer *ring, |
| 67 | u32 invalidate_domains, |
| 68 | u32 flush_domains) |
| 69 | { |
| 70 | u32 cmd; |
| 71 | int ret; |
| 72 | |
| 73 | cmd = MI_FLUSH; |
Daniel Vetter | 31b14c9 | 2012-04-19 16:45:22 +0200 | [diff] [blame] | 74 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 75 | cmd |= MI_NO_WRITE_FLUSH; |
| 76 | |
| 77 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 78 | cmd |= MI_READ_FLUSH; |
| 79 | |
| 80 | ret = intel_ring_begin(ring, 2); |
| 81 | if (ret) |
| 82 | return ret; |
| 83 | |
| 84 | intel_ring_emit(ring, cmd); |
| 85 | intel_ring_emit(ring, MI_NOOP); |
| 86 | intel_ring_advance(ring); |
| 87 | |
| 88 | return 0; |
| 89 | } |
| 90 | |
| 91 | static int |
| 92 | gen4_render_ring_flush(struct intel_ring_buffer *ring, |
| 93 | u32 invalidate_domains, |
| 94 | u32 flush_domains) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 95 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 96 | struct drm_device *dev = ring->dev; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 97 | u32 cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 98 | int ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 99 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 100 | /* |
| 101 | * read/write caches: |
| 102 | * |
| 103 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 104 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 105 | * also flushed at 2d versus 3d pipeline switches. |
| 106 | * |
| 107 | * read-only caches: |
| 108 | * |
| 109 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 110 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 111 | * |
| 112 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 113 | * |
| 114 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 115 | * invalidated when MI_EXE_FLUSH is set. |
| 116 | * |
| 117 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 118 | * invalidated with every MI_FLUSH. |
| 119 | * |
| 120 | * TLBs: |
| 121 | * |
| 122 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 123 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 124 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 125 | * are flushed at any MI_FLUSH. |
| 126 | */ |
| 127 | |
| 128 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 129 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 130 | cmd &= ~MI_NO_WRITE_FLUSH; |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 131 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 132 | cmd |= MI_EXE_FLUSH; |
| 133 | |
| 134 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
| 135 | (IS_G4X(dev) || IS_GEN5(dev))) |
| 136 | cmd |= MI_INVALIDATE_ISP; |
| 137 | |
| 138 | ret = intel_ring_begin(ring, 2); |
| 139 | if (ret) |
| 140 | return ret; |
| 141 | |
| 142 | intel_ring_emit(ring, cmd); |
| 143 | intel_ring_emit(ring, MI_NOOP); |
| 144 | intel_ring_advance(ring); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 145 | |
| 146 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 147 | } |
| 148 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 149 | /** |
| 150 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
| 151 | * implementing two workarounds on gen6. From section 1.4.7.1 |
| 152 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: |
| 153 | * |
| 154 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those |
| 155 | * produced by non-pipelined state commands), software needs to first |
| 156 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != |
| 157 | * 0. |
| 158 | * |
| 159 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable |
| 160 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. |
| 161 | * |
| 162 | * And the workaround for these two requires this workaround first: |
| 163 | * |
| 164 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent |
| 165 | * BEFORE the pipe-control with a post-sync op and no write-cache |
| 166 | * flushes. |
| 167 | * |
| 168 | * And this last workaround is tricky because of the requirements on |
| 169 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM |
| 170 | * volume 2 part 1: |
| 171 | * |
| 172 | * "1 of the following must also be set: |
| 173 | * - Render Target Cache Flush Enable ([12] of DW1) |
| 174 | * - Depth Cache Flush Enable ([0] of DW1) |
| 175 | * - Stall at Pixel Scoreboard ([1] of DW1) |
| 176 | * - Depth Stall ([13] of DW1) |
| 177 | * - Post-Sync Operation ([13] of DW1) |
| 178 | * - Notify Enable ([8] of DW1)" |
| 179 | * |
| 180 | * The cache flushes require the workaround flush that triggered this |
| 181 | * one, so we can't use it. Depth stall would trigger the same. |
| 182 | * Post-sync nonzero is what triggered this second workaround, so we |
| 183 | * can't use that one either. Notify enable is IRQs, which aren't |
| 184 | * really our business. That leaves only stall at scoreboard. |
| 185 | */ |
| 186 | static int |
| 187 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) |
| 188 | { |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 189 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 190 | int ret; |
| 191 | |
| 192 | |
| 193 | ret = intel_ring_begin(ring, 6); |
| 194 | if (ret) |
| 195 | return ret; |
| 196 | |
| 197 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 198 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 199 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 200 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 201 | intel_ring_emit(ring, 0); /* low dword */ |
| 202 | intel_ring_emit(ring, 0); /* high dword */ |
| 203 | intel_ring_emit(ring, MI_NOOP); |
| 204 | intel_ring_advance(ring); |
| 205 | |
| 206 | ret = intel_ring_begin(ring, 6); |
| 207 | if (ret) |
| 208 | return ret; |
| 209 | |
| 210 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 211 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); |
| 212 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 213 | intel_ring_emit(ring, 0); |
| 214 | intel_ring_emit(ring, 0); |
| 215 | intel_ring_emit(ring, MI_NOOP); |
| 216 | intel_ring_advance(ring); |
| 217 | |
| 218 | return 0; |
| 219 | } |
| 220 | |
| 221 | static int |
| 222 | gen6_render_ring_flush(struct intel_ring_buffer *ring, |
| 223 | u32 invalidate_domains, u32 flush_domains) |
| 224 | { |
| 225 | u32 flags = 0; |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 226 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 227 | int ret; |
| 228 | |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 229 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
| 230 | ret = intel_emit_post_sync_nonzero_flush(ring); |
| 231 | if (ret) |
| 232 | return ret; |
| 233 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 234 | /* Just flush everything. Experiments have shown that reducing the |
| 235 | * number of bits based on the write domains has little performance |
| 236 | * impact. |
| 237 | */ |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 238 | if (flush_domains) { |
| 239 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 240 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 241 | /* |
| 242 | * Ensure that any following seqno writes only happen |
| 243 | * when the render cache is indeed flushed. |
| 244 | */ |
Daniel Vetter | 97f209b | 2012-06-28 09:48:42 +0200 | [diff] [blame] | 245 | flags |= PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 246 | } |
| 247 | if (invalidate_domains) { |
| 248 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 249 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 250 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 251 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 252 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 253 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 254 | /* |
| 255 | * TLB invalidate requires a post-sync write. |
| 256 | */ |
Jesse Barnes | 3ac7831 | 2012-10-25 12:15:47 -0700 | [diff] [blame] | 257 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 258 | } |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 259 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 260 | ret = intel_ring_begin(ring, 4); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 261 | if (ret) |
| 262 | return ret; |
| 263 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 264 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 265 | intel_ring_emit(ring, flags); |
| 266 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 267 | intel_ring_emit(ring, 0); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 268 | intel_ring_advance(ring); |
| 269 | |
| 270 | return 0; |
| 271 | } |
| 272 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 273 | static int |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 274 | gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) |
| 275 | { |
| 276 | int ret; |
| 277 | |
| 278 | ret = intel_ring_begin(ring, 4); |
| 279 | if (ret) |
| 280 | return ret; |
| 281 | |
| 282 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
| 283 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 284 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 285 | intel_ring_emit(ring, 0); |
| 286 | intel_ring_emit(ring, 0); |
| 287 | intel_ring_advance(ring); |
| 288 | |
| 289 | return 0; |
| 290 | } |
| 291 | |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 292 | static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value) |
| 293 | { |
| 294 | int ret; |
| 295 | |
| 296 | if (!ring->fbc_dirty) |
| 297 | return 0; |
| 298 | |
Ville Syrjälä | 37c1d94 | 2013-11-06 23:02:20 +0200 | [diff] [blame] | 299 | ret = intel_ring_begin(ring, 6); |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 300 | if (ret) |
| 301 | return ret; |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 302 | /* WaFbcNukeOn3DBlt:ivb/hsw */ |
| 303 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 304 | intel_ring_emit(ring, MSG_FBC_REND_STATE); |
| 305 | intel_ring_emit(ring, value); |
Ville Syrjälä | 37c1d94 | 2013-11-06 23:02:20 +0200 | [diff] [blame] | 306 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); |
| 307 | intel_ring_emit(ring, MSG_FBC_REND_STATE); |
| 308 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 309 | intel_ring_advance(ring); |
| 310 | |
| 311 | ring->fbc_dirty = false; |
| 312 | return 0; |
| 313 | } |
| 314 | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 315 | static int |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 316 | gen7_render_ring_flush(struct intel_ring_buffer *ring, |
| 317 | u32 invalidate_domains, u32 flush_domains) |
| 318 | { |
| 319 | u32 flags = 0; |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 320 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 321 | int ret; |
| 322 | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 323 | /* |
| 324 | * Ensure that any following seqno writes only happen when the render |
| 325 | * cache is indeed flushed. |
| 326 | * |
| 327 | * Workaround: 4th PIPE_CONTROL command (except the ones with only |
| 328 | * read-cache invalidate bits set) must have the CS_STALL bit set. We |
| 329 | * don't try to be clever and just set it unconditionally. |
| 330 | */ |
| 331 | flags |= PIPE_CONTROL_CS_STALL; |
| 332 | |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 333 | /* Just flush everything. Experiments have shown that reducing the |
| 334 | * number of bits based on the write domains has little performance |
| 335 | * impact. |
| 336 | */ |
| 337 | if (flush_domains) { |
| 338 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 339 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 340 | } |
| 341 | if (invalidate_domains) { |
| 342 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 343 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 344 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 345 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 346 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 347 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 348 | /* |
| 349 | * TLB invalidate requires a post-sync write. |
| 350 | */ |
| 351 | flags |= PIPE_CONTROL_QW_WRITE; |
Ville Syrjälä | b9e1faa | 2013-02-14 21:53:51 +0200 | [diff] [blame] | 352 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 353 | |
| 354 | /* Workaround: we must issue a pipe_control with CS-stall bit |
| 355 | * set before a pipe_control command that has the state cache |
| 356 | * invalidate bit set. */ |
| 357 | gen7_render_ring_cs_stall_wa(ring); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 358 | } |
| 359 | |
| 360 | ret = intel_ring_begin(ring, 4); |
| 361 | if (ret) |
| 362 | return ret; |
| 363 | |
| 364 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
| 365 | intel_ring_emit(ring, flags); |
Ville Syrjälä | b9e1faa | 2013-02-14 21:53:51 +0200 | [diff] [blame] | 366 | intel_ring_emit(ring, scratch_addr); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 367 | intel_ring_emit(ring, 0); |
| 368 | intel_ring_advance(ring); |
| 369 | |
Ville Syrjälä | 9688eca | 2013-11-06 23:02:19 +0200 | [diff] [blame] | 370 | if (!invalidate_domains && flush_domains) |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 371 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
| 372 | |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 373 | return 0; |
| 374 | } |
| 375 | |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 376 | static int |
| 377 | gen8_render_ring_flush(struct intel_ring_buffer *ring, |
| 378 | u32 invalidate_domains, u32 flush_domains) |
| 379 | { |
| 380 | u32 flags = 0; |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 381 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 382 | int ret; |
| 383 | |
| 384 | flags |= PIPE_CONTROL_CS_STALL; |
| 385 | |
| 386 | if (flush_domains) { |
| 387 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 388 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 389 | } |
| 390 | if (invalidate_domains) { |
| 391 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 392 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 393 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 394 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 395 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 396 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 397 | flags |= PIPE_CONTROL_QW_WRITE; |
| 398 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
| 399 | } |
| 400 | |
| 401 | ret = intel_ring_begin(ring, 6); |
| 402 | if (ret) |
| 403 | return ret; |
| 404 | |
| 405 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
| 406 | intel_ring_emit(ring, flags); |
| 407 | intel_ring_emit(ring, scratch_addr); |
| 408 | intel_ring_emit(ring, 0); |
| 409 | intel_ring_emit(ring, 0); |
| 410 | intel_ring_emit(ring, 0); |
| 411 | intel_ring_advance(ring); |
| 412 | |
| 413 | return 0; |
| 414 | |
| 415 | } |
| 416 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 417 | static void ring_write_tail(struct intel_ring_buffer *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 418 | u32 value) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 419 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 420 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 421 | I915_WRITE_TAIL(ring, value); |
Xiang, Haihao | d46eefa | 2010-09-16 10:43:12 +0800 | [diff] [blame] | 422 | } |
| 423 | |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 424 | u64 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 425 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 426 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 427 | u64 acthd; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 428 | |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 429 | if (INTEL_INFO(ring->dev)->gen >= 8) |
| 430 | acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base), |
| 431 | RING_ACTHD_UDW(ring->mmio_base)); |
| 432 | else if (INTEL_INFO(ring->dev)->gen >= 4) |
| 433 | acthd = I915_READ(RING_ACTHD(ring->mmio_base)); |
| 434 | else |
| 435 | acthd = I915_READ(ACTHD); |
| 436 | |
| 437 | return acthd; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 438 | } |
| 439 | |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 440 | static void ring_setup_phys_status_page(struct intel_ring_buffer *ring) |
| 441 | { |
| 442 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 443 | u32 addr; |
| 444 | |
| 445 | addr = dev_priv->status_page_dmah->busaddr; |
| 446 | if (INTEL_INFO(ring->dev)->gen >= 4) |
| 447 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
| 448 | I915_WRITE(HWS_PGA, addr); |
| 449 | } |
| 450 | |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 451 | static bool stop_ring(struct intel_ring_buffer *ring) |
| 452 | { |
| 453 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
| 454 | |
| 455 | if (!IS_GEN2(ring->dev)) { |
| 456 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); |
| 457 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { |
| 458 | DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); |
| 459 | return false; |
| 460 | } |
| 461 | } |
| 462 | |
| 463 | I915_WRITE_CTL(ring, 0); |
| 464 | I915_WRITE_HEAD(ring, 0); |
| 465 | ring->write_tail(ring, 0); |
| 466 | |
| 467 | if (!IS_GEN2(ring->dev)) { |
| 468 | (void)I915_READ_CTL(ring); |
| 469 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); |
| 470 | } |
| 471 | |
| 472 | return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; |
| 473 | } |
| 474 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 475 | static int init_ring_common(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 476 | { |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 477 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 478 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 479 | struct drm_i915_gem_object *obj = ring->obj; |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 480 | int ret = 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 481 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 482 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 483 | |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 484 | if (!stop_ring(ring)) { |
| 485 | /* G45 ring initialization often fails to reset head to zero */ |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 486 | DRM_DEBUG_KMS("%s head not reset to zero " |
| 487 | "ctl %08x head %08x tail %08x start %08x\n", |
| 488 | ring->name, |
| 489 | I915_READ_CTL(ring), |
| 490 | I915_READ_HEAD(ring), |
| 491 | I915_READ_TAIL(ring), |
| 492 | I915_READ_START(ring)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 493 | |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 494 | if (!stop_ring(ring)) { |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 495 | DRM_ERROR("failed to set %s head to zero " |
| 496 | "ctl %08x head %08x tail %08x start %08x\n", |
| 497 | ring->name, |
| 498 | I915_READ_CTL(ring), |
| 499 | I915_READ_HEAD(ring), |
| 500 | I915_READ_TAIL(ring), |
| 501 | I915_READ_START(ring)); |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 502 | ret = -EIO; |
| 503 | goto out; |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 504 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 505 | } |
| 506 | |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 507 | if (I915_NEED_GFX_HWS(dev)) |
| 508 | intel_ring_setup_status_page(ring); |
| 509 | else |
| 510 | ring_setup_phys_status_page(ring); |
| 511 | |
Daniel Vetter | 0d8957c | 2012-08-07 09:54:14 +0200 | [diff] [blame] | 512 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
| 513 | * registers with the above sequence (the readback of the HEAD registers |
| 514 | * also enforces ordering), otherwise the hw might lose the new ring |
| 515 | * register values. */ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 516 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 517 | I915_WRITE_CTL(ring, |
Chris Wilson | ae69b42 | 2010-11-07 11:45:52 +0000 | [diff] [blame] | 518 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
Chris Wilson | 5d031e5 | 2012-02-08 13:34:13 +0000 | [diff] [blame] | 519 | | RING_VALID); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 520 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 521 | /* If the head is still not zero, the ring is dead */ |
Sean Paul | f01db98 | 2012-03-16 12:43:22 -0400 | [diff] [blame] | 522 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 523 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
Sean Paul | f01db98 | 2012-03-16 12:43:22 -0400 | [diff] [blame] | 524 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
Chris Wilson | e74cfed | 2010-11-09 10:16:56 +0000 | [diff] [blame] | 525 | DRM_ERROR("%s initialization failed " |
Chris Wilson | 48e48a0 | 2014-04-09 09:19:44 +0100 | [diff] [blame^] | 526 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
| 527 | ring->name, |
| 528 | I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID, |
| 529 | I915_READ_HEAD(ring), I915_READ_TAIL(ring), |
| 530 | I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj)); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 531 | ret = -EIO; |
| 532 | goto out; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 533 | } |
| 534 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 535 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
| 536 | i915_kernel_lost_context(ring->dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 537 | else { |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 538 | ring->head = I915_READ_HEAD(ring); |
Daniel Vetter | 870e86d | 2010-08-02 16:29:44 +0200 | [diff] [blame] | 539 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 540 | ring->space = ring_space(ring); |
Chris Wilson | c3b2003 | 2012-05-28 22:33:02 +0100 | [diff] [blame] | 541 | ring->last_retired_head = -1; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 542 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 543 | |
Chris Wilson | 50f018d | 2013-06-10 11:20:19 +0100 | [diff] [blame] | 544 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
| 545 | |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 546 | out: |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 547 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 548 | |
| 549 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 550 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 551 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 552 | static int |
| 553 | init_pipe_control(struct intel_ring_buffer *ring) |
| 554 | { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 555 | int ret; |
| 556 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 557 | if (ring->scratch.obj) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 558 | return 0; |
| 559 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 560 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
| 561 | if (ring->scratch.obj == NULL) { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 562 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 563 | ret = -ENOMEM; |
| 564 | goto err; |
| 565 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 566 | |
Daniel Vetter | a9cc726 | 2014-02-14 14:01:13 +0100 | [diff] [blame] | 567 | ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
| 568 | if (ret) |
| 569 | goto err_unref; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 570 | |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 571 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 572 | if (ret) |
| 573 | goto err_unref; |
| 574 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 575 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
| 576 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); |
| 577 | if (ring->scratch.cpu_page == NULL) { |
Wei Yongjun | 56b085a | 2013-05-28 17:51:44 +0800 | [diff] [blame] | 578 | ret = -ENOMEM; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 579 | goto err_unpin; |
Wei Yongjun | 56b085a | 2013-05-28 17:51:44 +0800 | [diff] [blame] | 580 | } |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 581 | |
Ville Syrjälä | 2b1086c | 2013-02-12 22:01:38 +0200 | [diff] [blame] | 582 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 583 | ring->name, ring->scratch.gtt_offset); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 584 | return 0; |
| 585 | |
| 586 | err_unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 587 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 588 | err_unref: |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 589 | drm_gem_object_unreference(&ring->scratch.obj->base); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 590 | err: |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 591 | return ret; |
| 592 | } |
| 593 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 594 | static int init_render_ring(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 595 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 596 | struct drm_device *dev = ring->dev; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 597 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 598 | int ret = init_ring_common(ring); |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 599 | |
Akash Goel | 61a563a | 2014-03-25 18:01:50 +0530 | [diff] [blame] | 600 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
| 601 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 602 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 603 | |
| 604 | /* We need to disable the AsyncFlip performance optimisations in order |
| 605 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be |
| 606 | * programmed to '1' on all products. |
Damien Lespiau | 8693a82 | 2013-05-03 18:48:11 +0100 | [diff] [blame] | 607 | * |
Ville Syrjälä | 8285222 | 2014-02-27 21:59:03 +0200 | [diff] [blame] | 608 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 609 | */ |
| 610 | if (INTEL_INFO(dev)->gen >= 6) |
| 611 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
| 612 | |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 613 | /* Required for the hardware to program scanline values for waiting */ |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 614 | /* WaEnableFlushTlbInvalidationMode:snb */ |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 615 | if (INTEL_INFO(dev)->gen == 6) |
| 616 | I915_WRITE(GFX_MODE, |
Chris Wilson | aa83e30 | 2014-03-21 17:18:54 +0000 | [diff] [blame] | 617 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 618 | |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 619 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 620 | if (IS_GEN7(dev)) |
| 621 | I915_WRITE(GFX_MODE_GEN7, |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 622 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 623 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 624 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 625 | if (INTEL_INFO(dev)->gen >= 5) { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 626 | ret = init_pipe_control(ring); |
| 627 | if (ret) |
| 628 | return ret; |
| 629 | } |
| 630 | |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 631 | if (IS_GEN6(dev)) { |
Kenneth Graunke | 3a69ddd | 2012-04-27 12:44:41 -0700 | [diff] [blame] | 632 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
| 633 | * "If this bit is set, STCunit will have LRA as replacement |
| 634 | * policy. [...] This bit must be reset. LRA replacement |
| 635 | * policy is not supported." |
| 636 | */ |
| 637 | I915_WRITE(CACHE_MODE_0, |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 638 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 639 | } |
| 640 | |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 641 | if (INTEL_INFO(dev)->gen >= 6) |
| 642 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 643 | |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 644 | if (HAS_L3_DPF(dev)) |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 645 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 646 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 647 | return ret; |
| 648 | } |
| 649 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 650 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
| 651 | { |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 652 | struct drm_device *dev = ring->dev; |
| 653 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 654 | if (ring->scratch.obj == NULL) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 655 | return; |
| 656 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 657 | if (INTEL_INFO(dev)->gen >= 5) { |
| 658 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 659 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 660 | } |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 661 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 662 | drm_gem_object_unreference(&ring->scratch.obj->base); |
| 663 | ring->scratch.obj = NULL; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 664 | } |
| 665 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 666 | static void |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 667 | update_mboxes(struct intel_ring_buffer *ring, |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 668 | u32 mmio_offset) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 669 | { |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 670 | /* NB: In order to be able to do semaphore MBOX updates for varying number |
| 671 | * of rings, it's easiest if we round up each individual update to a |
| 672 | * multiple of 2 (since ring updates must always be a multiple of 2) |
| 673 | * even though the actual update only requires 3 dwords. |
| 674 | */ |
| 675 | #define MBOX_UPDATE_DWORDS 4 |
Chris Wilson | 1c8b46f | 2012-11-14 09:15:14 +0000 | [diff] [blame] | 676 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 677 | intel_ring_emit(ring, mmio_offset); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 678 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 679 | intel_ring_emit(ring, MI_NOOP); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 680 | } |
| 681 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 682 | /** |
| 683 | * gen6_add_request - Update the semaphore mailbox registers |
| 684 | * |
| 685 | * @ring - ring that is adding a request |
| 686 | * @seqno - return seqno stuck into the ring |
| 687 | * |
| 688 | * Update the mailbox registers in the *other* rings with the current seqno. |
| 689 | * This acts like a signal in the canonical semaphore. |
| 690 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 691 | static int |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 692 | gen6_add_request(struct intel_ring_buffer *ring) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 693 | { |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 694 | struct drm_device *dev = ring->dev; |
| 695 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 696 | struct intel_ring_buffer *useless; |
Ben Widawsky | 52ed232 | 2013-12-16 20:50:38 -0800 | [diff] [blame] | 697 | int i, ret, num_dwords = 4; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 698 | |
Ben Widawsky | 52ed232 | 2013-12-16 20:50:38 -0800 | [diff] [blame] | 699 | if (i915_semaphore_is_enabled(dev)) |
| 700 | num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS); |
| 701 | #undef MBOX_UPDATE_DWORDS |
| 702 | |
| 703 | ret = intel_ring_begin(ring, num_dwords); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 704 | if (ret) |
| 705 | return ret; |
| 706 | |
Ben Widawsky | f0a9f74 | 2013-12-17 20:06:00 -0800 | [diff] [blame] | 707 | if (i915_semaphore_is_enabled(dev)) { |
| 708 | for_each_ring(useless, dev_priv, i) { |
| 709 | u32 mbox_reg = ring->signal_mbox[i]; |
| 710 | if (mbox_reg != GEN6_NOSYNC) |
| 711 | update_mboxes(ring, mbox_reg); |
| 712 | } |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 713 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 714 | |
| 715 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 716 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 717 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 718 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 719 | __intel_ring_advance(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 720 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 721 | return 0; |
| 722 | } |
| 723 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 724 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
| 725 | u32 seqno) |
| 726 | { |
| 727 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 728 | return dev_priv->last_seqno < seqno; |
| 729 | } |
| 730 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 731 | /** |
| 732 | * intel_ring_sync - sync the waiter to the signaller on seqno |
| 733 | * |
| 734 | * @waiter - ring that is waiting |
| 735 | * @signaller - ring which has, or will signal |
| 736 | * @seqno - seqno which the waiter will block on |
| 737 | */ |
| 738 | static int |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 739 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
| 740 | struct intel_ring_buffer *signaller, |
| 741 | u32 seqno) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 742 | { |
| 743 | int ret; |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 744 | u32 dw1 = MI_SEMAPHORE_MBOX | |
| 745 | MI_SEMAPHORE_COMPARE | |
| 746 | MI_SEMAPHORE_REGISTER; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 747 | |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 748 | /* Throughout all of the GEM code, seqno passed implies our current |
| 749 | * seqno is >= the last seqno executed. However for hardware the |
| 750 | * comparison is strictly greater than. |
| 751 | */ |
| 752 | seqno -= 1; |
| 753 | |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 754 | WARN_ON(signaller->semaphore_register[waiter->id] == |
| 755 | MI_SEMAPHORE_SYNC_INVALID); |
| 756 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 757 | ret = intel_ring_begin(waiter, 4); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 758 | if (ret) |
| 759 | return ret; |
| 760 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 761 | /* If seqno wrap happened, omit the wait with no-ops */ |
| 762 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { |
| 763 | intel_ring_emit(waiter, |
| 764 | dw1 | |
| 765 | signaller->semaphore_register[waiter->id]); |
| 766 | intel_ring_emit(waiter, seqno); |
| 767 | intel_ring_emit(waiter, 0); |
| 768 | intel_ring_emit(waiter, MI_NOOP); |
| 769 | } else { |
| 770 | intel_ring_emit(waiter, MI_NOOP); |
| 771 | intel_ring_emit(waiter, MI_NOOP); |
| 772 | intel_ring_emit(waiter, MI_NOOP); |
| 773 | intel_ring_emit(waiter, MI_NOOP); |
| 774 | } |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 775 | intel_ring_advance(waiter); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 776 | |
| 777 | return 0; |
| 778 | } |
| 779 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 780 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
| 781 | do { \ |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 782 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
| 783 | PIPE_CONTROL_DEPTH_STALL); \ |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 784 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
| 785 | intel_ring_emit(ring__, 0); \ |
| 786 | intel_ring_emit(ring__, 0); \ |
| 787 | } while (0) |
| 788 | |
| 789 | static int |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 790 | pc_render_add_request(struct intel_ring_buffer *ring) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 791 | { |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 792 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 793 | int ret; |
| 794 | |
| 795 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
| 796 | * incoherent with writes to memory, i.e. completely fubar, |
| 797 | * so we need to use PIPE_NOTIFY instead. |
| 798 | * |
| 799 | * However, we also need to workaround the qword write |
| 800 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
| 801 | * memory before requesting an interrupt. |
| 802 | */ |
| 803 | ret = intel_ring_begin(ring, 32); |
| 804 | if (ret) |
| 805 | return ret; |
| 806 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 807 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 808 | PIPE_CONTROL_WRITE_FLUSH | |
| 809 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 810 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 811 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 812 | intel_ring_emit(ring, 0); |
| 813 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 814 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 815 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 816 | scratch_addr += 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 817 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 818 | scratch_addr += 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 819 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 820 | scratch_addr += 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 821 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 822 | scratch_addr += 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 823 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 824 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 825 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 826 | PIPE_CONTROL_WRITE_FLUSH | |
| 827 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 828 | PIPE_CONTROL_NOTIFY); |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 829 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 830 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 831 | intel_ring_emit(ring, 0); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 832 | __intel_ring_advance(ring); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 833 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 834 | return 0; |
| 835 | } |
| 836 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 837 | static u32 |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 838 | gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 839 | { |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 840 | /* Workaround to force correct ordering between irq and seqno writes on |
| 841 | * ivb (and maybe also on snb) by reading from a CS register (like |
| 842 | * ACTHD) before reading the status page. */ |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 843 | if (!lazy_coherency) { |
| 844 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 845 | POSTING_READ(RING_ACTHD(ring->mmio_base)); |
| 846 | } |
| 847 | |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 848 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 849 | } |
| 850 | |
| 851 | static u32 |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 852 | ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 853 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 854 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 855 | } |
| 856 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 857 | static void |
| 858 | ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 859 | { |
| 860 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); |
| 861 | } |
| 862 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 863 | static u32 |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 864 | pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 865 | { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 866 | return ring->scratch.cpu_page[0]; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 867 | } |
| 868 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 869 | static void |
| 870 | pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 871 | { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 872 | ring->scratch.cpu_page[0] = seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 873 | } |
| 874 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 875 | static bool |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 876 | gen5_ring_get_irq(struct intel_ring_buffer *ring) |
| 877 | { |
| 878 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 879 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 880 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 881 | |
| 882 | if (!dev->irq_enabled) |
| 883 | return false; |
| 884 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 885 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 886 | if (ring->irq_refcount++ == 0) |
| 887 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 888 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 889 | |
| 890 | return true; |
| 891 | } |
| 892 | |
| 893 | static void |
| 894 | gen5_ring_put_irq(struct intel_ring_buffer *ring) |
| 895 | { |
| 896 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 897 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 898 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 899 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 900 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 901 | if (--ring->irq_refcount == 0) |
| 902 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 903 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 904 | } |
| 905 | |
| 906 | static bool |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 907 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 908 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 909 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 910 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 911 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 912 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 913 | if (!dev->irq_enabled) |
| 914 | return false; |
| 915 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 916 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 917 | if (ring->irq_refcount++ == 0) { |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 918 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 919 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 920 | POSTING_READ(IMR); |
| 921 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 922 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 923 | |
| 924 | return true; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 925 | } |
| 926 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 927 | static void |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 928 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 929 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 930 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 931 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 932 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 933 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 934 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 935 | if (--ring->irq_refcount == 0) { |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 936 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 937 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 938 | POSTING_READ(IMR); |
| 939 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 940 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 941 | } |
| 942 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 943 | static bool |
| 944 | i8xx_ring_get_irq(struct intel_ring_buffer *ring) |
| 945 | { |
| 946 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 947 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 948 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 949 | |
| 950 | if (!dev->irq_enabled) |
| 951 | return false; |
| 952 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 953 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 954 | if (ring->irq_refcount++ == 0) { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 955 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 956 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 957 | POSTING_READ16(IMR); |
| 958 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 959 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 960 | |
| 961 | return true; |
| 962 | } |
| 963 | |
| 964 | static void |
| 965 | i8xx_ring_put_irq(struct intel_ring_buffer *ring) |
| 966 | { |
| 967 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 968 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 969 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 970 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 971 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 972 | if (--ring->irq_refcount == 0) { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 973 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 974 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 975 | POSTING_READ16(IMR); |
| 976 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 977 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 978 | } |
| 979 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 980 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 981 | { |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 982 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 983 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 984 | u32 mmio = 0; |
| 985 | |
| 986 | /* The ring status page addresses are no longer next to the rest of |
| 987 | * the ring registers as of gen7. |
| 988 | */ |
| 989 | if (IS_GEN7(dev)) { |
| 990 | switch (ring->id) { |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 991 | case RCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 992 | mmio = RENDER_HWS_PGA_GEN7; |
| 993 | break; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 994 | case BCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 995 | mmio = BLT_HWS_PGA_GEN7; |
| 996 | break; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 997 | case VCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 998 | mmio = BSD_HWS_PGA_GEN7; |
| 999 | break; |
Ben Widawsky | 4a3dd19 | 2013-05-28 19:22:19 -0700 | [diff] [blame] | 1000 | case VECS: |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 1001 | mmio = VEBOX_HWS_PGA_GEN7; |
| 1002 | break; |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 1003 | } |
| 1004 | } else if (IS_GEN6(ring->dev)) { |
| 1005 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); |
| 1006 | } else { |
Ben Widawsky | eb0d4b7 | 2013-11-07 21:40:50 -0800 | [diff] [blame] | 1007 | /* XXX: gen8 returns to sanity */ |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 1008 | mmio = RING_HWS_PGA(ring->mmio_base); |
| 1009 | } |
| 1010 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1011 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
| 1012 | POSTING_READ(mmio); |
Chris Wilson | 884020b | 2013-08-06 19:01:14 +0100 | [diff] [blame] | 1013 | |
Damien Lespiau | dc616b8 | 2014-03-13 01:40:28 +0000 | [diff] [blame] | 1014 | /* |
| 1015 | * Flush the TLB for this page |
| 1016 | * |
| 1017 | * FIXME: These two bits have disappeared on gen8, so a question |
| 1018 | * arises: do we still need this and if so how should we go about |
| 1019 | * invalidating the TLB? |
| 1020 | */ |
| 1021 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { |
Chris Wilson | 884020b | 2013-08-06 19:01:14 +0100 | [diff] [blame] | 1022 | u32 reg = RING_INSTPM(ring->mmio_base); |
Naresh Kumar Kachhi | 02f6a1e | 2014-03-12 16:39:42 +0530 | [diff] [blame] | 1023 | |
| 1024 | /* ring should be idle before issuing a sync flush*/ |
| 1025 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); |
| 1026 | |
Chris Wilson | 884020b | 2013-08-06 19:01:14 +0100 | [diff] [blame] | 1027 | I915_WRITE(reg, |
| 1028 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | |
| 1029 | INSTPM_SYNC_FLUSH)); |
| 1030 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, |
| 1031 | 1000)) |
| 1032 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
| 1033 | ring->name); |
| 1034 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1035 | } |
| 1036 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1037 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1038 | bsd_ring_flush(struct intel_ring_buffer *ring, |
| 1039 | u32 invalidate_domains, |
| 1040 | u32 flush_domains) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1041 | { |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1042 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1043 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1044 | ret = intel_ring_begin(ring, 2); |
| 1045 | if (ret) |
| 1046 | return ret; |
| 1047 | |
| 1048 | intel_ring_emit(ring, MI_FLUSH); |
| 1049 | intel_ring_emit(ring, MI_NOOP); |
| 1050 | intel_ring_advance(ring); |
| 1051 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1052 | } |
| 1053 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1054 | static int |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1055 | i9xx_add_request(struct intel_ring_buffer *ring) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1056 | { |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1057 | int ret; |
| 1058 | |
| 1059 | ret = intel_ring_begin(ring, 4); |
| 1060 | if (ret) |
| 1061 | return ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 1062 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1063 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 1064 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1065 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1066 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 1067 | __intel_ring_advance(ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1068 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1069 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1070 | } |
| 1071 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1072 | static bool |
Ben Widawsky | 25c0630 | 2012-03-29 19:11:27 -0700 | [diff] [blame] | 1073 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1074 | { |
| 1075 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1076 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1077 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1078 | |
| 1079 | if (!dev->irq_enabled) |
| 1080 | return false; |
| 1081 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1082 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1083 | if (ring->irq_refcount++ == 0) { |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 1084 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1085 | I915_WRITE_IMR(ring, |
| 1086 | ~(ring->irq_enable_mask | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1087 | GT_PARITY_ERROR(dev))); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 1088 | else |
| 1089 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 1090 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1091 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1092 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1093 | |
| 1094 | return true; |
| 1095 | } |
| 1096 | |
| 1097 | static void |
Ben Widawsky | 25c0630 | 2012-03-29 19:11:27 -0700 | [diff] [blame] | 1098 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1099 | { |
| 1100 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1101 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1102 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1103 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1104 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1105 | if (--ring->irq_refcount == 0) { |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 1106 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1107 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 1108 | else |
| 1109 | I915_WRITE_IMR(ring, ~0); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 1110 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1111 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1112 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1113 | } |
| 1114 | |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1115 | static bool |
| 1116 | hsw_vebox_get_irq(struct intel_ring_buffer *ring) |
| 1117 | { |
| 1118 | struct drm_device *dev = ring->dev; |
| 1119 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1120 | unsigned long flags; |
| 1121 | |
| 1122 | if (!dev->irq_enabled) |
| 1123 | return false; |
| 1124 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1125 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1126 | if (ring->irq_refcount++ == 0) { |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1127 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 1128 | snb_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1129 | } |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1130 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1131 | |
| 1132 | return true; |
| 1133 | } |
| 1134 | |
| 1135 | static void |
| 1136 | hsw_vebox_put_irq(struct intel_ring_buffer *ring) |
| 1137 | { |
| 1138 | struct drm_device *dev = ring->dev; |
| 1139 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1140 | unsigned long flags; |
| 1141 | |
| 1142 | if (!dev->irq_enabled) |
| 1143 | return; |
| 1144 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1145 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1146 | if (--ring->irq_refcount == 0) { |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1147 | I915_WRITE_IMR(ring, ~0); |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 1148 | snb_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1149 | } |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1150 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1151 | } |
| 1152 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1153 | static bool |
| 1154 | gen8_ring_get_irq(struct intel_ring_buffer *ring) |
| 1155 | { |
| 1156 | struct drm_device *dev = ring->dev; |
| 1157 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1158 | unsigned long flags; |
| 1159 | |
| 1160 | if (!dev->irq_enabled) |
| 1161 | return false; |
| 1162 | |
| 1163 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1164 | if (ring->irq_refcount++ == 0) { |
| 1165 | if (HAS_L3_DPF(dev) && ring->id == RCS) { |
| 1166 | I915_WRITE_IMR(ring, |
| 1167 | ~(ring->irq_enable_mask | |
| 1168 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); |
| 1169 | } else { |
| 1170 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
| 1171 | } |
| 1172 | POSTING_READ(RING_IMR(ring->mmio_base)); |
| 1173 | } |
| 1174 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1175 | |
| 1176 | return true; |
| 1177 | } |
| 1178 | |
| 1179 | static void |
| 1180 | gen8_ring_put_irq(struct intel_ring_buffer *ring) |
| 1181 | { |
| 1182 | struct drm_device *dev = ring->dev; |
| 1183 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1184 | unsigned long flags; |
| 1185 | |
| 1186 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1187 | if (--ring->irq_refcount == 0) { |
| 1188 | if (HAS_L3_DPF(dev) && ring->id == RCS) { |
| 1189 | I915_WRITE_IMR(ring, |
| 1190 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
| 1191 | } else { |
| 1192 | I915_WRITE_IMR(ring, ~0); |
| 1193 | } |
| 1194 | POSTING_READ(RING_IMR(ring->mmio_base)); |
| 1195 | } |
| 1196 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1197 | } |
| 1198 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1199 | static int |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1200 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1201 | u32 offset, u32 length, |
| 1202 | unsigned flags) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1203 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1204 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1205 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1206 | ret = intel_ring_begin(ring, 2); |
| 1207 | if (ret) |
| 1208 | return ret; |
| 1209 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1210 | intel_ring_emit(ring, |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 1211 | MI_BATCH_BUFFER_START | |
| 1212 | MI_BATCH_GTT | |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1213 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1214 | intel_ring_emit(ring, offset); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1215 | intel_ring_advance(ring); |
| 1216 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1217 | return 0; |
| 1218 | } |
| 1219 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1220 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
| 1221 | #define I830_BATCH_LIMIT (256*1024) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1222 | static int |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1223 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1224 | u32 offset, u32 len, |
| 1225 | unsigned flags) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1226 | { |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1227 | int ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1228 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1229 | if (flags & I915_DISPATCH_PINNED) { |
| 1230 | ret = intel_ring_begin(ring, 4); |
| 1231 | if (ret) |
| 1232 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1233 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1234 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 1235 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
| 1236 | intel_ring_emit(ring, offset + len - 8); |
| 1237 | intel_ring_emit(ring, MI_NOOP); |
| 1238 | intel_ring_advance(ring); |
| 1239 | } else { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 1240 | u32 cs_offset = ring->scratch.gtt_offset; |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1241 | |
| 1242 | if (len > I830_BATCH_LIMIT) |
| 1243 | return -ENOSPC; |
| 1244 | |
| 1245 | ret = intel_ring_begin(ring, 9+3); |
| 1246 | if (ret) |
| 1247 | return ret; |
| 1248 | /* Blit the batch (which has now all relocs applied) to the stable batch |
| 1249 | * scratch bo area (so that the CS never stumbles over its tlb |
| 1250 | * invalidation bug) ... */ |
| 1251 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | |
| 1252 | XY_SRC_COPY_BLT_WRITE_ALPHA | |
| 1253 | XY_SRC_COPY_BLT_WRITE_RGB); |
| 1254 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); |
| 1255 | intel_ring_emit(ring, 0); |
| 1256 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); |
| 1257 | intel_ring_emit(ring, cs_offset); |
| 1258 | intel_ring_emit(ring, 0); |
| 1259 | intel_ring_emit(ring, 4096); |
| 1260 | intel_ring_emit(ring, offset); |
| 1261 | intel_ring_emit(ring, MI_FLUSH); |
| 1262 | |
| 1263 | /* ... and execute it. */ |
| 1264 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 1265 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
| 1266 | intel_ring_emit(ring, cs_offset + len - 8); |
| 1267 | intel_ring_advance(ring); |
| 1268 | } |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1269 | |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1270 | return 0; |
| 1271 | } |
| 1272 | |
| 1273 | static int |
| 1274 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1275 | u32 offset, u32 len, |
| 1276 | unsigned flags) |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1277 | { |
| 1278 | int ret; |
| 1279 | |
| 1280 | ret = intel_ring_begin(ring, 2); |
| 1281 | if (ret) |
| 1282 | return ret; |
| 1283 | |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 1284 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1285 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1286 | intel_ring_advance(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1287 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1288 | return 0; |
| 1289 | } |
| 1290 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1291 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1292 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1293 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1294 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1295 | obj = ring->status_page.obj; |
| 1296 | if (obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1297 | return; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1298 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1299 | kunmap(sg_page(obj->pages->sgl)); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 1300 | i915_gem_object_ggtt_unpin(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1301 | drm_gem_object_unreference(&obj->base); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1302 | ring->status_page.obj = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1303 | } |
| 1304 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1305 | static int init_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1306 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1307 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1308 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1309 | if ((obj = ring->status_page.obj) == NULL) { |
| 1310 | int ret; |
| 1311 | |
| 1312 | obj = i915_gem_alloc_object(ring->dev, 4096); |
| 1313 | if (obj == NULL) { |
| 1314 | DRM_ERROR("Failed to allocate status page\n"); |
| 1315 | return -ENOMEM; |
| 1316 | } |
| 1317 | |
| 1318 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
| 1319 | if (ret) |
| 1320 | goto err_unref; |
| 1321 | |
| 1322 | ret = i915_gem_obj_ggtt_pin(obj, 4096, 0); |
| 1323 | if (ret) { |
| 1324 | err_unref: |
| 1325 | drm_gem_object_unreference(&obj->base); |
| 1326 | return ret; |
| 1327 | } |
| 1328 | |
| 1329 | ring->status_page.obj = obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1330 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 1331 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1332 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1333 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1334 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1335 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1336 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
| 1337 | ring->name, ring->status_page.gfx_addr); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1338 | |
| 1339 | return 0; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1340 | } |
| 1341 | |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 1342 | static int init_phys_status_page(struct intel_ring_buffer *ring) |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1343 | { |
| 1344 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1345 | |
| 1346 | if (!dev_priv->status_page_dmah) { |
| 1347 | dev_priv->status_page_dmah = |
| 1348 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); |
| 1349 | if (!dev_priv->status_page_dmah) |
| 1350 | return -ENOMEM; |
| 1351 | } |
| 1352 | |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1353 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 1354 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
| 1355 | |
| 1356 | return 0; |
| 1357 | } |
| 1358 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1359 | static int allocate_ring_buffer(struct intel_ring_buffer *ring) |
| 1360 | { |
| 1361 | struct drm_device *dev = ring->dev; |
| 1362 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 1363 | struct drm_i915_gem_object *obj; |
| 1364 | int ret; |
| 1365 | |
| 1366 | if (ring->obj) |
| 1367 | return 0; |
| 1368 | |
| 1369 | obj = NULL; |
| 1370 | if (!HAS_LLC(dev)) |
| 1371 | obj = i915_gem_object_create_stolen(dev, ring->size); |
| 1372 | if (obj == NULL) |
| 1373 | obj = i915_gem_alloc_object(dev, ring->size); |
| 1374 | if (obj == NULL) |
| 1375 | return -ENOMEM; |
| 1376 | |
| 1377 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); |
| 1378 | if (ret) |
| 1379 | goto err_unref; |
| 1380 | |
| 1381 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 1382 | if (ret) |
| 1383 | goto err_unpin; |
| 1384 | |
| 1385 | ring->virtual_start = |
| 1386 | ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj), |
| 1387 | ring->size); |
| 1388 | if (ring->virtual_start == NULL) { |
| 1389 | ret = -EINVAL; |
| 1390 | goto err_unpin; |
| 1391 | } |
| 1392 | |
| 1393 | ring->obj = obj; |
| 1394 | return 0; |
| 1395 | |
| 1396 | err_unpin: |
| 1397 | i915_gem_object_ggtt_unpin(obj); |
| 1398 | err_unref: |
| 1399 | drm_gem_object_unreference(&obj->base); |
| 1400 | return ret; |
| 1401 | } |
| 1402 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 1403 | static int intel_init_ring_buffer(struct drm_device *dev, |
| 1404 | struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1405 | { |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1406 | int ret; |
| 1407 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1408 | ring->dev = dev; |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1409 | INIT_LIST_HEAD(&ring->active_list); |
| 1410 | INIT_LIST_HEAD(&ring->request_list); |
Daniel Vetter | dfc9ef2 | 2012-04-11 22:12:47 +0200 | [diff] [blame] | 1411 | ring->size = 32 * PAGE_SIZE; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1412 | memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno)); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 1413 | |
Chris Wilson | b259f67 | 2011-03-29 13:19:09 +0100 | [diff] [blame] | 1414 | init_waitqueue_head(&ring->irq_queue); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1415 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1416 | if (I915_NEED_GFX_HWS(dev)) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1417 | ret = init_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1418 | if (ret) |
| 1419 | return ret; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1420 | } else { |
| 1421 | BUG_ON(ring->id != RCS); |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 1422 | ret = init_phys_status_page(ring); |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1423 | if (ret) |
| 1424 | return ret; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1425 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1426 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1427 | ret = allocate_ring_buffer(ring); |
| 1428 | if (ret) { |
| 1429 | DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret); |
| 1430 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1431 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1432 | |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1433 | /* Workaround an erratum on the i830 which causes a hang if |
| 1434 | * the TAIL pointer points to within the last 2 cachelines |
| 1435 | * of the buffer. |
| 1436 | */ |
| 1437 | ring->effective_size = ring->size; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1438 | if (IS_I830(dev) || IS_845G(dev)) |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1439 | ring->effective_size -= 2 * CACHELINE_BYTES; |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1440 | |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 1441 | i915_cmd_parser_init_ring(ring); |
| 1442 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1443 | return ring->init(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1444 | } |
| 1445 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1446 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1447 | { |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1448 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1449 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1450 | if (ring->obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1451 | return; |
| 1452 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1453 | intel_stop_ring_buffer(ring); |
| 1454 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1455 | |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1456 | iounmap(ring->virtual_start); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1457 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 1458 | i915_gem_object_ggtt_unpin(ring->obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1459 | drm_gem_object_unreference(&ring->obj->base); |
| 1460 | ring->obj = NULL; |
Ben Widawsky | 3d57e5b | 2013-10-14 10:01:36 -0700 | [diff] [blame] | 1461 | ring->preallocated_lazy_request = NULL; |
| 1462 | ring->outstanding_lazy_seqno = 0; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1463 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1464 | if (ring->cleanup) |
| 1465 | ring->cleanup(ring); |
| 1466 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1467 | cleanup_status_page(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1468 | } |
| 1469 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1470 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) |
| 1471 | { |
| 1472 | struct drm_i915_gem_request *request; |
Chris Wilson | 1f70999 | 2014-01-27 22:43:07 +0000 | [diff] [blame] | 1473 | u32 seqno = 0, tail; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1474 | int ret; |
| 1475 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1476 | if (ring->last_retired_head != -1) { |
| 1477 | ring->head = ring->last_retired_head; |
| 1478 | ring->last_retired_head = -1; |
Chris Wilson | 1f70999 | 2014-01-27 22:43:07 +0000 | [diff] [blame] | 1479 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1480 | ring->space = ring_space(ring); |
| 1481 | if (ring->space >= n) |
| 1482 | return 0; |
| 1483 | } |
| 1484 | |
| 1485 | list_for_each_entry(request, &ring->request_list, list) { |
| 1486 | int space; |
| 1487 | |
| 1488 | if (request->tail == -1) |
| 1489 | continue; |
| 1490 | |
Ville Syrjälä | 633cf8f | 2012-12-03 18:43:32 +0200 | [diff] [blame] | 1491 | space = request->tail - (ring->tail + I915_RING_FREE_SPACE); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1492 | if (space < 0) |
| 1493 | space += ring->size; |
| 1494 | if (space >= n) { |
| 1495 | seqno = request->seqno; |
Chris Wilson | 1f70999 | 2014-01-27 22:43:07 +0000 | [diff] [blame] | 1496 | tail = request->tail; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1497 | break; |
| 1498 | } |
| 1499 | |
| 1500 | /* Consume this request in case we need more space than |
| 1501 | * is available and so need to prevent a race between |
| 1502 | * updating last_retired_head and direct reads of |
| 1503 | * I915_RING_HEAD. It also provides a nice sanity check. |
| 1504 | */ |
| 1505 | request->tail = -1; |
| 1506 | } |
| 1507 | |
| 1508 | if (seqno == 0) |
| 1509 | return -ENOSPC; |
| 1510 | |
Chris Wilson | 1f70999 | 2014-01-27 22:43:07 +0000 | [diff] [blame] | 1511 | ret = i915_wait_seqno(ring, seqno); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1512 | if (ret) |
| 1513 | return ret; |
| 1514 | |
Chris Wilson | 1f70999 | 2014-01-27 22:43:07 +0000 | [diff] [blame] | 1515 | ring->head = tail; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1516 | ring->space = ring_space(ring); |
| 1517 | if (WARN_ON(ring->space < n)) |
| 1518 | return -ENOSPC; |
| 1519 | |
| 1520 | return 0; |
| 1521 | } |
| 1522 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1523 | static int ring_wait_for_space(struct intel_ring_buffer *ring, int n) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1524 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1525 | struct drm_device *dev = ring->dev; |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1526 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1527 | unsigned long end; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1528 | int ret; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1529 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1530 | ret = intel_ring_wait_request(ring, n); |
| 1531 | if (ret != -ENOSPC) |
| 1532 | return ret; |
| 1533 | |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 1534 | /* force the tail write in case we have been skipping them */ |
| 1535 | __intel_ring_advance(ring); |
| 1536 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1537 | trace_i915_ring_wait_begin(ring); |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 1538 | /* With GEM the hangcheck timer should kick us out of the loop, |
| 1539 | * leaving it early runs the risk of corrupting GEM state (due |
| 1540 | * to running on almost untested codepaths). But on resume |
| 1541 | * timers don't work yet, so prevent a complete hang in that |
| 1542 | * case by choosing an insanely large timeout. */ |
| 1543 | end = jiffies + 60 * HZ; |
Daniel Vetter | e6bfaf8 | 2011-12-14 13:56:59 +0100 | [diff] [blame] | 1544 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1545 | do { |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1546 | ring->head = I915_READ_HEAD(ring); |
| 1547 | ring->space = ring_space(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1548 | if (ring->space >= n) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1549 | trace_i915_ring_wait_end(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1550 | return 0; |
| 1551 | } |
| 1552 | |
Daniel Vetter | fb19e2a | 2014-02-12 23:44:34 +0100 | [diff] [blame] | 1553 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && |
| 1554 | dev->primary->master) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1555 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
| 1556 | if (master_priv->sarea_priv) |
| 1557 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
| 1558 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1559 | |
Chris Wilson | e60a0b1 | 2010-10-13 10:09:14 +0100 | [diff] [blame] | 1560 | msleep(1); |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 1561 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1562 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 1563 | dev_priv->mm.interruptible); |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 1564 | if (ret) |
| 1565 | return ret; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1566 | } while (!time_after(jiffies, end)); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1567 | trace_i915_ring_wait_end(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1568 | return -EBUSY; |
| 1569 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1570 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1571 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
| 1572 | { |
| 1573 | uint32_t __iomem *virt; |
| 1574 | int rem = ring->size - ring->tail; |
| 1575 | |
| 1576 | if (ring->space < rem) { |
| 1577 | int ret = ring_wait_for_space(ring, rem); |
| 1578 | if (ret) |
| 1579 | return ret; |
| 1580 | } |
| 1581 | |
| 1582 | virt = ring->virtual_start + ring->tail; |
| 1583 | rem /= 4; |
| 1584 | while (rem--) |
| 1585 | iowrite32(MI_NOOP, virt++); |
| 1586 | |
| 1587 | ring->tail = 0; |
| 1588 | ring->space = ring_space(ring); |
| 1589 | |
| 1590 | return 0; |
| 1591 | } |
| 1592 | |
| 1593 | int intel_ring_idle(struct intel_ring_buffer *ring) |
| 1594 | { |
| 1595 | u32 seqno; |
| 1596 | int ret; |
| 1597 | |
| 1598 | /* We need to add any requests required to flush the objects and ring */ |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1599 | if (ring->outstanding_lazy_seqno) { |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 1600 | ret = i915_add_request(ring, NULL); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1601 | if (ret) |
| 1602 | return ret; |
| 1603 | } |
| 1604 | |
| 1605 | /* Wait upon the last request to be completed */ |
| 1606 | if (list_empty(&ring->request_list)) |
| 1607 | return 0; |
| 1608 | |
| 1609 | seqno = list_entry(ring->request_list.prev, |
| 1610 | struct drm_i915_gem_request, |
| 1611 | list)->seqno; |
| 1612 | |
| 1613 | return i915_wait_seqno(ring, seqno); |
| 1614 | } |
| 1615 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1616 | static int |
| 1617 | intel_ring_alloc_seqno(struct intel_ring_buffer *ring) |
| 1618 | { |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1619 | if (ring->outstanding_lazy_seqno) |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1620 | return 0; |
| 1621 | |
Chris Wilson | 3c0e234 | 2013-09-04 10:45:52 +0100 | [diff] [blame] | 1622 | if (ring->preallocated_lazy_request == NULL) { |
| 1623 | struct drm_i915_gem_request *request; |
| 1624 | |
| 1625 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
| 1626 | if (request == NULL) |
| 1627 | return -ENOMEM; |
| 1628 | |
| 1629 | ring->preallocated_lazy_request = request; |
| 1630 | } |
| 1631 | |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1632 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1633 | } |
| 1634 | |
Chris Wilson | 304d695 | 2014-01-02 14:32:35 +0000 | [diff] [blame] | 1635 | static int __intel_ring_prepare(struct intel_ring_buffer *ring, |
| 1636 | int bytes) |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 1637 | { |
| 1638 | int ret; |
| 1639 | |
| 1640 | if (unlikely(ring->tail + bytes > ring->effective_size)) { |
| 1641 | ret = intel_wrap_ring_buffer(ring); |
| 1642 | if (unlikely(ret)) |
| 1643 | return ret; |
| 1644 | } |
| 1645 | |
| 1646 | if (unlikely(ring->space < bytes)) { |
| 1647 | ret = ring_wait_for_space(ring, bytes); |
| 1648 | if (unlikely(ret)) |
| 1649 | return ret; |
| 1650 | } |
| 1651 | |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 1652 | return 0; |
| 1653 | } |
| 1654 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1655 | int intel_ring_begin(struct intel_ring_buffer *ring, |
| 1656 | int num_dwords) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1657 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1658 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1659 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1660 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1661 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 1662 | dev_priv->mm.interruptible); |
Daniel Vetter | de2b998 | 2012-07-04 22:52:50 +0200 | [diff] [blame] | 1663 | if (ret) |
| 1664 | return ret; |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 1665 | |
Chris Wilson | 304d695 | 2014-01-02 14:32:35 +0000 | [diff] [blame] | 1666 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
| 1667 | if (ret) |
| 1668 | return ret; |
| 1669 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1670 | /* Preallocate the olr before touching the ring */ |
| 1671 | ret = intel_ring_alloc_seqno(ring); |
| 1672 | if (ret) |
| 1673 | return ret; |
| 1674 | |
Chris Wilson | 304d695 | 2014-01-02 14:32:35 +0000 | [diff] [blame] | 1675 | ring->space -= num_dwords * sizeof(uint32_t); |
| 1676 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1677 | } |
| 1678 | |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 1679 | /* Align the ring tail to a cacheline boundary */ |
| 1680 | int intel_ring_cacheline_align(struct intel_ring_buffer *ring) |
| 1681 | { |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1682 | int num_dwords = (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 1683 | int ret; |
| 1684 | |
| 1685 | if (num_dwords == 0) |
| 1686 | return 0; |
| 1687 | |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1688 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 1689 | ret = intel_ring_begin(ring, num_dwords); |
| 1690 | if (ret) |
| 1691 | return ret; |
| 1692 | |
| 1693 | while (num_dwords--) |
| 1694 | intel_ring_emit(ring, MI_NOOP); |
| 1695 | |
| 1696 | intel_ring_advance(ring); |
| 1697 | |
| 1698 | return 0; |
| 1699 | } |
| 1700 | |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 1701 | void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno) |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 1702 | { |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 1703 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 1704 | |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1705 | BUG_ON(ring->outstanding_lazy_seqno); |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 1706 | |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 1707 | if (INTEL_INFO(ring->dev)->gen >= 6) { |
| 1708 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); |
| 1709 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); |
Ben Widawsky | 5020150 | 2013-08-12 16:53:03 -0700 | [diff] [blame] | 1710 | if (HAS_VEBOX(ring->dev)) |
| 1711 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1712 | } |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 1713 | |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 1714 | ring->set_seqno(ring, seqno); |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 1715 | ring->hangcheck.seqno = seqno; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1716 | } |
| 1717 | |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1718 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
| 1719 | u32 value) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1720 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1721 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1722 | |
| 1723 | /* Every tail move must follow the sequence below */ |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1724 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1725 | /* Disable notification that the ring is IDLE. The GT |
| 1726 | * will then assume that it is busy and bring it out of rc6. |
| 1727 | */ |
| 1728 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 1729 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
| 1730 | |
| 1731 | /* Clear the context id. Here be magic! */ |
| 1732 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); |
| 1733 | |
| 1734 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1735 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1736 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
| 1737 | 50)) |
| 1738 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1739 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1740 | /* Now that the ring is fully powered up, update the tail */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1741 | I915_WRITE_TAIL(ring, value); |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1742 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
| 1743 | |
| 1744 | /* Let the ring send IDLE messages to the GT again, |
| 1745 | * and so let it sleep to conserve power when idle. |
| 1746 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1747 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1748 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1749 | } |
| 1750 | |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 1751 | static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring, |
| 1752 | u32 invalidate, u32 flush) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1753 | { |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1754 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1755 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1756 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1757 | ret = intel_ring_begin(ring, 4); |
| 1758 | if (ret) |
| 1759 | return ret; |
| 1760 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1761 | cmd = MI_FLUSH_DW; |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 1762 | if (INTEL_INFO(ring->dev)->gen >= 8) |
| 1763 | cmd += 1; |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1764 | /* |
| 1765 | * Bspec vol 1c.5 - video engine command streamer: |
| 1766 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 1767 | * operation is complete. This bit is only valid when the |
| 1768 | * Post-Sync Operation field is a value of 1h or 3h." |
| 1769 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1770 | if (invalidate & I915_GEM_GPU_DOMAINS) |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1771 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
| 1772 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1773 | intel_ring_emit(ring, cmd); |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1774 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 1775 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
| 1776 | intel_ring_emit(ring, 0); /* upper addr */ |
| 1777 | intel_ring_emit(ring, 0); /* value */ |
| 1778 | } else { |
| 1779 | intel_ring_emit(ring, 0); |
| 1780 | intel_ring_emit(ring, MI_NOOP); |
| 1781 | } |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1782 | intel_ring_advance(ring); |
| 1783 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1784 | } |
| 1785 | |
| 1786 | static int |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 1787 | gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1788 | u32 offset, u32 len, |
| 1789 | unsigned flags) |
| 1790 | { |
Ben Widawsky | 28cf541 | 2013-11-02 21:07:26 -0700 | [diff] [blame] | 1791 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 1792 | bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL && |
| 1793 | !(flags & I915_DISPATCH_SECURE); |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 1794 | int ret; |
| 1795 | |
| 1796 | ret = intel_ring_begin(ring, 4); |
| 1797 | if (ret) |
| 1798 | return ret; |
| 1799 | |
| 1800 | /* FIXME(BDW): Address space and security selectors. */ |
Ben Widawsky | 28cf541 | 2013-11-02 21:07:26 -0700 | [diff] [blame] | 1801 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 1802 | intel_ring_emit(ring, offset); |
| 1803 | intel_ring_emit(ring, 0); |
| 1804 | intel_ring_emit(ring, MI_NOOP); |
| 1805 | intel_ring_advance(ring); |
| 1806 | |
| 1807 | return 0; |
| 1808 | } |
| 1809 | |
| 1810 | static int |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1811 | hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1812 | u32 offset, u32 len, |
| 1813 | unsigned flags) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1814 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1815 | int ret; |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1816 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1817 | ret = intel_ring_begin(ring, 2); |
| 1818 | if (ret) |
| 1819 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1820 | |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1821 | intel_ring_emit(ring, |
| 1822 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | |
| 1823 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); |
| 1824 | /* bit0-7 is the length on GEN6+ */ |
| 1825 | intel_ring_emit(ring, offset); |
| 1826 | intel_ring_advance(ring); |
| 1827 | |
| 1828 | return 0; |
| 1829 | } |
| 1830 | |
| 1831 | static int |
| 1832 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1833 | u32 offset, u32 len, |
| 1834 | unsigned flags) |
| 1835 | { |
| 1836 | int ret; |
| 1837 | |
| 1838 | ret = intel_ring_begin(ring, 2); |
| 1839 | if (ret) |
| 1840 | return ret; |
| 1841 | |
| 1842 | intel_ring_emit(ring, |
| 1843 | MI_BATCH_BUFFER_START | |
| 1844 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1845 | /* bit0-7 is the length on GEN6+ */ |
| 1846 | intel_ring_emit(ring, offset); |
| 1847 | intel_ring_advance(ring); |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1848 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1849 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1850 | } |
| 1851 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1852 | /* Blitter support (SandyBridge+) */ |
| 1853 | |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 1854 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
| 1855 | u32 invalidate, u32 flush) |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1856 | { |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 1857 | struct drm_device *dev = ring->dev; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1858 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1859 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1860 | |
Daniel Vetter | 6a233c7 | 2011-12-14 13:57:07 +0100 | [diff] [blame] | 1861 | ret = intel_ring_begin(ring, 4); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1862 | if (ret) |
| 1863 | return ret; |
| 1864 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1865 | cmd = MI_FLUSH_DW; |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 1866 | if (INTEL_INFO(ring->dev)->gen >= 8) |
| 1867 | cmd += 1; |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1868 | /* |
| 1869 | * Bspec vol 1c.3 - blitter engine command streamer: |
| 1870 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 1871 | * operation is complete. This bit is only valid when the |
| 1872 | * Post-Sync Operation field is a value of 1h or 3h." |
| 1873 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1874 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1875 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
Daniel Vetter | b3fcabb | 2012-11-04 12:24:47 +0100 | [diff] [blame] | 1876 | MI_FLUSH_DW_OP_STOREDW; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1877 | intel_ring_emit(ring, cmd); |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1878 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 1879 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
| 1880 | intel_ring_emit(ring, 0); /* upper addr */ |
| 1881 | intel_ring_emit(ring, 0); /* value */ |
| 1882 | } else { |
| 1883 | intel_ring_emit(ring, 0); |
| 1884 | intel_ring_emit(ring, MI_NOOP); |
| 1885 | } |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1886 | intel_ring_advance(ring); |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 1887 | |
Ville Syrjälä | 9688eca | 2013-11-06 23:02:19 +0200 | [diff] [blame] | 1888 | if (IS_GEN7(dev) && !invalidate && flush) |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 1889 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); |
| 1890 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1891 | return 0; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1892 | } |
| 1893 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1894 | int intel_init_render_ring_buffer(struct drm_device *dev) |
| 1895 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1896 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1897 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1898 | |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1899 | ring->name = "render ring"; |
| 1900 | ring->id = RCS; |
| 1901 | ring->mmio_base = RENDER_RING_BASE; |
| 1902 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1903 | if (INTEL_INFO(dev)->gen >= 6) { |
| 1904 | ring->add_request = gen6_add_request; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 1905 | ring->flush = gen7_render_ring_flush; |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 1906 | if (INTEL_INFO(dev)->gen == 6) |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 1907 | ring->flush = gen6_render_ring_flush; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1908 | if (INTEL_INFO(dev)->gen >= 8) { |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 1909 | ring->flush = gen8_render_ring_flush; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1910 | ring->irq_get = gen8_ring_get_irq; |
| 1911 | ring->irq_put = gen8_ring_put_irq; |
| 1912 | } else { |
| 1913 | ring->irq_get = gen6_ring_get_irq; |
| 1914 | ring->irq_put = gen6_ring_put_irq; |
| 1915 | } |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1916 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1917 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1918 | ring->set_seqno = ring_set_seqno; |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1919 | ring->sync_to = gen6_ring_sync; |
Ben Widawsky | 5586181 | 2013-05-28 19:22:17 -0700 | [diff] [blame] | 1920 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 1921 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV; |
| 1922 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB; |
Ben Widawsky | 1950de1 | 2013-05-28 19:22:20 -0700 | [diff] [blame] | 1923 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE; |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 1924 | ring->signal_mbox[RCS] = GEN6_NOSYNC; |
| 1925 | ring->signal_mbox[VCS] = GEN6_VRSYNC; |
| 1926 | ring->signal_mbox[BCS] = GEN6_BRSYNC; |
Ben Widawsky | 1950de1 | 2013-05-28 19:22:20 -0700 | [diff] [blame] | 1927 | ring->signal_mbox[VECS] = GEN6_VERSYNC; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1928 | } else if (IS_GEN5(dev)) { |
| 1929 | ring->add_request = pc_render_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 1930 | ring->flush = gen4_render_ring_flush; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1931 | ring->get_seqno = pc_render_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1932 | ring->set_seqno = pc_render_set_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1933 | ring->irq_get = gen5_ring_get_irq; |
| 1934 | ring->irq_put = gen5_ring_put_irq; |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1935 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
| 1936 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1937 | } else { |
Daniel Vetter | 8620a3a | 2012-04-11 22:12:57 +0200 | [diff] [blame] | 1938 | ring->add_request = i9xx_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 1939 | if (INTEL_INFO(dev)->gen < 4) |
| 1940 | ring->flush = gen2_render_ring_flush; |
| 1941 | else |
| 1942 | ring->flush = gen4_render_ring_flush; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1943 | ring->get_seqno = ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1944 | ring->set_seqno = ring_set_seqno; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1945 | if (IS_GEN2(dev)) { |
| 1946 | ring->irq_get = i8xx_ring_get_irq; |
| 1947 | ring->irq_put = i8xx_ring_put_irq; |
| 1948 | } else { |
| 1949 | ring->irq_get = i9xx_ring_get_irq; |
| 1950 | ring->irq_put = i9xx_ring_put_irq; |
| 1951 | } |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1952 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1953 | } |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1954 | ring->write_tail = ring_write_tail; |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1955 | if (IS_HASWELL(dev)) |
| 1956 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 1957 | else if (IS_GEN8(dev)) |
| 1958 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1959 | else if (INTEL_INFO(dev)->gen >= 6) |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1960 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
| 1961 | else if (INTEL_INFO(dev)->gen >= 4) |
| 1962 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
| 1963 | else if (IS_I830(dev) || IS_845G(dev)) |
| 1964 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
| 1965 | else |
| 1966 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1967 | ring->init = init_render_ring; |
| 1968 | ring->cleanup = render_ring_cleanup; |
| 1969 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1970 | /* Workaround batchbuffer to combat CS tlb bug. */ |
| 1971 | if (HAS_BROKEN_CS_TLB(dev)) { |
| 1972 | struct drm_i915_gem_object *obj; |
| 1973 | int ret; |
| 1974 | |
| 1975 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); |
| 1976 | if (obj == NULL) { |
| 1977 | DRM_ERROR("Failed to allocate batch bo\n"); |
| 1978 | return -ENOMEM; |
| 1979 | } |
| 1980 | |
Daniel Vetter | be1fa12 | 2014-02-14 14:01:14 +0100 | [diff] [blame] | 1981 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1982 | if (ret != 0) { |
| 1983 | drm_gem_object_unreference(&obj->base); |
| 1984 | DRM_ERROR("Failed to ping batch bo\n"); |
| 1985 | return ret; |
| 1986 | } |
| 1987 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 1988 | ring->scratch.obj = obj; |
| 1989 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1990 | } |
| 1991 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1992 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1993 | } |
| 1994 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1995 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
| 1996 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1997 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1998 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1999 | int ret; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2000 | |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2001 | ring->name = "render ring"; |
| 2002 | ring->id = RCS; |
| 2003 | ring->mmio_base = RENDER_RING_BASE; |
| 2004 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2005 | if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | b4178f8 | 2012-04-11 22:12:51 +0200 | [diff] [blame] | 2006 | /* non-kms not supported on gen6+ */ |
| 2007 | return -ENODEV; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2008 | } |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 2009 | |
| 2010 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding |
| 2011 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up |
| 2012 | * the special gen5 functions. */ |
| 2013 | ring->add_request = i9xx_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 2014 | if (INTEL_INFO(dev)->gen < 4) |
| 2015 | ring->flush = gen2_render_ring_flush; |
| 2016 | else |
| 2017 | ring->flush = gen4_render_ring_flush; |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 2018 | ring->get_seqno = ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2019 | ring->set_seqno = ring_set_seqno; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2020 | if (IS_GEN2(dev)) { |
| 2021 | ring->irq_get = i8xx_ring_get_irq; |
| 2022 | ring->irq_put = i8xx_ring_put_irq; |
| 2023 | } else { |
| 2024 | ring->irq_get = i9xx_ring_get_irq; |
| 2025 | ring->irq_put = i9xx_ring_put_irq; |
| 2026 | } |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 2027 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2028 | ring->write_tail = ring_write_tail; |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 2029 | if (INTEL_INFO(dev)->gen >= 4) |
| 2030 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
| 2031 | else if (IS_I830(dev) || IS_845G(dev)) |
| 2032 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
| 2033 | else |
| 2034 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2035 | ring->init = init_render_ring; |
| 2036 | ring->cleanup = render_ring_cleanup; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2037 | |
| 2038 | ring->dev = dev; |
| 2039 | INIT_LIST_HEAD(&ring->active_list); |
| 2040 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2041 | |
| 2042 | ring->size = size; |
| 2043 | ring->effective_size = ring->size; |
Mika Kuoppala | 17f10fd | 2012-10-29 16:59:26 +0200 | [diff] [blame] | 2044 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 2045 | ring->effective_size -= 2 * CACHELINE_BYTES; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2046 | |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 2047 | ring->virtual_start = ioremap_wc(start, size); |
| 2048 | if (ring->virtual_start == NULL) { |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2049 | DRM_ERROR("can not ioremap virtual address for" |
| 2050 | " ring buffer\n"); |
| 2051 | return -ENOMEM; |
| 2052 | } |
| 2053 | |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2054 | if (!I915_NEED_GFX_HWS(dev)) { |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 2055 | ret = init_phys_status_page(ring); |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2056 | if (ret) |
| 2057 | return ret; |
| 2058 | } |
| 2059 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2060 | return 0; |
| 2061 | } |
| 2062 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2063 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
| 2064 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2065 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2066 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2067 | |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2068 | ring->name = "bsd ring"; |
| 2069 | ring->id = VCS; |
| 2070 | |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 2071 | ring->write_tail = ring_write_tail; |
Ben Widawsky | 780f18c | 2013-11-02 21:07:28 -0700 | [diff] [blame] | 2072 | if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2073 | ring->mmio_base = GEN6_BSD_RING_BASE; |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 2074 | /* gen6 bsd needs a special wa for tail updates */ |
| 2075 | if (IS_GEN6(dev)) |
| 2076 | ring->write_tail = gen6_bsd_ring_write_tail; |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2077 | ring->flush = gen6_bsd_ring_flush; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2078 | ring->add_request = gen6_add_request; |
| 2079 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2080 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2081 | if (INTEL_INFO(dev)->gen >= 8) { |
| 2082 | ring->irq_enable_mask = |
| 2083 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
| 2084 | ring->irq_get = gen8_ring_get_irq; |
| 2085 | ring->irq_put = gen8_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2086 | ring->dispatch_execbuffer = |
| 2087 | gen8_ring_dispatch_execbuffer; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2088 | } else { |
| 2089 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
| 2090 | ring->irq_get = gen6_ring_get_irq; |
| 2091 | ring->irq_put = gen6_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2092 | ring->dispatch_execbuffer = |
| 2093 | gen6_ring_dispatch_execbuffer; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2094 | } |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 2095 | ring->sync_to = gen6_ring_sync; |
Ben Widawsky | 5586181 | 2013-05-28 19:22:17 -0700 | [diff] [blame] | 2096 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR; |
| 2097 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2098 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB; |
Ben Widawsky | 1950de1 | 2013-05-28 19:22:20 -0700 | [diff] [blame] | 2099 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE; |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 2100 | ring->signal_mbox[RCS] = GEN6_RVSYNC; |
| 2101 | ring->signal_mbox[VCS] = GEN6_NOSYNC; |
| 2102 | ring->signal_mbox[BCS] = GEN6_BVSYNC; |
Ben Widawsky | 1950de1 | 2013-05-28 19:22:20 -0700 | [diff] [blame] | 2103 | ring->signal_mbox[VECS] = GEN6_VEVSYNC; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2104 | } else { |
| 2105 | ring->mmio_base = BSD_RING_BASE; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2106 | ring->flush = bsd_ring_flush; |
Daniel Vetter | 8620a3a | 2012-04-11 22:12:57 +0200 | [diff] [blame] | 2107 | ring->add_request = i9xx_add_request; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2108 | ring->get_seqno = ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2109 | ring->set_seqno = ring_set_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2110 | if (IS_GEN5(dev)) { |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 2111 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2112 | ring->irq_get = gen5_ring_get_irq; |
| 2113 | ring->irq_put = gen5_ring_put_irq; |
| 2114 | } else { |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 2115 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2116 | ring->irq_get = i9xx_ring_get_irq; |
| 2117 | ring->irq_put = i9xx_ring_put_irq; |
| 2118 | } |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 2119 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2120 | } |
| 2121 | ring->init = init_ring_common; |
| 2122 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2123 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2124 | } |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2125 | |
| 2126 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
| 2127 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2128 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2129 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2130 | |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 2131 | ring->name = "blitter ring"; |
| 2132 | ring->id = BCS; |
| 2133 | |
| 2134 | ring->mmio_base = BLT_RING_BASE; |
| 2135 | ring->write_tail = ring_write_tail; |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2136 | ring->flush = gen6_ring_flush; |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 2137 | ring->add_request = gen6_add_request; |
| 2138 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2139 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2140 | if (INTEL_INFO(dev)->gen >= 8) { |
| 2141 | ring->irq_enable_mask = |
| 2142 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
| 2143 | ring->irq_get = gen8_ring_get_irq; |
| 2144 | ring->irq_put = gen8_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2145 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2146 | } else { |
| 2147 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
| 2148 | ring->irq_get = gen6_ring_get_irq; |
| 2149 | ring->irq_put = gen6_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2150 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2151 | } |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 2152 | ring->sync_to = gen6_ring_sync; |
Ben Widawsky | 5586181 | 2013-05-28 19:22:17 -0700 | [diff] [blame] | 2153 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR; |
| 2154 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV; |
| 2155 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID; |
Ben Widawsky | 1950de1 | 2013-05-28 19:22:20 -0700 | [diff] [blame] | 2156 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE; |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 2157 | ring->signal_mbox[RCS] = GEN6_RBSYNC; |
| 2158 | ring->signal_mbox[VCS] = GEN6_VBSYNC; |
| 2159 | ring->signal_mbox[BCS] = GEN6_NOSYNC; |
Ben Widawsky | 1950de1 | 2013-05-28 19:22:20 -0700 | [diff] [blame] | 2160 | ring->signal_mbox[VECS] = GEN6_VEBSYNC; |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 2161 | ring->init = init_ring_common; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2162 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2163 | return intel_init_ring_buffer(dev, ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2164 | } |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2165 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 2166 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
| 2167 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2168 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 2169 | struct intel_ring_buffer *ring = &dev_priv->ring[VECS]; |
| 2170 | |
| 2171 | ring->name = "video enhancement ring"; |
| 2172 | ring->id = VECS; |
| 2173 | |
| 2174 | ring->mmio_base = VEBOX_RING_BASE; |
| 2175 | ring->write_tail = ring_write_tail; |
| 2176 | ring->flush = gen6_ring_flush; |
| 2177 | ring->add_request = gen6_add_request; |
| 2178 | ring->get_seqno = gen6_ring_get_seqno; |
| 2179 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2180 | |
| 2181 | if (INTEL_INFO(dev)->gen >= 8) { |
| 2182 | ring->irq_enable_mask = |
Daniel Vetter | 40c499f | 2013-11-07 21:40:39 -0800 | [diff] [blame] | 2183 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2184 | ring->irq_get = gen8_ring_get_irq; |
| 2185 | ring->irq_put = gen8_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2186 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2187 | } else { |
| 2188 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
| 2189 | ring->irq_get = hsw_vebox_get_irq; |
| 2190 | ring->irq_put = hsw_vebox_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2191 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2192 | } |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 2193 | ring->sync_to = gen6_ring_sync; |
| 2194 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER; |
| 2195 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV; |
| 2196 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB; |
| 2197 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2198 | ring->signal_mbox[RCS] = GEN6_RVESYNC; |
| 2199 | ring->signal_mbox[VCS] = GEN6_VVESYNC; |
| 2200 | ring->signal_mbox[BCS] = GEN6_BVESYNC; |
| 2201 | ring->signal_mbox[VECS] = GEN6_NOSYNC; |
| 2202 | ring->init = init_ring_common; |
| 2203 | |
| 2204 | return intel_init_ring_buffer(dev, ring); |
| 2205 | } |
| 2206 | |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2207 | int |
| 2208 | intel_ring_flush_all_caches(struct intel_ring_buffer *ring) |
| 2209 | { |
| 2210 | int ret; |
| 2211 | |
| 2212 | if (!ring->gpu_caches_dirty) |
| 2213 | return 0; |
| 2214 | |
| 2215 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 2216 | if (ret) |
| 2217 | return ret; |
| 2218 | |
| 2219 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 2220 | |
| 2221 | ring->gpu_caches_dirty = false; |
| 2222 | return 0; |
| 2223 | } |
| 2224 | |
| 2225 | int |
| 2226 | intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) |
| 2227 | { |
| 2228 | uint32_t flush_domains; |
| 2229 | int ret; |
| 2230 | |
| 2231 | flush_domains = 0; |
| 2232 | if (ring->gpu_caches_dirty) |
| 2233 | flush_domains = I915_GEM_GPU_DOMAINS; |
| 2234 | |
| 2235 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 2236 | if (ret) |
| 2237 | return ret; |
| 2238 | |
| 2239 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 2240 | |
| 2241 | ring->gpu_caches_dirty = false; |
| 2242 | return 0; |
| 2243 | } |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2244 | |
| 2245 | void |
| 2246 | intel_stop_ring_buffer(struct intel_ring_buffer *ring) |
| 2247 | { |
| 2248 | int ret; |
| 2249 | |
| 2250 | if (!intel_ring_initialized(ring)) |
| 2251 | return; |
| 2252 | |
| 2253 | ret = intel_ring_idle(ring); |
| 2254 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) |
| 2255 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
| 2256 | ring->name, ret); |
| 2257 | |
| 2258 | stop_ring(ring); |
| 2259 | } |