Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008-2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Zou Nan hai <nanhai.zou@intel.com> |
| 26 | * Xiang Hai hao<haihao.xiang@intel.com> |
| 27 | * |
| 28 | */ |
| 29 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/drmP.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 31 | #include "i915_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 32 | #include <drm/i915_drm.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 33 | #include "i915_trace.h" |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 34 | #include "intel_drv.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 35 | |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 36 | static inline int ring_space(struct intel_ring_buffer *ring) |
| 37 | { |
Ville Syrjälä | 633cf8f | 2012-12-03 18:43:32 +0200 | [diff] [blame] | 38 | int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE); |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 39 | if (space < 0) |
| 40 | space += ring->size; |
| 41 | return space; |
| 42 | } |
| 43 | |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame^] | 44 | static bool intel_ring_stopped(struct intel_ring_buffer *ring) |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 45 | { |
| 46 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame^] | 47 | return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring); |
| 48 | } |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 49 | |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame^] | 50 | void __intel_ring_advance(struct intel_ring_buffer *ring) |
| 51 | { |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 52 | ring->tail &= ring->size - 1; |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame^] | 53 | if (intel_ring_stopped(ring)) |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 54 | return; |
| 55 | ring->write_tail(ring, ring->tail); |
| 56 | } |
| 57 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 58 | static int |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 59 | gen2_render_ring_flush(struct intel_ring_buffer *ring, |
| 60 | u32 invalidate_domains, |
| 61 | u32 flush_domains) |
| 62 | { |
| 63 | u32 cmd; |
| 64 | int ret; |
| 65 | |
| 66 | cmd = MI_FLUSH; |
Daniel Vetter | 31b14c9 | 2012-04-19 16:45:22 +0200 | [diff] [blame] | 67 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 68 | cmd |= MI_NO_WRITE_FLUSH; |
| 69 | |
| 70 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 71 | cmd |= MI_READ_FLUSH; |
| 72 | |
| 73 | ret = intel_ring_begin(ring, 2); |
| 74 | if (ret) |
| 75 | return ret; |
| 76 | |
| 77 | intel_ring_emit(ring, cmd); |
| 78 | intel_ring_emit(ring, MI_NOOP); |
| 79 | intel_ring_advance(ring); |
| 80 | |
| 81 | return 0; |
| 82 | } |
| 83 | |
| 84 | static int |
| 85 | gen4_render_ring_flush(struct intel_ring_buffer *ring, |
| 86 | u32 invalidate_domains, |
| 87 | u32 flush_domains) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 88 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 89 | struct drm_device *dev = ring->dev; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 90 | u32 cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 91 | int ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 92 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 93 | /* |
| 94 | * read/write caches: |
| 95 | * |
| 96 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 97 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 98 | * also flushed at 2d versus 3d pipeline switches. |
| 99 | * |
| 100 | * read-only caches: |
| 101 | * |
| 102 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 103 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 104 | * |
| 105 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 106 | * |
| 107 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 108 | * invalidated when MI_EXE_FLUSH is set. |
| 109 | * |
| 110 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 111 | * invalidated with every MI_FLUSH. |
| 112 | * |
| 113 | * TLBs: |
| 114 | * |
| 115 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 116 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 117 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 118 | * are flushed at any MI_FLUSH. |
| 119 | */ |
| 120 | |
| 121 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 122 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 123 | cmd &= ~MI_NO_WRITE_FLUSH; |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 124 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 125 | cmd |= MI_EXE_FLUSH; |
| 126 | |
| 127 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
| 128 | (IS_G4X(dev) || IS_GEN5(dev))) |
| 129 | cmd |= MI_INVALIDATE_ISP; |
| 130 | |
| 131 | ret = intel_ring_begin(ring, 2); |
| 132 | if (ret) |
| 133 | return ret; |
| 134 | |
| 135 | intel_ring_emit(ring, cmd); |
| 136 | intel_ring_emit(ring, MI_NOOP); |
| 137 | intel_ring_advance(ring); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 138 | |
| 139 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 140 | } |
| 141 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 142 | /** |
| 143 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
| 144 | * implementing two workarounds on gen6. From section 1.4.7.1 |
| 145 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: |
| 146 | * |
| 147 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those |
| 148 | * produced by non-pipelined state commands), software needs to first |
| 149 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != |
| 150 | * 0. |
| 151 | * |
| 152 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable |
| 153 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. |
| 154 | * |
| 155 | * And the workaround for these two requires this workaround first: |
| 156 | * |
| 157 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent |
| 158 | * BEFORE the pipe-control with a post-sync op and no write-cache |
| 159 | * flushes. |
| 160 | * |
| 161 | * And this last workaround is tricky because of the requirements on |
| 162 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM |
| 163 | * volume 2 part 1: |
| 164 | * |
| 165 | * "1 of the following must also be set: |
| 166 | * - Render Target Cache Flush Enable ([12] of DW1) |
| 167 | * - Depth Cache Flush Enable ([0] of DW1) |
| 168 | * - Stall at Pixel Scoreboard ([1] of DW1) |
| 169 | * - Depth Stall ([13] of DW1) |
| 170 | * - Post-Sync Operation ([13] of DW1) |
| 171 | * - Notify Enable ([8] of DW1)" |
| 172 | * |
| 173 | * The cache flushes require the workaround flush that triggered this |
| 174 | * one, so we can't use it. Depth stall would trigger the same. |
| 175 | * Post-sync nonzero is what triggered this second workaround, so we |
| 176 | * can't use that one either. Notify enable is IRQs, which aren't |
| 177 | * really our business. That leaves only stall at scoreboard. |
| 178 | */ |
| 179 | static int |
| 180 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) |
| 181 | { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 182 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 183 | int ret; |
| 184 | |
| 185 | |
| 186 | ret = intel_ring_begin(ring, 6); |
| 187 | if (ret) |
| 188 | return ret; |
| 189 | |
| 190 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 191 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 192 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 193 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 194 | intel_ring_emit(ring, 0); /* low dword */ |
| 195 | intel_ring_emit(ring, 0); /* high dword */ |
| 196 | intel_ring_emit(ring, MI_NOOP); |
| 197 | intel_ring_advance(ring); |
| 198 | |
| 199 | ret = intel_ring_begin(ring, 6); |
| 200 | if (ret) |
| 201 | return ret; |
| 202 | |
| 203 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 204 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); |
| 205 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 206 | intel_ring_emit(ring, 0); |
| 207 | intel_ring_emit(ring, 0); |
| 208 | intel_ring_emit(ring, MI_NOOP); |
| 209 | intel_ring_advance(ring); |
| 210 | |
| 211 | return 0; |
| 212 | } |
| 213 | |
| 214 | static int |
| 215 | gen6_render_ring_flush(struct intel_ring_buffer *ring, |
| 216 | u32 invalidate_domains, u32 flush_domains) |
| 217 | { |
| 218 | u32 flags = 0; |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 219 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 220 | int ret; |
| 221 | |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 222 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
| 223 | ret = intel_emit_post_sync_nonzero_flush(ring); |
| 224 | if (ret) |
| 225 | return ret; |
| 226 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 227 | /* Just flush everything. Experiments have shown that reducing the |
| 228 | * number of bits based on the write domains has little performance |
| 229 | * impact. |
| 230 | */ |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 231 | if (flush_domains) { |
| 232 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 233 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 234 | /* |
| 235 | * Ensure that any following seqno writes only happen |
| 236 | * when the render cache is indeed flushed. |
| 237 | */ |
Daniel Vetter | 97f209b | 2012-06-28 09:48:42 +0200 | [diff] [blame] | 238 | flags |= PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 239 | } |
| 240 | if (invalidate_domains) { |
| 241 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 242 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 243 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 244 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 245 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 246 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 247 | /* |
| 248 | * TLB invalidate requires a post-sync write. |
| 249 | */ |
Jesse Barnes | 3ac7831 | 2012-10-25 12:15:47 -0700 | [diff] [blame] | 250 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 251 | } |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 252 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 253 | ret = intel_ring_begin(ring, 4); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 254 | if (ret) |
| 255 | return ret; |
| 256 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 257 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 258 | intel_ring_emit(ring, flags); |
| 259 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 260 | intel_ring_emit(ring, 0); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 261 | intel_ring_advance(ring); |
| 262 | |
| 263 | return 0; |
| 264 | } |
| 265 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 266 | static int |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 267 | gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) |
| 268 | { |
| 269 | int ret; |
| 270 | |
| 271 | ret = intel_ring_begin(ring, 4); |
| 272 | if (ret) |
| 273 | return ret; |
| 274 | |
| 275 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
| 276 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 277 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 278 | intel_ring_emit(ring, 0); |
| 279 | intel_ring_emit(ring, 0); |
| 280 | intel_ring_advance(ring); |
| 281 | |
| 282 | return 0; |
| 283 | } |
| 284 | |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 285 | static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value) |
| 286 | { |
| 287 | int ret; |
| 288 | |
| 289 | if (!ring->fbc_dirty) |
| 290 | return 0; |
| 291 | |
Ville Syrjälä | 37c1d94 | 2013-11-06 23:02:20 +0200 | [diff] [blame] | 292 | ret = intel_ring_begin(ring, 6); |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 293 | if (ret) |
| 294 | return ret; |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 295 | /* WaFbcNukeOn3DBlt:ivb/hsw */ |
| 296 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 297 | intel_ring_emit(ring, MSG_FBC_REND_STATE); |
| 298 | intel_ring_emit(ring, value); |
Ville Syrjälä | 37c1d94 | 2013-11-06 23:02:20 +0200 | [diff] [blame] | 299 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); |
| 300 | intel_ring_emit(ring, MSG_FBC_REND_STATE); |
| 301 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 302 | intel_ring_advance(ring); |
| 303 | |
| 304 | ring->fbc_dirty = false; |
| 305 | return 0; |
| 306 | } |
| 307 | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 308 | static int |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 309 | gen7_render_ring_flush(struct intel_ring_buffer *ring, |
| 310 | u32 invalidate_domains, u32 flush_domains) |
| 311 | { |
| 312 | u32 flags = 0; |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 313 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 314 | int ret; |
| 315 | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 316 | /* |
| 317 | * Ensure that any following seqno writes only happen when the render |
| 318 | * cache is indeed flushed. |
| 319 | * |
| 320 | * Workaround: 4th PIPE_CONTROL command (except the ones with only |
| 321 | * read-cache invalidate bits set) must have the CS_STALL bit set. We |
| 322 | * don't try to be clever and just set it unconditionally. |
| 323 | */ |
| 324 | flags |= PIPE_CONTROL_CS_STALL; |
| 325 | |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 326 | /* Just flush everything. Experiments have shown that reducing the |
| 327 | * number of bits based on the write domains has little performance |
| 328 | * impact. |
| 329 | */ |
| 330 | if (flush_domains) { |
| 331 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 332 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 333 | } |
| 334 | if (invalidate_domains) { |
| 335 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 336 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 337 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 338 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 339 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 340 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 341 | /* |
| 342 | * TLB invalidate requires a post-sync write. |
| 343 | */ |
| 344 | flags |= PIPE_CONTROL_QW_WRITE; |
Ville Syrjälä | b9e1faa | 2013-02-14 21:53:51 +0200 | [diff] [blame] | 345 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 346 | |
| 347 | /* Workaround: we must issue a pipe_control with CS-stall bit |
| 348 | * set before a pipe_control command that has the state cache |
| 349 | * invalidate bit set. */ |
| 350 | gen7_render_ring_cs_stall_wa(ring); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 351 | } |
| 352 | |
| 353 | ret = intel_ring_begin(ring, 4); |
| 354 | if (ret) |
| 355 | return ret; |
| 356 | |
| 357 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
| 358 | intel_ring_emit(ring, flags); |
Ville Syrjälä | b9e1faa | 2013-02-14 21:53:51 +0200 | [diff] [blame] | 359 | intel_ring_emit(ring, scratch_addr); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 360 | intel_ring_emit(ring, 0); |
| 361 | intel_ring_advance(ring); |
| 362 | |
Ville Syrjälä | 9688eca | 2013-11-06 23:02:19 +0200 | [diff] [blame] | 363 | if (!invalidate_domains && flush_domains) |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 364 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
| 365 | |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 366 | return 0; |
| 367 | } |
| 368 | |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 369 | static int |
| 370 | gen8_render_ring_flush(struct intel_ring_buffer *ring, |
| 371 | u32 invalidate_domains, u32 flush_domains) |
| 372 | { |
| 373 | u32 flags = 0; |
| 374 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
| 375 | int ret; |
| 376 | |
| 377 | flags |= PIPE_CONTROL_CS_STALL; |
| 378 | |
| 379 | if (flush_domains) { |
| 380 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 381 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 382 | } |
| 383 | if (invalidate_domains) { |
| 384 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 385 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 386 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 387 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 388 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 389 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 390 | flags |= PIPE_CONTROL_QW_WRITE; |
| 391 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
| 392 | } |
| 393 | |
| 394 | ret = intel_ring_begin(ring, 6); |
| 395 | if (ret) |
| 396 | return ret; |
| 397 | |
| 398 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
| 399 | intel_ring_emit(ring, flags); |
| 400 | intel_ring_emit(ring, scratch_addr); |
| 401 | intel_ring_emit(ring, 0); |
| 402 | intel_ring_emit(ring, 0); |
| 403 | intel_ring_emit(ring, 0); |
| 404 | intel_ring_advance(ring); |
| 405 | |
| 406 | return 0; |
| 407 | |
| 408 | } |
| 409 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 410 | static void ring_write_tail(struct intel_ring_buffer *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 411 | u32 value) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 412 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 413 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 414 | I915_WRITE_TAIL(ring, value); |
Xiang, Haihao | d46eefa | 2010-09-16 10:43:12 +0800 | [diff] [blame] | 415 | } |
| 416 | |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 417 | u64 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 418 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 419 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 420 | u64 acthd; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 421 | |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 422 | if (INTEL_INFO(ring->dev)->gen >= 8) |
| 423 | acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base), |
| 424 | RING_ACTHD_UDW(ring->mmio_base)); |
| 425 | else if (INTEL_INFO(ring->dev)->gen >= 4) |
| 426 | acthd = I915_READ(RING_ACTHD(ring->mmio_base)); |
| 427 | else |
| 428 | acthd = I915_READ(ACTHD); |
| 429 | |
| 430 | return acthd; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 431 | } |
| 432 | |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 433 | static void ring_setup_phys_status_page(struct intel_ring_buffer *ring) |
| 434 | { |
| 435 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 436 | u32 addr; |
| 437 | |
| 438 | addr = dev_priv->status_page_dmah->busaddr; |
| 439 | if (INTEL_INFO(ring->dev)->gen >= 4) |
| 440 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
| 441 | I915_WRITE(HWS_PGA, addr); |
| 442 | } |
| 443 | |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 444 | static bool stop_ring(struct intel_ring_buffer *ring) |
| 445 | { |
| 446 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
| 447 | |
| 448 | if (!IS_GEN2(ring->dev)) { |
| 449 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); |
| 450 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { |
| 451 | DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); |
| 452 | return false; |
| 453 | } |
| 454 | } |
| 455 | |
| 456 | I915_WRITE_CTL(ring, 0); |
| 457 | I915_WRITE_HEAD(ring, 0); |
| 458 | ring->write_tail(ring, 0); |
| 459 | |
| 460 | if (!IS_GEN2(ring->dev)) { |
| 461 | (void)I915_READ_CTL(ring); |
| 462 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); |
| 463 | } |
| 464 | |
| 465 | return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; |
| 466 | } |
| 467 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 468 | static int init_ring_common(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 469 | { |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 470 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 471 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 472 | struct drm_i915_gem_object *obj = ring->obj; |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 473 | int ret = 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 474 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 475 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 476 | |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 477 | if (!stop_ring(ring)) { |
| 478 | /* G45 ring initialization often fails to reset head to zero */ |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 479 | DRM_DEBUG_KMS("%s head not reset to zero " |
| 480 | "ctl %08x head %08x tail %08x start %08x\n", |
| 481 | ring->name, |
| 482 | I915_READ_CTL(ring), |
| 483 | I915_READ_HEAD(ring), |
| 484 | I915_READ_TAIL(ring), |
| 485 | I915_READ_START(ring)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 486 | |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 487 | if (!stop_ring(ring)) { |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 488 | DRM_ERROR("failed to set %s head to zero " |
| 489 | "ctl %08x head %08x tail %08x start %08x\n", |
| 490 | ring->name, |
| 491 | I915_READ_CTL(ring), |
| 492 | I915_READ_HEAD(ring), |
| 493 | I915_READ_TAIL(ring), |
| 494 | I915_READ_START(ring)); |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 495 | ret = -EIO; |
| 496 | goto out; |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 497 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 498 | } |
| 499 | |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 500 | if (I915_NEED_GFX_HWS(dev)) |
| 501 | intel_ring_setup_status_page(ring); |
| 502 | else |
| 503 | ring_setup_phys_status_page(ring); |
| 504 | |
Daniel Vetter | 0d8957c | 2012-08-07 09:54:14 +0200 | [diff] [blame] | 505 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
| 506 | * registers with the above sequence (the readback of the HEAD registers |
| 507 | * also enforces ordering), otherwise the hw might lose the new ring |
| 508 | * register values. */ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 509 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 510 | I915_WRITE_CTL(ring, |
Chris Wilson | ae69b42 | 2010-11-07 11:45:52 +0000 | [diff] [blame] | 511 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
Chris Wilson | 5d031e5 | 2012-02-08 13:34:13 +0000 | [diff] [blame] | 512 | | RING_VALID); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 513 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 514 | /* If the head is still not zero, the ring is dead */ |
Sean Paul | f01db98 | 2012-03-16 12:43:22 -0400 | [diff] [blame] | 515 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 516 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
Sean Paul | f01db98 | 2012-03-16 12:43:22 -0400 | [diff] [blame] | 517 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
Chris Wilson | e74cfed | 2010-11-09 10:16:56 +0000 | [diff] [blame] | 518 | DRM_ERROR("%s initialization failed " |
| 519 | "ctl %08x head %08x tail %08x start %08x\n", |
| 520 | ring->name, |
| 521 | I915_READ_CTL(ring), |
| 522 | I915_READ_HEAD(ring), |
| 523 | I915_READ_TAIL(ring), |
| 524 | I915_READ_START(ring)); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 525 | ret = -EIO; |
| 526 | goto out; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 527 | } |
| 528 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 529 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
| 530 | i915_kernel_lost_context(ring->dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 531 | else { |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 532 | ring->head = I915_READ_HEAD(ring); |
Daniel Vetter | 870e86d | 2010-08-02 16:29:44 +0200 | [diff] [blame] | 533 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 534 | ring->space = ring_space(ring); |
Chris Wilson | c3b2003 | 2012-05-28 22:33:02 +0100 | [diff] [blame] | 535 | ring->last_retired_head = -1; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 536 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 537 | |
Chris Wilson | 50f018d | 2013-06-10 11:20:19 +0100 | [diff] [blame] | 538 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
| 539 | |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 540 | out: |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 541 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 542 | |
| 543 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 544 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 545 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 546 | static int |
| 547 | init_pipe_control(struct intel_ring_buffer *ring) |
| 548 | { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 549 | int ret; |
| 550 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 551 | if (ring->scratch.obj) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 552 | return 0; |
| 553 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 554 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
| 555 | if (ring->scratch.obj == NULL) { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 556 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 557 | ret = -ENOMEM; |
| 558 | goto err; |
| 559 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 560 | |
Daniel Vetter | a9cc726 | 2014-02-14 14:01:13 +0100 | [diff] [blame] | 561 | ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
| 562 | if (ret) |
| 563 | goto err_unref; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 564 | |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 565 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 566 | if (ret) |
| 567 | goto err_unref; |
| 568 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 569 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
| 570 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); |
| 571 | if (ring->scratch.cpu_page == NULL) { |
Wei Yongjun | 56b085a | 2013-05-28 17:51:44 +0800 | [diff] [blame] | 572 | ret = -ENOMEM; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 573 | goto err_unpin; |
Wei Yongjun | 56b085a | 2013-05-28 17:51:44 +0800 | [diff] [blame] | 574 | } |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 575 | |
Ville Syrjälä | 2b1086c | 2013-02-12 22:01:38 +0200 | [diff] [blame] | 576 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 577 | ring->name, ring->scratch.gtt_offset); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 578 | return 0; |
| 579 | |
| 580 | err_unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 581 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 582 | err_unref: |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 583 | drm_gem_object_unreference(&ring->scratch.obj->base); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 584 | err: |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 585 | return ret; |
| 586 | } |
| 587 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 588 | static int init_render_ring(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 589 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 590 | struct drm_device *dev = ring->dev; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 591 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 592 | int ret = init_ring_common(ring); |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 593 | |
Akash Goel | 61a563a | 2014-03-25 18:01:50 +0530 | [diff] [blame] | 594 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
| 595 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 596 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 597 | |
| 598 | /* We need to disable the AsyncFlip performance optimisations in order |
| 599 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be |
| 600 | * programmed to '1' on all products. |
Damien Lespiau | 8693a82 | 2013-05-03 18:48:11 +0100 | [diff] [blame] | 601 | * |
Ville Syrjälä | 8285222 | 2014-02-27 21:59:03 +0200 | [diff] [blame] | 602 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 603 | */ |
| 604 | if (INTEL_INFO(dev)->gen >= 6) |
| 605 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
| 606 | |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 607 | /* Required for the hardware to program scanline values for waiting */ |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 608 | /* WaEnableFlushTlbInvalidationMode:snb */ |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 609 | if (INTEL_INFO(dev)->gen == 6) |
| 610 | I915_WRITE(GFX_MODE, |
Chris Wilson | aa83e30 | 2014-03-21 17:18:54 +0000 | [diff] [blame] | 611 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 612 | |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 613 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 614 | if (IS_GEN7(dev)) |
| 615 | I915_WRITE(GFX_MODE_GEN7, |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 616 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 617 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 618 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 619 | if (INTEL_INFO(dev)->gen >= 5) { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 620 | ret = init_pipe_control(ring); |
| 621 | if (ret) |
| 622 | return ret; |
| 623 | } |
| 624 | |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 625 | if (IS_GEN6(dev)) { |
Kenneth Graunke | 3a69ddd | 2012-04-27 12:44:41 -0700 | [diff] [blame] | 626 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
| 627 | * "If this bit is set, STCunit will have LRA as replacement |
| 628 | * policy. [...] This bit must be reset. LRA replacement |
| 629 | * policy is not supported." |
| 630 | */ |
| 631 | I915_WRITE(CACHE_MODE_0, |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 632 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 633 | } |
| 634 | |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 635 | if (INTEL_INFO(dev)->gen >= 6) |
| 636 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 637 | |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 638 | if (HAS_L3_DPF(dev)) |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 639 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 640 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 641 | return ret; |
| 642 | } |
| 643 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 644 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
| 645 | { |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 646 | struct drm_device *dev = ring->dev; |
| 647 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 648 | if (ring->scratch.obj == NULL) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 649 | return; |
| 650 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 651 | if (INTEL_INFO(dev)->gen >= 5) { |
| 652 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 653 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 654 | } |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 655 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 656 | drm_gem_object_unreference(&ring->scratch.obj->base); |
| 657 | ring->scratch.obj = NULL; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 658 | } |
| 659 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 660 | static void |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 661 | update_mboxes(struct intel_ring_buffer *ring, |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 662 | u32 mmio_offset) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 663 | { |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 664 | /* NB: In order to be able to do semaphore MBOX updates for varying number |
| 665 | * of rings, it's easiest if we round up each individual update to a |
| 666 | * multiple of 2 (since ring updates must always be a multiple of 2) |
| 667 | * even though the actual update only requires 3 dwords. |
| 668 | */ |
| 669 | #define MBOX_UPDATE_DWORDS 4 |
Chris Wilson | 1c8b46f | 2012-11-14 09:15:14 +0000 | [diff] [blame] | 670 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 671 | intel_ring_emit(ring, mmio_offset); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 672 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 673 | intel_ring_emit(ring, MI_NOOP); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 674 | } |
| 675 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 676 | /** |
| 677 | * gen6_add_request - Update the semaphore mailbox registers |
| 678 | * |
| 679 | * @ring - ring that is adding a request |
| 680 | * @seqno - return seqno stuck into the ring |
| 681 | * |
| 682 | * Update the mailbox registers in the *other* rings with the current seqno. |
| 683 | * This acts like a signal in the canonical semaphore. |
| 684 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 685 | static int |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 686 | gen6_add_request(struct intel_ring_buffer *ring) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 687 | { |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 688 | struct drm_device *dev = ring->dev; |
| 689 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 690 | struct intel_ring_buffer *useless; |
Ben Widawsky | 52ed232 | 2013-12-16 20:50:38 -0800 | [diff] [blame] | 691 | int i, ret, num_dwords = 4; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 692 | |
Ben Widawsky | 52ed232 | 2013-12-16 20:50:38 -0800 | [diff] [blame] | 693 | if (i915_semaphore_is_enabled(dev)) |
| 694 | num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS); |
| 695 | #undef MBOX_UPDATE_DWORDS |
| 696 | |
| 697 | ret = intel_ring_begin(ring, num_dwords); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 698 | if (ret) |
| 699 | return ret; |
| 700 | |
Ben Widawsky | f0a9f74 | 2013-12-17 20:06:00 -0800 | [diff] [blame] | 701 | if (i915_semaphore_is_enabled(dev)) { |
| 702 | for_each_ring(useless, dev_priv, i) { |
| 703 | u32 mbox_reg = ring->signal_mbox[i]; |
| 704 | if (mbox_reg != GEN6_NOSYNC) |
| 705 | update_mboxes(ring, mbox_reg); |
| 706 | } |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 707 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 708 | |
| 709 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 710 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 711 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 712 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 713 | __intel_ring_advance(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 714 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 715 | return 0; |
| 716 | } |
| 717 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 718 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
| 719 | u32 seqno) |
| 720 | { |
| 721 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 722 | return dev_priv->last_seqno < seqno; |
| 723 | } |
| 724 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 725 | /** |
| 726 | * intel_ring_sync - sync the waiter to the signaller on seqno |
| 727 | * |
| 728 | * @waiter - ring that is waiting |
| 729 | * @signaller - ring which has, or will signal |
| 730 | * @seqno - seqno which the waiter will block on |
| 731 | */ |
| 732 | static int |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 733 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
| 734 | struct intel_ring_buffer *signaller, |
| 735 | u32 seqno) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 736 | { |
| 737 | int ret; |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 738 | u32 dw1 = MI_SEMAPHORE_MBOX | |
| 739 | MI_SEMAPHORE_COMPARE | |
| 740 | MI_SEMAPHORE_REGISTER; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 741 | |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 742 | /* Throughout all of the GEM code, seqno passed implies our current |
| 743 | * seqno is >= the last seqno executed. However for hardware the |
| 744 | * comparison is strictly greater than. |
| 745 | */ |
| 746 | seqno -= 1; |
| 747 | |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 748 | WARN_ON(signaller->semaphore_register[waiter->id] == |
| 749 | MI_SEMAPHORE_SYNC_INVALID); |
| 750 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 751 | ret = intel_ring_begin(waiter, 4); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 752 | if (ret) |
| 753 | return ret; |
| 754 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 755 | /* If seqno wrap happened, omit the wait with no-ops */ |
| 756 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { |
| 757 | intel_ring_emit(waiter, |
| 758 | dw1 | |
| 759 | signaller->semaphore_register[waiter->id]); |
| 760 | intel_ring_emit(waiter, seqno); |
| 761 | intel_ring_emit(waiter, 0); |
| 762 | intel_ring_emit(waiter, MI_NOOP); |
| 763 | } else { |
| 764 | intel_ring_emit(waiter, MI_NOOP); |
| 765 | intel_ring_emit(waiter, MI_NOOP); |
| 766 | intel_ring_emit(waiter, MI_NOOP); |
| 767 | intel_ring_emit(waiter, MI_NOOP); |
| 768 | } |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 769 | intel_ring_advance(waiter); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 770 | |
| 771 | return 0; |
| 772 | } |
| 773 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 774 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
| 775 | do { \ |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 776 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
| 777 | PIPE_CONTROL_DEPTH_STALL); \ |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 778 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
| 779 | intel_ring_emit(ring__, 0); \ |
| 780 | intel_ring_emit(ring__, 0); \ |
| 781 | } while (0) |
| 782 | |
| 783 | static int |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 784 | pc_render_add_request(struct intel_ring_buffer *ring) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 785 | { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 786 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 787 | int ret; |
| 788 | |
| 789 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
| 790 | * incoherent with writes to memory, i.e. completely fubar, |
| 791 | * so we need to use PIPE_NOTIFY instead. |
| 792 | * |
| 793 | * However, we also need to workaround the qword write |
| 794 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
| 795 | * memory before requesting an interrupt. |
| 796 | */ |
| 797 | ret = intel_ring_begin(ring, 32); |
| 798 | if (ret) |
| 799 | return ret; |
| 800 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 801 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 802 | PIPE_CONTROL_WRITE_FLUSH | |
| 803 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 804 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 805 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 806 | intel_ring_emit(ring, 0); |
| 807 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 808 | scratch_addr += 128; /* write to separate cachelines */ |
| 809 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 810 | scratch_addr += 128; |
| 811 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 812 | scratch_addr += 128; |
| 813 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 814 | scratch_addr += 128; |
| 815 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 816 | scratch_addr += 128; |
| 817 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 818 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 819 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 820 | PIPE_CONTROL_WRITE_FLUSH | |
| 821 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 822 | PIPE_CONTROL_NOTIFY); |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 823 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 824 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 825 | intel_ring_emit(ring, 0); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 826 | __intel_ring_advance(ring); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 827 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 828 | return 0; |
| 829 | } |
| 830 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 831 | static u32 |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 832 | gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 833 | { |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 834 | /* Workaround to force correct ordering between irq and seqno writes on |
| 835 | * ivb (and maybe also on snb) by reading from a CS register (like |
| 836 | * ACTHD) before reading the status page. */ |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 837 | if (!lazy_coherency) { |
| 838 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 839 | POSTING_READ(RING_ACTHD(ring->mmio_base)); |
| 840 | } |
| 841 | |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 842 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 843 | } |
| 844 | |
| 845 | static u32 |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 846 | ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 847 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 848 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 849 | } |
| 850 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 851 | static void |
| 852 | ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 853 | { |
| 854 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); |
| 855 | } |
| 856 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 857 | static u32 |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 858 | pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 859 | { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 860 | return ring->scratch.cpu_page[0]; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 861 | } |
| 862 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 863 | static void |
| 864 | pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 865 | { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 866 | ring->scratch.cpu_page[0] = seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 867 | } |
| 868 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 869 | static bool |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 870 | gen5_ring_get_irq(struct intel_ring_buffer *ring) |
| 871 | { |
| 872 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 873 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 874 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 875 | |
| 876 | if (!dev->irq_enabled) |
| 877 | return false; |
| 878 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 879 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 880 | if (ring->irq_refcount++ == 0) |
| 881 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 882 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 883 | |
| 884 | return true; |
| 885 | } |
| 886 | |
| 887 | static void |
| 888 | gen5_ring_put_irq(struct intel_ring_buffer *ring) |
| 889 | { |
| 890 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 891 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 892 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 893 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 894 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 895 | if (--ring->irq_refcount == 0) |
| 896 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 897 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 898 | } |
| 899 | |
| 900 | static bool |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 901 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 902 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 903 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 904 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 905 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 906 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 907 | if (!dev->irq_enabled) |
| 908 | return false; |
| 909 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 910 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 911 | if (ring->irq_refcount++ == 0) { |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 912 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 913 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 914 | POSTING_READ(IMR); |
| 915 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 916 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 917 | |
| 918 | return true; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 919 | } |
| 920 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 921 | static void |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 922 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 923 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 924 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 925 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 926 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 927 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 928 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 929 | if (--ring->irq_refcount == 0) { |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 930 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 931 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 932 | POSTING_READ(IMR); |
| 933 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 934 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 935 | } |
| 936 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 937 | static bool |
| 938 | i8xx_ring_get_irq(struct intel_ring_buffer *ring) |
| 939 | { |
| 940 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 941 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 942 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 943 | |
| 944 | if (!dev->irq_enabled) |
| 945 | return false; |
| 946 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 947 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 948 | if (ring->irq_refcount++ == 0) { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 949 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 950 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 951 | POSTING_READ16(IMR); |
| 952 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 953 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 954 | |
| 955 | return true; |
| 956 | } |
| 957 | |
| 958 | static void |
| 959 | i8xx_ring_put_irq(struct intel_ring_buffer *ring) |
| 960 | { |
| 961 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 962 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 963 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 964 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 965 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 966 | if (--ring->irq_refcount == 0) { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 967 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 968 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 969 | POSTING_READ16(IMR); |
| 970 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 971 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 972 | } |
| 973 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 974 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 975 | { |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 976 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 977 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 978 | u32 mmio = 0; |
| 979 | |
| 980 | /* The ring status page addresses are no longer next to the rest of |
| 981 | * the ring registers as of gen7. |
| 982 | */ |
| 983 | if (IS_GEN7(dev)) { |
| 984 | switch (ring->id) { |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 985 | case RCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 986 | mmio = RENDER_HWS_PGA_GEN7; |
| 987 | break; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 988 | case BCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 989 | mmio = BLT_HWS_PGA_GEN7; |
| 990 | break; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 991 | case VCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 992 | mmio = BSD_HWS_PGA_GEN7; |
| 993 | break; |
Ben Widawsky | 4a3dd19 | 2013-05-28 19:22:19 -0700 | [diff] [blame] | 994 | case VECS: |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 995 | mmio = VEBOX_HWS_PGA_GEN7; |
| 996 | break; |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 997 | } |
| 998 | } else if (IS_GEN6(ring->dev)) { |
| 999 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); |
| 1000 | } else { |
Ben Widawsky | eb0d4b7 | 2013-11-07 21:40:50 -0800 | [diff] [blame] | 1001 | /* XXX: gen8 returns to sanity */ |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 1002 | mmio = RING_HWS_PGA(ring->mmio_base); |
| 1003 | } |
| 1004 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1005 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
| 1006 | POSTING_READ(mmio); |
Chris Wilson | 884020b | 2013-08-06 19:01:14 +0100 | [diff] [blame] | 1007 | |
Damien Lespiau | dc616b8 | 2014-03-13 01:40:28 +0000 | [diff] [blame] | 1008 | /* |
| 1009 | * Flush the TLB for this page |
| 1010 | * |
| 1011 | * FIXME: These two bits have disappeared on gen8, so a question |
| 1012 | * arises: do we still need this and if so how should we go about |
| 1013 | * invalidating the TLB? |
| 1014 | */ |
| 1015 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { |
Chris Wilson | 884020b | 2013-08-06 19:01:14 +0100 | [diff] [blame] | 1016 | u32 reg = RING_INSTPM(ring->mmio_base); |
Naresh Kumar Kachhi | 02f6a1e | 2014-03-12 16:39:42 +0530 | [diff] [blame] | 1017 | |
| 1018 | /* ring should be idle before issuing a sync flush*/ |
| 1019 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); |
| 1020 | |
Chris Wilson | 884020b | 2013-08-06 19:01:14 +0100 | [diff] [blame] | 1021 | I915_WRITE(reg, |
| 1022 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | |
| 1023 | INSTPM_SYNC_FLUSH)); |
| 1024 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, |
| 1025 | 1000)) |
| 1026 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
| 1027 | ring->name); |
| 1028 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1029 | } |
| 1030 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1031 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1032 | bsd_ring_flush(struct intel_ring_buffer *ring, |
| 1033 | u32 invalidate_domains, |
| 1034 | u32 flush_domains) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1035 | { |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1036 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1037 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1038 | ret = intel_ring_begin(ring, 2); |
| 1039 | if (ret) |
| 1040 | return ret; |
| 1041 | |
| 1042 | intel_ring_emit(ring, MI_FLUSH); |
| 1043 | intel_ring_emit(ring, MI_NOOP); |
| 1044 | intel_ring_advance(ring); |
| 1045 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1046 | } |
| 1047 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1048 | static int |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1049 | i9xx_add_request(struct intel_ring_buffer *ring) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1050 | { |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1051 | int ret; |
| 1052 | |
| 1053 | ret = intel_ring_begin(ring, 4); |
| 1054 | if (ret) |
| 1055 | return ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 1056 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1057 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 1058 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1059 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1060 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 1061 | __intel_ring_advance(ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1062 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1063 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1064 | } |
| 1065 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1066 | static bool |
Ben Widawsky | 25c0630 | 2012-03-29 19:11:27 -0700 | [diff] [blame] | 1067 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1068 | { |
| 1069 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1070 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1071 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1072 | |
| 1073 | if (!dev->irq_enabled) |
| 1074 | return false; |
| 1075 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1076 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1077 | if (ring->irq_refcount++ == 0) { |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 1078 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1079 | I915_WRITE_IMR(ring, |
| 1080 | ~(ring->irq_enable_mask | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1081 | GT_PARITY_ERROR(dev))); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 1082 | else |
| 1083 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 1084 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1085 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1086 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1087 | |
| 1088 | return true; |
| 1089 | } |
| 1090 | |
| 1091 | static void |
Ben Widawsky | 25c0630 | 2012-03-29 19:11:27 -0700 | [diff] [blame] | 1092 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1093 | { |
| 1094 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1095 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1096 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1097 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1098 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1099 | if (--ring->irq_refcount == 0) { |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 1100 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1101 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 1102 | else |
| 1103 | I915_WRITE_IMR(ring, ~0); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 1104 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1105 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1106 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1107 | } |
| 1108 | |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1109 | static bool |
| 1110 | hsw_vebox_get_irq(struct intel_ring_buffer *ring) |
| 1111 | { |
| 1112 | struct drm_device *dev = ring->dev; |
| 1113 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1114 | unsigned long flags; |
| 1115 | |
| 1116 | if (!dev->irq_enabled) |
| 1117 | return false; |
| 1118 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1119 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1120 | if (ring->irq_refcount++ == 0) { |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1121 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 1122 | snb_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1123 | } |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1124 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1125 | |
| 1126 | return true; |
| 1127 | } |
| 1128 | |
| 1129 | static void |
| 1130 | hsw_vebox_put_irq(struct intel_ring_buffer *ring) |
| 1131 | { |
| 1132 | struct drm_device *dev = ring->dev; |
| 1133 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1134 | unsigned long flags; |
| 1135 | |
| 1136 | if (!dev->irq_enabled) |
| 1137 | return; |
| 1138 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1139 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1140 | if (--ring->irq_refcount == 0) { |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1141 | I915_WRITE_IMR(ring, ~0); |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 1142 | snb_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1143 | } |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1144 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1145 | } |
| 1146 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1147 | static bool |
| 1148 | gen8_ring_get_irq(struct intel_ring_buffer *ring) |
| 1149 | { |
| 1150 | struct drm_device *dev = ring->dev; |
| 1151 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1152 | unsigned long flags; |
| 1153 | |
| 1154 | if (!dev->irq_enabled) |
| 1155 | return false; |
| 1156 | |
| 1157 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1158 | if (ring->irq_refcount++ == 0) { |
| 1159 | if (HAS_L3_DPF(dev) && ring->id == RCS) { |
| 1160 | I915_WRITE_IMR(ring, |
| 1161 | ~(ring->irq_enable_mask | |
| 1162 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); |
| 1163 | } else { |
| 1164 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
| 1165 | } |
| 1166 | POSTING_READ(RING_IMR(ring->mmio_base)); |
| 1167 | } |
| 1168 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1169 | |
| 1170 | return true; |
| 1171 | } |
| 1172 | |
| 1173 | static void |
| 1174 | gen8_ring_put_irq(struct intel_ring_buffer *ring) |
| 1175 | { |
| 1176 | struct drm_device *dev = ring->dev; |
| 1177 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1178 | unsigned long flags; |
| 1179 | |
| 1180 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1181 | if (--ring->irq_refcount == 0) { |
| 1182 | if (HAS_L3_DPF(dev) && ring->id == RCS) { |
| 1183 | I915_WRITE_IMR(ring, |
| 1184 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
| 1185 | } else { |
| 1186 | I915_WRITE_IMR(ring, ~0); |
| 1187 | } |
| 1188 | POSTING_READ(RING_IMR(ring->mmio_base)); |
| 1189 | } |
| 1190 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1191 | } |
| 1192 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1193 | static int |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1194 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1195 | u32 offset, u32 length, |
| 1196 | unsigned flags) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1197 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1198 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1199 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1200 | ret = intel_ring_begin(ring, 2); |
| 1201 | if (ret) |
| 1202 | return ret; |
| 1203 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1204 | intel_ring_emit(ring, |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 1205 | MI_BATCH_BUFFER_START | |
| 1206 | MI_BATCH_GTT | |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1207 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1208 | intel_ring_emit(ring, offset); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1209 | intel_ring_advance(ring); |
| 1210 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1211 | return 0; |
| 1212 | } |
| 1213 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1214 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
| 1215 | #define I830_BATCH_LIMIT (256*1024) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1216 | static int |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1217 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1218 | u32 offset, u32 len, |
| 1219 | unsigned flags) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1220 | { |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1221 | int ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1222 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1223 | if (flags & I915_DISPATCH_PINNED) { |
| 1224 | ret = intel_ring_begin(ring, 4); |
| 1225 | if (ret) |
| 1226 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1227 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1228 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 1229 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
| 1230 | intel_ring_emit(ring, offset + len - 8); |
| 1231 | intel_ring_emit(ring, MI_NOOP); |
| 1232 | intel_ring_advance(ring); |
| 1233 | } else { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 1234 | u32 cs_offset = ring->scratch.gtt_offset; |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1235 | |
| 1236 | if (len > I830_BATCH_LIMIT) |
| 1237 | return -ENOSPC; |
| 1238 | |
| 1239 | ret = intel_ring_begin(ring, 9+3); |
| 1240 | if (ret) |
| 1241 | return ret; |
| 1242 | /* Blit the batch (which has now all relocs applied) to the stable batch |
| 1243 | * scratch bo area (so that the CS never stumbles over its tlb |
| 1244 | * invalidation bug) ... */ |
| 1245 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | |
| 1246 | XY_SRC_COPY_BLT_WRITE_ALPHA | |
| 1247 | XY_SRC_COPY_BLT_WRITE_RGB); |
| 1248 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); |
| 1249 | intel_ring_emit(ring, 0); |
| 1250 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); |
| 1251 | intel_ring_emit(ring, cs_offset); |
| 1252 | intel_ring_emit(ring, 0); |
| 1253 | intel_ring_emit(ring, 4096); |
| 1254 | intel_ring_emit(ring, offset); |
| 1255 | intel_ring_emit(ring, MI_FLUSH); |
| 1256 | |
| 1257 | /* ... and execute it. */ |
| 1258 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 1259 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
| 1260 | intel_ring_emit(ring, cs_offset + len - 8); |
| 1261 | intel_ring_advance(ring); |
| 1262 | } |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1263 | |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1264 | return 0; |
| 1265 | } |
| 1266 | |
| 1267 | static int |
| 1268 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1269 | u32 offset, u32 len, |
| 1270 | unsigned flags) |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1271 | { |
| 1272 | int ret; |
| 1273 | |
| 1274 | ret = intel_ring_begin(ring, 2); |
| 1275 | if (ret) |
| 1276 | return ret; |
| 1277 | |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 1278 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1279 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1280 | intel_ring_advance(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1281 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1282 | return 0; |
| 1283 | } |
| 1284 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1285 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1286 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1287 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1288 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1289 | obj = ring->status_page.obj; |
| 1290 | if (obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1291 | return; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1292 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1293 | kunmap(sg_page(obj->pages->sgl)); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 1294 | i915_gem_object_ggtt_unpin(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1295 | drm_gem_object_unreference(&obj->base); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1296 | ring->status_page.obj = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1297 | } |
| 1298 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1299 | static int init_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1300 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1301 | struct drm_device *dev = ring->dev; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1302 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1303 | int ret; |
| 1304 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1305 | obj = i915_gem_alloc_object(dev, 4096); |
| 1306 | if (obj == NULL) { |
| 1307 | DRM_ERROR("Failed to allocate status page\n"); |
| 1308 | ret = -ENOMEM; |
| 1309 | goto err; |
| 1310 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 1311 | |
Daniel Vetter | e01f692 | 2014-02-14 14:01:16 +0100 | [diff] [blame] | 1312 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
| 1313 | if (ret) |
| 1314 | goto err_unref; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1315 | |
Daniel Vetter | 9a6bbb6 | 2014-02-14 14:01:15 +0100 | [diff] [blame] | 1316 | ret = i915_gem_obj_ggtt_pin(obj, 4096, 0); |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 1317 | if (ret) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1318 | goto err_unref; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1319 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1320 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1321 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1322 | if (ring->status_page.page_addr == NULL) { |
Ben Widawsky | 2e6c21e | 2012-07-12 23:16:12 -0700 | [diff] [blame] | 1323 | ret = -ENOMEM; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1324 | goto err_unpin; |
| 1325 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1326 | ring->status_page.obj = obj; |
| 1327 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1328 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1329 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
| 1330 | ring->name, ring->status_page.gfx_addr); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1331 | |
| 1332 | return 0; |
| 1333 | |
| 1334 | err_unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 1335 | i915_gem_object_ggtt_unpin(obj); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1336 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1337 | drm_gem_object_unreference(&obj->base); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1338 | err: |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1339 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1340 | } |
| 1341 | |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 1342 | static int init_phys_status_page(struct intel_ring_buffer *ring) |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1343 | { |
| 1344 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1345 | |
| 1346 | if (!dev_priv->status_page_dmah) { |
| 1347 | dev_priv->status_page_dmah = |
| 1348 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); |
| 1349 | if (!dev_priv->status_page_dmah) |
| 1350 | return -ENOMEM; |
| 1351 | } |
| 1352 | |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1353 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 1354 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
| 1355 | |
| 1356 | return 0; |
| 1357 | } |
| 1358 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 1359 | static int intel_init_ring_buffer(struct drm_device *dev, |
| 1360 | struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1361 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1362 | struct drm_i915_gem_object *obj; |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1363 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1364 | int ret; |
| 1365 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1366 | ring->dev = dev; |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1367 | INIT_LIST_HEAD(&ring->active_list); |
| 1368 | INIT_LIST_HEAD(&ring->request_list); |
Daniel Vetter | dfc9ef2 | 2012-04-11 22:12:47 +0200 | [diff] [blame] | 1369 | ring->size = 32 * PAGE_SIZE; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1370 | memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno)); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 1371 | |
Chris Wilson | b259f67 | 2011-03-29 13:19:09 +0100 | [diff] [blame] | 1372 | init_waitqueue_head(&ring->irq_queue); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1373 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1374 | if (I915_NEED_GFX_HWS(dev)) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1375 | ret = init_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1376 | if (ret) |
| 1377 | return ret; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1378 | } else { |
| 1379 | BUG_ON(ring->id != RCS); |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 1380 | ret = init_phys_status_page(ring); |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1381 | if (ret) |
| 1382 | return ret; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1383 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1384 | |
Chris Wilson | ebc052e | 2012-11-15 11:32:28 +0000 | [diff] [blame] | 1385 | obj = NULL; |
| 1386 | if (!HAS_LLC(dev)) |
| 1387 | obj = i915_gem_object_create_stolen(dev, ring->size); |
| 1388 | if (obj == NULL) |
| 1389 | obj = i915_gem_alloc_object(dev, ring->size); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1390 | if (obj == NULL) { |
| 1391 | DRM_ERROR("Failed to allocate ringbuffer\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1392 | ret = -ENOMEM; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1393 | goto err_hws; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1394 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1395 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1396 | ring->obj = obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1397 | |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 1398 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1399 | if (ret) |
| 1400 | goto err_unref; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1401 | |
Chris Wilson | 3eef891 | 2012-06-04 17:05:40 +0100 | [diff] [blame] | 1402 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 1403 | if (ret) |
| 1404 | goto err_unpin; |
| 1405 | |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1406 | ring->virtual_start = |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1407 | ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj), |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1408 | ring->size); |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1409 | if (ring->virtual_start == NULL) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1410 | DRM_ERROR("Failed to map ringbuffer.\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1411 | ret = -EINVAL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1412 | goto err_unpin; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1413 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1414 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1415 | ret = ring->init(ring); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1416 | if (ret) |
| 1417 | goto err_unmap; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1418 | |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1419 | /* Workaround an erratum on the i830 which causes a hang if |
| 1420 | * the TAIL pointer points to within the last 2 cachelines |
| 1421 | * of the buffer. |
| 1422 | */ |
| 1423 | ring->effective_size = ring->size; |
Chris Wilson | 27c1cbd | 2012-04-09 13:59:46 +0100 | [diff] [blame] | 1424 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1425 | ring->effective_size -= 128; |
| 1426 | |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 1427 | i915_cmd_parser_init_ring(ring); |
| 1428 | |
Chris Wilson | c584fe4 | 2010-10-29 18:15:52 +0100 | [diff] [blame] | 1429 | return 0; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1430 | |
| 1431 | err_unmap: |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1432 | iounmap(ring->virtual_start); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1433 | err_unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 1434 | i915_gem_object_ggtt_unpin(obj); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1435 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1436 | drm_gem_object_unreference(&obj->base); |
| 1437 | ring->obj = NULL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1438 | err_hws: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1439 | cleanup_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1440 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1441 | } |
| 1442 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1443 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1444 | { |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1445 | struct drm_i915_private *dev_priv; |
| 1446 | int ret; |
| 1447 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1448 | if (ring->obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1449 | return; |
| 1450 | |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1451 | /* Disable the ring buffer. The ring must be idle at this point */ |
| 1452 | dev_priv = ring->dev->dev_private; |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1453 | ret = intel_ring_idle(ring); |
Ben Widawsky | 3d57e5b | 2013-10-14 10:01:36 -0700 | [diff] [blame] | 1454 | if (ret && !i915_reset_in_progress(&dev_priv->gpu_error)) |
Chris Wilson | 29ee399 | 2011-01-24 16:35:42 +0000 | [diff] [blame] | 1455 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
| 1456 | ring->name, ret); |
| 1457 | |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1458 | I915_WRITE_CTL(ring, 0); |
| 1459 | |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1460 | iounmap(ring->virtual_start); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1461 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 1462 | i915_gem_object_ggtt_unpin(ring->obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1463 | drm_gem_object_unreference(&ring->obj->base); |
| 1464 | ring->obj = NULL; |
Ben Widawsky | 3d57e5b | 2013-10-14 10:01:36 -0700 | [diff] [blame] | 1465 | ring->preallocated_lazy_request = NULL; |
| 1466 | ring->outstanding_lazy_seqno = 0; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1467 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1468 | if (ring->cleanup) |
| 1469 | ring->cleanup(ring); |
| 1470 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1471 | cleanup_status_page(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1472 | } |
| 1473 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1474 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) |
| 1475 | { |
| 1476 | struct drm_i915_gem_request *request; |
Chris Wilson | 1f70999 | 2014-01-27 22:43:07 +0000 | [diff] [blame] | 1477 | u32 seqno = 0, tail; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1478 | int ret; |
| 1479 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1480 | if (ring->last_retired_head != -1) { |
| 1481 | ring->head = ring->last_retired_head; |
| 1482 | ring->last_retired_head = -1; |
Chris Wilson | 1f70999 | 2014-01-27 22:43:07 +0000 | [diff] [blame] | 1483 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1484 | ring->space = ring_space(ring); |
| 1485 | if (ring->space >= n) |
| 1486 | return 0; |
| 1487 | } |
| 1488 | |
| 1489 | list_for_each_entry(request, &ring->request_list, list) { |
| 1490 | int space; |
| 1491 | |
| 1492 | if (request->tail == -1) |
| 1493 | continue; |
| 1494 | |
Ville Syrjälä | 633cf8f | 2012-12-03 18:43:32 +0200 | [diff] [blame] | 1495 | space = request->tail - (ring->tail + I915_RING_FREE_SPACE); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1496 | if (space < 0) |
| 1497 | space += ring->size; |
| 1498 | if (space >= n) { |
| 1499 | seqno = request->seqno; |
Chris Wilson | 1f70999 | 2014-01-27 22:43:07 +0000 | [diff] [blame] | 1500 | tail = request->tail; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1501 | break; |
| 1502 | } |
| 1503 | |
| 1504 | /* Consume this request in case we need more space than |
| 1505 | * is available and so need to prevent a race between |
| 1506 | * updating last_retired_head and direct reads of |
| 1507 | * I915_RING_HEAD. It also provides a nice sanity check. |
| 1508 | */ |
| 1509 | request->tail = -1; |
| 1510 | } |
| 1511 | |
| 1512 | if (seqno == 0) |
| 1513 | return -ENOSPC; |
| 1514 | |
Chris Wilson | 1f70999 | 2014-01-27 22:43:07 +0000 | [diff] [blame] | 1515 | ret = i915_wait_seqno(ring, seqno); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1516 | if (ret) |
| 1517 | return ret; |
| 1518 | |
Chris Wilson | 1f70999 | 2014-01-27 22:43:07 +0000 | [diff] [blame] | 1519 | ring->head = tail; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1520 | ring->space = ring_space(ring); |
| 1521 | if (WARN_ON(ring->space < n)) |
| 1522 | return -ENOSPC; |
| 1523 | |
| 1524 | return 0; |
| 1525 | } |
| 1526 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1527 | static int ring_wait_for_space(struct intel_ring_buffer *ring, int n) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1528 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1529 | struct drm_device *dev = ring->dev; |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1530 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1531 | unsigned long end; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1532 | int ret; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1533 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1534 | ret = intel_ring_wait_request(ring, n); |
| 1535 | if (ret != -ENOSPC) |
| 1536 | return ret; |
| 1537 | |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 1538 | /* force the tail write in case we have been skipping them */ |
| 1539 | __intel_ring_advance(ring); |
| 1540 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1541 | trace_i915_ring_wait_begin(ring); |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 1542 | /* With GEM the hangcheck timer should kick us out of the loop, |
| 1543 | * leaving it early runs the risk of corrupting GEM state (due |
| 1544 | * to running on almost untested codepaths). But on resume |
| 1545 | * timers don't work yet, so prevent a complete hang in that |
| 1546 | * case by choosing an insanely large timeout. */ |
| 1547 | end = jiffies + 60 * HZ; |
Daniel Vetter | e6bfaf8 | 2011-12-14 13:56:59 +0100 | [diff] [blame] | 1548 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1549 | do { |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1550 | ring->head = I915_READ_HEAD(ring); |
| 1551 | ring->space = ring_space(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1552 | if (ring->space >= n) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1553 | trace_i915_ring_wait_end(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1554 | return 0; |
| 1555 | } |
| 1556 | |
Daniel Vetter | fb19e2a | 2014-02-12 23:44:34 +0100 | [diff] [blame] | 1557 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && |
| 1558 | dev->primary->master) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1559 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
| 1560 | if (master_priv->sarea_priv) |
| 1561 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
| 1562 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1563 | |
Chris Wilson | e60a0b1 | 2010-10-13 10:09:14 +0100 | [diff] [blame] | 1564 | msleep(1); |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 1565 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1566 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 1567 | dev_priv->mm.interruptible); |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 1568 | if (ret) |
| 1569 | return ret; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1570 | } while (!time_after(jiffies, end)); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1571 | trace_i915_ring_wait_end(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1572 | return -EBUSY; |
| 1573 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1574 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1575 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
| 1576 | { |
| 1577 | uint32_t __iomem *virt; |
| 1578 | int rem = ring->size - ring->tail; |
| 1579 | |
| 1580 | if (ring->space < rem) { |
| 1581 | int ret = ring_wait_for_space(ring, rem); |
| 1582 | if (ret) |
| 1583 | return ret; |
| 1584 | } |
| 1585 | |
| 1586 | virt = ring->virtual_start + ring->tail; |
| 1587 | rem /= 4; |
| 1588 | while (rem--) |
| 1589 | iowrite32(MI_NOOP, virt++); |
| 1590 | |
| 1591 | ring->tail = 0; |
| 1592 | ring->space = ring_space(ring); |
| 1593 | |
| 1594 | return 0; |
| 1595 | } |
| 1596 | |
| 1597 | int intel_ring_idle(struct intel_ring_buffer *ring) |
| 1598 | { |
| 1599 | u32 seqno; |
| 1600 | int ret; |
| 1601 | |
| 1602 | /* We need to add any requests required to flush the objects and ring */ |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1603 | if (ring->outstanding_lazy_seqno) { |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 1604 | ret = i915_add_request(ring, NULL); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1605 | if (ret) |
| 1606 | return ret; |
| 1607 | } |
| 1608 | |
| 1609 | /* Wait upon the last request to be completed */ |
| 1610 | if (list_empty(&ring->request_list)) |
| 1611 | return 0; |
| 1612 | |
| 1613 | seqno = list_entry(ring->request_list.prev, |
| 1614 | struct drm_i915_gem_request, |
| 1615 | list)->seqno; |
| 1616 | |
| 1617 | return i915_wait_seqno(ring, seqno); |
| 1618 | } |
| 1619 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1620 | static int |
| 1621 | intel_ring_alloc_seqno(struct intel_ring_buffer *ring) |
| 1622 | { |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1623 | if (ring->outstanding_lazy_seqno) |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1624 | return 0; |
| 1625 | |
Chris Wilson | 3c0e234 | 2013-09-04 10:45:52 +0100 | [diff] [blame] | 1626 | if (ring->preallocated_lazy_request == NULL) { |
| 1627 | struct drm_i915_gem_request *request; |
| 1628 | |
| 1629 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
| 1630 | if (request == NULL) |
| 1631 | return -ENOMEM; |
| 1632 | |
| 1633 | ring->preallocated_lazy_request = request; |
| 1634 | } |
| 1635 | |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1636 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1637 | } |
| 1638 | |
Chris Wilson | 304d695 | 2014-01-02 14:32:35 +0000 | [diff] [blame] | 1639 | static int __intel_ring_prepare(struct intel_ring_buffer *ring, |
| 1640 | int bytes) |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 1641 | { |
| 1642 | int ret; |
| 1643 | |
| 1644 | if (unlikely(ring->tail + bytes > ring->effective_size)) { |
| 1645 | ret = intel_wrap_ring_buffer(ring); |
| 1646 | if (unlikely(ret)) |
| 1647 | return ret; |
| 1648 | } |
| 1649 | |
| 1650 | if (unlikely(ring->space < bytes)) { |
| 1651 | ret = ring_wait_for_space(ring, bytes); |
| 1652 | if (unlikely(ret)) |
| 1653 | return ret; |
| 1654 | } |
| 1655 | |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 1656 | return 0; |
| 1657 | } |
| 1658 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1659 | int intel_ring_begin(struct intel_ring_buffer *ring, |
| 1660 | int num_dwords) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1661 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1662 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1663 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1664 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1665 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 1666 | dev_priv->mm.interruptible); |
Daniel Vetter | de2b998 | 2012-07-04 22:52:50 +0200 | [diff] [blame] | 1667 | if (ret) |
| 1668 | return ret; |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 1669 | |
Chris Wilson | 304d695 | 2014-01-02 14:32:35 +0000 | [diff] [blame] | 1670 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
| 1671 | if (ret) |
| 1672 | return ret; |
| 1673 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1674 | /* Preallocate the olr before touching the ring */ |
| 1675 | ret = intel_ring_alloc_seqno(ring); |
| 1676 | if (ret) |
| 1677 | return ret; |
| 1678 | |
Chris Wilson | 304d695 | 2014-01-02 14:32:35 +0000 | [diff] [blame] | 1679 | ring->space -= num_dwords * sizeof(uint32_t); |
| 1680 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1681 | } |
| 1682 | |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 1683 | /* Align the ring tail to a cacheline boundary */ |
| 1684 | int intel_ring_cacheline_align(struct intel_ring_buffer *ring) |
| 1685 | { |
| 1686 | int num_dwords = (64 - (ring->tail & 63)) / sizeof(uint32_t); |
| 1687 | int ret; |
| 1688 | |
| 1689 | if (num_dwords == 0) |
| 1690 | return 0; |
| 1691 | |
| 1692 | ret = intel_ring_begin(ring, num_dwords); |
| 1693 | if (ret) |
| 1694 | return ret; |
| 1695 | |
| 1696 | while (num_dwords--) |
| 1697 | intel_ring_emit(ring, MI_NOOP); |
| 1698 | |
| 1699 | intel_ring_advance(ring); |
| 1700 | |
| 1701 | return 0; |
| 1702 | } |
| 1703 | |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 1704 | void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno) |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 1705 | { |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 1706 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 1707 | |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1708 | BUG_ON(ring->outstanding_lazy_seqno); |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 1709 | |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 1710 | if (INTEL_INFO(ring->dev)->gen >= 6) { |
| 1711 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); |
| 1712 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); |
Ben Widawsky | 5020150 | 2013-08-12 16:53:03 -0700 | [diff] [blame] | 1713 | if (HAS_VEBOX(ring->dev)) |
| 1714 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1715 | } |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 1716 | |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 1717 | ring->set_seqno(ring, seqno); |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 1718 | ring->hangcheck.seqno = seqno; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1719 | } |
| 1720 | |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1721 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
| 1722 | u32 value) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1723 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1724 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1725 | |
| 1726 | /* Every tail move must follow the sequence below */ |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1727 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1728 | /* Disable notification that the ring is IDLE. The GT |
| 1729 | * will then assume that it is busy and bring it out of rc6. |
| 1730 | */ |
| 1731 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 1732 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
| 1733 | |
| 1734 | /* Clear the context id. Here be magic! */ |
| 1735 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); |
| 1736 | |
| 1737 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1738 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1739 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
| 1740 | 50)) |
| 1741 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1742 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1743 | /* Now that the ring is fully powered up, update the tail */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1744 | I915_WRITE_TAIL(ring, value); |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1745 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
| 1746 | |
| 1747 | /* Let the ring send IDLE messages to the GT again, |
| 1748 | * and so let it sleep to conserve power when idle. |
| 1749 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1750 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1751 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1752 | } |
| 1753 | |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 1754 | static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring, |
| 1755 | u32 invalidate, u32 flush) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1756 | { |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1757 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1758 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1759 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1760 | ret = intel_ring_begin(ring, 4); |
| 1761 | if (ret) |
| 1762 | return ret; |
| 1763 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1764 | cmd = MI_FLUSH_DW; |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 1765 | if (INTEL_INFO(ring->dev)->gen >= 8) |
| 1766 | cmd += 1; |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1767 | /* |
| 1768 | * Bspec vol 1c.5 - video engine command streamer: |
| 1769 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 1770 | * operation is complete. This bit is only valid when the |
| 1771 | * Post-Sync Operation field is a value of 1h or 3h." |
| 1772 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1773 | if (invalidate & I915_GEM_GPU_DOMAINS) |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1774 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
| 1775 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1776 | intel_ring_emit(ring, cmd); |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1777 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 1778 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
| 1779 | intel_ring_emit(ring, 0); /* upper addr */ |
| 1780 | intel_ring_emit(ring, 0); /* value */ |
| 1781 | } else { |
| 1782 | intel_ring_emit(ring, 0); |
| 1783 | intel_ring_emit(ring, MI_NOOP); |
| 1784 | } |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1785 | intel_ring_advance(ring); |
| 1786 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1787 | } |
| 1788 | |
| 1789 | static int |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 1790 | gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1791 | u32 offset, u32 len, |
| 1792 | unsigned flags) |
| 1793 | { |
Ben Widawsky | 28cf541 | 2013-11-02 21:07:26 -0700 | [diff] [blame] | 1794 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 1795 | bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL && |
| 1796 | !(flags & I915_DISPATCH_SECURE); |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 1797 | int ret; |
| 1798 | |
| 1799 | ret = intel_ring_begin(ring, 4); |
| 1800 | if (ret) |
| 1801 | return ret; |
| 1802 | |
| 1803 | /* FIXME(BDW): Address space and security selectors. */ |
Ben Widawsky | 28cf541 | 2013-11-02 21:07:26 -0700 | [diff] [blame] | 1804 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 1805 | intel_ring_emit(ring, offset); |
| 1806 | intel_ring_emit(ring, 0); |
| 1807 | intel_ring_emit(ring, MI_NOOP); |
| 1808 | intel_ring_advance(ring); |
| 1809 | |
| 1810 | return 0; |
| 1811 | } |
| 1812 | |
| 1813 | static int |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1814 | hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1815 | u32 offset, u32 len, |
| 1816 | unsigned flags) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1817 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1818 | int ret; |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1819 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1820 | ret = intel_ring_begin(ring, 2); |
| 1821 | if (ret) |
| 1822 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1823 | |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1824 | intel_ring_emit(ring, |
| 1825 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | |
| 1826 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); |
| 1827 | /* bit0-7 is the length on GEN6+ */ |
| 1828 | intel_ring_emit(ring, offset); |
| 1829 | intel_ring_advance(ring); |
| 1830 | |
| 1831 | return 0; |
| 1832 | } |
| 1833 | |
| 1834 | static int |
| 1835 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1836 | u32 offset, u32 len, |
| 1837 | unsigned flags) |
| 1838 | { |
| 1839 | int ret; |
| 1840 | |
| 1841 | ret = intel_ring_begin(ring, 2); |
| 1842 | if (ret) |
| 1843 | return ret; |
| 1844 | |
| 1845 | intel_ring_emit(ring, |
| 1846 | MI_BATCH_BUFFER_START | |
| 1847 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1848 | /* bit0-7 is the length on GEN6+ */ |
| 1849 | intel_ring_emit(ring, offset); |
| 1850 | intel_ring_advance(ring); |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1851 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1852 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1853 | } |
| 1854 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1855 | /* Blitter support (SandyBridge+) */ |
| 1856 | |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 1857 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
| 1858 | u32 invalidate, u32 flush) |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1859 | { |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 1860 | struct drm_device *dev = ring->dev; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1861 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1862 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1863 | |
Daniel Vetter | 6a233c7 | 2011-12-14 13:57:07 +0100 | [diff] [blame] | 1864 | ret = intel_ring_begin(ring, 4); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1865 | if (ret) |
| 1866 | return ret; |
| 1867 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1868 | cmd = MI_FLUSH_DW; |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 1869 | if (INTEL_INFO(ring->dev)->gen >= 8) |
| 1870 | cmd += 1; |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1871 | /* |
| 1872 | * Bspec vol 1c.3 - blitter engine command streamer: |
| 1873 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 1874 | * operation is complete. This bit is only valid when the |
| 1875 | * Post-Sync Operation field is a value of 1h or 3h." |
| 1876 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1877 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1878 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
Daniel Vetter | b3fcabb | 2012-11-04 12:24:47 +0100 | [diff] [blame] | 1879 | MI_FLUSH_DW_OP_STOREDW; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1880 | intel_ring_emit(ring, cmd); |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1881 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 1882 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
| 1883 | intel_ring_emit(ring, 0); /* upper addr */ |
| 1884 | intel_ring_emit(ring, 0); /* value */ |
| 1885 | } else { |
| 1886 | intel_ring_emit(ring, 0); |
| 1887 | intel_ring_emit(ring, MI_NOOP); |
| 1888 | } |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1889 | intel_ring_advance(ring); |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 1890 | |
Ville Syrjälä | 9688eca | 2013-11-06 23:02:19 +0200 | [diff] [blame] | 1891 | if (IS_GEN7(dev) && !invalidate && flush) |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 1892 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); |
| 1893 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1894 | return 0; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1895 | } |
| 1896 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1897 | int intel_init_render_ring_buffer(struct drm_device *dev) |
| 1898 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1899 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1900 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1901 | |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1902 | ring->name = "render ring"; |
| 1903 | ring->id = RCS; |
| 1904 | ring->mmio_base = RENDER_RING_BASE; |
| 1905 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1906 | if (INTEL_INFO(dev)->gen >= 6) { |
| 1907 | ring->add_request = gen6_add_request; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 1908 | ring->flush = gen7_render_ring_flush; |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 1909 | if (INTEL_INFO(dev)->gen == 6) |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 1910 | ring->flush = gen6_render_ring_flush; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1911 | if (INTEL_INFO(dev)->gen >= 8) { |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 1912 | ring->flush = gen8_render_ring_flush; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1913 | ring->irq_get = gen8_ring_get_irq; |
| 1914 | ring->irq_put = gen8_ring_put_irq; |
| 1915 | } else { |
| 1916 | ring->irq_get = gen6_ring_get_irq; |
| 1917 | ring->irq_put = gen6_ring_put_irq; |
| 1918 | } |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1919 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1920 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1921 | ring->set_seqno = ring_set_seqno; |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1922 | ring->sync_to = gen6_ring_sync; |
Ben Widawsky | 5586181 | 2013-05-28 19:22:17 -0700 | [diff] [blame] | 1923 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 1924 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV; |
| 1925 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB; |
Ben Widawsky | 1950de1 | 2013-05-28 19:22:20 -0700 | [diff] [blame] | 1926 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE; |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 1927 | ring->signal_mbox[RCS] = GEN6_NOSYNC; |
| 1928 | ring->signal_mbox[VCS] = GEN6_VRSYNC; |
| 1929 | ring->signal_mbox[BCS] = GEN6_BRSYNC; |
Ben Widawsky | 1950de1 | 2013-05-28 19:22:20 -0700 | [diff] [blame] | 1930 | ring->signal_mbox[VECS] = GEN6_VERSYNC; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1931 | } else if (IS_GEN5(dev)) { |
| 1932 | ring->add_request = pc_render_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 1933 | ring->flush = gen4_render_ring_flush; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1934 | ring->get_seqno = pc_render_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1935 | ring->set_seqno = pc_render_set_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1936 | ring->irq_get = gen5_ring_get_irq; |
| 1937 | ring->irq_put = gen5_ring_put_irq; |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1938 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
| 1939 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1940 | } else { |
Daniel Vetter | 8620a3a | 2012-04-11 22:12:57 +0200 | [diff] [blame] | 1941 | ring->add_request = i9xx_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 1942 | if (INTEL_INFO(dev)->gen < 4) |
| 1943 | ring->flush = gen2_render_ring_flush; |
| 1944 | else |
| 1945 | ring->flush = gen4_render_ring_flush; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1946 | ring->get_seqno = ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1947 | ring->set_seqno = ring_set_seqno; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1948 | if (IS_GEN2(dev)) { |
| 1949 | ring->irq_get = i8xx_ring_get_irq; |
| 1950 | ring->irq_put = i8xx_ring_put_irq; |
| 1951 | } else { |
| 1952 | ring->irq_get = i9xx_ring_get_irq; |
| 1953 | ring->irq_put = i9xx_ring_put_irq; |
| 1954 | } |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1955 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1956 | } |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1957 | ring->write_tail = ring_write_tail; |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1958 | if (IS_HASWELL(dev)) |
| 1959 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 1960 | else if (IS_GEN8(dev)) |
| 1961 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1962 | else if (INTEL_INFO(dev)->gen >= 6) |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1963 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
| 1964 | else if (INTEL_INFO(dev)->gen >= 4) |
| 1965 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
| 1966 | else if (IS_I830(dev) || IS_845G(dev)) |
| 1967 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
| 1968 | else |
| 1969 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1970 | ring->init = init_render_ring; |
| 1971 | ring->cleanup = render_ring_cleanup; |
| 1972 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1973 | /* Workaround batchbuffer to combat CS tlb bug. */ |
| 1974 | if (HAS_BROKEN_CS_TLB(dev)) { |
| 1975 | struct drm_i915_gem_object *obj; |
| 1976 | int ret; |
| 1977 | |
| 1978 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); |
| 1979 | if (obj == NULL) { |
| 1980 | DRM_ERROR("Failed to allocate batch bo\n"); |
| 1981 | return -ENOMEM; |
| 1982 | } |
| 1983 | |
Daniel Vetter | be1fa12 | 2014-02-14 14:01:14 +0100 | [diff] [blame] | 1984 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1985 | if (ret != 0) { |
| 1986 | drm_gem_object_unreference(&obj->base); |
| 1987 | DRM_ERROR("Failed to ping batch bo\n"); |
| 1988 | return ret; |
| 1989 | } |
| 1990 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 1991 | ring->scratch.obj = obj; |
| 1992 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1993 | } |
| 1994 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1995 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1996 | } |
| 1997 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1998 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
| 1999 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2000 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2001 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2002 | int ret; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2003 | |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2004 | ring->name = "render ring"; |
| 2005 | ring->id = RCS; |
| 2006 | ring->mmio_base = RENDER_RING_BASE; |
| 2007 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2008 | if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | b4178f8 | 2012-04-11 22:12:51 +0200 | [diff] [blame] | 2009 | /* non-kms not supported on gen6+ */ |
| 2010 | return -ENODEV; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2011 | } |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 2012 | |
| 2013 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding |
| 2014 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up |
| 2015 | * the special gen5 functions. */ |
| 2016 | ring->add_request = i9xx_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 2017 | if (INTEL_INFO(dev)->gen < 4) |
| 2018 | ring->flush = gen2_render_ring_flush; |
| 2019 | else |
| 2020 | ring->flush = gen4_render_ring_flush; |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 2021 | ring->get_seqno = ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2022 | ring->set_seqno = ring_set_seqno; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2023 | if (IS_GEN2(dev)) { |
| 2024 | ring->irq_get = i8xx_ring_get_irq; |
| 2025 | ring->irq_put = i8xx_ring_put_irq; |
| 2026 | } else { |
| 2027 | ring->irq_get = i9xx_ring_get_irq; |
| 2028 | ring->irq_put = i9xx_ring_put_irq; |
| 2029 | } |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 2030 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2031 | ring->write_tail = ring_write_tail; |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 2032 | if (INTEL_INFO(dev)->gen >= 4) |
| 2033 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
| 2034 | else if (IS_I830(dev) || IS_845G(dev)) |
| 2035 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
| 2036 | else |
| 2037 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2038 | ring->init = init_render_ring; |
| 2039 | ring->cleanup = render_ring_cleanup; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2040 | |
| 2041 | ring->dev = dev; |
| 2042 | INIT_LIST_HEAD(&ring->active_list); |
| 2043 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2044 | |
| 2045 | ring->size = size; |
| 2046 | ring->effective_size = ring->size; |
Mika Kuoppala | 17f10fd | 2012-10-29 16:59:26 +0200 | [diff] [blame] | 2047 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2048 | ring->effective_size -= 128; |
| 2049 | |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 2050 | ring->virtual_start = ioremap_wc(start, size); |
| 2051 | if (ring->virtual_start == NULL) { |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2052 | DRM_ERROR("can not ioremap virtual address for" |
| 2053 | " ring buffer\n"); |
| 2054 | return -ENOMEM; |
| 2055 | } |
| 2056 | |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2057 | if (!I915_NEED_GFX_HWS(dev)) { |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 2058 | ret = init_phys_status_page(ring); |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2059 | if (ret) |
| 2060 | return ret; |
| 2061 | } |
| 2062 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2063 | return 0; |
| 2064 | } |
| 2065 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2066 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
| 2067 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2068 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2069 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2070 | |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2071 | ring->name = "bsd ring"; |
| 2072 | ring->id = VCS; |
| 2073 | |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 2074 | ring->write_tail = ring_write_tail; |
Ben Widawsky | 780f18c | 2013-11-02 21:07:28 -0700 | [diff] [blame] | 2075 | if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2076 | ring->mmio_base = GEN6_BSD_RING_BASE; |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 2077 | /* gen6 bsd needs a special wa for tail updates */ |
| 2078 | if (IS_GEN6(dev)) |
| 2079 | ring->write_tail = gen6_bsd_ring_write_tail; |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2080 | ring->flush = gen6_bsd_ring_flush; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2081 | ring->add_request = gen6_add_request; |
| 2082 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2083 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2084 | if (INTEL_INFO(dev)->gen >= 8) { |
| 2085 | ring->irq_enable_mask = |
| 2086 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
| 2087 | ring->irq_get = gen8_ring_get_irq; |
| 2088 | ring->irq_put = gen8_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2089 | ring->dispatch_execbuffer = |
| 2090 | gen8_ring_dispatch_execbuffer; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2091 | } else { |
| 2092 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
| 2093 | ring->irq_get = gen6_ring_get_irq; |
| 2094 | ring->irq_put = gen6_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2095 | ring->dispatch_execbuffer = |
| 2096 | gen6_ring_dispatch_execbuffer; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2097 | } |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 2098 | ring->sync_to = gen6_ring_sync; |
Ben Widawsky | 5586181 | 2013-05-28 19:22:17 -0700 | [diff] [blame] | 2099 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR; |
| 2100 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2101 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB; |
Ben Widawsky | 1950de1 | 2013-05-28 19:22:20 -0700 | [diff] [blame] | 2102 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE; |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 2103 | ring->signal_mbox[RCS] = GEN6_RVSYNC; |
| 2104 | ring->signal_mbox[VCS] = GEN6_NOSYNC; |
| 2105 | ring->signal_mbox[BCS] = GEN6_BVSYNC; |
Ben Widawsky | 1950de1 | 2013-05-28 19:22:20 -0700 | [diff] [blame] | 2106 | ring->signal_mbox[VECS] = GEN6_VEVSYNC; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2107 | } else { |
| 2108 | ring->mmio_base = BSD_RING_BASE; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2109 | ring->flush = bsd_ring_flush; |
Daniel Vetter | 8620a3a | 2012-04-11 22:12:57 +0200 | [diff] [blame] | 2110 | ring->add_request = i9xx_add_request; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2111 | ring->get_seqno = ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2112 | ring->set_seqno = ring_set_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2113 | if (IS_GEN5(dev)) { |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 2114 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2115 | ring->irq_get = gen5_ring_get_irq; |
| 2116 | ring->irq_put = gen5_ring_put_irq; |
| 2117 | } else { |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 2118 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2119 | ring->irq_get = i9xx_ring_get_irq; |
| 2120 | ring->irq_put = i9xx_ring_put_irq; |
| 2121 | } |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 2122 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2123 | } |
| 2124 | ring->init = init_ring_common; |
| 2125 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2126 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2127 | } |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2128 | |
| 2129 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
| 2130 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2131 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2132 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2133 | |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 2134 | ring->name = "blitter ring"; |
| 2135 | ring->id = BCS; |
| 2136 | |
| 2137 | ring->mmio_base = BLT_RING_BASE; |
| 2138 | ring->write_tail = ring_write_tail; |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2139 | ring->flush = gen6_ring_flush; |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 2140 | ring->add_request = gen6_add_request; |
| 2141 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2142 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2143 | if (INTEL_INFO(dev)->gen >= 8) { |
| 2144 | ring->irq_enable_mask = |
| 2145 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
| 2146 | ring->irq_get = gen8_ring_get_irq; |
| 2147 | ring->irq_put = gen8_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2148 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2149 | } else { |
| 2150 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
| 2151 | ring->irq_get = gen6_ring_get_irq; |
| 2152 | ring->irq_put = gen6_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2153 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2154 | } |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 2155 | ring->sync_to = gen6_ring_sync; |
Ben Widawsky | 5586181 | 2013-05-28 19:22:17 -0700 | [diff] [blame] | 2156 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR; |
| 2157 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV; |
| 2158 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID; |
Ben Widawsky | 1950de1 | 2013-05-28 19:22:20 -0700 | [diff] [blame] | 2159 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE; |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 2160 | ring->signal_mbox[RCS] = GEN6_RBSYNC; |
| 2161 | ring->signal_mbox[VCS] = GEN6_VBSYNC; |
| 2162 | ring->signal_mbox[BCS] = GEN6_NOSYNC; |
Ben Widawsky | 1950de1 | 2013-05-28 19:22:20 -0700 | [diff] [blame] | 2163 | ring->signal_mbox[VECS] = GEN6_VEBSYNC; |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 2164 | ring->init = init_ring_common; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2165 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2166 | return intel_init_ring_buffer(dev, ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2167 | } |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2168 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 2169 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
| 2170 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2171 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 2172 | struct intel_ring_buffer *ring = &dev_priv->ring[VECS]; |
| 2173 | |
| 2174 | ring->name = "video enhancement ring"; |
| 2175 | ring->id = VECS; |
| 2176 | |
| 2177 | ring->mmio_base = VEBOX_RING_BASE; |
| 2178 | ring->write_tail = ring_write_tail; |
| 2179 | ring->flush = gen6_ring_flush; |
| 2180 | ring->add_request = gen6_add_request; |
| 2181 | ring->get_seqno = gen6_ring_get_seqno; |
| 2182 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2183 | |
| 2184 | if (INTEL_INFO(dev)->gen >= 8) { |
| 2185 | ring->irq_enable_mask = |
Daniel Vetter | 40c499f | 2013-11-07 21:40:39 -0800 | [diff] [blame] | 2186 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2187 | ring->irq_get = gen8_ring_get_irq; |
| 2188 | ring->irq_put = gen8_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2189 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2190 | } else { |
| 2191 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
| 2192 | ring->irq_get = hsw_vebox_get_irq; |
| 2193 | ring->irq_put = hsw_vebox_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2194 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2195 | } |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 2196 | ring->sync_to = gen6_ring_sync; |
| 2197 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER; |
| 2198 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV; |
| 2199 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB; |
| 2200 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2201 | ring->signal_mbox[RCS] = GEN6_RVESYNC; |
| 2202 | ring->signal_mbox[VCS] = GEN6_VVESYNC; |
| 2203 | ring->signal_mbox[BCS] = GEN6_BVESYNC; |
| 2204 | ring->signal_mbox[VECS] = GEN6_NOSYNC; |
| 2205 | ring->init = init_ring_common; |
| 2206 | |
| 2207 | return intel_init_ring_buffer(dev, ring); |
| 2208 | } |
| 2209 | |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2210 | int |
| 2211 | intel_ring_flush_all_caches(struct intel_ring_buffer *ring) |
| 2212 | { |
| 2213 | int ret; |
| 2214 | |
| 2215 | if (!ring->gpu_caches_dirty) |
| 2216 | return 0; |
| 2217 | |
| 2218 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 2219 | if (ret) |
| 2220 | return ret; |
| 2221 | |
| 2222 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 2223 | |
| 2224 | ring->gpu_caches_dirty = false; |
| 2225 | return 0; |
| 2226 | } |
| 2227 | |
| 2228 | int |
| 2229 | intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) |
| 2230 | { |
| 2231 | uint32_t flush_domains; |
| 2232 | int ret; |
| 2233 | |
| 2234 | flush_domains = 0; |
| 2235 | if (ring->gpu_caches_dirty) |
| 2236 | flush_domains = I915_GEM_GPU_DOMAINS; |
| 2237 | |
| 2238 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 2239 | if (ret) |
| 2240 | return ret; |
| 2241 | |
| 2242 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 2243 | |
| 2244 | ring->gpu_caches_dirty = false; |
| 2245 | return 0; |
| 2246 | } |