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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Jesse Barnes5669fca2009-02-17 15:13:31 -080030#include <linux/device.h>
David Howells760285e2012-10-02 18:01:07 +010031#include <drm/drmP.h>
32#include <drm/i915_drm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070033#include "i915_drv.h"
Chris Wilson990bbda2012-07-02 11:51:02 -030034#include "i915_trace.h"
Kenneth Graunkef49f0582010-09-11 01:19:14 -070035#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070036
Jesse Barnes79e53942008-11-07 14:24:08 -080037#include <linux/console.h>
Paul Gortmakere0cd3602011-08-30 11:04:30 -040038#include <linux/module.h>
Imre Deakd6102972014-05-07 19:57:49 +030039#include <linux/pm_runtime.h>
David Howells760285e2012-10-02 18:01:07 +010040#include <drm/drm_crtc_helper.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080041
Kristian Høgsberg112b7152009-01-04 16:55:33 -050042static struct drm_driver driver;
43
Antti Koskipaaa57c7742014-02-04 14:22:24 +020044#define GEN_DEFAULT_PIPEOFFSETS \
45 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
46 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
47 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
48 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
49 .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \
50 .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
51 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
52
Rafael Barbalho84fd4f42014-04-28 14:00:42 +030053#define GEN_CHV_PIPEOFFSETS \
54 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
55 CHV_PIPE_C_OFFSET }, \
56 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
57 CHV_TRANSCODER_C_OFFSET, }, \
58 .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET, \
59 CHV_DPLL_C_OFFSET }, \
60 .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, \
61 CHV_DPLL_C_MD_OFFSET }, \
62 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
63 CHV_PALETTE_C_OFFSET }
Antti Koskipaaa57c7742014-02-04 14:22:24 +020064
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030065#define CURSOR_OFFSETS \
66 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
67
68#define IVB_CURSOR_OFFSETS \
69 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
70
Tobias Klauser9a7e8492010-05-20 10:33:46 +020071static const struct intel_device_info intel_i830_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070072 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
Chris Wilson315781482010-08-12 09:42:51 +010073 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070074 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020075 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030076 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050077};
78
Tobias Klauser9a7e8492010-05-20 10:33:46 +020079static const struct intel_device_info intel_845g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070080 .gen = 2, .num_pipes = 1,
Chris Wilson315781482010-08-12 09:42:51 +010081 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070082 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020083 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030084 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050085};
86
Tobias Klauser9a7e8492010-05-20 10:33:46 +020087static const struct intel_device_info intel_i85x_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070088 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
Adam Jackson5ce8ba72010-04-15 14:03:30 -040089 .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +010090 .has_overlay = 1, .overlay_needs_physical = 1,
Ville Syrjäläfd70d522013-11-28 17:30:02 +020091 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070092 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020093 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030094 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050095};
96
Tobias Klauser9a7e8492010-05-20 10:33:46 +020097static const struct intel_device_info intel_i865g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070098 .gen = 2, .num_pipes = 1,
Chris Wilson315781482010-08-12 09:42:51 +010099 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700100 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200101 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300102 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500103};
104
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200105static const struct intel_device_info intel_i915g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700106 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
Chris Wilson315781482010-08-12 09:42:51 +0100107 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700108 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200109 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300110 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500111};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200112static const struct intel_device_info intel_i915gm_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700113 .gen = 3, .is_mobile = 1, .num_pipes = 2,
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -0500114 .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100115 .has_overlay = 1, .overlay_needs_physical = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100116 .supports_tv = 1,
Ville Syrjäläfd70d522013-11-28 17:30:02 +0200117 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700118 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200119 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300120 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500121};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200122static const struct intel_device_info intel_i945g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700123 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
Chris Wilson315781482010-08-12 09:42:51 +0100124 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700125 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200126 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300127 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500128};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200129static const struct intel_device_info intel_i945gm_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700130 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -0500131 .has_hotplug = 1, .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100132 .has_overlay = 1, .overlay_needs_physical = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100133 .supports_tv = 1,
Ville Syrjäläfd70d522013-11-28 17:30:02 +0200134 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700135 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200136 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300137 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500138};
139
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200140static const struct intel_device_info intel_i965g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700141 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100142 .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100143 .has_overlay = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700144 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200145 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300146 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500147};
148
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200149static const struct intel_device_info intel_i965gm_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700150 .gen = 4, .is_crestline = 1, .num_pipes = 2,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000151 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100152 .has_overlay = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100153 .supports_tv = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700154 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200155 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300156 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500157};
158
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200159static const struct intel_device_info intel_g33_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700160 .gen = 3, .is_g33 = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100161 .need_gfx_hws = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100162 .has_overlay = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700163 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200164 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300165 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500166};
167
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200168static const struct intel_device_info intel_g45_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700169 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100170 .has_pipe_cxsr = 1, .has_hotplug = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700171 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200172 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300173 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500174};
175
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200176static const struct intel_device_info intel_gm45_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700177 .gen = 4, .is_g4x = 1, .num_pipes = 2,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000178 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100179 .has_pipe_cxsr = 1, .has_hotplug = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100180 .supports_tv = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700181 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200182 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300183 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500184};
185
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200186static const struct intel_device_info intel_pineview_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700187 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100188 .need_gfx_hws = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100189 .has_overlay = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200190 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300191 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500192};
193
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200194static const struct intel_device_info intel_ironlake_d_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700195 .gen = 5, .num_pipes = 2,
Eugeni Dodonov5a117db2012-01-05 09:34:29 -0200196 .need_gfx_hws = 1, .has_hotplug = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700197 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200198 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300199 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500200};
201
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200202static const struct intel_device_info intel_ironlake_m_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700203 .gen = 5, .is_mobile = 1, .num_pipes = 2,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000204 .need_gfx_hws = 1, .has_hotplug = 1,
Jesse Barnesc1a9f042011-05-05 15:24:21 -0700205 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700206 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200207 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300208 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500209};
210
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200211static const struct intel_device_info intel_sandybridge_d_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700212 .gen = 6, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100213 .need_gfx_hws = 1, .has_hotplug = 1,
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200214 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700215 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200216 .has_llc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200217 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300218 CURSOR_OFFSETS,
Eric Anholtf6e450a2009-11-02 12:08:22 -0800219};
220
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200221static const struct intel_device_info intel_sandybridge_m_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700222 .gen = 6, .is_mobile = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100223 .need_gfx_hws = 1, .has_hotplug = 1,
Yuanhan Liu9c04f012010-12-15 15:42:32 +0800224 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700225 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200226 .has_llc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200227 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300228 CURSOR_OFFSETS,
Eric Anholta13e4092010-01-07 15:08:18 -0800229};
230
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700231#define GEN7_FEATURES \
232 .gen = 7, .num_pipes = 3, \
233 .need_gfx_hws = 1, .has_hotplug = 1, \
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200234 .has_fbc = 1, \
Ben Widawsky73ae4782013-10-15 10:02:57 -0700235 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
Ben Widawskyab484f82013-10-05 17:57:11 -0700236 .has_llc = 1
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700237
Jesse Barnesc76b6152011-04-28 14:32:07 -0700238static const struct intel_device_info intel_ivybridge_d_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700239 GEN7_FEATURES,
240 .is_ivybridge = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200241 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300242 IVB_CURSOR_OFFSETS,
Jesse Barnesc76b6152011-04-28 14:32:07 -0700243};
244
245static const struct intel_device_info intel_ivybridge_m_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700246 GEN7_FEATURES,
247 .is_ivybridge = 1,
248 .is_mobile = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200249 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300250 IVB_CURSOR_OFFSETS,
Jesse Barnesc76b6152011-04-28 14:32:07 -0700251};
252
Ben Widawsky999bcde2013-04-05 13:12:45 -0700253static const struct intel_device_info intel_ivybridge_q_info = {
254 GEN7_FEATURES,
255 .is_ivybridge = 1,
256 .num_pipes = 0, /* legal, last one wins */
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200257 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300258 IVB_CURSOR_OFFSETS,
Ben Widawsky999bcde2013-04-05 13:12:45 -0700259};
260
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700261static const struct intel_device_info intel_valleyview_m_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700262 GEN7_FEATURES,
263 .is_mobile = 1,
264 .num_pipes = 2,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700265 .is_valleyview = 1,
Ville Syrjäläfba5d532013-01-24 15:29:56 +0200266 .display_mmio_offset = VLV_DISPLAY_BASE,
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200267 .has_fbc = 0, /* legal, last one wins */
Ben Widawsky30ccd962013-04-15 21:48:03 -0700268 .has_llc = 0, /* legal, last one wins */
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200269 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300270 CURSOR_OFFSETS,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700271};
272
273static const struct intel_device_info intel_valleyview_d_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700274 GEN7_FEATURES,
275 .num_pipes = 2,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700276 .is_valleyview = 1,
Ville Syrjäläfba5d532013-01-24 15:29:56 +0200277 .display_mmio_offset = VLV_DISPLAY_BASE,
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200278 .has_fbc = 0, /* legal, last one wins */
Ben Widawsky30ccd962013-04-15 21:48:03 -0700279 .has_llc = 0, /* legal, last one wins */
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200280 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300281 CURSOR_OFFSETS,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700282};
283
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -0300284static const struct intel_device_info intel_haswell_d_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700285 GEN7_FEATURES,
286 .is_haswell = 1,
Damien Lespiaudd93be52013-04-22 18:40:39 +0100287 .has_ddi = 1,
Damien Lespiau30568c42013-04-22 18:40:41 +0100288 .has_fpga_dbg = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700289 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200290 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300291 IVB_CURSOR_OFFSETS,
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -0300292};
293
294static const struct intel_device_info intel_haswell_m_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700295 GEN7_FEATURES,
296 .is_haswell = 1,
297 .is_mobile = 1,
Damien Lespiaudd93be52013-04-22 18:40:39 +0100298 .has_ddi = 1,
Damien Lespiau30568c42013-04-22 18:40:41 +0100299 .has_fpga_dbg = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700300 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200301 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300302 IVB_CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500303};
304
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800305static const struct intel_device_info intel_broadwell_d_info = {
Damien Lespiau4b305532013-11-02 21:07:32 -0700306 .gen = 8, .num_pipes = 3,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800307 .need_gfx_hws = 1, .has_hotplug = 1,
308 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
309 .has_llc = 1,
310 .has_ddi = 1,
Ben Widawsky8f94d242014-02-20 16:01:20 -0800311 .has_fbc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200312 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300313 IVB_CURSOR_OFFSETS,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800314};
315
316static const struct intel_device_info intel_broadwell_m_info = {
Damien Lespiau4b305532013-11-02 21:07:32 -0700317 .gen = 8, .is_mobile = 1, .num_pipes = 3,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800318 .need_gfx_hws = 1, .has_hotplug = 1,
319 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
320 .has_llc = 1,
321 .has_ddi = 1,
Ben Widawsky8f94d242014-02-20 16:01:20 -0800322 .has_fbc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200323 GEN_DEFAULT_PIPEOFFSETS,
Rodrigo Vivi15d24aa2014-06-04 17:09:30 -0700324 IVB_CURSOR_OFFSETS,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800325};
326
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800327static const struct intel_device_info intel_broadwell_gt3d_info = {
328 .gen = 8, .num_pipes = 3,
329 .need_gfx_hws = 1, .has_hotplug = 1,
Zhao Yakui845f74a2014-04-17 10:37:37 +0800330 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800331 .has_llc = 1,
332 .has_ddi = 1,
333 .has_fbc = 1,
334 GEN_DEFAULT_PIPEOFFSETS,
Rodrigo Vivi15d24aa2014-06-04 17:09:30 -0700335 IVB_CURSOR_OFFSETS,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800336};
337
338static const struct intel_device_info intel_broadwell_gt3m_info = {
339 .gen = 8, .is_mobile = 1, .num_pipes = 3,
340 .need_gfx_hws = 1, .has_hotplug = 1,
Zhao Yakui845f74a2014-04-17 10:37:37 +0800341 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800342 .has_llc = 1,
343 .has_ddi = 1,
344 .has_fbc = 1,
345 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300346 IVB_CURSOR_OFFSETS,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800347};
348
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300349static const struct intel_device_info intel_cherryview_info = {
350 .is_preliminary = 1,
Ville Syrjälä07fddb12014-04-09 13:28:54 +0300351 .gen = 8, .num_pipes = 3,
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300352 .need_gfx_hws = 1, .has_hotplug = 1,
353 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
354 .is_valleyview = 1,
355 .display_mmio_offset = VLV_DISPLAY_BASE,
Rafael Barbalho84fd4f42014-04-28 14:00:42 +0300356 GEN_CHV_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300357 CURSOR_OFFSETS,
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300358};
359
Jesse Barnesa0a18072013-07-26 13:32:51 -0700360/*
361 * Make sure any device matches here are from most specific to most
362 * general. For example, since the Quanta match is based on the subsystem
363 * and subvendor IDs, we need it to come before the more general IVB
364 * PCI ID matches, otherwise we'll use the wrong info struct above.
365 */
366#define INTEL_PCI_IDS \
367 INTEL_I830_IDS(&intel_i830_info), \
368 INTEL_I845G_IDS(&intel_845g_info), \
369 INTEL_I85X_IDS(&intel_i85x_info), \
370 INTEL_I865G_IDS(&intel_i865g_info), \
371 INTEL_I915G_IDS(&intel_i915g_info), \
372 INTEL_I915GM_IDS(&intel_i915gm_info), \
373 INTEL_I945G_IDS(&intel_i945g_info), \
374 INTEL_I945GM_IDS(&intel_i945gm_info), \
375 INTEL_I965G_IDS(&intel_i965g_info), \
376 INTEL_G33_IDS(&intel_g33_info), \
377 INTEL_I965GM_IDS(&intel_i965gm_info), \
378 INTEL_GM45_IDS(&intel_gm45_info), \
379 INTEL_G45_IDS(&intel_g45_info), \
380 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
381 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
382 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
383 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
384 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
385 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
386 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
387 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
388 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
389 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
390 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800391 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800392 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
393 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
394 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300395 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
396 INTEL_CHV_IDS(&intel_cherryview_info)
Jesse Barnesa0a18072013-07-26 13:32:51 -0700397
Chris Wilson6103da02010-07-05 18:01:47 +0100398static const struct pci_device_id pciidlist[] = { /* aka */
Jesse Barnesa0a18072013-07-26 13:32:51 -0700399 INTEL_PCI_IDS,
Kristian Høgsberg49ae35f2009-12-16 15:16:15 -0500400 {0, 0, 0}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700401};
402
Jesse Barnes79e53942008-11-07 14:24:08 -0800403#if defined(CONFIG_DRM_I915_KMS)
404MODULE_DEVICE_TABLE(pci, pciidlist);
405#endif
406
Akshay Joshi0206e352011-08-16 15:34:10 -0400407void intel_detect_pch(struct drm_device *dev)
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800408{
409 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deakbcdb72a2014-02-14 20:23:54 +0200410 struct pci_dev *pch = NULL;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800411
Ben Widawskyce1bb322013-04-05 13:12:44 -0700412 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
413 * (which really amounts to a PCH but no South Display).
414 */
415 if (INTEL_INFO(dev)->num_pipes == 0) {
416 dev_priv->pch_type = PCH_NOP;
Ben Widawskyce1bb322013-04-05 13:12:44 -0700417 return;
418 }
419
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800420 /*
421 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
422 * make graphics device passthrough work easy for VMM, that only
423 * need to expose ISA bridge to let driver know the real hardware
424 * underneath. This is a requirement from virtualization team.
Rui Guo6a9c4b32013-06-19 21:10:23 +0800425 *
426 * In some virtualized environments (e.g. XEN), there is irrelevant
427 * ISA bridge in the system. To work reliably, we should scan trhough
428 * all the ISA bridge devices and check for the first match, instead
429 * of only checking the first one.
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800430 */
Imre Deakbcdb72a2014-02-14 20:23:54 +0200431 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800432 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
Imre Deakbcdb72a2014-02-14 20:23:54 +0200433 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
Paulo Zanoni17a303e2012-11-20 15:12:07 -0200434 dev_priv->pch_id = id;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800435
Jesse Barnes90711d52011-04-28 14:48:02 -0700436 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
437 dev_priv->pch_type = PCH_IBX;
438 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100439 WARN_ON(!IS_GEN5(dev));
Jesse Barnes90711d52011-04-28 14:48:02 -0700440 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800441 dev_priv->pch_type = PCH_CPT;
442 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100443 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
Jesse Barnesc7925132011-04-07 12:33:56 -0700444 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
445 /* PantherPoint is CPT compatible */
446 dev_priv->pch_type = PCH_CPT;
Jani Nikula492ab662013-10-01 12:12:33 +0300447 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100448 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300449 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
450 dev_priv->pch_type = PCH_LPT;
451 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100452 WARN_ON(!IS_HASWELL(dev));
Paulo Zanoni08e14132013-04-12 18:16:54 -0300453 WARN_ON(IS_ULT(dev));
Paulo Zanoni018f52c2013-11-02 21:07:35 -0700454 } else if (IS_BROADWELL(dev)) {
455 dev_priv->pch_type = PCH_LPT;
456 dev_priv->pch_id =
457 INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
458 DRM_DEBUG_KMS("This is Broadwell, assuming "
459 "LynxPoint LP PCH\n");
Ben Widawskye76e0632013-11-07 21:40:41 -0800460 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
461 dev_priv->pch_type = PCH_LPT;
462 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
463 WARN_ON(!IS_HASWELL(dev));
464 WARN_ON(!IS_ULT(dev));
Imre Deakbcdb72a2014-02-14 20:23:54 +0200465 } else
466 continue;
467
Rui Guo6a9c4b32013-06-19 21:10:23 +0800468 break;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800469 }
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800470 }
Rui Guo6a9c4b32013-06-19 21:10:23 +0800471 if (!pch)
Imre Deakbcdb72a2014-02-14 20:23:54 +0200472 DRM_DEBUG_KMS("No PCH found.\n");
473
474 pci_dev_put(pch);
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800475}
476
Ben Widawsky2911a352012-04-05 14:47:36 -0700477bool i915_semaphore_is_enabled(struct drm_device *dev)
478{
479 if (INTEL_INFO(dev)->gen < 6)
Daniel Vettera08acaf2013-12-17 09:56:53 +0100480 return false;
Ben Widawsky2911a352012-04-05 14:47:36 -0700481
Jani Nikulad330a952014-01-21 11:24:25 +0200482 if (i915.semaphores >= 0)
483 return i915.semaphores;
Ben Widawsky2911a352012-04-05 14:47:36 -0700484
Jani Nikulac923fac2014-03-05 14:17:28 +0200485 /* Until we get further testing... */
486 if (IS_GEN8(dev))
487 return false;
488
Daniel Vetter59de3292012-04-02 20:48:43 +0200489#ifdef CONFIG_INTEL_IOMMU
Ben Widawsky2911a352012-04-05 14:47:36 -0700490 /* Enable semaphores on SNB when IO remapping is off */
Daniel Vetter59de3292012-04-02 20:48:43 +0200491 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
492 return false;
493#endif
Ben Widawsky2911a352012-04-05 14:47:36 -0700494
Daniel Vettera08acaf2013-12-17 09:56:53 +0100495 return true;
Ben Widawsky2911a352012-04-05 14:47:36 -0700496}
497
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100498static int i915_drm_freeze(struct drm_device *dev)
499{
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100500 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes24576d22013-03-26 09:25:45 -0700501 struct drm_crtc *crtc;
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100502
Paulo Zanoni8a187452013-12-06 20:32:13 -0200503 intel_runtime_pm_get(dev_priv);
504
Zhang Ruib8efb172013-02-05 15:41:53 +0800505 /* ignore lid events during suspend */
506 mutex_lock(&dev_priv->modeset_restore_lock);
507 dev_priv->modeset_restore = MODESET_SUSPENDED;
508 mutex_unlock(&dev_priv->modeset_restore_lock);
509
Paulo Zanonic67a4702013-08-19 13:18:09 -0300510 /* We do a lot of poking in a lot of registers, make sure they work
511 * properly. */
Imre Deakda7e29b2014-02-18 00:02:02 +0200512 intel_display_set_init_power(dev_priv, true);
Paulo Zanonicb107992013-01-25 16:59:15 -0200513
Dave Airlie5bcf7192010-12-07 09:20:40 +1000514 drm_kms_helper_poll_disable(dev);
515
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100516 pci_save_state(dev->pdev);
517
518 /* If KMS is active, we do the leavevt stuff here */
519 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
Daniel Vetterdb1b76c2013-07-09 16:51:37 +0200520 int error;
521
Chris Wilson45c5f202013-10-16 11:50:01 +0100522 error = i915_gem_suspend(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100523 if (error) {
524 dev_err(&dev->pdev->dev,
525 "GEM idle failed, resume might fail\n");
526 return error;
527 }
Daniel Vettera261b242012-07-26 19:21:47 +0200528
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100529 drm_irq_uninstall(dev);
Daniel Vetter15239092013-03-05 09:50:58 +0100530 dev_priv->enable_hotplug_processing = false;
Imre Deakfe5b1882014-05-12 18:35:05 +0300531
532 intel_disable_gt_powersave(dev);
533
Jesse Barnes24576d22013-03-26 09:25:45 -0700534 /*
535 * Disable CRTCs directly since we want to preserve sw state
536 * for _thaw.
537 */
Daniel Vetter6e9f7982014-05-29 23:54:47 +0200538 drm_modeset_lock_all(dev);
Chris Wilsonf7ef3fa2014-05-22 09:44:40 +0100539 for_each_crtc(dev, crtc) {
Jesse Barnes24576d22013-03-26 09:25:45 -0700540 dev_priv->display.crtc_disable(crtc);
Chris Wilsonf7ef3fa2014-05-22 09:44:40 +0100541 }
Daniel Vetter6e9f7982014-05-29 23:54:47 +0200542 drm_modeset_unlock_all(dev);
Imre Deak7d708ee2013-04-17 14:04:50 +0300543
544 intel_modeset_suspend_hw(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100545 }
546
Ben Widawsky828c7902013-10-16 09:21:30 -0700547 i915_gem_suspend_gtt_mappings(dev);
548
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100549 i915_save_state(dev);
550
Chris Wilson44834a62010-08-19 16:09:23 +0100551 intel_opregion_fini(dev);
Chris Wilson28d85cd2014-03-13 11:05:02 +0000552 intel_uncore_fini(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100553
Dave Airlie3fa016a2012-03-28 10:48:49 +0100554 console_lock();
Damien Lespiaub6f3eff2013-06-10 15:48:09 +0100555 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
Dave Airlie3fa016a2012-03-28 10:48:49 +0100556 console_unlock();
557
Mika Kuoppala62d5d692014-02-25 17:11:28 +0200558 dev_priv->suspend_count++;
559
Kristen Carlson Accardi85e90672014-06-12 08:35:44 -0700560 intel_display_set_init_power(dev_priv, false);
561
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100562 return 0;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100563}
564
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000565int i915_suspend(struct drm_device *dev, pm_message_t state)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100566{
567 int error;
568
569 if (!dev || !dev->dev_private) {
570 DRM_ERROR("dev: %p\n", dev);
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700571 DRM_ERROR("DRM not initialized, aborting suspend.\n");
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000572 return -ENODEV;
573 }
574
Dave Airlieb932ccb2008-02-20 10:02:20 +1000575 if (state.event == PM_EVENT_PRETHAW)
576 return 0;
577
Dave Airlie5bcf7192010-12-07 09:20:40 +1000578
579 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
580 return 0;
Chris Wilson6eecba32010-09-08 09:45:11 +0100581
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100582 error = i915_drm_freeze(dev);
583 if (error)
584 return error;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000585
Dave Airlieb932ccb2008-02-20 10:02:20 +1000586 if (state.event == PM_EVENT_SUSPEND) {
587 /* Shut down the device */
588 pci_disable_device(dev->pdev);
589 pci_set_power_state(dev->pdev, PCI_D3hot);
590 }
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000591
592 return 0;
593}
594
Jesse Barnes073f34d2012-11-02 11:13:59 -0700595void intel_console_resume(struct work_struct *work)
596{
597 struct drm_i915_private *dev_priv =
598 container_of(work, struct drm_i915_private,
599 console_resume_work);
600 struct drm_device *dev = dev_priv->dev;
601
602 console_lock();
Damien Lespiaub6f3eff2013-06-10 15:48:09 +0100603 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
Jesse Barnes073f34d2012-11-02 11:13:59 -0700604 console_unlock();
605}
606
Imre Deak76c4b252014-04-01 19:55:22 +0300607static int i915_drm_thaw_early(struct drm_device *dev)
608{
609 struct drm_i915_private *dev_priv = dev->dev_private;
610
611 intel_uncore_early_sanitize(dev);
612 intel_uncore_sanitize(dev);
613 intel_power_domains_init_hw(dev_priv);
614
615 return 0;
616}
617
Paulo Zanoni9d49c0e2013-09-12 18:06:43 -0300618static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000619{
Jesse Barnes5669fca2009-02-17 15:13:31 -0800620 struct drm_i915_private *dev_priv = dev->dev_private;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100621
Paulo Zanoni9d49c0e2013-09-12 18:06:43 -0300622 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
623 restore_gtt_mappings) {
624 mutex_lock(&dev->struct_mutex);
625 i915_gem_restore_gtt_mappings(dev);
626 mutex_unlock(&dev->struct_mutex);
627 }
628
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100629 i915_restore_state(dev);
Chris Wilson44834a62010-08-19 16:09:23 +0100630 intel_opregion_setup(dev);
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100631
Jesse Barnes5669fca2009-02-17 15:13:31 -0800632 /* KMS EnterVT equivalent */
633 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
Paulo Zanonidde86e22012-12-01 12:04:25 -0200634 intel_init_pch_refclk(dev);
Daniel Vetter754970ee2014-01-16 22:28:44 +0100635 drm_mode_config_reset(dev);
Chris Wilson1833b132012-05-09 11:56:28 +0100636
Jesse Barnes5669fca2009-02-17 15:13:31 -0800637 mutex_lock(&dev->struct_mutex);
Chris Wilson074c6ad2014-04-09 09:19:43 +0100638 if (i915_gem_init_hw(dev)) {
639 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
640 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
641 }
Jesse Barnes5669fca2009-02-17 15:13:31 -0800642 mutex_unlock(&dev->struct_mutex);
Jesse Barnes226485e2009-02-23 15:41:09 -0800643
Daniel Vetter15239092013-03-05 09:50:58 +0100644 /* We need working interrupts for modeset enabling ... */
Daniel Vetterbb0f1b52013-11-03 21:09:27 +0100645 drm_irq_install(dev, dev->pdev->irq);
Daniel Vetter15239092013-03-05 09:50:58 +0100646
Chris Wilson1833b132012-05-09 11:56:28 +0100647 intel_modeset_init_hw(dev);
Jesse Barnes24576d22013-03-26 09:25:45 -0700648
649 drm_modeset_lock_all(dev);
650 intel_modeset_setup_hw_state(dev, true);
651 drm_modeset_unlock_all(dev);
Daniel Vetter15239092013-03-05 09:50:58 +0100652
653 /*
654 * ... but also need to make sure that hotplug processing
655 * doesn't cause havoc. Like in the driver load code we don't
656 * bother with the tiny race here where we might loose hotplug
657 * notifications.
658 * */
Daniel Vetter20afbda2012-12-11 14:05:07 +0100659 intel_hpd_init(dev);
Daniel Vetter15239092013-03-05 09:50:58 +0100660 dev_priv->enable_hotplug_processing = true;
Jesse Barnesbb60b962013-03-26 09:25:46 -0700661 /* Config may have changed between suspend and resume */
Jesse Barnes1ff74cf2014-05-20 15:25:33 -0700662 drm_helper_hpd_irq_event(dev);
Jesse Barnesd5bb0812011-01-05 12:01:26 -0800663 }
Jesse Barnes1daed3f2011-01-05 12:01:25 -0800664
Chris Wilson44834a62010-08-19 16:09:23 +0100665 intel_opregion_init(dev);
666
Jesse Barnes073f34d2012-11-02 11:13:59 -0700667 /*
668 * The console lock can be pretty contented on resume due
669 * to all the printk activity. Try to keep it out of the hot
670 * path of resume if possible.
671 */
672 if (console_trylock()) {
Damien Lespiaub6f3eff2013-06-10 15:48:09 +0100673 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
Jesse Barnes073f34d2012-11-02 11:13:59 -0700674 console_unlock();
675 } else {
676 schedule_work(&dev_priv->console_resume_work);
677 }
678
Zhang Ruib8efb172013-02-05 15:41:53 +0800679 mutex_lock(&dev_priv->modeset_restore_lock);
680 dev_priv->modeset_restore = MODESET_DONE;
681 mutex_unlock(&dev_priv->modeset_restore_lock);
Paulo Zanoni8a187452013-12-06 20:32:13 -0200682
683 intel_runtime_pm_put(dev_priv);
Chris Wilson074c6ad2014-04-09 09:19:43 +0100684 return 0;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100685}
686
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700687static int i915_drm_thaw(struct drm_device *dev)
688{
Daniel Vetter7f16e5c2013-11-04 16:28:47 +0100689 if (drm_core_check_feature(dev, DRIVER_MODESET))
Ben Widawsky828c7902013-10-16 09:21:30 -0700690 i915_check_and_clear_faults(dev);
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700691
Paulo Zanoni9d49c0e2013-09-12 18:06:43 -0300692 return __i915_drm_thaw(dev, true);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100693}
694
Imre Deak76c4b252014-04-01 19:55:22 +0300695static int i915_resume_early(struct drm_device *dev)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100696{
Dave Airlie5bcf7192010-12-07 09:20:40 +1000697 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
698 return 0;
699
Imre Deak76c4b252014-04-01 19:55:22 +0300700 /*
701 * We have a resume ordering issue with the snd-hda driver also
702 * requiring our device to be power up. Due to the lack of a
703 * parent/child relationship we currently solve this with an early
704 * resume hook.
705 *
706 * FIXME: This should be solved with a special hdmi sink device or
707 * similar so that power domains can be employed.
708 */
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100709 if (pci_enable_device(dev->pdev))
710 return -EIO;
711
712 pci_set_master(dev->pdev);
713
Imre Deak76c4b252014-04-01 19:55:22 +0300714 return i915_drm_thaw_early(dev);
715}
716
717int i915_resume(struct drm_device *dev)
718{
719 struct drm_i915_private *dev_priv = dev->dev_private;
720 int ret;
721
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700722 /*
723 * Platforms with opregion should have sane BIOS, older ones (gen3 and
Paulo Zanoni9d49c0e2013-09-12 18:06:43 -0300724 * earlier) need to restore the GTT mappings since the BIOS might clear
725 * all our scratch PTEs.
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700726 */
Paulo Zanoni9d49c0e2013-09-12 18:06:43 -0300727 ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
Chris Wilson6eecba32010-09-08 09:45:11 +0100728 if (ret)
729 return ret;
730
731 drm_kms_helper_poll_enable(dev);
732 return 0;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000733}
734
Imre Deak76c4b252014-04-01 19:55:22 +0300735static int i915_resume_legacy(struct drm_device *dev)
736{
737 i915_resume_early(dev);
738 i915_resume(dev);
739
740 return 0;
741}
742
Ben Gamari11ed50e2009-09-14 17:48:45 -0400743/**
Eugeni Dodonovf3953dc2011-11-28 16:15:17 -0200744 * i915_reset - reset chip after a hang
Ben Gamari11ed50e2009-09-14 17:48:45 -0400745 * @dev: drm device to reset
Ben Gamari11ed50e2009-09-14 17:48:45 -0400746 *
747 * Reset the chip. Useful if a hang is detected. Returns zero on successful
748 * reset or otherwise an error code.
749 *
750 * Procedure is fairly simple:
751 * - reset the chip using the reset reg
752 * - re-init context state
753 * - re-init hardware status page
754 * - re-init ring buffer
755 * - re-init interrupt state
756 * - re-init display
757 */
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200758int i915_reset(struct drm_device *dev)
Ben Gamari11ed50e2009-09-14 17:48:45 -0400759{
Jani Nikula50227e12014-03-31 14:27:21 +0300760 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson2e7c8ee2013-05-28 10:38:44 +0100761 bool simulated;
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700762 int ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400763
Jani Nikulad330a952014-01-21 11:24:25 +0200764 if (!i915.reset)
Chris Wilsond78cb502010-12-23 13:33:15 +0000765 return 0;
766
Daniel Vetterd54a02c2012-07-04 22:18:39 +0200767 mutex_lock(&dev->struct_mutex);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400768
Chris Wilson069efc12010-09-30 16:53:18 +0100769 i915_gem_reset(dev);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400770
Chris Wilson2e7c8ee2013-05-28 10:38:44 +0100771 simulated = dev_priv->gpu_error.stop_rings != 0;
772
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300773 ret = intel_gpu_reset(dev);
Daniel Vetter350d2702012-04-27 15:17:42 +0200774
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300775 /* Also reset the gpu hangman. */
776 if (simulated) {
777 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
778 dev_priv->gpu_error.stop_rings = 0;
779 if (ret == -ENODEV) {
Daniel Vetterf2d91a22013-11-07 09:48:57 +0100780 DRM_INFO("Reset not implemented, but ignoring "
781 "error for simulated gpu hangs\n");
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300782 ret = 0;
783 }
Chris Wilson2e7c8ee2013-05-28 10:38:44 +0100784 }
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300785
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700786 if (ret) {
Daniel Vetterf2d91a22013-11-07 09:48:57 +0100787 DRM_ERROR("Failed to reset chip: %i\n", ret);
Daniel J Bluemanf953c932010-05-17 14:23:52 +0100788 mutex_unlock(&dev->struct_mutex);
Chris Wilsonf803aa52010-09-19 12:38:26 +0100789 return ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400790 }
791
792 /* Ok, now get things going again... */
793
794 /*
795 * Everything depends on having the GTT running, so we need to start
796 * there. Fortunately we don't need to do this unless we reset the
797 * chip at a PCI level.
798 *
799 * Next we need to restore the context, but we don't use those
800 * yet either...
801 *
802 * Ring buffer needs to be re-initialized in the KMS case, or if X
803 * was running at the time of the reset (i.e. we weren't VT
804 * switched away).
805 */
806 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
Daniel Vetterdb1b76c2013-07-09 16:51:37 +0200807 !dev_priv->ums.mm_suspended) {
Daniel Vetterdb1b76c2013-07-09 16:51:37 +0200808 dev_priv->ums.mm_suspended = 0;
Eric Anholt75a68982010-11-18 09:31:13 +0800809
Ben Widawsky3d57e5b2013-10-14 10:01:36 -0700810 ret = i915_gem_init_hw(dev);
Daniel Vetter8e88a2b2012-06-19 18:40:00 +0200811 mutex_unlock(&dev->struct_mutex);
Ben Widawsky3d57e5b2013-10-14 10:01:36 -0700812 if (ret) {
813 DRM_ERROR("Failed hw init on reset %d\n", ret);
814 return ret;
815 }
Daniel Vetterf8175862012-04-10 15:50:11 +0200816
Daniel Vettere090c532013-11-03 20:27:05 +0100817 /*
Daniel Vetter78ad4552014-05-22 22:18:21 +0200818 * FIXME: This races pretty badly against concurrent holders of
819 * ring interrupts. This is possible since we've started to drop
820 * dev->struct_mutex in select places when waiting for the gpu.
Daniel Vettere090c532013-11-03 20:27:05 +0100821 */
Jeff McGeedd0a1aa2014-02-04 11:32:31 -0600822
Daniel Vetter78ad4552014-05-22 22:18:21 +0200823 /*
824 * rps/rc6 re-init is necessary to restore state lost after the
825 * reset and the re-install of gt irqs. Skip for ironlake per
Jeff McGeedd0a1aa2014-02-04 11:32:31 -0600826 * previous concerns that it doesn't respond well to some forms
Daniel Vetter78ad4552014-05-22 22:18:21 +0200827 * of re-init after reset.
828 */
Imre Deakdc1d0132014-04-14 20:24:28 +0300829 if (INTEL_INFO(dev)->gen > 5)
Imre Deakc6df39b2014-04-14 20:24:29 +0300830 intel_reset_gt_powersave(dev);
Jeff McGeedd0a1aa2014-02-04 11:32:31 -0600831
Daniel Vetter20afbda2012-12-11 14:05:07 +0100832 intel_hpd_init(dev);
Daniel Vetterbcbc3242012-04-27 15:17:41 +0200833 } else {
834 mutex_unlock(&dev->struct_mutex);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400835 }
836
Ben Gamari11ed50e2009-09-14 17:48:45 -0400837 return 0;
838}
839
Greg Kroah-Hartman56550d92012-12-21 15:09:25 -0800840static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500841{
Daniel Vetter01a06852012-06-25 15:58:49 +0200842 struct intel_device_info *intel_info =
843 (struct intel_device_info *) ent->driver_data;
844
Jani Nikulad330a952014-01-21 11:24:25 +0200845 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
Ben Widawskyb833d682013-08-23 16:00:07 -0700846 DRM_INFO("This hardware requires preliminary hardware support.\n"
847 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
848 return -ENODEV;
849 }
850
Chris Wilson5fe49d82011-02-01 19:43:02 +0000851 /* Only bind to function 0 of the device. Early generations
852 * used function 1 as a placeholder for multi-head. This causes
853 * us confusion instead, especially on the systems where both
854 * functions have the same PCI-ID!
855 */
856 if (PCI_FUNC(pdev->devfn))
857 return -ENODEV;
858
Daniel Vetter24986ee2013-12-11 11:34:33 +0100859 driver.driver_features &= ~(DRIVER_USE_AGP);
Daniel Vetter01a06852012-06-25 15:58:49 +0200860
Jordan Crousedcdb1672010-05-27 13:40:25 -0600861 return drm_get_pci_dev(pdev, ent, &driver);
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500862}
863
864static void
865i915_pci_remove(struct pci_dev *pdev)
866{
867 struct drm_device *dev = pci_get_drvdata(pdev);
868
869 drm_put_dev(dev);
870}
871
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100872static int i915_pm_suspend(struct device *dev)
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500873{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100874 struct pci_dev *pdev = to_pci_dev(dev);
875 struct drm_device *drm_dev = pci_get_drvdata(pdev);
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500876
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100877 if (!drm_dev || !drm_dev->dev_private) {
878 dev_err(dev, "DRM not initialized, aborting suspend.\n");
879 return -ENODEV;
880 }
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500881
Dave Airlie5bcf7192010-12-07 09:20:40 +1000882 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
883 return 0;
884
Imre Deak76c4b252014-04-01 19:55:22 +0300885 return i915_drm_freeze(drm_dev);
886}
887
888static int i915_pm_suspend_late(struct device *dev)
889{
890 struct pci_dev *pdev = to_pci_dev(dev);
891 struct drm_device *drm_dev = pci_get_drvdata(pdev);
892
893 /*
894 * We have a suspedn ordering issue with the snd-hda driver also
895 * requiring our device to be power up. Due to the lack of a
896 * parent/child relationship we currently solve this with an late
897 * suspend hook.
898 *
899 * FIXME: This should be solved with a special hdmi sink device or
900 * similar so that power domains can be employed.
901 */
902 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
903 return 0;
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500904
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100905 pci_disable_device(pdev);
906 pci_set_power_state(pdev, PCI_D3hot);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800907
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800908 return 0;
909}
910
Imre Deak76c4b252014-04-01 19:55:22 +0300911static int i915_pm_resume_early(struct device *dev)
912{
913 struct pci_dev *pdev = to_pci_dev(dev);
914 struct drm_device *drm_dev = pci_get_drvdata(pdev);
915
916 return i915_resume_early(drm_dev);
917}
918
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100919static int i915_pm_resume(struct device *dev)
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800920{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100921 struct pci_dev *pdev = to_pci_dev(dev);
922 struct drm_device *drm_dev = pci_get_drvdata(pdev);
923
924 return i915_resume(drm_dev);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800925}
926
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100927static int i915_pm_freeze(struct device *dev)
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800928{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100929 struct pci_dev *pdev = to_pci_dev(dev);
930 struct drm_device *drm_dev = pci_get_drvdata(pdev);
931
932 if (!drm_dev || !drm_dev->dev_private) {
933 dev_err(dev, "DRM not initialized, aborting suspend.\n");
934 return -ENODEV;
935 }
936
937 return i915_drm_freeze(drm_dev);
938}
939
Imre Deak76c4b252014-04-01 19:55:22 +0300940static int i915_pm_thaw_early(struct device *dev)
941{
942 struct pci_dev *pdev = to_pci_dev(dev);
943 struct drm_device *drm_dev = pci_get_drvdata(pdev);
944
945 return i915_drm_thaw_early(drm_dev);
946}
947
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100948static int i915_pm_thaw(struct device *dev)
949{
950 struct pci_dev *pdev = to_pci_dev(dev);
951 struct drm_device *drm_dev = pci_get_drvdata(pdev);
952
953 return i915_drm_thaw(drm_dev);
954}
955
956static int i915_pm_poweroff(struct device *dev)
957{
958 struct pci_dev *pdev = to_pci_dev(dev);
959 struct drm_device *drm_dev = pci_get_drvdata(pdev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100960
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100961 return i915_drm_freeze(drm_dev);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800962}
963
Imre Deak0ab9cfe2014-04-15 16:39:45 +0300964static int hsw_runtime_suspend(struct drm_i915_private *dev_priv)
Paulo Zanoni97bea202014-03-07 20:12:33 -0300965{
Paulo Zanoni414de7a2014-03-07 20:12:35 -0300966 hsw_enable_pc8(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +0300967
968 return 0;
Paulo Zanoni97bea202014-03-07 20:12:33 -0300969}
970
Imre Deak0ab9cfe2014-04-15 16:39:45 +0300971static int snb_runtime_resume(struct drm_i915_private *dev_priv)
Paulo Zanoni9a952a02014-03-07 20:12:34 -0300972{
973 struct drm_device *dev = dev_priv->dev;
974
Paulo Zanoni9a952a02014-03-07 20:12:34 -0300975 intel_init_pch_refclk(dev);
Imre Deak0ab9cfe2014-04-15 16:39:45 +0300976
977 return 0;
Paulo Zanoni9a952a02014-03-07 20:12:34 -0300978}
979
Imre Deak0ab9cfe2014-04-15 16:39:45 +0300980static int hsw_runtime_resume(struct drm_i915_private *dev_priv)
Paulo Zanoni97bea202014-03-07 20:12:33 -0300981{
Paulo Zanoni414de7a2014-03-07 20:12:35 -0300982 hsw_disable_pc8(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +0300983
984 return 0;
Paulo Zanoni97bea202014-03-07 20:12:33 -0300985}
986
Imre Deakddeea5b2014-05-05 15:19:56 +0300987/*
988 * Save all Gunit registers that may be lost after a D3 and a subsequent
989 * S0i[R123] transition. The list of registers needing a save/restore is
990 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
991 * registers in the following way:
992 * - Driver: saved/restored by the driver
993 * - Punit : saved/restored by the Punit firmware
994 * - No, w/o marking: no need to save/restore, since the register is R/O or
995 * used internally by the HW in a way that doesn't depend
996 * keeping the content across a suspend/resume.
997 * - Debug : used for debugging
998 *
999 * We save/restore all registers marked with 'Driver', with the following
1000 * exceptions:
1001 * - Registers out of use, including also registers marked with 'Debug'.
1002 * These have no effect on the driver's operation, so we don't save/restore
1003 * them to reduce the overhead.
1004 * - Registers that are fully setup by an initialization function called from
1005 * the resume path. For example many clock gating and RPS/RC6 registers.
1006 * - Registers that provide the right functionality with their reset defaults.
1007 *
1008 * TODO: Except for registers that based on the above 3 criteria can be safely
1009 * ignored, we save/restore all others, practically treating the HW context as
1010 * a black-box for the driver. Further investigation is needed to reduce the
1011 * saved/restored registers even further, by following the same 3 criteria.
1012 */
1013static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1014{
1015 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1016 int i;
1017
1018 /* GAM 0x4000-0x4770 */
1019 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1020 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1021 s->arb_mode = I915_READ(ARB_MODE);
1022 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1023 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1024
1025 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1026 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1027
1028 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1029 s->gfx_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1030
1031 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1032 s->ecochk = I915_READ(GAM_ECOCHK);
1033 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1034 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1035
1036 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1037
1038 /* MBC 0x9024-0x91D0, 0x8500 */
1039 s->g3dctl = I915_READ(VLV_G3DCTL);
1040 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1041 s->mbctl = I915_READ(GEN6_MBCTL);
1042
1043 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1044 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1045 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1046 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1047 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1048 s->rstctl = I915_READ(GEN6_RSTCTL);
1049 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1050
1051 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1052 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1053 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1054 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1055 s->ecobus = I915_READ(ECOBUS);
1056 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1057 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1058 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1059 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1060 s->rcedata = I915_READ(VLV_RCEDATA);
1061 s->spare2gh = I915_READ(VLV_SPAREG2H);
1062
1063 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1064 s->gt_imr = I915_READ(GTIMR);
1065 s->gt_ier = I915_READ(GTIER);
1066 s->pm_imr = I915_READ(GEN6_PMIMR);
1067 s->pm_ier = I915_READ(GEN6_PMIER);
1068
1069 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1070 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1071
1072 /* GT SA CZ domain, 0x100000-0x138124 */
1073 s->tilectl = I915_READ(TILECTL);
1074 s->gt_fifoctl = I915_READ(GTFIFOCTL);
1075 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1076 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1077 s->pmwgicz = I915_READ(VLV_PMWGICZ);
1078
1079 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1080 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1081 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
1082 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1083
1084 /*
1085 * Not saving any of:
1086 * DFT, 0x9800-0x9EC0
1087 * SARB, 0xB000-0xB1FC
1088 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1089 * PCI CFG
1090 */
1091}
1092
1093static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1094{
1095 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1096 u32 val;
1097 int i;
1098
1099 /* GAM 0x4000-0x4770 */
1100 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1101 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1102 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1103 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1104 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1105
1106 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1107 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1108
1109 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1110 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1111
1112 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1113 I915_WRITE(GAM_ECOCHK, s->ecochk);
1114 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1115 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1116
1117 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1118
1119 /* MBC 0x9024-0x91D0, 0x8500 */
1120 I915_WRITE(VLV_G3DCTL, s->g3dctl);
1121 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1122 I915_WRITE(GEN6_MBCTL, s->mbctl);
1123
1124 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1125 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1126 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1127 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1128 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1129 I915_WRITE(GEN6_RSTCTL, s->rstctl);
1130 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1131
1132 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1133 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1134 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1135 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1136 I915_WRITE(ECOBUS, s->ecobus);
1137 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1138 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1139 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1140 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1141 I915_WRITE(VLV_RCEDATA, s->rcedata);
1142 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1143
1144 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1145 I915_WRITE(GTIMR, s->gt_imr);
1146 I915_WRITE(GTIER, s->gt_ier);
1147 I915_WRITE(GEN6_PMIMR, s->pm_imr);
1148 I915_WRITE(GEN6_PMIER, s->pm_ier);
1149
1150 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1151 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1152
1153 /* GT SA CZ domain, 0x100000-0x138124 */
1154 I915_WRITE(TILECTL, s->tilectl);
1155 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1156 /*
1157 * Preserve the GT allow wake and GFX force clock bit, they are not
1158 * be restored, as they are used to control the s0ix suspend/resume
1159 * sequence by the caller.
1160 */
1161 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1162 val &= VLV_GTLC_ALLOWWAKEREQ;
1163 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1164 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1165
1166 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1167 val &= VLV_GFX_CLK_FORCE_ON_BIT;
1168 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1169 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1170
1171 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1172
1173 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1174 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1175 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
1176 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1177}
1178
Imre Deak650ad972014-04-18 16:35:02 +03001179int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1180{
1181 u32 val;
1182 int err;
1183
1184 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1185 WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1186
1187#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1188 /* Wait for a previous force-off to settle */
1189 if (force_on) {
Imre Deak8d4eee92014-04-14 20:24:43 +03001190 err = wait_for(!COND, 20);
Imre Deak650ad972014-04-18 16:35:02 +03001191 if (err) {
1192 DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1193 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1194 return err;
1195 }
1196 }
1197
1198 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1199 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1200 if (force_on)
1201 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1202 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1203
1204 if (!force_on)
1205 return 0;
1206
Imre Deak8d4eee92014-04-14 20:24:43 +03001207 err = wait_for(COND, 20);
Imre Deak650ad972014-04-18 16:35:02 +03001208 if (err)
1209 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1210 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1211
1212 return err;
1213#undef COND
1214}
1215
Imre Deakddeea5b2014-05-05 15:19:56 +03001216static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1217{
1218 u32 val;
1219 int err = 0;
1220
1221 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1222 val &= ~VLV_GTLC_ALLOWWAKEREQ;
1223 if (allow)
1224 val |= VLV_GTLC_ALLOWWAKEREQ;
1225 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1226 POSTING_READ(VLV_GTLC_WAKE_CTRL);
1227
1228#define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1229 allow)
1230 err = wait_for(COND, 1);
1231 if (err)
1232 DRM_ERROR("timeout disabling GT waking\n");
1233 return err;
1234#undef COND
1235}
1236
1237static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1238 bool wait_for_on)
1239{
1240 u32 mask;
1241 u32 val;
1242 int err;
1243
1244 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1245 val = wait_for_on ? mask : 0;
1246#define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1247 if (COND)
1248 return 0;
1249
1250 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1251 wait_for_on ? "on" : "off",
1252 I915_READ(VLV_GTLC_PW_STATUS));
1253
1254 /*
1255 * RC6 transitioning can be delayed up to 2 msec (see
1256 * valleyview_enable_rps), use 3 msec for safety.
1257 */
1258 err = wait_for(COND, 3);
1259 if (err)
1260 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1261 wait_for_on ? "on" : "off");
1262
1263 return err;
1264#undef COND
1265}
1266
1267static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1268{
1269 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1270 return;
1271
1272 DRM_ERROR("GT register access while GT waking disabled\n");
1273 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1274}
1275
1276static int vlv_runtime_suspend(struct drm_i915_private *dev_priv)
1277{
1278 u32 mask;
1279 int err;
1280
1281 /*
1282 * Bspec defines the following GT well on flags as debug only, so
1283 * don't treat them as hard failures.
1284 */
1285 (void)vlv_wait_for_gt_wells(dev_priv, false);
1286
1287 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1288 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1289
1290 vlv_check_no_gt_access(dev_priv);
1291
1292 err = vlv_force_gfx_clock(dev_priv, true);
1293 if (err)
1294 goto err1;
1295
1296 err = vlv_allow_gt_wake(dev_priv, false);
1297 if (err)
1298 goto err2;
1299 vlv_save_gunit_s0ix_state(dev_priv);
1300
1301 err = vlv_force_gfx_clock(dev_priv, false);
1302 if (err)
1303 goto err2;
1304
1305 return 0;
1306
1307err2:
1308 /* For safety always re-enable waking and disable gfx clock forcing */
1309 vlv_allow_gt_wake(dev_priv, true);
1310err1:
1311 vlv_force_gfx_clock(dev_priv, false);
1312
1313 return err;
1314}
1315
1316static int vlv_runtime_resume(struct drm_i915_private *dev_priv)
1317{
1318 struct drm_device *dev = dev_priv->dev;
1319 int err;
1320 int ret;
1321
1322 /*
1323 * If any of the steps fail just try to continue, that's the best we
1324 * can do at this point. Return the first error code (which will also
1325 * leave RPM permanently disabled).
1326 */
1327 ret = vlv_force_gfx_clock(dev_priv, true);
1328
1329 vlv_restore_gunit_s0ix_state(dev_priv);
1330
1331 err = vlv_allow_gt_wake(dev_priv, true);
1332 if (!ret)
1333 ret = err;
1334
1335 err = vlv_force_gfx_clock(dev_priv, false);
1336 if (!ret)
1337 ret = err;
1338
1339 vlv_check_no_gt_access(dev_priv);
1340
1341 intel_init_clock_gating(dev);
1342 i915_gem_restore_fences(dev);
1343
1344 return ret;
1345}
1346
Paulo Zanoni97bea202014-03-07 20:12:33 -03001347static int intel_runtime_suspend(struct device *device)
Paulo Zanoni8a187452013-12-06 20:32:13 -02001348{
1349 struct pci_dev *pdev = to_pci_dev(device);
1350 struct drm_device *dev = pci_get_drvdata(pdev);
1351 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001352 int ret;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001353
Imre Deakaeab0b52014-04-14 20:24:36 +03001354 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
Imre Deakc6df39b2014-04-14 20:24:29 +03001355 return -ENODEV;
1356
Paulo Zanoni8a187452013-12-06 20:32:13 -02001357 WARN_ON(!HAS_RUNTIME_PM(dev));
Paulo Zanonie998c402014-02-21 13:52:26 -03001358 assert_force_wake_inactive(dev_priv);
Paulo Zanoni8a187452013-12-06 20:32:13 -02001359
1360 DRM_DEBUG_KMS("Suspending device\n");
1361
Imre Deak9486db62014-04-22 20:21:07 +03001362 /*
Imre Deakd6102972014-05-07 19:57:49 +03001363 * We could deadlock here in case another thread holding struct_mutex
1364 * calls RPM suspend concurrently, since the RPM suspend will wait
1365 * first for this RPM suspend to finish. In this case the concurrent
1366 * RPM resume will be followed by its RPM suspend counterpart. Still
1367 * for consistency return -EAGAIN, which will reschedule this suspend.
1368 */
1369 if (!mutex_trylock(&dev->struct_mutex)) {
1370 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1371 /*
1372 * Bump the expiration timestamp, otherwise the suspend won't
1373 * be rescheduled.
1374 */
1375 pm_runtime_mark_last_busy(device);
1376
1377 return -EAGAIN;
1378 }
1379 /*
1380 * We are safe here against re-faults, since the fault handler takes
1381 * an RPM reference.
1382 */
1383 i915_gem_release_all_mmaps(dev_priv);
1384 mutex_unlock(&dev->struct_mutex);
1385
1386 /*
Imre Deak9486db62014-04-22 20:21:07 +03001387 * rps.work can't be rearmed here, since we get here only after making
1388 * sure the GPU is idle and the RPS freq is set to the minimum. See
1389 * intel_mark_idle().
1390 */
1391 cancel_work_sync(&dev_priv->rps.work);
Imre Deakb5478bc2014-04-14 20:24:37 +03001392 intel_runtime_pm_disable_interrupts(dev);
1393
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001394 if (IS_GEN6(dev)) {
1395 ret = 0;
1396 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1397 ret = hsw_runtime_suspend(dev_priv);
Imre Deakddeea5b2014-05-05 15:19:56 +03001398 } else if (IS_VALLEYVIEW(dev)) {
1399 ret = vlv_runtime_suspend(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001400 } else {
1401 ret = -ENODEV;
Paulo Zanoni6157d3c2014-03-07 20:12:37 -03001402 WARN_ON(1);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001403 }
1404
1405 if (ret) {
1406 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1407 intel_runtime_pm_restore_interrupts(dev);
1408
1409 return ret;
1410 }
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001411
Paulo Zanoni16a3d6e2013-12-13 15:22:30 -02001412 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
Paulo Zanoni8a187452013-12-06 20:32:13 -02001413 dev_priv->pm.suspended = true;
Kristen Carlson Accardi1fb23622014-01-14 15:36:15 -08001414
1415 /*
1416 * current versions of firmware which depend on this opregion
1417 * notification have repurposed the D1 definition to mean
1418 * "runtime suspended" vs. what you would normally expect (D3)
1419 * to distinguish it from notifications that might be sent
1420 * via the suspend path.
1421 */
1422 intel_opregion_notify_adapter(dev, PCI_D1);
Paulo Zanoni8a187452013-12-06 20:32:13 -02001423
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001424 DRM_DEBUG_KMS("Device suspended\n");
Paulo Zanoni8a187452013-12-06 20:32:13 -02001425 return 0;
1426}
1427
Paulo Zanoni97bea202014-03-07 20:12:33 -03001428static int intel_runtime_resume(struct device *device)
Paulo Zanoni8a187452013-12-06 20:32:13 -02001429{
1430 struct pci_dev *pdev = to_pci_dev(device);
1431 struct drm_device *dev = pci_get_drvdata(pdev);
1432 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001433 int ret;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001434
1435 WARN_ON(!HAS_RUNTIME_PM(dev));
1436
1437 DRM_DEBUG_KMS("Resuming device\n");
1438
Paulo Zanonicd2e9e92013-12-06 20:34:21 -02001439 intel_opregion_notify_adapter(dev, PCI_D0);
Paulo Zanoni8a187452013-12-06 20:32:13 -02001440 dev_priv->pm.suspended = false;
1441
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001442 if (IS_GEN6(dev)) {
1443 ret = snb_runtime_resume(dev_priv);
1444 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1445 ret = hsw_runtime_resume(dev_priv);
Imre Deakddeea5b2014-05-05 15:19:56 +03001446 } else if (IS_VALLEYVIEW(dev)) {
1447 ret = vlv_runtime_resume(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001448 } else {
Paulo Zanoni6157d3c2014-03-07 20:12:37 -03001449 WARN_ON(1);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001450 ret = -ENODEV;
1451 }
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001452
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001453 /*
1454 * No point of rolling back things in case of an error, as the best
1455 * we can do is to hope that things will still work (and disable RPM).
1456 */
Imre Deak92b806d2014-04-14 20:24:39 +03001457 i915_gem_init_swizzling(dev);
1458 gen6_update_ring_freq(dev);
1459
Imre Deakb5478bc2014-04-14 20:24:37 +03001460 intel_runtime_pm_restore_interrupts(dev);
Imre Deak9486db62014-04-22 20:21:07 +03001461 intel_reset_gt_powersave(dev);
Imre Deakb5478bc2014-04-14 20:24:37 +03001462
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001463 if (ret)
1464 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1465 else
1466 DRM_DEBUG_KMS("Device resumed\n");
1467
1468 return ret;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001469}
1470
Chris Wilsonb4b78d12010-06-06 15:40:20 +01001471static const struct dev_pm_ops i915_pm_ops = {
Akshay Joshi0206e352011-08-16 15:34:10 -04001472 .suspend = i915_pm_suspend,
Imre Deak76c4b252014-04-01 19:55:22 +03001473 .suspend_late = i915_pm_suspend_late,
1474 .resume_early = i915_pm_resume_early,
Akshay Joshi0206e352011-08-16 15:34:10 -04001475 .resume = i915_pm_resume,
1476 .freeze = i915_pm_freeze,
Imre Deak76c4b252014-04-01 19:55:22 +03001477 .thaw_early = i915_pm_thaw_early,
Akshay Joshi0206e352011-08-16 15:34:10 -04001478 .thaw = i915_pm_thaw,
1479 .poweroff = i915_pm_poweroff,
Imre Deak76c4b252014-04-01 19:55:22 +03001480 .restore_early = i915_pm_resume_early,
Akshay Joshi0206e352011-08-16 15:34:10 -04001481 .restore = i915_pm_resume,
Paulo Zanoni97bea202014-03-07 20:12:33 -03001482 .runtime_suspend = intel_runtime_suspend,
1483 .runtime_resume = intel_runtime_resume,
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001484};
1485
Laurent Pinchart78b68552012-05-17 13:27:22 +02001486static const struct vm_operations_struct i915_gem_vm_ops = {
Jesse Barnesde151cf2008-11-12 10:03:55 -08001487 .fault = i915_gem_fault,
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001488 .open = drm_gem_vm_open,
1489 .close = drm_gem_vm_close,
Jesse Barnesde151cf2008-11-12 10:03:55 -08001490};
1491
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001492static const struct file_operations i915_driver_fops = {
1493 .owner = THIS_MODULE,
1494 .open = drm_open,
1495 .release = drm_release,
1496 .unlocked_ioctl = drm_ioctl,
1497 .mmap = drm_gem_mmap,
1498 .poll = drm_poll,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001499 .read = drm_read,
1500#ifdef CONFIG_COMPAT
1501 .compat_ioctl = i915_compat_ioctl,
1502#endif
1503 .llseek = noop_llseek,
1504};
1505
Linus Torvalds1da177e2005-04-16 15:20:36 -07001506static struct drm_driver driver = {
Michael Witten0c547812011-08-25 17:55:54 +00001507 /* Don't use MTRRs here; the Xserver or userspace app should
1508 * deal with them for Intel hardware.
Dave Airlie792d2b92005-11-11 23:30:27 +11001509 */
Eric Anholt673a3942008-07-30 12:06:12 -07001510 .driver_features =
Daniel Vetter24986ee2013-12-11 11:34:33 +01001511 DRIVER_USE_AGP |
Kristian Høgsberg10ba5012013-08-25 18:29:01 +02001512 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1513 DRIVER_RENDER,
Dave Airlie22eae942005-11-10 22:16:34 +11001514 .load = i915_driver_load,
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001515 .unload = i915_driver_unload,
Eric Anholt673a3942008-07-30 12:06:12 -07001516 .open = i915_driver_open,
Dave Airlie22eae942005-11-10 22:16:34 +11001517 .lastclose = i915_driver_lastclose,
1518 .preclose = i915_driver_preclose,
Eric Anholt673a3942008-07-30 12:06:12 -07001519 .postclose = i915_driver_postclose,
Rafael J. Wysockid8e29202010-01-09 00:45:33 +01001520
1521 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1522 .suspend = i915_suspend,
Imre Deak76c4b252014-04-01 19:55:22 +03001523 .resume = i915_resume_legacy,
Rafael J. Wysockid8e29202010-01-09 00:45:33 +01001524
Dave Airliecda17382005-07-10 17:31:26 +10001525 .device_is_agp = i915_driver_device_is_agp,
Dave Airlie7c1c2872008-11-28 14:22:24 +10001526 .master_create = i915_master_create,
1527 .master_destroy = i915_master_destroy,
Ben Gamari955b12d2009-02-17 20:08:49 -05001528#if defined(CONFIG_DEBUG_FS)
Ben Gamari27c202a2009-07-01 22:26:52 -04001529 .debugfs_init = i915_debugfs_init,
1530 .debugfs_cleanup = i915_debugfs_cleanup,
Ben Gamari955b12d2009-02-17 20:08:49 -05001531#endif
Eric Anholt673a3942008-07-30 12:06:12 -07001532 .gem_free_object = i915_gem_free_object,
Jesse Barnesde151cf2008-11-12 10:03:55 -08001533 .gem_vm_ops = &i915_gem_vm_ops,
Daniel Vetter1286ff72012-05-10 15:25:09 +02001534
1535 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1536 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1537 .gem_prime_export = i915_gem_prime_export,
1538 .gem_prime_import = i915_gem_prime_import,
1539
Dave Airlieff72145b2011-02-07 12:16:14 +10001540 .dumb_create = i915_gem_dumb_create,
1541 .dumb_map_offset = i915_gem_mmap_gtt,
Daniel Vetter43387b32013-07-16 09:12:04 +02001542 .dumb_destroy = drm_gem_dumb_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001543 .ioctls = i915_ioctls,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001544 .fops = &i915_driver_fops,
Dave Airlie22eae942005-11-10 22:16:34 +11001545 .name = DRIVER_NAME,
1546 .desc = DRIVER_DESC,
1547 .date = DRIVER_DATE,
1548 .major = DRIVER_MAJOR,
1549 .minor = DRIVER_MINOR,
1550 .patchlevel = DRIVER_PATCHLEVEL,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001551};
1552
Dave Airlie8410ea32010-12-15 03:16:38 +10001553static struct pci_driver i915_pci_driver = {
1554 .name = DRIVER_NAME,
1555 .id_table = pciidlist,
1556 .probe = i915_pci_probe,
1557 .remove = i915_pci_remove,
1558 .driver.pm = &i915_pm_ops,
1559};
1560
Linus Torvalds1da177e2005-04-16 15:20:36 -07001561static int __init i915_init(void)
1562{
1563 driver.num_ioctls = i915_max_ioctl;
Jesse Barnes79e53942008-11-07 14:24:08 -08001564
1565 /*
1566 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1567 * explicitly disabled with the module pararmeter.
1568 *
1569 * Otherwise, just follow the parameter (defaulting to off).
1570 *
1571 * Allow optional vga_text_mode_force boot option to override
1572 * the default behavior.
1573 */
1574#if defined(CONFIG_DRM_I915_KMS)
Jani Nikulad330a952014-01-21 11:24:25 +02001575 if (i915.modeset != 0)
Jesse Barnes79e53942008-11-07 14:24:08 -08001576 driver.driver_features |= DRIVER_MODESET;
1577#endif
Jani Nikulad330a952014-01-21 11:24:25 +02001578 if (i915.modeset == 1)
Jesse Barnes79e53942008-11-07 14:24:08 -08001579 driver.driver_features |= DRIVER_MODESET;
1580
1581#ifdef CONFIG_VGA_CONSOLE
Jani Nikulad330a952014-01-21 11:24:25 +02001582 if (vgacon_text_force() && i915.modeset == -1)
Jesse Barnes79e53942008-11-07 14:24:08 -08001583 driver.driver_features &= ~DRIVER_MODESET;
1584#endif
1585
Daniel Vetterb30324a2013-11-13 22:11:25 +01001586 if (!(driver.driver_features & DRIVER_MODESET)) {
Chris Wilson3885c6b2011-01-23 10:45:14 +00001587 driver.get_vblank_timestamp = NULL;
Daniel Vetterb30324a2013-11-13 22:11:25 +01001588#ifndef CONFIG_DRM_I915_UMS
1589 /* Silently fail loading to not upset userspace. */
Jani Nikulac9cd7b62014-06-02 16:58:30 +03001590 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
Daniel Vetterb30324a2013-11-13 22:11:25 +01001591 return 0;
1592#endif
1593 }
Chris Wilson3885c6b2011-01-23 10:45:14 +00001594
Dave Airlie8410ea32010-12-15 03:16:38 +10001595 return drm_pci_init(&driver, &i915_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001596}
1597
1598static void __exit i915_exit(void)
1599{
Daniel Vetterb33ecdd2013-11-15 17:16:33 +01001600#ifndef CONFIG_DRM_I915_UMS
1601 if (!(driver.driver_features & DRIVER_MODESET))
1602 return; /* Never loaded a driver. */
1603#endif
1604
Dave Airlie8410ea32010-12-15 03:16:38 +10001605 drm_pci_exit(&driver, &i915_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001606}
1607
1608module_init(i915_init);
1609module_exit(i915_exit);
1610
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001611MODULE_AUTHOR(DRIVER_AUTHOR);
1612MODULE_DESCRIPTION(DRIVER_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001613MODULE_LICENSE("GPL and additional rights");