Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #ifndef __RADEON_H__ |
| 29 | #define __RADEON_H__ |
| 30 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 31 | /* TODO: Here are things that needs to be done : |
| 32 | * - surface allocator & initializer : (bit like scratch reg) should |
| 33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
| 34 | * related to surface |
| 35 | * - WB : write back stuff (do it bit like scratch reg things) |
| 36 | * - Vblank : look at Jesse's rework and what we should do |
| 37 | * - r600/r700: gart & cp |
| 38 | * - cs : clean cs ioctl use bitmap & things like that. |
| 39 | * - power management stuff |
| 40 | * - Barrier in gart code |
| 41 | * - Unmappabled vram ? |
| 42 | * - TESTING, TESTING, TESTING |
| 43 | */ |
| 44 | |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 45 | /* Initialization path: |
| 46 | * We expect that acceleration initialization might fail for various |
| 47 | * reasons even thought we work hard to make it works on most |
| 48 | * configurations. In order to still have a working userspace in such |
| 49 | * situation the init path must succeed up to the memory controller |
| 50 | * initialization point. Failure before this point are considered as |
| 51 | * fatal error. Here is the init callchain : |
| 52 | * radeon_device_init perform common structure, mutex initialization |
| 53 | * asic_init setup the GPU memory layout and perform all |
| 54 | * one time initialization (failure in this |
| 55 | * function are considered fatal) |
| 56 | * asic_startup setup the GPU acceleration, in order to |
| 57 | * follow guideline the first thing this |
| 58 | * function should do is setting the GPU |
| 59 | * memory controller (only MC setup failure |
| 60 | * are considered as fatal) |
| 61 | */ |
| 62 | |
Arun Sharma | 60063497 | 2011-07-26 16:09:06 -0700 | [diff] [blame] | 63 | #include <linux/atomic.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 64 | #include <linux/wait.h> |
| 65 | #include <linux/list.h> |
| 66 | #include <linux/kref.h> |
| 67 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 68 | #include <ttm/ttm_bo_api.h> |
| 69 | #include <ttm/ttm_bo_driver.h> |
| 70 | #include <ttm/ttm_placement.h> |
| 71 | #include <ttm/ttm_module.h> |
Thomas Hellstrom | 147666f | 2010-11-17 12:38:32 +0000 | [diff] [blame] | 72 | #include <ttm/ttm_execbuf_util.h> |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 73 | |
Dave Airlie | c214271 | 2009-09-22 08:50:10 +1000 | [diff] [blame] | 74 | #include "radeon_family.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 75 | #include "radeon_mode.h" |
| 76 | #include "radeon_reg.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 77 | |
| 78 | /* |
| 79 | * Modules parameters. |
| 80 | */ |
| 81 | extern int radeon_no_wb; |
| 82 | extern int radeon_modeset; |
| 83 | extern int radeon_dynclks; |
| 84 | extern int radeon_r4xx_atom; |
| 85 | extern int radeon_agpmode; |
| 86 | extern int radeon_vram_limit; |
| 87 | extern int radeon_gart_size; |
| 88 | extern int radeon_benchmarking; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 89 | extern int radeon_testing; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 90 | extern int radeon_connector_table; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 91 | extern int radeon_tv; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 92 | extern int radeon_audio; |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 93 | extern int radeon_disp_priority; |
Alex Deucher | e2b0a8e | 2010-03-17 02:07:37 -0400 | [diff] [blame] | 94 | extern int radeon_hw_i2c; |
Alex Deucher | d42dd57 | 2011-01-12 20:05:11 -0500 | [diff] [blame] | 95 | extern int radeon_pcie_gen2; |
Alex Deucher | a18cee1 | 2011-11-01 14:20:30 -0400 | [diff] [blame] | 96 | extern int radeon_msi; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 97 | |
| 98 | /* |
| 99 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
| 100 | * symbol; |
| 101 | */ |
| 102 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 103 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 104 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 105 | #define RADEON_IB_POOL_SIZE 16 |
Michael Witten | c245cb9 | 2011-09-16 20:45:30 +0000 | [diff] [blame] | 106 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 107 | #define RADEONFB_CONN_LIMIT 4 |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 108 | #define RADEON_BIOS_NUM_SCRATCH 8 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 109 | |
Alex Deucher | 1b37078 | 2011-11-17 20:13:28 -0500 | [diff] [blame] | 110 | /* max number of rings */ |
| 111 | #define RADEON_NUM_RINGS 3 |
| 112 | |
| 113 | /* internal ring indices */ |
| 114 | /* r1xx+ has gfx CP ring */ |
| 115 | #define RADEON_RING_TYPE_GFX_INDEX 0 |
| 116 | |
| 117 | /* cayman has 2 compute CP rings */ |
| 118 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
| 119 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 |
| 120 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 121 | /* hardcode those limit for now */ |
| 122 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
| 123 | #define RADEON_IB_VM_MAX_SIZE (64 << 10) |
| 124 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 125 | /* |
| 126 | * Errata workarounds. |
| 127 | */ |
| 128 | enum radeon_pll_errata { |
| 129 | CHIP_ERRATA_R300_CG = 0x00000001, |
| 130 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
| 131 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
| 132 | }; |
| 133 | |
| 134 | |
| 135 | struct radeon_device; |
| 136 | |
| 137 | |
| 138 | /* |
| 139 | * BIOS. |
| 140 | */ |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 141 | #define ATRM_BIOS_PAGE 4096 |
| 142 | |
Dave Airlie | 8edb381 | 2010-03-01 21:50:01 +1100 | [diff] [blame] | 143 | #if defined(CONFIG_VGA_SWITCHEROO) |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 144 | bool radeon_atrm_supported(struct pci_dev *pdev); |
| 145 | int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len); |
Dave Airlie | 8edb381 | 2010-03-01 21:50:01 +1100 | [diff] [blame] | 146 | #else |
| 147 | static inline bool radeon_atrm_supported(struct pci_dev *pdev) |
| 148 | { |
| 149 | return false; |
| 150 | } |
| 151 | |
| 152 | static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){ |
| 153 | return -EINVAL; |
| 154 | } |
| 155 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 156 | bool radeon_get_bios(struct radeon_device *rdev); |
| 157 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 158 | |
| 159 | /* |
Jerome Glisse | 9fc04b5 | 2012-01-23 11:52:15 -0500 | [diff] [blame] | 160 | * Mutex which allows recursive locking from the same process. |
| 161 | */ |
| 162 | struct radeon_mutex { |
| 163 | struct mutex mutex; |
| 164 | struct task_struct *owner; |
| 165 | int level; |
| 166 | }; |
| 167 | |
| 168 | static inline void radeon_mutex_init(struct radeon_mutex *mutex) |
| 169 | { |
| 170 | mutex_init(&mutex->mutex); |
| 171 | mutex->owner = NULL; |
| 172 | mutex->level = 0; |
| 173 | } |
| 174 | |
| 175 | static inline void radeon_mutex_lock(struct radeon_mutex *mutex) |
| 176 | { |
| 177 | if (mutex_trylock(&mutex->mutex)) { |
| 178 | /* The mutex was unlocked before, so it's ours now */ |
| 179 | mutex->owner = current; |
| 180 | } else if (mutex->owner != current) { |
| 181 | /* Another process locked the mutex, take it */ |
| 182 | mutex_lock(&mutex->mutex); |
| 183 | mutex->owner = current; |
| 184 | } |
| 185 | /* Otherwise the mutex was already locked by this process */ |
| 186 | |
| 187 | mutex->level++; |
| 188 | } |
| 189 | |
| 190 | static inline void radeon_mutex_unlock(struct radeon_mutex *mutex) |
| 191 | { |
| 192 | if (--mutex->level > 0) |
| 193 | return; |
| 194 | |
| 195 | mutex->owner = NULL; |
| 196 | mutex_unlock(&mutex->mutex); |
| 197 | } |
| 198 | |
| 199 | |
| 200 | /* |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 201 | * Dummy page |
| 202 | */ |
| 203 | struct radeon_dummy_page { |
| 204 | struct page *page; |
| 205 | dma_addr_t addr; |
| 206 | }; |
| 207 | int radeon_dummy_page_init(struct radeon_device *rdev); |
| 208 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
| 209 | |
| 210 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 211 | /* |
| 212 | * Clocks |
| 213 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 214 | struct radeon_clock { |
| 215 | struct radeon_pll p1pll; |
| 216 | struct radeon_pll p2pll; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 217 | struct radeon_pll dcpll; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 218 | struct radeon_pll spll; |
| 219 | struct radeon_pll mpll; |
| 220 | /* 10 Khz units */ |
| 221 | uint32_t default_mclk; |
| 222 | uint32_t default_sclk; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 223 | uint32_t default_dispclk; |
| 224 | uint32_t dp_extclk; |
Alex Deucher | b20f9be | 2011-06-08 13:01:11 -0400 | [diff] [blame] | 225 | uint32_t max_pixel_clock; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 226 | }; |
| 227 | |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 228 | /* |
| 229 | * Power management |
| 230 | */ |
| 231 | int radeon_pm_init(struct radeon_device *rdev); |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 232 | void radeon_pm_fini(struct radeon_device *rdev); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 233 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 234 | void radeon_pm_suspend(struct radeon_device *rdev); |
| 235 | void radeon_pm_resume(struct radeon_device *rdev); |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 236 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
| 237 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
Alex Deucher | 8a83ec5 | 2011-04-12 14:49:23 -0400 | [diff] [blame] | 238 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
Alex Deucher | ee4017f | 2011-06-23 12:19:32 -0400 | [diff] [blame] | 239 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage); |
Alex Deucher | f892034 | 2010-06-30 12:02:03 -0400 | [diff] [blame] | 240 | void rs690_pm_info(struct radeon_device *rdev); |
Alex Deucher | 20d391d | 2011-02-01 16:12:34 -0500 | [diff] [blame] | 241 | extern int rv6xx_get_temp(struct radeon_device *rdev); |
| 242 | extern int rv770_get_temp(struct radeon_device *rdev); |
| 243 | extern int evergreen_get_temp(struct radeon_device *rdev); |
| 244 | extern int sumo_get_temp(struct radeon_device *rdev); |
Jerome Glisse | 285484e | 2011-12-16 17:03:42 -0500 | [diff] [blame] | 245 | extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
| 246 | unsigned *bankh, unsigned *mtaspect, |
| 247 | unsigned *tile_split); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 248 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 249 | /* |
| 250 | * Fences. |
| 251 | */ |
| 252 | struct radeon_fence_driver { |
| 253 | uint32_t scratch_reg; |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 254 | uint64_t gpu_addr; |
| 255 | volatile uint32_t *cpu_addr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 256 | atomic_t seq; |
| 257 | uint32_t last_seq; |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 258 | unsigned long last_jiffies; |
| 259 | unsigned long last_timeout; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 260 | wait_queue_head_t queue; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 261 | struct list_head created; |
Christian König | 851a6bd | 2011-10-24 15:05:29 +0200 | [diff] [blame] | 262 | struct list_head emitted; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 263 | struct list_head signaled; |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 264 | bool initialized; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 265 | }; |
| 266 | |
| 267 | struct radeon_fence { |
| 268 | struct radeon_device *rdev; |
| 269 | struct kref kref; |
| 270 | struct list_head list; |
| 271 | /* protected by radeon_fence.lock */ |
| 272 | uint32_t seq; |
Christian König | 851a6bd | 2011-10-24 15:05:29 +0200 | [diff] [blame] | 273 | bool emitted; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 274 | bool signaled; |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 275 | /* RB, DMA, etc. */ |
| 276 | int ring; |
Christian König | 93504fc | 2012-01-05 22:11:06 -0500 | [diff] [blame] | 277 | struct radeon_semaphore *semaphore; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 278 | }; |
| 279 | |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 280 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); |
| 281 | int radeon_fence_driver_init(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 282 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 283 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 284 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 285 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 286 | bool radeon_fence_signaled(struct radeon_fence *fence); |
| 287 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 288 | int radeon_fence_wait_next(struct radeon_device *rdev, int ring); |
| 289 | int radeon_fence_wait_last(struct radeon_device *rdev, int ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 290 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
| 291 | void radeon_fence_unref(struct radeon_fence **fence); |
Christian König | 47492a2 | 2011-10-20 12:38:09 +0200 | [diff] [blame] | 292 | int radeon_fence_count_emitted(struct radeon_device *rdev, int ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 293 | |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 294 | /* |
| 295 | * Tiling registers |
| 296 | */ |
| 297 | struct radeon_surface_reg { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 298 | struct radeon_bo *bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 299 | }; |
| 300 | |
| 301 | #define RADEON_GEM_MAX_SURFACES 8 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 302 | |
| 303 | /* |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 304 | * TTM. |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 305 | */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 306 | struct radeon_mman { |
| 307 | struct ttm_bo_global_ref bo_global_ref; |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 308 | struct drm_global_reference mem_global_ref; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 309 | struct ttm_bo_device bdev; |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 310 | bool mem_global_referenced; |
| 311 | bool initialized; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 312 | }; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 313 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 314 | /* bo virtual address in a specific vm */ |
| 315 | struct radeon_bo_va { |
| 316 | /* bo list is protected by bo being reserved */ |
| 317 | struct list_head bo_list; |
| 318 | /* vm list is protected by vm mutex */ |
| 319 | struct list_head vm_list; |
| 320 | /* constant after initialization */ |
| 321 | struct radeon_vm *vm; |
| 322 | struct radeon_bo *bo; |
| 323 | uint64_t soffset; |
| 324 | uint64_t eoffset; |
| 325 | uint32_t flags; |
| 326 | bool valid; |
| 327 | }; |
| 328 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 329 | struct radeon_bo { |
| 330 | /* Protected by gem.mutex */ |
| 331 | struct list_head list; |
| 332 | /* Protected by tbo.reserved */ |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 333 | u32 placements[3]; |
| 334 | struct ttm_placement placement; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 335 | struct ttm_buffer_object tbo; |
| 336 | struct ttm_bo_kmap_obj kmap; |
| 337 | unsigned pin_count; |
| 338 | void *kptr; |
| 339 | u32 tiling_flags; |
| 340 | u32 pitch; |
| 341 | int surface_reg; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 342 | /* list of all virtual address to which this bo |
| 343 | * is associated to |
| 344 | */ |
| 345 | struct list_head va; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 346 | /* Constant after initialization */ |
| 347 | struct radeon_device *rdev; |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 348 | struct drm_gem_object gem_base; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 349 | }; |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 350 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 351 | |
| 352 | struct radeon_bo_list { |
Thomas Hellstrom | 147666f | 2010-11-17 12:38:32 +0000 | [diff] [blame] | 353 | struct ttm_validate_buffer tv; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 354 | struct radeon_bo *bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 355 | uint64_t gpu_offset; |
| 356 | unsigned rdomain; |
| 357 | unsigned wdomain; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 358 | u32 tiling_flags; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 359 | }; |
| 360 | |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 361 | /* sub-allocation manager, it has to be protected by another lock. |
| 362 | * By conception this is an helper for other part of the driver |
| 363 | * like the indirect buffer or semaphore, which both have their |
| 364 | * locking. |
| 365 | * |
| 366 | * Principe is simple, we keep a list of sub allocation in offset |
| 367 | * order (first entry has offset == 0, last entry has the highest |
| 368 | * offset). |
| 369 | * |
| 370 | * When allocating new object we first check if there is room at |
| 371 | * the end total_size - (last_object_offset + last_object_size) >= |
| 372 | * alloc_size. If so we allocate new object there. |
| 373 | * |
| 374 | * When there is not enough room at the end, we start waiting for |
| 375 | * each sub object until we reach object_offset+object_size >= |
| 376 | * alloc_size, this object then become the sub object we return. |
| 377 | * |
| 378 | * Alignment can't be bigger than page size. |
| 379 | * |
| 380 | * Hole are not considered for allocation to keep things simple. |
| 381 | * Assumption is that there won't be hole (all object on same |
| 382 | * alignment). |
| 383 | */ |
| 384 | struct radeon_sa_manager { |
| 385 | struct radeon_bo *bo; |
| 386 | struct list_head sa_bo; |
| 387 | unsigned size; |
| 388 | uint64_t gpu_addr; |
| 389 | void *cpu_ptr; |
| 390 | uint32_t domain; |
| 391 | }; |
| 392 | |
| 393 | struct radeon_sa_bo; |
| 394 | |
| 395 | /* sub-allocation buffer */ |
| 396 | struct radeon_sa_bo { |
| 397 | struct list_head list; |
| 398 | struct radeon_sa_manager *manager; |
| 399 | unsigned offset; |
| 400 | unsigned size; |
| 401 | }; |
| 402 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 403 | /* |
| 404 | * GEM objects. |
| 405 | */ |
| 406 | struct radeon_gem { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 407 | struct mutex mutex; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 408 | struct list_head objects; |
| 409 | }; |
| 410 | |
| 411 | int radeon_gem_init(struct radeon_device *rdev); |
| 412 | void radeon_gem_fini(struct radeon_device *rdev); |
| 413 | int radeon_gem_object_create(struct radeon_device *rdev, int size, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 414 | int alignment, int initial_domain, |
| 415 | bool discardable, bool kernel, |
| 416 | struct drm_gem_object **obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 417 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
| 418 | uint64_t *gpu_addr); |
| 419 | void radeon_gem_object_unpin(struct drm_gem_object *obj); |
| 420 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 421 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
| 422 | struct drm_device *dev, |
| 423 | struct drm_mode_create_dumb *args); |
| 424 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
| 425 | struct drm_device *dev, |
| 426 | uint32_t handle, uint64_t *offset_p); |
| 427 | int radeon_mode_dumb_destroy(struct drm_file *file_priv, |
| 428 | struct drm_device *dev, |
| 429 | uint32_t handle); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 430 | |
| 431 | /* |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 432 | * Semaphores. |
| 433 | */ |
| 434 | struct radeon_ring; |
| 435 | |
| 436 | #define RADEON_SEMAPHORE_BO_SIZE 256 |
| 437 | |
| 438 | struct radeon_semaphore_driver { |
| 439 | rwlock_t lock; |
| 440 | struct list_head bo; |
| 441 | }; |
| 442 | |
| 443 | struct radeon_semaphore_bo; |
| 444 | |
| 445 | /* everything here is constant */ |
| 446 | struct radeon_semaphore { |
| 447 | struct list_head list; |
| 448 | uint64_t gpu_addr; |
| 449 | uint32_t *cpu_ptr; |
| 450 | struct radeon_semaphore_bo *bo; |
| 451 | }; |
| 452 | |
| 453 | struct radeon_semaphore_bo { |
| 454 | struct list_head list; |
| 455 | struct radeon_ib *ib; |
| 456 | struct list_head free; |
| 457 | struct radeon_semaphore semaphores[RADEON_SEMAPHORE_BO_SIZE/8]; |
| 458 | unsigned nused; |
| 459 | }; |
| 460 | |
| 461 | void radeon_semaphore_driver_fini(struct radeon_device *rdev); |
| 462 | int radeon_semaphore_create(struct radeon_device *rdev, |
| 463 | struct radeon_semaphore **semaphore); |
| 464 | void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, |
| 465 | struct radeon_semaphore *semaphore); |
| 466 | void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, |
| 467 | struct radeon_semaphore *semaphore); |
| 468 | void radeon_semaphore_free(struct radeon_device *rdev, |
| 469 | struct radeon_semaphore *semaphore); |
| 470 | |
| 471 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 472 | * GART structures, functions & helpers |
| 473 | */ |
| 474 | struct radeon_mc; |
| 475 | |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 476 | #define RADEON_GPU_PAGE_SIZE 4096 |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 477 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
Alex Deucher | 003cefe | 2011-09-16 12:04:08 -0400 | [diff] [blame] | 478 | #define RADEON_GPU_PAGE_SHIFT 12 |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 479 | #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 480 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 481 | struct radeon_gart { |
| 482 | dma_addr_t table_addr; |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 483 | struct radeon_bo *robj; |
| 484 | void *ptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 485 | unsigned num_gpu_pages; |
| 486 | unsigned num_cpu_pages; |
| 487 | unsigned table_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 488 | struct page **pages; |
| 489 | dma_addr_t *pages_addr; |
| 490 | bool ready; |
| 491 | }; |
| 492 | |
| 493 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
| 494 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
| 495 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
| 496 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 497 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
| 498 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 499 | int radeon_gart_init(struct radeon_device *rdev); |
| 500 | void radeon_gart_fini(struct radeon_device *rdev); |
| 501 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
| 502 | int pages); |
| 503 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
Konrad Rzeszutek Wilk | c39d351 | 2010-12-02 11:04:29 -0500 | [diff] [blame] | 504 | int pages, struct page **pagelist, |
| 505 | dma_addr_t *dma_addr); |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 506 | void radeon_gart_restore(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 507 | |
| 508 | |
| 509 | /* |
| 510 | * GPU MC structures, functions & helpers |
| 511 | */ |
| 512 | struct radeon_mc { |
| 513 | resource_size_t aper_size; |
| 514 | resource_size_t aper_base; |
| 515 | resource_size_t agp_base; |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 516 | /* for some chips with <= 32MB we need to lie |
| 517 | * about vram size near mc fb location */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 518 | u64 mc_vram_size; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 519 | u64 visible_vram_size; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 520 | u64 gtt_size; |
| 521 | u64 gtt_start; |
| 522 | u64 gtt_end; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 523 | u64 vram_start; |
| 524 | u64 vram_end; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 525 | unsigned vram_width; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 526 | u64 real_vram_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 527 | int vram_mtrr; |
| 528 | bool vram_is_ddr; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 529 | bool igp_sideport_enabled; |
Alex Deucher | 8d369bb | 2010-07-15 10:51:10 -0400 | [diff] [blame] | 530 | u64 gtt_base_align; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 531 | }; |
| 532 | |
Alex Deucher | 06b6476 | 2010-01-05 11:27:29 -0500 | [diff] [blame] | 533 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
| 534 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 535 | |
| 536 | /* |
| 537 | * GPU scratch registers structures, functions & helpers |
| 538 | */ |
| 539 | struct radeon_scratch { |
| 540 | unsigned num_reg; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 541 | uint32_t reg_base; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 542 | bool free[32]; |
| 543 | uint32_t reg[32]; |
| 544 | }; |
| 545 | |
| 546 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
| 547 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
| 548 | |
| 549 | |
| 550 | /* |
| 551 | * IRQS. |
| 552 | */ |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 553 | |
| 554 | struct radeon_unpin_work { |
| 555 | struct work_struct work; |
| 556 | struct radeon_device *rdev; |
| 557 | int crtc_id; |
| 558 | struct radeon_fence *fence; |
| 559 | struct drm_pending_vblank_event *event; |
| 560 | struct radeon_bo *old_rbo; |
| 561 | u64 new_crtc_base; |
| 562 | }; |
| 563 | |
| 564 | struct r500_irq_stat_regs { |
| 565 | u32 disp_int; |
| 566 | }; |
| 567 | |
| 568 | struct r600_irq_stat_regs { |
| 569 | u32 disp_int; |
| 570 | u32 disp_int_cont; |
| 571 | u32 disp_int_cont2; |
| 572 | u32 d1grph_int; |
| 573 | u32 d2grph_int; |
| 574 | }; |
| 575 | |
| 576 | struct evergreen_irq_stat_regs { |
| 577 | u32 disp_int; |
| 578 | u32 disp_int_cont; |
| 579 | u32 disp_int_cont2; |
| 580 | u32 disp_int_cont3; |
| 581 | u32 disp_int_cont4; |
| 582 | u32 disp_int_cont5; |
| 583 | u32 d1grph_int; |
| 584 | u32 d2grph_int; |
| 585 | u32 d3grph_int; |
| 586 | u32 d4grph_int; |
| 587 | u32 d5grph_int; |
| 588 | u32 d6grph_int; |
| 589 | }; |
| 590 | |
| 591 | union radeon_irq_stat_regs { |
| 592 | struct r500_irq_stat_regs r500; |
| 593 | struct r600_irq_stat_regs r600; |
| 594 | struct evergreen_irq_stat_regs evergreen; |
| 595 | }; |
| 596 | |
Ilija Hadzic | 54bd5206 | 2011-10-26 15:43:58 -0400 | [diff] [blame] | 597 | #define RADEON_MAX_HPD_PINS 6 |
| 598 | #define RADEON_MAX_CRTCS 6 |
| 599 | #define RADEON_MAX_HDMI_BLOCKS 2 |
| 600 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 601 | struct radeon_irq { |
| 602 | bool installed; |
Alex Deucher | 1b37078 | 2011-11-17 20:13:28 -0500 | [diff] [blame] | 603 | bool sw_int[RADEON_NUM_RINGS]; |
Ilija Hadzic | 54bd5206 | 2011-10-26 15:43:58 -0400 | [diff] [blame] | 604 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
| 605 | bool pflip[RADEON_MAX_CRTCS]; |
Rafał Miłecki | 73a6d3f | 2010-01-08 00:22:47 +0100 | [diff] [blame] | 606 | wait_queue_head_t vblank_queue; |
Ilija Hadzic | 54bd5206 | 2011-10-26 15:43:58 -0400 | [diff] [blame] | 607 | bool hpd[RADEON_MAX_HPD_PINS]; |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 608 | bool gui_idle; |
| 609 | bool gui_idle_acked; |
| 610 | wait_queue_head_t idle_queue; |
Ilija Hadzic | 54bd5206 | 2011-10-26 15:43:58 -0400 | [diff] [blame] | 611 | bool hdmi[RADEON_MAX_HDMI_BLOCKS]; |
Dave Airlie | 1614f8b | 2009-12-01 16:04:56 +1000 | [diff] [blame] | 612 | spinlock_t sw_lock; |
Alex Deucher | 1b37078 | 2011-11-17 20:13:28 -0500 | [diff] [blame] | 613 | int sw_refcount[RADEON_NUM_RINGS]; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 614 | union radeon_irq_stat_regs stat_regs; |
Ilija Hadzic | 54bd5206 | 2011-10-26 15:43:58 -0400 | [diff] [blame] | 615 | spinlock_t pflip_lock[RADEON_MAX_CRTCS]; |
| 616 | int pflip_refcount[RADEON_MAX_CRTCS]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 617 | }; |
| 618 | |
| 619 | int radeon_irq_kms_init(struct radeon_device *rdev); |
| 620 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
Alex Deucher | 1b37078 | 2011-11-17 20:13:28 -0500 | [diff] [blame] | 621 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); |
| 622 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 623 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
| 624 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 625 | |
| 626 | /* |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 627 | * CP & rings. |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 628 | */ |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 629 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 630 | struct radeon_ib { |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 631 | struct radeon_sa_bo sa_bo; |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 632 | unsigned idx; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 633 | uint32_t length_dw; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 634 | uint64_t gpu_addr; |
| 635 | uint32_t *ptr; |
| 636 | struct radeon_fence *fence; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 637 | unsigned vm_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 638 | }; |
| 639 | |
Dave Airlie | ecb114a | 2009-09-15 11:12:56 +1000 | [diff] [blame] | 640 | /* |
| 641 | * locking - |
| 642 | * mutex protects scheduled_ibs, ready, alloc_bm |
| 643 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 644 | struct radeon_ib_pool { |
Jerome Glisse | 9fc04b5 | 2012-01-23 11:52:15 -0500 | [diff] [blame] | 645 | struct radeon_mutex mutex; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 646 | struct radeon_sa_manager sa_manager; |
| 647 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
| 648 | bool ready; |
| 649 | unsigned head_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 650 | }; |
| 651 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 652 | struct radeon_ring { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 653 | struct radeon_bo *ring_obj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 654 | volatile uint32_t *ring; |
| 655 | unsigned rptr; |
Christian König | 5596a9d | 2011-10-13 12:48:45 +0200 | [diff] [blame] | 656 | unsigned rptr_offs; |
| 657 | unsigned rptr_reg; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 658 | unsigned wptr; |
| 659 | unsigned wptr_old; |
Christian König | 5596a9d | 2011-10-13 12:48:45 +0200 | [diff] [blame] | 660 | unsigned wptr_reg; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 661 | unsigned ring_size; |
| 662 | unsigned ring_free_dw; |
| 663 | int count_dw; |
| 664 | uint64_t gpu_addr; |
| 665 | uint32_t align_mask; |
| 666 | uint32_t ptr_mask; |
| 667 | struct mutex mutex; |
| 668 | bool ready; |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 669 | u32 ptr_reg_shift; |
| 670 | u32 ptr_reg_mask; |
| 671 | u32 nop; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 672 | }; |
| 673 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 674 | /* |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 675 | * VM |
| 676 | */ |
| 677 | struct radeon_vm { |
| 678 | struct list_head list; |
| 679 | struct list_head va; |
| 680 | int id; |
| 681 | unsigned last_pfn; |
| 682 | u64 pt_gpu_addr; |
| 683 | u64 *pt; |
| 684 | struct radeon_sa_bo sa_bo; |
| 685 | struct mutex mutex; |
| 686 | /* last fence for cs using this vm */ |
| 687 | struct radeon_fence *fence; |
| 688 | }; |
| 689 | |
| 690 | struct radeon_vm_funcs { |
| 691 | int (*init)(struct radeon_device *rdev); |
| 692 | void (*fini)(struct radeon_device *rdev); |
| 693 | /* cs mutex must be lock for schedule_ib */ |
| 694 | int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id); |
| 695 | void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm); |
| 696 | void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm); |
| 697 | uint32_t (*page_flags)(struct radeon_device *rdev, |
| 698 | struct radeon_vm *vm, |
| 699 | uint32_t flags); |
| 700 | void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm, |
| 701 | unsigned pfn, uint64_t addr, uint32_t flags); |
| 702 | }; |
| 703 | |
| 704 | struct radeon_vm_manager { |
| 705 | struct list_head lru_vm; |
| 706 | uint32_t use_bitmap; |
| 707 | struct radeon_sa_manager sa_manager; |
| 708 | uint32_t max_pfn; |
| 709 | /* fields constant after init */ |
| 710 | const struct radeon_vm_funcs *funcs; |
| 711 | /* number of VMIDs */ |
| 712 | unsigned nvm; |
| 713 | /* vram base address for page table entry */ |
| 714 | u64 vram_base_offset; |
Alex Deucher | 67e915e | 2012-01-06 09:38:15 -0500 | [diff] [blame] | 715 | /* is vm enabled? */ |
| 716 | bool enabled; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 717 | }; |
| 718 | |
| 719 | /* |
| 720 | * file private structure |
| 721 | */ |
| 722 | struct radeon_fpriv { |
| 723 | struct radeon_vm vm; |
| 724 | }; |
| 725 | |
| 726 | /* |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 727 | * R6xx+ IH ring |
| 728 | */ |
| 729 | struct r600_ih { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 730 | struct radeon_bo *ring_obj; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 731 | volatile uint32_t *ring; |
| 732 | unsigned rptr; |
Christian König | bf85279 | 2011-10-13 13:19:22 +0200 | [diff] [blame] | 733 | unsigned rptr_offs; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 734 | unsigned wptr; |
| 735 | unsigned wptr_old; |
| 736 | unsigned ring_size; |
| 737 | uint64_t gpu_addr; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 738 | uint32_t ptr_mask; |
| 739 | spinlock_t lock; |
| 740 | bool enabled; |
| 741 | }; |
| 742 | |
Ilija Hadzic | 8eec9d6 | 2011-10-12 23:29:40 -0400 | [diff] [blame] | 743 | struct r600_blit_cp_primitives { |
| 744 | void (*set_render_target)(struct radeon_device *rdev, int format, |
| 745 | int w, int h, u64 gpu_addr); |
| 746 | void (*cp_set_surface_sync)(struct radeon_device *rdev, |
| 747 | u32 sync_type, u32 size, |
| 748 | u64 mc_addr); |
| 749 | void (*set_shaders)(struct radeon_device *rdev); |
| 750 | void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); |
| 751 | void (*set_tex_resource)(struct radeon_device *rdev, |
| 752 | int format, int w, int h, int pitch, |
Alex Deucher | 9bb7703 | 2011-10-22 10:07:09 -0400 | [diff] [blame] | 753 | u64 gpu_addr, u32 size); |
Ilija Hadzic | 8eec9d6 | 2011-10-12 23:29:40 -0400 | [diff] [blame] | 754 | void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, |
| 755 | int x2, int y2); |
| 756 | void (*draw_auto)(struct radeon_device *rdev); |
| 757 | void (*set_default_state)(struct radeon_device *rdev); |
| 758 | }; |
| 759 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 760 | struct r600_blit { |
Jerome Glisse | ff82f05 | 2010-01-22 15:19:00 +0100 | [diff] [blame] | 761 | struct mutex mutex; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 762 | struct radeon_bo *shader_obj; |
Ilija Hadzic | 8eec9d6 | 2011-10-12 23:29:40 -0400 | [diff] [blame] | 763 | struct r600_blit_cp_primitives primitives; |
| 764 | int max_dim; |
| 765 | int ring_size_common; |
| 766 | int ring_size_per_loop; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 767 | u64 shader_gpu_addr; |
| 768 | u32 vs_offset, ps_offset; |
| 769 | u32 state_offset; |
| 770 | u32 state_len; |
| 771 | u32 vb_used, vb_total; |
| 772 | struct radeon_ib *vb_ib; |
| 773 | }; |
| 774 | |
Alex Deucher | 6ddddfe | 2011-10-14 10:51:22 -0400 | [diff] [blame] | 775 | void r600_blit_suspend(struct radeon_device *rdev); |
| 776 | |
Jerome Glisse | 69e130a | 2011-12-21 12:13:46 -0500 | [diff] [blame] | 777 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
| 778 | struct radeon_ib **ib, unsigned size); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 779 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 780 | bool radeon_ib_try_free(struct radeon_device *rdev, struct radeon_ib *ib); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 781 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); |
| 782 | int radeon_ib_pool_init(struct radeon_device *rdev); |
| 783 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 784 | int radeon_ib_pool_start(struct radeon_device *rdev); |
| 785 | int radeon_ib_pool_suspend(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 786 | int radeon_ib_test(struct radeon_device *rdev); |
| 787 | /* Ring access between begin & end cannot sleep */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 788 | int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *cp); |
| 789 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
| 790 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
| 791 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
| 792 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); |
| 793 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); |
| 794 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
| 795 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
| 796 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 797 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
| 798 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 799 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 800 | |
| 801 | |
| 802 | /* |
| 803 | * CS. |
| 804 | */ |
| 805 | struct radeon_cs_reloc { |
| 806 | struct drm_gem_object *gobj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 807 | struct radeon_bo *robj; |
| 808 | struct radeon_bo_list lobj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 809 | uint32_t handle; |
| 810 | uint32_t flags; |
| 811 | }; |
| 812 | |
| 813 | struct radeon_cs_chunk { |
| 814 | uint32_t chunk_id; |
| 815 | uint32_t length_dw; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 816 | int kpage_idx[2]; |
| 817 | uint32_t *kpage[2]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 818 | uint32_t *kdata; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 819 | void __user *user_ptr; |
| 820 | int last_copied_page; |
| 821 | int last_page_index; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 822 | }; |
| 823 | |
| 824 | struct radeon_cs_parser { |
Jerome Glisse | c8c15ff | 2010-01-18 13:01:36 +0100 | [diff] [blame] | 825 | struct device *dev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 826 | struct radeon_device *rdev; |
| 827 | struct drm_file *filp; |
| 828 | /* chunks */ |
| 829 | unsigned nchunks; |
| 830 | struct radeon_cs_chunk *chunks; |
| 831 | uint64_t *chunks_array; |
| 832 | /* IB */ |
| 833 | unsigned idx; |
| 834 | /* relocations */ |
| 835 | unsigned nrelocs; |
| 836 | struct radeon_cs_reloc *relocs; |
| 837 | struct radeon_cs_reloc **relocs_ptr; |
| 838 | struct list_head validated; |
Christian König | 93504fc | 2012-01-05 22:11:06 -0500 | [diff] [blame] | 839 | bool sync_to_ring[RADEON_NUM_RINGS]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 840 | /* indices of various chunks */ |
| 841 | int chunk_ib_idx; |
| 842 | int chunk_relocs_idx; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 843 | int chunk_flags_idx; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 844 | struct radeon_ib *ib; |
| 845 | void *track; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 846 | unsigned family; |
Marek Olšák | e70f224 | 2011-10-25 01:38:45 +0200 | [diff] [blame] | 847 | int parser_error; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 848 | u32 cs_flags; |
| 849 | u32 ring; |
| 850 | s32 priority; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 851 | }; |
| 852 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 853 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
| 854 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 855 | extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 856 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 857 | struct radeon_cs_packet { |
| 858 | unsigned idx; |
| 859 | unsigned type; |
| 860 | unsigned reg; |
| 861 | unsigned opcode; |
| 862 | int count; |
| 863 | unsigned one_reg_wr; |
| 864 | }; |
| 865 | |
| 866 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
| 867 | struct radeon_cs_packet *pkt, |
| 868 | unsigned idx, unsigned reg); |
| 869 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
| 870 | struct radeon_cs_packet *pkt); |
| 871 | |
| 872 | |
| 873 | /* |
| 874 | * AGP |
| 875 | */ |
| 876 | int radeon_agp_init(struct radeon_device *rdev); |
Dave Airlie | 0ebf171 | 2009-11-05 15:39:10 +1000 | [diff] [blame] | 877 | void radeon_agp_resume(struct radeon_device *rdev); |
Jerome Glisse | 10b0612 | 2010-05-21 18:48:54 +0200 | [diff] [blame] | 878 | void radeon_agp_suspend(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 879 | void radeon_agp_fini(struct radeon_device *rdev); |
| 880 | |
| 881 | |
| 882 | /* |
| 883 | * Writeback |
| 884 | */ |
| 885 | struct radeon_wb { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 886 | struct radeon_bo *wb_obj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 887 | volatile uint32_t *wb; |
| 888 | uint64_t gpu_addr; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 889 | bool enabled; |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 890 | bool use_event; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 891 | }; |
| 892 | |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 893 | #define RADEON_WB_SCRATCH_OFFSET 0 |
| 894 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
Alex Deucher | 0c88a02 | 2011-03-02 20:07:31 -0500 | [diff] [blame] | 895 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
| 896 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 897 | #define R600_WB_IH_WPTR_OFFSET 2048 |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 898 | #define R600_WB_EVENT_OFFSET 3072 |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 899 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 900 | /** |
| 901 | * struct radeon_pm - power management datas |
| 902 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
| 903 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
| 904 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
| 905 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
| 906 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
| 907 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
| 908 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
| 909 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
| 910 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 911 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 912 | * @needed_bandwidth: current bandwidth needs |
| 913 | * |
| 914 | * It keeps track of various data needed to take powermanagement decision. |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 915 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 916 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
| 917 | * (type of memory, bus size, efficiency, ...) |
| 918 | */ |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 919 | |
| 920 | enum radeon_pm_method { |
| 921 | PM_METHOD_PROFILE, |
| 922 | PM_METHOD_DYNPM, |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 923 | }; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 924 | |
| 925 | enum radeon_dynpm_state { |
| 926 | DYNPM_STATE_DISABLED, |
| 927 | DYNPM_STATE_MINIMUM, |
| 928 | DYNPM_STATE_PAUSED, |
Rafael J. Wysocki | 3f53eb6 | 2010-06-17 23:02:27 +0000 | [diff] [blame] | 929 | DYNPM_STATE_ACTIVE, |
| 930 | DYNPM_STATE_SUSPENDED, |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 931 | }; |
| 932 | enum radeon_dynpm_action { |
| 933 | DYNPM_ACTION_NONE, |
| 934 | DYNPM_ACTION_MINIMUM, |
| 935 | DYNPM_ACTION_DOWNCLOCK, |
| 936 | DYNPM_ACTION_UPCLOCK, |
| 937 | DYNPM_ACTION_DEFAULT |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 938 | }; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 939 | |
| 940 | enum radeon_voltage_type { |
| 941 | VOLTAGE_NONE = 0, |
| 942 | VOLTAGE_GPIO, |
| 943 | VOLTAGE_VDDC, |
| 944 | VOLTAGE_SW |
| 945 | }; |
| 946 | |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 947 | enum radeon_pm_state_type { |
| 948 | POWER_STATE_TYPE_DEFAULT, |
| 949 | POWER_STATE_TYPE_POWERSAVE, |
| 950 | POWER_STATE_TYPE_BATTERY, |
| 951 | POWER_STATE_TYPE_BALANCED, |
| 952 | POWER_STATE_TYPE_PERFORMANCE, |
| 953 | }; |
| 954 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 955 | enum radeon_pm_profile_type { |
| 956 | PM_PROFILE_DEFAULT, |
| 957 | PM_PROFILE_AUTO, |
| 958 | PM_PROFILE_LOW, |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 959 | PM_PROFILE_MID, |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 960 | PM_PROFILE_HIGH, |
| 961 | }; |
| 962 | |
| 963 | #define PM_PROFILE_DEFAULT_IDX 0 |
| 964 | #define PM_PROFILE_LOW_SH_IDX 1 |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 965 | #define PM_PROFILE_MID_SH_IDX 2 |
| 966 | #define PM_PROFILE_HIGH_SH_IDX 3 |
| 967 | #define PM_PROFILE_LOW_MH_IDX 4 |
| 968 | #define PM_PROFILE_MID_MH_IDX 5 |
| 969 | #define PM_PROFILE_HIGH_MH_IDX 6 |
| 970 | #define PM_PROFILE_MAX 7 |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 971 | |
| 972 | struct radeon_pm_profile { |
| 973 | int dpms_off_ps_idx; |
| 974 | int dpms_on_ps_idx; |
| 975 | int dpms_off_cm_idx; |
| 976 | int dpms_on_cm_idx; |
Alex Deucher | 516d0e4 | 2009-12-23 14:28:05 -0500 | [diff] [blame] | 977 | }; |
| 978 | |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 979 | enum radeon_int_thermal_type { |
| 980 | THERMAL_TYPE_NONE, |
| 981 | THERMAL_TYPE_RV6XX, |
| 982 | THERMAL_TYPE_RV770, |
| 983 | THERMAL_TYPE_EVERGREEN, |
Alex Deucher | e33df25 | 2010-11-22 17:56:32 -0500 | [diff] [blame] | 984 | THERMAL_TYPE_SUMO, |
Alex Deucher | 4fddba1 | 2011-01-06 21:19:22 -0500 | [diff] [blame] | 985 | THERMAL_TYPE_NI, |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 986 | }; |
| 987 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 988 | struct radeon_voltage { |
| 989 | enum radeon_voltage_type type; |
| 990 | /* gpio voltage */ |
| 991 | struct radeon_gpio_rec gpio; |
| 992 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
| 993 | bool active_high; /* voltage drop is active when bit is high */ |
| 994 | /* VDDC voltage */ |
| 995 | u8 vddc_id; /* index into vddc voltage table */ |
| 996 | u8 vddci_id; /* index into vddci voltage table */ |
| 997 | bool vddci_enabled; |
| 998 | /* r6xx+ sw */ |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 999 | u16 voltage; |
| 1000 | /* evergreen+ vddci */ |
| 1001 | u16 vddci; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1002 | }; |
| 1003 | |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 1004 | /* clock mode flags */ |
| 1005 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) |
| 1006 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1007 | struct radeon_pm_clock_info { |
| 1008 | /* memory clock */ |
| 1009 | u32 mclk; |
| 1010 | /* engine clock */ |
| 1011 | u32 sclk; |
| 1012 | /* voltage info */ |
| 1013 | struct radeon_voltage voltage; |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 1014 | /* standardized clock flags */ |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1015 | u32 flags; |
| 1016 | }; |
| 1017 | |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1018 | /* state flags */ |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 1019 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1020 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1021 | struct radeon_power_state { |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 1022 | enum radeon_pm_state_type type; |
Alex Deucher | 8f3f1c9 | 2011-11-04 10:09:43 -0400 | [diff] [blame] | 1023 | struct radeon_pm_clock_info *clock_info; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1024 | /* number of valid clock modes in this power state */ |
| 1025 | int num_clock_modes; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1026 | struct radeon_pm_clock_info *default_clock_mode; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1027 | /* standardized state flags */ |
| 1028 | u32 flags; |
Alex Deucher | 79daedc | 2010-04-22 14:25:19 -0400 | [diff] [blame] | 1029 | u32 misc; /* vbios specific flags */ |
| 1030 | u32 misc2; /* vbios specific flags */ |
| 1031 | int pcie_lanes; /* pcie lanes */ |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1032 | }; |
| 1033 | |
Rafał Miłecki | 2745932 | 2010-02-11 22:16:36 +0000 | [diff] [blame] | 1034 | /* |
| 1035 | * Some modes are overclocked by very low value, accept them |
| 1036 | */ |
| 1037 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
| 1038 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1039 | struct radeon_pm { |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1040 | struct mutex mutex; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1041 | u32 active_crtcs; |
| 1042 | int active_crtc_count; |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1043 | int req_vblank; |
Rafał Miłecki | 839461d | 2010-03-02 22:06:51 +0100 | [diff] [blame] | 1044 | bool vblank_sync; |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 1045 | bool gui_idle; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1046 | fixed20_12 max_bandwidth; |
| 1047 | fixed20_12 igp_sideport_mclk; |
| 1048 | fixed20_12 igp_system_mclk; |
| 1049 | fixed20_12 igp_ht_link_clk; |
| 1050 | fixed20_12 igp_ht_link_width; |
| 1051 | fixed20_12 k8_bandwidth; |
| 1052 | fixed20_12 sideport_bandwidth; |
| 1053 | fixed20_12 ht_bandwidth; |
| 1054 | fixed20_12 core_bandwidth; |
| 1055 | fixed20_12 sclk; |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1056 | fixed20_12 mclk; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1057 | fixed20_12 needed_bandwidth; |
Alex Deucher | 0975b16 | 2011-02-02 18:42:03 -0500 | [diff] [blame] | 1058 | struct radeon_power_state *power_state; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1059 | /* number of valid power states */ |
| 1060 | int num_power_states; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1061 | int current_power_state_index; |
| 1062 | int current_clock_mode_index; |
| 1063 | int requested_power_state_index; |
| 1064 | int requested_clock_mode_index; |
| 1065 | int default_power_state_index; |
| 1066 | u32 current_sclk; |
| 1067 | u32 current_mclk; |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 1068 | u16 current_vddc; |
| 1069 | u16 current_vddci; |
Alex Deucher | 9ace9f7 | 2011-01-06 21:19:26 -0500 | [diff] [blame] | 1070 | u32 default_sclk; |
| 1071 | u32 default_mclk; |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 1072 | u16 default_vddc; |
| 1073 | u16 default_vddci; |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 1074 | struct radeon_i2c_chan *i2c_bus; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1075 | /* selected pm method */ |
| 1076 | enum radeon_pm_method pm_method; |
| 1077 | /* dynpm power management */ |
| 1078 | struct delayed_work dynpm_idle_work; |
| 1079 | enum radeon_dynpm_state dynpm_state; |
| 1080 | enum radeon_dynpm_action dynpm_planned_action; |
| 1081 | unsigned long dynpm_action_timeout; |
| 1082 | bool dynpm_can_upclock; |
| 1083 | bool dynpm_can_downclock; |
| 1084 | /* profile-based power management */ |
| 1085 | enum radeon_pm_profile_type profile; |
| 1086 | int profile_index; |
| 1087 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 1088 | /* internal thermal controller on rv6xx+ */ |
| 1089 | enum radeon_int_thermal_type int_thermal_type; |
| 1090 | struct device *int_hwmon_dev; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1091 | }; |
| 1092 | |
Alex Deucher | a4c9e2e | 2011-11-04 10:09:41 -0400 | [diff] [blame] | 1093 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
| 1094 | enum radeon_pm_state_type ps_type, |
| 1095 | int instance); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1096 | |
| 1097 | /* |
| 1098 | * Benchmarking |
| 1099 | */ |
Ilija Hadzic | 638dd7d | 2011-10-12 23:29:39 -0400 | [diff] [blame] | 1100 | void radeon_benchmark(struct radeon_device *rdev, int test_number); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1101 | |
| 1102 | |
| 1103 | /* |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 1104 | * Testing |
| 1105 | */ |
| 1106 | void radeon_test_moves(struct radeon_device *rdev); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 1107 | void radeon_test_ring_sync(struct radeon_device *rdev, |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1108 | struct radeon_ring *cpA, |
| 1109 | struct radeon_ring *cpB); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 1110 | void radeon_test_syncing(struct radeon_device *rdev); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 1111 | |
| 1112 | |
| 1113 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1114 | * Debugfs |
| 1115 | */ |
Christian König | 4d8bf9a | 2011-10-24 14:54:54 +0200 | [diff] [blame] | 1116 | struct radeon_debugfs { |
| 1117 | struct drm_info_list *files; |
| 1118 | unsigned num_files; |
| 1119 | }; |
| 1120 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1121 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
| 1122 | struct drm_info_list *files, |
| 1123 | unsigned nfiles); |
| 1124 | int radeon_debugfs_fence_init(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1125 | |
| 1126 | |
| 1127 | /* |
| 1128 | * ASIC specific functions. |
| 1129 | */ |
| 1130 | struct radeon_asic { |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1131 | int (*init)(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1132 | void (*fini)(struct radeon_device *rdev); |
| 1133 | int (*resume)(struct radeon_device *rdev); |
| 1134 | int (*suspend)(struct radeon_device *rdev); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1135 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1136 | bool (*gpu_is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1137 | int (*asic_reset)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1138 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
| 1139 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
| 1140 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
| 1141 | void (*cp_fini)(struct radeon_device *rdev); |
| 1142 | void (*cp_disable)(struct radeon_device *rdev); |
| 1143 | void (*ring_start)(struct radeon_device *rdev); |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1144 | |
| 1145 | struct { |
| 1146 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1147 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1148 | void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1149 | void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1150 | struct radeon_semaphore *semaphore, bool emit_wait); |
| 1151 | } ring[RADEON_NUM_RINGS]; |
| 1152 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1153 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1154 | int (*irq_set)(struct radeon_device *rdev); |
| 1155 | int (*irq_process)(struct radeon_device *rdev); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 1156 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1157 | int (*cs_parse)(struct radeon_cs_parser *p); |
| 1158 | int (*copy_blit)(struct radeon_device *rdev, |
| 1159 | uint64_t src_offset, |
| 1160 | uint64_t dst_offset, |
Alex Deucher | 003cefe | 2011-09-16 12:04:08 -0400 | [diff] [blame] | 1161 | unsigned num_gpu_pages, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1162 | struct radeon_fence *fence); |
| 1163 | int (*copy_dma)(struct radeon_device *rdev, |
| 1164 | uint64_t src_offset, |
| 1165 | uint64_t dst_offset, |
Alex Deucher | 003cefe | 2011-09-16 12:04:08 -0400 | [diff] [blame] | 1166 | unsigned num_gpu_pages, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1167 | struct radeon_fence *fence); |
| 1168 | int (*copy)(struct radeon_device *rdev, |
| 1169 | uint64_t src_offset, |
| 1170 | uint64_t dst_offset, |
Alex Deucher | 003cefe | 2011-09-16 12:04:08 -0400 | [diff] [blame] | 1171 | unsigned num_gpu_pages, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1172 | struct radeon_fence *fence); |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1173 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1174 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1175 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1176 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
Alex Deucher | c836a41 | 2009-12-23 10:07:50 -0500 | [diff] [blame] | 1177 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1178 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
| 1179 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1180 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
| 1181 | uint32_t tiling_flags, uint32_t pitch, |
| 1182 | uint32_t offset, uint32_t obj_size); |
Daniel Vetter | 9479c54 | 2010-03-11 21:19:16 +0000 | [diff] [blame] | 1183 | void (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1184 | void (*bandwidth_update)(struct radeon_device *rdev); |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 1185 | |
| 1186 | struct { |
| 1187 | void (*init)(struct radeon_device *rdev); |
| 1188 | void (*fini)(struct radeon_device *rdev); |
| 1189 | bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| 1190 | void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| 1191 | } hpd; |
| 1192 | |
Jerome Glisse | 062b389 | 2010-02-04 20:36:39 +0100 | [diff] [blame] | 1193 | /* ioctl hw specific callback. Some hw might want to perform special |
| 1194 | * operation on specific ioctl. For instance on wait idle some hw |
| 1195 | * might want to perform and HDP flush through MMIO as it seems that |
| 1196 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed |
| 1197 | * through ring. |
| 1198 | */ |
| 1199 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); |
Alex Deucher | def9ba9 | 2010-04-22 12:39:58 -0400 | [diff] [blame] | 1200 | bool (*gui_idle)(struct radeon_device *rdev); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1201 | /* power management */ |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame^] | 1202 | struct { |
| 1203 | void (*misc)(struct radeon_device *rdev); |
| 1204 | void (*prepare)(struct radeon_device *rdev); |
| 1205 | void (*finish)(struct radeon_device *rdev); |
| 1206 | void (*init_profile)(struct radeon_device *rdev); |
| 1207 | void (*get_dynpm_state)(struct radeon_device *rdev); |
| 1208 | } pm; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 1209 | /* pageflipping */ |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1210 | struct { |
| 1211 | void (*pre_page_flip)(struct radeon_device *rdev, int crtc); |
| 1212 | u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); |
| 1213 | void (*post_page_flip)(struct radeon_device *rdev, int crtc); |
| 1214 | } pflip; |
Alex Deucher | 3ae19b7 | 2012-02-23 17:53:37 -0500 | [diff] [blame] | 1215 | /* wait for vblank */ |
| 1216 | void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); |
Alex Deucher | 89e5181 | 2012-02-23 17:53:38 -0500 | [diff] [blame] | 1217 | /* wait for mc_idle */ |
| 1218 | int (*mc_wait_for_idle)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1219 | }; |
| 1220 | |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1221 | /* |
| 1222 | * Asic structures |
| 1223 | */ |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1224 | struct r100_gpu_lockup { |
| 1225 | unsigned long last_jiffies; |
| 1226 | u32 last_cp_rptr; |
| 1227 | }; |
| 1228 | |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1229 | struct r100_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1230 | const unsigned *reg_safe_bm; |
| 1231 | unsigned reg_safe_bm_size; |
| 1232 | u32 hdp_cntl; |
| 1233 | struct r100_gpu_lockup lockup; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1234 | }; |
| 1235 | |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1236 | struct r300_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1237 | const unsigned *reg_safe_bm; |
| 1238 | unsigned reg_safe_bm_size; |
| 1239 | u32 resync_scratch; |
| 1240 | u32 hdp_cntl; |
| 1241 | struct r100_gpu_lockup lockup; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1242 | }; |
| 1243 | |
| 1244 | struct r600_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1245 | unsigned max_pipes; |
| 1246 | unsigned max_tile_pipes; |
| 1247 | unsigned max_simds; |
| 1248 | unsigned max_backends; |
| 1249 | unsigned max_gprs; |
| 1250 | unsigned max_threads; |
| 1251 | unsigned max_stack_entries; |
| 1252 | unsigned max_hw_contexts; |
| 1253 | unsigned max_gs_threads; |
| 1254 | unsigned sx_max_export_size; |
| 1255 | unsigned sx_max_export_pos_size; |
| 1256 | unsigned sx_max_export_smx_size; |
| 1257 | unsigned sq_num_cf_insts; |
| 1258 | unsigned tiling_nbanks; |
| 1259 | unsigned tiling_npipes; |
| 1260 | unsigned tiling_group_size; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 1261 | unsigned tile_config; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 1262 | unsigned backend_map; |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1263 | struct r100_gpu_lockup lockup; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1264 | }; |
| 1265 | |
| 1266 | struct rv770_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1267 | unsigned max_pipes; |
| 1268 | unsigned max_tile_pipes; |
| 1269 | unsigned max_simds; |
| 1270 | unsigned max_backends; |
| 1271 | unsigned max_gprs; |
| 1272 | unsigned max_threads; |
| 1273 | unsigned max_stack_entries; |
| 1274 | unsigned max_hw_contexts; |
| 1275 | unsigned max_gs_threads; |
| 1276 | unsigned sx_max_export_size; |
| 1277 | unsigned sx_max_export_pos_size; |
| 1278 | unsigned sx_max_export_smx_size; |
| 1279 | unsigned sq_num_cf_insts; |
| 1280 | unsigned sx_num_of_sets; |
| 1281 | unsigned sc_prim_fifo_size; |
| 1282 | unsigned sc_hiz_tile_fifo_size; |
| 1283 | unsigned sc_earlyz_tile_fifo_fize; |
| 1284 | unsigned tiling_nbanks; |
| 1285 | unsigned tiling_npipes; |
| 1286 | unsigned tiling_group_size; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 1287 | unsigned tile_config; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 1288 | unsigned backend_map; |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1289 | struct r100_gpu_lockup lockup; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1290 | }; |
| 1291 | |
Alex Deucher | 32fcdbf | 2010-03-24 13:33:47 -0400 | [diff] [blame] | 1292 | struct evergreen_asic { |
| 1293 | unsigned num_ses; |
| 1294 | unsigned max_pipes; |
| 1295 | unsigned max_tile_pipes; |
| 1296 | unsigned max_simds; |
| 1297 | unsigned max_backends; |
| 1298 | unsigned max_gprs; |
| 1299 | unsigned max_threads; |
| 1300 | unsigned max_stack_entries; |
| 1301 | unsigned max_hw_contexts; |
| 1302 | unsigned max_gs_threads; |
| 1303 | unsigned sx_max_export_size; |
| 1304 | unsigned sx_max_export_pos_size; |
| 1305 | unsigned sx_max_export_smx_size; |
| 1306 | unsigned sq_num_cf_insts; |
| 1307 | unsigned sx_num_of_sets; |
| 1308 | unsigned sc_prim_fifo_size; |
| 1309 | unsigned sc_hiz_tile_fifo_size; |
| 1310 | unsigned sc_earlyz_tile_fifo_size; |
| 1311 | unsigned tiling_nbanks; |
| 1312 | unsigned tiling_npipes; |
| 1313 | unsigned tiling_group_size; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 1314 | unsigned tile_config; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 1315 | unsigned backend_map; |
Alex Deucher | 17db704 | 2010-12-21 16:05:39 -0500 | [diff] [blame] | 1316 | struct r100_gpu_lockup lockup; |
Alex Deucher | 32fcdbf | 2010-03-24 13:33:47 -0400 | [diff] [blame] | 1317 | }; |
| 1318 | |
Alex Deucher | fecf1d0 | 2011-03-02 20:07:29 -0500 | [diff] [blame] | 1319 | struct cayman_asic { |
| 1320 | unsigned max_shader_engines; |
| 1321 | unsigned max_pipes_per_simd; |
| 1322 | unsigned max_tile_pipes; |
| 1323 | unsigned max_simds_per_se; |
| 1324 | unsigned max_backends_per_se; |
| 1325 | unsigned max_texture_channel_caches; |
| 1326 | unsigned max_gprs; |
| 1327 | unsigned max_threads; |
| 1328 | unsigned max_gs_threads; |
| 1329 | unsigned max_stack_entries; |
| 1330 | unsigned sx_num_of_sets; |
| 1331 | unsigned sx_max_export_size; |
| 1332 | unsigned sx_max_export_pos_size; |
| 1333 | unsigned sx_max_export_smx_size; |
| 1334 | unsigned max_hw_contexts; |
| 1335 | unsigned sq_num_cf_insts; |
| 1336 | unsigned sc_prim_fifo_size; |
| 1337 | unsigned sc_hiz_tile_fifo_size; |
| 1338 | unsigned sc_earlyz_tile_fifo_size; |
| 1339 | |
| 1340 | unsigned num_shader_engines; |
| 1341 | unsigned num_shader_pipes_per_simd; |
| 1342 | unsigned num_tile_pipes; |
| 1343 | unsigned num_simds_per_se; |
| 1344 | unsigned num_backends_per_se; |
| 1345 | unsigned backend_disable_mask_per_asic; |
| 1346 | unsigned backend_map; |
| 1347 | unsigned num_texture_channel_caches; |
| 1348 | unsigned mem_max_burst_length_bytes; |
| 1349 | unsigned mem_row_size_in_kb; |
| 1350 | unsigned shader_engine_tile_size; |
| 1351 | unsigned num_gpus; |
| 1352 | unsigned multi_gpu_tile_size; |
| 1353 | |
| 1354 | unsigned tile_config; |
| 1355 | struct r100_gpu_lockup lockup; |
| 1356 | }; |
| 1357 | |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1358 | union radeon_asic_config { |
| 1359 | struct r300_asic r300; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1360 | struct r100_asic r100; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1361 | struct r600_asic r600; |
| 1362 | struct rv770_asic rv770; |
Alex Deucher | 32fcdbf | 2010-03-24 13:33:47 -0400 | [diff] [blame] | 1363 | struct evergreen_asic evergreen; |
Alex Deucher | fecf1d0 | 2011-03-02 20:07:29 -0500 | [diff] [blame] | 1364 | struct cayman_asic cayman; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1365 | }; |
| 1366 | |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1367 | /* |
| 1368 | * asic initizalization from radeon_asic.c |
| 1369 | */ |
| 1370 | void radeon_agp_disable(struct radeon_device *rdev); |
| 1371 | int radeon_asic_init(struct radeon_device *rdev); |
| 1372 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1373 | |
| 1374 | /* |
| 1375 | * IOCTL. |
| 1376 | */ |
| 1377 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, |
| 1378 | struct drm_file *filp); |
| 1379 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, |
| 1380 | struct drm_file *filp); |
| 1381 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 1382 | struct drm_file *file_priv); |
| 1383 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 1384 | struct drm_file *file_priv); |
| 1385 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 1386 | struct drm_file *file_priv); |
| 1387 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 1388 | struct drm_file *file_priv); |
| 1389 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1390 | struct drm_file *filp); |
| 1391 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1392 | struct drm_file *filp); |
| 1393 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 1394 | struct drm_file *filp); |
| 1395 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, |
| 1396 | struct drm_file *filp); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1397 | int radeon_gem_va_ioctl(struct drm_device *dev, void *data, |
| 1398 | struct drm_file *filp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1399 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1400 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
| 1401 | struct drm_file *filp); |
| 1402 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, |
| 1403 | struct drm_file *filp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1404 | |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 1405 | /* VRAM scratch page for HDP bug, default vram page */ |
| 1406 | struct r600_vram_scratch { |
Alex Deucher | 87cbf8f | 2010-08-27 13:59:54 -0400 | [diff] [blame] | 1407 | struct radeon_bo *robj; |
| 1408 | volatile uint32_t *ptr; |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 1409 | u64 gpu_addr; |
Alex Deucher | 87cbf8f | 2010-08-27 13:59:54 -0400 | [diff] [blame] | 1410 | }; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1411 | |
Michel Dänzer | 7a1619b | 2011-11-10 18:57:26 +0100 | [diff] [blame] | 1412 | |
| 1413 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1414 | * Core structure, functions and helpers. |
| 1415 | */ |
| 1416 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
| 1417 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
| 1418 | |
| 1419 | struct radeon_device { |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1420 | struct device *dev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1421 | struct drm_device *ddev; |
| 1422 | struct pci_dev *pdev; |
| 1423 | /* ASIC */ |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1424 | union radeon_asic_config config; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1425 | enum radeon_family family; |
| 1426 | unsigned long flags; |
| 1427 | int usec_timeout; |
| 1428 | enum radeon_pll_errata pll_errata; |
| 1429 | int num_gb_pipes; |
Alex Deucher | f779b3e | 2009-08-19 19:11:39 -0400 | [diff] [blame] | 1430 | int num_z_pipes; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1431 | int disp_priority; |
| 1432 | /* BIOS */ |
| 1433 | uint8_t *bios; |
| 1434 | bool is_atom_bios; |
| 1435 | uint16_t bios_header_start; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1436 | struct radeon_bo *stollen_vga_memory; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1437 | /* Register mmio */ |
Dave Airlie | 4c9bc75 | 2009-06-29 18:29:12 +1000 | [diff] [blame] | 1438 | resource_size_t rmmio_base; |
| 1439 | resource_size_t rmmio_size; |
Benjamin Herrenschmidt | a0533fb | 2011-07-13 06:28:12 +0000 | [diff] [blame] | 1440 | void __iomem *rmmio; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1441 | radeon_rreg_t mc_rreg; |
| 1442 | radeon_wreg_t mc_wreg; |
| 1443 | radeon_rreg_t pll_rreg; |
| 1444 | radeon_wreg_t pll_wreg; |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1445 | uint32_t pcie_reg_mask; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1446 | radeon_rreg_t pciep_rreg; |
| 1447 | radeon_wreg_t pciep_wreg; |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 1448 | /* io port */ |
| 1449 | void __iomem *rio_mem; |
| 1450 | resource_size_t rio_mem_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1451 | struct radeon_clock clock; |
| 1452 | struct radeon_mc mc; |
| 1453 | struct radeon_gart gart; |
| 1454 | struct radeon_mode_info mode_info; |
| 1455 | struct radeon_scratch scratch; |
| 1456 | struct radeon_mman mman; |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 1457 | rwlock_t fence_lock; |
| 1458 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; |
Christian König | 15d3332 | 2011-09-15 19:02:22 +0200 | [diff] [blame] | 1459 | struct radeon_semaphore_driver semaphore_drv; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1460 | struct radeon_ring ring[RADEON_NUM_RINGS]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1461 | struct radeon_ib_pool ib_pool; |
| 1462 | struct radeon_irq irq; |
| 1463 | struct radeon_asic *asic; |
| 1464 | struct radeon_gem gem; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1465 | struct radeon_pm pm; |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 1466 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
Michel Dänzer | 7a1619b | 2011-11-10 18:57:26 +0100 | [diff] [blame] | 1467 | struct radeon_mutex cs_mutex; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1468 | struct radeon_wb wb; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1469 | struct radeon_dummy_page dummy_page; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1470 | bool gpu_lockup; |
| 1471 | bool shutdown; |
| 1472 | bool suspend; |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 1473 | bool need_dma32; |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 1474 | bool accel_working; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1475 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1476 | const struct firmware *me_fw; /* all family ME firmware */ |
| 1477 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1478 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
Alex Deucher | 0af62b0 | 2011-01-06 21:19:31 -0500 | [diff] [blame] | 1479 | const struct firmware *mc_fw; /* NI MC firmware */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1480 | struct r600_blit r600_blit; |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 1481 | struct r600_vram_scratch vram_scratch; |
Alex Deucher | 3e5cb98 | 2009-10-16 12:21:24 -0400 | [diff] [blame] | 1482 | int msi_enabled; /* msi enabled */ |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1483 | struct r600_ih ih; /* r6/700 interrupt ring */ |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 1484 | struct work_struct hotplug_work; |
Alex Deucher | 18917b6 | 2010-02-01 16:02:25 -0500 | [diff] [blame] | 1485 | int num_crtc; /* number of crtcs */ |
Alex Deucher | 40bacf1 | 2009-12-23 03:23:21 -0500 | [diff] [blame] | 1486 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 1487 | struct mutex vram_mutex; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1488 | |
| 1489 | /* audio stuff */ |
Rafał Miłecki | 7eea7e9 | 2010-06-19 12:24:56 +0200 | [diff] [blame] | 1490 | bool audio_enabled; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1491 | struct timer_list audio_timer; |
| 1492 | int audio_channels; |
| 1493 | int audio_rate; |
| 1494 | int audio_bits_per_sample; |
| 1495 | uint8_t audio_status_bits; |
| 1496 | uint8_t audio_category_code; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1497 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1498 | struct notifier_block acpi_nb; |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 1499 | /* only one userspace can use Hyperz features or CMASK at a time */ |
Dave Airlie | ab9e1f5 | 2010-07-13 11:11:11 +1000 | [diff] [blame] | 1500 | struct drm_file *hyperz_filp; |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 1501 | struct drm_file *cmask_filp; |
Alex Deucher | f376b94 | 2010-08-05 21:21:16 -0400 | [diff] [blame] | 1502 | /* i2c buses */ |
| 1503 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; |
Christian König | 4d8bf9a | 2011-10-24 14:54:54 +0200 | [diff] [blame] | 1504 | /* debugfs */ |
| 1505 | struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; |
| 1506 | unsigned debugfs_count; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1507 | /* virtual memory */ |
| 1508 | struct radeon_vm_manager vm_manager; |
Alex Deucher | 3000bf3 | 2012-01-05 22:11:07 -0500 | [diff] [blame] | 1509 | /* ring used for bo copies */ |
| 1510 | u32 copy_ring; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1511 | }; |
| 1512 | |
| 1513 | int radeon_device_init(struct radeon_device *rdev, |
| 1514 | struct drm_device *ddev, |
| 1515 | struct pci_dev *pdev, |
| 1516 | uint32_t flags); |
| 1517 | void radeon_device_fini(struct radeon_device *rdev); |
| 1518 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
| 1519 | |
Andi Kleen | 6fcbef7 | 2011-10-13 16:08:42 -0700 | [diff] [blame] | 1520 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); |
| 1521 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| 1522 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); |
| 1523 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 1524 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1525 | /* |
| 1526 | * Cast helper |
| 1527 | */ |
| 1528 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1529 | |
| 1530 | /* |
| 1531 | * Registers read & write functions. |
| 1532 | */ |
Benjamin Herrenschmidt | a0533fb | 2011-07-13 06:28:12 +0000 | [diff] [blame] | 1533 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
| 1534 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) |
| 1535 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) |
| 1536 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1537 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1538 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1539 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1540 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 1541 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 1542 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
| 1543 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
| 1544 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
| 1545 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1546 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
| 1547 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
Rafał Miłecki | aa5120d | 2010-02-18 20:24:28 +0000 | [diff] [blame] | 1548 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
| 1549 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1550 | #define WREG32_P(reg, val, mask) \ |
| 1551 | do { \ |
| 1552 | uint32_t tmp_ = RREG32(reg); \ |
| 1553 | tmp_ &= (mask); \ |
| 1554 | tmp_ |= ((val) & ~(mask)); \ |
| 1555 | WREG32(reg, tmp_); \ |
| 1556 | } while (0) |
| 1557 | #define WREG32_PLL_P(reg, val, mask) \ |
| 1558 | do { \ |
| 1559 | uint32_t tmp_ = RREG32_PLL(reg); \ |
| 1560 | tmp_ &= (mask); \ |
| 1561 | tmp_ |= ((val) & ~(mask)); \ |
| 1562 | WREG32_PLL(reg, tmp_); \ |
| 1563 | } while (0) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1564 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 1565 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
| 1566 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1567 | |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1568 | /* |
| 1569 | * Indirect registers accessor |
| 1570 | */ |
| 1571 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
| 1572 | { |
| 1573 | uint32_t r; |
| 1574 | |
| 1575 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
| 1576 | r = RREG32(RADEON_PCIE_DATA); |
| 1577 | return r; |
| 1578 | } |
| 1579 | |
| 1580 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 1581 | { |
| 1582 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
| 1583 | WREG32(RADEON_PCIE_DATA, (v)); |
| 1584 | } |
| 1585 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1586 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
| 1587 | |
| 1588 | |
| 1589 | /* |
| 1590 | * ASICs helpers. |
| 1591 | */ |
Dave Airlie | b995e43 | 2009-07-14 02:02:32 +1000 | [diff] [blame] | 1592 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
| 1593 | (rdev->pdev->device == 0x5969)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1594 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
| 1595 | (rdev->family == CHIP_RV200) || \ |
| 1596 | (rdev->family == CHIP_RS100) || \ |
| 1597 | (rdev->family == CHIP_RS200) || \ |
| 1598 | (rdev->family == CHIP_RV250) || \ |
| 1599 | (rdev->family == CHIP_RV280) || \ |
| 1600 | (rdev->family == CHIP_RS300)) |
| 1601 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
| 1602 | (rdev->family == CHIP_RV350) || \ |
| 1603 | (rdev->family == CHIP_R350) || \ |
| 1604 | (rdev->family == CHIP_RV380) || \ |
| 1605 | (rdev->family == CHIP_R420) || \ |
| 1606 | (rdev->family == CHIP_R423) || \ |
| 1607 | (rdev->family == CHIP_RV410) || \ |
| 1608 | (rdev->family == CHIP_RS400) || \ |
| 1609 | (rdev->family == CHIP_RS480)) |
Alex Deucher | 3313e3d | 2011-01-06 18:49:34 -0500 | [diff] [blame] | 1610 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
| 1611 | (rdev->ddev->pdev->device == 0x9443) || \ |
| 1612 | (rdev->ddev->pdev->device == 0x944B) || \ |
| 1613 | (rdev->ddev->pdev->device == 0x9506) || \ |
| 1614 | (rdev->ddev->pdev->device == 0x9509) || \ |
| 1615 | (rdev->ddev->pdev->device == 0x950F) || \ |
| 1616 | (rdev->ddev->pdev->device == 0x689C) || \ |
| 1617 | (rdev->ddev->pdev->device == 0x689D)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1618 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
Alex Deucher | 99999aa | 2010-11-16 12:09:41 -0500 | [diff] [blame] | 1619 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
| 1620 | (rdev->family == CHIP_RS690) || \ |
| 1621 | (rdev->family == CHIP_RS740) || \ |
| 1622 | (rdev->family >= CHIP_R600)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1623 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
| 1624 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1625 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
Alex Deucher | 633b916 | 2011-01-06 21:19:11 -0500 | [diff] [blame] | 1626 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
| 1627 | (rdev->flags & RADEON_IS_IGP)) |
Alex Deucher | 1fe1830 | 2011-01-06 21:19:12 -0500 | [diff] [blame] | 1628 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1629 | |
| 1630 | /* |
| 1631 | * BIOS helpers. |
| 1632 | */ |
| 1633 | #define RBIOS8(i) (rdev->bios[i]) |
| 1634 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
| 1635 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
| 1636 | |
| 1637 | int radeon_combios_init(struct radeon_device *rdev); |
| 1638 | void radeon_combios_fini(struct radeon_device *rdev); |
| 1639 | int radeon_atombios_init(struct radeon_device *rdev); |
| 1640 | void radeon_atombios_fini(struct radeon_device *rdev); |
| 1641 | |
| 1642 | |
| 1643 | /* |
| 1644 | * RING helpers. |
| 1645 | */ |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 1646 | #if DRM_DEBUG_CODE == 0 |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1647 | static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1648 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1649 | ring->ring[ring->wptr++] = v; |
| 1650 | ring->wptr &= ring->ptr_mask; |
| 1651 | ring->count_dw--; |
| 1652 | ring->ring_free_dw--; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1653 | } |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 1654 | #else |
| 1655 | /* With debugging this is just too big to inline */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1656 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v); |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 1657 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1658 | |
| 1659 | /* |
| 1660 | * ASICs macro. |
| 1661 | */ |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1662 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1663 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
| 1664 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
| 1665 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1666 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1667 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
Christian König | 7b1f248 | 2011-09-23 15:11:23 +0200 | [diff] [blame] | 1668 | #define radeon_gpu_is_lockup(rdev, cp) (rdev)->asic->gpu_is_lockup((rdev), (cp)) |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1669 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1670 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
| 1671 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1672 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
Christian König | 7b1f248 | 2011-09-23 15:11:23 +0200 | [diff] [blame] | 1673 | #define radeon_ring_test(rdev, cp) (rdev)->asic->ring_test((rdev), (cp)) |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1674 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1675 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1676 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
| 1677 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 1678 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1679 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) |
| 1680 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1681 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) |
| 1682 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) |
| 1683 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1684 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1685 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1686 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
Rafał Miłecki | 93e7de7 | 2009-11-04 23:34:10 +0100 | [diff] [blame] | 1687 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) |
Alex Deucher | c836a41 | 2009-12-23 10:07:50 -0500 | [diff] [blame] | 1688 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1689 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
| 1690 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1691 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
| 1692 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1693 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 1694 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) |
| 1695 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) |
| 1696 | #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) |
| 1697 | #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) |
Alex Deucher | def9ba9 | 2010-04-22 12:39:58 -0400 | [diff] [blame] | 1698 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame^] | 1699 | #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) |
| 1700 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) |
| 1701 | #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) |
| 1702 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) |
| 1703 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1704 | #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pflip.pre_page_flip((rdev), (crtc)) |
| 1705 | #define radeon_page_flip(rdev, crtc, base) rdev->asic->pflip.page_flip((rdev), (crtc), (base)) |
| 1706 | #define radeon_post_page_flip(rdev, crtc) rdev->asic->pflip.post_page_flip((rdev), (crtc)) |
Alex Deucher | 3ae19b7 | 2012-02-23 17:53:37 -0500 | [diff] [blame] | 1707 | #define radeon_wait_for_vblank(rdev, crtc) rdev->asic->wait_for_vblank((rdev), (crtc)) |
Alex Deucher | 89e5181 | 2012-02-23 17:53:38 -0500 | [diff] [blame] | 1708 | #define radeon_mc_wait_for_idle(rdev) rdev->asic->mc_wait_for_idle((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1709 | |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 1710 | /* Common functions */ |
Jerome Glisse | 700a0cc | 2010-01-13 15:16:38 +0100 | [diff] [blame] | 1711 | /* AGP */ |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 1712 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
Jerome Glisse | 700a0cc | 2010-01-13 15:16:38 +0100 | [diff] [blame] | 1713 | extern void radeon_agp_disable(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1714 | extern int radeon_modeset_init(struct radeon_device *rdev); |
| 1715 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1716 | extern bool radeon_card_posted(struct radeon_device *rdev); |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1717 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 1718 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 1719 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1720 | extern void radeon_scratch_init(struct radeon_device *rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1721 | extern void radeon_wb_fini(struct radeon_device *rdev); |
| 1722 | extern int radeon_wb_init(struct radeon_device *rdev); |
| 1723 | extern void radeon_wb_disable(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1724 | extern void radeon_surface_init(struct radeon_device *rdev); |
| 1725 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 1726 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 1727 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 1728 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 1729 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1730 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
| 1731 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1732 | extern int radeon_resume_kms(struct drm_device *dev); |
| 1733 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 1734 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 1735 | |
Daniel Vetter | 3574dda | 2011-02-18 17:59:19 +0100 | [diff] [blame] | 1736 | /* |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1737 | * vm |
| 1738 | */ |
| 1739 | int radeon_vm_manager_init(struct radeon_device *rdev); |
| 1740 | void radeon_vm_manager_fini(struct radeon_device *rdev); |
| 1741 | int radeon_vm_manager_start(struct radeon_device *rdev); |
| 1742 | int radeon_vm_manager_suspend(struct radeon_device *rdev); |
| 1743 | int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
| 1744 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); |
| 1745 | int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm); |
| 1746 | void radeon_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm); |
| 1747 | int radeon_vm_bo_update_pte(struct radeon_device *rdev, |
| 1748 | struct radeon_vm *vm, |
| 1749 | struct radeon_bo *bo, |
| 1750 | struct ttm_mem_reg *mem); |
| 1751 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, |
| 1752 | struct radeon_bo *bo); |
| 1753 | int radeon_vm_bo_add(struct radeon_device *rdev, |
| 1754 | struct radeon_vm *vm, |
| 1755 | struct radeon_bo *bo, |
| 1756 | uint64_t offset, |
| 1757 | uint32_t flags); |
| 1758 | int radeon_vm_bo_rmv(struct radeon_device *rdev, |
| 1759 | struct radeon_vm *vm, |
| 1760 | struct radeon_bo *bo); |
| 1761 | |
| 1762 | |
| 1763 | /* |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 1764 | * R600 vram scratch functions |
| 1765 | */ |
| 1766 | int r600_vram_scratch_init(struct radeon_device *rdev); |
| 1767 | void r600_vram_scratch_fini(struct radeon_device *rdev); |
| 1768 | |
| 1769 | /* |
Jerome Glisse | 285484e | 2011-12-16 17:03:42 -0500 | [diff] [blame] | 1770 | * r600 cs checking helper |
| 1771 | */ |
| 1772 | unsigned r600_mip_minify(unsigned size, unsigned level); |
| 1773 | bool r600_fmt_is_valid_color(u32 format); |
| 1774 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); |
| 1775 | int r600_fmt_get_blocksize(u32 format); |
| 1776 | int r600_fmt_get_nblocksx(u32 format, u32 w); |
| 1777 | int r600_fmt_get_nblocksy(u32 format, u32 h); |
| 1778 | |
| 1779 | /* |
Daniel Vetter | 3574dda | 2011-02-18 17:59:19 +0100 | [diff] [blame] | 1780 | * r600 functions used by radeon_encoder.c |
| 1781 | */ |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 1782 | extern void r600_hdmi_enable(struct drm_encoder *encoder); |
| 1783 | extern void r600_hdmi_disable(struct drm_encoder *encoder); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1784 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 1785 | |
Alex Deucher | 0af62b0 | 2011-01-06 21:19:31 -0500 | [diff] [blame] | 1786 | extern int ni_init_microcode(struct radeon_device *rdev); |
Alex Deucher | 755d819 | 2011-03-02 20:07:34 -0500 | [diff] [blame] | 1787 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
Alex Deucher | 0af62b0 | 2011-01-06 21:19:31 -0500 | [diff] [blame] | 1788 | |
Alberto Milone | d7a2952 | 2010-07-06 11:40:24 -0400 | [diff] [blame] | 1789 | /* radeon_acpi.c */ |
| 1790 | #if defined(CONFIG_ACPI) |
| 1791 | extern int radeon_acpi_init(struct radeon_device *rdev); |
| 1792 | #else |
| 1793 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } |
| 1794 | #endif |
| 1795 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1796 | #include "radeon_object.h" |
| 1797 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1798 | #endif |