blob: 0a30438832c92c9ff80316ef69b8de15a2635c1b [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Jiri Pirko22a67762017-02-03 10:29:07 +01003 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +020056#include <linux/netlink.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020057#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020058#include <net/pkt_cls.h>
59#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020060#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010061#include <net/tc_act/tc_sample.h>
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +020062#include <net/addrconf.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020063
64#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020065#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020066#include "core.h"
67#include "reg.h"
68#include "port.h"
69#include "trap.h"
70#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010071#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020072#include "spectrum_dpipe.h"
Yotam Gigid3b939b2017-09-19 10:00:09 +020073#include "spectrum_acl_flex_actions.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020074#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020075
Yotam Gigi6b742192017-05-23 21:56:29 +020076#define MLXSW_FWREV_MAJOR 13
Shalom Toledo2f53fbd2017-11-12 09:01:24 +010077#define MLXSW_FWREV_MINOR 1530
78#define MLXSW_FWREV_SUBMINOR 152
Yuval Mintzfd5204c2018-01-18 12:55:23 +010079#define MLXSW_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
Yotam Gigi6b742192017-05-23 21:56:29 +020080
81#define MLXSW_SP_FW_FILENAME \
Yotam Gigia4e1ce22017-06-04 16:49:58 +020082 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
Yotam Gigi6b742192017-05-23 21:56:29 +020083 "." __stringify(MLXSW_FWREV_MINOR) \
84 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
85
Jiri Pirko56ade8f2015-10-16 14:01:37 +020086static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
87static const char mlxsw_sp_driver_version[] = "1.0";
88
89/* tx_hdr_version
90 * Tx header version.
91 * Must be set to 1.
92 */
93MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
94
95/* tx_hdr_ctl
96 * Packet control type.
97 * 0 - Ethernet control (e.g. EMADs, LACP)
98 * 1 - Ethernet data
99 */
100MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
101
102/* tx_hdr_proto
103 * Packet protocol type. Must be set to 1 (Ethernet).
104 */
105MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
106
107/* tx_hdr_rx_is_router
108 * Packet is sent from the router. Valid for data packets only.
109 */
110MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
111
112/* tx_hdr_fid_valid
113 * Indicates if the 'fid' field is valid and should be used for
114 * forwarding lookup. Valid for data packets only.
115 */
116MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
117
118/* tx_hdr_swid
119 * Switch partition ID. Must be set to 0.
120 */
121MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
122
123/* tx_hdr_control_tclass
124 * Indicates if the packet should use the control TClass and not one
125 * of the data TClasses.
126 */
127MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
128
129/* tx_hdr_etclass
130 * Egress TClass to be used on the egress device on the egress port.
131 */
132MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
133
134/* tx_hdr_port_mid
135 * Destination local port for unicast packets.
136 * Destination multicast ID for multicast packets.
137 *
138 * Control packets are directed to a specific egress port, while data
139 * packets are transmitted through the CPU port (0) into the switch partition,
140 * where forwarding rules are applied.
141 */
142MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
143
144/* tx_hdr_fid
145 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
146 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
147 * Valid for data packets only.
148 */
149MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
150
151/* tx_hdr_type
152 * 0 - Data packets
153 * 6 - Control packets
154 */
155MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
156
Yotam Gigie5e5c882017-05-23 21:56:27 +0200157struct mlxsw_sp_mlxfw_dev {
158 struct mlxfw_dev mlxfw_dev;
159 struct mlxsw_sp *mlxsw_sp;
160};
161
162static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
163 u16 component_index, u32 *p_max_size,
164 u8 *p_align_bits, u16 *p_max_write_size)
165{
166 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
167 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
168 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
169 char mcqi_pl[MLXSW_REG_MCQI_LEN];
170 int err;
171
172 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
173 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
174 if (err)
175 return err;
176 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
177 p_max_write_size);
178
179 *p_align_bits = max_t(u8, *p_align_bits, 2);
180 *p_max_write_size = min_t(u16, *p_max_write_size,
181 MLXSW_REG_MCDA_MAX_DATA_LEN);
182 return 0;
183}
184
185static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
186{
187 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
188 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
189 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
190 char mcc_pl[MLXSW_REG_MCC_LEN];
191 u8 control_state;
192 int err;
193
194 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
195 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
196 if (err)
197 return err;
198
199 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
200 if (control_state != MLXFW_FSM_STATE_IDLE)
201 return -EBUSY;
202
203 mlxsw_reg_mcc_pack(mcc_pl,
204 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
205 0, *fwhandle, 0);
206 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
207}
208
209static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
210 u32 fwhandle, u16 component_index,
211 u32 component_size)
212{
213 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
214 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
215 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
216 char mcc_pl[MLXSW_REG_MCC_LEN];
217
218 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
219 component_index, fwhandle, component_size);
220 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
221}
222
223static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
224 u32 fwhandle, u8 *data, u16 size,
225 u32 offset)
226{
227 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
228 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
229 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
230 char mcda_pl[MLXSW_REG_MCDA_LEN];
231
232 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
233 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
234}
235
236static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
237 u32 fwhandle, u16 component_index)
238{
239 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
240 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
241 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
242 char mcc_pl[MLXSW_REG_MCC_LEN];
243
244 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
245 component_index, fwhandle, 0);
246 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
247}
248
249static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
250{
251 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
252 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
253 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
254 char mcc_pl[MLXSW_REG_MCC_LEN];
255
256 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
257 fwhandle, 0);
258 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
259}
260
261static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
262 enum mlxfw_fsm_state *fsm_state,
263 enum mlxfw_fsm_state_err *fsm_state_err)
264{
265 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
266 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
267 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
268 char mcc_pl[MLXSW_REG_MCC_LEN];
269 u8 control_state;
270 u8 error_code;
271 int err;
272
273 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
274 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
275 if (err)
276 return err;
277
278 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
279 *fsm_state = control_state;
280 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
281 MLXFW_FSM_STATE_ERR_MAX);
282 return 0;
283}
284
285static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
286{
287 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
288 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
289 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
290 char mcc_pl[MLXSW_REG_MCC_LEN];
291
292 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
293 fwhandle, 0);
294 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
295}
296
297static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
298{
299 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
300 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
301 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
302 char mcc_pl[MLXSW_REG_MCC_LEN];
303
304 mlxsw_reg_mcc_pack(mcc_pl,
305 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
306 fwhandle, 0);
307 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
308}
309
310static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
311 .component_query = mlxsw_sp_component_query,
312 .fsm_lock = mlxsw_sp_fsm_lock,
313 .fsm_component_update = mlxsw_sp_fsm_component_update,
314 .fsm_block_download = mlxsw_sp_fsm_block_download,
315 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
316 .fsm_activate = mlxsw_sp_fsm_activate,
317 .fsm_query_state = mlxsw_sp_fsm_query_state,
318 .fsm_cancel = mlxsw_sp_fsm_cancel,
319 .fsm_release = mlxsw_sp_fsm_release
320};
321
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300322static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
323 const struct firmware *firmware)
324{
325 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
326 .mlxfw_dev = {
327 .ops = &mlxsw_sp_mlxfw_dev_ops,
328 .psid = mlxsw_sp->bus_info->psid,
329 .psid_size = strlen(mlxsw_sp->bus_info->psid),
330 },
331 .mlxsw_sp = mlxsw_sp
332 };
333
334 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
335}
336
Yotam Gigi6b742192017-05-23 21:56:29 +0200337static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
338{
339 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
Yotam Gigi6b742192017-05-23 21:56:29 +0200340 const struct firmware *firmware;
341 int err;
342
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100343 /* Validate driver & FW are compatible */
344 if (rev->major != MLXSW_FWREV_MAJOR) {
345 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
346 rev->major, MLXSW_FWREV_MAJOR);
347 return -EINVAL;
348 }
349 if (MLXSW_FWREV_MINOR_TO_BRANCH(rev->minor) ==
350 MLXSW_FWREV_MINOR_TO_BRANCH(MLXSW_FWREV_MINOR))
Yotam Gigi6b742192017-05-23 21:56:29 +0200351 return 0;
352
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100353 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200354 rev->major, rev->minor, rev->subminor);
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100355 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200356 MLXSW_SP_FW_FILENAME);
357
358 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
359 mlxsw_sp->bus_info->dev);
360 if (err) {
361 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
362 MLXSW_SP_FW_FILENAME);
363 return err;
364 }
365
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300366 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
Yotam Gigi6b742192017-05-23 21:56:29 +0200367 release_firmware(firmware);
368 return err;
369}
370
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100371int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
372 unsigned int counter_index, u64 *packets,
373 u64 *bytes)
374{
375 char mgpc_pl[MLXSW_REG_MGPC_LEN];
376 int err;
377
378 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200379 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100380 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
381 if (err)
382 return err;
Arkadi Sharshevsky7cfcbc72017-08-24 08:40:08 +0200383 if (packets)
384 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
385 if (bytes)
386 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100387 return 0;
388}
389
390static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
391 unsigned int counter_index)
392{
393 char mgpc_pl[MLXSW_REG_MGPC_LEN];
394
395 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200396 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100397 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
398}
399
400int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
401 unsigned int *p_counter_index)
402{
403 int err;
404
405 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
406 p_counter_index);
407 if (err)
408 return err;
409 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
410 if (err)
411 goto err_counter_clear;
412 return 0;
413
414err_counter_clear:
415 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
416 *p_counter_index);
417 return err;
418}
419
420void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
421 unsigned int counter_index)
422{
423 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
424 counter_index);
425}
426
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200427static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
428 const struct mlxsw_tx_info *tx_info)
429{
430 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
431
432 memset(txhdr, 0, MLXSW_TXHDR_LEN);
433
434 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
435 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
436 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
437 mlxsw_tx_hdr_swid_set(txhdr, 0);
438 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
439 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
440 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
441}
442
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200443int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
444 u8 state)
445{
446 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
447 enum mlxsw_reg_spms_state spms_state;
448 char *spms_pl;
449 int err;
450
451 switch (state) {
452 case BR_STATE_FORWARDING:
453 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
454 break;
455 case BR_STATE_LEARNING:
456 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
457 break;
458 case BR_STATE_LISTENING: /* fall-through */
459 case BR_STATE_DISABLED: /* fall-through */
460 case BR_STATE_BLOCKING:
461 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
462 break;
463 default:
464 BUG();
465 }
466
467 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
468 if (!spms_pl)
469 return -ENOMEM;
470 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
471 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
472
473 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
474 kfree(spms_pl);
475 return err;
476}
477
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200478static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
479{
Elad Raz5b090742016-10-28 21:35:46 +0200480 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200481 int err;
482
483 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
484 if (err)
485 return err;
486 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
487 return 0;
488}
489
Yotam Gigi763b4b72016-07-21 12:03:17 +0200490static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
491{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200492 int i;
493
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200494 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
Yotam Gigi763b4b72016-07-21 12:03:17 +0200495 return -EIO;
496
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200497 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
498 MAX_SPAN);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200499 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
500 sizeof(struct mlxsw_sp_span_entry),
501 GFP_KERNEL);
502 if (!mlxsw_sp->span.entries)
503 return -ENOMEM;
504
505 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
506 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
507
508 return 0;
509}
510
511static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
512{
513 int i;
514
515 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
516 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
517
518 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
519 }
520 kfree(mlxsw_sp->span.entries);
521}
522
523static struct mlxsw_sp_span_entry *
524mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
525{
526 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
527 struct mlxsw_sp_span_entry *span_entry;
528 char mpat_pl[MLXSW_REG_MPAT_LEN];
529 u8 local_port = port->local_port;
530 int index;
531 int i;
532 int err;
533
534 /* find a free entry to use */
535 index = -1;
536 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
Petr Machatace470b42018-02-13 11:27:47 +0100537 if (!mlxsw_sp->span.entries[i].ref_count) {
Yotam Gigi763b4b72016-07-21 12:03:17 +0200538 index = i;
539 span_entry = &mlxsw_sp->span.entries[i];
540 break;
541 }
542 }
543 if (index < 0)
544 return NULL;
545
546 /* create a new port analayzer entry for local_port */
547 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
548 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
549 if (err)
550 return NULL;
551
Yotam Gigi763b4b72016-07-21 12:03:17 +0200552 span_entry->id = index;
Yotam Gigi2d644d42016-11-11 16:34:25 +0100553 span_entry->ref_count = 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200554 span_entry->local_port = local_port;
555 return span_entry;
556}
557
558static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
559 struct mlxsw_sp_span_entry *span_entry)
560{
561 u8 local_port = span_entry->local_port;
562 char mpat_pl[MLXSW_REG_MPAT_LEN];
563 int pa_id = span_entry->id;
564
565 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
566 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200567}
568
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100569struct mlxsw_sp_span_entry *
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200570mlxsw_sp_span_entry_find(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200571{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200572 int i;
573
574 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
575 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
576
Petr Machatace470b42018-02-13 11:27:47 +0100577 if (curr->ref_count && curr->local_port == local_port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200578 return curr;
579 }
580 return NULL;
581}
582
Petr Machata306a9342018-02-13 11:27:46 +0100583static struct mlxsw_sp_span_entry *
584mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200585{
586 struct mlxsw_sp_span_entry *span_entry;
587
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200588 span_entry = mlxsw_sp_span_entry_find(port->mlxsw_sp,
589 port->local_port);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200590 if (span_entry) {
Yotam Gigi2d644d42016-11-11 16:34:25 +0100591 /* Already exists, just take a reference */
Yotam Gigi763b4b72016-07-21 12:03:17 +0200592 span_entry->ref_count++;
593 return span_entry;
594 }
595
596 return mlxsw_sp_span_entry_create(port);
597}
598
599static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
600 struct mlxsw_sp_span_entry *span_entry)
601{
Yotam Gigi2d644d42016-11-11 16:34:25 +0100602 WARN_ON(!span_entry->ref_count);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200603 if (--span_entry->ref_count == 0)
604 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
605 return 0;
606}
607
608static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
609{
610 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
611 struct mlxsw_sp_span_inspected_port *p;
612 int i;
613
614 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
615 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
616
617 list_for_each_entry(p, &curr->bound_ports_list, list)
618 if (p->local_port == port->local_port &&
619 p->type == MLXSW_SP_SPAN_EGRESS)
620 return true;
621 }
622
623 return false;
624}
625
Ido Schimmel18281f22017-03-24 08:02:51 +0100626static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
627 int mtu)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200628{
Ido Schimmel18281f22017-03-24 08:02:51 +0100629 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200630}
631
632static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
633{
634 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
635 char sbib_pl[MLXSW_REG_SBIB_LEN];
636 int err;
637
638 /* If port is egress mirrored, the shared buffer size should be
639 * updated according to the mtu value
640 */
641 if (mlxsw_sp_span_is_egress_mirror(port)) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100642 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
643
644 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200645 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
646 if (err) {
647 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
648 return err;
649 }
650 }
651
652 return 0;
653}
654
655static struct mlxsw_sp_span_inspected_port *
656mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
657 struct mlxsw_sp_span_entry *span_entry)
658{
659 struct mlxsw_sp_span_inspected_port *p;
660
661 list_for_each_entry(p, &span_entry->bound_ports_list, list)
662 if (port->local_port == p->local_port)
663 return p;
664 return NULL;
665}
666
667static int
668mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
669 struct mlxsw_sp_span_entry *span_entry,
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100670 enum mlxsw_sp_span_type type,
671 bool bind)
672{
673 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
674 char mpar_pl[MLXSW_REG_MPAR_LEN];
675 int pa_id = span_entry->id;
676
677 /* bind the port to the SPAN entry */
678 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
679 (enum mlxsw_reg_mpar_i_e) type, bind, pa_id);
680 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
681}
682
683static int
684mlxsw_sp_span_inspected_port_add(struct mlxsw_sp_port *port,
685 struct mlxsw_sp_span_entry *span_entry,
686 enum mlxsw_sp_span_type type,
687 bool bind)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200688{
689 struct mlxsw_sp_span_inspected_port *inspected_port;
690 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200691 char sbib_pl[MLXSW_REG_SBIB_LEN];
Yotam Gigi763b4b72016-07-21 12:03:17 +0200692 int err;
693
694 /* if it is an egress SPAN, bind a shared buffer to it */
695 if (type == MLXSW_SP_SPAN_EGRESS) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100696 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
697 port->dev->mtu);
698
699 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200700 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
701 if (err) {
702 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
703 return err;
704 }
705 }
706
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100707 if (bind) {
708 err = mlxsw_sp_span_inspected_port_bind(port, span_entry, type,
709 true);
710 if (err)
711 goto err_port_bind;
712 }
Yotam Gigi763b4b72016-07-21 12:03:17 +0200713
714 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
715 if (!inspected_port) {
716 err = -ENOMEM;
717 goto err_inspected_port_alloc;
718 }
719 inspected_port->local_port = port->local_port;
720 inspected_port->type = type;
721 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
722
723 return 0;
724
Yotam Gigi763b4b72016-07-21 12:03:17 +0200725err_inspected_port_alloc:
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100726 if (bind)
727 mlxsw_sp_span_inspected_port_bind(port, span_entry, type,
728 false);
729err_port_bind:
Yotam Gigi763b4b72016-07-21 12:03:17 +0200730 if (type == MLXSW_SP_SPAN_EGRESS) {
731 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
732 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
733 }
734 return err;
735}
736
737static void
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100738mlxsw_sp_span_inspected_port_del(struct mlxsw_sp_port *port,
739 struct mlxsw_sp_span_entry *span_entry,
740 enum mlxsw_sp_span_type type,
741 bool bind)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200742{
743 struct mlxsw_sp_span_inspected_port *inspected_port;
744 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200745 char sbib_pl[MLXSW_REG_SBIB_LEN];
Yotam Gigi763b4b72016-07-21 12:03:17 +0200746
747 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
748 if (!inspected_port)
749 return;
750
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100751 if (bind)
752 mlxsw_sp_span_inspected_port_bind(port, span_entry, type,
753 false);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200754 /* remove the SBIB buffer if it was egress SPAN */
755 if (type == MLXSW_SP_SPAN_EGRESS) {
756 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
757 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
758 }
759
760 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
761
762 list_del(&inspected_port->list);
763 kfree(inspected_port);
764}
765
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100766int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
767 struct mlxsw_sp_port *to,
768 enum mlxsw_sp_span_type type, bool bind)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200769{
770 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
771 struct mlxsw_sp_span_entry *span_entry;
772 int err;
773
774 span_entry = mlxsw_sp_span_entry_get(to);
775 if (!span_entry)
776 return -ENOENT;
777
778 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
779 span_entry->id);
780
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100781 err = mlxsw_sp_span_inspected_port_add(from, span_entry, type, bind);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200782 if (err)
783 goto err_port_bind;
784
785 return 0;
786
787err_port_bind:
788 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
789 return err;
790}
791
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100792void mlxsw_sp_span_mirror_del(struct mlxsw_sp_port *from, u8 destination_port,
793 enum mlxsw_sp_span_type type, bool bind)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200794{
795 struct mlxsw_sp_span_entry *span_entry;
796
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200797 span_entry = mlxsw_sp_span_entry_find(from->mlxsw_sp,
798 destination_port);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200799 if (!span_entry) {
800 netdev_err(from->dev, "no span entry found\n");
801 return;
802 }
803
804 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
805 span_entry->id);
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100806 mlxsw_sp_span_inspected_port_del(from, span_entry, type, bind);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200807}
808
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100809static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
810 bool enable, u32 rate)
811{
812 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
813 char mpsc_pl[MLXSW_REG_MPSC_LEN];
814
815 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
816 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
817}
818
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200819static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
820 bool is_up)
821{
822 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
823 char paos_pl[MLXSW_REG_PAOS_LEN];
824
825 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
826 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
827 MLXSW_PORT_ADMIN_STATUS_DOWN);
828 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
829}
830
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200831static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
832 unsigned char *addr)
833{
834 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
835 char ppad_pl[MLXSW_REG_PPAD_LEN];
836
837 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
838 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
839 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
840}
841
842static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
843{
844 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
845 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
846
847 ether_addr_copy(addr, mlxsw_sp->base_mac);
848 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
849 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
850}
851
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200852static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
853{
854 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
855 char pmtu_pl[MLXSW_REG_PMTU_LEN];
856 int max_mtu;
857 int err;
858
859 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
860 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
861 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
862 if (err)
863 return err;
864 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
865
866 if (mtu > max_mtu)
867 return -EINVAL;
868
869 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
870 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
871}
872
873static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
874{
875 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel5b153852017-06-08 08:47:44 +0200876 char pspa_pl[MLXSW_REG_PSPA_LEN];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200877
Ido Schimmel5b153852017-06-08 08:47:44 +0200878 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
879 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200880}
881
Ido Schimmela1107482017-05-26 08:37:39 +0200882int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200883{
884 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
885 char svpe_pl[MLXSW_REG_SVPE_LEN];
886
887 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
888 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
889}
890
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200891int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
892 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200893{
894 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
895 char *spvmlr_pl;
896 int err;
897
898 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
899 if (!spvmlr_pl)
900 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200901 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
902 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200903 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
904 kfree(spvmlr_pl);
905 return err;
906}
907
Ido Schimmelb02eae92017-05-16 19:38:34 +0200908static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
909 u16 vid)
910{
911 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
912 char spvid_pl[MLXSW_REG_SPVID_LEN];
913
914 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
915 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
916}
917
918static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
919 bool allow)
920{
921 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
922 char spaft_pl[MLXSW_REG_SPAFT_LEN];
923
924 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
925 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
926}
927
928int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
929{
930 int err;
931
932 if (!vid) {
933 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
934 if (err)
935 return err;
936 } else {
937 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
938 if (err)
939 return err;
940 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
941 if (err)
942 goto err_port_allow_untagged_set;
943 }
944
945 mlxsw_sp_port->pvid = vid;
946 return 0;
947
948err_port_allow_untagged_set:
949 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
950 return err;
951}
952
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200953static int
954mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
955{
956 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
957 char sspr_pl[MLXSW_REG_SSPR_LEN];
958
959 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
960 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
961}
962
Ido Schimmeld664b412016-06-09 09:51:40 +0200963static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
964 u8 local_port, u8 *p_module,
965 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200966{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200967 char pmlp_pl[MLXSW_REG_PMLP_LEN];
968 int err;
969
Ido Schimmel558c2d52016-02-26 17:32:29 +0100970 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200971 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
972 if (err)
973 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100974 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
975 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200976 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200977 return 0;
978}
979
Ido Schimmel2e915e02017-06-08 08:47:45 +0200980static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100981 u8 module, u8 width, u8 lane)
982{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200983 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel18f1e702016-02-26 17:32:31 +0100984 char pmlp_pl[MLXSW_REG_PMLP_LEN];
985 int i;
986
Ido Schimmel2e915e02017-06-08 08:47:45 +0200987 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel18f1e702016-02-26 17:32:31 +0100988 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
989 for (i = 0; i < width; i++) {
990 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
991 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
992 }
993
994 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
995}
996
Ido Schimmel2e915e02017-06-08 08:47:45 +0200997static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100998{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200999 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01001000 char pmlp_pl[MLXSW_REG_PMLP_LEN];
1001
Ido Schimmel2e915e02017-06-08 08:47:45 +02001002 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01001003 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
1004 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
1005}
1006
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001007static int mlxsw_sp_port_open(struct net_device *dev)
1008{
1009 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1010 int err;
1011
1012 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1013 if (err)
1014 return err;
1015 netif_start_queue(dev);
1016 return 0;
1017}
1018
1019static int mlxsw_sp_port_stop(struct net_device *dev)
1020{
1021 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1022
1023 netif_stop_queue(dev);
1024 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1025}
1026
1027static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
1028 struct net_device *dev)
1029{
1030 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1031 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1032 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
1033 const struct mlxsw_tx_info tx_info = {
1034 .local_port = mlxsw_sp_port->local_port,
1035 .is_emad = false,
1036 };
1037 u64 len;
1038 int err;
1039
Jiri Pirko307c2432016-04-08 19:11:22 +02001040 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001041 return NETDEV_TX_BUSY;
1042
1043 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
1044 struct sk_buff *skb_orig = skb;
1045
1046 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
1047 if (!skb) {
1048 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1049 dev_kfree_skb_any(skb_orig);
1050 return NETDEV_TX_OK;
1051 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +01001052 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001053 }
1054
1055 if (eth_skb_pad(skb)) {
1056 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1057 return NETDEV_TX_OK;
1058 }
1059
1060 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +02001061 /* TX header is consumed by HW on the way so we shouldn't count its
1062 * bytes as being sent.
1063 */
1064 len = skb->len - MLXSW_TXHDR_LEN;
1065
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001066 /* Due to a race we might fail here because of a full queue. In that
1067 * unlikely case we simply drop the packet.
1068 */
Jiri Pirko307c2432016-04-08 19:11:22 +02001069 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001070
1071 if (!err) {
1072 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
1073 u64_stats_update_begin(&pcpu_stats->syncp);
1074 pcpu_stats->tx_packets++;
1075 pcpu_stats->tx_bytes += len;
1076 u64_stats_update_end(&pcpu_stats->syncp);
1077 } else {
1078 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1079 dev_kfree_skb_any(skb);
1080 }
1081 return NETDEV_TX_OK;
1082}
1083
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001084static void mlxsw_sp_set_rx_mode(struct net_device *dev)
1085{
1086}
1087
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001088static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
1089{
1090 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1091 struct sockaddr *addr = p;
1092 int err;
1093
1094 if (!is_valid_ether_addr(addr->sa_data))
1095 return -EADDRNOTAVAIL;
1096
1097 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
1098 if (err)
1099 return err;
1100 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1101 return 0;
1102}
1103
Ido Schimmel18281f22017-03-24 08:02:51 +01001104static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
1105 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001106{
Ido Schimmel18281f22017-03-24 08:02:51 +01001107 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001108}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001109
Ido Schimmelf417f042017-03-24 08:02:50 +01001110#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +01001111
1112static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1113 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +01001114{
Ido Schimmel18281f22017-03-24 08:02:51 +01001115 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
1116 BITS_PER_BYTE));
1117 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
1118 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001119}
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001120
Ido Schimmel18281f22017-03-24 08:02:51 +01001121/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +01001122 * Assumes 100m cable and maximum MTU.
1123 */
Ido Schimmel18281f22017-03-24 08:02:51 +01001124#define MLXSW_SP_PAUSE_DELAY 58752
1125
1126static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1127 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +01001128{
1129 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +01001130 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +01001131 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +01001132 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001133 else
Ido Schimmelf417f042017-03-24 08:02:50 +01001134 return 0;
1135}
1136
1137static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
1138 bool lossy)
1139{
1140 if (lossy)
1141 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
1142 else
1143 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
1144 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001145}
1146
1147int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001148 u8 *prio_tc, bool pause_en,
1149 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +02001150{
1151 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001152 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
1153 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001154 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001155 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001156
1157 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
1158 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1159 if (err)
1160 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001161
1162 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1163 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001164 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +01001165 bool lossy;
1166 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001167
1168 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
1169 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001170 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001171 configure = true;
1172 break;
1173 }
1174 }
1175
1176 if (!configure)
1177 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +01001178
1179 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +01001180 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
1181 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
1182 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +01001183 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001184 }
1185
Ido Schimmelff6551e2016-04-06 17:10:03 +02001186 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1187}
1188
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001189static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001190 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001191{
1192 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
1193 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001194 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001195 u8 *prio_tc;
1196
1197 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001198 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001199
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001200 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001201 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001202}
1203
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001204static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
1205{
1206 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001207 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001208 int err;
1209
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001210 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001211 if (err)
1212 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001213 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1214 if (err)
1215 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001216 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1217 if (err)
1218 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001219 dev->mtu = mtu;
1220 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001221
1222err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001223 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1224err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001225 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +02001226 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001227}
1228
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001229static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001230mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1231 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001232{
1233 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1234 struct mlxsw_sp_port_pcpu_stats *p;
1235 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1236 u32 tx_dropped = 0;
1237 unsigned int start;
1238 int i;
1239
1240 for_each_possible_cpu(i) {
1241 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1242 do {
1243 start = u64_stats_fetch_begin_irq(&p->syncp);
1244 rx_packets = p->rx_packets;
1245 rx_bytes = p->rx_bytes;
1246 tx_packets = p->tx_packets;
1247 tx_bytes = p->tx_bytes;
1248 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1249
1250 stats->rx_packets += rx_packets;
1251 stats->rx_bytes += rx_bytes;
1252 stats->tx_packets += tx_packets;
1253 stats->tx_bytes += tx_bytes;
1254 /* tx_dropped is u32, updated without syncp protection. */
1255 tx_dropped += p->tx_dropped;
1256 }
1257 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001258 return 0;
1259}
1260
Or Gerlitz3df5b3c2016-11-22 23:09:54 +02001261static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001262{
1263 switch (attr_id) {
1264 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1265 return true;
1266 }
1267
1268 return false;
1269}
1270
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001271static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1272 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001273{
1274 switch (attr_id) {
1275 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1276 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1277 }
1278
1279 return -EINVAL;
1280}
1281
1282static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1283 int prio, char *ppcnt_pl)
1284{
1285 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1286 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1287
1288 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1289 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1290}
1291
1292static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1293 struct rtnl_link_stats64 *stats)
1294{
1295 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1296 int err;
1297
1298 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1299 0, ppcnt_pl);
1300 if (err)
1301 goto out;
1302
1303 stats->tx_packets =
1304 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1305 stats->rx_packets =
1306 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1307 stats->tx_bytes =
1308 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1309 stats->rx_bytes =
1310 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1311 stats->multicast =
1312 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1313
1314 stats->rx_crc_errors =
1315 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1316 stats->rx_frame_errors =
1317 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1318
1319 stats->rx_length_errors = (
1320 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1321 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1322 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1323
1324 stats->rx_errors = (stats->rx_crc_errors +
1325 stats->rx_frame_errors + stats->rx_length_errors);
1326
1327out:
1328 return err;
1329}
1330
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001331static void
1332mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1333 struct mlxsw_sp_port_xstats *xstats)
1334{
1335 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1336 int err, i;
1337
1338 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1339 ppcnt_pl);
1340 if (!err)
1341 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1342
1343 for (i = 0; i < TC_MAX_QUEUE; i++) {
1344 err = mlxsw_sp_port_get_stats_raw(dev,
1345 MLXSW_REG_PPCNT_TC_CONG_TC,
1346 i, ppcnt_pl);
1347 if (!err)
1348 xstats->wred_drop[i] =
1349 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1350
1351 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1352 i, ppcnt_pl);
1353 if (err)
1354 continue;
1355
1356 xstats->backlog[i] =
1357 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1358 xstats->tail_drop[i] =
1359 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1360 }
1361}
1362
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001363static void update_stats_cache(struct work_struct *work)
1364{
1365 struct mlxsw_sp_port *mlxsw_sp_port =
1366 container_of(work, struct mlxsw_sp_port,
Nogah Frankel9deef432017-10-26 10:55:32 +02001367 periodic_hw_stats.update_dw.work);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001368
1369 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1370 goto out;
1371
1372 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
Nogah Frankel9deef432017-10-26 10:55:32 +02001373 &mlxsw_sp_port->periodic_hw_stats.stats);
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001374 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1375 &mlxsw_sp_port->periodic_hw_stats.xstats);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001376
1377out:
Nogah Frankel9deef432017-10-26 10:55:32 +02001378 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001379 MLXSW_HW_STATS_UPDATE_TIME);
1380}
1381
1382/* Return the stats from a cache that is updated periodically,
1383 * as this function might get called in an atomic context.
1384 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001385static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001386mlxsw_sp_port_get_stats64(struct net_device *dev,
1387 struct rtnl_link_stats64 *stats)
1388{
1389 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1390
Nogah Frankel9deef432017-10-26 10:55:32 +02001391 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001392}
1393
Jiri Pirko93cd0812017-04-18 16:55:35 +02001394static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1395 u16 vid_begin, u16 vid_end,
1396 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001397{
1398 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1399 char *spvm_pl;
1400 int err;
1401
1402 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1403 if (!spvm_pl)
1404 return -ENOMEM;
1405
1406 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1407 vid_end, is_member, untagged);
1408 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1409 kfree(spvm_pl);
1410 return err;
1411}
1412
Jiri Pirko93cd0812017-04-18 16:55:35 +02001413int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1414 u16 vid_end, bool is_member, bool untagged)
1415{
1416 u16 vid, vid_e;
1417 int err;
1418
1419 for (vid = vid_begin; vid <= vid_end;
1420 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1421 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1422 vid_end);
1423
1424 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1425 is_member, untagged);
1426 if (err)
1427 return err;
1428 }
1429
1430 return 0;
1431}
1432
Ido Schimmelc57529e2017-05-26 08:37:31 +02001433static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001434{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001435 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001436
Ido Schimmelc57529e2017-05-26 08:37:31 +02001437 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1438 &mlxsw_sp_port->vlans_list, list)
1439 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001440}
1441
Ido Schimmel31a08a52017-05-26 08:37:26 +02001442static struct mlxsw_sp_port_vlan *
1443mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1444{
1445 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001446 bool untagged = vid == 1;
1447 int err;
1448
1449 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1450 if (err)
1451 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001452
1453 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001454 if (!mlxsw_sp_port_vlan) {
1455 err = -ENOMEM;
1456 goto err_port_vlan_alloc;
1457 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02001458
1459 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1460 mlxsw_sp_port_vlan->vid = vid;
1461 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1462
1463 return mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001464
1465err_port_vlan_alloc:
1466 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1467 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001468}
1469
1470static void
1471mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1472{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001473 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1474 u16 vid = mlxsw_sp_port_vlan->vid;
Ido Schimmel7cbecf22017-05-26 08:37:28 +02001475
Ido Schimmel31a08a52017-05-26 08:37:26 +02001476 list_del(&mlxsw_sp_port_vlan->list);
1477 kfree(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001478 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1479}
1480
1481struct mlxsw_sp_port_vlan *
1482mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1483{
1484 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1485
1486 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1487 if (mlxsw_sp_port_vlan)
1488 return mlxsw_sp_port_vlan;
1489
1490 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1491}
1492
1493void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1494{
Ido Schimmela1107482017-05-26 08:37:39 +02001495 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1496
Ido Schimmelc57529e2017-05-26 08:37:31 +02001497 if (mlxsw_sp_port_vlan->bridge_port)
1498 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
Ido Schimmela1107482017-05-26 08:37:39 +02001499 else if (fid)
1500 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001501
1502 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001503}
1504
Ido Schimmel05978482016-08-17 16:39:30 +02001505static int mlxsw_sp_port_add_vid(struct net_device *dev,
1506 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001507{
1508 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001509
1510 /* VLAN 0 is added to HW filter when device goes up, but it is
1511 * reserved in our case, so simply return.
1512 */
1513 if (!vid)
1514 return 0;
1515
Ido Schimmelc57529e2017-05-26 08:37:31 +02001516 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001517}
1518
Ido Schimmel32d863f2016-07-02 11:00:10 +02001519static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1520 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001521{
1522 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001523 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001524
1525 /* VLAN 0 is removed from HW filter when device goes down, but
1526 * it is reserved in our case, so simply return.
1527 */
1528 if (!vid)
1529 return 0;
1530
Ido Schimmel31a08a52017-05-26 08:37:26 +02001531 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001532 if (!mlxsw_sp_port_vlan)
Ido Schimmel31a08a52017-05-26 08:37:26 +02001533 return 0;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001534 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001535
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001536 return 0;
1537}
1538
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001539static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1540 size_t len)
1541{
1542 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +02001543 u8 module = mlxsw_sp_port->mapping.module;
1544 u8 width = mlxsw_sp_port->mapping.width;
1545 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001546 int err;
1547
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001548 if (!mlxsw_sp_port->split)
1549 err = snprintf(name, len, "p%d", module + 1);
1550 else
1551 err = snprintf(name, len, "p%ds%d", module + 1,
1552 lane / width);
1553
1554 if (err >= len)
1555 return -EINVAL;
1556
1557 return 0;
1558}
1559
Yotam Gigi763b4b72016-07-21 12:03:17 +02001560static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001561mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1562 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001563 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1564
1565 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1566 if (mall_tc_entry->cookie == cookie)
1567 return mall_tc_entry;
1568
1569 return NULL;
1570}
1571
1572static int
1573mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001574 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001575 const struct tc_action *a,
1576 bool ingress)
1577{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001578 enum mlxsw_sp_span_type span_type;
1579 struct mlxsw_sp_port *to_port;
1580 struct net_device *to_dev;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001581
Cong Wang9f8a7392017-12-05 16:17:26 -08001582 to_dev = tcf_mirred_dev(a);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001583 if (!to_dev) {
1584 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1585 return -EINVAL;
1586 }
1587
1588 if (!mlxsw_sp_port_dev_check(to_dev)) {
1589 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
Yotam Gigie915ac62017-01-09 11:25:48 +01001590 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001591 }
1592 to_port = netdev_priv(to_dev);
1593
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001594 mirror->to_local_port = to_port->local_port;
1595 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001596 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +01001597 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type,
1598 true);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001599}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001600
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001601static void
1602mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1603 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1604{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001605 enum mlxsw_sp_span_type span_type;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001606
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001607 span_type = mirror->ingress ?
1608 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +01001609 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->to_local_port,
1610 span_type, true);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001611}
1612
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001613static int
1614mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1615 struct tc_cls_matchall_offload *cls,
1616 const struct tc_action *a,
1617 bool ingress)
1618{
1619 int err;
1620
1621 if (!mlxsw_sp_port->sample)
1622 return -EOPNOTSUPP;
1623 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1624 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1625 return -EEXIST;
1626 }
1627 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1628 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1629 return -EOPNOTSUPP;
1630 }
1631
1632 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1633 tcf_sample_psample_group(a));
1634 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1635 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1636 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1637
1638 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1639 if (err)
1640 goto err_port_sample_set;
1641 return 0;
1642
1643err_port_sample_set:
1644 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1645 return err;
1646}
1647
1648static void
1649mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1650{
1651 if (!mlxsw_sp_port->sample)
1652 return;
1653
1654 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1655 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1656}
1657
Yotam Gigi763b4b72016-07-21 12:03:17 +02001658static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001659 struct tc_cls_matchall_offload *f,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001660 bool ingress)
1661{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001662 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001663 __be16 protocol = f->common.protocol;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001664 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001665 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001666 int err;
1667
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001668 if (!tcf_exts_has_one_action(f->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001669 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001670 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001671 }
1672
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001673 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1674 if (!mall_tc_entry)
1675 return -ENOMEM;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001676 mall_tc_entry->cookie = f->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001677
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001678 tcf_exts_to_list(f->exts, &actions);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001679 a = list_first_entry(&actions, struct tc_action, list);
1680
1681 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1682 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1683
1684 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1685 mirror = &mall_tc_entry->mirror;
1686 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1687 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001688 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1689 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001690 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001691 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001692 } else {
1693 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001694 }
1695
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001696 if (err)
1697 goto err_add_action;
1698
1699 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001700 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001701
1702err_add_action:
1703 kfree(mall_tc_entry);
1704 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001705}
1706
1707static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001708 struct tc_cls_matchall_offload *f)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001709{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001710 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001711
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001712 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001713 f->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001714 if (!mall_tc_entry) {
1715 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1716 return;
1717 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001718 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001719
1720 switch (mall_tc_entry->type) {
1721 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001722 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1723 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001724 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001725 case MLXSW_SP_PORT_MALL_SAMPLE:
1726 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1727 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001728 default:
1729 WARN_ON(1);
1730 }
1731
Yotam Gigi763b4b72016-07-21 12:03:17 +02001732 kfree(mall_tc_entry);
1733}
1734
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001735static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001736 struct tc_cls_matchall_offload *f,
1737 bool ingress)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001738{
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001739 switch (f->command) {
1740 case TC_CLSMATCHALL_REPLACE:
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001741 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001742 ingress);
1743 case TC_CLSMATCHALL_DESTROY:
1744 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1745 return 0;
1746 default:
1747 return -EOPNOTSUPP;
1748 }
1749}
1750
1751static int
Jiri Pirko3aaff322018-01-17 11:46:56 +01001752mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1753 struct tc_cls_flower_offload *f)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001754{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001755 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1756
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001757 switch (f->command) {
1758 case TC_CLSFLOWER_REPLACE:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001759 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001760 case TC_CLSFLOWER_DESTROY:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001761 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001762 return 0;
1763 case TC_CLSFLOWER_STATS:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001764 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001765 default:
1766 return -EOPNOTSUPP;
1767 }
1768}
1769
Jiri Pirko3aaff322018-01-17 11:46:56 +01001770static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1771 void *type_data,
1772 void *cb_priv, bool ingress)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001773{
1774 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1775
1776 switch (type) {
1777 case TC_SETUP_CLSMATCHALL:
Jakub Kicinski15f4edb2018-01-25 14:00:51 -08001778 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1779 type_data))
Jiri Pirko3aaff322018-01-17 11:46:56 +01001780 return -EOPNOTSUPP;
1781
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001782 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1783 ingress);
1784 case TC_SETUP_CLSFLOWER:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001785 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001786 default:
1787 return -EOPNOTSUPP;
1788 }
1789}
1790
Jiri Pirko3aaff322018-01-17 11:46:56 +01001791static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1792 void *type_data,
1793 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001794{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001795 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1796 cb_priv, true);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001797}
1798
Jiri Pirko3aaff322018-01-17 11:46:56 +01001799static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1800 void *type_data,
1801 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001802{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001803 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1804 cb_priv, false);
1805}
1806
1807static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1808 void *type_data, void *cb_priv)
1809{
1810 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1811
1812 switch (type) {
1813 case TC_SETUP_CLSMATCHALL:
1814 return 0;
1815 case TC_SETUP_CLSFLOWER:
1816 if (mlxsw_sp_acl_block_disabled(acl_block))
1817 return -EOPNOTSUPP;
1818
1819 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1820 default:
1821 return -EOPNOTSUPP;
1822 }
1823}
1824
1825static int
1826mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1827 struct tcf_block *block, bool ingress)
1828{
1829 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1830 struct mlxsw_sp_acl_block *acl_block;
1831 struct tcf_block_cb *block_cb;
1832 int err;
1833
1834 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1835 mlxsw_sp);
1836 if (!block_cb) {
1837 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1838 if (!acl_block)
1839 return -ENOMEM;
1840 block_cb = __tcf_block_cb_register(block,
1841 mlxsw_sp_setup_tc_block_cb_flower,
1842 mlxsw_sp, acl_block);
1843 if (IS_ERR(block_cb)) {
1844 err = PTR_ERR(block_cb);
1845 goto err_cb_register;
1846 }
1847 } else {
1848 acl_block = tcf_block_cb_priv(block_cb);
1849 }
1850 tcf_block_cb_incref(block_cb);
1851 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1852 mlxsw_sp_port, ingress);
1853 if (err)
1854 goto err_block_bind;
1855
1856 if (ingress)
1857 mlxsw_sp_port->ing_acl_block = acl_block;
1858 else
1859 mlxsw_sp_port->eg_acl_block = acl_block;
1860
1861 return 0;
1862
1863err_block_bind:
1864 if (!tcf_block_cb_decref(block_cb)) {
1865 __tcf_block_cb_unregister(block_cb);
1866err_cb_register:
1867 mlxsw_sp_acl_block_destroy(acl_block);
1868 }
1869 return err;
1870}
1871
1872static void
1873mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1874 struct tcf_block *block, bool ingress)
1875{
1876 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1877 struct mlxsw_sp_acl_block *acl_block;
1878 struct tcf_block_cb *block_cb;
1879 int err;
1880
1881 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1882 mlxsw_sp);
1883 if (!block_cb)
1884 return;
1885
1886 if (ingress)
1887 mlxsw_sp_port->ing_acl_block = NULL;
1888 else
1889 mlxsw_sp_port->eg_acl_block = NULL;
1890
1891 acl_block = tcf_block_cb_priv(block_cb);
1892 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1893 mlxsw_sp_port, ingress);
1894 if (!err && !tcf_block_cb_decref(block_cb)) {
1895 __tcf_block_cb_unregister(block_cb);
1896 mlxsw_sp_acl_block_destroy(acl_block);
1897 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001898}
1899
1900static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1901 struct tc_block_offload *f)
1902{
1903 tc_setup_cb_t *cb;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001904 bool ingress;
1905 int err;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001906
Jiri Pirko3aaff322018-01-17 11:46:56 +01001907 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1908 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1909 ingress = true;
1910 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1911 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1912 ingress = false;
1913 } else {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001914 return -EOPNOTSUPP;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001915 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001916
1917 switch (f->command) {
1918 case TC_BLOCK_BIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001919 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1920 mlxsw_sp_port);
1921 if (err)
1922 return err;
1923 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
1924 f->block, ingress);
1925 if (err) {
1926 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1927 return err;
1928 }
1929 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001930 case TC_BLOCK_UNBIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001931 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1932 f->block, ingress);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001933 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1934 return 0;
1935 default:
1936 return -EOPNOTSUPP;
1937 }
1938}
1939
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001940static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
Jiri Pirkode4784c2017-08-07 10:15:32 +02001941 void *type_data)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001942{
1943 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1944
Jiri Pirko2572ac52017-08-07 10:15:17 +02001945 switch (type) {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001946 case TC_SETUP_BLOCK:
1947 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
Nogah Frankel96f17e02017-11-06 07:23:45 +01001948 case TC_SETUP_QDISC_RED:
1949 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
Nogah Frankel46a36152018-01-14 12:33:16 +01001950 case TC_SETUP_QDISC_PRIO:
1951 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
Jiri Pirko2572ac52017-08-07 10:15:17 +02001952 default:
1953 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001954 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001955}
1956
Jiri Pirko9454d932017-12-06 09:41:12 +01001957
1958static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1959{
1960 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1961
Jiri Pirko3aaff322018-01-17 11:46:56 +01001962 if (!enable) {
1963 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1964 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1965 !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1966 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1967 return -EINVAL;
1968 }
1969 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1970 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1971 } else {
1972 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1973 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
Jiri Pirko9454d932017-12-06 09:41:12 +01001974 }
1975 return 0;
1976}
1977
1978typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1979
1980static int mlxsw_sp_handle_feature(struct net_device *dev,
1981 netdev_features_t wanted_features,
1982 netdev_features_t feature,
1983 mlxsw_sp_feature_handler feature_handler)
1984{
1985 netdev_features_t changes = wanted_features ^ dev->features;
1986 bool enable = !!(wanted_features & feature);
1987 int err;
1988
1989 if (!(changes & feature))
1990 return 0;
1991
1992 err = feature_handler(dev, enable);
1993 if (err) {
1994 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1995 enable ? "Enable" : "Disable", &feature, err);
1996 return err;
1997 }
1998
1999 if (enable)
2000 dev->features |= feature;
2001 else
2002 dev->features &= ~feature;
2003
2004 return 0;
2005}
2006static int mlxsw_sp_set_features(struct net_device *dev,
2007 netdev_features_t features)
2008{
2009 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
2010 mlxsw_sp_feature_hw_tc);
2011}
2012
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002013static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
2014 .ndo_open = mlxsw_sp_port_open,
2015 .ndo_stop = mlxsw_sp_port_stop,
2016 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02002017 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01002018 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002019 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
2020 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
2021 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002022 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
2023 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002024 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
2025 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02002026 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko9454d932017-12-06 09:41:12 +01002027 .ndo_set_features = mlxsw_sp_set_features,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002028};
2029
2030static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
2031 struct ethtool_drvinfo *drvinfo)
2032{
2033 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2034 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2035
2036 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
2037 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
2038 sizeof(drvinfo->version));
2039 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
2040 "%d.%d.%d",
2041 mlxsw_sp->bus_info->fw_rev.major,
2042 mlxsw_sp->bus_info->fw_rev.minor,
2043 mlxsw_sp->bus_info->fw_rev.subminor);
2044 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
2045 sizeof(drvinfo->bus_info));
2046}
2047
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002048static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
2049 struct ethtool_pauseparam *pause)
2050{
2051 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2052
2053 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
2054 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
2055}
2056
2057static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
2058 struct ethtool_pauseparam *pause)
2059{
2060 char pfcc_pl[MLXSW_REG_PFCC_LEN];
2061
2062 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
2063 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
2064 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
2065
2066 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
2067 pfcc_pl);
2068}
2069
2070static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
2071 struct ethtool_pauseparam *pause)
2072{
2073 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2074 bool pause_en = pause->tx_pause || pause->rx_pause;
2075 int err;
2076
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02002077 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
2078 netdev_err(dev, "PFC already enabled on port\n");
2079 return -EINVAL;
2080 }
2081
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002082 if (pause->autoneg) {
2083 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
2084 return -EINVAL;
2085 }
2086
2087 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
2088 if (err) {
2089 netdev_err(dev, "Failed to configure port's headroom\n");
2090 return err;
2091 }
2092
2093 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
2094 if (err) {
2095 netdev_err(dev, "Failed to set PAUSE parameters\n");
2096 goto err_port_pause_configure;
2097 }
2098
2099 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
2100 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
2101
2102 return 0;
2103
2104err_port_pause_configure:
2105 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
2106 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
2107 return err;
2108}
2109
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002110struct mlxsw_sp_port_hw_stats {
2111 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02002112 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01002113 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002114};
2115
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002116static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002117 {
2118 .str = "a_frames_transmitted_ok",
2119 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
2120 },
2121 {
2122 .str = "a_frames_received_ok",
2123 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
2124 },
2125 {
2126 .str = "a_frame_check_sequence_errors",
2127 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
2128 },
2129 {
2130 .str = "a_alignment_errors",
2131 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
2132 },
2133 {
2134 .str = "a_octets_transmitted_ok",
2135 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
2136 },
2137 {
2138 .str = "a_octets_received_ok",
2139 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
2140 },
2141 {
2142 .str = "a_multicast_frames_xmitted_ok",
2143 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
2144 },
2145 {
2146 .str = "a_broadcast_frames_xmitted_ok",
2147 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
2148 },
2149 {
2150 .str = "a_multicast_frames_received_ok",
2151 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
2152 },
2153 {
2154 .str = "a_broadcast_frames_received_ok",
2155 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
2156 },
2157 {
2158 .str = "a_in_range_length_errors",
2159 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
2160 },
2161 {
2162 .str = "a_out_of_range_length_field",
2163 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
2164 },
2165 {
2166 .str = "a_frame_too_long_errors",
2167 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
2168 },
2169 {
2170 .str = "a_symbol_error_during_carrier",
2171 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
2172 },
2173 {
2174 .str = "a_mac_control_frames_transmitted",
2175 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
2176 },
2177 {
2178 .str = "a_mac_control_frames_received",
2179 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
2180 },
2181 {
2182 .str = "a_unsupported_opcodes_received",
2183 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
2184 },
2185 {
2186 .str = "a_pause_mac_ctrl_frames_received",
2187 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
2188 },
2189 {
2190 .str = "a_pause_mac_ctrl_frames_xmitted",
2191 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
2192 },
2193};
2194
2195#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
2196
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002197static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
2198 {
2199 .str = "rx_octets_prio",
2200 .getter = mlxsw_reg_ppcnt_rx_octets_get,
2201 },
2202 {
2203 .str = "rx_frames_prio",
2204 .getter = mlxsw_reg_ppcnt_rx_frames_get,
2205 },
2206 {
2207 .str = "tx_octets_prio",
2208 .getter = mlxsw_reg_ppcnt_tx_octets_get,
2209 },
2210 {
2211 .str = "tx_frames_prio",
2212 .getter = mlxsw_reg_ppcnt_tx_frames_get,
2213 },
2214 {
2215 .str = "rx_pause_prio",
2216 .getter = mlxsw_reg_ppcnt_rx_pause_get,
2217 },
2218 {
2219 .str = "rx_pause_duration_prio",
2220 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2221 },
2222 {
2223 .str = "tx_pause_prio",
2224 .getter = mlxsw_reg_ppcnt_tx_pause_get,
2225 },
2226 {
2227 .str = "tx_pause_duration_prio",
2228 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2229 },
2230};
2231
2232#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2233
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002234static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2235 {
2236 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01002237 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2238 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002239 },
2240 {
2241 .str = "tc_no_buffer_discard_uc_tc",
2242 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2243 },
2244};
2245
2246#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2247
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002248#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002249 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
2250 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002251 IEEE_8021QAZ_MAX_TCS)
2252
2253static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2254{
2255 int i;
2256
2257 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2258 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2259 mlxsw_sp_port_hw_prio_stats[i].str, prio);
2260 *p += ETH_GSTRING_LEN;
2261 }
2262}
2263
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002264static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2265{
2266 int i;
2267
2268 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2269 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2270 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2271 *p += ETH_GSTRING_LEN;
2272 }
2273}
2274
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002275static void mlxsw_sp_port_get_strings(struct net_device *dev,
2276 u32 stringset, u8 *data)
2277{
2278 u8 *p = data;
2279 int i;
2280
2281 switch (stringset) {
2282 case ETH_SS_STATS:
2283 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2284 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2285 ETH_GSTRING_LEN);
2286 p += ETH_GSTRING_LEN;
2287 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002288
2289 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2290 mlxsw_sp_port_get_prio_strings(&p, i);
2291
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002292 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2293 mlxsw_sp_port_get_tc_strings(&p, i);
2294
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002295 break;
2296 }
2297}
2298
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002299static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2300 enum ethtool_phys_id_state state)
2301{
2302 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2303 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2304 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2305 bool active;
2306
2307 switch (state) {
2308 case ETHTOOL_ID_ACTIVE:
2309 active = true;
2310 break;
2311 case ETHTOOL_ID_INACTIVE:
2312 active = false;
2313 break;
2314 default:
2315 return -EOPNOTSUPP;
2316 }
2317
2318 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2319 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2320}
2321
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002322static int
2323mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2324 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2325{
2326 switch (grp) {
2327 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2328 *p_hw_stats = mlxsw_sp_port_hw_stats;
2329 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2330 break;
2331 case MLXSW_REG_PPCNT_PRIO_CNT:
2332 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2333 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2334 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002335 case MLXSW_REG_PPCNT_TC_CNT:
2336 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2337 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2338 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002339 default:
2340 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002341 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002342 }
2343 return 0;
2344}
2345
2346static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2347 enum mlxsw_reg_ppcnt_grp grp, int prio,
2348 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002349{
Ido Schimmel18281f22017-03-24 08:02:51 +01002350 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2351 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002352 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002353 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002354 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002355 int err;
2356
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002357 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2358 if (err)
2359 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002360 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002361 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002362 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002363 if (!hw_stats[i].cells_bytes)
2364 continue;
2365 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2366 data[data_index + i]);
2367 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002368}
2369
2370static void mlxsw_sp_port_get_stats(struct net_device *dev,
2371 struct ethtool_stats *stats, u64 *data)
2372{
2373 int i, data_index = 0;
2374
2375 /* IEEE 802.3 Counters */
2376 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2377 data, data_index);
2378 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2379
2380 /* Per-Priority Counters */
2381 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2382 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2383 data, data_index);
2384 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2385 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002386
2387 /* Per-TC Counters */
2388 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2389 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2390 data, data_index);
2391 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2392 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002393}
2394
2395static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2396{
2397 switch (sset) {
2398 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002399 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002400 default:
2401 return -EOPNOTSUPP;
2402 }
2403}
2404
2405struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002406 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002407 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002408 u32 speed;
2409};
2410
2411static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2412 {
2413 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002414 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2415 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002416 },
2417 {
2418 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2419 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002420 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2421 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002422 },
2423 {
2424 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002425 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2426 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002427 },
2428 {
2429 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2430 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002431 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2432 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002433 },
2434 {
2435 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2436 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2437 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2438 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002439 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2440 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002441 },
2442 {
2443 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002444 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2445 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002446 },
2447 {
2448 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002449 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2450 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002451 },
2452 {
2453 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002454 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2455 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002456 },
2457 {
2458 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002459 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2460 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002461 },
2462 {
2463 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002464 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2465 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002466 },
2467 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002468 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2469 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2470 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002471 },
2472 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002473 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2474 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2475 .speed = SPEED_25000,
2476 },
2477 {
2478 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2479 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2480 .speed = SPEED_25000,
2481 },
2482 {
2483 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2484 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2485 .speed = SPEED_25000,
2486 },
2487 {
2488 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2489 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2490 .speed = SPEED_50000,
2491 },
2492 {
2493 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2494 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2495 .speed = SPEED_50000,
2496 },
2497 {
2498 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2499 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2500 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002501 },
2502 {
2503 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002504 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2505 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002506 },
2507 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002508 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2509 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2510 .speed = SPEED_56000,
2511 },
2512 {
2513 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2514 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2515 .speed = SPEED_56000,
2516 },
2517 {
2518 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2519 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2520 .speed = SPEED_56000,
2521 },
2522 {
2523 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2524 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2525 .speed = SPEED_100000,
2526 },
2527 {
2528 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2529 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2530 .speed = SPEED_100000,
2531 },
2532 {
2533 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2534 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2535 .speed = SPEED_100000,
2536 },
2537 {
2538 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2539 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2540 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002541 },
2542};
2543
2544#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2545
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002546static void
2547mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2548 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002549{
2550 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2551 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2552 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2553 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2554 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2555 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002556 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002557
2558 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2559 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2560 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2561 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2562 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002563 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002564}
2565
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002566static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002567{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002568 int i;
2569
2570 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2571 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002572 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2573 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002574 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002575}
2576
2577static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002578 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002579{
2580 u32 speed = SPEED_UNKNOWN;
2581 u8 duplex = DUPLEX_UNKNOWN;
2582 int i;
2583
2584 if (!carrier_ok)
2585 goto out;
2586
2587 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2588 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2589 speed = mlxsw_sp_port_link_mode[i].speed;
2590 duplex = DUPLEX_FULL;
2591 break;
2592 }
2593 }
2594out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002595 cmd->base.speed = speed;
2596 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002597}
2598
2599static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2600{
2601 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2602 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2603 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2604 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2605 return PORT_FIBRE;
2606
2607 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2608 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2609 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2610 return PORT_DA;
2611
2612 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2613 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2614 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2615 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2616 return PORT_NONE;
2617
2618 return PORT_OTHER;
2619}
2620
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002621static u32
2622mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002623{
2624 u32 ptys_proto = 0;
2625 int i;
2626
2627 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002628 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2629 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002630 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2631 }
2632 return ptys_proto;
2633}
2634
2635static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2636{
2637 u32 ptys_proto = 0;
2638 int i;
2639
2640 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2641 if (speed == mlxsw_sp_port_link_mode[i].speed)
2642 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2643 }
2644 return ptys_proto;
2645}
2646
Ido Schimmel18f1e702016-02-26 17:32:31 +01002647static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2648{
2649 u32 ptys_proto = 0;
2650 int i;
2651
2652 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2653 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2654 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2655 }
2656 return ptys_proto;
2657}
2658
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002659static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2660 struct ethtool_link_ksettings *cmd)
2661{
2662 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2663 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2664 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2665
2666 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2667 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2668}
2669
2670static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2671 struct ethtool_link_ksettings *cmd)
2672{
2673 if (!autoneg)
2674 return;
2675
2676 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2677 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2678}
2679
2680static void
2681mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2682 struct ethtool_link_ksettings *cmd)
2683{
2684 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2685 return;
2686
2687 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2688 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2689}
2690
2691static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2692 struct ethtool_link_ksettings *cmd)
2693{
2694 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2695 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2696 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2697 char ptys_pl[MLXSW_REG_PTYS_LEN];
2698 u8 autoneg_status;
2699 bool autoneg;
2700 int err;
2701
2702 autoneg = mlxsw_sp_port->link.autoneg;
Elad Raz401c8b42016-10-28 21:35:52 +02002703 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002704 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2705 if (err)
2706 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002707 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2708 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002709
2710 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2711
2712 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2713
2714 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2715 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2716 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2717
2718 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2719 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2720 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2721 cmd);
2722
2723 return 0;
2724}
2725
2726static int
2727mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2728 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002729{
2730 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2731 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2732 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002733 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002734 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002735 int err;
2736
Elad Raz401c8b42016-10-28 21:35:52 +02002737 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002738 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002739 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002740 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002741 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002742
2743 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2744 eth_proto_new = autoneg ?
2745 mlxsw_sp_to_ptys_advert_link(cmd) :
2746 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002747
2748 eth_proto_new = eth_proto_new & eth_proto_cap;
2749 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002750 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002751 return -EINVAL;
2752 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002753
Elad Raz401c8b42016-10-28 21:35:52 +02002754 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2755 eth_proto_new);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002756 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002757 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002758 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002759
Ido Schimmel6277d462016-07-15 11:14:58 +02002760 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002761 return 0;
2762
Ido Schimmel0c83f882016-09-12 13:26:23 +02002763 mlxsw_sp_port->link.autoneg = autoneg;
2764
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002765 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2766 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002767
2768 return 0;
2769}
2770
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002771static int mlxsw_sp_flash_device(struct net_device *dev,
2772 struct ethtool_flash *flash)
2773{
2774 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2775 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2776 const struct firmware *firmware;
2777 int err;
2778
2779 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2780 return -EOPNOTSUPP;
2781
2782 dev_hold(dev);
2783 rtnl_unlock();
2784
2785 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2786 if (err)
2787 goto out;
2788 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2789 release_firmware(firmware);
2790out:
2791 rtnl_lock();
2792 dev_put(dev);
2793 return err;
2794}
2795
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002796#define MLXSW_SP_I2C_ADDR_LOW 0x50
2797#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2798#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002799
2800static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2801 u16 offset, u16 size, void *data,
2802 unsigned int *p_read_size)
2803{
2804 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2805 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2806 char mcia_pl[MLXSW_REG_MCIA_LEN];
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002807 u16 i2c_addr;
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002808 int status;
2809 int err;
2810
2811 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002812
2813 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2814 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2815 /* Cross pages read, read until offset 256 in low page */
2816 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2817
2818 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2819 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2820 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2821 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2822 }
2823
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002824 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002825 0, 0, offset, size, i2c_addr);
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002826
2827 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2828 if (err)
2829 return err;
2830
2831 status = mlxsw_reg_mcia_status_get(mcia_pl);
2832 if (status)
2833 return -EIO;
2834
2835 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2836 memcpy(data, eeprom_tmp, size);
2837 *p_read_size = size;
2838
2839 return 0;
2840}
2841
2842enum mlxsw_sp_eeprom_module_info_rev_id {
2843 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2844 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2845 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2846};
2847
2848enum mlxsw_sp_eeprom_module_info_id {
2849 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2850 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2851 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2852 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2853};
2854
2855enum mlxsw_sp_eeprom_module_info {
2856 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2857 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2858 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2859};
2860
2861static int mlxsw_sp_get_module_info(struct net_device *netdev,
2862 struct ethtool_modinfo *modinfo)
2863{
2864 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2865 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2866 u8 module_rev_id, module_id;
2867 unsigned int read_size;
2868 int err;
2869
2870 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2871 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2872 module_info, &read_size);
2873 if (err)
2874 return err;
2875
2876 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2877 return -EIO;
2878
2879 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2880 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2881
2882 switch (module_id) {
2883 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2884 modinfo->type = ETH_MODULE_SFF_8436;
2885 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2886 break;
2887 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2888 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2889 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2890 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2891 modinfo->type = ETH_MODULE_SFF_8636;
2892 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2893 } else {
2894 modinfo->type = ETH_MODULE_SFF_8436;
2895 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2896 }
2897 break;
2898 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2899 modinfo->type = ETH_MODULE_SFF_8472;
2900 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2901 break;
2902 default:
2903 return -EINVAL;
2904 }
2905
2906 return 0;
2907}
2908
2909static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2910 struct ethtool_eeprom *ee,
2911 u8 *data)
2912{
2913 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2914 int offset = ee->offset;
2915 unsigned int read_size;
2916 int i = 0;
2917 int err;
2918
2919 if (!ee->len)
2920 return -EINVAL;
2921
2922 memset(data, 0, ee->len);
2923
2924 while (i < ee->len) {
2925 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2926 ee->len - i, data + i,
2927 &read_size);
2928 if (err) {
2929 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2930 return err;
2931 }
2932
2933 i += read_size;
2934 offset += read_size;
2935 }
2936
2937 return 0;
2938}
2939
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002940static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2941 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2942 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002943 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2944 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002945 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002946 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002947 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2948 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002949 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2950 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002951 .flash_device = mlxsw_sp_flash_device,
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002952 .get_module_info = mlxsw_sp_get_module_info,
2953 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002954};
2955
Ido Schimmel18f1e702016-02-26 17:32:31 +01002956static int
2957mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2958{
2959 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2960 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2961 char ptys_pl[MLXSW_REG_PTYS_LEN];
2962 u32 eth_proto_admin;
2963
2964 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002965 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2966 eth_proto_admin);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002967 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2968}
2969
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002970int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2971 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2972 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002973{
2974 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2975 char qeec_pl[MLXSW_REG_QEEC_LEN];
2976
2977 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2978 next_index);
2979 mlxsw_reg_qeec_de_set(qeec_pl, true);
2980 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2981 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2982 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2983}
2984
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002985int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2986 enum mlxsw_reg_qeec_hr hr, u8 index,
2987 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002988{
2989 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2990 char qeec_pl[MLXSW_REG_QEEC_LEN];
2991
2992 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2993 next_index);
2994 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2995 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2996 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2997}
2998
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002999int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
3000 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02003001{
3002 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3003 char qtct_pl[MLXSW_REG_QTCT_LEN];
3004
3005 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
3006 tclass);
3007 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
3008}
3009
3010static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
3011{
3012 int err, i;
3013
3014 /* Setup the elements hierarcy, so that each TC is linked to
3015 * one subgroup, which are all member in the same group.
3016 */
3017 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3018 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
3019 0);
3020 if (err)
3021 return err;
3022 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3023 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3024 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
3025 0, false, 0);
3026 if (err)
3027 return err;
3028 }
3029 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3030 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3031 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
3032 false, 0);
3033 if (err)
3034 return err;
3035 }
3036
3037 /* Make sure the max shaper is disabled in all hierarcies that
3038 * support it.
3039 */
3040 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3041 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
3042 MLXSW_REG_QEEC_MAS_DIS);
3043 if (err)
3044 return err;
3045 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3046 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3047 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3048 i, 0,
3049 MLXSW_REG_QEEC_MAS_DIS);
3050 if (err)
3051 return err;
3052 }
3053 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3054 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3055 MLXSW_REG_QEEC_HIERARCY_TC,
3056 i, i,
3057 MLXSW_REG_QEEC_MAS_DIS);
3058 if (err)
3059 return err;
3060 }
3061
3062 /* Map all priorities to traffic class 0. */
3063 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3064 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
3065 if (err)
3066 return err;
3067 }
3068
3069 return 0;
3070}
3071
Ido Schimmel5b153852017-06-08 08:47:44 +02003072static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
3073 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003074{
Ido Schimmelc57529e2017-05-26 08:37:31 +02003075 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003076 struct mlxsw_sp_port *mlxsw_sp_port;
3077 struct net_device *dev;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003078 int err;
3079
Ido Schimmel5b153852017-06-08 08:47:44 +02003080 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
3081 if (err) {
3082 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
3083 local_port);
3084 return err;
3085 }
3086
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003087 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
Ido Schimmel5b153852017-06-08 08:47:44 +02003088 if (!dev) {
3089 err = -ENOMEM;
3090 goto err_alloc_etherdev;
3091 }
Jiri Pirkof20a91f2016-10-27 15:13:00 +02003092 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003093 mlxsw_sp_port = netdev_priv(dev);
3094 mlxsw_sp_port->dev = dev;
3095 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
3096 mlxsw_sp_port->local_port = local_port;
Ido Schimmelc57529e2017-05-26 08:37:31 +02003097 mlxsw_sp_port->pvid = 1;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003098 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02003099 mlxsw_sp_port->mapping.module = module;
3100 mlxsw_sp_port->mapping.width = width;
3101 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02003102 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02003103 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02003104 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003105
3106 mlxsw_sp_port->pcpu_stats =
3107 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
3108 if (!mlxsw_sp_port->pcpu_stats) {
3109 err = -ENOMEM;
3110 goto err_alloc_stats;
3111 }
3112
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003113 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
3114 GFP_KERNEL);
3115 if (!mlxsw_sp_port->sample) {
3116 err = -ENOMEM;
3117 goto err_alloc_sample;
3118 }
3119
Nogah Frankel9deef432017-10-26 10:55:32 +02003120 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02003121 &update_stats_cache);
3122
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003123 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
3124 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
3125
Ido Schimmel2e915e02017-06-08 08:47:45 +02003126 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
Ido Schimmel5b153852017-06-08 08:47:44 +02003127 if (err) {
3128 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
3129 mlxsw_sp_port->local_port);
3130 goto err_port_module_map;
3131 }
3132
Ido Schimmel3247ff22016-09-08 08:16:02 +02003133 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
3134 if (err) {
3135 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
3136 mlxsw_sp_port->local_port);
3137 goto err_port_swid_set;
3138 }
3139
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003140 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
3141 if (err) {
3142 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
3143 mlxsw_sp_port->local_port);
3144 goto err_dev_addr_init;
3145 }
3146
3147 netif_carrier_off(dev);
3148
3149 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02003150 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
3151 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003152
Jarod Wilsond894be52016-10-20 13:55:16 -04003153 dev->min_mtu = 0;
3154 dev->max_mtu = ETH_MAX_MTU;
3155
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003156 /* Each packet needs to have a Tx header (metadata) on top all other
3157 * headers.
3158 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02003159 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003160
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003161 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
3162 if (err) {
3163 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
3164 mlxsw_sp_port->local_port);
3165 goto err_port_system_port_mapping_set;
3166 }
3167
Ido Schimmel18f1e702016-02-26 17:32:31 +01003168 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
3169 if (err) {
3170 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
3171 mlxsw_sp_port->local_port);
3172 goto err_port_speed_by_width_set;
3173 }
3174
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003175 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
3176 if (err) {
3177 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
3178 mlxsw_sp_port->local_port);
3179 goto err_port_mtu_set;
3180 }
3181
3182 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3183 if (err)
3184 goto err_port_admin_status_set;
3185
3186 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
3187 if (err) {
3188 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
3189 mlxsw_sp_port->local_port);
3190 goto err_port_buffers_init;
3191 }
3192
Ido Schimmel90183b92016-04-06 17:10:08 +02003193 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
3194 if (err) {
3195 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
3196 mlxsw_sp_port->local_port);
3197 goto err_port_ets_init;
3198 }
3199
Ido Schimmelf00817d2016-04-06 17:10:09 +02003200 /* ETS and buffers must be initialized before DCB. */
3201 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
3202 if (err) {
3203 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
3204 mlxsw_sp_port->local_port);
3205 goto err_port_dcb_init;
3206 }
3207
Ido Schimmela1107482017-05-26 08:37:39 +02003208 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
Ido Schimmel45a4a162017-05-16 19:38:35 +02003209 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003210 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
Ido Schimmel45a4a162017-05-16 19:38:35 +02003211 mlxsw_sp_port->local_port);
Ido Schimmela1107482017-05-26 08:37:39 +02003212 goto err_port_fids_init;
Ido Schimmel45a4a162017-05-16 19:38:35 +02003213 }
3214
Nogah Frankel371b4372018-01-10 14:59:57 +01003215 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
3216 if (err) {
3217 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
3218 mlxsw_sp_port->local_port);
3219 goto err_port_qdiscs_init;
3220 }
3221
Ido Schimmelc57529e2017-05-26 08:37:31 +02003222 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
3223 if (IS_ERR(mlxsw_sp_port_vlan)) {
3224 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
Ido Schimmel05978482016-08-17 16:39:30 +02003225 mlxsw_sp_port->local_port);
Wei Yongjund86fd112017-11-06 11:11:28 +00003226 err = PTR_ERR(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003227 goto err_port_vlan_get;
Ido Schimmel05978482016-08-17 16:39:30 +02003228 }
3229
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003230 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02003231 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003232 err = register_netdev(dev);
3233 if (err) {
3234 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3235 mlxsw_sp_port->local_port);
3236 goto err_register_netdev;
3237 }
3238
Elad Razd808c7e2016-10-28 21:35:57 +02003239 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3240 mlxsw_sp_port, dev, mlxsw_sp_port->split,
3241 module);
Nogah Frankel9deef432017-10-26 10:55:32 +02003242 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003243 return 0;
3244
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003245err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02003246 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02003247 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003248 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
3249err_port_vlan_get:
Nogah Frankel371b4372018-01-10 14:59:57 +01003250 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3251err_port_qdiscs_init:
Ido Schimmela1107482017-05-26 08:37:39 +02003252 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3253err_port_fids_init:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03003254 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02003255err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02003256err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003257err_port_buffers_init:
3258err_port_admin_status_set:
3259err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01003260err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003261err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003262err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02003263 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3264err_port_swid_set:
Ido Schimmel2e915e02017-06-08 08:47:45 +02003265 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Ido Schimmel5b153852017-06-08 08:47:44 +02003266err_port_module_map:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003267 kfree(mlxsw_sp_port->sample);
3268err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003269 free_percpu(mlxsw_sp_port->pcpu_stats);
3270err_alloc_stats:
3271 free_netdev(dev);
Ido Schimmel5b153852017-06-08 08:47:44 +02003272err_alloc_etherdev:
Jiri Pirko67963a32016-10-28 21:35:55 +02003273 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3274 return err;
3275}
3276
Ido Schimmel5b153852017-06-08 08:47:44 +02003277static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003278{
3279 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3280
Nogah Frankel9deef432017-10-26 10:55:32 +02003281 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02003282 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003283 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02003284 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02003285 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003286 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Nogah Frankel371b4372018-01-10 14:59:57 +01003287 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
Ido Schimmela1107482017-05-26 08:37:39 +02003288 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02003289 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01003290 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
Ido Schimmel2e915e02017-06-08 08:47:45 +02003291 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003292 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01003293 free_percpu(mlxsw_sp_port->pcpu_stats);
Ido Schimmel31a08a52017-05-26 08:37:26 +02003294 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003295 free_netdev(mlxsw_sp_port->dev);
Jiri Pirko67963a32016-10-28 21:35:55 +02003296 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3297}
3298
Jiri Pirkof83e2102016-10-28 21:35:49 +02003299static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3300{
3301 return mlxsw_sp->ports[local_port] != NULL;
3302}
3303
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003304static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3305{
3306 int i;
3307
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003308 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003309 if (mlxsw_sp_port_created(mlxsw_sp, i))
3310 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003311 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003312 kfree(mlxsw_sp->ports);
3313}
3314
3315static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3316{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003317 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02003318 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003319 size_t alloc_size;
3320 int i;
3321 int err;
3322
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003323 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003324 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3325 if (!mlxsw_sp->ports)
3326 return -ENOMEM;
3327
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003328 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3329 GFP_KERNEL);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003330 if (!mlxsw_sp->port_to_module) {
3331 err = -ENOMEM;
3332 goto err_port_to_module_alloc;
3333 }
3334
3335 for (i = 1; i < max_ports; i++) {
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003336 /* Mark as invalid */
3337 mlxsw_sp->port_to_module[i] = -1;
3338
Ido Schimmel558c2d52016-02-26 17:32:29 +01003339 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003340 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01003341 if (err)
3342 goto err_port_module_info_get;
3343 if (!width)
3344 continue;
3345 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02003346 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3347 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003348 if (err)
3349 goto err_port_create;
3350 }
3351 return 0;
3352
3353err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01003354err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003355 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003356 if (mlxsw_sp_port_created(mlxsw_sp, i))
3357 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003358 kfree(mlxsw_sp->port_to_module);
3359err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003360 kfree(mlxsw_sp->ports);
3361 return err;
3362}
3363
Ido Schimmel18f1e702016-02-26 17:32:31 +01003364static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3365{
3366 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3367
3368 return local_port - offset;
3369}
3370
Ido Schimmelbe945352016-06-09 09:51:39 +02003371static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3372 u8 module, unsigned int count)
3373{
3374 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3375 int err, i;
3376
3377 for (i = 0; i < count; i++) {
Ido Schimmelbe945352016-06-09 09:51:39 +02003378 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02003379 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02003380 if (err)
3381 goto err_port_create;
3382 }
3383
3384 return 0;
3385
3386err_port_create:
3387 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003388 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3389 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02003390 return err;
3391}
3392
3393static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3394 u8 base_port, unsigned int count)
3395{
3396 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3397 int i;
3398
3399 /* Split by four means we need to re-create two ports, otherwise
3400 * only one.
3401 */
3402 count = count / 2;
3403
3404 for (i = 0; i < count; i++) {
3405 local_port = base_port + i * 2;
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003406 if (mlxsw_sp->port_to_module[local_port] < 0)
3407 continue;
Ido Schimmelbe945352016-06-09 09:51:39 +02003408 module = mlxsw_sp->port_to_module[local_port];
3409
Ido Schimmelbe945352016-06-09 09:51:39 +02003410 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003411 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003412 }
3413}
3414
Jiri Pirkob2f10572016-04-08 19:11:23 +02003415static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3416 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003417{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003418 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003419 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003420 u8 module, cur_width, base_port;
3421 int i;
3422 int err;
3423
3424 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3425 if (!mlxsw_sp_port) {
3426 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3427 local_port);
3428 return -EINVAL;
3429 }
3430
Ido Schimmeld664b412016-06-09 09:51:40 +02003431 module = mlxsw_sp_port->mapping.module;
3432 cur_width = mlxsw_sp_port->mapping.width;
3433
Ido Schimmel18f1e702016-02-26 17:32:31 +01003434 if (count != 2 && count != 4) {
3435 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3436 return -EINVAL;
3437 }
3438
Ido Schimmel18f1e702016-02-26 17:32:31 +01003439 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3440 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3441 return -EINVAL;
3442 }
3443
3444 /* Make sure we have enough slave (even) ports for the split. */
3445 if (count == 2) {
3446 base_port = local_port;
3447 if (mlxsw_sp->ports[base_port + 1]) {
3448 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3449 return -EINVAL;
3450 }
3451 } else {
3452 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3453 if (mlxsw_sp->ports[base_port + 1] ||
3454 mlxsw_sp->ports[base_port + 3]) {
3455 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3456 return -EINVAL;
3457 }
3458 }
3459
3460 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003461 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3462 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003463
Ido Schimmelbe945352016-06-09 09:51:39 +02003464 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3465 if (err) {
3466 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3467 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003468 }
3469
3470 return 0;
3471
Ido Schimmelbe945352016-06-09 09:51:39 +02003472err_port_split_create:
3473 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003474 return err;
3475}
3476
Jiri Pirkob2f10572016-04-08 19:11:23 +02003477static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003478{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003479 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003480 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003481 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003482 unsigned int count;
3483 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003484
3485 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3486 if (!mlxsw_sp_port) {
3487 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3488 local_port);
3489 return -EINVAL;
3490 }
3491
3492 if (!mlxsw_sp_port->split) {
3493 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3494 return -EINVAL;
3495 }
3496
Ido Schimmeld664b412016-06-09 09:51:40 +02003497 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003498 count = cur_width == 1 ? 4 : 2;
3499
3500 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3501
3502 /* Determine which ports to remove. */
3503 if (count == 2 && local_port >= base_port + 2)
3504 base_port = base_port + 2;
3505
3506 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003507 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3508 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003509
Ido Schimmelbe945352016-06-09 09:51:39 +02003510 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003511
3512 return 0;
3513}
3514
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003515static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3516 char *pude_pl, void *priv)
3517{
3518 struct mlxsw_sp *mlxsw_sp = priv;
3519 struct mlxsw_sp_port *mlxsw_sp_port;
3520 enum mlxsw_reg_pude_oper_status status;
3521 u8 local_port;
3522
3523 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3524 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003525 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003526 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003527
3528 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3529 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3530 netdev_info(mlxsw_sp_port->dev, "link up\n");
3531 netif_carrier_on(mlxsw_sp_port->dev);
3532 } else {
3533 netdev_info(mlxsw_sp_port->dev, "link down\n");
3534 netif_carrier_off(mlxsw_sp_port->dev);
3535 }
3536}
3537
Nogah Frankel14eeda92016-11-25 10:33:32 +01003538static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3539 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003540{
3541 struct mlxsw_sp *mlxsw_sp = priv;
3542 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3543 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3544
3545 if (unlikely(!mlxsw_sp_port)) {
3546 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3547 local_port);
3548 return;
3549 }
3550
3551 skb->dev = mlxsw_sp_port->dev;
3552
3553 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3554 u64_stats_update_begin(&pcpu_stats->syncp);
3555 pcpu_stats->rx_packets++;
3556 pcpu_stats->rx_bytes += skb->len;
3557 u64_stats_update_end(&pcpu_stats->syncp);
3558
3559 skb->protocol = eth_type_trans(skb, skb->dev);
3560 netif_receive_skb(skb);
3561}
3562
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003563static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3564 void *priv)
3565{
3566 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003567 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003568}
3569
Yotam Gigia0040c82017-10-03 09:58:10 +02003570static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3571 u8 local_port, void *priv)
3572{
3573 skb->offload_mr_fwd_mark = 1;
3574 skb->offload_fwd_mark = 1;
3575 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3576}
3577
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003578static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3579 void *priv)
3580{
3581 struct mlxsw_sp *mlxsw_sp = priv;
3582 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3583 struct psample_group *psample_group;
3584 u32 size;
3585
3586 if (unlikely(!mlxsw_sp_port)) {
3587 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3588 local_port);
3589 goto out;
3590 }
3591 if (unlikely(!mlxsw_sp_port->sample)) {
3592 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3593 local_port);
3594 goto out;
3595 }
3596
3597 size = mlxsw_sp_port->sample->truncate ?
3598 mlxsw_sp_port->sample->trunc_size : skb->len;
3599
3600 rcu_read_lock();
3601 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3602 if (!psample_group)
3603 goto out_unlock;
3604 psample_sample_packet(psample_group, skb, size,
3605 mlxsw_sp_port->dev->ifindex, 0,
3606 mlxsw_sp_port->sample->rate);
3607out_unlock:
3608 rcu_read_unlock();
3609out:
3610 consume_skb(skb);
3611}
3612
Nogah Frankel117b0da2016-11-25 10:33:44 +01003613#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003614 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003615 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003616
Nogah Frankel117b0da2016-11-25 10:33:44 +01003617#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003618 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003619 _is_ctrl, SP_##_trap_group, DISCARD)
3620
Yotam Gigia0040c82017-10-03 09:58:10 +02003621#define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3622 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3623 _is_ctrl, SP_##_trap_group, DISCARD)
3624
Nogah Frankel117b0da2016-11-25 10:33:44 +01003625#define MLXSW_SP_EVENTL(_func, _trap_id) \
3626 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003627
Nogah Frankel45449132016-11-25 10:33:35 +01003628static const struct mlxsw_listener mlxsw_sp_listener[] = {
3629 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003630 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003631 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003632 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3633 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3634 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3635 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3636 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3637 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3638 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3639 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3640 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3641 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3642 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003643 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003644 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3645 false),
3646 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3647 false),
3648 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3649 false),
3650 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3651 false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003652 /* L3 traps */
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003653 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3654 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3655 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003656 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003657 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3658 false),
3659 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3660 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3661 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3662 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3663 false),
3664 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3665 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3666 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003667 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003668 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3669 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3670 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3671 false),
3672 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3673 false),
3674 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3675 false),
3676 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3677 false),
3678 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3679 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3680 false),
3681 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3682 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
Ido Schimmel7607dd32017-07-17 14:15:30 +02003683 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003684 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
Petr Machata86484de2017-09-02 23:49:27 +02003685 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003686 /* PKT Sample trap */
3687 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
Jiri Pirko0db7b382017-06-06 14:12:05 +02003688 false, SP_IP2ME, DISCARD),
3689 /* ACL trap */
3690 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
Yotam Gigib48cfc82017-09-19 10:00:20 +02003691 /* Multicast Router Traps */
3692 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3693 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3694 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
Yotam Gigia0040c82017-10-03 09:58:10 +02003695 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003696};
3697
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003698static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3699{
3700 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3701 enum mlxsw_reg_qpcr_ir_units ir_units;
3702 int max_cpu_policers;
3703 bool is_bytes;
3704 u8 burst_size;
3705 u32 rate;
3706 int i, err;
3707
3708 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3709 return -EIO;
3710
3711 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3712
3713 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3714 for (i = 0; i < max_cpu_policers; i++) {
3715 is_bytes = false;
3716 switch (i) {
3717 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3718 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3719 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3720 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003721 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3722 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003723 rate = 128;
3724 burst_size = 7;
3725 break;
3726 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003727 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003728 rate = 16 * 1024;
3729 burst_size = 10;
3730 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003731 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003732 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3733 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003734 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003735 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3736 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003737 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003738 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003739 rate = 1024;
3740 burst_size = 7;
3741 break;
3742 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3743 is_bytes = true;
3744 rate = 4 * 1024;
3745 burst_size = 4;
3746 break;
3747 default:
3748 continue;
3749 }
3750
3751 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3752 burst_size);
3753 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3754 if (err)
3755 return err;
3756 }
3757
3758 return 0;
3759}
3760
Nogah Frankel579c82e2016-11-25 10:33:42 +01003761static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003762{
3763 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003764 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003765 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003766 int max_trap_groups;
3767 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003768 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003769 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003770
3771 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3772 return -EIO;
3773
3774 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003775 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003776
3777 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003778 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003779 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003780 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3781 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3782 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3783 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003784 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003785 priority = 5;
3786 tc = 5;
3787 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003788 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003789 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3790 priority = 4;
3791 tc = 4;
3792 break;
3793 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3794 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003795 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003796 priority = 3;
3797 tc = 3;
3798 break;
3799 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003800 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003801 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003802 priority = 2;
3803 tc = 2;
3804 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003805 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003806 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3807 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003808 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003809 priority = 1;
3810 tc = 1;
3811 break;
3812 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003813 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3814 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003815 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003816 break;
3817 default:
3818 continue;
3819 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003820
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003821 if (max_cpu_policers <= policer_id &&
3822 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3823 return -EIO;
3824
3825 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003826 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3827 if (err)
3828 return err;
3829 }
3830
3831 return 0;
3832}
3833
3834static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3835{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003836 int i;
3837 int err;
3838
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003839 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3840 if (err)
3841 return err;
3842
Nogah Frankel579c82e2016-11-25 10:33:42 +01003843 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003844 if (err)
3845 return err;
3846
Nogah Frankel45449132016-11-25 10:33:35 +01003847 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003848 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003849 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003850 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003851 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003852 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003853
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003854 }
3855 return 0;
3856
Nogah Frankel45449132016-11-25 10:33:35 +01003857err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003858 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003859 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003860 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003861 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003862 }
3863 return err;
3864}
3865
3866static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3867{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003868 int i;
3869
Nogah Frankel45449132016-11-25 10:33:35 +01003870 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003871 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003872 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003873 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003874 }
3875}
3876
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003877static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3878{
3879 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003880 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003881
3882 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3883 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3884 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3885 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3886 MLXSW_REG_SLCR_LAG_HASH_SIP |
3887 MLXSW_REG_SLCR_LAG_HASH_DIP |
3888 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3889 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3890 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003891 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3892 if (err)
3893 return err;
3894
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003895 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3896 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003897 return -EIO;
3898
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003899 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003900 sizeof(struct mlxsw_sp_upper),
3901 GFP_KERNEL);
3902 if (!mlxsw_sp->lags)
3903 return -ENOMEM;
3904
3905 return 0;
3906}
3907
3908static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3909{
3910 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003911}
3912
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003913static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3914{
3915 char htgt_pl[MLXSW_REG_HTGT_LEN];
3916
Nogah Frankel579c82e2016-11-25 10:33:42 +01003917 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3918 MLXSW_REG_HTGT_INVALID_POLICER,
3919 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3920 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003921 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3922}
3923
Petr Machatac30f5d02017-10-16 16:26:35 +02003924static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3925 unsigned long event, void *ptr);
3926
Jiri Pirkob2f10572016-04-08 19:11:23 +02003927static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003928 const struct mlxsw_bus_info *mlxsw_bus_info)
3929{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003930 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003931 int err;
3932
3933 mlxsw_sp->core = mlxsw_core;
3934 mlxsw_sp->bus_info = mlxsw_bus_info;
3935
Yotam Gigi6b742192017-05-23 21:56:29 +02003936 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3937 if (err) {
3938 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3939 return err;
3940 }
3941
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003942 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3943 if (err) {
3944 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3945 return err;
3946 }
3947
Ido Schimmela875a2e2017-10-22 23:11:44 +02003948 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3949 if (err) {
3950 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3951 return err;
3952 }
3953
Ido Schimmela1107482017-05-26 08:37:39 +02003954 err = mlxsw_sp_fids_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003955 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003956 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
Ido Schimmela875a2e2017-10-22 23:11:44 +02003957 goto err_fids_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003958 }
3959
Ido Schimmela1107482017-05-26 08:37:39 +02003960 err = mlxsw_sp_traps_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003961 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003962 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3963 goto err_traps_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003964 }
3965
3966 err = mlxsw_sp_buffers_init(mlxsw_sp);
3967 if (err) {
3968 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3969 goto err_buffers_init;
3970 }
3971
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003972 err = mlxsw_sp_lag_init(mlxsw_sp);
3973 if (err) {
3974 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3975 goto err_lag_init;
3976 }
3977
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003978 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3979 if (err) {
3980 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3981 goto err_switchdev_init;
3982 }
3983
Yotam Gigie2b2d352017-09-19 10:00:08 +02003984 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3985 if (err) {
3986 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3987 goto err_counter_pool_init;
3988 }
3989
Yotam Gigid3b939b2017-09-19 10:00:09 +02003990 err = mlxsw_sp_afa_init(mlxsw_sp);
3991 if (err) {
3992 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3993 goto err_afa_init;
3994 }
3995
Ido Schimmel464dce12016-07-02 11:00:15 +02003996 err = mlxsw_sp_router_init(mlxsw_sp);
3997 if (err) {
3998 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3999 goto err_router_init;
4000 }
4001
Petr Machatac30f5d02017-10-16 16:26:35 +02004002 /* Initialize netdevice notifier after router is initialized, so that
4003 * the event handler can use router structures.
4004 */
4005 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
4006 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4007 if (err) {
4008 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
4009 goto err_netdev_notifier;
4010 }
4011
Yotam Gigi763b4b72016-07-21 12:03:17 +02004012 err = mlxsw_sp_span_init(mlxsw_sp);
4013 if (err) {
4014 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
4015 goto err_span_init;
4016 }
4017
Jiri Pirko22a67762017-02-03 10:29:07 +01004018 err = mlxsw_sp_acl_init(mlxsw_sp);
4019 if (err) {
4020 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
4021 goto err_acl_init;
4022 }
4023
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02004024 err = mlxsw_sp_dpipe_init(mlxsw_sp);
4025 if (err) {
4026 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
4027 goto err_dpipe_init;
4028 }
4029
Ido Schimmelbbf2a472016-07-02 11:00:14 +02004030 err = mlxsw_sp_ports_create(mlxsw_sp);
4031 if (err) {
4032 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
4033 goto err_ports_create;
4034 }
4035
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004036 return 0;
4037
Ido Schimmelbbf2a472016-07-02 11:00:14 +02004038err_ports_create:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02004039 mlxsw_sp_dpipe_fini(mlxsw_sp);
4040err_dpipe_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01004041 mlxsw_sp_acl_fini(mlxsw_sp);
4042err_acl_init:
Yotam Gigi763b4b72016-07-21 12:03:17 +02004043 mlxsw_sp_span_fini(mlxsw_sp);
4044err_span_init:
Petr Machatac30f5d02017-10-16 16:26:35 +02004045 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4046err_netdev_notifier:
Ido Schimmel464dce12016-07-02 11:00:15 +02004047 mlxsw_sp_router_fini(mlxsw_sp);
4048err_router_init:
Yotam Gigid3b939b2017-09-19 10:00:09 +02004049 mlxsw_sp_afa_fini(mlxsw_sp);
4050err_afa_init:
Yotam Gigie2b2d352017-09-19 10:00:08 +02004051 mlxsw_sp_counter_pool_fini(mlxsw_sp);
4052err_counter_pool_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02004053 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004054err_switchdev_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02004055 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004056err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02004057 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004058err_buffers_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004059 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02004060err_traps_init:
4061 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02004062err_fids_init:
4063 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004064 return err;
4065}
4066
Jiri Pirkob2f10572016-04-08 19:11:23 +02004067static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004068{
Jiri Pirkob2f10572016-04-08 19:11:23 +02004069 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004070
Ido Schimmelbbf2a472016-07-02 11:00:14 +02004071 mlxsw_sp_ports_remove(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02004072 mlxsw_sp_dpipe_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01004073 mlxsw_sp_acl_fini(mlxsw_sp);
Yotam Gigi763b4b72016-07-21 12:03:17 +02004074 mlxsw_sp_span_fini(mlxsw_sp);
Petr Machatac30f5d02017-10-16 16:26:35 +02004075 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
Ido Schimmel464dce12016-07-02 11:00:15 +02004076 mlxsw_sp_router_fini(mlxsw_sp);
Yotam Gigid3b939b2017-09-19 10:00:09 +02004077 mlxsw_sp_afa_fini(mlxsw_sp);
Yotam Gigie2b2d352017-09-19 10:00:08 +02004078 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004079 mlxsw_sp_switchdev_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02004080 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02004081 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004082 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02004083 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02004084 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004085}
4086
Bhumika Goyal159fe882017-08-11 19:10:42 +05304087static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004088 .used_max_vepa_channels = 1,
4089 .max_vepa_channels = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004090 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01004091 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004092 .used_max_pgt = 1,
4093 .max_pgt = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004094 .used_flood_tables = 1,
4095 .used_flood_mode = 1,
4096 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01004097 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004098 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01004099 .max_fid_flood_tables = 3,
Ido Schimmela1107482017-05-26 08:37:39 +02004100 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004101 .used_max_ib_mc = 1,
4102 .max_ib_mc = 0,
4103 .used_max_pkey = 1,
4104 .max_pkey = 0,
Nogah Frankel403547d2016-09-20 11:16:52 +02004105 .used_kvd_split_data = 1,
4106 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
Ido Schimmelf11fbaf2017-10-22 23:11:49 +02004107 .kvd_hash_single_parts = 59,
4108 .kvd_hash_double_parts = 41,
Jiri Pirkoc6022422016-07-05 11:27:46 +02004109 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004110 .swid_config = {
4111 {
4112 .used_type = 1,
4113 .type = MLXSW_PORT_SWID_TYPE_ETH,
4114 }
4115 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02004116 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004117};
4118
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004119static bool
4120mlxsw_sp_resource_kvd_granularity_validate(struct netlink_ext_ack *extack,
4121 u64 size)
4122{
4123 const struct mlxsw_config_profile *profile;
4124
4125 profile = &mlxsw_sp_config_profile;
4126 if (size % profile->kvd_hash_granularity) {
4127 NL_SET_ERR_MSG_MOD(extack, "resource set with wrong granularity");
4128 return false;
4129 }
4130 return true;
4131}
4132
4133static int
4134mlxsw_sp_resource_kvd_size_validate(struct devlink *devlink, u64 size,
4135 struct netlink_ext_ack *extack)
4136{
4137 NL_SET_ERR_MSG_MOD(extack, "kvd size cannot be changed");
4138 return -EINVAL;
4139}
4140
4141static int
4142mlxsw_sp_resource_kvd_linear_size_validate(struct devlink *devlink, u64 size,
4143 struct netlink_ext_ack *extack)
4144{
4145 if (!mlxsw_sp_resource_kvd_granularity_validate(extack, size))
4146 return -EINVAL;
4147
4148 return 0;
4149}
4150
4151static int
4152mlxsw_sp_resource_kvd_hash_single_size_validate(struct devlink *devlink, u64 size,
4153 struct netlink_ext_ack *extack)
4154{
4155 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
4156
4157 if (!mlxsw_sp_resource_kvd_granularity_validate(extack, size))
4158 return -EINVAL;
4159
4160 if (size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE)) {
4161 NL_SET_ERR_MSG_MOD(extack, "hash single size is smaller than minimum");
4162 return -EINVAL;
4163 }
4164 return 0;
4165}
4166
4167static int
4168mlxsw_sp_resource_kvd_hash_double_size_validate(struct devlink *devlink, u64 size,
4169 struct netlink_ext_ack *extack)
4170{
4171 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
4172
4173 if (!mlxsw_sp_resource_kvd_granularity_validate(extack, size))
4174 return -EINVAL;
4175
4176 if (size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE)) {
4177 NL_SET_ERR_MSG_MOD(extack, "hash double size is smaller than minimum");
4178 return -EINVAL;
4179 }
4180 return 0;
4181}
4182
Arkadi Sharshevskyafadc262018-01-15 08:59:09 +01004183static u64 mlxsw_sp_resource_kvd_linear_occ_get(struct devlink *devlink)
4184{
4185 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
4186 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4187
4188 return mlxsw_sp_kvdl_occ_get(mlxsw_sp);
4189}
4190
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004191static struct devlink_resource_ops mlxsw_sp_resource_kvd_ops = {
4192 .size_validate = mlxsw_sp_resource_kvd_size_validate,
4193};
4194
4195static struct devlink_resource_ops mlxsw_sp_resource_kvd_linear_ops = {
4196 .size_validate = mlxsw_sp_resource_kvd_linear_size_validate,
Arkadi Sharshevskyafadc262018-01-15 08:59:09 +01004197 .occ_get = mlxsw_sp_resource_kvd_linear_occ_get,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004198};
4199
4200static struct devlink_resource_ops mlxsw_sp_resource_kvd_hash_single_ops = {
4201 .size_validate = mlxsw_sp_resource_kvd_hash_single_size_validate,
4202};
4203
4204static struct devlink_resource_ops mlxsw_sp_resource_kvd_hash_double_ops = {
4205 .size_validate = mlxsw_sp_resource_kvd_hash_double_size_validate,
4206};
4207
4208static struct devlink_resource_size_params mlxsw_sp_kvd_size_params;
4209static struct devlink_resource_size_params mlxsw_sp_linear_size_params;
4210static struct devlink_resource_size_params mlxsw_sp_hash_single_size_params;
4211static struct devlink_resource_size_params mlxsw_sp_hash_double_size_params;
4212
4213static void
4214mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core)
4215{
4216 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
4217 KVD_SINGLE_MIN_SIZE);
4218 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
4219 KVD_DOUBLE_MIN_SIZE);
4220 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4221 u32 linear_size_min = 0;
4222
4223 /* KVD top resource */
4224 mlxsw_sp_kvd_size_params.size_min = kvd_size;
4225 mlxsw_sp_kvd_size_params.size_max = kvd_size;
4226 mlxsw_sp_kvd_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
4227 mlxsw_sp_kvd_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
4228
4229 /* Linear part init */
4230 mlxsw_sp_linear_size_params.size_min = linear_size_min;
4231 mlxsw_sp_linear_size_params.size_max = kvd_size - single_size_min -
4232 double_size_min;
4233 mlxsw_sp_linear_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
4234 mlxsw_sp_linear_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
4235
4236 /* Hash double part init */
4237 mlxsw_sp_hash_double_size_params.size_min = double_size_min;
4238 mlxsw_sp_hash_double_size_params.size_max = kvd_size - single_size_min -
4239 linear_size_min;
4240 mlxsw_sp_hash_double_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
4241 mlxsw_sp_hash_double_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
4242
4243 /* Hash single part init */
4244 mlxsw_sp_hash_single_size_params.size_min = single_size_min;
4245 mlxsw_sp_hash_single_size_params.size_max = kvd_size - double_size_min -
4246 linear_size_min;
4247 mlxsw_sp_hash_single_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
4248 mlxsw_sp_hash_single_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
4249}
4250
4251static int mlxsw_sp_resources_register(struct mlxsw_core *mlxsw_core)
4252{
4253 struct devlink *devlink = priv_to_devlink(mlxsw_core);
4254 u32 kvd_size, single_size, double_size, linear_size;
4255 const struct mlxsw_config_profile *profile;
4256 int err;
4257
4258 profile = &mlxsw_sp_config_profile;
4259 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
4260 return -EIO;
4261
4262 mlxsw_sp_resource_size_params_prepare(mlxsw_core);
4263 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4264 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
4265 true, kvd_size,
4266 MLXSW_SP_RESOURCE_KVD,
4267 DEVLINK_RESOURCE_ID_PARENT_TOP,
4268 &mlxsw_sp_kvd_size_params,
4269 &mlxsw_sp_resource_kvd_ops);
4270 if (err)
4271 return err;
4272
4273 linear_size = profile->kvd_linear_size;
4274 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
4275 false, linear_size,
4276 MLXSW_SP_RESOURCE_KVD_LINEAR,
4277 MLXSW_SP_RESOURCE_KVD,
4278 &mlxsw_sp_linear_size_params,
4279 &mlxsw_sp_resource_kvd_linear_ops);
4280 if (err)
4281 return err;
4282
4283 double_size = kvd_size - linear_size;
4284 double_size *= profile->kvd_hash_double_parts;
4285 double_size /= profile->kvd_hash_double_parts +
4286 profile->kvd_hash_single_parts;
4287 double_size = rounddown(double_size, profile->kvd_hash_granularity);
4288 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
4289 false, double_size,
4290 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4291 MLXSW_SP_RESOURCE_KVD,
4292 &mlxsw_sp_hash_double_size_params,
4293 &mlxsw_sp_resource_kvd_hash_double_ops);
4294 if (err)
4295 return err;
4296
4297 single_size = kvd_size - double_size - linear_size;
4298 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
4299 false, single_size,
4300 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4301 MLXSW_SP_RESOURCE_KVD,
4302 &mlxsw_sp_hash_single_size_params,
4303 &mlxsw_sp_resource_kvd_hash_single_ops);
4304 if (err)
4305 return err;
4306
4307 return 0;
4308}
4309
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01004310static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
4311 const struct mlxsw_config_profile *profile,
4312 u64 *p_single_size, u64 *p_double_size,
4313 u64 *p_linear_size)
4314{
4315 struct devlink *devlink = priv_to_devlink(mlxsw_core);
4316 u32 double_size;
4317 int err;
4318
4319 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4320 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
4321 !profile->used_kvd_split_data)
4322 return -EIO;
4323
4324 /* The hash part is what left of the kvd without the
4325 * linear part. It is split to the single size and
4326 * double size by the parts ratio from the profile.
4327 * Both sizes must be a multiplications of the
4328 * granularity from the profile. In case the user
4329 * provided the sizes they are obtained via devlink.
4330 */
4331 err = devlink_resource_size_get(devlink,
4332 MLXSW_SP_RESOURCE_KVD_LINEAR,
4333 p_linear_size);
4334 if (err)
4335 *p_linear_size = profile->kvd_linear_size;
4336
4337 err = devlink_resource_size_get(devlink,
4338 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4339 p_double_size);
4340 if (err) {
4341 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4342 *p_linear_size;
4343 double_size *= profile->kvd_hash_double_parts;
4344 double_size /= profile->kvd_hash_double_parts +
4345 profile->kvd_hash_single_parts;
4346 *p_double_size = rounddown(double_size,
4347 profile->kvd_hash_granularity);
4348 }
4349
4350 err = devlink_resource_size_get(devlink,
4351 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4352 p_single_size);
4353 if (err)
4354 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4355 *p_double_size - *p_linear_size;
4356
4357 /* Check results are legal. */
4358 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4359 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
4360 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
4361 return -EIO;
4362
4363 return 0;
4364}
4365
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004366static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02004367 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02004368 .priv_size = sizeof(struct mlxsw_sp),
4369 .init = mlxsw_sp_init,
4370 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01004371 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02004372 .port_split = mlxsw_sp_port_split,
4373 .port_unsplit = mlxsw_sp_port_unsplit,
4374 .sb_pool_get = mlxsw_sp_sb_pool_get,
4375 .sb_pool_set = mlxsw_sp_sb_pool_set,
4376 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
4377 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
4378 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
4379 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4380 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4381 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4382 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4383 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4384 .txhdr_construct = mlxsw_sp_txhdr_construct,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004385 .resources_register = mlxsw_sp_resources_register,
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01004386 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02004387 .txhdr_len = MLXSW_TXHDR_LEN,
4388 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004389};
4390
Jiri Pirko22a67762017-02-03 10:29:07 +01004391bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004392{
4393 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4394}
4395
Jiri Pirko1182e532017-03-06 21:25:20 +01004396static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07004397{
Jiri Pirko1182e532017-03-06 21:25:20 +01004398 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07004399 int ret = 0;
4400
4401 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01004402 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07004403 ret = 1;
4404 }
4405
4406 return ret;
4407}
4408
Ido Schimmelc57529e2017-05-26 08:37:31 +02004409struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004410{
Jiri Pirko1182e532017-03-06 21:25:20 +01004411 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004412
4413 if (mlxsw_sp_port_dev_check(dev))
4414 return netdev_priv(dev);
4415
Jiri Pirko1182e532017-03-06 21:25:20 +01004416 mlxsw_sp_port = NULL;
4417 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004418
Jiri Pirko1182e532017-03-06 21:25:20 +01004419 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004420}
4421
Ido Schimmel4724ba562017-03-10 08:53:39 +01004422struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004423{
4424 struct mlxsw_sp_port *mlxsw_sp_port;
4425
4426 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4427 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4428}
4429
Arkadi Sharshevskyaf0613782017-06-08 08:44:20 +02004430struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004431{
Jiri Pirko1182e532017-03-06 21:25:20 +01004432 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004433
4434 if (mlxsw_sp_port_dev_check(dev))
4435 return netdev_priv(dev);
4436
Jiri Pirko1182e532017-03-06 21:25:20 +01004437 mlxsw_sp_port = NULL;
4438 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4439 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004440
Jiri Pirko1182e532017-03-06 21:25:20 +01004441 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004442}
4443
4444struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4445{
4446 struct mlxsw_sp_port *mlxsw_sp_port;
4447
4448 rcu_read_lock();
4449 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4450 if (mlxsw_sp_port)
4451 dev_hold(mlxsw_sp_port->dev);
4452 rcu_read_unlock();
4453 return mlxsw_sp_port;
4454}
4455
4456void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4457{
4458 dev_put(mlxsw_sp_port->dev);
4459}
4460
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004461static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004462{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004463 char sldr_pl[MLXSW_REG_SLDR_LEN];
4464
4465 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4466 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4467}
4468
4469static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4470{
4471 char sldr_pl[MLXSW_REG_SLDR_LEN];
4472
4473 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4474 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4475}
4476
4477static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4478 u16 lag_id, u8 port_index)
4479{
4480 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4481 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4482
4483 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4484 lag_id, port_index);
4485 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4486}
4487
4488static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4489 u16 lag_id)
4490{
4491 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4492 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4493
4494 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4495 lag_id);
4496 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4497}
4498
4499static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4500 u16 lag_id)
4501{
4502 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4503 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4504
4505 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4506 lag_id);
4507 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4508}
4509
4510static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4511 u16 lag_id)
4512{
4513 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4514 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4515
4516 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4517 lag_id);
4518 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4519}
4520
4521static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4522 struct net_device *lag_dev,
4523 u16 *p_lag_id)
4524{
4525 struct mlxsw_sp_upper *lag;
4526 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004527 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004528 int i;
4529
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004530 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4531 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004532 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4533 if (lag->ref_count) {
4534 if (lag->dev == lag_dev) {
4535 *p_lag_id = i;
4536 return 0;
4537 }
4538 } else if (free_lag_id < 0) {
4539 free_lag_id = i;
4540 }
4541 }
4542 if (free_lag_id < 0)
4543 return -EBUSY;
4544 *p_lag_id = free_lag_id;
4545 return 0;
4546}
4547
4548static bool
4549mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4550 struct net_device *lag_dev,
David Aherne58376e2017-10-04 17:48:51 -07004551 struct netdev_lag_upper_info *lag_upper_info,
4552 struct netlink_ext_ack *extack)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004553{
4554 u16 lag_id;
4555
David Aherne58376e2017-10-04 17:48:51 -07004556 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
4557 NL_SET_ERR_MSG(extack,
4558 "spectrum: Exceeded number of supported LAG devices");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004559 return false;
David Aherne58376e2017-10-04 17:48:51 -07004560 }
4561 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
4562 NL_SET_ERR_MSG(extack,
4563 "spectrum: LAG device using unsupported Tx type");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004564 return false;
David Aherne58376e2017-10-04 17:48:51 -07004565 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004566 return true;
4567}
4568
4569static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4570 u16 lag_id, u8 *p_port_index)
4571{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004572 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004573 int i;
4574
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004575 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4576 MAX_LAG_MEMBERS);
4577 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004578 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4579 *p_port_index = i;
4580 return 0;
4581 }
4582 }
4583 return -EBUSY;
4584}
4585
4586static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4587 struct net_device *lag_dev)
4588{
4589 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004590 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004591 struct mlxsw_sp_upper *lag;
4592 u16 lag_id;
4593 u8 port_index;
4594 int err;
4595
4596 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4597 if (err)
4598 return err;
4599 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4600 if (!lag->ref_count) {
4601 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4602 if (err)
4603 return err;
4604 lag->dev = lag_dev;
4605 }
4606
4607 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4608 if (err)
4609 return err;
4610 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4611 if (err)
4612 goto err_col_port_add;
4613 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4614 if (err)
4615 goto err_col_port_enable;
4616
4617 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4618 mlxsw_sp_port->local_port);
4619 mlxsw_sp_port->lag_id = lag_id;
4620 mlxsw_sp_port->lagged = 1;
4621 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004622
Ido Schimmelc57529e2017-05-26 08:37:31 +02004623 /* Port is no longer usable as a router interface */
4624 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4625 if (mlxsw_sp_port_vlan->fid)
Ido Schimmela1107482017-05-26 08:37:39 +02004626 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004627
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004628 return 0;
4629
Ido Schimmel51554db2016-05-06 22:18:39 +02004630err_col_port_enable:
4631 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004632err_col_port_add:
4633 if (!lag->ref_count)
4634 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004635 return err;
4636}
4637
Ido Schimmel82e6db02016-06-20 23:04:04 +02004638static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4639 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004640{
4641 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004642 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004643 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004644
4645 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004646 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004647 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4648 WARN_ON(lag->ref_count == 0);
4649
Ido Schimmel82e6db02016-06-20 23:04:04 +02004650 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4651 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004652
Ido Schimmelc57529e2017-05-26 08:37:31 +02004653 /* Any VLANs configured on the port are no longer valid */
4654 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004655
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004656 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004657 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004658
4659 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4660 mlxsw_sp_port->local_port);
4661 mlxsw_sp_port->lagged = 0;
4662 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004663
Ido Schimmelc57529e2017-05-26 08:37:31 +02004664 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4665 /* Make sure untagged frames are allowed to ingress */
4666 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004667}
4668
Jiri Pirko74581202015-12-03 12:12:30 +01004669static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4670 u16 lag_id)
4671{
4672 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4673 char sldr_pl[MLXSW_REG_SLDR_LEN];
4674
4675 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4676 mlxsw_sp_port->local_port);
4677 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4678}
4679
4680static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4681 u16 lag_id)
4682{
4683 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4684 char sldr_pl[MLXSW_REG_SLDR_LEN];
4685
4686 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4687 mlxsw_sp_port->local_port);
4688 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4689}
4690
4691static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4692 bool lag_tx_enabled)
4693{
4694 if (lag_tx_enabled)
4695 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4696 mlxsw_sp_port->lag_id);
4697 else
4698 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4699 mlxsw_sp_port->lag_id);
4700}
4701
4702static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4703 struct netdev_lag_lower_state_info *info)
4704{
4705 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4706}
4707
Jiri Pirko2b94e582017-04-18 16:55:37 +02004708static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4709 bool enable)
4710{
4711 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4712 enum mlxsw_reg_spms_state spms_state;
4713 char *spms_pl;
4714 u16 vid;
4715 int err;
4716
4717 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4718 MLXSW_REG_SPMS_STATE_DISCARDING;
4719
4720 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4721 if (!spms_pl)
4722 return -ENOMEM;
4723 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4724
4725 for (vid = 0; vid < VLAN_N_VID; vid++)
4726 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4727
4728 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4729 kfree(spms_pl);
4730 return err;
4731}
4732
4733static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4734{
Yuval Mintzfccff082017-12-15 08:44:21 +01004735 u16 vid = 1;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004736 int err;
4737
Ido Schimmel4aafc362017-05-26 08:37:25 +02004738 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004739 if (err)
4740 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02004741 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4742 if (err)
4743 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004744 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4745 true, false);
4746 if (err)
4747 goto err_port_vlan_set;
Yuval Mintzfccff082017-12-15 08:44:21 +01004748
4749 for (; vid <= VLAN_N_VID - 1; vid++) {
4750 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4751 vid, false);
4752 if (err)
4753 goto err_vid_learning_set;
4754 }
4755
Jiri Pirko2b94e582017-04-18 16:55:37 +02004756 return 0;
4757
Yuval Mintzfccff082017-12-15 08:44:21 +01004758err_vid_learning_set:
4759 for (vid--; vid >= 1; vid--)
4760 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004761err_port_vlan_set:
4762 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004763err_port_stp_set:
4764 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004765 return err;
4766}
4767
4768static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4769{
Yuval Mintzfccff082017-12-15 08:44:21 +01004770 u16 vid;
4771
4772 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4773 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4774 vid, true);
4775
Jiri Pirko2b94e582017-04-18 16:55:37 +02004776 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4777 false, false);
4778 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004779 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004780}
4781
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004782static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4783 struct net_device *dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004784 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004785{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004786 struct netdev_notifier_changeupper_info *info;
4787 struct mlxsw_sp_port *mlxsw_sp_port;
David Aherne58376e2017-10-04 17:48:51 -07004788 struct netlink_ext_ack *extack;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004789 struct net_device *upper_dev;
4790 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004791 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004792
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004793 mlxsw_sp_port = netdev_priv(dev);
4794 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4795 info = ptr;
David Aherne58376e2017-10-04 17:48:51 -07004796 extack = netdev_notifier_info_to_extack(&info->info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004797
4798 switch (event) {
4799 case NETDEV_PRECHANGEUPPER:
4800 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004801 if (!is_vlan_dev(upper_dev) &&
4802 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004803 !netif_is_bridge_master(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004804 !netif_is_ovs_master(upper_dev)) {
4805 NL_SET_ERR_MSG(extack,
4806 "spectrum: Unknown upper device type");
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004807 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004808 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004809 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004810 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004811 if (netdev_has_any_upper_dev(upper_dev) &&
4812 (!netif_is_bridge_master(upper_dev) ||
4813 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4814 upper_dev))) {
David Aherne58376e2017-10-04 17:48:51 -07004815 NL_SET_ERR_MSG(extack,
4816 "spectrum: Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004817 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004818 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004819 if (netif_is_lag_master(upper_dev) &&
4820 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
David Aherne58376e2017-10-04 17:48:51 -07004821 info->upper_info, extack))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004822 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004823 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
4824 NL_SET_ERR_MSG(extack,
4825 "spectrum: Master device is a LAG master and this device has a VLAN");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004826 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004827 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004828 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004829 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
4830 NL_SET_ERR_MSG(extack,
4831 "spectrum: Can not put a VLAN on a LAG port");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004832 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004833 }
4834 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
4835 NL_SET_ERR_MSG(extack,
4836 "spectrum: Master device is an OVS master and this device has a VLAN");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004837 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004838 }
4839 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
4840 NL_SET_ERR_MSG(extack,
4841 "spectrum: Can not put a VLAN on an OVS port");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004842 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004843 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004844 break;
4845 case NETDEV_CHANGEUPPER:
4846 upper_dev = info->upper_dev;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004847 if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004848 if (info->linking)
4849 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004850 lower_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004851 upper_dev,
4852 extack);
Ido Schimmel7117a572016-06-20 23:04:06 +02004853 else
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004854 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4855 lower_dev,
4856 upper_dev);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004857 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004858 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004859 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4860 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004861 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004862 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4863 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004864 } else if (netif_is_ovs_master(upper_dev)) {
4865 if (info->linking)
4866 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4867 else
4868 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004869 }
4870 break;
4871 }
4872
Ido Schimmel80bedf12016-06-20 23:03:59 +02004873 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004874}
4875
Jiri Pirko74581202015-12-03 12:12:30 +01004876static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4877 unsigned long event, void *ptr)
4878{
4879 struct netdev_notifier_changelowerstate_info *info;
4880 struct mlxsw_sp_port *mlxsw_sp_port;
4881 int err;
4882
4883 mlxsw_sp_port = netdev_priv(dev);
4884 info = ptr;
4885
4886 switch (event) {
4887 case NETDEV_CHANGELOWERSTATE:
4888 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4889 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4890 info->lower_state_info);
4891 if (err)
4892 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4893 }
4894 break;
4895 }
4896
Ido Schimmel80bedf12016-06-20 23:03:59 +02004897 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004898}
4899
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004900static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4901 struct net_device *port_dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004902 unsigned long event, void *ptr)
4903{
4904 switch (event) {
4905 case NETDEV_PRECHANGEUPPER:
4906 case NETDEV_CHANGEUPPER:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004907 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4908 event, ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004909 case NETDEV_CHANGELOWERSTATE:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004910 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4911 ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004912 }
4913
Ido Schimmel80bedf12016-06-20 23:03:59 +02004914 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004915}
4916
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004917static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4918 unsigned long event, void *ptr)
4919{
4920 struct net_device *dev;
4921 struct list_head *iter;
4922 int ret;
4923
4924 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4925 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004926 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4927 ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004928 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004929 return ret;
4930 }
4931 }
4932
Ido Schimmel80bedf12016-06-20 23:03:59 +02004933 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004934}
4935
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004936static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4937 struct net_device *dev,
4938 unsigned long event, void *ptr,
4939 u16 vid)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004940{
4941 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel90045fc2017-12-25 09:05:33 +01004942 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004943 struct netdev_notifier_changeupper_info *info = ptr;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004944 struct netlink_ext_ack *extack;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004945 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004946 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004947
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004948 extack = netdev_notifier_info_to_extack(&info->info);
4949
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004950 switch (event) {
4951 case NETDEV_PRECHANGEUPPER:
4952 upper_dev = info->upper_dev;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004953 if (!netif_is_bridge_master(upper_dev)) {
4954 NL_SET_ERR_MSG(extack, "spectrum: VLAN devices only support bridge and VRF uppers");
Ido Schimmel80bedf12016-06-20 23:03:59 +02004955 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004956 }
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004957 if (!info->linking)
4958 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004959 if (netdev_has_any_upper_dev(upper_dev) &&
4960 (!netif_is_bridge_master(upper_dev) ||
4961 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4962 upper_dev))) {
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004963 NL_SET_ERR_MSG(extack, "spectrum: Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004964 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004965 }
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004966 break;
4967 case NETDEV_CHANGEUPPER:
4968 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004969 if (netif_is_bridge_master(upper_dev)) {
4970 if (info->linking)
Ido Schimmelc57529e2017-05-26 08:37:31 +02004971 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4972 vlan_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004973 upper_dev,
4974 extack);
Ido Schimmel1f880612017-03-10 08:53:35 +01004975 else
Ido Schimmelc57529e2017-05-26 08:37:31 +02004976 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4977 vlan_dev,
4978 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004979 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004980 err = -EINVAL;
4981 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004982 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004983 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004984 }
4985
Ido Schimmel80bedf12016-06-20 23:03:59 +02004986 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004987}
4988
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004989static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4990 struct net_device *lag_dev,
4991 unsigned long event,
4992 void *ptr, u16 vid)
Ido Schimmel272c4472015-12-15 16:03:47 +01004993{
4994 struct net_device *dev;
4995 struct list_head *iter;
4996 int ret;
4997
4998 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4999 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02005000 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
5001 event, ptr,
5002 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02005003 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01005004 return ret;
5005 }
5006 }
5007
Ido Schimmel80bedf12016-06-20 23:03:59 +02005008 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01005009}
5010
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01005011static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
5012 unsigned long event, void *ptr)
5013{
5014 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
5015 u16 vid = vlan_dev_vlan_id(vlan_dev);
5016
Ido Schimmel272c4472015-12-15 16:03:47 +01005017 if (mlxsw_sp_port_dev_check(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02005018 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
5019 event, ptr, vid);
Ido Schimmel272c4472015-12-15 16:03:47 +01005020 else if (netif_is_lag_master(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02005021 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
5022 real_dev, event,
5023 ptr, vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01005024
Ido Schimmel80bedf12016-06-20 23:03:59 +02005025 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01005026}
5027
Ido Schimmelb1e45522017-04-30 19:47:14 +03005028static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
5029{
5030 struct netdev_notifier_changeupper_info *info = ptr;
5031
5032 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
5033 return false;
5034 return netif_is_l3_master(info->upper_dev);
5035}
5036
Petr Machata00635872017-10-16 16:26:37 +02005037static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005038 unsigned long event, void *ptr)
5039{
5040 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Petr Machata00635872017-10-16 16:26:37 +02005041 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02005042 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005043
Petr Machata00635872017-10-16 16:26:37 +02005044 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
Petr Machata796ec772017-11-03 10:03:29 +01005045 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
5046 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
5047 event, ptr);
Petr Machata61481f22017-11-03 10:03:41 +01005048 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
5049 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
5050 event, ptr);
Petr Machata00635872017-10-16 16:26:37 +02005051 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
Ido Schimmel6e095fd2016-07-04 08:23:13 +02005052 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03005053 else if (mlxsw_sp_is_vrf_event(event, ptr))
5054 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02005055 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02005056 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02005057 else if (netif_is_lag_master(dev))
5058 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
5059 else if (is_vlan_dev(dev))
5060 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005061
Ido Schimmel80bedf12016-06-20 23:03:59 +02005062 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005063}
5064
David Ahern89d5dd22017-10-18 09:56:55 -07005065static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
5066 .notifier_call = mlxsw_sp_inetaddr_valid_event,
5067};
5068
Ido Schimmel99724c12016-07-04 08:23:14 +02005069static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
5070 .notifier_call = mlxsw_sp_inetaddr_event,
David Ahern89d5dd22017-10-18 09:56:55 -07005071};
5072
5073static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
5074 .notifier_call = mlxsw_sp_inet6addr_valid_event,
Ido Schimmel99724c12016-07-04 08:23:14 +02005075};
5076
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005077static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
5078 .notifier_call = mlxsw_sp_inet6addr_event,
5079};
5080
Jiri Pirko1d20d232016-10-27 15:12:59 +02005081static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
5082 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
5083 {0, },
5084};
5085
5086static struct pci_driver mlxsw_sp_pci_driver = {
5087 .name = mlxsw_sp_driver_name,
5088 .id_table = mlxsw_sp_pci_id_table,
5089};
5090
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005091static int __init mlxsw_sp_module_init(void)
5092{
5093 int err;
5094
David Ahern89d5dd22017-10-18 09:56:55 -07005095 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02005096 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005097 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005098 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02005099
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005100 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
5101 if (err)
5102 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02005103
5104 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
5105 if (err)
5106 goto err_pci_driver_register;
5107
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005108 return 0;
5109
Jiri Pirko1d20d232016-10-27 15:12:59 +02005110err_pci_driver_register:
5111 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005112err_core_driver_register:
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005113 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005114 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02005115 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005116 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005117 return err;
5118}
5119
5120static void __exit mlxsw_sp_module_exit(void)
5121{
Jiri Pirko1d20d232016-10-27 15:12:59 +02005122 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005123 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005124 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005125 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02005126 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005127 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005128}
5129
5130module_init(mlxsw_sp_module_init);
5131module_exit(mlxsw_sp_module_exit);
5132
5133MODULE_LICENSE("Dual BSD/GPL");
5134MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
5135MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02005136MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Yotam Gigi6b742192017-05-23 21:56:29 +02005137MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);