blob: 7e2b552c2237c6cb5e3cf0942eb8a49f77b46a46 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Jiri Pirko22a67762017-02-03 10:29:07 +01003 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +020056#include <linux/netlink.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020057#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020058#include <net/pkt_cls.h>
59#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020060#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010061#include <net/tc_act/tc_sample.h>
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +020062#include <net/addrconf.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020063
64#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020065#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020066#include "core.h"
67#include "reg.h"
68#include "port.h"
69#include "trap.h"
70#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010071#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020072#include "spectrum_dpipe.h"
Yotam Gigid3b939b2017-09-19 10:00:09 +020073#include "spectrum_acl_flex_actions.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020074#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020075
Yotam Gigi6b742192017-05-23 21:56:29 +020076#define MLXSW_FWREV_MAJOR 13
Shalom Toledo2f53fbd2017-11-12 09:01:24 +010077#define MLXSW_FWREV_MINOR 1530
78#define MLXSW_FWREV_SUBMINOR 152
Yuval Mintzfd5204c2018-01-18 12:55:23 +010079#define MLXSW_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
Yotam Gigi6b742192017-05-23 21:56:29 +020080
81#define MLXSW_SP_FW_FILENAME \
Yotam Gigia4e1ce22017-06-04 16:49:58 +020082 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
Yotam Gigi6b742192017-05-23 21:56:29 +020083 "." __stringify(MLXSW_FWREV_MINOR) \
84 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
85
Jiri Pirko56ade8f2015-10-16 14:01:37 +020086static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
87static const char mlxsw_sp_driver_version[] = "1.0";
88
89/* tx_hdr_version
90 * Tx header version.
91 * Must be set to 1.
92 */
93MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
94
95/* tx_hdr_ctl
96 * Packet control type.
97 * 0 - Ethernet control (e.g. EMADs, LACP)
98 * 1 - Ethernet data
99 */
100MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
101
102/* tx_hdr_proto
103 * Packet protocol type. Must be set to 1 (Ethernet).
104 */
105MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
106
107/* tx_hdr_rx_is_router
108 * Packet is sent from the router. Valid for data packets only.
109 */
110MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
111
112/* tx_hdr_fid_valid
113 * Indicates if the 'fid' field is valid and should be used for
114 * forwarding lookup. Valid for data packets only.
115 */
116MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
117
118/* tx_hdr_swid
119 * Switch partition ID. Must be set to 0.
120 */
121MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
122
123/* tx_hdr_control_tclass
124 * Indicates if the packet should use the control TClass and not one
125 * of the data TClasses.
126 */
127MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
128
129/* tx_hdr_etclass
130 * Egress TClass to be used on the egress device on the egress port.
131 */
132MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
133
134/* tx_hdr_port_mid
135 * Destination local port for unicast packets.
136 * Destination multicast ID for multicast packets.
137 *
138 * Control packets are directed to a specific egress port, while data
139 * packets are transmitted through the CPU port (0) into the switch partition,
140 * where forwarding rules are applied.
141 */
142MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
143
144/* tx_hdr_fid
145 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
146 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
147 * Valid for data packets only.
148 */
149MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
150
151/* tx_hdr_type
152 * 0 - Data packets
153 * 6 - Control packets
154 */
155MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
156
Yotam Gigie5e5c882017-05-23 21:56:27 +0200157struct mlxsw_sp_mlxfw_dev {
158 struct mlxfw_dev mlxfw_dev;
159 struct mlxsw_sp *mlxsw_sp;
160};
161
162static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
163 u16 component_index, u32 *p_max_size,
164 u8 *p_align_bits, u16 *p_max_write_size)
165{
166 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
167 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
168 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
169 char mcqi_pl[MLXSW_REG_MCQI_LEN];
170 int err;
171
172 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
173 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
174 if (err)
175 return err;
176 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
177 p_max_write_size);
178
179 *p_align_bits = max_t(u8, *p_align_bits, 2);
180 *p_max_write_size = min_t(u16, *p_max_write_size,
181 MLXSW_REG_MCDA_MAX_DATA_LEN);
182 return 0;
183}
184
185static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
186{
187 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
188 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
189 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
190 char mcc_pl[MLXSW_REG_MCC_LEN];
191 u8 control_state;
192 int err;
193
194 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
195 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
196 if (err)
197 return err;
198
199 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
200 if (control_state != MLXFW_FSM_STATE_IDLE)
201 return -EBUSY;
202
203 mlxsw_reg_mcc_pack(mcc_pl,
204 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
205 0, *fwhandle, 0);
206 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
207}
208
209static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
210 u32 fwhandle, u16 component_index,
211 u32 component_size)
212{
213 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
214 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
215 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
216 char mcc_pl[MLXSW_REG_MCC_LEN];
217
218 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
219 component_index, fwhandle, component_size);
220 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
221}
222
223static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
224 u32 fwhandle, u8 *data, u16 size,
225 u32 offset)
226{
227 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
228 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
229 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
230 char mcda_pl[MLXSW_REG_MCDA_LEN];
231
232 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
233 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
234}
235
236static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
237 u32 fwhandle, u16 component_index)
238{
239 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
240 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
241 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
242 char mcc_pl[MLXSW_REG_MCC_LEN];
243
244 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
245 component_index, fwhandle, 0);
246 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
247}
248
249static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
250{
251 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
252 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
253 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
254 char mcc_pl[MLXSW_REG_MCC_LEN];
255
256 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
257 fwhandle, 0);
258 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
259}
260
261static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
262 enum mlxfw_fsm_state *fsm_state,
263 enum mlxfw_fsm_state_err *fsm_state_err)
264{
265 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
266 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
267 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
268 char mcc_pl[MLXSW_REG_MCC_LEN];
269 u8 control_state;
270 u8 error_code;
271 int err;
272
273 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
274 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
275 if (err)
276 return err;
277
278 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
279 *fsm_state = control_state;
280 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
281 MLXFW_FSM_STATE_ERR_MAX);
282 return 0;
283}
284
285static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
286{
287 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
288 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
289 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
290 char mcc_pl[MLXSW_REG_MCC_LEN];
291
292 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
293 fwhandle, 0);
294 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
295}
296
297static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
298{
299 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
300 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
301 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
302 char mcc_pl[MLXSW_REG_MCC_LEN];
303
304 mlxsw_reg_mcc_pack(mcc_pl,
305 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
306 fwhandle, 0);
307 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
308}
309
310static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
311 .component_query = mlxsw_sp_component_query,
312 .fsm_lock = mlxsw_sp_fsm_lock,
313 .fsm_component_update = mlxsw_sp_fsm_component_update,
314 .fsm_block_download = mlxsw_sp_fsm_block_download,
315 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
316 .fsm_activate = mlxsw_sp_fsm_activate,
317 .fsm_query_state = mlxsw_sp_fsm_query_state,
318 .fsm_cancel = mlxsw_sp_fsm_cancel,
319 .fsm_release = mlxsw_sp_fsm_release
320};
321
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300322static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
323 const struct firmware *firmware)
324{
325 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
326 .mlxfw_dev = {
327 .ops = &mlxsw_sp_mlxfw_dev_ops,
328 .psid = mlxsw_sp->bus_info->psid,
329 .psid_size = strlen(mlxsw_sp->bus_info->psid),
330 },
331 .mlxsw_sp = mlxsw_sp
332 };
333
334 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
335}
336
Yotam Gigi6b742192017-05-23 21:56:29 +0200337static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
338{
339 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
Yotam Gigi6b742192017-05-23 21:56:29 +0200340 const struct firmware *firmware;
341 int err;
342
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100343 /* Validate driver & FW are compatible */
344 if (rev->major != MLXSW_FWREV_MAJOR) {
345 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
346 rev->major, MLXSW_FWREV_MAJOR);
347 return -EINVAL;
348 }
349 if (MLXSW_FWREV_MINOR_TO_BRANCH(rev->minor) ==
350 MLXSW_FWREV_MINOR_TO_BRANCH(MLXSW_FWREV_MINOR))
Yotam Gigi6b742192017-05-23 21:56:29 +0200351 return 0;
352
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100353 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200354 rev->major, rev->minor, rev->subminor);
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100355 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200356 MLXSW_SP_FW_FILENAME);
357
358 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
359 mlxsw_sp->bus_info->dev);
360 if (err) {
361 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
362 MLXSW_SP_FW_FILENAME);
363 return err;
364 }
365
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300366 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
Yotam Gigi6b742192017-05-23 21:56:29 +0200367 release_firmware(firmware);
368 return err;
369}
370
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100371int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
372 unsigned int counter_index, u64 *packets,
373 u64 *bytes)
374{
375 char mgpc_pl[MLXSW_REG_MGPC_LEN];
376 int err;
377
378 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200379 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100380 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
381 if (err)
382 return err;
Arkadi Sharshevsky7cfcbc72017-08-24 08:40:08 +0200383 if (packets)
384 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
385 if (bytes)
386 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100387 return 0;
388}
389
390static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
391 unsigned int counter_index)
392{
393 char mgpc_pl[MLXSW_REG_MGPC_LEN];
394
395 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200396 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100397 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
398}
399
400int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
401 unsigned int *p_counter_index)
402{
403 int err;
404
405 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
406 p_counter_index);
407 if (err)
408 return err;
409 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
410 if (err)
411 goto err_counter_clear;
412 return 0;
413
414err_counter_clear:
415 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
416 *p_counter_index);
417 return err;
418}
419
420void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
421 unsigned int counter_index)
422{
423 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
424 counter_index);
425}
426
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200427static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
428 const struct mlxsw_tx_info *tx_info)
429{
430 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
431
432 memset(txhdr, 0, MLXSW_TXHDR_LEN);
433
434 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
435 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
436 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
437 mlxsw_tx_hdr_swid_set(txhdr, 0);
438 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
439 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
440 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
441}
442
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200443int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
444 u8 state)
445{
446 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
447 enum mlxsw_reg_spms_state spms_state;
448 char *spms_pl;
449 int err;
450
451 switch (state) {
452 case BR_STATE_FORWARDING:
453 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
454 break;
455 case BR_STATE_LEARNING:
456 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
457 break;
458 case BR_STATE_LISTENING: /* fall-through */
459 case BR_STATE_DISABLED: /* fall-through */
460 case BR_STATE_BLOCKING:
461 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
462 break;
463 default:
464 BUG();
465 }
466
467 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
468 if (!spms_pl)
469 return -ENOMEM;
470 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
471 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
472
473 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
474 kfree(spms_pl);
475 return err;
476}
477
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200478static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
479{
Elad Raz5b090742016-10-28 21:35:46 +0200480 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200481 int err;
482
483 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
484 if (err)
485 return err;
486 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
487 return 0;
488}
489
Yotam Gigi763b4b72016-07-21 12:03:17 +0200490static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
491{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200492 int i;
493
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200494 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
Yotam Gigi763b4b72016-07-21 12:03:17 +0200495 return -EIO;
496
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200497 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
498 MAX_SPAN);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200499 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
500 sizeof(struct mlxsw_sp_span_entry),
501 GFP_KERNEL);
502 if (!mlxsw_sp->span.entries)
503 return -ENOMEM;
504
505 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
506 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
507
508 return 0;
509}
510
511static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
512{
513 int i;
514
515 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
516 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
517
518 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
519 }
520 kfree(mlxsw_sp->span.entries);
521}
522
523static struct mlxsw_sp_span_entry *
524mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
525{
526 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
527 struct mlxsw_sp_span_entry *span_entry;
528 char mpat_pl[MLXSW_REG_MPAT_LEN];
529 u8 local_port = port->local_port;
530 int index;
531 int i;
532 int err;
533
534 /* find a free entry to use */
535 index = -1;
536 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
537 if (!mlxsw_sp->span.entries[i].used) {
538 index = i;
539 span_entry = &mlxsw_sp->span.entries[i];
540 break;
541 }
542 }
543 if (index < 0)
544 return NULL;
545
546 /* create a new port analayzer entry for local_port */
547 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
548 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
549 if (err)
550 return NULL;
551
552 span_entry->used = true;
553 span_entry->id = index;
Yotam Gigi2d644d42016-11-11 16:34:25 +0100554 span_entry->ref_count = 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200555 span_entry->local_port = local_port;
556 return span_entry;
557}
558
559static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
560 struct mlxsw_sp_span_entry *span_entry)
561{
562 u8 local_port = span_entry->local_port;
563 char mpat_pl[MLXSW_REG_MPAT_LEN];
564 int pa_id = span_entry->id;
565
566 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
567 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
568 span_entry->used = false;
569}
570
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200571static struct mlxsw_sp_span_entry *
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200572mlxsw_sp_span_entry_find(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200573{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200574 int i;
575
576 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
577 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
578
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200579 if (curr->used && curr->local_port == local_port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200580 return curr;
581 }
582 return NULL;
583}
584
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200585static struct mlxsw_sp_span_entry
586*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200587{
588 struct mlxsw_sp_span_entry *span_entry;
589
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200590 span_entry = mlxsw_sp_span_entry_find(port->mlxsw_sp,
591 port->local_port);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200592 if (span_entry) {
Yotam Gigi2d644d42016-11-11 16:34:25 +0100593 /* Already exists, just take a reference */
Yotam Gigi763b4b72016-07-21 12:03:17 +0200594 span_entry->ref_count++;
595 return span_entry;
596 }
597
598 return mlxsw_sp_span_entry_create(port);
599}
600
601static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
602 struct mlxsw_sp_span_entry *span_entry)
603{
Yotam Gigi2d644d42016-11-11 16:34:25 +0100604 WARN_ON(!span_entry->ref_count);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200605 if (--span_entry->ref_count == 0)
606 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
607 return 0;
608}
609
610static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
611{
612 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
613 struct mlxsw_sp_span_inspected_port *p;
614 int i;
615
616 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
617 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
618
619 list_for_each_entry(p, &curr->bound_ports_list, list)
620 if (p->local_port == port->local_port &&
621 p->type == MLXSW_SP_SPAN_EGRESS)
622 return true;
623 }
624
625 return false;
626}
627
Ido Schimmel18281f22017-03-24 08:02:51 +0100628static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
629 int mtu)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200630{
Ido Schimmel18281f22017-03-24 08:02:51 +0100631 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200632}
633
634static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
635{
636 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
637 char sbib_pl[MLXSW_REG_SBIB_LEN];
638 int err;
639
640 /* If port is egress mirrored, the shared buffer size should be
641 * updated according to the mtu value
642 */
643 if (mlxsw_sp_span_is_egress_mirror(port)) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100644 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
645
646 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200647 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
648 if (err) {
649 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
650 return err;
651 }
652 }
653
654 return 0;
655}
656
657static struct mlxsw_sp_span_inspected_port *
658mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
659 struct mlxsw_sp_span_entry *span_entry)
660{
661 struct mlxsw_sp_span_inspected_port *p;
662
663 list_for_each_entry(p, &span_entry->bound_ports_list, list)
664 if (port->local_port == p->local_port)
665 return p;
666 return NULL;
667}
668
669static int
670mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
671 struct mlxsw_sp_span_entry *span_entry,
672 enum mlxsw_sp_span_type type)
673{
674 struct mlxsw_sp_span_inspected_port *inspected_port;
675 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
676 char mpar_pl[MLXSW_REG_MPAR_LEN];
677 char sbib_pl[MLXSW_REG_SBIB_LEN];
678 int pa_id = span_entry->id;
679 int err;
680
681 /* if it is an egress SPAN, bind a shared buffer to it */
682 if (type == MLXSW_SP_SPAN_EGRESS) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100683 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
684 port->dev->mtu);
685
686 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200687 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
688 if (err) {
689 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
690 return err;
691 }
692 }
693
694 /* bind the port to the SPAN entry */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200695 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
696 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200697 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
698 if (err)
699 goto err_mpar_reg_write;
700
701 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
702 if (!inspected_port) {
703 err = -ENOMEM;
704 goto err_inspected_port_alloc;
705 }
706 inspected_port->local_port = port->local_port;
707 inspected_port->type = type;
708 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
709
710 return 0;
711
712err_mpar_reg_write:
713err_inspected_port_alloc:
714 if (type == MLXSW_SP_SPAN_EGRESS) {
715 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
716 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
717 }
718 return err;
719}
720
721static void
722mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
723 struct mlxsw_sp_span_entry *span_entry,
724 enum mlxsw_sp_span_type type)
725{
726 struct mlxsw_sp_span_inspected_port *inspected_port;
727 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
728 char mpar_pl[MLXSW_REG_MPAR_LEN];
729 char sbib_pl[MLXSW_REG_SBIB_LEN];
730 int pa_id = span_entry->id;
731
732 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
733 if (!inspected_port)
734 return;
735
736 /* remove the inspected port */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200737 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
738 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200739 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
740
741 /* remove the SBIB buffer if it was egress SPAN */
742 if (type == MLXSW_SP_SPAN_EGRESS) {
743 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
744 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
745 }
746
747 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
748
749 list_del(&inspected_port->list);
750 kfree(inspected_port);
751}
752
753static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
754 struct mlxsw_sp_port *to,
755 enum mlxsw_sp_span_type type)
756{
757 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
758 struct mlxsw_sp_span_entry *span_entry;
759 int err;
760
761 span_entry = mlxsw_sp_span_entry_get(to);
762 if (!span_entry)
763 return -ENOENT;
764
765 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
766 span_entry->id);
767
768 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
769 if (err)
770 goto err_port_bind;
771
772 return 0;
773
774err_port_bind:
775 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
776 return err;
777}
778
779static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200780 u8 destination_port,
Yotam Gigi763b4b72016-07-21 12:03:17 +0200781 enum mlxsw_sp_span_type type)
782{
783 struct mlxsw_sp_span_entry *span_entry;
784
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200785 span_entry = mlxsw_sp_span_entry_find(from->mlxsw_sp,
786 destination_port);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200787 if (!span_entry) {
788 netdev_err(from->dev, "no span entry found\n");
789 return;
790 }
791
792 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
793 span_entry->id);
794 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
795}
796
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100797static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
798 bool enable, u32 rate)
799{
800 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
801 char mpsc_pl[MLXSW_REG_MPSC_LEN];
802
803 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
804 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
805}
806
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200807static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
808 bool is_up)
809{
810 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
811 char paos_pl[MLXSW_REG_PAOS_LEN];
812
813 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
814 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
815 MLXSW_PORT_ADMIN_STATUS_DOWN);
816 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
817}
818
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200819static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
820 unsigned char *addr)
821{
822 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
823 char ppad_pl[MLXSW_REG_PPAD_LEN];
824
825 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
826 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
827 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
828}
829
830static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
831{
832 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
833 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
834
835 ether_addr_copy(addr, mlxsw_sp->base_mac);
836 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
837 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
838}
839
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200840static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
841{
842 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
843 char pmtu_pl[MLXSW_REG_PMTU_LEN];
844 int max_mtu;
845 int err;
846
847 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
848 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
849 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
850 if (err)
851 return err;
852 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
853
854 if (mtu > max_mtu)
855 return -EINVAL;
856
857 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
858 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
859}
860
861static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
862{
863 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel5b153852017-06-08 08:47:44 +0200864 char pspa_pl[MLXSW_REG_PSPA_LEN];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200865
Ido Schimmel5b153852017-06-08 08:47:44 +0200866 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
867 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200868}
869
Ido Schimmela1107482017-05-26 08:37:39 +0200870int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200871{
872 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
873 char svpe_pl[MLXSW_REG_SVPE_LEN];
874
875 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
876 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
877}
878
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200879int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
880 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200881{
882 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
883 char *spvmlr_pl;
884 int err;
885
886 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
887 if (!spvmlr_pl)
888 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200889 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
890 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200891 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
892 kfree(spvmlr_pl);
893 return err;
894}
895
Ido Schimmelb02eae92017-05-16 19:38:34 +0200896static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
897 u16 vid)
898{
899 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
900 char spvid_pl[MLXSW_REG_SPVID_LEN];
901
902 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
903 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
904}
905
906static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
907 bool allow)
908{
909 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
910 char spaft_pl[MLXSW_REG_SPAFT_LEN];
911
912 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
913 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
914}
915
916int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
917{
918 int err;
919
920 if (!vid) {
921 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
922 if (err)
923 return err;
924 } else {
925 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
926 if (err)
927 return err;
928 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
929 if (err)
930 goto err_port_allow_untagged_set;
931 }
932
933 mlxsw_sp_port->pvid = vid;
934 return 0;
935
936err_port_allow_untagged_set:
937 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
938 return err;
939}
940
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200941static int
942mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
943{
944 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
945 char sspr_pl[MLXSW_REG_SSPR_LEN];
946
947 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
948 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
949}
950
Ido Schimmeld664b412016-06-09 09:51:40 +0200951static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
952 u8 local_port, u8 *p_module,
953 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200954{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200955 char pmlp_pl[MLXSW_REG_PMLP_LEN];
956 int err;
957
Ido Schimmel558c2d52016-02-26 17:32:29 +0100958 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200959 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
960 if (err)
961 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100962 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
963 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200964 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200965 return 0;
966}
967
Ido Schimmel2e915e02017-06-08 08:47:45 +0200968static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100969 u8 module, u8 width, u8 lane)
970{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200971 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel18f1e702016-02-26 17:32:31 +0100972 char pmlp_pl[MLXSW_REG_PMLP_LEN];
973 int i;
974
Ido Schimmel2e915e02017-06-08 08:47:45 +0200975 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel18f1e702016-02-26 17:32:31 +0100976 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
977 for (i = 0; i < width; i++) {
978 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
979 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
980 }
981
982 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
983}
984
Ido Schimmel2e915e02017-06-08 08:47:45 +0200985static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100986{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200987 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100988 char pmlp_pl[MLXSW_REG_PMLP_LEN];
989
Ido Schimmel2e915e02017-06-08 08:47:45 +0200990 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100991 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
992 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
993}
994
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200995static int mlxsw_sp_port_open(struct net_device *dev)
996{
997 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
998 int err;
999
1000 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1001 if (err)
1002 return err;
1003 netif_start_queue(dev);
1004 return 0;
1005}
1006
1007static int mlxsw_sp_port_stop(struct net_device *dev)
1008{
1009 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1010
1011 netif_stop_queue(dev);
1012 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1013}
1014
1015static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
1016 struct net_device *dev)
1017{
1018 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1019 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1020 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
1021 const struct mlxsw_tx_info tx_info = {
1022 .local_port = mlxsw_sp_port->local_port,
1023 .is_emad = false,
1024 };
1025 u64 len;
1026 int err;
1027
Jiri Pirko307c2432016-04-08 19:11:22 +02001028 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001029 return NETDEV_TX_BUSY;
1030
1031 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
1032 struct sk_buff *skb_orig = skb;
1033
1034 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
1035 if (!skb) {
1036 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1037 dev_kfree_skb_any(skb_orig);
1038 return NETDEV_TX_OK;
1039 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +01001040 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001041 }
1042
1043 if (eth_skb_pad(skb)) {
1044 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1045 return NETDEV_TX_OK;
1046 }
1047
1048 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +02001049 /* TX header is consumed by HW on the way so we shouldn't count its
1050 * bytes as being sent.
1051 */
1052 len = skb->len - MLXSW_TXHDR_LEN;
1053
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001054 /* Due to a race we might fail here because of a full queue. In that
1055 * unlikely case we simply drop the packet.
1056 */
Jiri Pirko307c2432016-04-08 19:11:22 +02001057 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001058
1059 if (!err) {
1060 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
1061 u64_stats_update_begin(&pcpu_stats->syncp);
1062 pcpu_stats->tx_packets++;
1063 pcpu_stats->tx_bytes += len;
1064 u64_stats_update_end(&pcpu_stats->syncp);
1065 } else {
1066 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1067 dev_kfree_skb_any(skb);
1068 }
1069 return NETDEV_TX_OK;
1070}
1071
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001072static void mlxsw_sp_set_rx_mode(struct net_device *dev)
1073{
1074}
1075
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001076static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
1077{
1078 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1079 struct sockaddr *addr = p;
1080 int err;
1081
1082 if (!is_valid_ether_addr(addr->sa_data))
1083 return -EADDRNOTAVAIL;
1084
1085 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
1086 if (err)
1087 return err;
1088 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1089 return 0;
1090}
1091
Ido Schimmel18281f22017-03-24 08:02:51 +01001092static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
1093 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001094{
Ido Schimmel18281f22017-03-24 08:02:51 +01001095 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001096}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001097
Ido Schimmelf417f042017-03-24 08:02:50 +01001098#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +01001099
1100static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1101 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +01001102{
Ido Schimmel18281f22017-03-24 08:02:51 +01001103 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
1104 BITS_PER_BYTE));
1105 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
1106 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001107}
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001108
Ido Schimmel18281f22017-03-24 08:02:51 +01001109/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +01001110 * Assumes 100m cable and maximum MTU.
1111 */
Ido Schimmel18281f22017-03-24 08:02:51 +01001112#define MLXSW_SP_PAUSE_DELAY 58752
1113
1114static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1115 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +01001116{
1117 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +01001118 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +01001119 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +01001120 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001121 else
Ido Schimmelf417f042017-03-24 08:02:50 +01001122 return 0;
1123}
1124
1125static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
1126 bool lossy)
1127{
1128 if (lossy)
1129 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
1130 else
1131 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
1132 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001133}
1134
1135int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001136 u8 *prio_tc, bool pause_en,
1137 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +02001138{
1139 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001140 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
1141 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001142 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001143 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001144
1145 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
1146 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1147 if (err)
1148 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001149
1150 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1151 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001152 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +01001153 bool lossy;
1154 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001155
1156 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
1157 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001158 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001159 configure = true;
1160 break;
1161 }
1162 }
1163
1164 if (!configure)
1165 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +01001166
1167 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +01001168 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
1169 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
1170 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +01001171 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001172 }
1173
Ido Schimmelff6551e2016-04-06 17:10:03 +02001174 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1175}
1176
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001177static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001178 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001179{
1180 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
1181 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001182 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001183 u8 *prio_tc;
1184
1185 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001186 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001187
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001188 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001189 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001190}
1191
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001192static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
1193{
1194 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001195 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001196 int err;
1197
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001198 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001199 if (err)
1200 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001201 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1202 if (err)
1203 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001204 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1205 if (err)
1206 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001207 dev->mtu = mtu;
1208 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001209
1210err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001211 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1212err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001213 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +02001214 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001215}
1216
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001217static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001218mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1219 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001220{
1221 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1222 struct mlxsw_sp_port_pcpu_stats *p;
1223 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1224 u32 tx_dropped = 0;
1225 unsigned int start;
1226 int i;
1227
1228 for_each_possible_cpu(i) {
1229 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1230 do {
1231 start = u64_stats_fetch_begin_irq(&p->syncp);
1232 rx_packets = p->rx_packets;
1233 rx_bytes = p->rx_bytes;
1234 tx_packets = p->tx_packets;
1235 tx_bytes = p->tx_bytes;
1236 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1237
1238 stats->rx_packets += rx_packets;
1239 stats->rx_bytes += rx_bytes;
1240 stats->tx_packets += tx_packets;
1241 stats->tx_bytes += tx_bytes;
1242 /* tx_dropped is u32, updated without syncp protection. */
1243 tx_dropped += p->tx_dropped;
1244 }
1245 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001246 return 0;
1247}
1248
Or Gerlitz3df5b3c2016-11-22 23:09:54 +02001249static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001250{
1251 switch (attr_id) {
1252 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1253 return true;
1254 }
1255
1256 return false;
1257}
1258
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001259static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1260 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001261{
1262 switch (attr_id) {
1263 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1264 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1265 }
1266
1267 return -EINVAL;
1268}
1269
1270static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1271 int prio, char *ppcnt_pl)
1272{
1273 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1274 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1275
1276 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1277 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1278}
1279
1280static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1281 struct rtnl_link_stats64 *stats)
1282{
1283 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1284 int err;
1285
1286 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1287 0, ppcnt_pl);
1288 if (err)
1289 goto out;
1290
1291 stats->tx_packets =
1292 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1293 stats->rx_packets =
1294 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1295 stats->tx_bytes =
1296 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1297 stats->rx_bytes =
1298 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1299 stats->multicast =
1300 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1301
1302 stats->rx_crc_errors =
1303 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1304 stats->rx_frame_errors =
1305 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1306
1307 stats->rx_length_errors = (
1308 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1309 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1310 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1311
1312 stats->rx_errors = (stats->rx_crc_errors +
1313 stats->rx_frame_errors + stats->rx_length_errors);
1314
1315out:
1316 return err;
1317}
1318
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001319static void
1320mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1321 struct mlxsw_sp_port_xstats *xstats)
1322{
1323 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1324 int err, i;
1325
1326 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1327 ppcnt_pl);
1328 if (!err)
1329 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1330
1331 for (i = 0; i < TC_MAX_QUEUE; i++) {
1332 err = mlxsw_sp_port_get_stats_raw(dev,
1333 MLXSW_REG_PPCNT_TC_CONG_TC,
1334 i, ppcnt_pl);
1335 if (!err)
1336 xstats->wred_drop[i] =
1337 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1338
1339 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1340 i, ppcnt_pl);
1341 if (err)
1342 continue;
1343
1344 xstats->backlog[i] =
1345 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1346 xstats->tail_drop[i] =
1347 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1348 }
1349}
1350
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001351static void update_stats_cache(struct work_struct *work)
1352{
1353 struct mlxsw_sp_port *mlxsw_sp_port =
1354 container_of(work, struct mlxsw_sp_port,
Nogah Frankel9deef432017-10-26 10:55:32 +02001355 periodic_hw_stats.update_dw.work);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001356
1357 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1358 goto out;
1359
1360 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
Nogah Frankel9deef432017-10-26 10:55:32 +02001361 &mlxsw_sp_port->periodic_hw_stats.stats);
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001362 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1363 &mlxsw_sp_port->periodic_hw_stats.xstats);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001364
1365out:
Nogah Frankel9deef432017-10-26 10:55:32 +02001366 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001367 MLXSW_HW_STATS_UPDATE_TIME);
1368}
1369
1370/* Return the stats from a cache that is updated periodically,
1371 * as this function might get called in an atomic context.
1372 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001373static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001374mlxsw_sp_port_get_stats64(struct net_device *dev,
1375 struct rtnl_link_stats64 *stats)
1376{
1377 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1378
Nogah Frankel9deef432017-10-26 10:55:32 +02001379 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001380}
1381
Jiri Pirko93cd0812017-04-18 16:55:35 +02001382static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1383 u16 vid_begin, u16 vid_end,
1384 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001385{
1386 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1387 char *spvm_pl;
1388 int err;
1389
1390 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1391 if (!spvm_pl)
1392 return -ENOMEM;
1393
1394 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1395 vid_end, is_member, untagged);
1396 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1397 kfree(spvm_pl);
1398 return err;
1399}
1400
Jiri Pirko93cd0812017-04-18 16:55:35 +02001401int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1402 u16 vid_end, bool is_member, bool untagged)
1403{
1404 u16 vid, vid_e;
1405 int err;
1406
1407 for (vid = vid_begin; vid <= vid_end;
1408 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1409 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1410 vid_end);
1411
1412 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1413 is_member, untagged);
1414 if (err)
1415 return err;
1416 }
1417
1418 return 0;
1419}
1420
Ido Schimmelc57529e2017-05-26 08:37:31 +02001421static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001422{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001423 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001424
Ido Schimmelc57529e2017-05-26 08:37:31 +02001425 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1426 &mlxsw_sp_port->vlans_list, list)
1427 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001428}
1429
Ido Schimmel31a08a52017-05-26 08:37:26 +02001430static struct mlxsw_sp_port_vlan *
1431mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1432{
1433 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001434 bool untagged = vid == 1;
1435 int err;
1436
1437 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1438 if (err)
1439 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001440
1441 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001442 if (!mlxsw_sp_port_vlan) {
1443 err = -ENOMEM;
1444 goto err_port_vlan_alloc;
1445 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02001446
1447 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1448 mlxsw_sp_port_vlan->vid = vid;
1449 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1450
1451 return mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001452
1453err_port_vlan_alloc:
1454 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1455 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001456}
1457
1458static void
1459mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1460{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001461 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1462 u16 vid = mlxsw_sp_port_vlan->vid;
Ido Schimmel7cbecf22017-05-26 08:37:28 +02001463
Ido Schimmel31a08a52017-05-26 08:37:26 +02001464 list_del(&mlxsw_sp_port_vlan->list);
1465 kfree(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001466 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1467}
1468
1469struct mlxsw_sp_port_vlan *
1470mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1471{
1472 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1473
1474 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1475 if (mlxsw_sp_port_vlan)
1476 return mlxsw_sp_port_vlan;
1477
1478 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1479}
1480
1481void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1482{
Ido Schimmela1107482017-05-26 08:37:39 +02001483 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1484
Ido Schimmelc57529e2017-05-26 08:37:31 +02001485 if (mlxsw_sp_port_vlan->bridge_port)
1486 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
Ido Schimmela1107482017-05-26 08:37:39 +02001487 else if (fid)
1488 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001489
1490 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001491}
1492
Ido Schimmel05978482016-08-17 16:39:30 +02001493static int mlxsw_sp_port_add_vid(struct net_device *dev,
1494 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001495{
1496 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001497
1498 /* VLAN 0 is added to HW filter when device goes up, but it is
1499 * reserved in our case, so simply return.
1500 */
1501 if (!vid)
1502 return 0;
1503
Ido Schimmelc57529e2017-05-26 08:37:31 +02001504 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001505}
1506
Ido Schimmel32d863f2016-07-02 11:00:10 +02001507static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1508 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001509{
1510 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001511 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001512
1513 /* VLAN 0 is removed from HW filter when device goes down, but
1514 * it is reserved in our case, so simply return.
1515 */
1516 if (!vid)
1517 return 0;
1518
Ido Schimmel31a08a52017-05-26 08:37:26 +02001519 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001520 if (!mlxsw_sp_port_vlan)
Ido Schimmel31a08a52017-05-26 08:37:26 +02001521 return 0;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001522 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001523
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001524 return 0;
1525}
1526
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001527static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1528 size_t len)
1529{
1530 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +02001531 u8 module = mlxsw_sp_port->mapping.module;
1532 u8 width = mlxsw_sp_port->mapping.width;
1533 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001534 int err;
1535
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001536 if (!mlxsw_sp_port->split)
1537 err = snprintf(name, len, "p%d", module + 1);
1538 else
1539 err = snprintf(name, len, "p%ds%d", module + 1,
1540 lane / width);
1541
1542 if (err >= len)
1543 return -EINVAL;
1544
1545 return 0;
1546}
1547
Yotam Gigi763b4b72016-07-21 12:03:17 +02001548static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001549mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1550 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001551 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1552
1553 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1554 if (mall_tc_entry->cookie == cookie)
1555 return mall_tc_entry;
1556
1557 return NULL;
1558}
1559
1560static int
1561mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001562 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001563 const struct tc_action *a,
1564 bool ingress)
1565{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001566 enum mlxsw_sp_span_type span_type;
1567 struct mlxsw_sp_port *to_port;
1568 struct net_device *to_dev;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001569
Cong Wang9f8a7392017-12-05 16:17:26 -08001570 to_dev = tcf_mirred_dev(a);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001571 if (!to_dev) {
1572 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1573 return -EINVAL;
1574 }
1575
1576 if (!mlxsw_sp_port_dev_check(to_dev)) {
1577 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
Yotam Gigie915ac62017-01-09 11:25:48 +01001578 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001579 }
1580 to_port = netdev_priv(to_dev);
1581
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001582 mirror->to_local_port = to_port->local_port;
1583 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001584 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001585 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1586}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001587
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001588static void
1589mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1590 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1591{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001592 enum mlxsw_sp_span_type span_type;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001593
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001594 span_type = mirror->ingress ?
1595 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Yuval Mintz6399ebc2017-09-12 08:50:53 +02001596 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, mirror->to_local_port,
1597 span_type);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001598}
1599
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001600static int
1601mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1602 struct tc_cls_matchall_offload *cls,
1603 const struct tc_action *a,
1604 bool ingress)
1605{
1606 int err;
1607
1608 if (!mlxsw_sp_port->sample)
1609 return -EOPNOTSUPP;
1610 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1611 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1612 return -EEXIST;
1613 }
1614 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1615 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1616 return -EOPNOTSUPP;
1617 }
1618
1619 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1620 tcf_sample_psample_group(a));
1621 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1622 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1623 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1624
1625 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1626 if (err)
1627 goto err_port_sample_set;
1628 return 0;
1629
1630err_port_sample_set:
1631 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1632 return err;
1633}
1634
1635static void
1636mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1637{
1638 if (!mlxsw_sp_port->sample)
1639 return;
1640
1641 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1642 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1643}
1644
Yotam Gigi763b4b72016-07-21 12:03:17 +02001645static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001646 struct tc_cls_matchall_offload *f,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001647 bool ingress)
1648{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001649 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001650 __be16 protocol = f->common.protocol;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001651 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001652 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001653 int err;
1654
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001655 if (!tcf_exts_has_one_action(f->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001656 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001657 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001658 }
1659
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001660 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1661 if (!mall_tc_entry)
1662 return -ENOMEM;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001663 mall_tc_entry->cookie = f->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001664
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001665 tcf_exts_to_list(f->exts, &actions);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001666 a = list_first_entry(&actions, struct tc_action, list);
1667
1668 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1669 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1670
1671 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1672 mirror = &mall_tc_entry->mirror;
1673 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1674 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001675 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1676 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001677 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001678 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001679 } else {
1680 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001681 }
1682
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001683 if (err)
1684 goto err_add_action;
1685
1686 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001687 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001688
1689err_add_action:
1690 kfree(mall_tc_entry);
1691 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001692}
1693
1694static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001695 struct tc_cls_matchall_offload *f)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001696{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001697 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001698
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001699 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001700 f->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001701 if (!mall_tc_entry) {
1702 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1703 return;
1704 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001705 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001706
1707 switch (mall_tc_entry->type) {
1708 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001709 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1710 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001711 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001712 case MLXSW_SP_PORT_MALL_SAMPLE:
1713 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1714 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001715 default:
1716 WARN_ON(1);
1717 }
1718
Yotam Gigi763b4b72016-07-21 12:03:17 +02001719 kfree(mall_tc_entry);
1720}
1721
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001722static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001723 struct tc_cls_matchall_offload *f,
1724 bool ingress)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001725{
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001726 if (f->common.chain_index)
Jiri Pirkoa5fcf8a2017-06-06 17:00:16 +02001727 return -EOPNOTSUPP;
1728
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001729 switch (f->command) {
1730 case TC_CLSMATCHALL_REPLACE:
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001731 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001732 ingress);
1733 case TC_CLSMATCHALL_DESTROY:
1734 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1735 return 0;
1736 default:
1737 return -EOPNOTSUPP;
1738 }
1739}
1740
1741static int
Jiri Pirko3aaff322018-01-17 11:46:56 +01001742mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1743 struct tc_cls_flower_offload *f)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001744{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001745 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1746
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001747 switch (f->command) {
1748 case TC_CLSFLOWER_REPLACE:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001749 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001750 case TC_CLSFLOWER_DESTROY:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001751 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001752 return 0;
1753 case TC_CLSFLOWER_STATS:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001754 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001755 default:
1756 return -EOPNOTSUPP;
1757 }
1758}
1759
Jiri Pirko3aaff322018-01-17 11:46:56 +01001760static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1761 void *type_data,
1762 void *cb_priv, bool ingress)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001763{
1764 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1765
1766 switch (type) {
1767 case TC_SETUP_CLSMATCHALL:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001768 if (!tc_can_offload(mlxsw_sp_port->dev))
1769 return -EOPNOTSUPP;
1770
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001771 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1772 ingress);
1773 case TC_SETUP_CLSFLOWER:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001774 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001775 default:
1776 return -EOPNOTSUPP;
1777 }
1778}
1779
Jiri Pirko3aaff322018-01-17 11:46:56 +01001780static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1781 void *type_data,
1782 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001783{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001784 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1785 cb_priv, true);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001786}
1787
Jiri Pirko3aaff322018-01-17 11:46:56 +01001788static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1789 void *type_data,
1790 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001791{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001792 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1793 cb_priv, false);
1794}
1795
1796static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1797 void *type_data, void *cb_priv)
1798{
1799 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1800
1801 switch (type) {
1802 case TC_SETUP_CLSMATCHALL:
1803 return 0;
1804 case TC_SETUP_CLSFLOWER:
1805 if (mlxsw_sp_acl_block_disabled(acl_block))
1806 return -EOPNOTSUPP;
1807
1808 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1809 default:
1810 return -EOPNOTSUPP;
1811 }
1812}
1813
1814static int
1815mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1816 struct tcf_block *block, bool ingress)
1817{
1818 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1819 struct mlxsw_sp_acl_block *acl_block;
1820 struct tcf_block_cb *block_cb;
1821 int err;
1822
1823 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1824 mlxsw_sp);
1825 if (!block_cb) {
1826 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1827 if (!acl_block)
1828 return -ENOMEM;
1829 block_cb = __tcf_block_cb_register(block,
1830 mlxsw_sp_setup_tc_block_cb_flower,
1831 mlxsw_sp, acl_block);
1832 if (IS_ERR(block_cb)) {
1833 err = PTR_ERR(block_cb);
1834 goto err_cb_register;
1835 }
1836 } else {
1837 acl_block = tcf_block_cb_priv(block_cb);
1838 }
1839 tcf_block_cb_incref(block_cb);
1840 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1841 mlxsw_sp_port, ingress);
1842 if (err)
1843 goto err_block_bind;
1844
1845 if (ingress)
1846 mlxsw_sp_port->ing_acl_block = acl_block;
1847 else
1848 mlxsw_sp_port->eg_acl_block = acl_block;
1849
1850 return 0;
1851
1852err_block_bind:
1853 if (!tcf_block_cb_decref(block_cb)) {
1854 __tcf_block_cb_unregister(block_cb);
1855err_cb_register:
1856 mlxsw_sp_acl_block_destroy(acl_block);
1857 }
1858 return err;
1859}
1860
1861static void
1862mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1863 struct tcf_block *block, bool ingress)
1864{
1865 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1866 struct mlxsw_sp_acl_block *acl_block;
1867 struct tcf_block_cb *block_cb;
1868 int err;
1869
1870 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1871 mlxsw_sp);
1872 if (!block_cb)
1873 return;
1874
1875 if (ingress)
1876 mlxsw_sp_port->ing_acl_block = NULL;
1877 else
1878 mlxsw_sp_port->eg_acl_block = NULL;
1879
1880 acl_block = tcf_block_cb_priv(block_cb);
1881 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1882 mlxsw_sp_port, ingress);
1883 if (!err && !tcf_block_cb_decref(block_cb)) {
1884 __tcf_block_cb_unregister(block_cb);
1885 mlxsw_sp_acl_block_destroy(acl_block);
1886 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001887}
1888
1889static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1890 struct tc_block_offload *f)
1891{
1892 tc_setup_cb_t *cb;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001893 bool ingress;
1894 int err;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001895
Jiri Pirko3aaff322018-01-17 11:46:56 +01001896 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1897 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1898 ingress = true;
1899 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1900 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1901 ingress = false;
1902 } else {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001903 return -EOPNOTSUPP;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001904 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001905
1906 switch (f->command) {
1907 case TC_BLOCK_BIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001908 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1909 mlxsw_sp_port);
1910 if (err)
1911 return err;
1912 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
1913 f->block, ingress);
1914 if (err) {
1915 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1916 return err;
1917 }
1918 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001919 case TC_BLOCK_UNBIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001920 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1921 f->block, ingress);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001922 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1923 return 0;
1924 default:
1925 return -EOPNOTSUPP;
1926 }
1927}
1928
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001929static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
Jiri Pirkode4784c2017-08-07 10:15:32 +02001930 void *type_data)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001931{
1932 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1933
Jiri Pirko2572ac52017-08-07 10:15:17 +02001934 switch (type) {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001935 case TC_SETUP_BLOCK:
1936 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
Nogah Frankel96f17e02017-11-06 07:23:45 +01001937 case TC_SETUP_QDISC_RED:
1938 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
Nogah Frankel46a36152018-01-14 12:33:16 +01001939 case TC_SETUP_QDISC_PRIO:
1940 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
Jiri Pirko2572ac52017-08-07 10:15:17 +02001941 default:
1942 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001943 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001944}
1945
Jiri Pirko9454d932017-12-06 09:41:12 +01001946
1947static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1948{
1949 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1950
Jiri Pirko3aaff322018-01-17 11:46:56 +01001951 if (!enable) {
1952 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1953 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1954 !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1955 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1956 return -EINVAL;
1957 }
1958 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1959 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1960 } else {
1961 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1962 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
Jiri Pirko9454d932017-12-06 09:41:12 +01001963 }
1964 return 0;
1965}
1966
1967typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1968
1969static int mlxsw_sp_handle_feature(struct net_device *dev,
1970 netdev_features_t wanted_features,
1971 netdev_features_t feature,
1972 mlxsw_sp_feature_handler feature_handler)
1973{
1974 netdev_features_t changes = wanted_features ^ dev->features;
1975 bool enable = !!(wanted_features & feature);
1976 int err;
1977
1978 if (!(changes & feature))
1979 return 0;
1980
1981 err = feature_handler(dev, enable);
1982 if (err) {
1983 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1984 enable ? "Enable" : "Disable", &feature, err);
1985 return err;
1986 }
1987
1988 if (enable)
1989 dev->features |= feature;
1990 else
1991 dev->features &= ~feature;
1992
1993 return 0;
1994}
1995static int mlxsw_sp_set_features(struct net_device *dev,
1996 netdev_features_t features)
1997{
1998 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1999 mlxsw_sp_feature_hw_tc);
2000}
2001
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002002static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
2003 .ndo_open = mlxsw_sp_port_open,
2004 .ndo_stop = mlxsw_sp_port_stop,
2005 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02002006 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01002007 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002008 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
2009 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
2010 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002011 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
2012 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002013 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
2014 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02002015 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko9454d932017-12-06 09:41:12 +01002016 .ndo_set_features = mlxsw_sp_set_features,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002017};
2018
2019static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
2020 struct ethtool_drvinfo *drvinfo)
2021{
2022 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2023 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2024
2025 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
2026 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
2027 sizeof(drvinfo->version));
2028 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
2029 "%d.%d.%d",
2030 mlxsw_sp->bus_info->fw_rev.major,
2031 mlxsw_sp->bus_info->fw_rev.minor,
2032 mlxsw_sp->bus_info->fw_rev.subminor);
2033 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
2034 sizeof(drvinfo->bus_info));
2035}
2036
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002037static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
2038 struct ethtool_pauseparam *pause)
2039{
2040 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2041
2042 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
2043 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
2044}
2045
2046static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
2047 struct ethtool_pauseparam *pause)
2048{
2049 char pfcc_pl[MLXSW_REG_PFCC_LEN];
2050
2051 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
2052 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
2053 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
2054
2055 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
2056 pfcc_pl);
2057}
2058
2059static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
2060 struct ethtool_pauseparam *pause)
2061{
2062 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2063 bool pause_en = pause->tx_pause || pause->rx_pause;
2064 int err;
2065
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02002066 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
2067 netdev_err(dev, "PFC already enabled on port\n");
2068 return -EINVAL;
2069 }
2070
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002071 if (pause->autoneg) {
2072 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
2073 return -EINVAL;
2074 }
2075
2076 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
2077 if (err) {
2078 netdev_err(dev, "Failed to configure port's headroom\n");
2079 return err;
2080 }
2081
2082 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
2083 if (err) {
2084 netdev_err(dev, "Failed to set PAUSE parameters\n");
2085 goto err_port_pause_configure;
2086 }
2087
2088 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
2089 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
2090
2091 return 0;
2092
2093err_port_pause_configure:
2094 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
2095 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
2096 return err;
2097}
2098
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002099struct mlxsw_sp_port_hw_stats {
2100 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02002101 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01002102 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002103};
2104
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002105static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002106 {
2107 .str = "a_frames_transmitted_ok",
2108 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
2109 },
2110 {
2111 .str = "a_frames_received_ok",
2112 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
2113 },
2114 {
2115 .str = "a_frame_check_sequence_errors",
2116 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
2117 },
2118 {
2119 .str = "a_alignment_errors",
2120 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
2121 },
2122 {
2123 .str = "a_octets_transmitted_ok",
2124 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
2125 },
2126 {
2127 .str = "a_octets_received_ok",
2128 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
2129 },
2130 {
2131 .str = "a_multicast_frames_xmitted_ok",
2132 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
2133 },
2134 {
2135 .str = "a_broadcast_frames_xmitted_ok",
2136 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
2137 },
2138 {
2139 .str = "a_multicast_frames_received_ok",
2140 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
2141 },
2142 {
2143 .str = "a_broadcast_frames_received_ok",
2144 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
2145 },
2146 {
2147 .str = "a_in_range_length_errors",
2148 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
2149 },
2150 {
2151 .str = "a_out_of_range_length_field",
2152 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
2153 },
2154 {
2155 .str = "a_frame_too_long_errors",
2156 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
2157 },
2158 {
2159 .str = "a_symbol_error_during_carrier",
2160 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
2161 },
2162 {
2163 .str = "a_mac_control_frames_transmitted",
2164 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
2165 },
2166 {
2167 .str = "a_mac_control_frames_received",
2168 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
2169 },
2170 {
2171 .str = "a_unsupported_opcodes_received",
2172 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
2173 },
2174 {
2175 .str = "a_pause_mac_ctrl_frames_received",
2176 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
2177 },
2178 {
2179 .str = "a_pause_mac_ctrl_frames_xmitted",
2180 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
2181 },
2182};
2183
2184#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
2185
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002186static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
2187 {
2188 .str = "rx_octets_prio",
2189 .getter = mlxsw_reg_ppcnt_rx_octets_get,
2190 },
2191 {
2192 .str = "rx_frames_prio",
2193 .getter = mlxsw_reg_ppcnt_rx_frames_get,
2194 },
2195 {
2196 .str = "tx_octets_prio",
2197 .getter = mlxsw_reg_ppcnt_tx_octets_get,
2198 },
2199 {
2200 .str = "tx_frames_prio",
2201 .getter = mlxsw_reg_ppcnt_tx_frames_get,
2202 },
2203 {
2204 .str = "rx_pause_prio",
2205 .getter = mlxsw_reg_ppcnt_rx_pause_get,
2206 },
2207 {
2208 .str = "rx_pause_duration_prio",
2209 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2210 },
2211 {
2212 .str = "tx_pause_prio",
2213 .getter = mlxsw_reg_ppcnt_tx_pause_get,
2214 },
2215 {
2216 .str = "tx_pause_duration_prio",
2217 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2218 },
2219};
2220
2221#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2222
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002223static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2224 {
2225 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01002226 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2227 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002228 },
2229 {
2230 .str = "tc_no_buffer_discard_uc_tc",
2231 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2232 },
2233};
2234
2235#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2236
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002237#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002238 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
2239 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002240 IEEE_8021QAZ_MAX_TCS)
2241
2242static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2243{
2244 int i;
2245
2246 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2247 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2248 mlxsw_sp_port_hw_prio_stats[i].str, prio);
2249 *p += ETH_GSTRING_LEN;
2250 }
2251}
2252
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002253static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2254{
2255 int i;
2256
2257 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2258 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2259 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2260 *p += ETH_GSTRING_LEN;
2261 }
2262}
2263
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002264static void mlxsw_sp_port_get_strings(struct net_device *dev,
2265 u32 stringset, u8 *data)
2266{
2267 u8 *p = data;
2268 int i;
2269
2270 switch (stringset) {
2271 case ETH_SS_STATS:
2272 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2273 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2274 ETH_GSTRING_LEN);
2275 p += ETH_GSTRING_LEN;
2276 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002277
2278 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2279 mlxsw_sp_port_get_prio_strings(&p, i);
2280
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002281 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2282 mlxsw_sp_port_get_tc_strings(&p, i);
2283
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002284 break;
2285 }
2286}
2287
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002288static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2289 enum ethtool_phys_id_state state)
2290{
2291 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2292 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2293 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2294 bool active;
2295
2296 switch (state) {
2297 case ETHTOOL_ID_ACTIVE:
2298 active = true;
2299 break;
2300 case ETHTOOL_ID_INACTIVE:
2301 active = false;
2302 break;
2303 default:
2304 return -EOPNOTSUPP;
2305 }
2306
2307 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2308 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2309}
2310
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002311static int
2312mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2313 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2314{
2315 switch (grp) {
2316 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2317 *p_hw_stats = mlxsw_sp_port_hw_stats;
2318 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2319 break;
2320 case MLXSW_REG_PPCNT_PRIO_CNT:
2321 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2322 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2323 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002324 case MLXSW_REG_PPCNT_TC_CNT:
2325 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2326 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2327 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002328 default:
2329 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002330 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002331 }
2332 return 0;
2333}
2334
2335static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2336 enum mlxsw_reg_ppcnt_grp grp, int prio,
2337 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002338{
Ido Schimmel18281f22017-03-24 08:02:51 +01002339 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2340 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002341 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002342 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002343 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002344 int err;
2345
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002346 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2347 if (err)
2348 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002349 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002350 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002351 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002352 if (!hw_stats[i].cells_bytes)
2353 continue;
2354 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2355 data[data_index + i]);
2356 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002357}
2358
2359static void mlxsw_sp_port_get_stats(struct net_device *dev,
2360 struct ethtool_stats *stats, u64 *data)
2361{
2362 int i, data_index = 0;
2363
2364 /* IEEE 802.3 Counters */
2365 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2366 data, data_index);
2367 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2368
2369 /* Per-Priority Counters */
2370 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2371 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2372 data, data_index);
2373 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2374 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002375
2376 /* Per-TC Counters */
2377 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2378 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2379 data, data_index);
2380 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2381 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002382}
2383
2384static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2385{
2386 switch (sset) {
2387 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002388 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002389 default:
2390 return -EOPNOTSUPP;
2391 }
2392}
2393
2394struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002395 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002396 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002397 u32 speed;
2398};
2399
2400static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2401 {
2402 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002403 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2404 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002405 },
2406 {
2407 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2408 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002409 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2410 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002411 },
2412 {
2413 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002414 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2415 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002416 },
2417 {
2418 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2419 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002420 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2421 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002422 },
2423 {
2424 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2425 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2426 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2427 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002428 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2429 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002430 },
2431 {
2432 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002433 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2434 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002435 },
2436 {
2437 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002438 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2439 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002440 },
2441 {
2442 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002443 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2444 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002445 },
2446 {
2447 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002448 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2449 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002450 },
2451 {
2452 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002453 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2454 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002455 },
2456 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002457 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2458 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2459 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002460 },
2461 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002462 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2463 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2464 .speed = SPEED_25000,
2465 },
2466 {
2467 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2468 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2469 .speed = SPEED_25000,
2470 },
2471 {
2472 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2473 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2474 .speed = SPEED_25000,
2475 },
2476 {
2477 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2478 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2479 .speed = SPEED_50000,
2480 },
2481 {
2482 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2483 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2484 .speed = SPEED_50000,
2485 },
2486 {
2487 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2488 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2489 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002490 },
2491 {
2492 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002493 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2494 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002495 },
2496 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002497 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2498 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2499 .speed = SPEED_56000,
2500 },
2501 {
2502 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2503 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2504 .speed = SPEED_56000,
2505 },
2506 {
2507 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2508 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2509 .speed = SPEED_56000,
2510 },
2511 {
2512 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2513 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2514 .speed = SPEED_100000,
2515 },
2516 {
2517 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2518 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2519 .speed = SPEED_100000,
2520 },
2521 {
2522 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2523 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2524 .speed = SPEED_100000,
2525 },
2526 {
2527 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2528 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2529 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002530 },
2531};
2532
2533#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2534
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002535static void
2536mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2537 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002538{
2539 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2540 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2541 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2542 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2543 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2544 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002545 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002546
2547 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2548 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2549 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2550 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2551 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002552 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002553}
2554
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002555static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002556{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002557 int i;
2558
2559 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2560 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002561 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2562 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002563 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002564}
2565
2566static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002567 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002568{
2569 u32 speed = SPEED_UNKNOWN;
2570 u8 duplex = DUPLEX_UNKNOWN;
2571 int i;
2572
2573 if (!carrier_ok)
2574 goto out;
2575
2576 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2577 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2578 speed = mlxsw_sp_port_link_mode[i].speed;
2579 duplex = DUPLEX_FULL;
2580 break;
2581 }
2582 }
2583out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002584 cmd->base.speed = speed;
2585 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002586}
2587
2588static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2589{
2590 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2591 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2592 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2593 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2594 return PORT_FIBRE;
2595
2596 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2597 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2598 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2599 return PORT_DA;
2600
2601 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2602 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2603 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2604 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2605 return PORT_NONE;
2606
2607 return PORT_OTHER;
2608}
2609
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002610static u32
2611mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002612{
2613 u32 ptys_proto = 0;
2614 int i;
2615
2616 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002617 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2618 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002619 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2620 }
2621 return ptys_proto;
2622}
2623
2624static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2625{
2626 u32 ptys_proto = 0;
2627 int i;
2628
2629 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2630 if (speed == mlxsw_sp_port_link_mode[i].speed)
2631 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2632 }
2633 return ptys_proto;
2634}
2635
Ido Schimmel18f1e702016-02-26 17:32:31 +01002636static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2637{
2638 u32 ptys_proto = 0;
2639 int i;
2640
2641 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2642 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2643 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2644 }
2645 return ptys_proto;
2646}
2647
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002648static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2649 struct ethtool_link_ksettings *cmd)
2650{
2651 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2652 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2653 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2654
2655 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2656 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2657}
2658
2659static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2660 struct ethtool_link_ksettings *cmd)
2661{
2662 if (!autoneg)
2663 return;
2664
2665 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2666 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2667}
2668
2669static void
2670mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2671 struct ethtool_link_ksettings *cmd)
2672{
2673 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2674 return;
2675
2676 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2677 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2678}
2679
2680static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2681 struct ethtool_link_ksettings *cmd)
2682{
2683 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2684 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2685 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2686 char ptys_pl[MLXSW_REG_PTYS_LEN];
2687 u8 autoneg_status;
2688 bool autoneg;
2689 int err;
2690
2691 autoneg = mlxsw_sp_port->link.autoneg;
Elad Raz401c8b42016-10-28 21:35:52 +02002692 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002693 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2694 if (err)
2695 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002696 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2697 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002698
2699 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2700
2701 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2702
2703 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2704 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2705 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2706
2707 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2708 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2709 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2710 cmd);
2711
2712 return 0;
2713}
2714
2715static int
2716mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2717 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002718{
2719 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2720 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2721 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002722 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002723 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002724 int err;
2725
Elad Raz401c8b42016-10-28 21:35:52 +02002726 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002727 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002728 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002729 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002730 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002731
2732 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2733 eth_proto_new = autoneg ?
2734 mlxsw_sp_to_ptys_advert_link(cmd) :
2735 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002736
2737 eth_proto_new = eth_proto_new & eth_proto_cap;
2738 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002739 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002740 return -EINVAL;
2741 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002742
Elad Raz401c8b42016-10-28 21:35:52 +02002743 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2744 eth_proto_new);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002745 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002746 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002747 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002748
Ido Schimmel6277d462016-07-15 11:14:58 +02002749 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002750 return 0;
2751
Ido Schimmel0c83f882016-09-12 13:26:23 +02002752 mlxsw_sp_port->link.autoneg = autoneg;
2753
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002754 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2755 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002756
2757 return 0;
2758}
2759
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002760static int mlxsw_sp_flash_device(struct net_device *dev,
2761 struct ethtool_flash *flash)
2762{
2763 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2764 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2765 const struct firmware *firmware;
2766 int err;
2767
2768 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2769 return -EOPNOTSUPP;
2770
2771 dev_hold(dev);
2772 rtnl_unlock();
2773
2774 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2775 if (err)
2776 goto out;
2777 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2778 release_firmware(firmware);
2779out:
2780 rtnl_lock();
2781 dev_put(dev);
2782 return err;
2783}
2784
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002785#define MLXSW_SP_I2C_ADDR_LOW 0x50
2786#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2787#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002788
2789static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2790 u16 offset, u16 size, void *data,
2791 unsigned int *p_read_size)
2792{
2793 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2794 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2795 char mcia_pl[MLXSW_REG_MCIA_LEN];
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002796 u16 i2c_addr;
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002797 int status;
2798 int err;
2799
2800 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002801
2802 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2803 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2804 /* Cross pages read, read until offset 256 in low page */
2805 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2806
2807 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2808 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2809 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2810 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2811 }
2812
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002813 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002814 0, 0, offset, size, i2c_addr);
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002815
2816 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2817 if (err)
2818 return err;
2819
2820 status = mlxsw_reg_mcia_status_get(mcia_pl);
2821 if (status)
2822 return -EIO;
2823
2824 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2825 memcpy(data, eeprom_tmp, size);
2826 *p_read_size = size;
2827
2828 return 0;
2829}
2830
2831enum mlxsw_sp_eeprom_module_info_rev_id {
2832 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2833 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2834 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2835};
2836
2837enum mlxsw_sp_eeprom_module_info_id {
2838 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2839 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2840 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2841 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2842};
2843
2844enum mlxsw_sp_eeprom_module_info {
2845 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2846 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2847 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2848};
2849
2850static int mlxsw_sp_get_module_info(struct net_device *netdev,
2851 struct ethtool_modinfo *modinfo)
2852{
2853 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2854 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2855 u8 module_rev_id, module_id;
2856 unsigned int read_size;
2857 int err;
2858
2859 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2860 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2861 module_info, &read_size);
2862 if (err)
2863 return err;
2864
2865 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2866 return -EIO;
2867
2868 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2869 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2870
2871 switch (module_id) {
2872 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2873 modinfo->type = ETH_MODULE_SFF_8436;
2874 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2875 break;
2876 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2877 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2878 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2879 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2880 modinfo->type = ETH_MODULE_SFF_8636;
2881 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2882 } else {
2883 modinfo->type = ETH_MODULE_SFF_8436;
2884 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2885 }
2886 break;
2887 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2888 modinfo->type = ETH_MODULE_SFF_8472;
2889 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2890 break;
2891 default:
2892 return -EINVAL;
2893 }
2894
2895 return 0;
2896}
2897
2898static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2899 struct ethtool_eeprom *ee,
2900 u8 *data)
2901{
2902 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2903 int offset = ee->offset;
2904 unsigned int read_size;
2905 int i = 0;
2906 int err;
2907
2908 if (!ee->len)
2909 return -EINVAL;
2910
2911 memset(data, 0, ee->len);
2912
2913 while (i < ee->len) {
2914 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2915 ee->len - i, data + i,
2916 &read_size);
2917 if (err) {
2918 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2919 return err;
2920 }
2921
2922 i += read_size;
2923 offset += read_size;
2924 }
2925
2926 return 0;
2927}
2928
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002929static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2930 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2931 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002932 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2933 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002934 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002935 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002936 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2937 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002938 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2939 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002940 .flash_device = mlxsw_sp_flash_device,
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002941 .get_module_info = mlxsw_sp_get_module_info,
2942 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002943};
2944
Ido Schimmel18f1e702016-02-26 17:32:31 +01002945static int
2946mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2947{
2948 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2949 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2950 char ptys_pl[MLXSW_REG_PTYS_LEN];
2951 u32 eth_proto_admin;
2952
2953 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002954 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2955 eth_proto_admin);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002956 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2957}
2958
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002959int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2960 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2961 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002962{
2963 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2964 char qeec_pl[MLXSW_REG_QEEC_LEN];
2965
2966 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2967 next_index);
2968 mlxsw_reg_qeec_de_set(qeec_pl, true);
2969 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2970 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2971 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2972}
2973
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002974int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2975 enum mlxsw_reg_qeec_hr hr, u8 index,
2976 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002977{
2978 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2979 char qeec_pl[MLXSW_REG_QEEC_LEN];
2980
2981 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2982 next_index);
2983 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2984 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2985 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2986}
2987
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002988int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2989 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002990{
2991 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2992 char qtct_pl[MLXSW_REG_QTCT_LEN];
2993
2994 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2995 tclass);
2996 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2997}
2998
2999static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
3000{
3001 int err, i;
3002
3003 /* Setup the elements hierarcy, so that each TC is linked to
3004 * one subgroup, which are all member in the same group.
3005 */
3006 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3007 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
3008 0);
3009 if (err)
3010 return err;
3011 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3012 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3013 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
3014 0, false, 0);
3015 if (err)
3016 return err;
3017 }
3018 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3019 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3020 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
3021 false, 0);
3022 if (err)
3023 return err;
3024 }
3025
3026 /* Make sure the max shaper is disabled in all hierarcies that
3027 * support it.
3028 */
3029 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3030 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
3031 MLXSW_REG_QEEC_MAS_DIS);
3032 if (err)
3033 return err;
3034 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3035 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3036 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3037 i, 0,
3038 MLXSW_REG_QEEC_MAS_DIS);
3039 if (err)
3040 return err;
3041 }
3042 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3043 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3044 MLXSW_REG_QEEC_HIERARCY_TC,
3045 i, i,
3046 MLXSW_REG_QEEC_MAS_DIS);
3047 if (err)
3048 return err;
3049 }
3050
3051 /* Map all priorities to traffic class 0. */
3052 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3053 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
3054 if (err)
3055 return err;
3056 }
3057
3058 return 0;
3059}
3060
Ido Schimmel5b153852017-06-08 08:47:44 +02003061static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
3062 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003063{
Ido Schimmelc57529e2017-05-26 08:37:31 +02003064 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003065 struct mlxsw_sp_port *mlxsw_sp_port;
3066 struct net_device *dev;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003067 int err;
3068
Ido Schimmel5b153852017-06-08 08:47:44 +02003069 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
3070 if (err) {
3071 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
3072 local_port);
3073 return err;
3074 }
3075
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003076 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
Ido Schimmel5b153852017-06-08 08:47:44 +02003077 if (!dev) {
3078 err = -ENOMEM;
3079 goto err_alloc_etherdev;
3080 }
Jiri Pirkof20a91f2016-10-27 15:13:00 +02003081 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003082 mlxsw_sp_port = netdev_priv(dev);
3083 mlxsw_sp_port->dev = dev;
3084 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
3085 mlxsw_sp_port->local_port = local_port;
Ido Schimmelc57529e2017-05-26 08:37:31 +02003086 mlxsw_sp_port->pvid = 1;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003087 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02003088 mlxsw_sp_port->mapping.module = module;
3089 mlxsw_sp_port->mapping.width = width;
3090 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02003091 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02003092 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02003093 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003094
3095 mlxsw_sp_port->pcpu_stats =
3096 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
3097 if (!mlxsw_sp_port->pcpu_stats) {
3098 err = -ENOMEM;
3099 goto err_alloc_stats;
3100 }
3101
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003102 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
3103 GFP_KERNEL);
3104 if (!mlxsw_sp_port->sample) {
3105 err = -ENOMEM;
3106 goto err_alloc_sample;
3107 }
3108
Nogah Frankel9deef432017-10-26 10:55:32 +02003109 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02003110 &update_stats_cache);
3111
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003112 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
3113 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
3114
Ido Schimmel2e915e02017-06-08 08:47:45 +02003115 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
Ido Schimmel5b153852017-06-08 08:47:44 +02003116 if (err) {
3117 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
3118 mlxsw_sp_port->local_port);
3119 goto err_port_module_map;
3120 }
3121
Ido Schimmel3247ff22016-09-08 08:16:02 +02003122 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
3123 if (err) {
3124 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
3125 mlxsw_sp_port->local_port);
3126 goto err_port_swid_set;
3127 }
3128
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003129 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
3130 if (err) {
3131 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
3132 mlxsw_sp_port->local_port);
3133 goto err_dev_addr_init;
3134 }
3135
3136 netif_carrier_off(dev);
3137
3138 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02003139 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
3140 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003141
Jarod Wilsond894be52016-10-20 13:55:16 -04003142 dev->min_mtu = 0;
3143 dev->max_mtu = ETH_MAX_MTU;
3144
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003145 /* Each packet needs to have a Tx header (metadata) on top all other
3146 * headers.
3147 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02003148 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003149
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003150 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
3151 if (err) {
3152 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
3153 mlxsw_sp_port->local_port);
3154 goto err_port_system_port_mapping_set;
3155 }
3156
Ido Schimmel18f1e702016-02-26 17:32:31 +01003157 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
3158 if (err) {
3159 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
3160 mlxsw_sp_port->local_port);
3161 goto err_port_speed_by_width_set;
3162 }
3163
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003164 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
3165 if (err) {
3166 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
3167 mlxsw_sp_port->local_port);
3168 goto err_port_mtu_set;
3169 }
3170
3171 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3172 if (err)
3173 goto err_port_admin_status_set;
3174
3175 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
3176 if (err) {
3177 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
3178 mlxsw_sp_port->local_port);
3179 goto err_port_buffers_init;
3180 }
3181
Ido Schimmel90183b92016-04-06 17:10:08 +02003182 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
3183 if (err) {
3184 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
3185 mlxsw_sp_port->local_port);
3186 goto err_port_ets_init;
3187 }
3188
Ido Schimmelf00817d2016-04-06 17:10:09 +02003189 /* ETS and buffers must be initialized before DCB. */
3190 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
3191 if (err) {
3192 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
3193 mlxsw_sp_port->local_port);
3194 goto err_port_dcb_init;
3195 }
3196
Ido Schimmela1107482017-05-26 08:37:39 +02003197 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
Ido Schimmel45a4a162017-05-16 19:38:35 +02003198 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003199 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
Ido Schimmel45a4a162017-05-16 19:38:35 +02003200 mlxsw_sp_port->local_port);
Ido Schimmela1107482017-05-26 08:37:39 +02003201 goto err_port_fids_init;
Ido Schimmel45a4a162017-05-16 19:38:35 +02003202 }
3203
Nogah Frankel371b4372018-01-10 14:59:57 +01003204 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
3205 if (err) {
3206 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
3207 mlxsw_sp_port->local_port);
3208 goto err_port_qdiscs_init;
3209 }
3210
Ido Schimmelc57529e2017-05-26 08:37:31 +02003211 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
3212 if (IS_ERR(mlxsw_sp_port_vlan)) {
3213 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
Ido Schimmel05978482016-08-17 16:39:30 +02003214 mlxsw_sp_port->local_port);
Wei Yongjund86fd112017-11-06 11:11:28 +00003215 err = PTR_ERR(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003216 goto err_port_vlan_get;
Ido Schimmel05978482016-08-17 16:39:30 +02003217 }
3218
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003219 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02003220 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003221 err = register_netdev(dev);
3222 if (err) {
3223 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3224 mlxsw_sp_port->local_port);
3225 goto err_register_netdev;
3226 }
3227
Elad Razd808c7e2016-10-28 21:35:57 +02003228 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3229 mlxsw_sp_port, dev, mlxsw_sp_port->split,
3230 module);
Nogah Frankel9deef432017-10-26 10:55:32 +02003231 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003232 return 0;
3233
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003234err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02003235 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02003236 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003237 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
3238err_port_vlan_get:
Nogah Frankel371b4372018-01-10 14:59:57 +01003239 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3240err_port_qdiscs_init:
Ido Schimmela1107482017-05-26 08:37:39 +02003241 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3242err_port_fids_init:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03003243 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02003244err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02003245err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003246err_port_buffers_init:
3247err_port_admin_status_set:
3248err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01003249err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003250err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003251err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02003252 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3253err_port_swid_set:
Ido Schimmel2e915e02017-06-08 08:47:45 +02003254 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Ido Schimmel5b153852017-06-08 08:47:44 +02003255err_port_module_map:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003256 kfree(mlxsw_sp_port->sample);
3257err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003258 free_percpu(mlxsw_sp_port->pcpu_stats);
3259err_alloc_stats:
3260 free_netdev(dev);
Ido Schimmel5b153852017-06-08 08:47:44 +02003261err_alloc_etherdev:
Jiri Pirko67963a32016-10-28 21:35:55 +02003262 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3263 return err;
3264}
3265
Ido Schimmel5b153852017-06-08 08:47:44 +02003266static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003267{
3268 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3269
Nogah Frankel9deef432017-10-26 10:55:32 +02003270 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02003271 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003272 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02003273 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02003274 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003275 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Nogah Frankel371b4372018-01-10 14:59:57 +01003276 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
Ido Schimmela1107482017-05-26 08:37:39 +02003277 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02003278 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01003279 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
Ido Schimmel2e915e02017-06-08 08:47:45 +02003280 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003281 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01003282 free_percpu(mlxsw_sp_port->pcpu_stats);
Ido Schimmel31a08a52017-05-26 08:37:26 +02003283 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003284 free_netdev(mlxsw_sp_port->dev);
Jiri Pirko67963a32016-10-28 21:35:55 +02003285 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3286}
3287
Jiri Pirkof83e2102016-10-28 21:35:49 +02003288static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3289{
3290 return mlxsw_sp->ports[local_port] != NULL;
3291}
3292
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003293static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3294{
3295 int i;
3296
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003297 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003298 if (mlxsw_sp_port_created(mlxsw_sp, i))
3299 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003300 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003301 kfree(mlxsw_sp->ports);
3302}
3303
3304static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3305{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003306 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02003307 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003308 size_t alloc_size;
3309 int i;
3310 int err;
3311
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003312 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003313 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3314 if (!mlxsw_sp->ports)
3315 return -ENOMEM;
3316
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003317 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3318 GFP_KERNEL);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003319 if (!mlxsw_sp->port_to_module) {
3320 err = -ENOMEM;
3321 goto err_port_to_module_alloc;
3322 }
3323
3324 for (i = 1; i < max_ports; i++) {
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003325 /* Mark as invalid */
3326 mlxsw_sp->port_to_module[i] = -1;
3327
Ido Schimmel558c2d52016-02-26 17:32:29 +01003328 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003329 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01003330 if (err)
3331 goto err_port_module_info_get;
3332 if (!width)
3333 continue;
3334 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02003335 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3336 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003337 if (err)
3338 goto err_port_create;
3339 }
3340 return 0;
3341
3342err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01003343err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003344 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003345 if (mlxsw_sp_port_created(mlxsw_sp, i))
3346 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003347 kfree(mlxsw_sp->port_to_module);
3348err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003349 kfree(mlxsw_sp->ports);
3350 return err;
3351}
3352
Ido Schimmel18f1e702016-02-26 17:32:31 +01003353static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3354{
3355 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3356
3357 return local_port - offset;
3358}
3359
Ido Schimmelbe945352016-06-09 09:51:39 +02003360static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3361 u8 module, unsigned int count)
3362{
3363 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3364 int err, i;
3365
3366 for (i = 0; i < count; i++) {
Ido Schimmelbe945352016-06-09 09:51:39 +02003367 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02003368 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02003369 if (err)
3370 goto err_port_create;
3371 }
3372
3373 return 0;
3374
3375err_port_create:
3376 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003377 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3378 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02003379 return err;
3380}
3381
3382static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3383 u8 base_port, unsigned int count)
3384{
3385 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3386 int i;
3387
3388 /* Split by four means we need to re-create two ports, otherwise
3389 * only one.
3390 */
3391 count = count / 2;
3392
3393 for (i = 0; i < count; i++) {
3394 local_port = base_port + i * 2;
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003395 if (mlxsw_sp->port_to_module[local_port] < 0)
3396 continue;
Ido Schimmelbe945352016-06-09 09:51:39 +02003397 module = mlxsw_sp->port_to_module[local_port];
3398
Ido Schimmelbe945352016-06-09 09:51:39 +02003399 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003400 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003401 }
3402}
3403
Jiri Pirkob2f10572016-04-08 19:11:23 +02003404static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3405 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003406{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003407 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003408 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003409 u8 module, cur_width, base_port;
3410 int i;
3411 int err;
3412
3413 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3414 if (!mlxsw_sp_port) {
3415 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3416 local_port);
3417 return -EINVAL;
3418 }
3419
Ido Schimmeld664b412016-06-09 09:51:40 +02003420 module = mlxsw_sp_port->mapping.module;
3421 cur_width = mlxsw_sp_port->mapping.width;
3422
Ido Schimmel18f1e702016-02-26 17:32:31 +01003423 if (count != 2 && count != 4) {
3424 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3425 return -EINVAL;
3426 }
3427
Ido Schimmel18f1e702016-02-26 17:32:31 +01003428 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3429 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3430 return -EINVAL;
3431 }
3432
3433 /* Make sure we have enough slave (even) ports for the split. */
3434 if (count == 2) {
3435 base_port = local_port;
3436 if (mlxsw_sp->ports[base_port + 1]) {
3437 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3438 return -EINVAL;
3439 }
3440 } else {
3441 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3442 if (mlxsw_sp->ports[base_port + 1] ||
3443 mlxsw_sp->ports[base_port + 3]) {
3444 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3445 return -EINVAL;
3446 }
3447 }
3448
3449 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003450 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3451 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003452
Ido Schimmelbe945352016-06-09 09:51:39 +02003453 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3454 if (err) {
3455 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3456 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003457 }
3458
3459 return 0;
3460
Ido Schimmelbe945352016-06-09 09:51:39 +02003461err_port_split_create:
3462 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003463 return err;
3464}
3465
Jiri Pirkob2f10572016-04-08 19:11:23 +02003466static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003467{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003468 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003469 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003470 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003471 unsigned int count;
3472 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003473
3474 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3475 if (!mlxsw_sp_port) {
3476 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3477 local_port);
3478 return -EINVAL;
3479 }
3480
3481 if (!mlxsw_sp_port->split) {
3482 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3483 return -EINVAL;
3484 }
3485
Ido Schimmeld664b412016-06-09 09:51:40 +02003486 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003487 count = cur_width == 1 ? 4 : 2;
3488
3489 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3490
3491 /* Determine which ports to remove. */
3492 if (count == 2 && local_port >= base_port + 2)
3493 base_port = base_port + 2;
3494
3495 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003496 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3497 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003498
Ido Schimmelbe945352016-06-09 09:51:39 +02003499 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003500
3501 return 0;
3502}
3503
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003504static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3505 char *pude_pl, void *priv)
3506{
3507 struct mlxsw_sp *mlxsw_sp = priv;
3508 struct mlxsw_sp_port *mlxsw_sp_port;
3509 enum mlxsw_reg_pude_oper_status status;
3510 u8 local_port;
3511
3512 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3513 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003514 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003515 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003516
3517 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3518 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3519 netdev_info(mlxsw_sp_port->dev, "link up\n");
3520 netif_carrier_on(mlxsw_sp_port->dev);
3521 } else {
3522 netdev_info(mlxsw_sp_port->dev, "link down\n");
3523 netif_carrier_off(mlxsw_sp_port->dev);
3524 }
3525}
3526
Nogah Frankel14eeda92016-11-25 10:33:32 +01003527static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3528 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003529{
3530 struct mlxsw_sp *mlxsw_sp = priv;
3531 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3532 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3533
3534 if (unlikely(!mlxsw_sp_port)) {
3535 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3536 local_port);
3537 return;
3538 }
3539
3540 skb->dev = mlxsw_sp_port->dev;
3541
3542 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3543 u64_stats_update_begin(&pcpu_stats->syncp);
3544 pcpu_stats->rx_packets++;
3545 pcpu_stats->rx_bytes += skb->len;
3546 u64_stats_update_end(&pcpu_stats->syncp);
3547
3548 skb->protocol = eth_type_trans(skb, skb->dev);
3549 netif_receive_skb(skb);
3550}
3551
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003552static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3553 void *priv)
3554{
3555 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003556 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003557}
3558
Yotam Gigia0040c82017-10-03 09:58:10 +02003559static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3560 u8 local_port, void *priv)
3561{
3562 skb->offload_mr_fwd_mark = 1;
3563 skb->offload_fwd_mark = 1;
3564 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3565}
3566
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003567static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3568 void *priv)
3569{
3570 struct mlxsw_sp *mlxsw_sp = priv;
3571 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3572 struct psample_group *psample_group;
3573 u32 size;
3574
3575 if (unlikely(!mlxsw_sp_port)) {
3576 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3577 local_port);
3578 goto out;
3579 }
3580 if (unlikely(!mlxsw_sp_port->sample)) {
3581 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3582 local_port);
3583 goto out;
3584 }
3585
3586 size = mlxsw_sp_port->sample->truncate ?
3587 mlxsw_sp_port->sample->trunc_size : skb->len;
3588
3589 rcu_read_lock();
3590 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3591 if (!psample_group)
3592 goto out_unlock;
3593 psample_sample_packet(psample_group, skb, size,
3594 mlxsw_sp_port->dev->ifindex, 0,
3595 mlxsw_sp_port->sample->rate);
3596out_unlock:
3597 rcu_read_unlock();
3598out:
3599 consume_skb(skb);
3600}
3601
Nogah Frankel117b0da2016-11-25 10:33:44 +01003602#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003603 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003604 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003605
Nogah Frankel117b0da2016-11-25 10:33:44 +01003606#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003607 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003608 _is_ctrl, SP_##_trap_group, DISCARD)
3609
Yotam Gigia0040c82017-10-03 09:58:10 +02003610#define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3611 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3612 _is_ctrl, SP_##_trap_group, DISCARD)
3613
Nogah Frankel117b0da2016-11-25 10:33:44 +01003614#define MLXSW_SP_EVENTL(_func, _trap_id) \
3615 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003616
Nogah Frankel45449132016-11-25 10:33:35 +01003617static const struct mlxsw_listener mlxsw_sp_listener[] = {
3618 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003619 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003620 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003621 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3622 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3623 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3624 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3625 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3626 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3627 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3628 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3629 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3630 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3631 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003632 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003633 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3634 false),
3635 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3636 false),
3637 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3638 false),
3639 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3640 false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003641 /* L3 traps */
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003642 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3643 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3644 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003645 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003646 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3647 false),
3648 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3649 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3650 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3651 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3652 false),
3653 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3654 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3655 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003656 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003657 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3658 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3659 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3660 false),
3661 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3662 false),
3663 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3664 false),
3665 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3666 false),
3667 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3668 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3669 false),
3670 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3671 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
Ido Schimmel7607dd32017-07-17 14:15:30 +02003672 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003673 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
Petr Machata86484de2017-09-02 23:49:27 +02003674 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003675 /* PKT Sample trap */
3676 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
Jiri Pirko0db7b382017-06-06 14:12:05 +02003677 false, SP_IP2ME, DISCARD),
3678 /* ACL trap */
3679 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
Yotam Gigib48cfc82017-09-19 10:00:20 +02003680 /* Multicast Router Traps */
3681 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3682 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3683 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
Yotam Gigia0040c82017-10-03 09:58:10 +02003684 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003685};
3686
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003687static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3688{
3689 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3690 enum mlxsw_reg_qpcr_ir_units ir_units;
3691 int max_cpu_policers;
3692 bool is_bytes;
3693 u8 burst_size;
3694 u32 rate;
3695 int i, err;
3696
3697 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3698 return -EIO;
3699
3700 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3701
3702 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3703 for (i = 0; i < max_cpu_policers; i++) {
3704 is_bytes = false;
3705 switch (i) {
3706 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3707 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3708 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3709 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003710 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3711 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003712 rate = 128;
3713 burst_size = 7;
3714 break;
3715 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003716 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003717 rate = 16 * 1024;
3718 burst_size = 10;
3719 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003720 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003721 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3722 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003723 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003724 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3725 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003726 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003727 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003728 rate = 1024;
3729 burst_size = 7;
3730 break;
3731 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3732 is_bytes = true;
3733 rate = 4 * 1024;
3734 burst_size = 4;
3735 break;
3736 default:
3737 continue;
3738 }
3739
3740 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3741 burst_size);
3742 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3743 if (err)
3744 return err;
3745 }
3746
3747 return 0;
3748}
3749
Nogah Frankel579c82e2016-11-25 10:33:42 +01003750static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003751{
3752 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003753 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003754 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003755 int max_trap_groups;
3756 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003757 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003758 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003759
3760 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3761 return -EIO;
3762
3763 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003764 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003765
3766 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003767 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003768 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003769 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3770 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3771 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3772 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003773 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003774 priority = 5;
3775 tc = 5;
3776 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003777 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003778 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3779 priority = 4;
3780 tc = 4;
3781 break;
3782 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3783 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003784 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003785 priority = 3;
3786 tc = 3;
3787 break;
3788 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003789 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003790 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003791 priority = 2;
3792 tc = 2;
3793 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003794 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003795 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3796 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003797 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003798 priority = 1;
3799 tc = 1;
3800 break;
3801 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003802 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3803 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003804 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003805 break;
3806 default:
3807 continue;
3808 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003809
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003810 if (max_cpu_policers <= policer_id &&
3811 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3812 return -EIO;
3813
3814 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003815 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3816 if (err)
3817 return err;
3818 }
3819
3820 return 0;
3821}
3822
3823static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3824{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003825 int i;
3826 int err;
3827
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003828 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3829 if (err)
3830 return err;
3831
Nogah Frankel579c82e2016-11-25 10:33:42 +01003832 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003833 if (err)
3834 return err;
3835
Nogah Frankel45449132016-11-25 10:33:35 +01003836 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003837 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003838 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003839 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003840 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003841 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003842
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003843 }
3844 return 0;
3845
Nogah Frankel45449132016-11-25 10:33:35 +01003846err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003847 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003848 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003849 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003850 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003851 }
3852 return err;
3853}
3854
3855static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3856{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003857 int i;
3858
Nogah Frankel45449132016-11-25 10:33:35 +01003859 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003860 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003861 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003862 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003863 }
3864}
3865
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003866static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3867{
3868 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003869 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003870
3871 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3872 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3873 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3874 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3875 MLXSW_REG_SLCR_LAG_HASH_SIP |
3876 MLXSW_REG_SLCR_LAG_HASH_DIP |
3877 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3878 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3879 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003880 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3881 if (err)
3882 return err;
3883
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003884 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3885 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003886 return -EIO;
3887
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003888 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003889 sizeof(struct mlxsw_sp_upper),
3890 GFP_KERNEL);
3891 if (!mlxsw_sp->lags)
3892 return -ENOMEM;
3893
3894 return 0;
3895}
3896
3897static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3898{
3899 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003900}
3901
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003902static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3903{
3904 char htgt_pl[MLXSW_REG_HTGT_LEN];
3905
Nogah Frankel579c82e2016-11-25 10:33:42 +01003906 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3907 MLXSW_REG_HTGT_INVALID_POLICER,
3908 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3909 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003910 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3911}
3912
Petr Machatac30f5d02017-10-16 16:26:35 +02003913static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3914 unsigned long event, void *ptr);
3915
Jiri Pirkob2f10572016-04-08 19:11:23 +02003916static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003917 const struct mlxsw_bus_info *mlxsw_bus_info)
3918{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003919 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003920 int err;
3921
3922 mlxsw_sp->core = mlxsw_core;
3923 mlxsw_sp->bus_info = mlxsw_bus_info;
3924
Yotam Gigi6b742192017-05-23 21:56:29 +02003925 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3926 if (err) {
3927 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3928 return err;
3929 }
3930
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003931 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3932 if (err) {
3933 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3934 return err;
3935 }
3936
Ido Schimmela875a2e2017-10-22 23:11:44 +02003937 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3938 if (err) {
3939 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3940 return err;
3941 }
3942
Ido Schimmela1107482017-05-26 08:37:39 +02003943 err = mlxsw_sp_fids_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003944 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003945 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
Ido Schimmela875a2e2017-10-22 23:11:44 +02003946 goto err_fids_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003947 }
3948
Ido Schimmela1107482017-05-26 08:37:39 +02003949 err = mlxsw_sp_traps_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003950 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003951 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3952 goto err_traps_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003953 }
3954
3955 err = mlxsw_sp_buffers_init(mlxsw_sp);
3956 if (err) {
3957 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3958 goto err_buffers_init;
3959 }
3960
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003961 err = mlxsw_sp_lag_init(mlxsw_sp);
3962 if (err) {
3963 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3964 goto err_lag_init;
3965 }
3966
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003967 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3968 if (err) {
3969 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3970 goto err_switchdev_init;
3971 }
3972
Yotam Gigie2b2d352017-09-19 10:00:08 +02003973 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3974 if (err) {
3975 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3976 goto err_counter_pool_init;
3977 }
3978
Yotam Gigid3b939b2017-09-19 10:00:09 +02003979 err = mlxsw_sp_afa_init(mlxsw_sp);
3980 if (err) {
3981 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3982 goto err_afa_init;
3983 }
3984
Ido Schimmel464dce12016-07-02 11:00:15 +02003985 err = mlxsw_sp_router_init(mlxsw_sp);
3986 if (err) {
3987 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3988 goto err_router_init;
3989 }
3990
Petr Machatac30f5d02017-10-16 16:26:35 +02003991 /* Initialize netdevice notifier after router is initialized, so that
3992 * the event handler can use router structures.
3993 */
3994 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3995 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3996 if (err) {
3997 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3998 goto err_netdev_notifier;
3999 }
4000
Yotam Gigi763b4b72016-07-21 12:03:17 +02004001 err = mlxsw_sp_span_init(mlxsw_sp);
4002 if (err) {
4003 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
4004 goto err_span_init;
4005 }
4006
Jiri Pirko22a67762017-02-03 10:29:07 +01004007 err = mlxsw_sp_acl_init(mlxsw_sp);
4008 if (err) {
4009 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
4010 goto err_acl_init;
4011 }
4012
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02004013 err = mlxsw_sp_dpipe_init(mlxsw_sp);
4014 if (err) {
4015 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
4016 goto err_dpipe_init;
4017 }
4018
Ido Schimmelbbf2a472016-07-02 11:00:14 +02004019 err = mlxsw_sp_ports_create(mlxsw_sp);
4020 if (err) {
4021 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
4022 goto err_ports_create;
4023 }
4024
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004025 return 0;
4026
Ido Schimmelbbf2a472016-07-02 11:00:14 +02004027err_ports_create:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02004028 mlxsw_sp_dpipe_fini(mlxsw_sp);
4029err_dpipe_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01004030 mlxsw_sp_acl_fini(mlxsw_sp);
4031err_acl_init:
Yotam Gigi763b4b72016-07-21 12:03:17 +02004032 mlxsw_sp_span_fini(mlxsw_sp);
4033err_span_init:
Petr Machatac30f5d02017-10-16 16:26:35 +02004034 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4035err_netdev_notifier:
Ido Schimmel464dce12016-07-02 11:00:15 +02004036 mlxsw_sp_router_fini(mlxsw_sp);
4037err_router_init:
Yotam Gigid3b939b2017-09-19 10:00:09 +02004038 mlxsw_sp_afa_fini(mlxsw_sp);
4039err_afa_init:
Yotam Gigie2b2d352017-09-19 10:00:08 +02004040 mlxsw_sp_counter_pool_fini(mlxsw_sp);
4041err_counter_pool_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02004042 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004043err_switchdev_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02004044 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004045err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02004046 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004047err_buffers_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004048 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02004049err_traps_init:
4050 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02004051err_fids_init:
4052 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004053 return err;
4054}
4055
Jiri Pirkob2f10572016-04-08 19:11:23 +02004056static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004057{
Jiri Pirkob2f10572016-04-08 19:11:23 +02004058 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004059
Ido Schimmelbbf2a472016-07-02 11:00:14 +02004060 mlxsw_sp_ports_remove(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02004061 mlxsw_sp_dpipe_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01004062 mlxsw_sp_acl_fini(mlxsw_sp);
Yotam Gigi763b4b72016-07-21 12:03:17 +02004063 mlxsw_sp_span_fini(mlxsw_sp);
Petr Machatac30f5d02017-10-16 16:26:35 +02004064 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
Ido Schimmel464dce12016-07-02 11:00:15 +02004065 mlxsw_sp_router_fini(mlxsw_sp);
Yotam Gigid3b939b2017-09-19 10:00:09 +02004066 mlxsw_sp_afa_fini(mlxsw_sp);
Yotam Gigie2b2d352017-09-19 10:00:08 +02004067 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004068 mlxsw_sp_switchdev_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02004069 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02004070 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004071 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02004072 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02004073 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004074}
4075
Bhumika Goyal159fe882017-08-11 19:10:42 +05304076static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004077 .used_max_vepa_channels = 1,
4078 .max_vepa_channels = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004079 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01004080 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004081 .used_max_pgt = 1,
4082 .max_pgt = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004083 .used_flood_tables = 1,
4084 .used_flood_mode = 1,
4085 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01004086 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004087 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01004088 .max_fid_flood_tables = 3,
Ido Schimmela1107482017-05-26 08:37:39 +02004089 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004090 .used_max_ib_mc = 1,
4091 .max_ib_mc = 0,
4092 .used_max_pkey = 1,
4093 .max_pkey = 0,
Nogah Frankel403547d2016-09-20 11:16:52 +02004094 .used_kvd_split_data = 1,
4095 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
Ido Schimmelf11fbaf2017-10-22 23:11:49 +02004096 .kvd_hash_single_parts = 59,
4097 .kvd_hash_double_parts = 41,
Jiri Pirkoc6022422016-07-05 11:27:46 +02004098 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004099 .swid_config = {
4100 {
4101 .used_type = 1,
4102 .type = MLXSW_PORT_SWID_TYPE_ETH,
4103 }
4104 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02004105 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004106};
4107
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004108static bool
4109mlxsw_sp_resource_kvd_granularity_validate(struct netlink_ext_ack *extack,
4110 u64 size)
4111{
4112 const struct mlxsw_config_profile *profile;
4113
4114 profile = &mlxsw_sp_config_profile;
4115 if (size % profile->kvd_hash_granularity) {
4116 NL_SET_ERR_MSG_MOD(extack, "resource set with wrong granularity");
4117 return false;
4118 }
4119 return true;
4120}
4121
4122static int
4123mlxsw_sp_resource_kvd_size_validate(struct devlink *devlink, u64 size,
4124 struct netlink_ext_ack *extack)
4125{
4126 NL_SET_ERR_MSG_MOD(extack, "kvd size cannot be changed");
4127 return -EINVAL;
4128}
4129
4130static int
4131mlxsw_sp_resource_kvd_linear_size_validate(struct devlink *devlink, u64 size,
4132 struct netlink_ext_ack *extack)
4133{
4134 if (!mlxsw_sp_resource_kvd_granularity_validate(extack, size))
4135 return -EINVAL;
4136
4137 return 0;
4138}
4139
4140static int
4141mlxsw_sp_resource_kvd_hash_single_size_validate(struct devlink *devlink, u64 size,
4142 struct netlink_ext_ack *extack)
4143{
4144 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
4145
4146 if (!mlxsw_sp_resource_kvd_granularity_validate(extack, size))
4147 return -EINVAL;
4148
4149 if (size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE)) {
4150 NL_SET_ERR_MSG_MOD(extack, "hash single size is smaller than minimum");
4151 return -EINVAL;
4152 }
4153 return 0;
4154}
4155
4156static int
4157mlxsw_sp_resource_kvd_hash_double_size_validate(struct devlink *devlink, u64 size,
4158 struct netlink_ext_ack *extack)
4159{
4160 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
4161
4162 if (!mlxsw_sp_resource_kvd_granularity_validate(extack, size))
4163 return -EINVAL;
4164
4165 if (size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE)) {
4166 NL_SET_ERR_MSG_MOD(extack, "hash double size is smaller than minimum");
4167 return -EINVAL;
4168 }
4169 return 0;
4170}
4171
Arkadi Sharshevskyafadc262018-01-15 08:59:09 +01004172static u64 mlxsw_sp_resource_kvd_linear_occ_get(struct devlink *devlink)
4173{
4174 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
4175 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4176
4177 return mlxsw_sp_kvdl_occ_get(mlxsw_sp);
4178}
4179
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004180static struct devlink_resource_ops mlxsw_sp_resource_kvd_ops = {
4181 .size_validate = mlxsw_sp_resource_kvd_size_validate,
4182};
4183
4184static struct devlink_resource_ops mlxsw_sp_resource_kvd_linear_ops = {
4185 .size_validate = mlxsw_sp_resource_kvd_linear_size_validate,
Arkadi Sharshevskyafadc262018-01-15 08:59:09 +01004186 .occ_get = mlxsw_sp_resource_kvd_linear_occ_get,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004187};
4188
4189static struct devlink_resource_ops mlxsw_sp_resource_kvd_hash_single_ops = {
4190 .size_validate = mlxsw_sp_resource_kvd_hash_single_size_validate,
4191};
4192
4193static struct devlink_resource_ops mlxsw_sp_resource_kvd_hash_double_ops = {
4194 .size_validate = mlxsw_sp_resource_kvd_hash_double_size_validate,
4195};
4196
4197static struct devlink_resource_size_params mlxsw_sp_kvd_size_params;
4198static struct devlink_resource_size_params mlxsw_sp_linear_size_params;
4199static struct devlink_resource_size_params mlxsw_sp_hash_single_size_params;
4200static struct devlink_resource_size_params mlxsw_sp_hash_double_size_params;
4201
4202static void
4203mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core)
4204{
4205 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
4206 KVD_SINGLE_MIN_SIZE);
4207 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
4208 KVD_DOUBLE_MIN_SIZE);
4209 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4210 u32 linear_size_min = 0;
4211
4212 /* KVD top resource */
4213 mlxsw_sp_kvd_size_params.size_min = kvd_size;
4214 mlxsw_sp_kvd_size_params.size_max = kvd_size;
4215 mlxsw_sp_kvd_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
4216 mlxsw_sp_kvd_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
4217
4218 /* Linear part init */
4219 mlxsw_sp_linear_size_params.size_min = linear_size_min;
4220 mlxsw_sp_linear_size_params.size_max = kvd_size - single_size_min -
4221 double_size_min;
4222 mlxsw_sp_linear_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
4223 mlxsw_sp_linear_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
4224
4225 /* Hash double part init */
4226 mlxsw_sp_hash_double_size_params.size_min = double_size_min;
4227 mlxsw_sp_hash_double_size_params.size_max = kvd_size - single_size_min -
4228 linear_size_min;
4229 mlxsw_sp_hash_double_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
4230 mlxsw_sp_hash_double_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
4231
4232 /* Hash single part init */
4233 mlxsw_sp_hash_single_size_params.size_min = single_size_min;
4234 mlxsw_sp_hash_single_size_params.size_max = kvd_size - double_size_min -
4235 linear_size_min;
4236 mlxsw_sp_hash_single_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
4237 mlxsw_sp_hash_single_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
4238}
4239
4240static int mlxsw_sp_resources_register(struct mlxsw_core *mlxsw_core)
4241{
4242 struct devlink *devlink = priv_to_devlink(mlxsw_core);
4243 u32 kvd_size, single_size, double_size, linear_size;
4244 const struct mlxsw_config_profile *profile;
4245 int err;
4246
4247 profile = &mlxsw_sp_config_profile;
4248 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
4249 return -EIO;
4250
4251 mlxsw_sp_resource_size_params_prepare(mlxsw_core);
4252 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4253 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
4254 true, kvd_size,
4255 MLXSW_SP_RESOURCE_KVD,
4256 DEVLINK_RESOURCE_ID_PARENT_TOP,
4257 &mlxsw_sp_kvd_size_params,
4258 &mlxsw_sp_resource_kvd_ops);
4259 if (err)
4260 return err;
4261
4262 linear_size = profile->kvd_linear_size;
4263 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
4264 false, linear_size,
4265 MLXSW_SP_RESOURCE_KVD_LINEAR,
4266 MLXSW_SP_RESOURCE_KVD,
4267 &mlxsw_sp_linear_size_params,
4268 &mlxsw_sp_resource_kvd_linear_ops);
4269 if (err)
4270 return err;
4271
4272 double_size = kvd_size - linear_size;
4273 double_size *= profile->kvd_hash_double_parts;
4274 double_size /= profile->kvd_hash_double_parts +
4275 profile->kvd_hash_single_parts;
4276 double_size = rounddown(double_size, profile->kvd_hash_granularity);
4277 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
4278 false, double_size,
4279 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4280 MLXSW_SP_RESOURCE_KVD,
4281 &mlxsw_sp_hash_double_size_params,
4282 &mlxsw_sp_resource_kvd_hash_double_ops);
4283 if (err)
4284 return err;
4285
4286 single_size = kvd_size - double_size - linear_size;
4287 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
4288 false, single_size,
4289 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4290 MLXSW_SP_RESOURCE_KVD,
4291 &mlxsw_sp_hash_single_size_params,
4292 &mlxsw_sp_resource_kvd_hash_single_ops);
4293 if (err)
4294 return err;
4295
4296 return 0;
4297}
4298
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01004299static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
4300 const struct mlxsw_config_profile *profile,
4301 u64 *p_single_size, u64 *p_double_size,
4302 u64 *p_linear_size)
4303{
4304 struct devlink *devlink = priv_to_devlink(mlxsw_core);
4305 u32 double_size;
4306 int err;
4307
4308 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4309 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
4310 !profile->used_kvd_split_data)
4311 return -EIO;
4312
4313 /* The hash part is what left of the kvd without the
4314 * linear part. It is split to the single size and
4315 * double size by the parts ratio from the profile.
4316 * Both sizes must be a multiplications of the
4317 * granularity from the profile. In case the user
4318 * provided the sizes they are obtained via devlink.
4319 */
4320 err = devlink_resource_size_get(devlink,
4321 MLXSW_SP_RESOURCE_KVD_LINEAR,
4322 p_linear_size);
4323 if (err)
4324 *p_linear_size = profile->kvd_linear_size;
4325
4326 err = devlink_resource_size_get(devlink,
4327 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4328 p_double_size);
4329 if (err) {
4330 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4331 *p_linear_size;
4332 double_size *= profile->kvd_hash_double_parts;
4333 double_size /= profile->kvd_hash_double_parts +
4334 profile->kvd_hash_single_parts;
4335 *p_double_size = rounddown(double_size,
4336 profile->kvd_hash_granularity);
4337 }
4338
4339 err = devlink_resource_size_get(devlink,
4340 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4341 p_single_size);
4342 if (err)
4343 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4344 *p_double_size - *p_linear_size;
4345
4346 /* Check results are legal. */
4347 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4348 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
4349 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
4350 return -EIO;
4351
4352 return 0;
4353}
4354
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004355static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02004356 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02004357 .priv_size = sizeof(struct mlxsw_sp),
4358 .init = mlxsw_sp_init,
4359 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01004360 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02004361 .port_split = mlxsw_sp_port_split,
4362 .port_unsplit = mlxsw_sp_port_unsplit,
4363 .sb_pool_get = mlxsw_sp_sb_pool_get,
4364 .sb_pool_set = mlxsw_sp_sb_pool_set,
4365 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
4366 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
4367 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
4368 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4369 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4370 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4371 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4372 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4373 .txhdr_construct = mlxsw_sp_txhdr_construct,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004374 .resources_register = mlxsw_sp_resources_register,
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01004375 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02004376 .txhdr_len = MLXSW_TXHDR_LEN,
4377 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004378};
4379
Jiri Pirko22a67762017-02-03 10:29:07 +01004380bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004381{
4382 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4383}
4384
Jiri Pirko1182e532017-03-06 21:25:20 +01004385static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07004386{
Jiri Pirko1182e532017-03-06 21:25:20 +01004387 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07004388 int ret = 0;
4389
4390 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01004391 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07004392 ret = 1;
4393 }
4394
4395 return ret;
4396}
4397
Ido Schimmelc57529e2017-05-26 08:37:31 +02004398struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004399{
Jiri Pirko1182e532017-03-06 21:25:20 +01004400 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004401
4402 if (mlxsw_sp_port_dev_check(dev))
4403 return netdev_priv(dev);
4404
Jiri Pirko1182e532017-03-06 21:25:20 +01004405 mlxsw_sp_port = NULL;
4406 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004407
Jiri Pirko1182e532017-03-06 21:25:20 +01004408 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004409}
4410
Ido Schimmel4724ba562017-03-10 08:53:39 +01004411struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004412{
4413 struct mlxsw_sp_port *mlxsw_sp_port;
4414
4415 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4416 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4417}
4418
Arkadi Sharshevskyaf0613782017-06-08 08:44:20 +02004419struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004420{
Jiri Pirko1182e532017-03-06 21:25:20 +01004421 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004422
4423 if (mlxsw_sp_port_dev_check(dev))
4424 return netdev_priv(dev);
4425
Jiri Pirko1182e532017-03-06 21:25:20 +01004426 mlxsw_sp_port = NULL;
4427 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4428 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004429
Jiri Pirko1182e532017-03-06 21:25:20 +01004430 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004431}
4432
4433struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4434{
4435 struct mlxsw_sp_port *mlxsw_sp_port;
4436
4437 rcu_read_lock();
4438 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4439 if (mlxsw_sp_port)
4440 dev_hold(mlxsw_sp_port->dev);
4441 rcu_read_unlock();
4442 return mlxsw_sp_port;
4443}
4444
4445void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4446{
4447 dev_put(mlxsw_sp_port->dev);
4448}
4449
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004450static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004451{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004452 char sldr_pl[MLXSW_REG_SLDR_LEN];
4453
4454 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4455 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4456}
4457
4458static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4459{
4460 char sldr_pl[MLXSW_REG_SLDR_LEN];
4461
4462 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4463 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4464}
4465
4466static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4467 u16 lag_id, u8 port_index)
4468{
4469 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4470 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4471
4472 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4473 lag_id, port_index);
4474 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4475}
4476
4477static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4478 u16 lag_id)
4479{
4480 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4481 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4482
4483 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4484 lag_id);
4485 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4486}
4487
4488static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4489 u16 lag_id)
4490{
4491 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4492 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4493
4494 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4495 lag_id);
4496 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4497}
4498
4499static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4500 u16 lag_id)
4501{
4502 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4503 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4504
4505 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4506 lag_id);
4507 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4508}
4509
4510static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4511 struct net_device *lag_dev,
4512 u16 *p_lag_id)
4513{
4514 struct mlxsw_sp_upper *lag;
4515 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004516 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004517 int i;
4518
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004519 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4520 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004521 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4522 if (lag->ref_count) {
4523 if (lag->dev == lag_dev) {
4524 *p_lag_id = i;
4525 return 0;
4526 }
4527 } else if (free_lag_id < 0) {
4528 free_lag_id = i;
4529 }
4530 }
4531 if (free_lag_id < 0)
4532 return -EBUSY;
4533 *p_lag_id = free_lag_id;
4534 return 0;
4535}
4536
4537static bool
4538mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4539 struct net_device *lag_dev,
David Aherne58376e2017-10-04 17:48:51 -07004540 struct netdev_lag_upper_info *lag_upper_info,
4541 struct netlink_ext_ack *extack)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004542{
4543 u16 lag_id;
4544
David Aherne58376e2017-10-04 17:48:51 -07004545 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
4546 NL_SET_ERR_MSG(extack,
4547 "spectrum: Exceeded number of supported LAG devices");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004548 return false;
David Aherne58376e2017-10-04 17:48:51 -07004549 }
4550 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
4551 NL_SET_ERR_MSG(extack,
4552 "spectrum: LAG device using unsupported Tx type");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004553 return false;
David Aherne58376e2017-10-04 17:48:51 -07004554 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004555 return true;
4556}
4557
4558static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4559 u16 lag_id, u8 *p_port_index)
4560{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004561 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004562 int i;
4563
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004564 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4565 MAX_LAG_MEMBERS);
4566 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004567 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4568 *p_port_index = i;
4569 return 0;
4570 }
4571 }
4572 return -EBUSY;
4573}
4574
4575static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4576 struct net_device *lag_dev)
4577{
4578 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004579 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004580 struct mlxsw_sp_upper *lag;
4581 u16 lag_id;
4582 u8 port_index;
4583 int err;
4584
4585 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4586 if (err)
4587 return err;
4588 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4589 if (!lag->ref_count) {
4590 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4591 if (err)
4592 return err;
4593 lag->dev = lag_dev;
4594 }
4595
4596 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4597 if (err)
4598 return err;
4599 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4600 if (err)
4601 goto err_col_port_add;
4602 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4603 if (err)
4604 goto err_col_port_enable;
4605
4606 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4607 mlxsw_sp_port->local_port);
4608 mlxsw_sp_port->lag_id = lag_id;
4609 mlxsw_sp_port->lagged = 1;
4610 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004611
Ido Schimmelc57529e2017-05-26 08:37:31 +02004612 /* Port is no longer usable as a router interface */
4613 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4614 if (mlxsw_sp_port_vlan->fid)
Ido Schimmela1107482017-05-26 08:37:39 +02004615 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004616
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004617 return 0;
4618
Ido Schimmel51554db2016-05-06 22:18:39 +02004619err_col_port_enable:
4620 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004621err_col_port_add:
4622 if (!lag->ref_count)
4623 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004624 return err;
4625}
4626
Ido Schimmel82e6db02016-06-20 23:04:04 +02004627static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4628 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004629{
4630 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004631 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004632 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004633
4634 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004635 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004636 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4637 WARN_ON(lag->ref_count == 0);
4638
Ido Schimmel82e6db02016-06-20 23:04:04 +02004639 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4640 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004641
Ido Schimmelc57529e2017-05-26 08:37:31 +02004642 /* Any VLANs configured on the port are no longer valid */
4643 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004644
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004645 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004646 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004647
4648 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4649 mlxsw_sp_port->local_port);
4650 mlxsw_sp_port->lagged = 0;
4651 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004652
Ido Schimmelc57529e2017-05-26 08:37:31 +02004653 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4654 /* Make sure untagged frames are allowed to ingress */
4655 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004656}
4657
Jiri Pirko74581202015-12-03 12:12:30 +01004658static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4659 u16 lag_id)
4660{
4661 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4662 char sldr_pl[MLXSW_REG_SLDR_LEN];
4663
4664 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4665 mlxsw_sp_port->local_port);
4666 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4667}
4668
4669static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4670 u16 lag_id)
4671{
4672 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4673 char sldr_pl[MLXSW_REG_SLDR_LEN];
4674
4675 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4676 mlxsw_sp_port->local_port);
4677 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4678}
4679
4680static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4681 bool lag_tx_enabled)
4682{
4683 if (lag_tx_enabled)
4684 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4685 mlxsw_sp_port->lag_id);
4686 else
4687 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4688 mlxsw_sp_port->lag_id);
4689}
4690
4691static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4692 struct netdev_lag_lower_state_info *info)
4693{
4694 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4695}
4696
Jiri Pirko2b94e582017-04-18 16:55:37 +02004697static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4698 bool enable)
4699{
4700 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4701 enum mlxsw_reg_spms_state spms_state;
4702 char *spms_pl;
4703 u16 vid;
4704 int err;
4705
4706 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4707 MLXSW_REG_SPMS_STATE_DISCARDING;
4708
4709 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4710 if (!spms_pl)
4711 return -ENOMEM;
4712 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4713
4714 for (vid = 0; vid < VLAN_N_VID; vid++)
4715 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4716
4717 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4718 kfree(spms_pl);
4719 return err;
4720}
4721
4722static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4723{
Yuval Mintzfccff082017-12-15 08:44:21 +01004724 u16 vid = 1;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004725 int err;
4726
Ido Schimmel4aafc362017-05-26 08:37:25 +02004727 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004728 if (err)
4729 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02004730 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4731 if (err)
4732 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004733 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4734 true, false);
4735 if (err)
4736 goto err_port_vlan_set;
Yuval Mintzfccff082017-12-15 08:44:21 +01004737
4738 for (; vid <= VLAN_N_VID - 1; vid++) {
4739 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4740 vid, false);
4741 if (err)
4742 goto err_vid_learning_set;
4743 }
4744
Jiri Pirko2b94e582017-04-18 16:55:37 +02004745 return 0;
4746
Yuval Mintzfccff082017-12-15 08:44:21 +01004747err_vid_learning_set:
4748 for (vid--; vid >= 1; vid--)
4749 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004750err_port_vlan_set:
4751 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004752err_port_stp_set:
4753 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004754 return err;
4755}
4756
4757static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4758{
Yuval Mintzfccff082017-12-15 08:44:21 +01004759 u16 vid;
4760
4761 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4762 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4763 vid, true);
4764
Jiri Pirko2b94e582017-04-18 16:55:37 +02004765 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4766 false, false);
4767 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004768 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004769}
4770
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004771static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4772 struct net_device *dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004773 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004774{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004775 struct netdev_notifier_changeupper_info *info;
4776 struct mlxsw_sp_port *mlxsw_sp_port;
David Aherne58376e2017-10-04 17:48:51 -07004777 struct netlink_ext_ack *extack;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004778 struct net_device *upper_dev;
4779 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004780 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004781
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004782 mlxsw_sp_port = netdev_priv(dev);
4783 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4784 info = ptr;
David Aherne58376e2017-10-04 17:48:51 -07004785 extack = netdev_notifier_info_to_extack(&info->info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004786
4787 switch (event) {
4788 case NETDEV_PRECHANGEUPPER:
4789 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004790 if (!is_vlan_dev(upper_dev) &&
4791 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004792 !netif_is_bridge_master(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004793 !netif_is_ovs_master(upper_dev)) {
4794 NL_SET_ERR_MSG(extack,
4795 "spectrum: Unknown upper device type");
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004796 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004797 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004798 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004799 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004800 if (netdev_has_any_upper_dev(upper_dev) &&
4801 (!netif_is_bridge_master(upper_dev) ||
4802 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4803 upper_dev))) {
David Aherne58376e2017-10-04 17:48:51 -07004804 NL_SET_ERR_MSG(extack,
4805 "spectrum: Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004806 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004807 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004808 if (netif_is_lag_master(upper_dev) &&
4809 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
David Aherne58376e2017-10-04 17:48:51 -07004810 info->upper_info, extack))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004811 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004812 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
4813 NL_SET_ERR_MSG(extack,
4814 "spectrum: Master device is a LAG master and this device has a VLAN");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004815 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004816 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004817 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004818 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
4819 NL_SET_ERR_MSG(extack,
4820 "spectrum: Can not put a VLAN on a LAG port");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004821 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004822 }
4823 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
4824 NL_SET_ERR_MSG(extack,
4825 "spectrum: Master device is an OVS master and this device has a VLAN");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004826 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004827 }
4828 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
4829 NL_SET_ERR_MSG(extack,
4830 "spectrum: Can not put a VLAN on an OVS port");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004831 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004832 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004833 break;
4834 case NETDEV_CHANGEUPPER:
4835 upper_dev = info->upper_dev;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004836 if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004837 if (info->linking)
4838 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004839 lower_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004840 upper_dev,
4841 extack);
Ido Schimmel7117a572016-06-20 23:04:06 +02004842 else
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004843 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4844 lower_dev,
4845 upper_dev);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004846 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004847 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004848 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4849 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004850 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004851 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4852 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004853 } else if (netif_is_ovs_master(upper_dev)) {
4854 if (info->linking)
4855 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4856 else
4857 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004858 }
4859 break;
4860 }
4861
Ido Schimmel80bedf12016-06-20 23:03:59 +02004862 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004863}
4864
Jiri Pirko74581202015-12-03 12:12:30 +01004865static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4866 unsigned long event, void *ptr)
4867{
4868 struct netdev_notifier_changelowerstate_info *info;
4869 struct mlxsw_sp_port *mlxsw_sp_port;
4870 int err;
4871
4872 mlxsw_sp_port = netdev_priv(dev);
4873 info = ptr;
4874
4875 switch (event) {
4876 case NETDEV_CHANGELOWERSTATE:
4877 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4878 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4879 info->lower_state_info);
4880 if (err)
4881 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4882 }
4883 break;
4884 }
4885
Ido Schimmel80bedf12016-06-20 23:03:59 +02004886 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004887}
4888
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004889static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4890 struct net_device *port_dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004891 unsigned long event, void *ptr)
4892{
4893 switch (event) {
4894 case NETDEV_PRECHANGEUPPER:
4895 case NETDEV_CHANGEUPPER:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004896 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4897 event, ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004898 case NETDEV_CHANGELOWERSTATE:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004899 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4900 ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004901 }
4902
Ido Schimmel80bedf12016-06-20 23:03:59 +02004903 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004904}
4905
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004906static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4907 unsigned long event, void *ptr)
4908{
4909 struct net_device *dev;
4910 struct list_head *iter;
4911 int ret;
4912
4913 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4914 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004915 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4916 ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004917 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004918 return ret;
4919 }
4920 }
4921
Ido Schimmel80bedf12016-06-20 23:03:59 +02004922 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004923}
4924
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004925static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4926 struct net_device *dev,
4927 unsigned long event, void *ptr,
4928 u16 vid)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004929{
4930 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel90045fc2017-12-25 09:05:33 +01004931 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004932 struct netdev_notifier_changeupper_info *info = ptr;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004933 struct netlink_ext_ack *extack;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004934 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004935 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004936
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004937 extack = netdev_notifier_info_to_extack(&info->info);
4938
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004939 switch (event) {
4940 case NETDEV_PRECHANGEUPPER:
4941 upper_dev = info->upper_dev;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004942 if (!netif_is_bridge_master(upper_dev)) {
4943 NL_SET_ERR_MSG(extack, "spectrum: VLAN devices only support bridge and VRF uppers");
Ido Schimmel80bedf12016-06-20 23:03:59 +02004944 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004945 }
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004946 if (!info->linking)
4947 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004948 if (netdev_has_any_upper_dev(upper_dev) &&
4949 (!netif_is_bridge_master(upper_dev) ||
4950 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4951 upper_dev))) {
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004952 NL_SET_ERR_MSG(extack, "spectrum: Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004953 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004954 }
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004955 break;
4956 case NETDEV_CHANGEUPPER:
4957 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004958 if (netif_is_bridge_master(upper_dev)) {
4959 if (info->linking)
Ido Schimmelc57529e2017-05-26 08:37:31 +02004960 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4961 vlan_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004962 upper_dev,
4963 extack);
Ido Schimmel1f880612017-03-10 08:53:35 +01004964 else
Ido Schimmelc57529e2017-05-26 08:37:31 +02004965 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4966 vlan_dev,
4967 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004968 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004969 err = -EINVAL;
4970 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004971 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004972 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004973 }
4974
Ido Schimmel80bedf12016-06-20 23:03:59 +02004975 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004976}
4977
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004978static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4979 struct net_device *lag_dev,
4980 unsigned long event,
4981 void *ptr, u16 vid)
Ido Schimmel272c4472015-12-15 16:03:47 +01004982{
4983 struct net_device *dev;
4984 struct list_head *iter;
4985 int ret;
4986
4987 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4988 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004989 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4990 event, ptr,
4991 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004992 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004993 return ret;
4994 }
4995 }
4996
Ido Schimmel80bedf12016-06-20 23:03:59 +02004997 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004998}
4999
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01005000static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
5001 unsigned long event, void *ptr)
5002{
5003 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
5004 u16 vid = vlan_dev_vlan_id(vlan_dev);
5005
Ido Schimmel272c4472015-12-15 16:03:47 +01005006 if (mlxsw_sp_port_dev_check(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02005007 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
5008 event, ptr, vid);
Ido Schimmel272c4472015-12-15 16:03:47 +01005009 else if (netif_is_lag_master(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02005010 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
5011 real_dev, event,
5012 ptr, vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01005013
Ido Schimmel80bedf12016-06-20 23:03:59 +02005014 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01005015}
5016
Ido Schimmelb1e45522017-04-30 19:47:14 +03005017static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
5018{
5019 struct netdev_notifier_changeupper_info *info = ptr;
5020
5021 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
5022 return false;
5023 return netif_is_l3_master(info->upper_dev);
5024}
5025
Petr Machata00635872017-10-16 16:26:37 +02005026static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005027 unsigned long event, void *ptr)
5028{
5029 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Petr Machata00635872017-10-16 16:26:37 +02005030 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02005031 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005032
Petr Machata00635872017-10-16 16:26:37 +02005033 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
Petr Machata796ec772017-11-03 10:03:29 +01005034 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
5035 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
5036 event, ptr);
Petr Machata61481f22017-11-03 10:03:41 +01005037 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
5038 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
5039 event, ptr);
Petr Machata00635872017-10-16 16:26:37 +02005040 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
Ido Schimmel6e095fd2016-07-04 08:23:13 +02005041 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03005042 else if (mlxsw_sp_is_vrf_event(event, ptr))
5043 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02005044 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02005045 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02005046 else if (netif_is_lag_master(dev))
5047 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
5048 else if (is_vlan_dev(dev))
5049 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005050
Ido Schimmel80bedf12016-06-20 23:03:59 +02005051 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005052}
5053
David Ahern89d5dd22017-10-18 09:56:55 -07005054static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
5055 .notifier_call = mlxsw_sp_inetaddr_valid_event,
5056};
5057
Ido Schimmel99724c12016-07-04 08:23:14 +02005058static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
5059 .notifier_call = mlxsw_sp_inetaddr_event,
David Ahern89d5dd22017-10-18 09:56:55 -07005060};
5061
5062static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
5063 .notifier_call = mlxsw_sp_inet6addr_valid_event,
Ido Schimmel99724c12016-07-04 08:23:14 +02005064};
5065
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005066static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
5067 .notifier_call = mlxsw_sp_inet6addr_event,
5068};
5069
Jiri Pirko1d20d232016-10-27 15:12:59 +02005070static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
5071 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
5072 {0, },
5073};
5074
5075static struct pci_driver mlxsw_sp_pci_driver = {
5076 .name = mlxsw_sp_driver_name,
5077 .id_table = mlxsw_sp_pci_id_table,
5078};
5079
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005080static int __init mlxsw_sp_module_init(void)
5081{
5082 int err;
5083
David Ahern89d5dd22017-10-18 09:56:55 -07005084 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02005085 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005086 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005087 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02005088
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005089 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
5090 if (err)
5091 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02005092
5093 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
5094 if (err)
5095 goto err_pci_driver_register;
5096
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005097 return 0;
5098
Jiri Pirko1d20d232016-10-27 15:12:59 +02005099err_pci_driver_register:
5100 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005101err_core_driver_register:
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005102 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005103 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02005104 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005105 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005106 return err;
5107}
5108
5109static void __exit mlxsw_sp_module_exit(void)
5110{
Jiri Pirko1d20d232016-10-27 15:12:59 +02005111 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005112 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005113 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005114 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02005115 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005116 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005117}
5118
5119module_init(mlxsw_sp_module_init);
5120module_exit(mlxsw_sp_module_exit);
5121
5122MODULE_LICENSE("Dual BSD/GPL");
5123MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
5124MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02005125MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Yotam Gigi6b742192017-05-23 21:56:29 +02005126MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);