blob: 833cd0a96fd9d20581175a4d01f88fa43a5f9cc1 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Jiri Pirko22a67762017-02-03 10:29:07 +01003 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +020056#include <linux/netlink.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020057#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020058#include <net/pkt_cls.h>
59#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020060#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010061#include <net/tc_act/tc_sample.h>
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +020062#include <net/addrconf.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020063
64#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020065#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020066#include "core.h"
67#include "reg.h"
68#include "port.h"
69#include "trap.h"
70#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010071#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020072#include "spectrum_dpipe.h"
Yotam Gigid3b939b2017-09-19 10:00:09 +020073#include "spectrum_acl_flex_actions.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020074#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020075
Yotam Gigi6b742192017-05-23 21:56:29 +020076#define MLXSW_FWREV_MAJOR 13
Shalom Toledo2f53fbd2017-11-12 09:01:24 +010077#define MLXSW_FWREV_MINOR 1530
78#define MLXSW_FWREV_SUBMINOR 152
Yuval Mintzfd5204c2018-01-18 12:55:23 +010079#define MLXSW_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
Yotam Gigi6b742192017-05-23 21:56:29 +020080
81#define MLXSW_SP_FW_FILENAME \
Yotam Gigia4e1ce22017-06-04 16:49:58 +020082 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
Yotam Gigi6b742192017-05-23 21:56:29 +020083 "." __stringify(MLXSW_FWREV_MINOR) \
84 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
85
Jiri Pirko56ade8f2015-10-16 14:01:37 +020086static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
87static const char mlxsw_sp_driver_version[] = "1.0";
88
89/* tx_hdr_version
90 * Tx header version.
91 * Must be set to 1.
92 */
93MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
94
95/* tx_hdr_ctl
96 * Packet control type.
97 * 0 - Ethernet control (e.g. EMADs, LACP)
98 * 1 - Ethernet data
99 */
100MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
101
102/* tx_hdr_proto
103 * Packet protocol type. Must be set to 1 (Ethernet).
104 */
105MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
106
107/* tx_hdr_rx_is_router
108 * Packet is sent from the router. Valid for data packets only.
109 */
110MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
111
112/* tx_hdr_fid_valid
113 * Indicates if the 'fid' field is valid and should be used for
114 * forwarding lookup. Valid for data packets only.
115 */
116MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
117
118/* tx_hdr_swid
119 * Switch partition ID. Must be set to 0.
120 */
121MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
122
123/* tx_hdr_control_tclass
124 * Indicates if the packet should use the control TClass and not one
125 * of the data TClasses.
126 */
127MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
128
129/* tx_hdr_etclass
130 * Egress TClass to be used on the egress device on the egress port.
131 */
132MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
133
134/* tx_hdr_port_mid
135 * Destination local port for unicast packets.
136 * Destination multicast ID for multicast packets.
137 *
138 * Control packets are directed to a specific egress port, while data
139 * packets are transmitted through the CPU port (0) into the switch partition,
140 * where forwarding rules are applied.
141 */
142MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
143
144/* tx_hdr_fid
145 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
146 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
147 * Valid for data packets only.
148 */
149MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
150
151/* tx_hdr_type
152 * 0 - Data packets
153 * 6 - Control packets
154 */
155MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
156
Yotam Gigie5e5c882017-05-23 21:56:27 +0200157struct mlxsw_sp_mlxfw_dev {
158 struct mlxfw_dev mlxfw_dev;
159 struct mlxsw_sp *mlxsw_sp;
160};
161
162static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
163 u16 component_index, u32 *p_max_size,
164 u8 *p_align_bits, u16 *p_max_write_size)
165{
166 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
167 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
168 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
169 char mcqi_pl[MLXSW_REG_MCQI_LEN];
170 int err;
171
172 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
173 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
174 if (err)
175 return err;
176 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
177 p_max_write_size);
178
179 *p_align_bits = max_t(u8, *p_align_bits, 2);
180 *p_max_write_size = min_t(u16, *p_max_write_size,
181 MLXSW_REG_MCDA_MAX_DATA_LEN);
182 return 0;
183}
184
185static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
186{
187 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
188 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
189 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
190 char mcc_pl[MLXSW_REG_MCC_LEN];
191 u8 control_state;
192 int err;
193
194 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
195 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
196 if (err)
197 return err;
198
199 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
200 if (control_state != MLXFW_FSM_STATE_IDLE)
201 return -EBUSY;
202
203 mlxsw_reg_mcc_pack(mcc_pl,
204 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
205 0, *fwhandle, 0);
206 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
207}
208
209static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
210 u32 fwhandle, u16 component_index,
211 u32 component_size)
212{
213 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
214 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
215 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
216 char mcc_pl[MLXSW_REG_MCC_LEN];
217
218 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
219 component_index, fwhandle, component_size);
220 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
221}
222
223static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
224 u32 fwhandle, u8 *data, u16 size,
225 u32 offset)
226{
227 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
228 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
229 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
230 char mcda_pl[MLXSW_REG_MCDA_LEN];
231
232 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
233 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
234}
235
236static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
237 u32 fwhandle, u16 component_index)
238{
239 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
240 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
241 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
242 char mcc_pl[MLXSW_REG_MCC_LEN];
243
244 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
245 component_index, fwhandle, 0);
246 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
247}
248
249static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
250{
251 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
252 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
253 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
254 char mcc_pl[MLXSW_REG_MCC_LEN];
255
256 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
257 fwhandle, 0);
258 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
259}
260
261static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
262 enum mlxfw_fsm_state *fsm_state,
263 enum mlxfw_fsm_state_err *fsm_state_err)
264{
265 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
266 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
267 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
268 char mcc_pl[MLXSW_REG_MCC_LEN];
269 u8 control_state;
270 u8 error_code;
271 int err;
272
273 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
274 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
275 if (err)
276 return err;
277
278 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
279 *fsm_state = control_state;
280 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
281 MLXFW_FSM_STATE_ERR_MAX);
282 return 0;
283}
284
285static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
286{
287 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
288 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
289 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
290 char mcc_pl[MLXSW_REG_MCC_LEN];
291
292 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
293 fwhandle, 0);
294 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
295}
296
297static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
298{
299 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
300 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
301 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
302 char mcc_pl[MLXSW_REG_MCC_LEN];
303
304 mlxsw_reg_mcc_pack(mcc_pl,
305 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
306 fwhandle, 0);
307 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
308}
309
310static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
311 .component_query = mlxsw_sp_component_query,
312 .fsm_lock = mlxsw_sp_fsm_lock,
313 .fsm_component_update = mlxsw_sp_fsm_component_update,
314 .fsm_block_download = mlxsw_sp_fsm_block_download,
315 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
316 .fsm_activate = mlxsw_sp_fsm_activate,
317 .fsm_query_state = mlxsw_sp_fsm_query_state,
318 .fsm_cancel = mlxsw_sp_fsm_cancel,
319 .fsm_release = mlxsw_sp_fsm_release
320};
321
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300322static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
323 const struct firmware *firmware)
324{
325 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
326 .mlxfw_dev = {
327 .ops = &mlxsw_sp_mlxfw_dev_ops,
328 .psid = mlxsw_sp->bus_info->psid,
329 .psid_size = strlen(mlxsw_sp->bus_info->psid),
330 },
331 .mlxsw_sp = mlxsw_sp
332 };
333
334 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
335}
336
Yotam Gigi6b742192017-05-23 21:56:29 +0200337static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
338{
339 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
Yotam Gigi6b742192017-05-23 21:56:29 +0200340 const struct firmware *firmware;
341 int err;
342
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100343 /* Validate driver & FW are compatible */
344 if (rev->major != MLXSW_FWREV_MAJOR) {
345 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
346 rev->major, MLXSW_FWREV_MAJOR);
347 return -EINVAL;
348 }
349 if (MLXSW_FWREV_MINOR_TO_BRANCH(rev->minor) ==
350 MLXSW_FWREV_MINOR_TO_BRANCH(MLXSW_FWREV_MINOR))
Yotam Gigi6b742192017-05-23 21:56:29 +0200351 return 0;
352
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100353 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200354 rev->major, rev->minor, rev->subminor);
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100355 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200356 MLXSW_SP_FW_FILENAME);
357
358 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
359 mlxsw_sp->bus_info->dev);
360 if (err) {
361 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
362 MLXSW_SP_FW_FILENAME);
363 return err;
364 }
365
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300366 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
Yotam Gigi6b742192017-05-23 21:56:29 +0200367 release_firmware(firmware);
368 return err;
369}
370
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100371int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
372 unsigned int counter_index, u64 *packets,
373 u64 *bytes)
374{
375 char mgpc_pl[MLXSW_REG_MGPC_LEN];
376 int err;
377
378 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200379 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100380 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
381 if (err)
382 return err;
Arkadi Sharshevsky7cfcbc72017-08-24 08:40:08 +0200383 if (packets)
384 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
385 if (bytes)
386 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100387 return 0;
388}
389
390static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
391 unsigned int counter_index)
392{
393 char mgpc_pl[MLXSW_REG_MGPC_LEN];
394
395 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200396 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100397 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
398}
399
400int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
401 unsigned int *p_counter_index)
402{
403 int err;
404
405 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
406 p_counter_index);
407 if (err)
408 return err;
409 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
410 if (err)
411 goto err_counter_clear;
412 return 0;
413
414err_counter_clear:
415 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
416 *p_counter_index);
417 return err;
418}
419
420void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
421 unsigned int counter_index)
422{
423 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
424 counter_index);
425}
426
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200427static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
428 const struct mlxsw_tx_info *tx_info)
429{
430 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
431
432 memset(txhdr, 0, MLXSW_TXHDR_LEN);
433
434 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
435 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
436 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
437 mlxsw_tx_hdr_swid_set(txhdr, 0);
438 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
439 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
440 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
441}
442
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200443int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
444 u8 state)
445{
446 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
447 enum mlxsw_reg_spms_state spms_state;
448 char *spms_pl;
449 int err;
450
451 switch (state) {
452 case BR_STATE_FORWARDING:
453 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
454 break;
455 case BR_STATE_LEARNING:
456 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
457 break;
458 case BR_STATE_LISTENING: /* fall-through */
459 case BR_STATE_DISABLED: /* fall-through */
460 case BR_STATE_BLOCKING:
461 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
462 break;
463 default:
464 BUG();
465 }
466
467 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
468 if (!spms_pl)
469 return -ENOMEM;
470 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
471 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
472
473 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
474 kfree(spms_pl);
475 return err;
476}
477
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200478static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
479{
Elad Raz5b090742016-10-28 21:35:46 +0200480 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200481 int err;
482
483 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
484 if (err)
485 return err;
486 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
487 return 0;
488}
489
Yotam Gigi763b4b72016-07-21 12:03:17 +0200490static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
491{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200492 int i;
493
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200494 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
Yotam Gigi763b4b72016-07-21 12:03:17 +0200495 return -EIO;
496
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200497 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
498 MAX_SPAN);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200499 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
500 sizeof(struct mlxsw_sp_span_entry),
501 GFP_KERNEL);
502 if (!mlxsw_sp->span.entries)
503 return -ENOMEM;
504
505 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
506 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
507
508 return 0;
509}
510
511static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
512{
513 int i;
514
515 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
516 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
517
518 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
519 }
520 kfree(mlxsw_sp->span.entries);
521}
522
523static struct mlxsw_sp_span_entry *
524mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
525{
526 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
527 struct mlxsw_sp_span_entry *span_entry;
528 char mpat_pl[MLXSW_REG_MPAT_LEN];
529 u8 local_port = port->local_port;
530 int index;
531 int i;
532 int err;
533
534 /* find a free entry to use */
535 index = -1;
536 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
537 if (!mlxsw_sp->span.entries[i].used) {
538 index = i;
539 span_entry = &mlxsw_sp->span.entries[i];
540 break;
541 }
542 }
543 if (index < 0)
544 return NULL;
545
546 /* create a new port analayzer entry for local_port */
547 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
548 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
549 if (err)
550 return NULL;
551
552 span_entry->used = true;
553 span_entry->id = index;
Yotam Gigi2d644d42016-11-11 16:34:25 +0100554 span_entry->ref_count = 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200555 span_entry->local_port = local_port;
556 return span_entry;
557}
558
559static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
560 struct mlxsw_sp_span_entry *span_entry)
561{
562 u8 local_port = span_entry->local_port;
563 char mpat_pl[MLXSW_REG_MPAT_LEN];
564 int pa_id = span_entry->id;
565
566 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
567 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
568 span_entry->used = false;
569}
570
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100571struct mlxsw_sp_span_entry *
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200572mlxsw_sp_span_entry_find(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200573{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200574 int i;
575
576 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
577 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
578
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200579 if (curr->used && curr->local_port == local_port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200580 return curr;
581 }
582 return NULL;
583}
584
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200585static struct mlxsw_sp_span_entry
586*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200587{
588 struct mlxsw_sp_span_entry *span_entry;
589
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200590 span_entry = mlxsw_sp_span_entry_find(port->mlxsw_sp,
591 port->local_port);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200592 if (span_entry) {
Yotam Gigi2d644d42016-11-11 16:34:25 +0100593 /* Already exists, just take a reference */
Yotam Gigi763b4b72016-07-21 12:03:17 +0200594 span_entry->ref_count++;
595 return span_entry;
596 }
597
598 return mlxsw_sp_span_entry_create(port);
599}
600
601static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
602 struct mlxsw_sp_span_entry *span_entry)
603{
Yotam Gigi2d644d42016-11-11 16:34:25 +0100604 WARN_ON(!span_entry->ref_count);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200605 if (--span_entry->ref_count == 0)
606 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
607 return 0;
608}
609
610static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
611{
612 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
613 struct mlxsw_sp_span_inspected_port *p;
614 int i;
615
616 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
617 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
618
619 list_for_each_entry(p, &curr->bound_ports_list, list)
620 if (p->local_port == port->local_port &&
621 p->type == MLXSW_SP_SPAN_EGRESS)
622 return true;
623 }
624
625 return false;
626}
627
Ido Schimmel18281f22017-03-24 08:02:51 +0100628static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
629 int mtu)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200630{
Ido Schimmel18281f22017-03-24 08:02:51 +0100631 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200632}
633
634static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
635{
636 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
637 char sbib_pl[MLXSW_REG_SBIB_LEN];
638 int err;
639
640 /* If port is egress mirrored, the shared buffer size should be
641 * updated according to the mtu value
642 */
643 if (mlxsw_sp_span_is_egress_mirror(port)) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100644 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
645
646 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200647 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
648 if (err) {
649 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
650 return err;
651 }
652 }
653
654 return 0;
655}
656
657static struct mlxsw_sp_span_inspected_port *
658mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
659 struct mlxsw_sp_span_entry *span_entry)
660{
661 struct mlxsw_sp_span_inspected_port *p;
662
663 list_for_each_entry(p, &span_entry->bound_ports_list, list)
664 if (port->local_port == p->local_port)
665 return p;
666 return NULL;
667}
668
669static int
670mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
671 struct mlxsw_sp_span_entry *span_entry,
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100672 enum mlxsw_sp_span_type type,
673 bool bind)
674{
675 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
676 char mpar_pl[MLXSW_REG_MPAR_LEN];
677 int pa_id = span_entry->id;
678
679 /* bind the port to the SPAN entry */
680 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
681 (enum mlxsw_reg_mpar_i_e) type, bind, pa_id);
682 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
683}
684
685static int
686mlxsw_sp_span_inspected_port_add(struct mlxsw_sp_port *port,
687 struct mlxsw_sp_span_entry *span_entry,
688 enum mlxsw_sp_span_type type,
689 bool bind)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200690{
691 struct mlxsw_sp_span_inspected_port *inspected_port;
692 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200693 char sbib_pl[MLXSW_REG_SBIB_LEN];
Yotam Gigi763b4b72016-07-21 12:03:17 +0200694 int err;
695
696 /* if it is an egress SPAN, bind a shared buffer to it */
697 if (type == MLXSW_SP_SPAN_EGRESS) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100698 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
699 port->dev->mtu);
700
701 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200702 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
703 if (err) {
704 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
705 return err;
706 }
707 }
708
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100709 if (bind) {
710 err = mlxsw_sp_span_inspected_port_bind(port, span_entry, type,
711 true);
712 if (err)
713 goto err_port_bind;
714 }
Yotam Gigi763b4b72016-07-21 12:03:17 +0200715
716 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
717 if (!inspected_port) {
718 err = -ENOMEM;
719 goto err_inspected_port_alloc;
720 }
721 inspected_port->local_port = port->local_port;
722 inspected_port->type = type;
723 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
724
725 return 0;
726
Yotam Gigi763b4b72016-07-21 12:03:17 +0200727err_inspected_port_alloc:
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100728 if (bind)
729 mlxsw_sp_span_inspected_port_bind(port, span_entry, type,
730 false);
731err_port_bind:
Yotam Gigi763b4b72016-07-21 12:03:17 +0200732 if (type == MLXSW_SP_SPAN_EGRESS) {
733 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
734 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
735 }
736 return err;
737}
738
739static void
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100740mlxsw_sp_span_inspected_port_del(struct mlxsw_sp_port *port,
741 struct mlxsw_sp_span_entry *span_entry,
742 enum mlxsw_sp_span_type type,
743 bool bind)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200744{
745 struct mlxsw_sp_span_inspected_port *inspected_port;
746 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200747 char sbib_pl[MLXSW_REG_SBIB_LEN];
Yotam Gigi763b4b72016-07-21 12:03:17 +0200748
749 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
750 if (!inspected_port)
751 return;
752
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100753 if (bind)
754 mlxsw_sp_span_inspected_port_bind(port, span_entry, type,
755 false);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200756 /* remove the SBIB buffer if it was egress SPAN */
757 if (type == MLXSW_SP_SPAN_EGRESS) {
758 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
759 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
760 }
761
762 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
763
764 list_del(&inspected_port->list);
765 kfree(inspected_port);
766}
767
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100768int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
769 struct mlxsw_sp_port *to,
770 enum mlxsw_sp_span_type type, bool bind)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200771{
772 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
773 struct mlxsw_sp_span_entry *span_entry;
774 int err;
775
776 span_entry = mlxsw_sp_span_entry_get(to);
777 if (!span_entry)
778 return -ENOENT;
779
780 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
781 span_entry->id);
782
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100783 err = mlxsw_sp_span_inspected_port_add(from, span_entry, type, bind);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200784 if (err)
785 goto err_port_bind;
786
787 return 0;
788
789err_port_bind:
790 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
791 return err;
792}
793
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100794void mlxsw_sp_span_mirror_del(struct mlxsw_sp_port *from, u8 destination_port,
795 enum mlxsw_sp_span_type type, bool bind)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200796{
797 struct mlxsw_sp_span_entry *span_entry;
798
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200799 span_entry = mlxsw_sp_span_entry_find(from->mlxsw_sp,
800 destination_port);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200801 if (!span_entry) {
802 netdev_err(from->dev, "no span entry found\n");
803 return;
804 }
805
806 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
807 span_entry->id);
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +0100808 mlxsw_sp_span_inspected_port_del(from, span_entry, type, bind);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200809}
810
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100811static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
812 bool enable, u32 rate)
813{
814 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
815 char mpsc_pl[MLXSW_REG_MPSC_LEN];
816
817 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
818 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
819}
820
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200821static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
822 bool is_up)
823{
824 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
825 char paos_pl[MLXSW_REG_PAOS_LEN];
826
827 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
828 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
829 MLXSW_PORT_ADMIN_STATUS_DOWN);
830 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
831}
832
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200833static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
834 unsigned char *addr)
835{
836 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
837 char ppad_pl[MLXSW_REG_PPAD_LEN];
838
839 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
840 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
841 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
842}
843
844static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
845{
846 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
847 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
848
849 ether_addr_copy(addr, mlxsw_sp->base_mac);
850 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
851 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
852}
853
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200854static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
855{
856 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
857 char pmtu_pl[MLXSW_REG_PMTU_LEN];
858 int max_mtu;
859 int err;
860
861 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
862 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
863 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
864 if (err)
865 return err;
866 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
867
868 if (mtu > max_mtu)
869 return -EINVAL;
870
871 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
872 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
873}
874
875static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
876{
877 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel5b153852017-06-08 08:47:44 +0200878 char pspa_pl[MLXSW_REG_PSPA_LEN];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200879
Ido Schimmel5b153852017-06-08 08:47:44 +0200880 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
881 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200882}
883
Ido Schimmela1107482017-05-26 08:37:39 +0200884int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200885{
886 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
887 char svpe_pl[MLXSW_REG_SVPE_LEN];
888
889 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
890 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
891}
892
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200893int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
894 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200895{
896 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
897 char *spvmlr_pl;
898 int err;
899
900 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
901 if (!spvmlr_pl)
902 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200903 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
904 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200905 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
906 kfree(spvmlr_pl);
907 return err;
908}
909
Ido Schimmelb02eae92017-05-16 19:38:34 +0200910static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
911 u16 vid)
912{
913 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
914 char spvid_pl[MLXSW_REG_SPVID_LEN];
915
916 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
917 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
918}
919
920static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
921 bool allow)
922{
923 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
924 char spaft_pl[MLXSW_REG_SPAFT_LEN];
925
926 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
927 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
928}
929
930int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
931{
932 int err;
933
934 if (!vid) {
935 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
936 if (err)
937 return err;
938 } else {
939 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
940 if (err)
941 return err;
942 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
943 if (err)
944 goto err_port_allow_untagged_set;
945 }
946
947 mlxsw_sp_port->pvid = vid;
948 return 0;
949
950err_port_allow_untagged_set:
951 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
952 return err;
953}
954
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200955static int
956mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
957{
958 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
959 char sspr_pl[MLXSW_REG_SSPR_LEN];
960
961 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
962 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
963}
964
Ido Schimmeld664b412016-06-09 09:51:40 +0200965static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
966 u8 local_port, u8 *p_module,
967 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200968{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200969 char pmlp_pl[MLXSW_REG_PMLP_LEN];
970 int err;
971
Ido Schimmel558c2d52016-02-26 17:32:29 +0100972 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200973 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
974 if (err)
975 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100976 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
977 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200978 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200979 return 0;
980}
981
Ido Schimmel2e915e02017-06-08 08:47:45 +0200982static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100983 u8 module, u8 width, u8 lane)
984{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200985 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel18f1e702016-02-26 17:32:31 +0100986 char pmlp_pl[MLXSW_REG_PMLP_LEN];
987 int i;
988
Ido Schimmel2e915e02017-06-08 08:47:45 +0200989 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel18f1e702016-02-26 17:32:31 +0100990 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
991 for (i = 0; i < width; i++) {
992 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
993 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
994 }
995
996 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
997}
998
Ido Schimmel2e915e02017-06-08 08:47:45 +0200999static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01001000{
Ido Schimmel2e915e02017-06-08 08:47:45 +02001001 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01001002 char pmlp_pl[MLXSW_REG_PMLP_LEN];
1003
Ido Schimmel2e915e02017-06-08 08:47:45 +02001004 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01001005 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
1006 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
1007}
1008
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001009static int mlxsw_sp_port_open(struct net_device *dev)
1010{
1011 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1012 int err;
1013
1014 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1015 if (err)
1016 return err;
1017 netif_start_queue(dev);
1018 return 0;
1019}
1020
1021static int mlxsw_sp_port_stop(struct net_device *dev)
1022{
1023 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1024
1025 netif_stop_queue(dev);
1026 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1027}
1028
1029static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
1030 struct net_device *dev)
1031{
1032 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1033 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1034 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
1035 const struct mlxsw_tx_info tx_info = {
1036 .local_port = mlxsw_sp_port->local_port,
1037 .is_emad = false,
1038 };
1039 u64 len;
1040 int err;
1041
Jiri Pirko307c2432016-04-08 19:11:22 +02001042 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001043 return NETDEV_TX_BUSY;
1044
1045 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
1046 struct sk_buff *skb_orig = skb;
1047
1048 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
1049 if (!skb) {
1050 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1051 dev_kfree_skb_any(skb_orig);
1052 return NETDEV_TX_OK;
1053 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +01001054 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001055 }
1056
1057 if (eth_skb_pad(skb)) {
1058 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1059 return NETDEV_TX_OK;
1060 }
1061
1062 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +02001063 /* TX header is consumed by HW on the way so we shouldn't count its
1064 * bytes as being sent.
1065 */
1066 len = skb->len - MLXSW_TXHDR_LEN;
1067
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001068 /* Due to a race we might fail here because of a full queue. In that
1069 * unlikely case we simply drop the packet.
1070 */
Jiri Pirko307c2432016-04-08 19:11:22 +02001071 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001072
1073 if (!err) {
1074 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
1075 u64_stats_update_begin(&pcpu_stats->syncp);
1076 pcpu_stats->tx_packets++;
1077 pcpu_stats->tx_bytes += len;
1078 u64_stats_update_end(&pcpu_stats->syncp);
1079 } else {
1080 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1081 dev_kfree_skb_any(skb);
1082 }
1083 return NETDEV_TX_OK;
1084}
1085
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001086static void mlxsw_sp_set_rx_mode(struct net_device *dev)
1087{
1088}
1089
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001090static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
1091{
1092 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1093 struct sockaddr *addr = p;
1094 int err;
1095
1096 if (!is_valid_ether_addr(addr->sa_data))
1097 return -EADDRNOTAVAIL;
1098
1099 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
1100 if (err)
1101 return err;
1102 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1103 return 0;
1104}
1105
Ido Schimmel18281f22017-03-24 08:02:51 +01001106static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
1107 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001108{
Ido Schimmel18281f22017-03-24 08:02:51 +01001109 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001110}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001111
Ido Schimmelf417f042017-03-24 08:02:50 +01001112#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +01001113
1114static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1115 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +01001116{
Ido Schimmel18281f22017-03-24 08:02:51 +01001117 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
1118 BITS_PER_BYTE));
1119 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
1120 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001121}
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001122
Ido Schimmel18281f22017-03-24 08:02:51 +01001123/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +01001124 * Assumes 100m cable and maximum MTU.
1125 */
Ido Schimmel18281f22017-03-24 08:02:51 +01001126#define MLXSW_SP_PAUSE_DELAY 58752
1127
1128static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1129 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +01001130{
1131 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +01001132 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +01001133 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +01001134 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001135 else
Ido Schimmelf417f042017-03-24 08:02:50 +01001136 return 0;
1137}
1138
1139static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
1140 bool lossy)
1141{
1142 if (lossy)
1143 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
1144 else
1145 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
1146 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001147}
1148
1149int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001150 u8 *prio_tc, bool pause_en,
1151 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +02001152{
1153 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001154 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
1155 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001156 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001157 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001158
1159 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
1160 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1161 if (err)
1162 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001163
1164 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1165 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001166 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +01001167 bool lossy;
1168 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001169
1170 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
1171 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001172 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001173 configure = true;
1174 break;
1175 }
1176 }
1177
1178 if (!configure)
1179 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +01001180
1181 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +01001182 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
1183 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
1184 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +01001185 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001186 }
1187
Ido Schimmelff6551e2016-04-06 17:10:03 +02001188 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1189}
1190
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001191static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001192 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001193{
1194 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
1195 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001196 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001197 u8 *prio_tc;
1198
1199 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001200 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001201
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001202 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001203 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001204}
1205
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001206static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
1207{
1208 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001209 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001210 int err;
1211
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001212 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001213 if (err)
1214 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001215 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1216 if (err)
1217 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001218 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1219 if (err)
1220 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001221 dev->mtu = mtu;
1222 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001223
1224err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001225 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1226err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001227 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +02001228 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001229}
1230
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001231static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001232mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1233 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001234{
1235 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1236 struct mlxsw_sp_port_pcpu_stats *p;
1237 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1238 u32 tx_dropped = 0;
1239 unsigned int start;
1240 int i;
1241
1242 for_each_possible_cpu(i) {
1243 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1244 do {
1245 start = u64_stats_fetch_begin_irq(&p->syncp);
1246 rx_packets = p->rx_packets;
1247 rx_bytes = p->rx_bytes;
1248 tx_packets = p->tx_packets;
1249 tx_bytes = p->tx_bytes;
1250 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1251
1252 stats->rx_packets += rx_packets;
1253 stats->rx_bytes += rx_bytes;
1254 stats->tx_packets += tx_packets;
1255 stats->tx_bytes += tx_bytes;
1256 /* tx_dropped is u32, updated without syncp protection. */
1257 tx_dropped += p->tx_dropped;
1258 }
1259 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001260 return 0;
1261}
1262
Or Gerlitz3df5b3c2016-11-22 23:09:54 +02001263static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001264{
1265 switch (attr_id) {
1266 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1267 return true;
1268 }
1269
1270 return false;
1271}
1272
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001273static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1274 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001275{
1276 switch (attr_id) {
1277 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1278 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1279 }
1280
1281 return -EINVAL;
1282}
1283
1284static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1285 int prio, char *ppcnt_pl)
1286{
1287 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1288 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1289
1290 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1291 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1292}
1293
1294static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1295 struct rtnl_link_stats64 *stats)
1296{
1297 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1298 int err;
1299
1300 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1301 0, ppcnt_pl);
1302 if (err)
1303 goto out;
1304
1305 stats->tx_packets =
1306 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1307 stats->rx_packets =
1308 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1309 stats->tx_bytes =
1310 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1311 stats->rx_bytes =
1312 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1313 stats->multicast =
1314 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1315
1316 stats->rx_crc_errors =
1317 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1318 stats->rx_frame_errors =
1319 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1320
1321 stats->rx_length_errors = (
1322 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1323 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1324 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1325
1326 stats->rx_errors = (stats->rx_crc_errors +
1327 stats->rx_frame_errors + stats->rx_length_errors);
1328
1329out:
1330 return err;
1331}
1332
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001333static void
1334mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1335 struct mlxsw_sp_port_xstats *xstats)
1336{
1337 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1338 int err, i;
1339
1340 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1341 ppcnt_pl);
1342 if (!err)
1343 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1344
1345 for (i = 0; i < TC_MAX_QUEUE; i++) {
1346 err = mlxsw_sp_port_get_stats_raw(dev,
1347 MLXSW_REG_PPCNT_TC_CONG_TC,
1348 i, ppcnt_pl);
1349 if (!err)
1350 xstats->wred_drop[i] =
1351 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1352
1353 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1354 i, ppcnt_pl);
1355 if (err)
1356 continue;
1357
1358 xstats->backlog[i] =
1359 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1360 xstats->tail_drop[i] =
1361 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1362 }
1363}
1364
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001365static void update_stats_cache(struct work_struct *work)
1366{
1367 struct mlxsw_sp_port *mlxsw_sp_port =
1368 container_of(work, struct mlxsw_sp_port,
Nogah Frankel9deef432017-10-26 10:55:32 +02001369 periodic_hw_stats.update_dw.work);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001370
1371 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1372 goto out;
1373
1374 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
Nogah Frankel9deef432017-10-26 10:55:32 +02001375 &mlxsw_sp_port->periodic_hw_stats.stats);
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001376 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1377 &mlxsw_sp_port->periodic_hw_stats.xstats);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001378
1379out:
Nogah Frankel9deef432017-10-26 10:55:32 +02001380 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001381 MLXSW_HW_STATS_UPDATE_TIME);
1382}
1383
1384/* Return the stats from a cache that is updated periodically,
1385 * as this function might get called in an atomic context.
1386 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001387static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001388mlxsw_sp_port_get_stats64(struct net_device *dev,
1389 struct rtnl_link_stats64 *stats)
1390{
1391 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1392
Nogah Frankel9deef432017-10-26 10:55:32 +02001393 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001394}
1395
Jiri Pirko93cd0812017-04-18 16:55:35 +02001396static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1397 u16 vid_begin, u16 vid_end,
1398 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001399{
1400 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1401 char *spvm_pl;
1402 int err;
1403
1404 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1405 if (!spvm_pl)
1406 return -ENOMEM;
1407
1408 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1409 vid_end, is_member, untagged);
1410 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1411 kfree(spvm_pl);
1412 return err;
1413}
1414
Jiri Pirko93cd0812017-04-18 16:55:35 +02001415int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1416 u16 vid_end, bool is_member, bool untagged)
1417{
1418 u16 vid, vid_e;
1419 int err;
1420
1421 for (vid = vid_begin; vid <= vid_end;
1422 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1423 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1424 vid_end);
1425
1426 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1427 is_member, untagged);
1428 if (err)
1429 return err;
1430 }
1431
1432 return 0;
1433}
1434
Ido Schimmelc57529e2017-05-26 08:37:31 +02001435static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001436{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001437 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001438
Ido Schimmelc57529e2017-05-26 08:37:31 +02001439 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1440 &mlxsw_sp_port->vlans_list, list)
1441 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001442}
1443
Ido Schimmel31a08a52017-05-26 08:37:26 +02001444static struct mlxsw_sp_port_vlan *
1445mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1446{
1447 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001448 bool untagged = vid == 1;
1449 int err;
1450
1451 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1452 if (err)
1453 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001454
1455 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001456 if (!mlxsw_sp_port_vlan) {
1457 err = -ENOMEM;
1458 goto err_port_vlan_alloc;
1459 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02001460
1461 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1462 mlxsw_sp_port_vlan->vid = vid;
1463 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1464
1465 return mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001466
1467err_port_vlan_alloc:
1468 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1469 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001470}
1471
1472static void
1473mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1474{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001475 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1476 u16 vid = mlxsw_sp_port_vlan->vid;
Ido Schimmel7cbecf22017-05-26 08:37:28 +02001477
Ido Schimmel31a08a52017-05-26 08:37:26 +02001478 list_del(&mlxsw_sp_port_vlan->list);
1479 kfree(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001480 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1481}
1482
1483struct mlxsw_sp_port_vlan *
1484mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1485{
1486 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1487
1488 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1489 if (mlxsw_sp_port_vlan)
1490 return mlxsw_sp_port_vlan;
1491
1492 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1493}
1494
1495void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1496{
Ido Schimmela1107482017-05-26 08:37:39 +02001497 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1498
Ido Schimmelc57529e2017-05-26 08:37:31 +02001499 if (mlxsw_sp_port_vlan->bridge_port)
1500 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
Ido Schimmela1107482017-05-26 08:37:39 +02001501 else if (fid)
1502 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001503
1504 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001505}
1506
Ido Schimmel05978482016-08-17 16:39:30 +02001507static int mlxsw_sp_port_add_vid(struct net_device *dev,
1508 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001509{
1510 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001511
1512 /* VLAN 0 is added to HW filter when device goes up, but it is
1513 * reserved in our case, so simply return.
1514 */
1515 if (!vid)
1516 return 0;
1517
Ido Schimmelc57529e2017-05-26 08:37:31 +02001518 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001519}
1520
Ido Schimmel32d863f2016-07-02 11:00:10 +02001521static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1522 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001523{
1524 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001525 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001526
1527 /* VLAN 0 is removed from HW filter when device goes down, but
1528 * it is reserved in our case, so simply return.
1529 */
1530 if (!vid)
1531 return 0;
1532
Ido Schimmel31a08a52017-05-26 08:37:26 +02001533 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001534 if (!mlxsw_sp_port_vlan)
Ido Schimmel31a08a52017-05-26 08:37:26 +02001535 return 0;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001536 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001537
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001538 return 0;
1539}
1540
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001541static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1542 size_t len)
1543{
1544 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +02001545 u8 module = mlxsw_sp_port->mapping.module;
1546 u8 width = mlxsw_sp_port->mapping.width;
1547 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001548 int err;
1549
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001550 if (!mlxsw_sp_port->split)
1551 err = snprintf(name, len, "p%d", module + 1);
1552 else
1553 err = snprintf(name, len, "p%ds%d", module + 1,
1554 lane / width);
1555
1556 if (err >= len)
1557 return -EINVAL;
1558
1559 return 0;
1560}
1561
Yotam Gigi763b4b72016-07-21 12:03:17 +02001562static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001563mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1564 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001565 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1566
1567 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1568 if (mall_tc_entry->cookie == cookie)
1569 return mall_tc_entry;
1570
1571 return NULL;
1572}
1573
1574static int
1575mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001576 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001577 const struct tc_action *a,
1578 bool ingress)
1579{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001580 enum mlxsw_sp_span_type span_type;
1581 struct mlxsw_sp_port *to_port;
1582 struct net_device *to_dev;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001583
Cong Wang9f8a7392017-12-05 16:17:26 -08001584 to_dev = tcf_mirred_dev(a);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001585 if (!to_dev) {
1586 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1587 return -EINVAL;
1588 }
1589
1590 if (!mlxsw_sp_port_dev_check(to_dev)) {
1591 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
Yotam Gigie915ac62017-01-09 11:25:48 +01001592 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001593 }
1594 to_port = netdev_priv(to_dev);
1595
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001596 mirror->to_local_port = to_port->local_port;
1597 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001598 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +01001599 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type,
1600 true);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001601}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001602
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001603static void
1604mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1605 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1606{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001607 enum mlxsw_sp_span_type span_type;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001608
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001609 span_type = mirror->ingress ?
1610 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +01001611 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->to_local_port,
1612 span_type, true);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001613}
1614
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001615static int
1616mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1617 struct tc_cls_matchall_offload *cls,
1618 const struct tc_action *a,
1619 bool ingress)
1620{
1621 int err;
1622
1623 if (!mlxsw_sp_port->sample)
1624 return -EOPNOTSUPP;
1625 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1626 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1627 return -EEXIST;
1628 }
1629 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1630 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1631 return -EOPNOTSUPP;
1632 }
1633
1634 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1635 tcf_sample_psample_group(a));
1636 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1637 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1638 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1639
1640 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1641 if (err)
1642 goto err_port_sample_set;
1643 return 0;
1644
1645err_port_sample_set:
1646 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1647 return err;
1648}
1649
1650static void
1651mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1652{
1653 if (!mlxsw_sp_port->sample)
1654 return;
1655
1656 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1657 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1658}
1659
Yotam Gigi763b4b72016-07-21 12:03:17 +02001660static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001661 struct tc_cls_matchall_offload *f,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001662 bool ingress)
1663{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001664 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001665 __be16 protocol = f->common.protocol;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001666 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001667 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001668 int err;
1669
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001670 if (!tcf_exts_has_one_action(f->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001671 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001672 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001673 }
1674
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001675 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1676 if (!mall_tc_entry)
1677 return -ENOMEM;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001678 mall_tc_entry->cookie = f->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001679
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001680 tcf_exts_to_list(f->exts, &actions);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001681 a = list_first_entry(&actions, struct tc_action, list);
1682
1683 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1684 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1685
1686 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1687 mirror = &mall_tc_entry->mirror;
1688 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1689 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001690 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1691 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001692 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001693 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001694 } else {
1695 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001696 }
1697
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001698 if (err)
1699 goto err_add_action;
1700
1701 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001702 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001703
1704err_add_action:
1705 kfree(mall_tc_entry);
1706 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001707}
1708
1709static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001710 struct tc_cls_matchall_offload *f)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001711{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001712 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001713
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001714 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001715 f->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001716 if (!mall_tc_entry) {
1717 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1718 return;
1719 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001720 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001721
1722 switch (mall_tc_entry->type) {
1723 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001724 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1725 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001726 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001727 case MLXSW_SP_PORT_MALL_SAMPLE:
1728 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1729 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001730 default:
1731 WARN_ON(1);
1732 }
1733
Yotam Gigi763b4b72016-07-21 12:03:17 +02001734 kfree(mall_tc_entry);
1735}
1736
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001737static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001738 struct tc_cls_matchall_offload *f,
1739 bool ingress)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001740{
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001741 if (f->common.chain_index)
Jiri Pirkoa5fcf8a2017-06-06 17:00:16 +02001742 return -EOPNOTSUPP;
1743
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001744 switch (f->command) {
1745 case TC_CLSMATCHALL_REPLACE:
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001746 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001747 ingress);
1748 case TC_CLSMATCHALL_DESTROY:
1749 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1750 return 0;
1751 default:
1752 return -EOPNOTSUPP;
1753 }
1754}
1755
1756static int
Jiri Pirko3aaff322018-01-17 11:46:56 +01001757mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1758 struct tc_cls_flower_offload *f)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001759{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001760 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1761
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001762 switch (f->command) {
1763 case TC_CLSFLOWER_REPLACE:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001764 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001765 case TC_CLSFLOWER_DESTROY:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001766 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001767 return 0;
1768 case TC_CLSFLOWER_STATS:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001769 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001770 default:
1771 return -EOPNOTSUPP;
1772 }
1773}
1774
Jiri Pirko3aaff322018-01-17 11:46:56 +01001775static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1776 void *type_data,
1777 void *cb_priv, bool ingress)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001778{
1779 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1780
1781 switch (type) {
1782 case TC_SETUP_CLSMATCHALL:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001783 if (!tc_can_offload(mlxsw_sp_port->dev))
1784 return -EOPNOTSUPP;
1785
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001786 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1787 ingress);
1788 case TC_SETUP_CLSFLOWER:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001789 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001790 default:
1791 return -EOPNOTSUPP;
1792 }
1793}
1794
Jiri Pirko3aaff322018-01-17 11:46:56 +01001795static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1796 void *type_data,
1797 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001798{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001799 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1800 cb_priv, true);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001801}
1802
Jiri Pirko3aaff322018-01-17 11:46:56 +01001803static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1804 void *type_data,
1805 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001806{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001807 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1808 cb_priv, false);
1809}
1810
1811static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1812 void *type_data, void *cb_priv)
1813{
1814 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1815
1816 switch (type) {
1817 case TC_SETUP_CLSMATCHALL:
1818 return 0;
1819 case TC_SETUP_CLSFLOWER:
1820 if (mlxsw_sp_acl_block_disabled(acl_block))
1821 return -EOPNOTSUPP;
1822
1823 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1824 default:
1825 return -EOPNOTSUPP;
1826 }
1827}
1828
1829static int
1830mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1831 struct tcf_block *block, bool ingress)
1832{
1833 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1834 struct mlxsw_sp_acl_block *acl_block;
1835 struct tcf_block_cb *block_cb;
1836 int err;
1837
1838 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1839 mlxsw_sp);
1840 if (!block_cb) {
1841 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1842 if (!acl_block)
1843 return -ENOMEM;
1844 block_cb = __tcf_block_cb_register(block,
1845 mlxsw_sp_setup_tc_block_cb_flower,
1846 mlxsw_sp, acl_block);
1847 if (IS_ERR(block_cb)) {
1848 err = PTR_ERR(block_cb);
1849 goto err_cb_register;
1850 }
1851 } else {
1852 acl_block = tcf_block_cb_priv(block_cb);
1853 }
1854 tcf_block_cb_incref(block_cb);
1855 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1856 mlxsw_sp_port, ingress);
1857 if (err)
1858 goto err_block_bind;
1859
1860 if (ingress)
1861 mlxsw_sp_port->ing_acl_block = acl_block;
1862 else
1863 mlxsw_sp_port->eg_acl_block = acl_block;
1864
1865 return 0;
1866
1867err_block_bind:
1868 if (!tcf_block_cb_decref(block_cb)) {
1869 __tcf_block_cb_unregister(block_cb);
1870err_cb_register:
1871 mlxsw_sp_acl_block_destroy(acl_block);
1872 }
1873 return err;
1874}
1875
1876static void
1877mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1878 struct tcf_block *block, bool ingress)
1879{
1880 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1881 struct mlxsw_sp_acl_block *acl_block;
1882 struct tcf_block_cb *block_cb;
1883 int err;
1884
1885 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1886 mlxsw_sp);
1887 if (!block_cb)
1888 return;
1889
1890 if (ingress)
1891 mlxsw_sp_port->ing_acl_block = NULL;
1892 else
1893 mlxsw_sp_port->eg_acl_block = NULL;
1894
1895 acl_block = tcf_block_cb_priv(block_cb);
1896 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1897 mlxsw_sp_port, ingress);
1898 if (!err && !tcf_block_cb_decref(block_cb)) {
1899 __tcf_block_cb_unregister(block_cb);
1900 mlxsw_sp_acl_block_destroy(acl_block);
1901 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001902}
1903
1904static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1905 struct tc_block_offload *f)
1906{
1907 tc_setup_cb_t *cb;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001908 bool ingress;
1909 int err;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001910
Jiri Pirko3aaff322018-01-17 11:46:56 +01001911 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1912 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1913 ingress = true;
1914 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1915 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1916 ingress = false;
1917 } else {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001918 return -EOPNOTSUPP;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001919 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001920
1921 switch (f->command) {
1922 case TC_BLOCK_BIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001923 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1924 mlxsw_sp_port);
1925 if (err)
1926 return err;
1927 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
1928 f->block, ingress);
1929 if (err) {
1930 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1931 return err;
1932 }
1933 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001934 case TC_BLOCK_UNBIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001935 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1936 f->block, ingress);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001937 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1938 return 0;
1939 default:
1940 return -EOPNOTSUPP;
1941 }
1942}
1943
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001944static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
Jiri Pirkode4784c2017-08-07 10:15:32 +02001945 void *type_data)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001946{
1947 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1948
Jiri Pirko2572ac52017-08-07 10:15:17 +02001949 switch (type) {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001950 case TC_SETUP_BLOCK:
1951 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
Nogah Frankel96f17e02017-11-06 07:23:45 +01001952 case TC_SETUP_QDISC_RED:
1953 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
Nogah Frankel46a36152018-01-14 12:33:16 +01001954 case TC_SETUP_QDISC_PRIO:
1955 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
Jiri Pirko2572ac52017-08-07 10:15:17 +02001956 default:
1957 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001958 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001959}
1960
Jiri Pirko9454d932017-12-06 09:41:12 +01001961
1962static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1963{
1964 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1965
Jiri Pirko3aaff322018-01-17 11:46:56 +01001966 if (!enable) {
1967 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1968 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1969 !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1970 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1971 return -EINVAL;
1972 }
1973 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1974 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1975 } else {
1976 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1977 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
Jiri Pirko9454d932017-12-06 09:41:12 +01001978 }
1979 return 0;
1980}
1981
1982typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1983
1984static int mlxsw_sp_handle_feature(struct net_device *dev,
1985 netdev_features_t wanted_features,
1986 netdev_features_t feature,
1987 mlxsw_sp_feature_handler feature_handler)
1988{
1989 netdev_features_t changes = wanted_features ^ dev->features;
1990 bool enable = !!(wanted_features & feature);
1991 int err;
1992
1993 if (!(changes & feature))
1994 return 0;
1995
1996 err = feature_handler(dev, enable);
1997 if (err) {
1998 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1999 enable ? "Enable" : "Disable", &feature, err);
2000 return err;
2001 }
2002
2003 if (enable)
2004 dev->features |= feature;
2005 else
2006 dev->features &= ~feature;
2007
2008 return 0;
2009}
2010static int mlxsw_sp_set_features(struct net_device *dev,
2011 netdev_features_t features)
2012{
2013 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
2014 mlxsw_sp_feature_hw_tc);
2015}
2016
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002017static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
2018 .ndo_open = mlxsw_sp_port_open,
2019 .ndo_stop = mlxsw_sp_port_stop,
2020 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02002021 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01002022 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002023 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
2024 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
2025 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002026 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
2027 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002028 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
2029 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02002030 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko9454d932017-12-06 09:41:12 +01002031 .ndo_set_features = mlxsw_sp_set_features,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002032};
2033
2034static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
2035 struct ethtool_drvinfo *drvinfo)
2036{
2037 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2038 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2039
2040 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
2041 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
2042 sizeof(drvinfo->version));
2043 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
2044 "%d.%d.%d",
2045 mlxsw_sp->bus_info->fw_rev.major,
2046 mlxsw_sp->bus_info->fw_rev.minor,
2047 mlxsw_sp->bus_info->fw_rev.subminor);
2048 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
2049 sizeof(drvinfo->bus_info));
2050}
2051
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002052static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
2053 struct ethtool_pauseparam *pause)
2054{
2055 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2056
2057 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
2058 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
2059}
2060
2061static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
2062 struct ethtool_pauseparam *pause)
2063{
2064 char pfcc_pl[MLXSW_REG_PFCC_LEN];
2065
2066 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
2067 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
2068 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
2069
2070 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
2071 pfcc_pl);
2072}
2073
2074static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
2075 struct ethtool_pauseparam *pause)
2076{
2077 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2078 bool pause_en = pause->tx_pause || pause->rx_pause;
2079 int err;
2080
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02002081 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
2082 netdev_err(dev, "PFC already enabled on port\n");
2083 return -EINVAL;
2084 }
2085
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002086 if (pause->autoneg) {
2087 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
2088 return -EINVAL;
2089 }
2090
2091 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
2092 if (err) {
2093 netdev_err(dev, "Failed to configure port's headroom\n");
2094 return err;
2095 }
2096
2097 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
2098 if (err) {
2099 netdev_err(dev, "Failed to set PAUSE parameters\n");
2100 goto err_port_pause_configure;
2101 }
2102
2103 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
2104 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
2105
2106 return 0;
2107
2108err_port_pause_configure:
2109 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
2110 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
2111 return err;
2112}
2113
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002114struct mlxsw_sp_port_hw_stats {
2115 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02002116 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01002117 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002118};
2119
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002120static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002121 {
2122 .str = "a_frames_transmitted_ok",
2123 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
2124 },
2125 {
2126 .str = "a_frames_received_ok",
2127 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
2128 },
2129 {
2130 .str = "a_frame_check_sequence_errors",
2131 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
2132 },
2133 {
2134 .str = "a_alignment_errors",
2135 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
2136 },
2137 {
2138 .str = "a_octets_transmitted_ok",
2139 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
2140 },
2141 {
2142 .str = "a_octets_received_ok",
2143 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
2144 },
2145 {
2146 .str = "a_multicast_frames_xmitted_ok",
2147 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
2148 },
2149 {
2150 .str = "a_broadcast_frames_xmitted_ok",
2151 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
2152 },
2153 {
2154 .str = "a_multicast_frames_received_ok",
2155 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
2156 },
2157 {
2158 .str = "a_broadcast_frames_received_ok",
2159 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
2160 },
2161 {
2162 .str = "a_in_range_length_errors",
2163 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
2164 },
2165 {
2166 .str = "a_out_of_range_length_field",
2167 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
2168 },
2169 {
2170 .str = "a_frame_too_long_errors",
2171 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
2172 },
2173 {
2174 .str = "a_symbol_error_during_carrier",
2175 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
2176 },
2177 {
2178 .str = "a_mac_control_frames_transmitted",
2179 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
2180 },
2181 {
2182 .str = "a_mac_control_frames_received",
2183 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
2184 },
2185 {
2186 .str = "a_unsupported_opcodes_received",
2187 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
2188 },
2189 {
2190 .str = "a_pause_mac_ctrl_frames_received",
2191 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
2192 },
2193 {
2194 .str = "a_pause_mac_ctrl_frames_xmitted",
2195 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
2196 },
2197};
2198
2199#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
2200
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002201static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
2202 {
2203 .str = "rx_octets_prio",
2204 .getter = mlxsw_reg_ppcnt_rx_octets_get,
2205 },
2206 {
2207 .str = "rx_frames_prio",
2208 .getter = mlxsw_reg_ppcnt_rx_frames_get,
2209 },
2210 {
2211 .str = "tx_octets_prio",
2212 .getter = mlxsw_reg_ppcnt_tx_octets_get,
2213 },
2214 {
2215 .str = "tx_frames_prio",
2216 .getter = mlxsw_reg_ppcnt_tx_frames_get,
2217 },
2218 {
2219 .str = "rx_pause_prio",
2220 .getter = mlxsw_reg_ppcnt_rx_pause_get,
2221 },
2222 {
2223 .str = "rx_pause_duration_prio",
2224 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2225 },
2226 {
2227 .str = "tx_pause_prio",
2228 .getter = mlxsw_reg_ppcnt_tx_pause_get,
2229 },
2230 {
2231 .str = "tx_pause_duration_prio",
2232 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2233 },
2234};
2235
2236#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2237
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002238static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2239 {
2240 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01002241 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2242 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002243 },
2244 {
2245 .str = "tc_no_buffer_discard_uc_tc",
2246 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2247 },
2248};
2249
2250#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2251
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002252#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002253 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
2254 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002255 IEEE_8021QAZ_MAX_TCS)
2256
2257static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2258{
2259 int i;
2260
2261 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2262 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2263 mlxsw_sp_port_hw_prio_stats[i].str, prio);
2264 *p += ETH_GSTRING_LEN;
2265 }
2266}
2267
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002268static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2269{
2270 int i;
2271
2272 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2273 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2274 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2275 *p += ETH_GSTRING_LEN;
2276 }
2277}
2278
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002279static void mlxsw_sp_port_get_strings(struct net_device *dev,
2280 u32 stringset, u8 *data)
2281{
2282 u8 *p = data;
2283 int i;
2284
2285 switch (stringset) {
2286 case ETH_SS_STATS:
2287 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2288 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2289 ETH_GSTRING_LEN);
2290 p += ETH_GSTRING_LEN;
2291 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002292
2293 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2294 mlxsw_sp_port_get_prio_strings(&p, i);
2295
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002296 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2297 mlxsw_sp_port_get_tc_strings(&p, i);
2298
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002299 break;
2300 }
2301}
2302
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002303static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2304 enum ethtool_phys_id_state state)
2305{
2306 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2307 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2308 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2309 bool active;
2310
2311 switch (state) {
2312 case ETHTOOL_ID_ACTIVE:
2313 active = true;
2314 break;
2315 case ETHTOOL_ID_INACTIVE:
2316 active = false;
2317 break;
2318 default:
2319 return -EOPNOTSUPP;
2320 }
2321
2322 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2323 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2324}
2325
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002326static int
2327mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2328 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2329{
2330 switch (grp) {
2331 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2332 *p_hw_stats = mlxsw_sp_port_hw_stats;
2333 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2334 break;
2335 case MLXSW_REG_PPCNT_PRIO_CNT:
2336 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2337 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2338 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002339 case MLXSW_REG_PPCNT_TC_CNT:
2340 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2341 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2342 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002343 default:
2344 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002345 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002346 }
2347 return 0;
2348}
2349
2350static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2351 enum mlxsw_reg_ppcnt_grp grp, int prio,
2352 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002353{
Ido Schimmel18281f22017-03-24 08:02:51 +01002354 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2355 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002356 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002357 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002358 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002359 int err;
2360
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002361 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2362 if (err)
2363 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002364 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002365 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002366 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002367 if (!hw_stats[i].cells_bytes)
2368 continue;
2369 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2370 data[data_index + i]);
2371 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002372}
2373
2374static void mlxsw_sp_port_get_stats(struct net_device *dev,
2375 struct ethtool_stats *stats, u64 *data)
2376{
2377 int i, data_index = 0;
2378
2379 /* IEEE 802.3 Counters */
2380 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2381 data, data_index);
2382 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2383
2384 /* Per-Priority Counters */
2385 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2386 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2387 data, data_index);
2388 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2389 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002390
2391 /* Per-TC Counters */
2392 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2393 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2394 data, data_index);
2395 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2396 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002397}
2398
2399static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2400{
2401 switch (sset) {
2402 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002403 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002404 default:
2405 return -EOPNOTSUPP;
2406 }
2407}
2408
2409struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002410 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002411 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002412 u32 speed;
2413};
2414
2415static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2416 {
2417 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002418 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2419 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002420 },
2421 {
2422 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2423 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002424 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2425 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002426 },
2427 {
2428 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002429 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2430 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002431 },
2432 {
2433 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2434 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002435 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2436 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002437 },
2438 {
2439 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2440 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2441 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2442 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002443 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2444 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002445 },
2446 {
2447 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002448 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2449 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002450 },
2451 {
2452 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002453 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2454 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002455 },
2456 {
2457 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002458 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2459 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002460 },
2461 {
2462 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002463 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2464 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002465 },
2466 {
2467 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002468 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2469 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002470 },
2471 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002472 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2473 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2474 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002475 },
2476 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002477 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2478 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2479 .speed = SPEED_25000,
2480 },
2481 {
2482 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2483 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2484 .speed = SPEED_25000,
2485 },
2486 {
2487 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2488 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2489 .speed = SPEED_25000,
2490 },
2491 {
2492 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2493 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2494 .speed = SPEED_50000,
2495 },
2496 {
2497 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2498 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2499 .speed = SPEED_50000,
2500 },
2501 {
2502 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2503 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2504 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002505 },
2506 {
2507 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002508 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2509 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002510 },
2511 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002512 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2513 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2514 .speed = SPEED_56000,
2515 },
2516 {
2517 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2518 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2519 .speed = SPEED_56000,
2520 },
2521 {
2522 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2523 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2524 .speed = SPEED_56000,
2525 },
2526 {
2527 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2528 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2529 .speed = SPEED_100000,
2530 },
2531 {
2532 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2533 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2534 .speed = SPEED_100000,
2535 },
2536 {
2537 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2538 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2539 .speed = SPEED_100000,
2540 },
2541 {
2542 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2543 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2544 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002545 },
2546};
2547
2548#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2549
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002550static void
2551mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2552 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002553{
2554 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2555 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2556 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2557 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2558 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2559 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002560 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002561
2562 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2563 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2564 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2565 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2566 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002567 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002568}
2569
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002570static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002571{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002572 int i;
2573
2574 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2575 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002576 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2577 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002578 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002579}
2580
2581static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002582 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002583{
2584 u32 speed = SPEED_UNKNOWN;
2585 u8 duplex = DUPLEX_UNKNOWN;
2586 int i;
2587
2588 if (!carrier_ok)
2589 goto out;
2590
2591 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2592 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2593 speed = mlxsw_sp_port_link_mode[i].speed;
2594 duplex = DUPLEX_FULL;
2595 break;
2596 }
2597 }
2598out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002599 cmd->base.speed = speed;
2600 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002601}
2602
2603static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2604{
2605 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2606 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2607 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2608 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2609 return PORT_FIBRE;
2610
2611 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2612 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2613 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2614 return PORT_DA;
2615
2616 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2617 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2618 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2619 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2620 return PORT_NONE;
2621
2622 return PORT_OTHER;
2623}
2624
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002625static u32
2626mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002627{
2628 u32 ptys_proto = 0;
2629 int i;
2630
2631 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002632 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2633 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002634 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2635 }
2636 return ptys_proto;
2637}
2638
2639static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2640{
2641 u32 ptys_proto = 0;
2642 int i;
2643
2644 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2645 if (speed == mlxsw_sp_port_link_mode[i].speed)
2646 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2647 }
2648 return ptys_proto;
2649}
2650
Ido Schimmel18f1e702016-02-26 17:32:31 +01002651static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2652{
2653 u32 ptys_proto = 0;
2654 int i;
2655
2656 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2657 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2658 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2659 }
2660 return ptys_proto;
2661}
2662
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002663static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2664 struct ethtool_link_ksettings *cmd)
2665{
2666 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2667 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2668 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2669
2670 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2671 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2672}
2673
2674static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2675 struct ethtool_link_ksettings *cmd)
2676{
2677 if (!autoneg)
2678 return;
2679
2680 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2681 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2682}
2683
2684static void
2685mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2686 struct ethtool_link_ksettings *cmd)
2687{
2688 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2689 return;
2690
2691 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2692 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2693}
2694
2695static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2696 struct ethtool_link_ksettings *cmd)
2697{
2698 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2699 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2700 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2701 char ptys_pl[MLXSW_REG_PTYS_LEN];
2702 u8 autoneg_status;
2703 bool autoneg;
2704 int err;
2705
2706 autoneg = mlxsw_sp_port->link.autoneg;
Elad Raz401c8b42016-10-28 21:35:52 +02002707 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002708 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2709 if (err)
2710 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002711 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2712 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002713
2714 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2715
2716 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2717
2718 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2719 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2720 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2721
2722 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2723 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2724 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2725 cmd);
2726
2727 return 0;
2728}
2729
2730static int
2731mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2732 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002733{
2734 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2735 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2736 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002737 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002738 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002739 int err;
2740
Elad Raz401c8b42016-10-28 21:35:52 +02002741 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002742 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002743 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002744 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002745 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002746
2747 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2748 eth_proto_new = autoneg ?
2749 mlxsw_sp_to_ptys_advert_link(cmd) :
2750 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002751
2752 eth_proto_new = eth_proto_new & eth_proto_cap;
2753 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002754 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002755 return -EINVAL;
2756 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002757
Elad Raz401c8b42016-10-28 21:35:52 +02002758 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2759 eth_proto_new);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002760 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002761 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002762 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002763
Ido Schimmel6277d462016-07-15 11:14:58 +02002764 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002765 return 0;
2766
Ido Schimmel0c83f882016-09-12 13:26:23 +02002767 mlxsw_sp_port->link.autoneg = autoneg;
2768
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002769 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2770 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002771
2772 return 0;
2773}
2774
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002775static int mlxsw_sp_flash_device(struct net_device *dev,
2776 struct ethtool_flash *flash)
2777{
2778 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2779 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2780 const struct firmware *firmware;
2781 int err;
2782
2783 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2784 return -EOPNOTSUPP;
2785
2786 dev_hold(dev);
2787 rtnl_unlock();
2788
2789 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2790 if (err)
2791 goto out;
2792 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2793 release_firmware(firmware);
2794out:
2795 rtnl_lock();
2796 dev_put(dev);
2797 return err;
2798}
2799
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002800#define MLXSW_SP_I2C_ADDR_LOW 0x50
2801#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2802#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002803
2804static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2805 u16 offset, u16 size, void *data,
2806 unsigned int *p_read_size)
2807{
2808 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2809 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2810 char mcia_pl[MLXSW_REG_MCIA_LEN];
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002811 u16 i2c_addr;
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002812 int status;
2813 int err;
2814
2815 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002816
2817 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2818 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2819 /* Cross pages read, read until offset 256 in low page */
2820 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2821
2822 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2823 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2824 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2825 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2826 }
2827
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002828 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002829 0, 0, offset, size, i2c_addr);
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002830
2831 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2832 if (err)
2833 return err;
2834
2835 status = mlxsw_reg_mcia_status_get(mcia_pl);
2836 if (status)
2837 return -EIO;
2838
2839 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2840 memcpy(data, eeprom_tmp, size);
2841 *p_read_size = size;
2842
2843 return 0;
2844}
2845
2846enum mlxsw_sp_eeprom_module_info_rev_id {
2847 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2848 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2849 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2850};
2851
2852enum mlxsw_sp_eeprom_module_info_id {
2853 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2854 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2855 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2856 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2857};
2858
2859enum mlxsw_sp_eeprom_module_info {
2860 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2861 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2862 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2863};
2864
2865static int mlxsw_sp_get_module_info(struct net_device *netdev,
2866 struct ethtool_modinfo *modinfo)
2867{
2868 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2869 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2870 u8 module_rev_id, module_id;
2871 unsigned int read_size;
2872 int err;
2873
2874 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2875 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2876 module_info, &read_size);
2877 if (err)
2878 return err;
2879
2880 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2881 return -EIO;
2882
2883 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2884 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2885
2886 switch (module_id) {
2887 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2888 modinfo->type = ETH_MODULE_SFF_8436;
2889 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2890 break;
2891 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2892 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2893 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2894 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2895 modinfo->type = ETH_MODULE_SFF_8636;
2896 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2897 } else {
2898 modinfo->type = ETH_MODULE_SFF_8436;
2899 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2900 }
2901 break;
2902 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2903 modinfo->type = ETH_MODULE_SFF_8472;
2904 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2905 break;
2906 default:
2907 return -EINVAL;
2908 }
2909
2910 return 0;
2911}
2912
2913static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2914 struct ethtool_eeprom *ee,
2915 u8 *data)
2916{
2917 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2918 int offset = ee->offset;
2919 unsigned int read_size;
2920 int i = 0;
2921 int err;
2922
2923 if (!ee->len)
2924 return -EINVAL;
2925
2926 memset(data, 0, ee->len);
2927
2928 while (i < ee->len) {
2929 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2930 ee->len - i, data + i,
2931 &read_size);
2932 if (err) {
2933 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2934 return err;
2935 }
2936
2937 i += read_size;
2938 offset += read_size;
2939 }
2940
2941 return 0;
2942}
2943
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002944static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2945 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2946 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002947 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2948 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002949 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002950 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002951 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2952 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002953 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2954 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002955 .flash_device = mlxsw_sp_flash_device,
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002956 .get_module_info = mlxsw_sp_get_module_info,
2957 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002958};
2959
Ido Schimmel18f1e702016-02-26 17:32:31 +01002960static int
2961mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2962{
2963 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2964 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2965 char ptys_pl[MLXSW_REG_PTYS_LEN];
2966 u32 eth_proto_admin;
2967
2968 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002969 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2970 eth_proto_admin);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002971 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2972}
2973
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002974int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2975 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2976 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002977{
2978 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2979 char qeec_pl[MLXSW_REG_QEEC_LEN];
2980
2981 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2982 next_index);
2983 mlxsw_reg_qeec_de_set(qeec_pl, true);
2984 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2985 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2986 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2987}
2988
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002989int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2990 enum mlxsw_reg_qeec_hr hr, u8 index,
2991 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002992{
2993 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2994 char qeec_pl[MLXSW_REG_QEEC_LEN];
2995
2996 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2997 next_index);
2998 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2999 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
3000 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3001}
3002
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02003003int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
3004 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02003005{
3006 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3007 char qtct_pl[MLXSW_REG_QTCT_LEN];
3008
3009 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
3010 tclass);
3011 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
3012}
3013
3014static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
3015{
3016 int err, i;
3017
3018 /* Setup the elements hierarcy, so that each TC is linked to
3019 * one subgroup, which are all member in the same group.
3020 */
3021 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3022 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
3023 0);
3024 if (err)
3025 return err;
3026 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3027 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3028 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
3029 0, false, 0);
3030 if (err)
3031 return err;
3032 }
3033 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3034 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3035 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
3036 false, 0);
3037 if (err)
3038 return err;
3039 }
3040
3041 /* Make sure the max shaper is disabled in all hierarcies that
3042 * support it.
3043 */
3044 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3045 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
3046 MLXSW_REG_QEEC_MAS_DIS);
3047 if (err)
3048 return err;
3049 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3050 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3051 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3052 i, 0,
3053 MLXSW_REG_QEEC_MAS_DIS);
3054 if (err)
3055 return err;
3056 }
3057 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3058 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3059 MLXSW_REG_QEEC_HIERARCY_TC,
3060 i, i,
3061 MLXSW_REG_QEEC_MAS_DIS);
3062 if (err)
3063 return err;
3064 }
3065
3066 /* Map all priorities to traffic class 0. */
3067 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3068 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
3069 if (err)
3070 return err;
3071 }
3072
3073 return 0;
3074}
3075
Ido Schimmel5b153852017-06-08 08:47:44 +02003076static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
3077 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003078{
Ido Schimmelc57529e2017-05-26 08:37:31 +02003079 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003080 struct mlxsw_sp_port *mlxsw_sp_port;
3081 struct net_device *dev;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003082 int err;
3083
Ido Schimmel5b153852017-06-08 08:47:44 +02003084 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
3085 if (err) {
3086 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
3087 local_port);
3088 return err;
3089 }
3090
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003091 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
Ido Schimmel5b153852017-06-08 08:47:44 +02003092 if (!dev) {
3093 err = -ENOMEM;
3094 goto err_alloc_etherdev;
3095 }
Jiri Pirkof20a91f2016-10-27 15:13:00 +02003096 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003097 mlxsw_sp_port = netdev_priv(dev);
3098 mlxsw_sp_port->dev = dev;
3099 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
3100 mlxsw_sp_port->local_port = local_port;
Ido Schimmelc57529e2017-05-26 08:37:31 +02003101 mlxsw_sp_port->pvid = 1;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003102 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02003103 mlxsw_sp_port->mapping.module = module;
3104 mlxsw_sp_port->mapping.width = width;
3105 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02003106 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02003107 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02003108 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003109
3110 mlxsw_sp_port->pcpu_stats =
3111 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
3112 if (!mlxsw_sp_port->pcpu_stats) {
3113 err = -ENOMEM;
3114 goto err_alloc_stats;
3115 }
3116
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003117 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
3118 GFP_KERNEL);
3119 if (!mlxsw_sp_port->sample) {
3120 err = -ENOMEM;
3121 goto err_alloc_sample;
3122 }
3123
Nogah Frankel9deef432017-10-26 10:55:32 +02003124 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02003125 &update_stats_cache);
3126
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003127 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
3128 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
3129
Ido Schimmel2e915e02017-06-08 08:47:45 +02003130 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
Ido Schimmel5b153852017-06-08 08:47:44 +02003131 if (err) {
3132 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
3133 mlxsw_sp_port->local_port);
3134 goto err_port_module_map;
3135 }
3136
Ido Schimmel3247ff22016-09-08 08:16:02 +02003137 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
3138 if (err) {
3139 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
3140 mlxsw_sp_port->local_port);
3141 goto err_port_swid_set;
3142 }
3143
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003144 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
3145 if (err) {
3146 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
3147 mlxsw_sp_port->local_port);
3148 goto err_dev_addr_init;
3149 }
3150
3151 netif_carrier_off(dev);
3152
3153 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02003154 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
3155 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003156
Jarod Wilsond894be52016-10-20 13:55:16 -04003157 dev->min_mtu = 0;
3158 dev->max_mtu = ETH_MAX_MTU;
3159
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003160 /* Each packet needs to have a Tx header (metadata) on top all other
3161 * headers.
3162 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02003163 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003164
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003165 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
3166 if (err) {
3167 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
3168 mlxsw_sp_port->local_port);
3169 goto err_port_system_port_mapping_set;
3170 }
3171
Ido Schimmel18f1e702016-02-26 17:32:31 +01003172 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
3173 if (err) {
3174 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
3175 mlxsw_sp_port->local_port);
3176 goto err_port_speed_by_width_set;
3177 }
3178
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003179 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
3180 if (err) {
3181 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
3182 mlxsw_sp_port->local_port);
3183 goto err_port_mtu_set;
3184 }
3185
3186 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3187 if (err)
3188 goto err_port_admin_status_set;
3189
3190 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
3191 if (err) {
3192 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
3193 mlxsw_sp_port->local_port);
3194 goto err_port_buffers_init;
3195 }
3196
Ido Schimmel90183b92016-04-06 17:10:08 +02003197 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
3198 if (err) {
3199 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
3200 mlxsw_sp_port->local_port);
3201 goto err_port_ets_init;
3202 }
3203
Ido Schimmelf00817d2016-04-06 17:10:09 +02003204 /* ETS and buffers must be initialized before DCB. */
3205 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
3206 if (err) {
3207 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
3208 mlxsw_sp_port->local_port);
3209 goto err_port_dcb_init;
3210 }
3211
Ido Schimmela1107482017-05-26 08:37:39 +02003212 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
Ido Schimmel45a4a162017-05-16 19:38:35 +02003213 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003214 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
Ido Schimmel45a4a162017-05-16 19:38:35 +02003215 mlxsw_sp_port->local_port);
Ido Schimmela1107482017-05-26 08:37:39 +02003216 goto err_port_fids_init;
Ido Schimmel45a4a162017-05-16 19:38:35 +02003217 }
3218
Nogah Frankel371b4372018-01-10 14:59:57 +01003219 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
3220 if (err) {
3221 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
3222 mlxsw_sp_port->local_port);
3223 goto err_port_qdiscs_init;
3224 }
3225
Ido Schimmelc57529e2017-05-26 08:37:31 +02003226 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
3227 if (IS_ERR(mlxsw_sp_port_vlan)) {
3228 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
Ido Schimmel05978482016-08-17 16:39:30 +02003229 mlxsw_sp_port->local_port);
Wei Yongjund86fd112017-11-06 11:11:28 +00003230 err = PTR_ERR(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003231 goto err_port_vlan_get;
Ido Schimmel05978482016-08-17 16:39:30 +02003232 }
3233
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003234 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02003235 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003236 err = register_netdev(dev);
3237 if (err) {
3238 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3239 mlxsw_sp_port->local_port);
3240 goto err_register_netdev;
3241 }
3242
Elad Razd808c7e2016-10-28 21:35:57 +02003243 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3244 mlxsw_sp_port, dev, mlxsw_sp_port->split,
3245 module);
Nogah Frankel9deef432017-10-26 10:55:32 +02003246 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003247 return 0;
3248
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003249err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02003250 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02003251 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003252 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
3253err_port_vlan_get:
Nogah Frankel371b4372018-01-10 14:59:57 +01003254 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3255err_port_qdiscs_init:
Ido Schimmela1107482017-05-26 08:37:39 +02003256 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3257err_port_fids_init:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03003258 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02003259err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02003260err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003261err_port_buffers_init:
3262err_port_admin_status_set:
3263err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01003264err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003265err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003266err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02003267 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3268err_port_swid_set:
Ido Schimmel2e915e02017-06-08 08:47:45 +02003269 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Ido Schimmel5b153852017-06-08 08:47:44 +02003270err_port_module_map:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003271 kfree(mlxsw_sp_port->sample);
3272err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003273 free_percpu(mlxsw_sp_port->pcpu_stats);
3274err_alloc_stats:
3275 free_netdev(dev);
Ido Schimmel5b153852017-06-08 08:47:44 +02003276err_alloc_etherdev:
Jiri Pirko67963a32016-10-28 21:35:55 +02003277 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3278 return err;
3279}
3280
Ido Schimmel5b153852017-06-08 08:47:44 +02003281static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003282{
3283 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3284
Nogah Frankel9deef432017-10-26 10:55:32 +02003285 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02003286 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003287 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02003288 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02003289 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003290 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Nogah Frankel371b4372018-01-10 14:59:57 +01003291 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
Ido Schimmela1107482017-05-26 08:37:39 +02003292 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02003293 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01003294 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
Ido Schimmel2e915e02017-06-08 08:47:45 +02003295 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003296 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01003297 free_percpu(mlxsw_sp_port->pcpu_stats);
Ido Schimmel31a08a52017-05-26 08:37:26 +02003298 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003299 free_netdev(mlxsw_sp_port->dev);
Jiri Pirko67963a32016-10-28 21:35:55 +02003300 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3301}
3302
Jiri Pirkof83e2102016-10-28 21:35:49 +02003303static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3304{
3305 return mlxsw_sp->ports[local_port] != NULL;
3306}
3307
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003308static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3309{
3310 int i;
3311
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003312 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003313 if (mlxsw_sp_port_created(mlxsw_sp, i))
3314 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003315 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003316 kfree(mlxsw_sp->ports);
3317}
3318
3319static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3320{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003321 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02003322 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003323 size_t alloc_size;
3324 int i;
3325 int err;
3326
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003327 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003328 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3329 if (!mlxsw_sp->ports)
3330 return -ENOMEM;
3331
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003332 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3333 GFP_KERNEL);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003334 if (!mlxsw_sp->port_to_module) {
3335 err = -ENOMEM;
3336 goto err_port_to_module_alloc;
3337 }
3338
3339 for (i = 1; i < max_ports; i++) {
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003340 /* Mark as invalid */
3341 mlxsw_sp->port_to_module[i] = -1;
3342
Ido Schimmel558c2d52016-02-26 17:32:29 +01003343 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003344 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01003345 if (err)
3346 goto err_port_module_info_get;
3347 if (!width)
3348 continue;
3349 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02003350 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3351 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003352 if (err)
3353 goto err_port_create;
3354 }
3355 return 0;
3356
3357err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01003358err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003359 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003360 if (mlxsw_sp_port_created(mlxsw_sp, i))
3361 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003362 kfree(mlxsw_sp->port_to_module);
3363err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003364 kfree(mlxsw_sp->ports);
3365 return err;
3366}
3367
Ido Schimmel18f1e702016-02-26 17:32:31 +01003368static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3369{
3370 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3371
3372 return local_port - offset;
3373}
3374
Ido Schimmelbe945352016-06-09 09:51:39 +02003375static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3376 u8 module, unsigned int count)
3377{
3378 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3379 int err, i;
3380
3381 for (i = 0; i < count; i++) {
Ido Schimmelbe945352016-06-09 09:51:39 +02003382 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02003383 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02003384 if (err)
3385 goto err_port_create;
3386 }
3387
3388 return 0;
3389
3390err_port_create:
3391 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003392 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3393 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02003394 return err;
3395}
3396
3397static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3398 u8 base_port, unsigned int count)
3399{
3400 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3401 int i;
3402
3403 /* Split by four means we need to re-create two ports, otherwise
3404 * only one.
3405 */
3406 count = count / 2;
3407
3408 for (i = 0; i < count; i++) {
3409 local_port = base_port + i * 2;
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003410 if (mlxsw_sp->port_to_module[local_port] < 0)
3411 continue;
Ido Schimmelbe945352016-06-09 09:51:39 +02003412 module = mlxsw_sp->port_to_module[local_port];
3413
Ido Schimmelbe945352016-06-09 09:51:39 +02003414 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003415 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003416 }
3417}
3418
Jiri Pirkob2f10572016-04-08 19:11:23 +02003419static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3420 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003421{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003422 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003423 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003424 u8 module, cur_width, base_port;
3425 int i;
3426 int err;
3427
3428 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3429 if (!mlxsw_sp_port) {
3430 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3431 local_port);
3432 return -EINVAL;
3433 }
3434
Ido Schimmeld664b412016-06-09 09:51:40 +02003435 module = mlxsw_sp_port->mapping.module;
3436 cur_width = mlxsw_sp_port->mapping.width;
3437
Ido Schimmel18f1e702016-02-26 17:32:31 +01003438 if (count != 2 && count != 4) {
3439 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3440 return -EINVAL;
3441 }
3442
Ido Schimmel18f1e702016-02-26 17:32:31 +01003443 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3444 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3445 return -EINVAL;
3446 }
3447
3448 /* Make sure we have enough slave (even) ports for the split. */
3449 if (count == 2) {
3450 base_port = local_port;
3451 if (mlxsw_sp->ports[base_port + 1]) {
3452 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3453 return -EINVAL;
3454 }
3455 } else {
3456 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3457 if (mlxsw_sp->ports[base_port + 1] ||
3458 mlxsw_sp->ports[base_port + 3]) {
3459 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3460 return -EINVAL;
3461 }
3462 }
3463
3464 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003465 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3466 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003467
Ido Schimmelbe945352016-06-09 09:51:39 +02003468 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3469 if (err) {
3470 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3471 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003472 }
3473
3474 return 0;
3475
Ido Schimmelbe945352016-06-09 09:51:39 +02003476err_port_split_create:
3477 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003478 return err;
3479}
3480
Jiri Pirkob2f10572016-04-08 19:11:23 +02003481static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003482{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003483 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003484 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003485 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003486 unsigned int count;
3487 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003488
3489 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3490 if (!mlxsw_sp_port) {
3491 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3492 local_port);
3493 return -EINVAL;
3494 }
3495
3496 if (!mlxsw_sp_port->split) {
3497 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3498 return -EINVAL;
3499 }
3500
Ido Schimmeld664b412016-06-09 09:51:40 +02003501 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003502 count = cur_width == 1 ? 4 : 2;
3503
3504 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3505
3506 /* Determine which ports to remove. */
3507 if (count == 2 && local_port >= base_port + 2)
3508 base_port = base_port + 2;
3509
3510 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003511 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3512 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003513
Ido Schimmelbe945352016-06-09 09:51:39 +02003514 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003515
3516 return 0;
3517}
3518
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003519static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3520 char *pude_pl, void *priv)
3521{
3522 struct mlxsw_sp *mlxsw_sp = priv;
3523 struct mlxsw_sp_port *mlxsw_sp_port;
3524 enum mlxsw_reg_pude_oper_status status;
3525 u8 local_port;
3526
3527 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3528 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003529 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003530 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003531
3532 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3533 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3534 netdev_info(mlxsw_sp_port->dev, "link up\n");
3535 netif_carrier_on(mlxsw_sp_port->dev);
3536 } else {
3537 netdev_info(mlxsw_sp_port->dev, "link down\n");
3538 netif_carrier_off(mlxsw_sp_port->dev);
3539 }
3540}
3541
Nogah Frankel14eeda92016-11-25 10:33:32 +01003542static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3543 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003544{
3545 struct mlxsw_sp *mlxsw_sp = priv;
3546 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3547 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3548
3549 if (unlikely(!mlxsw_sp_port)) {
3550 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3551 local_port);
3552 return;
3553 }
3554
3555 skb->dev = mlxsw_sp_port->dev;
3556
3557 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3558 u64_stats_update_begin(&pcpu_stats->syncp);
3559 pcpu_stats->rx_packets++;
3560 pcpu_stats->rx_bytes += skb->len;
3561 u64_stats_update_end(&pcpu_stats->syncp);
3562
3563 skb->protocol = eth_type_trans(skb, skb->dev);
3564 netif_receive_skb(skb);
3565}
3566
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003567static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3568 void *priv)
3569{
3570 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003571 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003572}
3573
Yotam Gigia0040c82017-10-03 09:58:10 +02003574static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3575 u8 local_port, void *priv)
3576{
3577 skb->offload_mr_fwd_mark = 1;
3578 skb->offload_fwd_mark = 1;
3579 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3580}
3581
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003582static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3583 void *priv)
3584{
3585 struct mlxsw_sp *mlxsw_sp = priv;
3586 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3587 struct psample_group *psample_group;
3588 u32 size;
3589
3590 if (unlikely(!mlxsw_sp_port)) {
3591 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3592 local_port);
3593 goto out;
3594 }
3595 if (unlikely(!mlxsw_sp_port->sample)) {
3596 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3597 local_port);
3598 goto out;
3599 }
3600
3601 size = mlxsw_sp_port->sample->truncate ?
3602 mlxsw_sp_port->sample->trunc_size : skb->len;
3603
3604 rcu_read_lock();
3605 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3606 if (!psample_group)
3607 goto out_unlock;
3608 psample_sample_packet(psample_group, skb, size,
3609 mlxsw_sp_port->dev->ifindex, 0,
3610 mlxsw_sp_port->sample->rate);
3611out_unlock:
3612 rcu_read_unlock();
3613out:
3614 consume_skb(skb);
3615}
3616
Nogah Frankel117b0da2016-11-25 10:33:44 +01003617#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003618 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003619 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003620
Nogah Frankel117b0da2016-11-25 10:33:44 +01003621#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003622 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003623 _is_ctrl, SP_##_trap_group, DISCARD)
3624
Yotam Gigia0040c82017-10-03 09:58:10 +02003625#define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3626 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3627 _is_ctrl, SP_##_trap_group, DISCARD)
3628
Nogah Frankel117b0da2016-11-25 10:33:44 +01003629#define MLXSW_SP_EVENTL(_func, _trap_id) \
3630 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003631
Nogah Frankel45449132016-11-25 10:33:35 +01003632static const struct mlxsw_listener mlxsw_sp_listener[] = {
3633 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003634 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003635 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003636 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3637 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3638 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3639 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3640 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3641 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3642 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3643 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3644 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3645 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3646 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003647 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003648 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3649 false),
3650 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3651 false),
3652 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3653 false),
3654 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3655 false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003656 /* L3 traps */
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003657 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3658 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3659 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003660 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003661 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3662 false),
3663 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3664 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3665 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3666 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3667 false),
3668 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3669 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3670 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003671 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003672 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3673 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3674 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3675 false),
3676 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3677 false),
3678 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3679 false),
3680 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3681 false),
3682 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3683 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3684 false),
3685 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3686 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
Ido Schimmel7607dd32017-07-17 14:15:30 +02003687 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003688 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
Petr Machata86484de2017-09-02 23:49:27 +02003689 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003690 /* PKT Sample trap */
3691 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
Jiri Pirko0db7b382017-06-06 14:12:05 +02003692 false, SP_IP2ME, DISCARD),
3693 /* ACL trap */
3694 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
Yotam Gigib48cfc82017-09-19 10:00:20 +02003695 /* Multicast Router Traps */
3696 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3697 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3698 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
Yotam Gigia0040c82017-10-03 09:58:10 +02003699 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003700};
3701
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003702static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3703{
3704 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3705 enum mlxsw_reg_qpcr_ir_units ir_units;
3706 int max_cpu_policers;
3707 bool is_bytes;
3708 u8 burst_size;
3709 u32 rate;
3710 int i, err;
3711
3712 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3713 return -EIO;
3714
3715 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3716
3717 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3718 for (i = 0; i < max_cpu_policers; i++) {
3719 is_bytes = false;
3720 switch (i) {
3721 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3722 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3723 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3724 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003725 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3726 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003727 rate = 128;
3728 burst_size = 7;
3729 break;
3730 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003731 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003732 rate = 16 * 1024;
3733 burst_size = 10;
3734 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003735 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003736 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3737 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003738 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003739 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3740 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003741 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003742 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003743 rate = 1024;
3744 burst_size = 7;
3745 break;
3746 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3747 is_bytes = true;
3748 rate = 4 * 1024;
3749 burst_size = 4;
3750 break;
3751 default:
3752 continue;
3753 }
3754
3755 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3756 burst_size);
3757 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3758 if (err)
3759 return err;
3760 }
3761
3762 return 0;
3763}
3764
Nogah Frankel579c82e2016-11-25 10:33:42 +01003765static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003766{
3767 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003768 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003769 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003770 int max_trap_groups;
3771 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003772 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003773 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003774
3775 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3776 return -EIO;
3777
3778 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003779 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003780
3781 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003782 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003783 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003784 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3785 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3786 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3787 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003788 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003789 priority = 5;
3790 tc = 5;
3791 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003792 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003793 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3794 priority = 4;
3795 tc = 4;
3796 break;
3797 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3798 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003799 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003800 priority = 3;
3801 tc = 3;
3802 break;
3803 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003804 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003805 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003806 priority = 2;
3807 tc = 2;
3808 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003809 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003810 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3811 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003812 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003813 priority = 1;
3814 tc = 1;
3815 break;
3816 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003817 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3818 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003819 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003820 break;
3821 default:
3822 continue;
3823 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003824
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003825 if (max_cpu_policers <= policer_id &&
3826 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3827 return -EIO;
3828
3829 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003830 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3831 if (err)
3832 return err;
3833 }
3834
3835 return 0;
3836}
3837
3838static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3839{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003840 int i;
3841 int err;
3842
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003843 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3844 if (err)
3845 return err;
3846
Nogah Frankel579c82e2016-11-25 10:33:42 +01003847 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003848 if (err)
3849 return err;
3850
Nogah Frankel45449132016-11-25 10:33:35 +01003851 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003852 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003853 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003854 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003855 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003856 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003857
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003858 }
3859 return 0;
3860
Nogah Frankel45449132016-11-25 10:33:35 +01003861err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003862 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003863 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003864 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003865 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003866 }
3867 return err;
3868}
3869
3870static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3871{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003872 int i;
3873
Nogah Frankel45449132016-11-25 10:33:35 +01003874 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003875 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003876 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003877 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003878 }
3879}
3880
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003881static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3882{
3883 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003884 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003885
3886 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3887 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3888 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3889 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3890 MLXSW_REG_SLCR_LAG_HASH_SIP |
3891 MLXSW_REG_SLCR_LAG_HASH_DIP |
3892 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3893 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3894 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003895 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3896 if (err)
3897 return err;
3898
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003899 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3900 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003901 return -EIO;
3902
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003903 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003904 sizeof(struct mlxsw_sp_upper),
3905 GFP_KERNEL);
3906 if (!mlxsw_sp->lags)
3907 return -ENOMEM;
3908
3909 return 0;
3910}
3911
3912static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3913{
3914 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003915}
3916
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003917static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3918{
3919 char htgt_pl[MLXSW_REG_HTGT_LEN];
3920
Nogah Frankel579c82e2016-11-25 10:33:42 +01003921 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3922 MLXSW_REG_HTGT_INVALID_POLICER,
3923 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3924 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003925 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3926}
3927
Petr Machatac30f5d02017-10-16 16:26:35 +02003928static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3929 unsigned long event, void *ptr);
3930
Jiri Pirkob2f10572016-04-08 19:11:23 +02003931static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003932 const struct mlxsw_bus_info *mlxsw_bus_info)
3933{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003934 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003935 int err;
3936
3937 mlxsw_sp->core = mlxsw_core;
3938 mlxsw_sp->bus_info = mlxsw_bus_info;
3939
Yotam Gigi6b742192017-05-23 21:56:29 +02003940 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3941 if (err) {
3942 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3943 return err;
3944 }
3945
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003946 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3947 if (err) {
3948 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3949 return err;
3950 }
3951
Ido Schimmela875a2e2017-10-22 23:11:44 +02003952 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3953 if (err) {
3954 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3955 return err;
3956 }
3957
Ido Schimmela1107482017-05-26 08:37:39 +02003958 err = mlxsw_sp_fids_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003959 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003960 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
Ido Schimmela875a2e2017-10-22 23:11:44 +02003961 goto err_fids_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003962 }
3963
Ido Schimmela1107482017-05-26 08:37:39 +02003964 err = mlxsw_sp_traps_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003965 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003966 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3967 goto err_traps_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003968 }
3969
3970 err = mlxsw_sp_buffers_init(mlxsw_sp);
3971 if (err) {
3972 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3973 goto err_buffers_init;
3974 }
3975
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003976 err = mlxsw_sp_lag_init(mlxsw_sp);
3977 if (err) {
3978 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3979 goto err_lag_init;
3980 }
3981
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003982 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3983 if (err) {
3984 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3985 goto err_switchdev_init;
3986 }
3987
Yotam Gigie2b2d352017-09-19 10:00:08 +02003988 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3989 if (err) {
3990 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3991 goto err_counter_pool_init;
3992 }
3993
Yotam Gigid3b939b2017-09-19 10:00:09 +02003994 err = mlxsw_sp_afa_init(mlxsw_sp);
3995 if (err) {
3996 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3997 goto err_afa_init;
3998 }
3999
Ido Schimmel464dce12016-07-02 11:00:15 +02004000 err = mlxsw_sp_router_init(mlxsw_sp);
4001 if (err) {
4002 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
4003 goto err_router_init;
4004 }
4005
Petr Machatac30f5d02017-10-16 16:26:35 +02004006 /* Initialize netdevice notifier after router is initialized, so that
4007 * the event handler can use router structures.
4008 */
4009 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
4010 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4011 if (err) {
4012 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
4013 goto err_netdev_notifier;
4014 }
4015
Yotam Gigi763b4b72016-07-21 12:03:17 +02004016 err = mlxsw_sp_span_init(mlxsw_sp);
4017 if (err) {
4018 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
4019 goto err_span_init;
4020 }
4021
Jiri Pirko22a67762017-02-03 10:29:07 +01004022 err = mlxsw_sp_acl_init(mlxsw_sp);
4023 if (err) {
4024 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
4025 goto err_acl_init;
4026 }
4027
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02004028 err = mlxsw_sp_dpipe_init(mlxsw_sp);
4029 if (err) {
4030 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
4031 goto err_dpipe_init;
4032 }
4033
Ido Schimmelbbf2a472016-07-02 11:00:14 +02004034 err = mlxsw_sp_ports_create(mlxsw_sp);
4035 if (err) {
4036 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
4037 goto err_ports_create;
4038 }
4039
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004040 return 0;
4041
Ido Schimmelbbf2a472016-07-02 11:00:14 +02004042err_ports_create:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02004043 mlxsw_sp_dpipe_fini(mlxsw_sp);
4044err_dpipe_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01004045 mlxsw_sp_acl_fini(mlxsw_sp);
4046err_acl_init:
Yotam Gigi763b4b72016-07-21 12:03:17 +02004047 mlxsw_sp_span_fini(mlxsw_sp);
4048err_span_init:
Petr Machatac30f5d02017-10-16 16:26:35 +02004049 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4050err_netdev_notifier:
Ido Schimmel464dce12016-07-02 11:00:15 +02004051 mlxsw_sp_router_fini(mlxsw_sp);
4052err_router_init:
Yotam Gigid3b939b2017-09-19 10:00:09 +02004053 mlxsw_sp_afa_fini(mlxsw_sp);
4054err_afa_init:
Yotam Gigie2b2d352017-09-19 10:00:08 +02004055 mlxsw_sp_counter_pool_fini(mlxsw_sp);
4056err_counter_pool_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02004057 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004058err_switchdev_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02004059 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004060err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02004061 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004062err_buffers_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004063 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02004064err_traps_init:
4065 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02004066err_fids_init:
4067 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004068 return err;
4069}
4070
Jiri Pirkob2f10572016-04-08 19:11:23 +02004071static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004072{
Jiri Pirkob2f10572016-04-08 19:11:23 +02004073 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004074
Ido Schimmelbbf2a472016-07-02 11:00:14 +02004075 mlxsw_sp_ports_remove(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02004076 mlxsw_sp_dpipe_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01004077 mlxsw_sp_acl_fini(mlxsw_sp);
Yotam Gigi763b4b72016-07-21 12:03:17 +02004078 mlxsw_sp_span_fini(mlxsw_sp);
Petr Machatac30f5d02017-10-16 16:26:35 +02004079 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
Ido Schimmel464dce12016-07-02 11:00:15 +02004080 mlxsw_sp_router_fini(mlxsw_sp);
Yotam Gigid3b939b2017-09-19 10:00:09 +02004081 mlxsw_sp_afa_fini(mlxsw_sp);
Yotam Gigie2b2d352017-09-19 10:00:08 +02004082 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004083 mlxsw_sp_switchdev_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02004084 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02004085 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004086 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02004087 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02004088 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004089}
4090
Bhumika Goyal159fe882017-08-11 19:10:42 +05304091static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004092 .used_max_vepa_channels = 1,
4093 .max_vepa_channels = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004094 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01004095 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004096 .used_max_pgt = 1,
4097 .max_pgt = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004098 .used_flood_tables = 1,
4099 .used_flood_mode = 1,
4100 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01004101 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004102 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01004103 .max_fid_flood_tables = 3,
Ido Schimmela1107482017-05-26 08:37:39 +02004104 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004105 .used_max_ib_mc = 1,
4106 .max_ib_mc = 0,
4107 .used_max_pkey = 1,
4108 .max_pkey = 0,
Nogah Frankel403547d2016-09-20 11:16:52 +02004109 .used_kvd_split_data = 1,
4110 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
Ido Schimmelf11fbaf2017-10-22 23:11:49 +02004111 .kvd_hash_single_parts = 59,
4112 .kvd_hash_double_parts = 41,
Jiri Pirkoc6022422016-07-05 11:27:46 +02004113 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004114 .swid_config = {
4115 {
4116 .used_type = 1,
4117 .type = MLXSW_PORT_SWID_TYPE_ETH,
4118 }
4119 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02004120 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004121};
4122
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004123static bool
4124mlxsw_sp_resource_kvd_granularity_validate(struct netlink_ext_ack *extack,
4125 u64 size)
4126{
4127 const struct mlxsw_config_profile *profile;
4128
4129 profile = &mlxsw_sp_config_profile;
4130 if (size % profile->kvd_hash_granularity) {
4131 NL_SET_ERR_MSG_MOD(extack, "resource set with wrong granularity");
4132 return false;
4133 }
4134 return true;
4135}
4136
4137static int
4138mlxsw_sp_resource_kvd_size_validate(struct devlink *devlink, u64 size,
4139 struct netlink_ext_ack *extack)
4140{
4141 NL_SET_ERR_MSG_MOD(extack, "kvd size cannot be changed");
4142 return -EINVAL;
4143}
4144
4145static int
4146mlxsw_sp_resource_kvd_linear_size_validate(struct devlink *devlink, u64 size,
4147 struct netlink_ext_ack *extack)
4148{
4149 if (!mlxsw_sp_resource_kvd_granularity_validate(extack, size))
4150 return -EINVAL;
4151
4152 return 0;
4153}
4154
4155static int
4156mlxsw_sp_resource_kvd_hash_single_size_validate(struct devlink *devlink, u64 size,
4157 struct netlink_ext_ack *extack)
4158{
4159 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
4160
4161 if (!mlxsw_sp_resource_kvd_granularity_validate(extack, size))
4162 return -EINVAL;
4163
4164 if (size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE)) {
4165 NL_SET_ERR_MSG_MOD(extack, "hash single size is smaller than minimum");
4166 return -EINVAL;
4167 }
4168 return 0;
4169}
4170
4171static int
4172mlxsw_sp_resource_kvd_hash_double_size_validate(struct devlink *devlink, u64 size,
4173 struct netlink_ext_ack *extack)
4174{
4175 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
4176
4177 if (!mlxsw_sp_resource_kvd_granularity_validate(extack, size))
4178 return -EINVAL;
4179
4180 if (size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE)) {
4181 NL_SET_ERR_MSG_MOD(extack, "hash double size is smaller than minimum");
4182 return -EINVAL;
4183 }
4184 return 0;
4185}
4186
Arkadi Sharshevskyafadc262018-01-15 08:59:09 +01004187static u64 mlxsw_sp_resource_kvd_linear_occ_get(struct devlink *devlink)
4188{
4189 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
4190 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4191
4192 return mlxsw_sp_kvdl_occ_get(mlxsw_sp);
4193}
4194
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004195static struct devlink_resource_ops mlxsw_sp_resource_kvd_ops = {
4196 .size_validate = mlxsw_sp_resource_kvd_size_validate,
4197};
4198
4199static struct devlink_resource_ops mlxsw_sp_resource_kvd_linear_ops = {
4200 .size_validate = mlxsw_sp_resource_kvd_linear_size_validate,
Arkadi Sharshevskyafadc262018-01-15 08:59:09 +01004201 .occ_get = mlxsw_sp_resource_kvd_linear_occ_get,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004202};
4203
4204static struct devlink_resource_ops mlxsw_sp_resource_kvd_hash_single_ops = {
4205 .size_validate = mlxsw_sp_resource_kvd_hash_single_size_validate,
4206};
4207
4208static struct devlink_resource_ops mlxsw_sp_resource_kvd_hash_double_ops = {
4209 .size_validate = mlxsw_sp_resource_kvd_hash_double_size_validate,
4210};
4211
4212static struct devlink_resource_size_params mlxsw_sp_kvd_size_params;
4213static struct devlink_resource_size_params mlxsw_sp_linear_size_params;
4214static struct devlink_resource_size_params mlxsw_sp_hash_single_size_params;
4215static struct devlink_resource_size_params mlxsw_sp_hash_double_size_params;
4216
4217static void
4218mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core)
4219{
4220 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
4221 KVD_SINGLE_MIN_SIZE);
4222 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
4223 KVD_DOUBLE_MIN_SIZE);
4224 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4225 u32 linear_size_min = 0;
4226
4227 /* KVD top resource */
4228 mlxsw_sp_kvd_size_params.size_min = kvd_size;
4229 mlxsw_sp_kvd_size_params.size_max = kvd_size;
4230 mlxsw_sp_kvd_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
4231 mlxsw_sp_kvd_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
4232
4233 /* Linear part init */
4234 mlxsw_sp_linear_size_params.size_min = linear_size_min;
4235 mlxsw_sp_linear_size_params.size_max = kvd_size - single_size_min -
4236 double_size_min;
4237 mlxsw_sp_linear_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
4238 mlxsw_sp_linear_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
4239
4240 /* Hash double part init */
4241 mlxsw_sp_hash_double_size_params.size_min = double_size_min;
4242 mlxsw_sp_hash_double_size_params.size_max = kvd_size - single_size_min -
4243 linear_size_min;
4244 mlxsw_sp_hash_double_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
4245 mlxsw_sp_hash_double_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
4246
4247 /* Hash single part init */
4248 mlxsw_sp_hash_single_size_params.size_min = single_size_min;
4249 mlxsw_sp_hash_single_size_params.size_max = kvd_size - double_size_min -
4250 linear_size_min;
4251 mlxsw_sp_hash_single_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
4252 mlxsw_sp_hash_single_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
4253}
4254
4255static int mlxsw_sp_resources_register(struct mlxsw_core *mlxsw_core)
4256{
4257 struct devlink *devlink = priv_to_devlink(mlxsw_core);
4258 u32 kvd_size, single_size, double_size, linear_size;
4259 const struct mlxsw_config_profile *profile;
4260 int err;
4261
4262 profile = &mlxsw_sp_config_profile;
4263 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
4264 return -EIO;
4265
4266 mlxsw_sp_resource_size_params_prepare(mlxsw_core);
4267 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4268 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
4269 true, kvd_size,
4270 MLXSW_SP_RESOURCE_KVD,
4271 DEVLINK_RESOURCE_ID_PARENT_TOP,
4272 &mlxsw_sp_kvd_size_params,
4273 &mlxsw_sp_resource_kvd_ops);
4274 if (err)
4275 return err;
4276
4277 linear_size = profile->kvd_linear_size;
4278 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
4279 false, linear_size,
4280 MLXSW_SP_RESOURCE_KVD_LINEAR,
4281 MLXSW_SP_RESOURCE_KVD,
4282 &mlxsw_sp_linear_size_params,
4283 &mlxsw_sp_resource_kvd_linear_ops);
4284 if (err)
4285 return err;
4286
4287 double_size = kvd_size - linear_size;
4288 double_size *= profile->kvd_hash_double_parts;
4289 double_size /= profile->kvd_hash_double_parts +
4290 profile->kvd_hash_single_parts;
4291 double_size = rounddown(double_size, profile->kvd_hash_granularity);
4292 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
4293 false, double_size,
4294 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4295 MLXSW_SP_RESOURCE_KVD,
4296 &mlxsw_sp_hash_double_size_params,
4297 &mlxsw_sp_resource_kvd_hash_double_ops);
4298 if (err)
4299 return err;
4300
4301 single_size = kvd_size - double_size - linear_size;
4302 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
4303 false, single_size,
4304 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4305 MLXSW_SP_RESOURCE_KVD,
4306 &mlxsw_sp_hash_single_size_params,
4307 &mlxsw_sp_resource_kvd_hash_single_ops);
4308 if (err)
4309 return err;
4310
4311 return 0;
4312}
4313
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01004314static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
4315 const struct mlxsw_config_profile *profile,
4316 u64 *p_single_size, u64 *p_double_size,
4317 u64 *p_linear_size)
4318{
4319 struct devlink *devlink = priv_to_devlink(mlxsw_core);
4320 u32 double_size;
4321 int err;
4322
4323 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4324 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
4325 !profile->used_kvd_split_data)
4326 return -EIO;
4327
4328 /* The hash part is what left of the kvd without the
4329 * linear part. It is split to the single size and
4330 * double size by the parts ratio from the profile.
4331 * Both sizes must be a multiplications of the
4332 * granularity from the profile. In case the user
4333 * provided the sizes they are obtained via devlink.
4334 */
4335 err = devlink_resource_size_get(devlink,
4336 MLXSW_SP_RESOURCE_KVD_LINEAR,
4337 p_linear_size);
4338 if (err)
4339 *p_linear_size = profile->kvd_linear_size;
4340
4341 err = devlink_resource_size_get(devlink,
4342 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4343 p_double_size);
4344 if (err) {
4345 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4346 *p_linear_size;
4347 double_size *= profile->kvd_hash_double_parts;
4348 double_size /= profile->kvd_hash_double_parts +
4349 profile->kvd_hash_single_parts;
4350 *p_double_size = rounddown(double_size,
4351 profile->kvd_hash_granularity);
4352 }
4353
4354 err = devlink_resource_size_get(devlink,
4355 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4356 p_single_size);
4357 if (err)
4358 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4359 *p_double_size - *p_linear_size;
4360
4361 /* Check results are legal. */
4362 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4363 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
4364 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
4365 return -EIO;
4366
4367 return 0;
4368}
4369
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004370static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02004371 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02004372 .priv_size = sizeof(struct mlxsw_sp),
4373 .init = mlxsw_sp_init,
4374 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01004375 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02004376 .port_split = mlxsw_sp_port_split,
4377 .port_unsplit = mlxsw_sp_port_unsplit,
4378 .sb_pool_get = mlxsw_sp_sb_pool_get,
4379 .sb_pool_set = mlxsw_sp_sb_pool_set,
4380 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
4381 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
4382 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
4383 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4384 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4385 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4386 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4387 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4388 .txhdr_construct = mlxsw_sp_txhdr_construct,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004389 .resources_register = mlxsw_sp_resources_register,
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01004390 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02004391 .txhdr_len = MLXSW_TXHDR_LEN,
4392 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004393};
4394
Jiri Pirko22a67762017-02-03 10:29:07 +01004395bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004396{
4397 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4398}
4399
Jiri Pirko1182e532017-03-06 21:25:20 +01004400static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07004401{
Jiri Pirko1182e532017-03-06 21:25:20 +01004402 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07004403 int ret = 0;
4404
4405 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01004406 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07004407 ret = 1;
4408 }
4409
4410 return ret;
4411}
4412
Ido Schimmelc57529e2017-05-26 08:37:31 +02004413struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004414{
Jiri Pirko1182e532017-03-06 21:25:20 +01004415 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004416
4417 if (mlxsw_sp_port_dev_check(dev))
4418 return netdev_priv(dev);
4419
Jiri Pirko1182e532017-03-06 21:25:20 +01004420 mlxsw_sp_port = NULL;
4421 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004422
Jiri Pirko1182e532017-03-06 21:25:20 +01004423 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004424}
4425
Ido Schimmel4724ba562017-03-10 08:53:39 +01004426struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004427{
4428 struct mlxsw_sp_port *mlxsw_sp_port;
4429
4430 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4431 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4432}
4433
Arkadi Sharshevskyaf0613782017-06-08 08:44:20 +02004434struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004435{
Jiri Pirko1182e532017-03-06 21:25:20 +01004436 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004437
4438 if (mlxsw_sp_port_dev_check(dev))
4439 return netdev_priv(dev);
4440
Jiri Pirko1182e532017-03-06 21:25:20 +01004441 mlxsw_sp_port = NULL;
4442 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4443 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004444
Jiri Pirko1182e532017-03-06 21:25:20 +01004445 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004446}
4447
4448struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4449{
4450 struct mlxsw_sp_port *mlxsw_sp_port;
4451
4452 rcu_read_lock();
4453 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4454 if (mlxsw_sp_port)
4455 dev_hold(mlxsw_sp_port->dev);
4456 rcu_read_unlock();
4457 return mlxsw_sp_port;
4458}
4459
4460void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4461{
4462 dev_put(mlxsw_sp_port->dev);
4463}
4464
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004465static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004466{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004467 char sldr_pl[MLXSW_REG_SLDR_LEN];
4468
4469 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4470 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4471}
4472
4473static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4474{
4475 char sldr_pl[MLXSW_REG_SLDR_LEN];
4476
4477 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4478 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4479}
4480
4481static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4482 u16 lag_id, u8 port_index)
4483{
4484 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4485 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4486
4487 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4488 lag_id, port_index);
4489 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4490}
4491
4492static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4493 u16 lag_id)
4494{
4495 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4496 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4497
4498 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4499 lag_id);
4500 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4501}
4502
4503static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4504 u16 lag_id)
4505{
4506 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4507 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4508
4509 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4510 lag_id);
4511 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4512}
4513
4514static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4515 u16 lag_id)
4516{
4517 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4518 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4519
4520 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4521 lag_id);
4522 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4523}
4524
4525static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4526 struct net_device *lag_dev,
4527 u16 *p_lag_id)
4528{
4529 struct mlxsw_sp_upper *lag;
4530 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004531 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004532 int i;
4533
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004534 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4535 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004536 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4537 if (lag->ref_count) {
4538 if (lag->dev == lag_dev) {
4539 *p_lag_id = i;
4540 return 0;
4541 }
4542 } else if (free_lag_id < 0) {
4543 free_lag_id = i;
4544 }
4545 }
4546 if (free_lag_id < 0)
4547 return -EBUSY;
4548 *p_lag_id = free_lag_id;
4549 return 0;
4550}
4551
4552static bool
4553mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4554 struct net_device *lag_dev,
David Aherne58376e2017-10-04 17:48:51 -07004555 struct netdev_lag_upper_info *lag_upper_info,
4556 struct netlink_ext_ack *extack)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004557{
4558 u16 lag_id;
4559
David Aherne58376e2017-10-04 17:48:51 -07004560 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
4561 NL_SET_ERR_MSG(extack,
4562 "spectrum: Exceeded number of supported LAG devices");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004563 return false;
David Aherne58376e2017-10-04 17:48:51 -07004564 }
4565 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
4566 NL_SET_ERR_MSG(extack,
4567 "spectrum: LAG device using unsupported Tx type");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004568 return false;
David Aherne58376e2017-10-04 17:48:51 -07004569 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004570 return true;
4571}
4572
4573static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4574 u16 lag_id, u8 *p_port_index)
4575{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004576 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004577 int i;
4578
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004579 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4580 MAX_LAG_MEMBERS);
4581 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004582 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4583 *p_port_index = i;
4584 return 0;
4585 }
4586 }
4587 return -EBUSY;
4588}
4589
4590static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4591 struct net_device *lag_dev)
4592{
4593 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004594 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004595 struct mlxsw_sp_upper *lag;
4596 u16 lag_id;
4597 u8 port_index;
4598 int err;
4599
4600 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4601 if (err)
4602 return err;
4603 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4604 if (!lag->ref_count) {
4605 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4606 if (err)
4607 return err;
4608 lag->dev = lag_dev;
4609 }
4610
4611 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4612 if (err)
4613 return err;
4614 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4615 if (err)
4616 goto err_col_port_add;
4617 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4618 if (err)
4619 goto err_col_port_enable;
4620
4621 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4622 mlxsw_sp_port->local_port);
4623 mlxsw_sp_port->lag_id = lag_id;
4624 mlxsw_sp_port->lagged = 1;
4625 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004626
Ido Schimmelc57529e2017-05-26 08:37:31 +02004627 /* Port is no longer usable as a router interface */
4628 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4629 if (mlxsw_sp_port_vlan->fid)
Ido Schimmela1107482017-05-26 08:37:39 +02004630 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004631
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004632 return 0;
4633
Ido Schimmel51554db2016-05-06 22:18:39 +02004634err_col_port_enable:
4635 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004636err_col_port_add:
4637 if (!lag->ref_count)
4638 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004639 return err;
4640}
4641
Ido Schimmel82e6db02016-06-20 23:04:04 +02004642static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4643 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004644{
4645 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004646 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004647 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004648
4649 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004650 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004651 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4652 WARN_ON(lag->ref_count == 0);
4653
Ido Schimmel82e6db02016-06-20 23:04:04 +02004654 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4655 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004656
Ido Schimmelc57529e2017-05-26 08:37:31 +02004657 /* Any VLANs configured on the port are no longer valid */
4658 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004659
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004660 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004661 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004662
4663 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4664 mlxsw_sp_port->local_port);
4665 mlxsw_sp_port->lagged = 0;
4666 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004667
Ido Schimmelc57529e2017-05-26 08:37:31 +02004668 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4669 /* Make sure untagged frames are allowed to ingress */
4670 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004671}
4672
Jiri Pirko74581202015-12-03 12:12:30 +01004673static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4674 u16 lag_id)
4675{
4676 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4677 char sldr_pl[MLXSW_REG_SLDR_LEN];
4678
4679 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4680 mlxsw_sp_port->local_port);
4681 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4682}
4683
4684static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4685 u16 lag_id)
4686{
4687 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4688 char sldr_pl[MLXSW_REG_SLDR_LEN];
4689
4690 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4691 mlxsw_sp_port->local_port);
4692 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4693}
4694
4695static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4696 bool lag_tx_enabled)
4697{
4698 if (lag_tx_enabled)
4699 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4700 mlxsw_sp_port->lag_id);
4701 else
4702 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4703 mlxsw_sp_port->lag_id);
4704}
4705
4706static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4707 struct netdev_lag_lower_state_info *info)
4708{
4709 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4710}
4711
Jiri Pirko2b94e582017-04-18 16:55:37 +02004712static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4713 bool enable)
4714{
4715 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4716 enum mlxsw_reg_spms_state spms_state;
4717 char *spms_pl;
4718 u16 vid;
4719 int err;
4720
4721 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4722 MLXSW_REG_SPMS_STATE_DISCARDING;
4723
4724 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4725 if (!spms_pl)
4726 return -ENOMEM;
4727 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4728
4729 for (vid = 0; vid < VLAN_N_VID; vid++)
4730 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4731
4732 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4733 kfree(spms_pl);
4734 return err;
4735}
4736
4737static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4738{
Yuval Mintzfccff082017-12-15 08:44:21 +01004739 u16 vid = 1;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004740 int err;
4741
Ido Schimmel4aafc362017-05-26 08:37:25 +02004742 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004743 if (err)
4744 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02004745 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4746 if (err)
4747 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004748 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4749 true, false);
4750 if (err)
4751 goto err_port_vlan_set;
Yuval Mintzfccff082017-12-15 08:44:21 +01004752
4753 for (; vid <= VLAN_N_VID - 1; vid++) {
4754 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4755 vid, false);
4756 if (err)
4757 goto err_vid_learning_set;
4758 }
4759
Jiri Pirko2b94e582017-04-18 16:55:37 +02004760 return 0;
4761
Yuval Mintzfccff082017-12-15 08:44:21 +01004762err_vid_learning_set:
4763 for (vid--; vid >= 1; vid--)
4764 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004765err_port_vlan_set:
4766 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004767err_port_stp_set:
4768 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004769 return err;
4770}
4771
4772static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4773{
Yuval Mintzfccff082017-12-15 08:44:21 +01004774 u16 vid;
4775
4776 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4777 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4778 vid, true);
4779
Jiri Pirko2b94e582017-04-18 16:55:37 +02004780 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4781 false, false);
4782 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004783 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004784}
4785
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004786static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4787 struct net_device *dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004788 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004789{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004790 struct netdev_notifier_changeupper_info *info;
4791 struct mlxsw_sp_port *mlxsw_sp_port;
David Aherne58376e2017-10-04 17:48:51 -07004792 struct netlink_ext_ack *extack;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004793 struct net_device *upper_dev;
4794 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004795 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004796
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004797 mlxsw_sp_port = netdev_priv(dev);
4798 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4799 info = ptr;
David Aherne58376e2017-10-04 17:48:51 -07004800 extack = netdev_notifier_info_to_extack(&info->info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004801
4802 switch (event) {
4803 case NETDEV_PRECHANGEUPPER:
4804 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004805 if (!is_vlan_dev(upper_dev) &&
4806 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004807 !netif_is_bridge_master(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004808 !netif_is_ovs_master(upper_dev)) {
4809 NL_SET_ERR_MSG(extack,
4810 "spectrum: Unknown upper device type");
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004811 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004812 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004813 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004814 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004815 if (netdev_has_any_upper_dev(upper_dev) &&
4816 (!netif_is_bridge_master(upper_dev) ||
4817 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4818 upper_dev))) {
David Aherne58376e2017-10-04 17:48:51 -07004819 NL_SET_ERR_MSG(extack,
4820 "spectrum: Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004821 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004822 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004823 if (netif_is_lag_master(upper_dev) &&
4824 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
David Aherne58376e2017-10-04 17:48:51 -07004825 info->upper_info, extack))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004826 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004827 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
4828 NL_SET_ERR_MSG(extack,
4829 "spectrum: Master device is a LAG master and this device has a VLAN");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004830 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004831 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004832 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004833 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
4834 NL_SET_ERR_MSG(extack,
4835 "spectrum: Can not put a VLAN on a LAG port");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004836 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004837 }
4838 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
4839 NL_SET_ERR_MSG(extack,
4840 "spectrum: Master device is an OVS master and this device has a VLAN");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004841 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004842 }
4843 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
4844 NL_SET_ERR_MSG(extack,
4845 "spectrum: Can not put a VLAN on an OVS port");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004846 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004847 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004848 break;
4849 case NETDEV_CHANGEUPPER:
4850 upper_dev = info->upper_dev;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004851 if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004852 if (info->linking)
4853 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004854 lower_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004855 upper_dev,
4856 extack);
Ido Schimmel7117a572016-06-20 23:04:06 +02004857 else
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004858 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4859 lower_dev,
4860 upper_dev);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004861 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004862 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004863 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4864 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004865 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004866 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4867 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004868 } else if (netif_is_ovs_master(upper_dev)) {
4869 if (info->linking)
4870 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4871 else
4872 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004873 }
4874 break;
4875 }
4876
Ido Schimmel80bedf12016-06-20 23:03:59 +02004877 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004878}
4879
Jiri Pirko74581202015-12-03 12:12:30 +01004880static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4881 unsigned long event, void *ptr)
4882{
4883 struct netdev_notifier_changelowerstate_info *info;
4884 struct mlxsw_sp_port *mlxsw_sp_port;
4885 int err;
4886
4887 mlxsw_sp_port = netdev_priv(dev);
4888 info = ptr;
4889
4890 switch (event) {
4891 case NETDEV_CHANGELOWERSTATE:
4892 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4893 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4894 info->lower_state_info);
4895 if (err)
4896 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4897 }
4898 break;
4899 }
4900
Ido Schimmel80bedf12016-06-20 23:03:59 +02004901 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004902}
4903
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004904static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4905 struct net_device *port_dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004906 unsigned long event, void *ptr)
4907{
4908 switch (event) {
4909 case NETDEV_PRECHANGEUPPER:
4910 case NETDEV_CHANGEUPPER:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004911 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4912 event, ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004913 case NETDEV_CHANGELOWERSTATE:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004914 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4915 ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004916 }
4917
Ido Schimmel80bedf12016-06-20 23:03:59 +02004918 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004919}
4920
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004921static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4922 unsigned long event, void *ptr)
4923{
4924 struct net_device *dev;
4925 struct list_head *iter;
4926 int ret;
4927
4928 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4929 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004930 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4931 ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004932 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004933 return ret;
4934 }
4935 }
4936
Ido Schimmel80bedf12016-06-20 23:03:59 +02004937 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004938}
4939
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004940static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4941 struct net_device *dev,
4942 unsigned long event, void *ptr,
4943 u16 vid)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004944{
4945 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel90045fc2017-12-25 09:05:33 +01004946 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004947 struct netdev_notifier_changeupper_info *info = ptr;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004948 struct netlink_ext_ack *extack;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004949 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004950 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004951
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004952 extack = netdev_notifier_info_to_extack(&info->info);
4953
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004954 switch (event) {
4955 case NETDEV_PRECHANGEUPPER:
4956 upper_dev = info->upper_dev;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004957 if (!netif_is_bridge_master(upper_dev)) {
4958 NL_SET_ERR_MSG(extack, "spectrum: VLAN devices only support bridge and VRF uppers");
Ido Schimmel80bedf12016-06-20 23:03:59 +02004959 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004960 }
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004961 if (!info->linking)
4962 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004963 if (netdev_has_any_upper_dev(upper_dev) &&
4964 (!netif_is_bridge_master(upper_dev) ||
4965 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4966 upper_dev))) {
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004967 NL_SET_ERR_MSG(extack, "spectrum: Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004968 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004969 }
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004970 break;
4971 case NETDEV_CHANGEUPPER:
4972 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004973 if (netif_is_bridge_master(upper_dev)) {
4974 if (info->linking)
Ido Schimmelc57529e2017-05-26 08:37:31 +02004975 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4976 vlan_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004977 upper_dev,
4978 extack);
Ido Schimmel1f880612017-03-10 08:53:35 +01004979 else
Ido Schimmelc57529e2017-05-26 08:37:31 +02004980 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4981 vlan_dev,
4982 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004983 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004984 err = -EINVAL;
4985 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004986 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004987 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004988 }
4989
Ido Schimmel80bedf12016-06-20 23:03:59 +02004990 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004991}
4992
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004993static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4994 struct net_device *lag_dev,
4995 unsigned long event,
4996 void *ptr, u16 vid)
Ido Schimmel272c4472015-12-15 16:03:47 +01004997{
4998 struct net_device *dev;
4999 struct list_head *iter;
5000 int ret;
5001
5002 netdev_for_each_lower_dev(lag_dev, dev, iter) {
5003 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02005004 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
5005 event, ptr,
5006 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02005007 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01005008 return ret;
5009 }
5010 }
5011
Ido Schimmel80bedf12016-06-20 23:03:59 +02005012 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01005013}
5014
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01005015static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
5016 unsigned long event, void *ptr)
5017{
5018 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
5019 u16 vid = vlan_dev_vlan_id(vlan_dev);
5020
Ido Schimmel272c4472015-12-15 16:03:47 +01005021 if (mlxsw_sp_port_dev_check(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02005022 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
5023 event, ptr, vid);
Ido Schimmel272c4472015-12-15 16:03:47 +01005024 else if (netif_is_lag_master(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02005025 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
5026 real_dev, event,
5027 ptr, vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01005028
Ido Schimmel80bedf12016-06-20 23:03:59 +02005029 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01005030}
5031
Ido Schimmelb1e45522017-04-30 19:47:14 +03005032static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
5033{
5034 struct netdev_notifier_changeupper_info *info = ptr;
5035
5036 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
5037 return false;
5038 return netif_is_l3_master(info->upper_dev);
5039}
5040
Petr Machata00635872017-10-16 16:26:37 +02005041static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005042 unsigned long event, void *ptr)
5043{
5044 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Petr Machata00635872017-10-16 16:26:37 +02005045 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02005046 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005047
Petr Machata00635872017-10-16 16:26:37 +02005048 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
Petr Machata796ec772017-11-03 10:03:29 +01005049 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
5050 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
5051 event, ptr);
Petr Machata61481f22017-11-03 10:03:41 +01005052 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
5053 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
5054 event, ptr);
Petr Machata00635872017-10-16 16:26:37 +02005055 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
Ido Schimmel6e095fd2016-07-04 08:23:13 +02005056 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03005057 else if (mlxsw_sp_is_vrf_event(event, ptr))
5058 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02005059 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02005060 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02005061 else if (netif_is_lag_master(dev))
5062 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
5063 else if (is_vlan_dev(dev))
5064 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005065
Ido Schimmel80bedf12016-06-20 23:03:59 +02005066 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005067}
5068
David Ahern89d5dd22017-10-18 09:56:55 -07005069static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
5070 .notifier_call = mlxsw_sp_inetaddr_valid_event,
5071};
5072
Ido Schimmel99724c12016-07-04 08:23:14 +02005073static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
5074 .notifier_call = mlxsw_sp_inetaddr_event,
David Ahern89d5dd22017-10-18 09:56:55 -07005075};
5076
5077static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
5078 .notifier_call = mlxsw_sp_inet6addr_valid_event,
Ido Schimmel99724c12016-07-04 08:23:14 +02005079};
5080
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005081static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
5082 .notifier_call = mlxsw_sp_inet6addr_event,
5083};
5084
Jiri Pirko1d20d232016-10-27 15:12:59 +02005085static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
5086 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
5087 {0, },
5088};
5089
5090static struct pci_driver mlxsw_sp_pci_driver = {
5091 .name = mlxsw_sp_driver_name,
5092 .id_table = mlxsw_sp_pci_id_table,
5093};
5094
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005095static int __init mlxsw_sp_module_init(void)
5096{
5097 int err;
5098
David Ahern89d5dd22017-10-18 09:56:55 -07005099 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02005100 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005101 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005102 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02005103
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005104 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
5105 if (err)
5106 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02005107
5108 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
5109 if (err)
5110 goto err_pci_driver_register;
5111
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005112 return 0;
5113
Jiri Pirko1d20d232016-10-27 15:12:59 +02005114err_pci_driver_register:
5115 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005116err_core_driver_register:
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005117 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005118 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02005119 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005120 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005121 return err;
5122}
5123
5124static void __exit mlxsw_sp_module_exit(void)
5125{
Jiri Pirko1d20d232016-10-27 15:12:59 +02005126 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005127 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005128 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005129 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02005130 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005131 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005132}
5133
5134module_init(mlxsw_sp_module_init);
5135module_exit(mlxsw_sp_module_exit);
5136
5137MODULE_LICENSE("Dual BSD/GPL");
5138MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
5139MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02005140MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Yotam Gigi6b742192017-05-23 21:56:29 +02005141MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);