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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Jesse Barnes5669fca2009-02-17 15:13:31 -080030#include <linux/device.h>
David Howells760285e2012-10-02 18:01:07 +010031#include <drm/drmP.h>
32#include <drm/i915_drm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070033#include "i915_drv.h"
Chris Wilson990bbda2012-07-02 11:51:02 -030034#include "i915_trace.h"
Kenneth Graunkef49f0582010-09-11 01:19:14 -070035#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070036
Jesse Barnes79e53942008-11-07 14:24:08 -080037#include <linux/console.h>
Paul Gortmakere0cd3602011-08-30 11:04:30 -040038#include <linux/module.h>
David Howells760285e2012-10-02 18:01:07 +010039#include <drm/drm_crtc_helper.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080040
Ben Widawskya35d9d32011-07-13 14:38:17 -070041static int i915_modeset __read_mostly = -1;
Jesse Barnes79e53942008-11-07 14:24:08 -080042module_param_named(modeset, i915_modeset, int, 0400);
Ben Widawsky6e96e772011-07-13 14:38:18 -070043MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
Jesse Barnes79e53942008-11-07 14:24:08 -080046
Ben Widawskya35d9d32011-07-13 14:38:17 -070047unsigned int i915_fbpercrtc __always_unused = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -080048module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
Linus Torvalds1da177e2005-04-16 15:20:36 -070049
Daniel Vettera7269152012-11-20 14:50:08 +010050int i915_panel_ignore_lid __read_mostly = 1;
Chris Wilsonfca87402011-02-17 13:44:48 +000051module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -070052MODULE_PARM_DESC(panel_ignore_lid,
Daniel Vettera7269152012-11-20 14:50:08 +010053 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
54 "-1=force lid closed, -2=force lid open)");
Chris Wilsonfca87402011-02-17 13:44:48 +000055
Ben Widawskya35d9d32011-07-13 14:38:17 -070056unsigned int i915_powersave __read_mostly = 1;
Chris Wilson0aa99272010-11-02 09:20:50 +000057module_param_named(powersave, i915_powersave, int, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -070058MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
Jesse Barnes652c3932009-08-17 13:31:43 -070060
Eugeni Dodonovf45b5552011-12-09 17:16:37 -080061int i915_semaphores __read_mostly = -1;
Chris Wilsona1656b92011-03-04 18:48:03 +000062module_param_named(semaphores, i915_semaphores, int, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -070063MODULE_PARM_DESC(semaphores,
Eugeni Dodonovf45b5552011-12-09 17:16:37 -080064 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
Chris Wilsona1656b92011-03-04 18:48:03 +000065
Keith Packardc0f372b32011-11-16 22:24:52 -080066int i915_enable_rc6 __read_mostly = -1;
Jesse Barnesf57f9c12012-04-11 09:39:02 -070067module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
Ben Widawsky6e96e772011-07-13 14:38:18 -070068MODULE_PARM_DESC(i915_enable_rc6,
Eugeni Dodonov83b7f9a2012-03-23 11:57:18 -030069 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
Chris Wilsonac668082011-02-09 16:15:32 +000074
Keith Packard4415e632011-11-09 09:57:50 -080075int i915_enable_fbc __read_mostly = -1;
Jesse Barnesc1a9f042011-05-05 15:24:21 -070076module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -070077MODULE_PARM_DESC(i915_enable_fbc,
78 "Enable frame buffer compression for power savings "
Keith Packardcd0de032011-09-19 21:34:19 -070079 "(default: -1 (use per-chip default))");
Jesse Barnesc1a9f042011-05-05 15:24:21 -070080
Ben Widawskya35d9d32011-07-13 14:38:17 -070081unsigned int i915_lvds_downclock __read_mostly = 0;
Jesse Barnes33814342010-01-14 20:48:02 +000082module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
Ben Widawsky6e96e772011-07-13 14:38:18 -070083MODULE_PARM_DESC(lvds_downclock,
84 "Use panel (LVDS/eDP) downclocking for power savings "
85 "(default: false)");
Jesse Barnes33814342010-01-14 20:48:02 +000086
Takashi Iwai121d5272012-03-20 13:07:06 +010087int i915_lvds_channel_mode __read_mostly;
88module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
89MODULE_PARM_DESC(lvds_channel_mode,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
92
Keith Packard4415e632011-11-09 09:57:50 -080093int i915_panel_use_ssc __read_mostly = -1;
Chris Wilsona7615032011-01-12 17:04:08 +000094module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -070095MODULE_PARM_DESC(lvds_use_ssc,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
Keith Packard72bbe582011-09-26 16:09:45 -070097 "(default: auto from VBT)");
Chris Wilsona7615032011-01-12 17:04:08 +000098
Ben Widawskya35d9d32011-07-13 14:38:17 -070099int i915_vbt_sdvo_panel_type __read_mostly = -1;
Chris Wilson5a1e5b62011-01-29 16:50:25 +0000100module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -0700101MODULE_PARM_DESC(vbt_sdvo_panel_type,
Mathias Fröhlichc10e4082012-03-01 06:44:35 +0100102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
Chris Wilson5a1e5b62011-01-29 16:50:25 +0000104
Ben Widawskya35d9d32011-07-13 14:38:17 -0700105static bool i915_try_reset __read_mostly = true;
Chris Wilsond78cb502010-12-23 13:33:15 +0000106module_param_named(reset, i915_try_reset, bool, 0600);
Ben Widawsky6e96e772011-07-13 14:38:18 -0700107MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
Chris Wilsond78cb502010-12-23 13:33:15 +0000108
Ben Widawskya35d9d32011-07-13 14:38:17 -0700109bool i915_enable_hangcheck __read_mostly = true;
Ben Widawsky3e0dc6b2011-06-29 10:26:42 -0700110module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
Ben Widawsky6e96e772011-07-13 14:38:18 -0700111MODULE_PARM_DESC(enable_hangcheck,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
114 "(default: true)");
Ben Widawsky3e0dc6b2011-06-29 10:26:42 -0700115
Daniel Vetter650dc072012-04-02 10:08:35 +0200116int i915_enable_ppgtt __read_mostly = -1;
117module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
Daniel Vettere21af882012-02-09 20:53:27 +0100118MODULE_PARM_DESC(i915_enable_ppgtt,
119 "Enable PPGTT (default: true)");
120
Rodrigo Vivi0a3af262012-10-15 17:16:23 -0300121unsigned int i915_preliminary_hw_support __read_mostly = 0;
122module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
123MODULE_PARM_DESC(preliminary_hw_support,
124 "Enable preliminary hardware support. "
125 "Enable Haswell and ValleyView Support. "
126 "(default: false)");
127
Paulo Zanoni2124b722013-03-22 14:07:23 -0300128int i915_disable_power_well __read_mostly = 0;
129module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
130MODULE_PARM_DESC(disable_power_well,
131 "Disable the power well when possible (default: false)");
132
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500133static struct drm_driver driver;
Zhenyu Wang1f7a6e32010-02-23 14:05:24 +0800134extern int intel_agp_enabled;
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500135
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500136#define INTEL_VGA_DEVICE(id, info) { \
Daniel Vetter80a29012011-10-11 10:59:05 +0200137 .class = PCI_BASE_CLASS_DISPLAY << 16, \
Chris Wilson934f9922011-01-20 13:09:12 +0000138 .class_mask = 0xff0000, \
Kristian Høgsberg49ae35f2009-12-16 15:16:15 -0500139 .vendor = 0x8086, \
140 .device = id, \
141 .subvendor = PCI_ANY_ID, \
142 .subdevice = PCI_ANY_ID, \
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500143 .driver_data = (unsigned long) info }
Kristian Høgsberg49ae35f2009-12-16 15:16:15 -0500144
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200145static const struct intel_device_info intel_i830_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100146 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100147 .has_overlay = 1, .overlay_needs_physical = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500148};
149
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200150static const struct intel_device_info intel_845g_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100151 .gen = 2,
Chris Wilson315781482010-08-12 09:42:51 +0100152 .has_overlay = 1, .overlay_needs_physical = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500153};
154
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200155static const struct intel_device_info intel_i85x_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100156 .gen = 2, .is_i85x = 1, .is_mobile = 1,
Adam Jackson5ce8ba72010-04-15 14:03:30 -0400157 .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100158 .has_overlay = 1, .overlay_needs_physical = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500159};
160
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200161static const struct intel_device_info intel_i865g_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100162 .gen = 2,
Chris Wilson315781482010-08-12 09:42:51 +0100163 .has_overlay = 1, .overlay_needs_physical = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500164};
165
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200166static const struct intel_device_info intel_i915g_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100167 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100168 .has_overlay = 1, .overlay_needs_physical = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500169};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200170static const struct intel_device_info intel_i915gm_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100171 .gen = 3, .is_mobile = 1,
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -0500172 .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100173 .has_overlay = 1, .overlay_needs_physical = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100174 .supports_tv = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500175};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200176static const struct intel_device_info intel_i945g_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100177 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100178 .has_overlay = 1, .overlay_needs_physical = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500179};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200180static const struct intel_device_info intel_i945gm_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100181 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -0500182 .has_hotplug = 1, .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100183 .has_overlay = 1, .overlay_needs_physical = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100184 .supports_tv = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500185};
186
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200187static const struct intel_device_info intel_i965g_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100188 .gen = 4, .is_broadwater = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100189 .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100190 .has_overlay = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500191};
192
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200193static const struct intel_device_info intel_i965gm_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100194 .gen = 4, .is_crestline = 1,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000195 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100196 .has_overlay = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100197 .supports_tv = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500198};
199
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200200static const struct intel_device_info intel_g33_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100201 .gen = 3, .is_g33 = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100202 .need_gfx_hws = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100203 .has_overlay = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500204};
205
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200206static const struct intel_device_info intel_g45_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100207 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100208 .has_pipe_cxsr = 1, .has_hotplug = 1,
Xiang, Haihao92f49d92010-09-16 10:43:10 +0800209 .has_bsd_ring = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500210};
211
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200212static const struct intel_device_info intel_gm45_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100213 .gen = 4, .is_g4x = 1,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000214 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100215 .has_pipe_cxsr = 1, .has_hotplug = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100216 .supports_tv = 1,
Xiang, Haihao92f49d92010-09-16 10:43:10 +0800217 .has_bsd_ring = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500218};
219
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200220static const struct intel_device_info intel_pineview_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100221 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100222 .need_gfx_hws = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100223 .has_overlay = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500224};
225
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200226static const struct intel_device_info intel_ironlake_d_info = {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +0100227 .gen = 5,
Eugeni Dodonov5a117db2012-01-05 09:34:29 -0200228 .need_gfx_hws = 1, .has_hotplug = 1,
Xiang, Haihao92f49d92010-09-16 10:43:10 +0800229 .has_bsd_ring = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500230};
231
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200232static const struct intel_device_info intel_ironlake_m_info = {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +0100233 .gen = 5, .is_mobile = 1,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000234 .need_gfx_hws = 1, .has_hotplug = 1,
Jesse Barnesc1a9f042011-05-05 15:24:21 -0700235 .has_fbc = 1,
Xiang, Haihao92f49d92010-09-16 10:43:10 +0800236 .has_bsd_ring = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500237};
238
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200239static const struct intel_device_info intel_sandybridge_d_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100240 .gen = 6,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100241 .need_gfx_hws = 1, .has_hotplug = 1,
Xiang, Haihao881f47b2010-09-19 14:40:43 +0100242 .has_bsd_ring = 1,
Chris Wilson549f7362010-10-19 11:19:32 +0100243 .has_blt_ring = 1,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200244 .has_llc = 1,
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200245 .has_force_wake = 1,
Eric Anholtf6e450a2009-11-02 12:08:22 -0800246};
247
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200248static const struct intel_device_info intel_sandybridge_m_info = {
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100249 .gen = 6, .is_mobile = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100250 .need_gfx_hws = 1, .has_hotplug = 1,
Yuanhan Liu9c04f012010-12-15 15:42:32 +0800251 .has_fbc = 1,
Xiang, Haihao881f47b2010-09-19 14:40:43 +0100252 .has_bsd_ring = 1,
Chris Wilson549f7362010-10-19 11:19:32 +0100253 .has_blt_ring = 1,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200254 .has_llc = 1,
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200255 .has_force_wake = 1,
Eric Anholta13e4092010-01-07 15:08:18 -0800256};
257
Jesse Barnesc76b6152011-04-28 14:32:07 -0700258static const struct intel_device_info intel_ivybridge_d_info = {
259 .is_ivybridge = 1, .gen = 7,
260 .need_gfx_hws = 1, .has_hotplug = 1,
261 .has_bsd_ring = 1,
262 .has_blt_ring = 1,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200263 .has_llc = 1,
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200264 .has_force_wake = 1,
Jesse Barnesc76b6152011-04-28 14:32:07 -0700265};
266
267static const struct intel_device_info intel_ivybridge_m_info = {
268 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
269 .need_gfx_hws = 1, .has_hotplug = 1,
270 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
271 .has_bsd_ring = 1,
272 .has_blt_ring = 1,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200273 .has_llc = 1,
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200274 .has_force_wake = 1,
Jesse Barnesc76b6152011-04-28 14:32:07 -0700275};
276
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700277static const struct intel_device_info intel_valleyview_m_info = {
278 .gen = 7, .is_mobile = 1,
279 .need_gfx_hws = 1, .has_hotplug = 1,
280 .has_fbc = 0,
281 .has_bsd_ring = 1,
282 .has_blt_ring = 1,
283 .is_valleyview = 1,
Ville Syrjäläfba5d532013-01-24 15:29:56 +0200284 .display_mmio_offset = VLV_DISPLAY_BASE,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700285};
286
287static const struct intel_device_info intel_valleyview_d_info = {
288 .gen = 7,
289 .need_gfx_hws = 1, .has_hotplug = 1,
290 .has_fbc = 0,
291 .has_bsd_ring = 1,
292 .has_blt_ring = 1,
293 .is_valleyview = 1,
Ville Syrjäläfba5d532013-01-24 15:29:56 +0200294 .display_mmio_offset = VLV_DISPLAY_BASE,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700295};
296
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -0300297static const struct intel_device_info intel_haswell_d_info = {
298 .is_haswell = 1, .gen = 7,
299 .need_gfx_hws = 1, .has_hotplug = 1,
300 .has_bsd_ring = 1,
301 .has_blt_ring = 1,
302 .has_llc = 1,
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200303 .has_force_wake = 1,
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -0300304};
305
306static const struct intel_device_info intel_haswell_m_info = {
307 .is_haswell = 1, .gen = 7, .is_mobile = 1,
308 .need_gfx_hws = 1, .has_hotplug = 1,
309 .has_bsd_ring = 1,
310 .has_blt_ring = 1,
311 .has_llc = 1,
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200312 .has_force_wake = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500313};
314
Chris Wilson6103da02010-07-05 18:01:47 +0100315static const struct pci_device_id pciidlist[] = { /* aka */
316 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
317 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
318 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
Adam Jackson5ce8ba72010-04-15 14:03:30 -0400319 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
Chris Wilson6103da02010-07-05 18:01:47 +0100320 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
321 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
322 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
323 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
324 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
325 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
326 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
327 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
328 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
329 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
330 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
331 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
332 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
333 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
334 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
335 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
336 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
337 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
338 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
339 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
340 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
341 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
Chris Wilson41a51422010-09-17 08:22:30 +0100342 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500343 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
344 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
345 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
346 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
Eric Anholtf6e450a2009-11-02 12:08:22 -0800347 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
Zhenyu Wang85540482010-09-07 13:45:32 +0800348 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
349 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
Eric Anholta13e4092010-01-07 15:08:18 -0800350 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
Zhenyu Wang85540482010-09-07 13:45:32 +0800351 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
Zhenyu Wang4fefe432010-08-19 09:46:16 +0800352 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
Zhenyu Wang85540482010-09-07 13:45:32 +0800353 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
Jesse Barnesc76b6152011-04-28 14:32:07 -0700354 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
355 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
356 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
357 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
358 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
Eugeni Dodonovcc22a932012-03-29 20:55:48 -0300359 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
Eugeni Dodonovc14f5282012-05-09 15:37:32 -0300360 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
361 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
Paulo Zanonida612d82012-08-06 18:45:01 -0300362 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
Eugeni Dodonovc14f5282012-05-09 15:37:32 -0300363 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
364 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
Paulo Zanonida612d82012-08-06 18:45:01 -0300365 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
Eugeni Dodonovc14f5282012-05-09 15:37:32 -0300366 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
367 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
Paulo Zanonida612d82012-08-06 18:45:01 -0300368 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
369 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
370 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
371 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
372 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
373 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
374 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
375 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
376 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
377 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
378 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
379 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
380 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
381 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
382 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
383 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
384 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
385 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
386 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
Kenneth Graunke86c268e2013-03-01 17:00:50 -0800387 INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
388 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
Paulo Zanonida612d82012-08-06 18:45:01 -0300389 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
Kenneth Graunke86c268e2013-03-01 17:00:50 -0800390 INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
391 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
Paulo Zanonida612d82012-08-06 18:45:01 -0300392 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
Kenneth Graunke86c268e2013-03-01 17:00:50 -0800393 INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
394 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
Paulo Zanonida612d82012-08-06 18:45:01 -0300395 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
Jesse Barnesff049b62012-06-20 10:53:13 -0700396 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
397 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
398 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
Kristian Høgsberg49ae35f2009-12-16 15:16:15 -0500399 {0, 0, 0}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400};
401
Jesse Barnes79e53942008-11-07 14:24:08 -0800402#if defined(CONFIG_DRM_I915_KMS)
403MODULE_DEVICE_TABLE(pci, pciidlist);
404#endif
405
Akshay Joshi0206e352011-08-16 15:34:10 -0400406void intel_detect_pch(struct drm_device *dev)
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800407{
408 struct drm_i915_private *dev_priv = dev->dev_private;
409 struct pci_dev *pch;
410
411 /*
412 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
413 * make graphics device passthrough work easy for VMM, that only
414 * need to expose ISA bridge to let driver know the real hardware
415 * underneath. This is a requirement from virtualization team.
416 */
417 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
418 if (pch) {
419 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
Paulo Zanoni17a303e2012-11-20 15:12:07 -0200420 unsigned short id;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800421 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
Paulo Zanoni17a303e2012-11-20 15:12:07 -0200422 dev_priv->pch_id = id;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800423
Jesse Barnes90711d52011-04-28 14:48:02 -0700424 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
425 dev_priv->pch_type = PCH_IBX;
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100426 dev_priv->num_pch_pll = 2;
Jesse Barnes90711d52011-04-28 14:48:02 -0700427 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100428 WARN_ON(!IS_GEN5(dev));
Jesse Barnes90711d52011-04-28 14:48:02 -0700429 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800430 dev_priv->pch_type = PCH_CPT;
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100431 dev_priv->num_pch_pll = 2;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800432 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100433 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
Jesse Barnesc7925132011-04-07 12:33:56 -0700434 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
435 /* PantherPoint is CPT compatible */
436 dev_priv->pch_type = PCH_CPT;
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100437 dev_priv->num_pch_pll = 2;
Jesse Barnesc7925132011-04-07 12:33:56 -0700438 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100439 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300440 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
441 dev_priv->pch_type = PCH_LPT;
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100442 dev_priv->num_pch_pll = 0;
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300443 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100444 WARN_ON(!IS_HASWELL(dev));
Wei Shun Changae6935d2012-11-12 18:54:13 -0200445 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
446 dev_priv->pch_type = PCH_LPT;
447 dev_priv->num_pch_pll = 0;
448 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
449 WARN_ON(!IS_HASWELL(dev));
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800450 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100451 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800452 }
453 pci_dev_put(pch);
454 }
455}
456
Ben Widawsky2911a352012-04-05 14:47:36 -0700457bool i915_semaphore_is_enabled(struct drm_device *dev)
458{
459 if (INTEL_INFO(dev)->gen < 6)
460 return 0;
461
462 if (i915_semaphores >= 0)
463 return i915_semaphores;
464
Daniel Vetter59de3292012-04-02 20:48:43 +0200465#ifdef CONFIG_INTEL_IOMMU
Ben Widawsky2911a352012-04-05 14:47:36 -0700466 /* Enable semaphores on SNB when IO remapping is off */
Daniel Vetter59de3292012-04-02 20:48:43 +0200467 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
468 return false;
469#endif
Ben Widawsky2911a352012-04-05 14:47:36 -0700470
471 return 1;
472}
473
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100474static int i915_drm_freeze(struct drm_device *dev)
475{
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100476 struct drm_i915_private *dev_priv = dev->dev_private;
477
Zhang Ruib8efb172013-02-05 15:41:53 +0800478 /* ignore lid events during suspend */
479 mutex_lock(&dev_priv->modeset_restore_lock);
480 dev_priv->modeset_restore = MODESET_SUSPENDED;
481 mutex_unlock(&dev_priv->modeset_restore_lock);
482
Paulo Zanonicb107992013-01-25 16:59:15 -0200483 intel_set_power_well(dev, true);
484
Dave Airlie5bcf7192010-12-07 09:20:40 +1000485 drm_kms_helper_poll_disable(dev);
486
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100487 pci_save_state(dev->pdev);
488
489 /* If KMS is active, we do the leavevt stuff here */
490 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
491 int error = i915_gem_idle(dev);
492 if (error) {
493 dev_err(&dev->pdev->dev,
494 "GEM idle failed, resume might fail\n");
495 return error;
496 }
Daniel Vettera261b242012-07-26 19:21:47 +0200497
Jesse Barnes1a01ab32012-11-02 11:14:00 -0700498 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
499
Daniel Vettera261b242012-07-26 19:21:47 +0200500 intel_modeset_disable(dev);
501
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100502 drm_irq_uninstall(dev);
Daniel Vetter15239092013-03-05 09:50:58 +0100503 dev_priv->enable_hotplug_processing = false;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100504 }
505
506 i915_save_state(dev);
507
Chris Wilson44834a62010-08-19 16:09:23 +0100508 intel_opregion_fini(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100509
Dave Airlie3fa016a2012-03-28 10:48:49 +0100510 console_lock();
511 intel_fbdev_set_suspend(dev, 1);
512 console_unlock();
513
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100514 return 0;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100515}
516
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000517int i915_suspend(struct drm_device *dev, pm_message_t state)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100518{
519 int error;
520
521 if (!dev || !dev->dev_private) {
522 DRM_ERROR("dev: %p\n", dev);
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700523 DRM_ERROR("DRM not initialized, aborting suspend.\n");
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000524 return -ENODEV;
525 }
526
Dave Airlieb932ccb2008-02-20 10:02:20 +1000527 if (state.event == PM_EVENT_PRETHAW)
528 return 0;
529
Dave Airlie5bcf7192010-12-07 09:20:40 +1000530
531 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
532 return 0;
Chris Wilson6eecba32010-09-08 09:45:11 +0100533
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100534 error = i915_drm_freeze(dev);
535 if (error)
536 return error;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000537
Dave Airlieb932ccb2008-02-20 10:02:20 +1000538 if (state.event == PM_EVENT_SUSPEND) {
539 /* Shut down the device */
540 pci_disable_device(dev->pdev);
541 pci_set_power_state(dev->pdev, PCI_D3hot);
542 }
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000543
544 return 0;
545}
546
Jesse Barnes073f34d2012-11-02 11:13:59 -0700547void intel_console_resume(struct work_struct *work)
548{
549 struct drm_i915_private *dev_priv =
550 container_of(work, struct drm_i915_private,
551 console_resume_work);
552 struct drm_device *dev = dev_priv->dev;
553
554 console_lock();
555 intel_fbdev_set_suspend(dev, 0);
556 console_unlock();
557}
558
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700559static int __i915_drm_thaw(struct drm_device *dev)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000560{
Jesse Barnes5669fca2009-02-17 15:13:31 -0800561 struct drm_i915_private *dev_priv = dev->dev_private;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100562 int error = 0;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100563
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100564 i915_restore_state(dev);
Chris Wilson44834a62010-08-19 16:09:23 +0100565 intel_opregion_setup(dev);
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100566
Jesse Barnes5669fca2009-02-17 15:13:31 -0800567 /* KMS EnterVT equivalent */
568 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
Paulo Zanonidde86e22012-12-01 12:04:25 -0200569 intel_init_pch_refclk(dev);
Chris Wilson1833b132012-05-09 11:56:28 +0100570
Jesse Barnes5669fca2009-02-17 15:13:31 -0800571 mutex_lock(&dev->struct_mutex);
572 dev_priv->mm.suspended = 0;
573
Daniel Vetterf691e2f2012-02-02 09:58:12 +0100574 error = i915_gem_init_hw(dev);
Jesse Barnes5669fca2009-02-17 15:13:31 -0800575 mutex_unlock(&dev->struct_mutex);
Jesse Barnes226485e2009-02-23 15:41:09 -0800576
Daniel Vetter15239092013-03-05 09:50:58 +0100577 /* We need working interrupts for modeset enabling ... */
578 drm_irq_install(dev);
579
Chris Wilson1833b132012-05-09 11:56:28 +0100580 intel_modeset_init_hw(dev);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +0100581 intel_modeset_setup_hw_state(dev, false);
Daniel Vetter15239092013-03-05 09:50:58 +0100582
583 /*
584 * ... but also need to make sure that hotplug processing
585 * doesn't cause havoc. Like in the driver load code we don't
586 * bother with the tiny race here where we might loose hotplug
587 * notifications.
588 * */
Daniel Vetter20afbda2012-12-11 14:05:07 +0100589 intel_hpd_init(dev);
Daniel Vetter15239092013-03-05 09:50:58 +0100590 dev_priv->enable_hotplug_processing = true;
Jesse Barnesd5bb0812011-01-05 12:01:26 -0800591 }
Jesse Barnes1daed3f2011-01-05 12:01:25 -0800592
Chris Wilson44834a62010-08-19 16:09:23 +0100593 intel_opregion_init(dev);
594
Jesse Barnes073f34d2012-11-02 11:13:59 -0700595 /*
596 * The console lock can be pretty contented on resume due
597 * to all the printk activity. Try to keep it out of the hot
598 * path of resume if possible.
599 */
600 if (console_trylock()) {
601 intel_fbdev_set_suspend(dev, 0);
602 console_unlock();
603 } else {
604 schedule_work(&dev_priv->console_resume_work);
605 }
606
Zhang Ruib8efb172013-02-05 15:41:53 +0800607 mutex_lock(&dev_priv->modeset_restore_lock);
608 dev_priv->modeset_restore = MODESET_DONE;
609 mutex_unlock(&dev_priv->modeset_restore_lock);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100610 return error;
611}
612
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700613static int i915_drm_thaw(struct drm_device *dev)
614{
615 int error = 0;
616
617 intel_gt_reset(dev);
618
619 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
620 mutex_lock(&dev->struct_mutex);
621 i915_gem_restore_gtt_mappings(dev);
622 mutex_unlock(&dev->struct_mutex);
623 }
624
625 __i915_drm_thaw(dev);
626
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100627 return error;
628}
629
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000630int i915_resume(struct drm_device *dev)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100631{
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700632 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson6eecba32010-09-08 09:45:11 +0100633 int ret;
634
Dave Airlie5bcf7192010-12-07 09:20:40 +1000635 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
636 return 0;
637
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100638 if (pci_enable_device(dev->pdev))
639 return -EIO;
640
641 pci_set_master(dev->pdev);
642
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700643 intel_gt_reset(dev);
644
645 /*
646 * Platforms with opregion should have sane BIOS, older ones (gen3 and
647 * earlier) need this since the BIOS might clear all our scratch PTEs.
648 */
649 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
650 !dev_priv->opregion.header) {
651 mutex_lock(&dev->struct_mutex);
652 i915_gem_restore_gtt_mappings(dev);
653 mutex_unlock(&dev->struct_mutex);
654 }
655
656 ret = __i915_drm_thaw(dev);
Chris Wilson6eecba32010-09-08 09:45:11 +0100657 if (ret)
658 return ret;
659
660 drm_kms_helper_poll_enable(dev);
661 return 0;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000662}
663
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200664static int i8xx_do_reset(struct drm_device *dev)
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100665{
666 struct drm_i915_private *dev_priv = dev->dev_private;
667
668 if (IS_I85X(dev))
669 return -ENODEV;
670
671 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
672 POSTING_READ(D_STATE);
673
674 if (IS_I830(dev) || IS_845G(dev)) {
675 I915_WRITE(DEBUG_RESET_I830,
676 DEBUG_RESET_DISPLAY |
677 DEBUG_RESET_RENDER |
678 DEBUG_RESET_FULL);
679 POSTING_READ(DEBUG_RESET_I830);
680 msleep(1);
681
682 I915_WRITE(DEBUG_RESET_I830, 0);
683 POSTING_READ(DEBUG_RESET_I830);
684 }
685
686 msleep(1);
687
688 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
689 POSTING_READ(D_STATE);
690
691 return 0;
692}
693
Kenneth Graunkef49f0582010-09-11 01:19:14 -0700694static int i965_reset_complete(struct drm_device *dev)
695{
696 u8 gdrst;
Kenneth Graunkeeeccdca2010-09-11 01:24:50 -0700697 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
Daniel Vetter5fe9fe82012-05-02 21:33:52 +0200698 return (gdrst & GRDOM_RESET_ENABLE) == 0;
Kenneth Graunkef49f0582010-09-11 01:19:14 -0700699}
700
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200701static int i965_do_reset(struct drm_device *dev)
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700702{
Daniel Vetter5ccce182012-04-27 15:17:45 +0200703 int ret;
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700704 u8 gdrst;
705
Chris Wilsonae681d92010-10-01 14:57:56 +0100706 /*
707 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
708 * well as the reset bit (GR/bit 0). Setting the GR bit
709 * triggers the reset; when done, the hardware will clear it.
710 */
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700711 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200712 pci_write_config_byte(dev->pdev, I965_GDRST,
Daniel Vetter5ccce182012-04-27 15:17:45 +0200713 gdrst | GRDOM_RENDER |
714 GRDOM_RESET_ENABLE);
715 ret = wait_for(i965_reset_complete(dev), 500);
716 if (ret)
717 return ret;
718
719 /* We can't reset render&media without also resetting display ... */
720 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
721 pci_write_config_byte(dev->pdev, I965_GDRST,
722 gdrst | GRDOM_MEDIA |
723 GRDOM_RESET_ENABLE);
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700724
725 return wait_for(i965_reset_complete(dev), 500);
726}
727
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200728static int ironlake_do_reset(struct drm_device *dev)
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700729{
730 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter5ccce182012-04-27 15:17:45 +0200731 u32 gdrst;
732 int ret;
733
734 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200735 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
Daniel Vetter5ccce182012-04-27 15:17:45 +0200736 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
737 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
738 if (ret)
739 return ret;
740
741 /* We can't reset render&media without also resetting display ... */
742 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
743 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
744 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700745 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700746}
747
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200748static int gen6_do_reset(struct drm_device *dev)
Eric Anholtcff458c2010-11-18 09:31:14 +0800749{
750 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packardb6e45f82012-01-06 11:34:04 -0800751 int ret;
752 unsigned long irqflags;
Eric Anholtcff458c2010-11-18 09:31:14 +0800753
Keith Packard286fed42012-01-06 11:44:11 -0800754 /* Hold gt_lock across reset to prevent any register access
755 * with forcewake not set correctly
756 */
Keith Packardb6e45f82012-01-06 11:34:04 -0800757 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
Keith Packard286fed42012-01-06 11:44:11 -0800758
759 /* Reset the chip */
760
761 /* GEN6_GDRST is not in the gt power well, no need to check
762 * for fifo space for the write or forcewake the chip for
763 * the read
764 */
765 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
766
767 /* Spin waiting for the device to ack the reset request */
768 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
769
770 /* If reset with a user forcewake, try to restore, otherwise turn it off */
Keith Packardb6e45f82012-01-06 11:34:04 -0800771 if (dev_priv->forcewake_count)
Chris Wilson990bbda2012-07-02 11:51:02 -0300772 dev_priv->gt.force_wake_get(dev_priv);
Keith Packard286fed42012-01-06 11:44:11 -0800773 else
Chris Wilson990bbda2012-07-02 11:51:02 -0300774 dev_priv->gt.force_wake_put(dev_priv);
Keith Packard286fed42012-01-06 11:44:11 -0800775
776 /* Restore fifo count */
777 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
778
Keith Packardb6e45f82012-01-06 11:34:04 -0800779 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
780 return ret;
Eric Anholtcff458c2010-11-18 09:31:14 +0800781}
782
Ben Widawsky8e96d9c2012-06-04 14:42:56 -0700783int intel_gpu_reset(struct drm_device *dev)
Daniel Vetter350d2702012-04-27 15:17:42 +0200784{
Daniel Vetter2b9dc9a2012-04-27 15:17:43 +0200785 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter350d2702012-04-27 15:17:42 +0200786 int ret = -ENODEV;
787
788 switch (INTEL_INFO(dev)->gen) {
789 case 7:
790 case 6:
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200791 ret = gen6_do_reset(dev);
Daniel Vetter350d2702012-04-27 15:17:42 +0200792 break;
793 case 5:
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200794 ret = ironlake_do_reset(dev);
Daniel Vetter350d2702012-04-27 15:17:42 +0200795 break;
796 case 4:
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200797 ret = i965_do_reset(dev);
Daniel Vetter350d2702012-04-27 15:17:42 +0200798 break;
799 case 2:
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200800 ret = i8xx_do_reset(dev);
Daniel Vetter350d2702012-04-27 15:17:42 +0200801 break;
802 }
803
Daniel Vetter2b9dc9a2012-04-27 15:17:43 +0200804 /* Also reset the gpu hangman. */
Daniel Vetter99584db2012-11-14 17:14:04 +0100805 if (dev_priv->gpu_error.stop_rings) {
Daniel Vetter2b9dc9a2012-04-27 15:17:43 +0200806 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
Daniel Vetter99584db2012-11-14 17:14:04 +0100807 dev_priv->gpu_error.stop_rings = 0;
Daniel Vetter2b9dc9a2012-04-27 15:17:43 +0200808 if (ret == -ENODEV) {
809 DRM_ERROR("Reset not implemented, but ignoring "
810 "error for simulated gpu hangs\n");
811 ret = 0;
812 }
813 }
814
Daniel Vetter350d2702012-04-27 15:17:42 +0200815 return ret;
816}
817
Ben Gamari11ed50e2009-09-14 17:48:45 -0400818/**
Eugeni Dodonovf3953dc2011-11-28 16:15:17 -0200819 * i915_reset - reset chip after a hang
Ben Gamari11ed50e2009-09-14 17:48:45 -0400820 * @dev: drm device to reset
Ben Gamari11ed50e2009-09-14 17:48:45 -0400821 *
822 * Reset the chip. Useful if a hang is detected. Returns zero on successful
823 * reset or otherwise an error code.
824 *
825 * Procedure is fairly simple:
826 * - reset the chip using the reset reg
827 * - re-init context state
828 * - re-init hardware status page
829 * - re-init ring buffer
830 * - re-init interrupt state
831 * - re-init display
832 */
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200833int i915_reset(struct drm_device *dev)
Ben Gamari11ed50e2009-09-14 17:48:45 -0400834{
835 drm_i915_private_t *dev_priv = dev->dev_private;
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700836 int ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400837
Chris Wilsond78cb502010-12-23 13:33:15 +0000838 if (!i915_try_reset)
839 return 0;
840
Daniel Vetterd54a02c2012-07-04 22:18:39 +0200841 mutex_lock(&dev->struct_mutex);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400842
Chris Wilson069efc12010-09-30 16:53:18 +0100843 i915_gem_reset(dev);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400844
Chris Wilsonf803aa52010-09-19 12:38:26 +0100845 ret = -ENODEV;
Daniel Vetter99584db2012-11-14 17:14:04 +0100846 if (get_seconds() - dev_priv->gpu_error.last_reset < 5)
Chris Wilsonae681d92010-10-01 14:57:56 +0100847 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
Daniel Vetter350d2702012-04-27 15:17:42 +0200848 else
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200849 ret = intel_gpu_reset(dev);
Daniel Vetter350d2702012-04-27 15:17:42 +0200850
Daniel Vetter99584db2012-11-14 17:14:04 +0100851 dev_priv->gpu_error.last_reset = get_seconds();
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700852 if (ret) {
Chris Wilsonf803aa52010-09-19 12:38:26 +0100853 DRM_ERROR("Failed to reset chip.\n");
Daniel J Bluemanf953c932010-05-17 14:23:52 +0100854 mutex_unlock(&dev->struct_mutex);
Chris Wilsonf803aa52010-09-19 12:38:26 +0100855 return ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400856 }
857
858 /* Ok, now get things going again... */
859
860 /*
861 * Everything depends on having the GTT running, so we need to start
862 * there. Fortunately we don't need to do this unless we reset the
863 * chip at a PCI level.
864 *
865 * Next we need to restore the context, but we don't use those
866 * yet either...
867 *
868 * Ring buffer needs to be re-initialized in the KMS case, or if X
869 * was running at the time of the reset (i.e. we weren't VT
870 * switched away).
871 */
872 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800873 !dev_priv->mm.suspended) {
Chris Wilsonb4519512012-05-11 14:29:30 +0100874 struct intel_ring_buffer *ring;
875 int i;
876
Ben Gamari11ed50e2009-09-14 17:48:45 -0400877 dev_priv->mm.suspended = 0;
Eric Anholt75a68982010-11-18 09:31:13 +0800878
Daniel Vetterf691e2f2012-02-02 09:58:12 +0100879 i915_gem_init_swizzling(dev);
880
Chris Wilsonb4519512012-05-11 14:29:30 +0100881 for_each_ring(ring, dev_priv, i)
882 ring->init(ring);
Eric Anholt75a68982010-11-18 09:31:13 +0800883
Ben Widawsky254f9652012-06-04 14:42:42 -0700884 i915_gem_context_init(dev);
Daniel Vettere21af882012-02-09 20:53:27 +0100885 i915_gem_init_ppgtt(dev);
886
Daniel Vetter8e88a2b2012-06-19 18:40:00 +0200887 /*
888 * It would make sense to re-init all the other hw state, at
889 * least the rps/rc6/emon init done within modeset_init_hw. For
890 * some unknown reason, this blows up my ilk, so don't.
891 */
Daniel Vetterf8175862012-04-10 15:50:11 +0200892
Daniel Vetter8e88a2b2012-06-19 18:40:00 +0200893 mutex_unlock(&dev->struct_mutex);
Daniel Vetterf8175862012-04-10 15:50:11 +0200894
Ben Gamari11ed50e2009-09-14 17:48:45 -0400895 drm_irq_uninstall(dev);
896 drm_irq_install(dev);
Daniel Vetter20afbda2012-12-11 14:05:07 +0100897 intel_hpd_init(dev);
Daniel Vetterbcbc3242012-04-27 15:17:41 +0200898 } else {
899 mutex_unlock(&dev->struct_mutex);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400900 }
901
Ben Gamari11ed50e2009-09-14 17:48:45 -0400902 return 0;
903}
904
Greg Kroah-Hartman56550d92012-12-21 15:09:25 -0800905static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500906{
Daniel Vetter01a06852012-06-25 15:58:49 +0200907 struct intel_device_info *intel_info =
908 (struct intel_device_info *) ent->driver_data;
909
Paulo Zanoni70b12bb2012-11-20 13:32:30 -0200910 if (intel_info->is_valleyview)
Rodrigo Vivi0a3af262012-10-15 17:16:23 -0300911 if(!i915_preliminary_hw_support) {
912 DRM_ERROR("Preliminary hardware support disabled\n");
913 return -ENODEV;
914 }
915
Chris Wilson5fe49d82011-02-01 19:43:02 +0000916 /* Only bind to function 0 of the device. Early generations
917 * used function 1 as a placeholder for multi-head. This causes
918 * us confusion instead, especially on the systems where both
919 * functions have the same PCI-ID!
920 */
921 if (PCI_FUNC(pdev->devfn))
922 return -ENODEV;
923
Daniel Vetter01a06852012-06-25 15:58:49 +0200924 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
925 * implementation for gen3 (and only gen3) that used legacy drm maps
926 * (gasp!) to share buffers between X and the client. Hence we need to
927 * keep around the fake agp stuff for gen3, even when kms is enabled. */
928 if (intel_info->gen != 3) {
929 driver.driver_features &=
930 ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
931 } else if (!intel_agp_enabled) {
932 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
933 return -ENODEV;
934 }
935
Jordan Crousedcdb1672010-05-27 13:40:25 -0600936 return drm_get_pci_dev(pdev, ent, &driver);
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500937}
938
939static void
940i915_pci_remove(struct pci_dev *pdev)
941{
942 struct drm_device *dev = pci_get_drvdata(pdev);
943
944 drm_put_dev(dev);
945}
946
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100947static int i915_pm_suspend(struct device *dev)
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500948{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100949 struct pci_dev *pdev = to_pci_dev(dev);
950 struct drm_device *drm_dev = pci_get_drvdata(pdev);
951 int error;
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500952
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100953 if (!drm_dev || !drm_dev->dev_private) {
954 dev_err(dev, "DRM not initialized, aborting suspend.\n");
955 return -ENODEV;
956 }
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500957
Dave Airlie5bcf7192010-12-07 09:20:40 +1000958 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
959 return 0;
960
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100961 error = i915_drm_freeze(drm_dev);
962 if (error)
963 return error;
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500964
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100965 pci_disable_device(pdev);
966 pci_set_power_state(pdev, PCI_D3hot);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800967
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800968 return 0;
969}
970
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100971static int i915_pm_resume(struct device *dev)
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800972{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100973 struct pci_dev *pdev = to_pci_dev(dev);
974 struct drm_device *drm_dev = pci_get_drvdata(pdev);
975
976 return i915_resume(drm_dev);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800977}
978
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100979static int i915_pm_freeze(struct device *dev)
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800980{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100981 struct pci_dev *pdev = to_pci_dev(dev);
982 struct drm_device *drm_dev = pci_get_drvdata(pdev);
983
984 if (!drm_dev || !drm_dev->dev_private) {
985 dev_err(dev, "DRM not initialized, aborting suspend.\n");
986 return -ENODEV;
987 }
988
989 return i915_drm_freeze(drm_dev);
990}
991
992static int i915_pm_thaw(struct device *dev)
993{
994 struct pci_dev *pdev = to_pci_dev(dev);
995 struct drm_device *drm_dev = pci_get_drvdata(pdev);
996
997 return i915_drm_thaw(drm_dev);
998}
999
1000static int i915_pm_poweroff(struct device *dev)
1001{
1002 struct pci_dev *pdev = to_pci_dev(dev);
1003 struct drm_device *drm_dev = pci_get_drvdata(pdev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001004
Rafael J. Wysocki61caf872010-02-18 23:06:27 +01001005 return i915_drm_freeze(drm_dev);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001006}
1007
Chris Wilsonb4b78d12010-06-06 15:40:20 +01001008static const struct dev_pm_ops i915_pm_ops = {
Akshay Joshi0206e352011-08-16 15:34:10 -04001009 .suspend = i915_pm_suspend,
1010 .resume = i915_pm_resume,
1011 .freeze = i915_pm_freeze,
1012 .thaw = i915_pm_thaw,
1013 .poweroff = i915_pm_poweroff,
1014 .restore = i915_pm_resume,
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001015};
1016
Laurent Pinchart78b68552012-05-17 13:27:22 +02001017static const struct vm_operations_struct i915_gem_vm_ops = {
Jesse Barnesde151cf2008-11-12 10:03:55 -08001018 .fault = i915_gem_fault,
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001019 .open = drm_gem_vm_open,
1020 .close = drm_gem_vm_close,
Jesse Barnesde151cf2008-11-12 10:03:55 -08001021};
1022
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001023static const struct file_operations i915_driver_fops = {
1024 .owner = THIS_MODULE,
1025 .open = drm_open,
1026 .release = drm_release,
1027 .unlocked_ioctl = drm_ioctl,
1028 .mmap = drm_gem_mmap,
1029 .poll = drm_poll,
1030 .fasync = drm_fasync,
1031 .read = drm_read,
1032#ifdef CONFIG_COMPAT
1033 .compat_ioctl = i915_compat_ioctl,
1034#endif
1035 .llseek = noop_llseek,
1036};
1037
Linus Torvalds1da177e2005-04-16 15:20:36 -07001038static struct drm_driver driver = {
Michael Witten0c547812011-08-25 17:55:54 +00001039 /* Don't use MTRRs here; the Xserver or userspace app should
1040 * deal with them for Intel hardware.
Dave Airlie792d2b92005-11-11 23:30:27 +11001041 */
Eric Anholt673a3942008-07-30 12:06:12 -07001042 .driver_features =
1043 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
Daniel Vetter1286ff72012-05-10 15:25:09 +02001044 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
Dave Airlie22eae942005-11-10 22:16:34 +11001045 .load = i915_driver_load,
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001046 .unload = i915_driver_unload,
Eric Anholt673a3942008-07-30 12:06:12 -07001047 .open = i915_driver_open,
Dave Airlie22eae942005-11-10 22:16:34 +11001048 .lastclose = i915_driver_lastclose,
1049 .preclose = i915_driver_preclose,
Eric Anholt673a3942008-07-30 12:06:12 -07001050 .postclose = i915_driver_postclose,
Rafael J. Wysockid8e29202010-01-09 00:45:33 +01001051
1052 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1053 .suspend = i915_suspend,
1054 .resume = i915_resume,
1055
Dave Airliecda17382005-07-10 17:31:26 +10001056 .device_is_agp = i915_driver_device_is_agp,
Dave Airlie7c1c2872008-11-28 14:22:24 +10001057 .master_create = i915_master_create,
1058 .master_destroy = i915_master_destroy,
Ben Gamari955b12d2009-02-17 20:08:49 -05001059#if defined(CONFIG_DEBUG_FS)
Ben Gamari27c202a2009-07-01 22:26:52 -04001060 .debugfs_init = i915_debugfs_init,
1061 .debugfs_cleanup = i915_debugfs_cleanup,
Ben Gamari955b12d2009-02-17 20:08:49 -05001062#endif
Eric Anholt673a3942008-07-30 12:06:12 -07001063 .gem_init_object = i915_gem_init_object,
1064 .gem_free_object = i915_gem_free_object,
Jesse Barnesde151cf2008-11-12 10:03:55 -08001065 .gem_vm_ops = &i915_gem_vm_ops,
Daniel Vetter1286ff72012-05-10 15:25:09 +02001066
1067 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1068 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1069 .gem_prime_export = i915_gem_prime_export,
1070 .gem_prime_import = i915_gem_prime_import,
1071
Dave Airlieff72145b2011-02-07 12:16:14 +10001072 .dumb_create = i915_gem_dumb_create,
1073 .dumb_map_offset = i915_gem_mmap_gtt,
1074 .dumb_destroy = i915_gem_dumb_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001075 .ioctls = i915_ioctls,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001076 .fops = &i915_driver_fops,
Dave Airlie22eae942005-11-10 22:16:34 +11001077 .name = DRIVER_NAME,
1078 .desc = DRIVER_DESC,
1079 .date = DRIVER_DATE,
1080 .major = DRIVER_MAJOR,
1081 .minor = DRIVER_MINOR,
1082 .patchlevel = DRIVER_PATCHLEVEL,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001083};
1084
Dave Airlie8410ea32010-12-15 03:16:38 +10001085static struct pci_driver i915_pci_driver = {
1086 .name = DRIVER_NAME,
1087 .id_table = pciidlist,
1088 .probe = i915_pci_probe,
1089 .remove = i915_pci_remove,
1090 .driver.pm = &i915_pm_ops,
1091};
1092
Linus Torvalds1da177e2005-04-16 15:20:36 -07001093static int __init i915_init(void)
1094{
1095 driver.num_ioctls = i915_max_ioctl;
Jesse Barnes79e53942008-11-07 14:24:08 -08001096
1097 /*
1098 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1099 * explicitly disabled with the module pararmeter.
1100 *
1101 * Otherwise, just follow the parameter (defaulting to off).
1102 *
1103 * Allow optional vga_text_mode_force boot option to override
1104 * the default behavior.
1105 */
1106#if defined(CONFIG_DRM_I915_KMS)
1107 if (i915_modeset != 0)
1108 driver.driver_features |= DRIVER_MODESET;
1109#endif
1110 if (i915_modeset == 1)
1111 driver.driver_features |= DRIVER_MODESET;
1112
1113#ifdef CONFIG_VGA_CONSOLE
1114 if (vgacon_text_force() && i915_modeset == -1)
1115 driver.driver_features &= ~DRIVER_MODESET;
1116#endif
1117
Chris Wilson3885c6b2011-01-23 10:45:14 +00001118 if (!(driver.driver_features & DRIVER_MODESET))
1119 driver.get_vblank_timestamp = NULL;
1120
Dave Airlie8410ea32010-12-15 03:16:38 +10001121 return drm_pci_init(&driver, &i915_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001122}
1123
1124static void __exit i915_exit(void)
1125{
Dave Airlie8410ea32010-12-15 03:16:38 +10001126 drm_pci_exit(&driver, &i915_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001127}
1128
1129module_init(i915_init);
1130module_exit(i915_exit);
1131
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001132MODULE_AUTHOR(DRIVER_AUTHOR);
1133MODULE_DESCRIPTION(DRIVER_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001134MODULE_LICENSE("GPL and additional rights");
Andi Kleenf7000882011-10-13 16:08:51 -07001135
Jesse Barnesb7d84092012-03-22 14:38:43 -07001136/* We give fast paths for the really cool registers */
1137#define NEEDS_FORCE_WAKE(dev_priv, reg) \
Daniel Vetterb7884eb2012-06-04 11:18:15 +02001138 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1139 ((reg) < 0x40000) && \
1140 ((reg) != FORCEWAKE))
Daniel Vettera8b13972012-10-18 14:16:09 +02001141static void
1142ilk_dummy_write(struct drm_i915_private *dev_priv)
1143{
1144 /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
1145 * chip from rc6 before touching it for real. MI_MODE is masked, hence
1146 * harmless to write 0 into. */
1147 I915_WRITE_NOTRACE(MI_MODE, 0);
1148}
1149
Andi Kleenf7000882011-10-13 16:08:51 -07001150#define __i915_read(x, y) \
1151u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1152 u##x val = 0; \
Daniel Vettera8b13972012-10-18 14:16:09 +02001153 if (IS_GEN5(dev_priv->dev)) \
1154 ilk_dummy_write(dev_priv); \
Andi Kleenf7000882011-10-13 16:08:51 -07001155 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
Keith Packardc9375042012-01-06 11:48:38 -08001156 unsigned long irqflags; \
1157 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1158 if (dev_priv->forcewake_count == 0) \
Chris Wilson990bbda2012-07-02 11:51:02 -03001159 dev_priv->gt.force_wake_get(dev_priv); \
Andi Kleenf7000882011-10-13 16:08:51 -07001160 val = read##y(dev_priv->regs + reg); \
Keith Packardc9375042012-01-06 11:48:38 -08001161 if (dev_priv->forcewake_count == 0) \
Chris Wilson990bbda2012-07-02 11:51:02 -03001162 dev_priv->gt.force_wake_put(dev_priv); \
Keith Packardc9375042012-01-06 11:48:38 -08001163 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
Andi Kleenf7000882011-10-13 16:08:51 -07001164 } else { \
1165 val = read##y(dev_priv->regs + reg); \
1166 } \
1167 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1168 return val; \
1169}
1170
1171__i915_read(8, b)
1172__i915_read(16, w)
1173__i915_read(32, l)
1174__i915_read(64, q)
1175#undef __i915_read
1176
1177#define __i915_write(x, y) \
1178void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
Ben Widawsky67a37442012-02-09 10:15:20 +01001179 u32 __fifo_ret = 0; \
Andi Kleenf7000882011-10-13 16:08:51 -07001180 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1181 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
Ben Widawsky67a37442012-02-09 10:15:20 +01001182 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
Andi Kleenf7000882011-10-13 16:08:51 -07001183 } \
Daniel Vettera8b13972012-10-18 14:16:09 +02001184 if (IS_GEN5(dev_priv->dev)) \
1185 ilk_dummy_write(dev_priv); \
Paulo Zanonic54e5902012-11-20 13:27:38 -02001186 if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1187 DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
1188 I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
1189 } \
Ville Syrjäläfe31b572013-01-25 21:44:47 +02001190 write##y(val, dev_priv->regs + reg); \
Ben Widawsky67a37442012-02-09 10:15:20 +01001191 if (unlikely(__fifo_ret)) { \
1192 gen6_gt_check_fifodbg(dev_priv); \
1193 } \
Ben Widawskyb4c145c2012-08-20 16:15:14 -07001194 if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1195 DRM_ERROR("Unclaimed write to %x\n", reg); \
1196 writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT); \
1197 } \
Andi Kleenf7000882011-10-13 16:08:51 -07001198}
1199__i915_write(8, b)
1200__i915_write(16, w)
1201__i915_write(32, l)
1202__i915_write(64, q)
1203#undef __i915_write
Ben Widawskyc0c7bab2012-07-12 11:01:05 -07001204
1205static const struct register_whitelist {
1206 uint64_t offset;
1207 uint32_t size;
1208 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1209} whitelist[] = {
1210 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1211};
1212
1213int i915_reg_read_ioctl(struct drm_device *dev,
1214 void *data, struct drm_file *file)
1215{
1216 struct drm_i915_private *dev_priv = dev->dev_private;
1217 struct drm_i915_reg_read *reg = data;
1218 struct register_whitelist const *entry = whitelist;
1219 int i;
1220
1221 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1222 if (entry->offset == reg->offset &&
1223 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1224 break;
1225 }
1226
1227 if (i == ARRAY_SIZE(whitelist))
1228 return -EINVAL;
1229
1230 switch (entry->size) {
1231 case 8:
1232 reg->val = I915_READ64(reg->offset);
1233 break;
1234 case 4:
1235 reg->val = I915_READ(reg->offset);
1236 break;
1237 case 2:
1238 reg->val = I915_READ16(reg->offset);
1239 break;
1240 case 1:
1241 reg->val = I915_READ8(reg->offset);
1242 break;
1243 default:
1244 WARN_ON(1);
1245 return -EINVAL;
1246 }
1247
1248 return 0;
1249}