Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Keith Packard <keithp@keithp.com> |
| 26 | * |
| 27 | */ |
| 28 | |
| 29 | #include <linux/seq_file.h> |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 30 | #include <linux/circ_buf.h> |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 31 | #include <linux/ctype.h> |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 32 | #include <linux/debugfs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 33 | #include <linux/slab.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 34 | #include <linux/export.h> |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 35 | #include <linux/list_sort.h> |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 36 | #include <asm/msr-index.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 37 | #include <drm/drmP.h> |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 38 | #include "intel_drv.h" |
Chris Wilson | e5c6526 | 2010-11-01 11:35:28 +0000 | [diff] [blame] | 39 | #include "intel_ringbuffer.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 40 | #include <drm/i915_drm.h> |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 41 | #include "i915_drv.h" |
| 42 | |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 43 | enum { |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 44 | ACTIVE_LIST, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 45 | INACTIVE_LIST, |
Chris Wilson | d21d597 | 2010-09-26 11:19:33 +0100 | [diff] [blame] | 46 | PINNED_LIST, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 47 | }; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 48 | |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 49 | static const char *yesno(int v) |
| 50 | { |
| 51 | return v ? "yes" : "no"; |
| 52 | } |
| 53 | |
Damien Lespiau | 497666d | 2013-10-15 18:55:39 +0100 | [diff] [blame] | 54 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
| 55 | * allocated we need to hook into the minor for release. */ |
| 56 | static int |
| 57 | drm_add_fake_info_node(struct drm_minor *minor, |
| 58 | struct dentry *ent, |
| 59 | const void *key) |
| 60 | { |
| 61 | struct drm_info_node *node; |
| 62 | |
| 63 | node = kmalloc(sizeof(*node), GFP_KERNEL); |
| 64 | if (node == NULL) { |
| 65 | debugfs_remove(ent); |
| 66 | return -ENOMEM; |
| 67 | } |
| 68 | |
| 69 | node->minor = minor; |
| 70 | node->dent = ent; |
| 71 | node->info_ent = (void *) key; |
| 72 | |
| 73 | mutex_lock(&minor->debugfs_lock); |
| 74 | list_add(&node->list, &minor->debugfs_list); |
| 75 | mutex_unlock(&minor->debugfs_lock); |
| 76 | |
| 77 | return 0; |
| 78 | } |
| 79 | |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 80 | static int i915_capabilities(struct seq_file *m, void *data) |
| 81 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 82 | struct drm_info_node *node = m->private; |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 83 | struct drm_device *dev = node->minor->dev; |
| 84 | const struct intel_device_info *info = INTEL_INFO(dev); |
| 85 | |
| 86 | seq_printf(m, "gen: %d\n", info->gen); |
Paulo Zanoni | 03d00ac | 2011-10-14 18:17:41 -0300 | [diff] [blame] | 87 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 88 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
| 89 | #define SEP_SEMICOLON ; |
| 90 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); |
| 91 | #undef PRINT_FLAG |
| 92 | #undef SEP_SEMICOLON |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 93 | |
| 94 | return 0; |
| 95 | } |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 96 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 97 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 98 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 99 | if (obj->user_pin_count > 0) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 100 | return "P"; |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 101 | else if (i915_gem_obj_is_pinned(obj)) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 102 | return "p"; |
| 103 | else |
| 104 | return " "; |
| 105 | } |
| 106 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 107 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 108 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 109 | switch (obj->tiling_mode) { |
| 110 | default: |
| 111 | case I915_TILING_NONE: return " "; |
| 112 | case I915_TILING_X: return "X"; |
| 113 | case I915_TILING_Y: return "Y"; |
| 114 | } |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 115 | } |
| 116 | |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 117 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
| 118 | { |
| 119 | return obj->has_global_gtt_mapping ? "g" : " "; |
| 120 | } |
| 121 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 122 | static void |
| 123 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) |
| 124 | { |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 125 | struct i915_vma *vma; |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 126 | int pin_count = 0; |
| 127 | |
Ville Syrjälä | fb1ae91 | 2013-08-22 19:21:30 +0300 | [diff] [blame] | 128 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 129 | &obj->base, |
| 130 | get_pin_flag(obj), |
| 131 | get_tiling_flag(obj), |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 132 | get_global_flag(obj), |
Eric Anholt | a05a586 | 2011-12-20 08:54:15 -0800 | [diff] [blame] | 133 | obj->base.size / 1024, |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 134 | obj->base.read_domains, |
| 135 | obj->base.write_domain, |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 136 | obj->last_read_seqno, |
| 137 | obj->last_write_seqno, |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 138 | obj->last_fenced_seqno, |
Mika Kuoppala | 84734a0 | 2013-07-12 16:50:57 +0300 | [diff] [blame] | 139 | i915_cache_level_str(obj->cache_level), |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 140 | obj->dirty ? " dirty" : "", |
| 141 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); |
| 142 | if (obj->base.name) |
| 143 | seq_printf(m, " (name: %d)", obj->base.name); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 144 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 145 | if (vma->pin_count > 0) |
| 146 | pin_count++; |
| 147 | seq_printf(m, " (pinned x %d)", pin_count); |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 148 | if (obj->pin_display) |
| 149 | seq_printf(m, " (display)"); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 150 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
| 151 | seq_printf(m, " (fence: %d)", obj->fence_reg); |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 152 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
| 153 | if (!i915_is_ggtt(vma->vm)) |
| 154 | seq_puts(m, " (pp"); |
| 155 | else |
| 156 | seq_puts(m, " (g"); |
| 157 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", |
| 158 | vma->node.start, vma->node.size); |
| 159 | } |
Chris Wilson | c1ad11f | 2012-11-15 11:32:21 +0000 | [diff] [blame] | 160 | if (obj->stolen) |
| 161 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 162 | if (obj->pin_mappable || obj->fault_mappable) { |
| 163 | char s[3], *t = s; |
| 164 | if (obj->pin_mappable) |
| 165 | *t++ = 'p'; |
| 166 | if (obj->fault_mappable) |
| 167 | *t++ = 'f'; |
| 168 | *t = '\0'; |
| 169 | seq_printf(m, " (%s mappable)", s); |
| 170 | } |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 171 | if (obj->ring != NULL) |
| 172 | seq_printf(m, " (%s)", obj->ring->name); |
Daniel Vetter | d5a81ef | 2014-06-18 14:46:49 +0200 | [diff] [blame] | 173 | if (obj->frontbuffer_bits) |
| 174 | seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 175 | } |
| 176 | |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 177 | static void describe_ctx(struct seq_file *m, struct intel_context *ctx) |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 178 | { |
Oscar Mateo | ea0c76f | 2014-07-03 16:27:59 +0100 | [diff] [blame] | 179 | seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i'); |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 180 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
| 181 | seq_putc(m, ' '); |
| 182 | } |
| 183 | |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 184 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 185 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 186 | struct drm_info_node *node = m->private; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 187 | uintptr_t list = (uintptr_t) node->info_ent->data; |
| 188 | struct list_head *head; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 189 | struct drm_device *dev = node->minor->dev; |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 190 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 191 | struct i915_address_space *vm = &dev_priv->gtt.base; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 192 | struct i915_vma *vma; |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 193 | size_t total_obj_size, total_gtt_size; |
| 194 | int count, ret; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 195 | |
| 196 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 197 | if (ret) |
| 198 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 199 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 200 | /* FIXME: the user of this interface might want more than just GGTT */ |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 201 | switch (list) { |
| 202 | case ACTIVE_LIST: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 203 | seq_puts(m, "Active:\n"); |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 204 | head = &vm->active_list; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 205 | break; |
| 206 | case INACTIVE_LIST: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 207 | seq_puts(m, "Inactive:\n"); |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 208 | head = &vm->inactive_list; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 209 | break; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 210 | default: |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 211 | mutex_unlock(&dev->struct_mutex); |
| 212 | return -EINVAL; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 213 | } |
| 214 | |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 215 | total_obj_size = total_gtt_size = count = 0; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 216 | list_for_each_entry(vma, head, mm_list) { |
| 217 | seq_printf(m, " "); |
| 218 | describe_obj(m, vma->obj); |
| 219 | seq_printf(m, "\n"); |
| 220 | total_obj_size += vma->obj->base.size; |
| 221 | total_gtt_size += vma->node.size; |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 222 | count++; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 223 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 224 | mutex_unlock(&dev->struct_mutex); |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 225 | |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 226 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 227 | count, total_obj_size, total_gtt_size); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 228 | return 0; |
| 229 | } |
| 230 | |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 231 | static int obj_rank_by_stolen(void *priv, |
| 232 | struct list_head *A, struct list_head *B) |
| 233 | { |
| 234 | struct drm_i915_gem_object *a = |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 235 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 236 | struct drm_i915_gem_object *b = |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 237 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 238 | |
| 239 | return a->stolen->start - b->stolen->start; |
| 240 | } |
| 241 | |
| 242 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) |
| 243 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 244 | struct drm_info_node *node = m->private; |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 245 | struct drm_device *dev = node->minor->dev; |
| 246 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 247 | struct drm_i915_gem_object *obj; |
| 248 | size_t total_obj_size, total_gtt_size; |
| 249 | LIST_HEAD(stolen); |
| 250 | int count, ret; |
| 251 | |
| 252 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 253 | if (ret) |
| 254 | return ret; |
| 255 | |
| 256 | total_obj_size = total_gtt_size = count = 0; |
| 257 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
| 258 | if (obj->stolen == NULL) |
| 259 | continue; |
| 260 | |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 261 | list_add(&obj->obj_exec_link, &stolen); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 262 | |
| 263 | total_obj_size += obj->base.size; |
| 264 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
| 265 | count++; |
| 266 | } |
| 267 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
| 268 | if (obj->stolen == NULL) |
| 269 | continue; |
| 270 | |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 271 | list_add(&obj->obj_exec_link, &stolen); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 272 | |
| 273 | total_obj_size += obj->base.size; |
| 274 | count++; |
| 275 | } |
| 276 | list_sort(NULL, &stolen, obj_rank_by_stolen); |
| 277 | seq_puts(m, "Stolen:\n"); |
| 278 | while (!list_empty(&stolen)) { |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 279 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 280 | seq_puts(m, " "); |
| 281 | describe_obj(m, obj); |
| 282 | seq_putc(m, '\n'); |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 283 | list_del_init(&obj->obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 284 | } |
| 285 | mutex_unlock(&dev->struct_mutex); |
| 286 | |
| 287 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 288 | count, total_obj_size, total_gtt_size); |
| 289 | return 0; |
| 290 | } |
| 291 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 292 | #define count_objects(list, member) do { \ |
| 293 | list_for_each_entry(obj, list, member) { \ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 294 | size += i915_gem_obj_ggtt_size(obj); \ |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 295 | ++count; \ |
| 296 | if (obj->map_and_fenceable) { \ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 297 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 298 | ++mappable_count; \ |
| 299 | } \ |
| 300 | } \ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 301 | } while (0) |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 302 | |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 303 | struct file_stats { |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 304 | struct drm_i915_file_private *file_priv; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 305 | int count; |
Chris Wilson | c67a17e | 2014-03-19 13:45:46 +0000 | [diff] [blame] | 306 | size_t total, unbound; |
| 307 | size_t global, shared; |
| 308 | size_t active, inactive; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 309 | }; |
| 310 | |
| 311 | static int per_file_stats(int id, void *ptr, void *data) |
| 312 | { |
| 313 | struct drm_i915_gem_object *obj = ptr; |
| 314 | struct file_stats *stats = data; |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 315 | struct i915_vma *vma; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 316 | |
| 317 | stats->count++; |
| 318 | stats->total += obj->base.size; |
| 319 | |
Chris Wilson | c67a17e | 2014-03-19 13:45:46 +0000 | [diff] [blame] | 320 | if (obj->base.name || obj->base.dma_buf) |
| 321 | stats->shared += obj->base.size; |
| 322 | |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 323 | if (USES_FULL_PPGTT(obj->base.dev)) { |
| 324 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
| 325 | struct i915_hw_ppgtt *ppgtt; |
| 326 | |
| 327 | if (!drm_mm_node_allocated(&vma->node)) |
| 328 | continue; |
| 329 | |
| 330 | if (i915_is_ggtt(vma->vm)) { |
| 331 | stats->global += obj->base.size; |
| 332 | continue; |
| 333 | } |
| 334 | |
| 335 | ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base); |
| 336 | if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv) |
| 337 | continue; |
| 338 | |
| 339 | if (obj->ring) /* XXX per-vma statistic */ |
| 340 | stats->active += obj->base.size; |
| 341 | else |
| 342 | stats->inactive += obj->base.size; |
| 343 | |
| 344 | return 0; |
| 345 | } |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 346 | } else { |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 347 | if (i915_gem_obj_ggtt_bound(obj)) { |
| 348 | stats->global += obj->base.size; |
| 349 | if (obj->ring) |
| 350 | stats->active += obj->base.size; |
| 351 | else |
| 352 | stats->inactive += obj->base.size; |
| 353 | return 0; |
| 354 | } |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 355 | } |
| 356 | |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 357 | if (!list_empty(&obj->global_list)) |
| 358 | stats->unbound += obj->base.size; |
| 359 | |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 360 | return 0; |
| 361 | } |
| 362 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 363 | #define count_vmas(list, member) do { \ |
| 364 | list_for_each_entry(vma, list, member) { \ |
| 365 | size += i915_gem_obj_ggtt_size(vma->obj); \ |
| 366 | ++count; \ |
| 367 | if (vma->obj->map_and_fenceable) { \ |
| 368 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ |
| 369 | ++mappable_count; \ |
| 370 | } \ |
| 371 | } \ |
| 372 | } while (0) |
| 373 | |
| 374 | static int i915_gem_object_info(struct seq_file *m, void* data) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 375 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 376 | struct drm_info_node *node = m->private; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 377 | struct drm_device *dev = node->minor->dev; |
| 378 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 379 | u32 count, mappable_count, purgeable_count; |
| 380 | size_t size, mappable_size, purgeable_size; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 381 | struct drm_i915_gem_object *obj; |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 382 | struct i915_address_space *vm = &dev_priv->gtt.base; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 383 | struct drm_file *file; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 384 | struct i915_vma *vma; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 385 | int ret; |
| 386 | |
| 387 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 388 | if (ret) |
| 389 | return ret; |
| 390 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 391 | seq_printf(m, "%u objects, %zu bytes\n", |
| 392 | dev_priv->mm.object_count, |
| 393 | dev_priv->mm.object_memory); |
| 394 | |
| 395 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 396 | count_objects(&dev_priv->mm.bound_list, global_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 397 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
| 398 | count, mappable_count, size, mappable_size); |
| 399 | |
| 400 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 401 | count_vmas(&vm->active_list, mm_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 402 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
| 403 | count, mappable_count, size, mappable_size); |
| 404 | |
| 405 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 406 | count_vmas(&vm->inactive_list, mm_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 407 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
| 408 | count, mappable_count, size, mappable_size); |
| 409 | |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 410 | size = count = purgeable_size = purgeable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 411 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 412 | size += obj->base.size, ++count; |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 413 | if (obj->madv == I915_MADV_DONTNEED) |
| 414 | purgeable_size += obj->base.size, ++purgeable_count; |
| 415 | } |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 416 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
| 417 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 418 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 419 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 420 | if (obj->fault_mappable) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 421 | size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 422 | ++count; |
| 423 | } |
| 424 | if (obj->pin_mappable) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 425 | mappable_size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 426 | ++mappable_count; |
| 427 | } |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 428 | if (obj->madv == I915_MADV_DONTNEED) { |
| 429 | purgeable_size += obj->base.size; |
| 430 | ++purgeable_count; |
| 431 | } |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 432 | } |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 433 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
| 434 | purgeable_count, purgeable_size); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 435 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
| 436 | mappable_count, mappable_size); |
| 437 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", |
| 438 | count, size); |
| 439 | |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 440 | seq_printf(m, "%zu [%lu] gtt total\n", |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 441 | dev_priv->gtt.base.total, |
| 442 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 443 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 444 | seq_putc(m, '\n'); |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 445 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
| 446 | struct file_stats stats; |
Tetsuo Handa | 3ec2f42 | 2014-01-03 20:42:18 +0900 | [diff] [blame] | 447 | struct task_struct *task; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 448 | |
| 449 | memset(&stats, 0, sizeof(stats)); |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 450 | stats.file_priv = file->driver_priv; |
Chris Wilson | 5b5ffff | 2014-06-17 09:56:24 +0100 | [diff] [blame] | 451 | spin_lock(&file->table_lock); |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 452 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
Chris Wilson | 5b5ffff | 2014-06-17 09:56:24 +0100 | [diff] [blame] | 453 | spin_unlock(&file->table_lock); |
Tetsuo Handa | 3ec2f42 | 2014-01-03 20:42:18 +0900 | [diff] [blame] | 454 | /* |
| 455 | * Although we have a valid reference on file->pid, that does |
| 456 | * not guarantee that the task_struct who called get_pid() is |
| 457 | * still alive (e.g. get_pid(current) => fork() => exit()). |
| 458 | * Therefore, we need to protect this ->comm access using RCU. |
| 459 | */ |
| 460 | rcu_read_lock(); |
| 461 | task = pid_task(file->pid, PIDTYPE_PID); |
Chris Wilson | c67a17e | 2014-03-19 13:45:46 +0000 | [diff] [blame] | 462 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", |
Tetsuo Handa | 3ec2f42 | 2014-01-03 20:42:18 +0900 | [diff] [blame] | 463 | task ? task->comm : "<unknown>", |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 464 | stats.count, |
| 465 | stats.total, |
| 466 | stats.active, |
| 467 | stats.inactive, |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 468 | stats.global, |
Chris Wilson | c67a17e | 2014-03-19 13:45:46 +0000 | [diff] [blame] | 469 | stats.shared, |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 470 | stats.unbound); |
Tetsuo Handa | 3ec2f42 | 2014-01-03 20:42:18 +0900 | [diff] [blame] | 471 | rcu_read_unlock(); |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 472 | } |
| 473 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 474 | mutex_unlock(&dev->struct_mutex); |
| 475 | |
| 476 | return 0; |
| 477 | } |
| 478 | |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 479 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 480 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 481 | struct drm_info_node *node = m->private; |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 482 | struct drm_device *dev = node->minor->dev; |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 483 | uintptr_t list = (uintptr_t) node->info_ent->data; |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 484 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 485 | struct drm_i915_gem_object *obj; |
| 486 | size_t total_obj_size, total_gtt_size; |
| 487 | int count, ret; |
| 488 | |
| 489 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 490 | if (ret) |
| 491 | return ret; |
| 492 | |
| 493 | total_obj_size = total_gtt_size = count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 494 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 495 | if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 496 | continue; |
| 497 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 498 | seq_puts(m, " "); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 499 | describe_obj(m, obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 500 | seq_putc(m, '\n'); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 501 | total_obj_size += obj->base.size; |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 502 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 503 | count++; |
| 504 | } |
| 505 | |
| 506 | mutex_unlock(&dev->struct_mutex); |
| 507 | |
| 508 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 509 | count, total_obj_size, total_gtt_size); |
| 510 | |
| 511 | return 0; |
| 512 | } |
| 513 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 514 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
| 515 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 516 | struct drm_info_node *node = m->private; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 517 | struct drm_device *dev = node->minor->dev; |
| 518 | unsigned long flags; |
| 519 | struct intel_crtc *crtc; |
Daniel Vetter | 8a270eb | 2014-06-17 22:34:37 +0200 | [diff] [blame] | 520 | int ret; |
| 521 | |
| 522 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 523 | if (ret) |
| 524 | return ret; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 525 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 526 | for_each_intel_crtc(dev, crtc) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 527 | const char pipe = pipe_name(crtc->pipe); |
| 528 | const char plane = plane_name(crtc->plane); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 529 | struct intel_unpin_work *work; |
| 530 | |
| 531 | spin_lock_irqsave(&dev->event_lock, flags); |
| 532 | work = crtc->unpin_work; |
| 533 | if (work == NULL) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 534 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 535 | pipe, plane); |
| 536 | } else { |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 537 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 538 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 539 | pipe, plane); |
| 540 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 541 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 542 | pipe, plane); |
| 543 | } |
| 544 | if (work->enable_stall_check) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 545 | seq_puts(m, "Stall check enabled, "); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 546 | else |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 547 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 548 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 549 | |
| 550 | if (work->old_fb_obj) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 551 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
| 552 | if (obj) |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 553 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
| 554 | i915_gem_obj_ggtt_offset(obj)); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 555 | } |
| 556 | if (work->pending_flip_obj) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 557 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
| 558 | if (obj) |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 559 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
| 560 | i915_gem_obj_ggtt_offset(obj)); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 561 | } |
| 562 | } |
| 563 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 564 | } |
| 565 | |
Daniel Vetter | 8a270eb | 2014-06-17 22:34:37 +0200 | [diff] [blame] | 566 | mutex_unlock(&dev->struct_mutex); |
| 567 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 568 | return 0; |
| 569 | } |
| 570 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 571 | static int i915_gem_request_info(struct seq_file *m, void *data) |
| 572 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 573 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 574 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 575 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 576 | struct intel_engine_cs *ring; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 577 | struct drm_i915_gem_request *gem_request; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 578 | int ret, count, i; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 579 | |
| 580 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 581 | if (ret) |
| 582 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 583 | |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 584 | count = 0; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 585 | for_each_ring(ring, dev_priv, i) { |
| 586 | if (list_empty(&ring->request_list)) |
| 587 | continue; |
| 588 | |
| 589 | seq_printf(m, "%s requests:\n", ring->name); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 590 | list_for_each_entry(gem_request, |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 591 | &ring->request_list, |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 592 | list) { |
| 593 | seq_printf(m, " %d @ %d\n", |
| 594 | gem_request->seqno, |
| 595 | (int) (jiffies - gem_request->emitted_jiffies)); |
| 596 | } |
| 597 | count++; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 598 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 599 | mutex_unlock(&dev->struct_mutex); |
| 600 | |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 601 | if (count == 0) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 602 | seq_puts(m, "No requests\n"); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 603 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 604 | return 0; |
| 605 | } |
| 606 | |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 607 | static void i915_ring_seqno_info(struct seq_file *m, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 608 | struct intel_engine_cs *ring) |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 609 | { |
| 610 | if (ring->get_seqno) { |
Mika Kuoppala | 43a7b92 | 2012-12-04 15:12:01 +0200 | [diff] [blame] | 611 | seq_printf(m, "Current sequence (%s): %u\n", |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 612 | ring->name, ring->get_seqno(ring, false)); |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 613 | } |
| 614 | } |
| 615 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 616 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
| 617 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 618 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 619 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 620 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 621 | struct intel_engine_cs *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 622 | int ret, i; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 623 | |
| 624 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 625 | if (ret) |
| 626 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 627 | intel_runtime_pm_get(dev_priv); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 628 | |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 629 | for_each_ring(ring, dev_priv, i) |
| 630 | i915_ring_seqno_info(m, ring); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 631 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 632 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 633 | mutex_unlock(&dev->struct_mutex); |
| 634 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 635 | return 0; |
| 636 | } |
| 637 | |
| 638 | |
| 639 | static int i915_interrupt_info(struct seq_file *m, void *data) |
| 640 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 641 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 642 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 643 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 644 | struct intel_engine_cs *ring; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 645 | int ret, i, pipe; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 646 | |
| 647 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 648 | if (ret) |
| 649 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 650 | intel_runtime_pm_get(dev_priv); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 651 | |
Ville Syrjälä | 74e1ca8 | 2014-04-09 13:28:09 +0300 | [diff] [blame] | 652 | if (IS_CHERRYVIEW(dev)) { |
| 653 | int i; |
| 654 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
| 655 | I915_READ(GEN8_MASTER_IRQ)); |
| 656 | |
| 657 | seq_printf(m, "Display IER:\t%08x\n", |
| 658 | I915_READ(VLV_IER)); |
| 659 | seq_printf(m, "Display IIR:\t%08x\n", |
| 660 | I915_READ(VLV_IIR)); |
| 661 | seq_printf(m, "Display IIR_RW:\t%08x\n", |
| 662 | I915_READ(VLV_IIR_RW)); |
| 663 | seq_printf(m, "Display IMR:\t%08x\n", |
| 664 | I915_READ(VLV_IMR)); |
| 665 | for_each_pipe(pipe) |
| 666 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
| 667 | pipe_name(pipe), |
| 668 | I915_READ(PIPESTAT(pipe))); |
| 669 | |
| 670 | seq_printf(m, "Port hotplug:\t%08x\n", |
| 671 | I915_READ(PORT_HOTPLUG_EN)); |
| 672 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", |
| 673 | I915_READ(VLV_DPFLIPSTAT)); |
| 674 | seq_printf(m, "DPINVGTT:\t%08x\n", |
| 675 | I915_READ(DPINVGTT)); |
| 676 | |
| 677 | for (i = 0; i < 4; i++) { |
| 678 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", |
| 679 | i, I915_READ(GEN8_GT_IMR(i))); |
| 680 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", |
| 681 | i, I915_READ(GEN8_GT_IIR(i))); |
| 682 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", |
| 683 | i, I915_READ(GEN8_GT_IER(i))); |
| 684 | } |
| 685 | |
| 686 | seq_printf(m, "PCU interrupt mask:\t%08x\n", |
| 687 | I915_READ(GEN8_PCU_IMR)); |
| 688 | seq_printf(m, "PCU interrupt identity:\t%08x\n", |
| 689 | I915_READ(GEN8_PCU_IIR)); |
| 690 | seq_printf(m, "PCU interrupt enable:\t%08x\n", |
| 691 | I915_READ(GEN8_PCU_IER)); |
| 692 | } else if (INTEL_INFO(dev)->gen >= 8) { |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 693 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
| 694 | I915_READ(GEN8_MASTER_IRQ)); |
| 695 | |
| 696 | for (i = 0; i < 4; i++) { |
| 697 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", |
| 698 | i, I915_READ(GEN8_GT_IMR(i))); |
| 699 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", |
| 700 | i, I915_READ(GEN8_GT_IIR(i))); |
| 701 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", |
| 702 | i, I915_READ(GEN8_GT_IER(i))); |
| 703 | } |
| 704 | |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 705 | for_each_pipe(pipe) { |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 706 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 707 | pipe_name(pipe), |
| 708 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 709 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 710 | pipe_name(pipe), |
| 711 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 712 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 713 | pipe_name(pipe), |
| 714 | I915_READ(GEN8_DE_PIPE_IER(pipe))); |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 715 | } |
| 716 | |
| 717 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", |
| 718 | I915_READ(GEN8_DE_PORT_IMR)); |
| 719 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", |
| 720 | I915_READ(GEN8_DE_PORT_IIR)); |
| 721 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", |
| 722 | I915_READ(GEN8_DE_PORT_IER)); |
| 723 | |
| 724 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", |
| 725 | I915_READ(GEN8_DE_MISC_IMR)); |
| 726 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", |
| 727 | I915_READ(GEN8_DE_MISC_IIR)); |
| 728 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", |
| 729 | I915_READ(GEN8_DE_MISC_IER)); |
| 730 | |
| 731 | seq_printf(m, "PCU interrupt mask:\t%08x\n", |
| 732 | I915_READ(GEN8_PCU_IMR)); |
| 733 | seq_printf(m, "PCU interrupt identity:\t%08x\n", |
| 734 | I915_READ(GEN8_PCU_IIR)); |
| 735 | seq_printf(m, "PCU interrupt enable:\t%08x\n", |
| 736 | I915_READ(GEN8_PCU_IER)); |
| 737 | } else if (IS_VALLEYVIEW(dev)) { |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 738 | seq_printf(m, "Display IER:\t%08x\n", |
| 739 | I915_READ(VLV_IER)); |
| 740 | seq_printf(m, "Display IIR:\t%08x\n", |
| 741 | I915_READ(VLV_IIR)); |
| 742 | seq_printf(m, "Display IIR_RW:\t%08x\n", |
| 743 | I915_READ(VLV_IIR_RW)); |
| 744 | seq_printf(m, "Display IMR:\t%08x\n", |
| 745 | I915_READ(VLV_IMR)); |
| 746 | for_each_pipe(pipe) |
| 747 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
| 748 | pipe_name(pipe), |
| 749 | I915_READ(PIPESTAT(pipe))); |
| 750 | |
| 751 | seq_printf(m, "Master IER:\t%08x\n", |
| 752 | I915_READ(VLV_MASTER_IER)); |
| 753 | |
| 754 | seq_printf(m, "Render IER:\t%08x\n", |
| 755 | I915_READ(GTIER)); |
| 756 | seq_printf(m, "Render IIR:\t%08x\n", |
| 757 | I915_READ(GTIIR)); |
| 758 | seq_printf(m, "Render IMR:\t%08x\n", |
| 759 | I915_READ(GTIMR)); |
| 760 | |
| 761 | seq_printf(m, "PM IER:\t\t%08x\n", |
| 762 | I915_READ(GEN6_PMIER)); |
| 763 | seq_printf(m, "PM IIR:\t\t%08x\n", |
| 764 | I915_READ(GEN6_PMIIR)); |
| 765 | seq_printf(m, "PM IMR:\t\t%08x\n", |
| 766 | I915_READ(GEN6_PMIMR)); |
| 767 | |
| 768 | seq_printf(m, "Port hotplug:\t%08x\n", |
| 769 | I915_READ(PORT_HOTPLUG_EN)); |
| 770 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", |
| 771 | I915_READ(VLV_DPFLIPSTAT)); |
| 772 | seq_printf(m, "DPINVGTT:\t%08x\n", |
| 773 | I915_READ(DPINVGTT)); |
| 774 | |
| 775 | } else if (!HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 5f6a169 | 2009-08-10 21:37:24 +0800 | [diff] [blame] | 776 | seq_printf(m, "Interrupt enable: %08x\n", |
| 777 | I915_READ(IER)); |
| 778 | seq_printf(m, "Interrupt identity: %08x\n", |
| 779 | I915_READ(IIR)); |
| 780 | seq_printf(m, "Interrupt mask: %08x\n", |
| 781 | I915_READ(IMR)); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 782 | for_each_pipe(pipe) |
| 783 | seq_printf(m, "Pipe %c stat: %08x\n", |
| 784 | pipe_name(pipe), |
| 785 | I915_READ(PIPESTAT(pipe))); |
Zhenyu Wang | 5f6a169 | 2009-08-10 21:37:24 +0800 | [diff] [blame] | 786 | } else { |
| 787 | seq_printf(m, "North Display Interrupt enable: %08x\n", |
| 788 | I915_READ(DEIER)); |
| 789 | seq_printf(m, "North Display Interrupt identity: %08x\n", |
| 790 | I915_READ(DEIIR)); |
| 791 | seq_printf(m, "North Display Interrupt mask: %08x\n", |
| 792 | I915_READ(DEIMR)); |
| 793 | seq_printf(m, "South Display Interrupt enable: %08x\n", |
| 794 | I915_READ(SDEIER)); |
| 795 | seq_printf(m, "South Display Interrupt identity: %08x\n", |
| 796 | I915_READ(SDEIIR)); |
| 797 | seq_printf(m, "South Display Interrupt mask: %08x\n", |
| 798 | I915_READ(SDEIMR)); |
| 799 | seq_printf(m, "Graphics Interrupt enable: %08x\n", |
| 800 | I915_READ(GTIER)); |
| 801 | seq_printf(m, "Graphics Interrupt identity: %08x\n", |
| 802 | I915_READ(GTIIR)); |
| 803 | seq_printf(m, "Graphics Interrupt mask: %08x\n", |
| 804 | I915_READ(GTIMR)); |
| 805 | } |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 806 | for_each_ring(ring, dev_priv, i) { |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 807 | if (INTEL_INFO(dev)->gen >= 6) { |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 808 | seq_printf(m, |
| 809 | "Graphics Interrupt mask (%s): %08x\n", |
| 810 | ring->name, I915_READ_IMR(ring)); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 811 | } |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 812 | i915_ring_seqno_info(m, ring); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 813 | } |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 814 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 815 | mutex_unlock(&dev->struct_mutex); |
| 816 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 817 | return 0; |
| 818 | } |
| 819 | |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 820 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
| 821 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 822 | struct drm_info_node *node = m->private; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 823 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 824 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 825 | int i, ret; |
| 826 | |
| 827 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 828 | if (ret) |
| 829 | return ret; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 830 | |
| 831 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); |
| 832 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
| 833 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 834 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 835 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 836 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
| 837 | i, dev_priv->fence_regs[i].pin_count); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 838 | if (obj == NULL) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 839 | seq_puts(m, "unused"); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 840 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 841 | describe_obj(m, obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 842 | seq_putc(m, '\n'); |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 843 | } |
| 844 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 845 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 846 | return 0; |
| 847 | } |
| 848 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 849 | static int i915_hws_info(struct seq_file *m, void *data) |
| 850 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 851 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 852 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 853 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 854 | struct intel_engine_cs *ring; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 855 | const u32 *hws; |
Chris Wilson | 4066c0a | 2010-10-29 21:00:54 +0100 | [diff] [blame] | 856 | int i; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 857 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 858 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 859 | hws = ring->status_page.page_addr; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 860 | if (hws == NULL) |
| 861 | return 0; |
| 862 | |
| 863 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { |
| 864 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 865 | i * 4, |
| 866 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); |
| 867 | } |
| 868 | return 0; |
| 869 | } |
| 870 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 871 | static ssize_t |
| 872 | i915_error_state_write(struct file *filp, |
| 873 | const char __user *ubuf, |
| 874 | size_t cnt, |
| 875 | loff_t *ppos) |
| 876 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 877 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 878 | struct drm_device *dev = error_priv->dev; |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 879 | int ret; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 880 | |
| 881 | DRM_DEBUG_DRIVER("Resetting error state\n"); |
| 882 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 883 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 884 | if (ret) |
| 885 | return ret; |
| 886 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 887 | i915_destroy_error_state(dev); |
| 888 | mutex_unlock(&dev->struct_mutex); |
| 889 | |
| 890 | return cnt; |
| 891 | } |
| 892 | |
| 893 | static int i915_error_state_open(struct inode *inode, struct file *file) |
| 894 | { |
| 895 | struct drm_device *dev = inode->i_private; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 896 | struct i915_error_state_file_priv *error_priv; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 897 | |
| 898 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); |
| 899 | if (!error_priv) |
| 900 | return -ENOMEM; |
| 901 | |
| 902 | error_priv->dev = dev; |
| 903 | |
Mika Kuoppala | 95d5bfb | 2013-06-06 15:18:40 +0300 | [diff] [blame] | 904 | i915_error_state_get(dev, error_priv); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 905 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 906 | file->private_data = error_priv; |
| 907 | |
| 908 | return 0; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 909 | } |
| 910 | |
| 911 | static int i915_error_state_release(struct inode *inode, struct file *file) |
| 912 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 913 | struct i915_error_state_file_priv *error_priv = file->private_data; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 914 | |
Mika Kuoppala | 95d5bfb | 2013-06-06 15:18:40 +0300 | [diff] [blame] | 915 | i915_error_state_put(error_priv); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 916 | kfree(error_priv); |
| 917 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 918 | return 0; |
| 919 | } |
| 920 | |
| 921 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
| 922 | size_t count, loff_t *pos) |
| 923 | { |
| 924 | struct i915_error_state_file_priv *error_priv = file->private_data; |
| 925 | struct drm_i915_error_state_buf error_str; |
| 926 | loff_t tmp_pos = 0; |
| 927 | ssize_t ret_count = 0; |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 928 | int ret; |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 929 | |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 930 | ret = i915_error_state_buf_init(&error_str, count, *pos); |
| 931 | if (ret) |
| 932 | return ret; |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 933 | |
Mika Kuoppala | fc16b48 | 2013-06-06 15:18:39 +0300 | [diff] [blame] | 934 | ret = i915_error_state_to_str(&error_str, error_priv); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 935 | if (ret) |
| 936 | goto out; |
| 937 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 938 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
| 939 | error_str.buf, |
| 940 | error_str.bytes); |
| 941 | |
| 942 | if (ret_count < 0) |
| 943 | ret = ret_count; |
| 944 | else |
| 945 | *pos = error_str.start + ret_count; |
| 946 | out: |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 947 | i915_error_state_buf_release(&error_str); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 948 | return ret ?: ret_count; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 949 | } |
| 950 | |
| 951 | static const struct file_operations i915_error_state_fops = { |
| 952 | .owner = THIS_MODULE, |
| 953 | .open = i915_error_state_open, |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 954 | .read = i915_error_state_read, |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 955 | .write = i915_error_state_write, |
| 956 | .llseek = default_llseek, |
| 957 | .release = i915_error_state_release, |
| 958 | }; |
| 959 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 960 | static int |
| 961 | i915_next_seqno_get(void *data, u64 *val) |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 962 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 963 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 964 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 965 | int ret; |
| 966 | |
| 967 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 968 | if (ret) |
| 969 | return ret; |
| 970 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 971 | *val = dev_priv->next_seqno; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 972 | mutex_unlock(&dev->struct_mutex); |
| 973 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 974 | return 0; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 975 | } |
| 976 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 977 | static int |
| 978 | i915_next_seqno_set(void *data, u64 val) |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 979 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 980 | struct drm_device *dev = data; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 981 | int ret; |
| 982 | |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 983 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 984 | if (ret) |
| 985 | return ret; |
| 986 | |
Mika Kuoppala | e94fbaa | 2012-12-19 11:13:09 +0200 | [diff] [blame] | 987 | ret = i915_gem_set_seqno(dev, val); |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 988 | mutex_unlock(&dev->struct_mutex); |
| 989 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 990 | return ret; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 991 | } |
| 992 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 993 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
| 994 | i915_next_seqno_get, i915_next_seqno_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 995 | "0x%llx\n"); |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 996 | |
Deepak S | adb4bd1 | 2014-03-31 11:30:02 +0530 | [diff] [blame] | 997 | static int i915_frequency_info(struct seq_file *m, void *unused) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 998 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 999 | struct drm_info_node *node = m->private; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1000 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1001 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1002 | int ret = 0; |
| 1003 | |
| 1004 | intel_runtime_pm_get(dev_priv); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1005 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 1006 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 1007 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1008 | if (IS_GEN5(dev)) { |
| 1009 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
| 1010 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); |
| 1011 | |
| 1012 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); |
| 1013 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); |
| 1014 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> |
| 1015 | MEMSTAT_VID_SHIFT); |
| 1016 | seq_printf(m, "Current P-state: %d\n", |
| 1017 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 1018 | } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) || |
| 1019 | IS_BROADWELL(dev)) { |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1020 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
| 1021 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
| 1022 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1023 | u32 rpmodectl, rpinclimit, rpdeclimit; |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1024 | u32 rpstat, cagf, reqf; |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1025 | u32 rpupei, rpcurup, rpprevup; |
| 1026 | u32 rpdownei, rpcurdown, rpprevdown; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1027 | int max_freq; |
| 1028 | |
| 1029 | /* RPSTAT1 is in the GT power well */ |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 1030 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1031 | if (ret) |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1032 | goto out; |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 1033 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 1034 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1035 | |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1036 | reqf = I915_READ(GEN6_RPNSWREQ); |
| 1037 | reqf &= ~GEN6_TURBO_DISABLE; |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 1038 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1039 | reqf >>= 24; |
| 1040 | else |
| 1041 | reqf >>= 25; |
| 1042 | reqf *= GT_FREQUENCY_MULTIPLIER; |
| 1043 | |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1044 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
| 1045 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); |
| 1046 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); |
| 1047 | |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1048 | rpstat = I915_READ(GEN6_RPSTAT1); |
| 1049 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); |
| 1050 | rpcurup = I915_READ(GEN6_RP_CUR_UP); |
| 1051 | rpprevup = I915_READ(GEN6_RP_PREV_UP); |
| 1052 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); |
| 1053 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); |
| 1054 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 1055 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 1056 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
| 1057 | else |
| 1058 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; |
| 1059 | cagf *= GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1060 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 1061 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 1062 | mutex_unlock(&dev->struct_mutex); |
| 1063 | |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1064 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
| 1065 | I915_READ(GEN6_PMIER), |
| 1066 | I915_READ(GEN6_PMIMR), |
| 1067 | I915_READ(GEN6_PMISR), |
| 1068 | I915_READ(GEN6_PMIIR), |
| 1069 | I915_READ(GEN6_PMINTRMSK)); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1070 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1071 | seq_printf(m, "Render p-state ratio: %d\n", |
| 1072 | (gt_perf_status & 0xff00) >> 8); |
| 1073 | seq_printf(m, "Render p-state VID: %d\n", |
| 1074 | gt_perf_status & 0xff); |
| 1075 | seq_printf(m, "Render p-state limit: %d\n", |
| 1076 | rp_state_limits & 0xff); |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1077 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
| 1078 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); |
| 1079 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); |
| 1080 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1081 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 1082 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1083 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
| 1084 | GEN6_CURICONT_MASK); |
| 1085 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & |
| 1086 | GEN6_CURBSYTAVG_MASK); |
| 1087 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & |
| 1088 | GEN6_CURBSYTAVG_MASK); |
| 1089 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & |
| 1090 | GEN6_CURIAVG_MASK); |
| 1091 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & |
| 1092 | GEN6_CURBSYTAVG_MASK); |
| 1093 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & |
| 1094 | GEN6_CURBSYTAVG_MASK); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1095 | |
| 1096 | max_freq = (rp_state_cap & 0xff0000) >> 16; |
| 1097 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1098 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1099 | |
| 1100 | max_freq = (rp_state_cap & 0xff00) >> 8; |
| 1101 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1102 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1103 | |
| 1104 | max_freq = rp_state_cap & 0xff; |
| 1105 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1106 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Ben Widawsky | 31c7738 | 2013-04-05 14:29:22 -0700 | [diff] [blame] | 1107 | |
| 1108 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1109 | dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1110 | } else if (IS_VALLEYVIEW(dev)) { |
| 1111 | u32 freq_sts, val; |
| 1112 | |
Jesse Barnes | 259bd5d | 2013-04-22 15:59:30 -0700 | [diff] [blame] | 1113 | mutex_lock(&dev_priv->rps.hw_lock); |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 1114 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1115 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
| 1116 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); |
| 1117 | |
Chon Ming Lee | c5bd2bf | 2013-11-07 15:23:27 +0800 | [diff] [blame] | 1118 | val = valleyview_rps_max_freq(dev_priv); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1119 | seq_printf(m, "max GPU freq: %d MHz\n", |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 1120 | vlv_gpu_freq(dev_priv, val)); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1121 | |
Chon Ming Lee | c5bd2bf | 2013-11-07 15:23:27 +0800 | [diff] [blame] | 1122 | val = valleyview_rps_min_freq(dev_priv); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1123 | seq_printf(m, "min GPU freq: %d MHz\n", |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 1124 | vlv_gpu_freq(dev_priv, val)); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1125 | |
| 1126 | seq_printf(m, "current GPU freq: %d MHz\n", |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 1127 | vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); |
Jesse Barnes | 259bd5d | 2013-04-22 15:59:30 -0700 | [diff] [blame] | 1128 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1129 | } else { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1130 | seq_puts(m, "no P-state info available\n"); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1131 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1132 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1133 | out: |
| 1134 | intel_runtime_pm_put(dev_priv); |
| 1135 | return ret; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1136 | } |
| 1137 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1138 | static int ironlake_drpc_info(struct seq_file *m) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1139 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1140 | struct drm_info_node *node = m->private; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1141 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1142 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1143 | u32 rgvmodectl, rstdbyctl; |
| 1144 | u16 crstandvid; |
| 1145 | int ret; |
| 1146 | |
| 1147 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1148 | if (ret) |
| 1149 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1150 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1151 | |
| 1152 | rgvmodectl = I915_READ(MEMMODECTL); |
| 1153 | rstdbyctl = I915_READ(RSTDBYCTL); |
| 1154 | crstandvid = I915_READ16(CRSTANDVID); |
| 1155 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1156 | intel_runtime_pm_put(dev_priv); |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1157 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1158 | |
| 1159 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? |
| 1160 | "yes" : "no"); |
| 1161 | seq_printf(m, "Boost freq: %d\n", |
| 1162 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> |
| 1163 | MEMMODE_BOOST_FREQ_SHIFT); |
| 1164 | seq_printf(m, "HW control enabled: %s\n", |
| 1165 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); |
| 1166 | seq_printf(m, "SW control enabled: %s\n", |
| 1167 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); |
| 1168 | seq_printf(m, "Gated voltage change: %s\n", |
| 1169 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); |
| 1170 | seq_printf(m, "Starting frequency: P%d\n", |
| 1171 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1172 | seq_printf(m, "Max P-state: P%d\n", |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1173 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1174 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
| 1175 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); |
| 1176 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); |
| 1177 | seq_printf(m, "Render standby enabled: %s\n", |
| 1178 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1179 | seq_puts(m, "Current RS state: "); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1180 | switch (rstdbyctl & RSX_STATUS_MASK) { |
| 1181 | case RSX_STATUS_ON: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1182 | seq_puts(m, "on\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1183 | break; |
| 1184 | case RSX_STATUS_RC1: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1185 | seq_puts(m, "RC1\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1186 | break; |
| 1187 | case RSX_STATUS_RC1E: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1188 | seq_puts(m, "RC1E\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1189 | break; |
| 1190 | case RSX_STATUS_RS1: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1191 | seq_puts(m, "RS1\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1192 | break; |
| 1193 | case RSX_STATUS_RS2: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1194 | seq_puts(m, "RS2 (RC6)\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1195 | break; |
| 1196 | case RSX_STATUS_RS3: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1197 | seq_puts(m, "RC3 (RC6+)\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1198 | break; |
| 1199 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1200 | seq_puts(m, "unknown\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1201 | break; |
| 1202 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1203 | |
| 1204 | return 0; |
| 1205 | } |
| 1206 | |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1207 | static int vlv_drpc_info(struct seq_file *m) |
| 1208 | { |
| 1209 | |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1210 | struct drm_info_node *node = m->private; |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1211 | struct drm_device *dev = node->minor->dev; |
| 1212 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1213 | u32 rpmodectl1, rcctl1; |
| 1214 | unsigned fw_rendercount = 0, fw_mediacount = 0; |
| 1215 | |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 1216 | intel_runtime_pm_get(dev_priv); |
| 1217 | |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1218 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
| 1219 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
| 1220 | |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 1221 | intel_runtime_pm_put(dev_priv); |
| 1222 | |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1223 | seq_printf(m, "Video Turbo Mode: %s\n", |
| 1224 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); |
| 1225 | seq_printf(m, "Turbo enabled: %s\n", |
| 1226 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); |
| 1227 | seq_printf(m, "HW control enabled: %s\n", |
| 1228 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); |
| 1229 | seq_printf(m, "SW control enabled: %s\n", |
| 1230 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == |
| 1231 | GEN6_RP_MEDIA_SW_MODE)); |
| 1232 | seq_printf(m, "RC6 Enabled: %s\n", |
| 1233 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | |
| 1234 | GEN6_RC_CTL_EI_MODE(1)))); |
| 1235 | seq_printf(m, "Render Power Well: %s\n", |
| 1236 | (I915_READ(VLV_GTLC_PW_STATUS) & |
| 1237 | VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
| 1238 | seq_printf(m, "Media Power Well: %s\n", |
| 1239 | (I915_READ(VLV_GTLC_PW_STATUS) & |
| 1240 | VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
| 1241 | |
Imre Deak | 9cc19be | 2014-04-14 20:24:24 +0300 | [diff] [blame] | 1242 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
| 1243 | I915_READ(VLV_GT_RENDER_RC6)); |
| 1244 | seq_printf(m, "Media RC6 residency since boot: %u\n", |
| 1245 | I915_READ(VLV_GT_MEDIA_RC6)); |
| 1246 | |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1247 | spin_lock_irq(&dev_priv->uncore.lock); |
| 1248 | fw_rendercount = dev_priv->uncore.fw_rendercount; |
| 1249 | fw_mediacount = dev_priv->uncore.fw_mediacount; |
| 1250 | spin_unlock_irq(&dev_priv->uncore.lock); |
| 1251 | |
| 1252 | seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount); |
| 1253 | seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount); |
| 1254 | |
| 1255 | |
| 1256 | return 0; |
| 1257 | } |
| 1258 | |
| 1259 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1260 | static int gen6_drpc_info(struct seq_file *m) |
| 1261 | { |
| 1262 | |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1263 | struct drm_info_node *node = m->private; |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1264 | struct drm_device *dev = node->minor->dev; |
| 1265 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | ecd8fae | 2012-09-26 10:34:02 -0700 | [diff] [blame] | 1266 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
Daniel Vetter | 93b525d | 2012-01-25 13:52:43 +0100 | [diff] [blame] | 1267 | unsigned forcewake_count; |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 1268 | int count = 0, ret; |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1269 | |
| 1270 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1271 | if (ret) |
| 1272 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1273 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1274 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1275 | spin_lock_irq(&dev_priv->uncore.lock); |
| 1276 | forcewake_count = dev_priv->uncore.forcewake_count; |
| 1277 | spin_unlock_irq(&dev_priv->uncore.lock); |
Daniel Vetter | 93b525d | 2012-01-25 13:52:43 +0100 | [diff] [blame] | 1278 | |
| 1279 | if (forcewake_count) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1280 | seq_puts(m, "RC information inaccurate because somebody " |
| 1281 | "holds a forcewake reference \n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1282 | } else { |
| 1283 | /* NB: we cannot use forcewake, else we read the wrong values */ |
| 1284 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) |
| 1285 | udelay(10); |
| 1286 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); |
| 1287 | } |
| 1288 | |
| 1289 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); |
Chris Wilson | ed71f1b | 2013-07-19 20:36:56 +0100 | [diff] [blame] | 1290 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1291 | |
| 1292 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
| 1293 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
| 1294 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | 44cbd33 | 2012-11-06 14:36:36 +0000 | [diff] [blame] | 1295 | mutex_lock(&dev_priv->rps.hw_lock); |
| 1296 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
| 1297 | mutex_unlock(&dev_priv->rps.hw_lock); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1298 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1299 | intel_runtime_pm_put(dev_priv); |
| 1300 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1301 | seq_printf(m, "Video Turbo Mode: %s\n", |
| 1302 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); |
| 1303 | seq_printf(m, "HW control enabled: %s\n", |
| 1304 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); |
| 1305 | seq_printf(m, "SW control enabled: %s\n", |
| 1306 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == |
| 1307 | GEN6_RP_MEDIA_SW_MODE)); |
Eric Anholt | fff24e2 | 2012-01-23 16:14:05 -0800 | [diff] [blame] | 1308 | seq_printf(m, "RC1e Enabled: %s\n", |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1309 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
| 1310 | seq_printf(m, "RC6 Enabled: %s\n", |
| 1311 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); |
| 1312 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
| 1313 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); |
| 1314 | seq_printf(m, "Deepest RC6 Enabled: %s\n", |
| 1315 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1316 | seq_puts(m, "Current RC state: "); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1317 | switch (gt_core_status & GEN6_RCn_MASK) { |
| 1318 | case GEN6_RC0: |
| 1319 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1320 | seq_puts(m, "Core Power Down\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1321 | else |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1322 | seq_puts(m, "on\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1323 | break; |
| 1324 | case GEN6_RC3: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1325 | seq_puts(m, "RC3\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1326 | break; |
| 1327 | case GEN6_RC6: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1328 | seq_puts(m, "RC6\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1329 | break; |
| 1330 | case GEN6_RC7: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1331 | seq_puts(m, "RC7\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1332 | break; |
| 1333 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1334 | seq_puts(m, "Unknown\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1335 | break; |
| 1336 | } |
| 1337 | |
| 1338 | seq_printf(m, "Core Power Down: %s\n", |
| 1339 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); |
Ben Widawsky | cce66a2 | 2012-03-27 18:59:38 -0700 | [diff] [blame] | 1340 | |
| 1341 | /* Not exactly sure what this is */ |
| 1342 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", |
| 1343 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); |
| 1344 | seq_printf(m, "RC6 residency since boot: %u\n", |
| 1345 | I915_READ(GEN6_GT_GFX_RC6)); |
| 1346 | seq_printf(m, "RC6+ residency since boot: %u\n", |
| 1347 | I915_READ(GEN6_GT_GFX_RC6p)); |
| 1348 | seq_printf(m, "RC6++ residency since boot: %u\n", |
| 1349 | I915_READ(GEN6_GT_GFX_RC6pp)); |
| 1350 | |
Ben Widawsky | ecd8fae | 2012-09-26 10:34:02 -0700 | [diff] [blame] | 1351 | seq_printf(m, "RC6 voltage: %dmV\n", |
| 1352 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); |
| 1353 | seq_printf(m, "RC6+ voltage: %dmV\n", |
| 1354 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); |
| 1355 | seq_printf(m, "RC6++ voltage: %dmV\n", |
| 1356 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1357 | return 0; |
| 1358 | } |
| 1359 | |
| 1360 | static int i915_drpc_info(struct seq_file *m, void *unused) |
| 1361 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1362 | struct drm_info_node *node = m->private; |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1363 | struct drm_device *dev = node->minor->dev; |
| 1364 | |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1365 | if (IS_VALLEYVIEW(dev)) |
| 1366 | return vlv_drpc_info(m); |
| 1367 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1368 | return gen6_drpc_info(m); |
| 1369 | else |
| 1370 | return ironlake_drpc_info(m); |
| 1371 | } |
| 1372 | |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1373 | static int i915_fbc_status(struct seq_file *m, void *unused) |
| 1374 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1375 | struct drm_info_node *node = m->private; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1376 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1377 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1378 | |
Daniel Vetter | 3a77c4c | 2014-01-10 08:50:12 +0100 | [diff] [blame] | 1379 | if (!HAS_FBC(dev)) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1380 | seq_puts(m, "FBC unsupported on this chipset\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1381 | return 0; |
| 1382 | } |
| 1383 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1384 | intel_runtime_pm_get(dev_priv); |
| 1385 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1386 | if (intel_fbc_enabled(dev)) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1387 | seq_puts(m, "FBC enabled\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1388 | } else { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1389 | seq_puts(m, "FBC disabled: "); |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 1390 | switch (dev_priv->fbc.no_fbc_reason) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 1391 | case FBC_OK: |
| 1392 | seq_puts(m, "FBC actived, but currently disabled in hardware"); |
| 1393 | break; |
| 1394 | case FBC_UNSUPPORTED: |
| 1395 | seq_puts(m, "unsupported by this chipset"); |
| 1396 | break; |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1397 | case FBC_NO_OUTPUT: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1398 | seq_puts(m, "no outputs"); |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1399 | break; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1400 | case FBC_STOLEN_TOO_SMALL: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1401 | seq_puts(m, "not enough stolen memory"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1402 | break; |
| 1403 | case FBC_UNSUPPORTED_MODE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1404 | seq_puts(m, "mode not supported"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1405 | break; |
| 1406 | case FBC_MODE_TOO_LARGE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1407 | seq_puts(m, "mode too large"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1408 | break; |
| 1409 | case FBC_BAD_PLANE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1410 | seq_puts(m, "FBC unsupported on plane"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1411 | break; |
| 1412 | case FBC_NOT_TILED: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1413 | seq_puts(m, "scanout buffer not tiled"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1414 | break; |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1415 | case FBC_MULTIPLE_PIPES: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1416 | seq_puts(m, "multiple pipes are enabled"); |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1417 | break; |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 1418 | case FBC_MODULE_PARAM: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1419 | seq_puts(m, "disabled per module param (default off)"); |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 1420 | break; |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 1421 | case FBC_CHIP_DEFAULT: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1422 | seq_puts(m, "disabled per chip default"); |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 1423 | break; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1424 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1425 | seq_puts(m, "unknown reason"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1426 | } |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1427 | seq_putc(m, '\n'); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1428 | } |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1429 | |
| 1430 | intel_runtime_pm_put(dev_priv); |
| 1431 | |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1432 | return 0; |
| 1433 | } |
| 1434 | |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1435 | static int i915_ips_status(struct seq_file *m, void *unused) |
| 1436 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1437 | struct drm_info_node *node = m->private; |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1438 | struct drm_device *dev = node->minor->dev; |
| 1439 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1440 | |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 1441 | if (!HAS_IPS(dev)) { |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1442 | seq_puts(m, "not supported\n"); |
| 1443 | return 0; |
| 1444 | } |
| 1445 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1446 | intel_runtime_pm_get(dev_priv); |
| 1447 | |
Rodrigo Vivi | 0eaa53f | 2014-06-30 04:45:01 -0700 | [diff] [blame] | 1448 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
| 1449 | yesno(i915.enable_ips)); |
| 1450 | |
| 1451 | if (INTEL_INFO(dev)->gen >= 8) { |
| 1452 | seq_puts(m, "Currently: unknown\n"); |
| 1453 | } else { |
| 1454 | if (I915_READ(IPS_CTL) & IPS_ENABLE) |
| 1455 | seq_puts(m, "Currently: enabled\n"); |
| 1456 | else |
| 1457 | seq_puts(m, "Currently: disabled\n"); |
| 1458 | } |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1459 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1460 | intel_runtime_pm_put(dev_priv); |
| 1461 | |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1462 | return 0; |
| 1463 | } |
| 1464 | |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1465 | static int i915_sr_status(struct seq_file *m, void *unused) |
| 1466 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1467 | struct drm_info_node *node = m->private; |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1468 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1469 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1470 | bool sr_enabled = false; |
| 1471 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1472 | intel_runtime_pm_get(dev_priv); |
| 1473 | |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 1474 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 5ba2aaa | 2010-08-19 18:04:08 +0100 | [diff] [blame] | 1475 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1476 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1477 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
| 1478 | else if (IS_I915GM(dev)) |
| 1479 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
| 1480 | else if (IS_PINEVIEW(dev)) |
| 1481 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
| 1482 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1483 | intel_runtime_pm_put(dev_priv); |
| 1484 | |
Chris Wilson | 5ba2aaa | 2010-08-19 18:04:08 +0100 | [diff] [blame] | 1485 | seq_printf(m, "self-refresh: %s\n", |
| 1486 | sr_enabled ? "enabled" : "disabled"); |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1487 | |
| 1488 | return 0; |
| 1489 | } |
| 1490 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1491 | static int i915_emon_status(struct seq_file *m, void *unused) |
| 1492 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1493 | struct drm_info_node *node = m->private; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1494 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1495 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1496 | unsigned long temp, chipset, gfx; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1497 | int ret; |
| 1498 | |
Chris Wilson | 582be6b | 2012-04-30 19:35:02 +0100 | [diff] [blame] | 1499 | if (!IS_GEN5(dev)) |
| 1500 | return -ENODEV; |
| 1501 | |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1502 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1503 | if (ret) |
| 1504 | return ret; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1505 | |
| 1506 | temp = i915_mch_val(dev_priv); |
| 1507 | chipset = i915_chipset_val(dev_priv); |
| 1508 | gfx = i915_gfx_val(dev_priv); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1509 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1510 | |
| 1511 | seq_printf(m, "GMCH temp: %ld\n", temp); |
| 1512 | seq_printf(m, "Chipset power: %ld\n", chipset); |
| 1513 | seq_printf(m, "GFX power: %ld\n", gfx); |
| 1514 | seq_printf(m, "Total power: %ld\n", chipset + gfx); |
| 1515 | |
| 1516 | return 0; |
| 1517 | } |
| 1518 | |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1519 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
| 1520 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1521 | struct drm_info_node *node = m->private; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1522 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1523 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1524 | int ret = 0; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1525 | int gpu_freq, ia_freq; |
| 1526 | |
Jesse Barnes | 1c70c0c | 2011-06-29 13:34:36 -0700 | [diff] [blame] | 1527 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1528 | seq_puts(m, "unsupported on this chipset\n"); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1529 | return 0; |
| 1530 | } |
| 1531 | |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1532 | intel_runtime_pm_get(dev_priv); |
| 1533 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 1534 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 1535 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1536 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1537 | if (ret) |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1538 | goto out; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1539 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1540 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1541 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1542 | for (gpu_freq = dev_priv->rps.min_freq_softlimit; |
| 1543 | gpu_freq <= dev_priv->rps.max_freq_softlimit; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1544 | gpu_freq++) { |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 1545 | ia_freq = gpu_freq; |
| 1546 | sandybridge_pcode_read(dev_priv, |
| 1547 | GEN6_PCODE_READ_MIN_FREQ_TABLE, |
| 1548 | &ia_freq); |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 1549 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
| 1550 | gpu_freq * GT_FREQUENCY_MULTIPLIER, |
| 1551 | ((ia_freq >> 0) & 0xff) * 100, |
| 1552 | ((ia_freq >> 8) & 0xff) * 100); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1553 | } |
| 1554 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1555 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1556 | |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1557 | out: |
| 1558 | intel_runtime_pm_put(dev_priv); |
| 1559 | return ret; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1560 | } |
| 1561 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1562 | static int i915_opregion(struct seq_file *m, void *unused) |
| 1563 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1564 | struct drm_info_node *node = m->private; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1565 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1566 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1567 | struct intel_opregion *opregion = &dev_priv->opregion; |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1568 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1569 | int ret; |
| 1570 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1571 | if (data == NULL) |
| 1572 | return -ENOMEM; |
| 1573 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1574 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1575 | if (ret) |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1576 | goto out; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1577 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1578 | if (opregion->header) { |
| 1579 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); |
| 1580 | seq_write(m, data, OPREGION_SIZE); |
| 1581 | } |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1582 | |
| 1583 | mutex_unlock(&dev->struct_mutex); |
| 1584 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1585 | out: |
| 1586 | kfree(data); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1587 | return 0; |
| 1588 | } |
| 1589 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1590 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
| 1591 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1592 | struct drm_info_node *node = m->private; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1593 | struct drm_device *dev = node->minor->dev; |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1594 | struct intel_fbdev *ifbdev = NULL; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1595 | struct intel_framebuffer *fb; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1596 | |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1597 | #ifdef CONFIG_DRM_I915_FBDEV |
| 1598 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1599 | |
| 1600 | ifbdev = dev_priv->fbdev; |
| 1601 | fb = to_intel_framebuffer(ifbdev->helper.fb); |
| 1602 | |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1603 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1604 | fb->base.width, |
| 1605 | fb->base.height, |
| 1606 | fb->base.depth, |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1607 | fb->base.bits_per_pixel, |
| 1608 | atomic_read(&fb->base.refcount.refcount)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1609 | describe_obj(m, fb->obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1610 | seq_putc(m, '\n'); |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1611 | #endif |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1612 | |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1613 | mutex_lock(&dev->mode_config.fb_lock); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1614 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
Daniel Vetter | 131a56d | 2013-10-17 14:35:31 +0200 | [diff] [blame] | 1615 | if (ifbdev && &fb->base == ifbdev->helper.fb) |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1616 | continue; |
| 1617 | |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1618 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1619 | fb->base.width, |
| 1620 | fb->base.height, |
| 1621 | fb->base.depth, |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1622 | fb->base.bits_per_pixel, |
| 1623 | atomic_read(&fb->base.refcount.refcount)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1624 | describe_obj(m, fb->obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1625 | seq_putc(m, '\n'); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1626 | } |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1627 | mutex_unlock(&dev->mode_config.fb_lock); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1628 | |
| 1629 | return 0; |
| 1630 | } |
| 1631 | |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1632 | static int i915_context_status(struct seq_file *m, void *unused) |
| 1633 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1634 | struct drm_info_node *node = m->private; |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1635 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1636 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1637 | struct intel_engine_cs *ring; |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 1638 | struct intel_context *ctx; |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 1639 | int ret, i; |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1640 | |
Daniel Vetter | f3d2887 | 2014-05-29 23:23:08 +0200 | [diff] [blame] | 1641 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1642 | if (ret) |
| 1643 | return ret; |
| 1644 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1645 | if (dev_priv->ips.pwrctx) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1646 | seq_puts(m, "power context "); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1647 | describe_obj(m, dev_priv->ips.pwrctx); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1648 | seq_putc(m, '\n'); |
Ben Widawsky | dc501fb | 2011-06-29 11:41:51 -0700 | [diff] [blame] | 1649 | } |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1650 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1651 | if (dev_priv->ips.renderctx) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1652 | seq_puts(m, "render context "); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1653 | describe_obj(m, dev_priv->ips.renderctx); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1654 | seq_putc(m, '\n'); |
Ben Widawsky | dc501fb | 2011-06-29 11:41:51 -0700 | [diff] [blame] | 1655 | } |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1656 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1657 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
Oscar Mateo | ea0c76f | 2014-07-03 16:27:59 +0100 | [diff] [blame] | 1658 | if (ctx->legacy_hw_ctx.rcs_state == NULL) |
Chris Wilson | b77f699 | 2014-04-30 08:30:00 +0100 | [diff] [blame] | 1659 | continue; |
| 1660 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1661 | seq_puts(m, "HW context "); |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 1662 | describe_ctx(m, ctx); |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1663 | for_each_ring(ring, dev_priv, i) |
| 1664 | if (ring->default_context == ctx) |
| 1665 | seq_printf(m, "(default context %s) ", ring->name); |
| 1666 | |
Oscar Mateo | ea0c76f | 2014-07-03 16:27:59 +0100 | [diff] [blame] | 1667 | describe_obj(m, ctx->legacy_hw_ctx.rcs_state); |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1668 | seq_putc(m, '\n'); |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 1669 | } |
| 1670 | |
Daniel Vetter | f3d2887 | 2014-05-29 23:23:08 +0200 | [diff] [blame] | 1671 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1672 | |
| 1673 | return 0; |
| 1674 | } |
| 1675 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1676 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
| 1677 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1678 | struct drm_info_node *node = m->private; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1679 | struct drm_device *dev = node->minor->dev; |
| 1680 | struct drm_i915_private *dev_priv = dev->dev_private; |
Deepak S | 43709ba | 2013-11-23 14:55:44 +0530 | [diff] [blame] | 1681 | unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1682 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1683 | spin_lock_irq(&dev_priv->uncore.lock); |
Deepak S | 43709ba | 2013-11-23 14:55:44 +0530 | [diff] [blame] | 1684 | if (IS_VALLEYVIEW(dev)) { |
| 1685 | fw_rendercount = dev_priv->uncore.fw_rendercount; |
| 1686 | fw_mediacount = dev_priv->uncore.fw_mediacount; |
| 1687 | } else |
| 1688 | forcewake_count = dev_priv->uncore.forcewake_count; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1689 | spin_unlock_irq(&dev_priv->uncore.lock); |
Daniel Vetter | 9f1f46a | 2011-12-14 13:57:03 +0100 | [diff] [blame] | 1690 | |
Deepak S | 43709ba | 2013-11-23 14:55:44 +0530 | [diff] [blame] | 1691 | if (IS_VALLEYVIEW(dev)) { |
| 1692 | seq_printf(m, "fw_rendercount = %u\n", fw_rendercount); |
| 1693 | seq_printf(m, "fw_mediacount = %u\n", fw_mediacount); |
| 1694 | } else |
| 1695 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1696 | |
| 1697 | return 0; |
| 1698 | } |
| 1699 | |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1700 | static const char *swizzle_string(unsigned swizzle) |
| 1701 | { |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 1702 | switch (swizzle) { |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1703 | case I915_BIT_6_SWIZZLE_NONE: |
| 1704 | return "none"; |
| 1705 | case I915_BIT_6_SWIZZLE_9: |
| 1706 | return "bit9"; |
| 1707 | case I915_BIT_6_SWIZZLE_9_10: |
| 1708 | return "bit9/bit10"; |
| 1709 | case I915_BIT_6_SWIZZLE_9_11: |
| 1710 | return "bit9/bit11"; |
| 1711 | case I915_BIT_6_SWIZZLE_9_10_11: |
| 1712 | return "bit9/bit10/bit11"; |
| 1713 | case I915_BIT_6_SWIZZLE_9_17: |
| 1714 | return "bit9/bit17"; |
| 1715 | case I915_BIT_6_SWIZZLE_9_10_17: |
| 1716 | return "bit9/bit10/bit17"; |
| 1717 | case I915_BIT_6_SWIZZLE_UNKNOWN: |
Masanari Iida | 8a168ca | 2012-12-29 02:00:09 +0900 | [diff] [blame] | 1718 | return "unknown"; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1719 | } |
| 1720 | |
| 1721 | return "bug"; |
| 1722 | } |
| 1723 | |
| 1724 | static int i915_swizzle_info(struct seq_file *m, void *data) |
| 1725 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1726 | struct drm_info_node *node = m->private; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1727 | struct drm_device *dev = node->minor->dev; |
| 1728 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1729 | int ret; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1730 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1731 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1732 | if (ret) |
| 1733 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1734 | intel_runtime_pm_get(dev_priv); |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1735 | |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1736 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
| 1737 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); |
| 1738 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", |
| 1739 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); |
| 1740 | |
| 1741 | if (IS_GEN3(dev) || IS_GEN4(dev)) { |
| 1742 | seq_printf(m, "DDC = 0x%08x\n", |
| 1743 | I915_READ(DCC)); |
| 1744 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
| 1745 | I915_READ16(C0DRB3)); |
| 1746 | seq_printf(m, "C1DRB3 = 0x%04x\n", |
| 1747 | I915_READ16(C1DRB3)); |
Ben Widawsky | 9d3203e | 2013-11-02 21:07:14 -0700 | [diff] [blame] | 1748 | } else if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | 3fa7d23 | 2012-01-31 16:47:56 +0100 | [diff] [blame] | 1749 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
| 1750 | I915_READ(MAD_DIMM_C0)); |
| 1751 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", |
| 1752 | I915_READ(MAD_DIMM_C1)); |
| 1753 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", |
| 1754 | I915_READ(MAD_DIMM_C2)); |
| 1755 | seq_printf(m, "TILECTL = 0x%08x\n", |
| 1756 | I915_READ(TILECTL)); |
Ben Widawsky | 9d3203e | 2013-11-02 21:07:14 -0700 | [diff] [blame] | 1757 | if (IS_GEN8(dev)) |
| 1758 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
| 1759 | I915_READ(GAMTARBMODE)); |
| 1760 | else |
| 1761 | seq_printf(m, "ARB_MODE = 0x%08x\n", |
| 1762 | I915_READ(ARB_MODE)); |
Daniel Vetter | 3fa7d23 | 2012-01-31 16:47:56 +0100 | [diff] [blame] | 1763 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
| 1764 | I915_READ(DISP_ARB_CTL)); |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1765 | } |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1766 | intel_runtime_pm_put(dev_priv); |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1767 | mutex_unlock(&dev->struct_mutex); |
| 1768 | |
| 1769 | return 0; |
| 1770 | } |
| 1771 | |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 1772 | static int per_file_ctx(int id, void *ptr, void *data) |
| 1773 | { |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 1774 | struct intel_context *ctx = ptr; |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 1775 | struct seq_file *m = data; |
| 1776 | struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx); |
| 1777 | |
Oscar Mateo | f83d651 | 2014-05-22 14:13:38 +0100 | [diff] [blame] | 1778 | if (i915_gem_context_is_default(ctx)) |
| 1779 | seq_puts(m, " default context:\n"); |
| 1780 | else |
Oscar Mateo | 821d66d | 2014-07-03 16:28:00 +0100 | [diff] [blame] | 1781 | seq_printf(m, " context %d:\n", ctx->user_handle); |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 1782 | ppgtt->debug_dump(ppgtt, m); |
| 1783 | |
| 1784 | return 0; |
| 1785 | } |
| 1786 | |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 1787 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1788 | { |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1789 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1790 | struct intel_engine_cs *ring; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 1791 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 1792 | int unused, i; |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1793 | |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 1794 | if (!ppgtt) |
| 1795 | return; |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1796 | |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 1797 | seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages); |
Ben Widawsky | 5abbcca | 2014-02-21 13:06:34 -0800 | [diff] [blame] | 1798 | seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 1799 | for_each_ring(ring, dev_priv, unused) { |
| 1800 | seq_printf(m, "%s\n", ring->name); |
| 1801 | for (i = 0; i < 4; i++) { |
| 1802 | u32 offset = 0x270 + i * 8; |
| 1803 | u64 pdp = I915_READ(ring->mmio_base + offset + 4); |
| 1804 | pdp <<= 32; |
| 1805 | pdp |= I915_READ(ring->mmio_base + offset); |
Ville Syrjälä | a2a5b15 | 2014-03-31 18:17:16 +0300 | [diff] [blame] | 1806 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 1807 | } |
| 1808 | } |
| 1809 | } |
| 1810 | |
| 1811 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
| 1812 | { |
| 1813 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1814 | struct intel_engine_cs *ring; |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 1815 | struct drm_file *file; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 1816 | int i; |
| 1817 | |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1818 | if (INTEL_INFO(dev)->gen == 6) |
| 1819 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
| 1820 | |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 1821 | for_each_ring(ring, dev_priv, i) { |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1822 | seq_printf(m, "%s\n", ring->name); |
| 1823 | if (INTEL_INFO(dev)->gen == 7) |
| 1824 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); |
| 1825 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); |
| 1826 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); |
| 1827 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); |
| 1828 | } |
| 1829 | if (dev_priv->mm.aliasing_ppgtt) { |
| 1830 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 1831 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1832 | seq_puts(m, "aliasing PPGTT:\n"); |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1833 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 1834 | |
Ben Widawsky | 87d60b6 | 2013-12-06 14:11:29 -0800 | [diff] [blame] | 1835 | ppgtt->debug_dump(ppgtt, m); |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 1836 | } else |
| 1837 | return; |
| 1838 | |
| 1839 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
| 1840 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 1841 | |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 1842 | seq_printf(m, "proc: %s\n", |
| 1843 | get_pid_task(file->pid, PIDTYPE_PID)->comm); |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 1844 | idr_for_each(&file_priv->context_idr, per_file_ctx, m); |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1845 | } |
| 1846 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 1847 | } |
| 1848 | |
| 1849 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
| 1850 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1851 | struct drm_info_node *node = m->private; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 1852 | struct drm_device *dev = node->minor->dev; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1853 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 1854 | |
| 1855 | int ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1856 | if (ret) |
| 1857 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1858 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 1859 | |
| 1860 | if (INTEL_INFO(dev)->gen >= 8) |
| 1861 | gen8_ppgtt_info(m, dev); |
| 1862 | else if (INTEL_INFO(dev)->gen >= 6) |
| 1863 | gen6_ppgtt_info(m, dev); |
| 1864 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1865 | intel_runtime_pm_put(dev_priv); |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1866 | mutex_unlock(&dev->struct_mutex); |
| 1867 | |
| 1868 | return 0; |
| 1869 | } |
| 1870 | |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 1871 | static int i915_llc(struct seq_file *m, void *data) |
| 1872 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1873 | struct drm_info_node *node = m->private; |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 1874 | struct drm_device *dev = node->minor->dev; |
| 1875 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1876 | |
| 1877 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ |
| 1878 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); |
| 1879 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); |
| 1880 | |
| 1881 | return 0; |
| 1882 | } |
| 1883 | |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 1884 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
| 1885 | { |
| 1886 | struct drm_info_node *node = m->private; |
| 1887 | struct drm_device *dev = node->minor->dev; |
| 1888 | struct drm_i915_private *dev_priv = dev->dev_private; |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1889 | u32 psrperf = 0; |
| 1890 | bool enabled = false; |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 1891 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1892 | intel_runtime_pm_get(dev_priv); |
| 1893 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1894 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
| 1895 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); |
Rodrigo Vivi | 5755c78 | 2014-06-12 10:16:45 -0700 | [diff] [blame] | 1896 | seq_printf(m, "Enabled: %s\n", yesno(dev_priv->psr.enabled)); |
| 1897 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 1898 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1899 | enabled = HAS_PSR(dev) && |
| 1900 | I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; |
Rodrigo Vivi | 5755c78 | 2014-06-12 10:16:45 -0700 | [diff] [blame] | 1901 | seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled)); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 1902 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1903 | if (HAS_PSR(dev)) |
| 1904 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & |
| 1905 | EDP_PSR_PERF_CNT_MASK; |
| 1906 | seq_printf(m, "Performance_Counter: %u\n", psrperf); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 1907 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1908 | intel_runtime_pm_put(dev_priv); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 1909 | return 0; |
| 1910 | } |
| 1911 | |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 1912 | static int i915_sink_crc(struct seq_file *m, void *data) |
| 1913 | { |
| 1914 | struct drm_info_node *node = m->private; |
| 1915 | struct drm_device *dev = node->minor->dev; |
| 1916 | struct intel_encoder *encoder; |
| 1917 | struct intel_connector *connector; |
| 1918 | struct intel_dp *intel_dp = NULL; |
| 1919 | int ret; |
| 1920 | u8 crc[6]; |
| 1921 | |
| 1922 | drm_modeset_lock_all(dev); |
| 1923 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 1924 | base.head) { |
| 1925 | |
| 1926 | if (connector->base.dpms != DRM_MODE_DPMS_ON) |
| 1927 | continue; |
| 1928 | |
Paulo Zanoni | b6ae3c7 | 2014-02-13 17:51:33 -0200 | [diff] [blame] | 1929 | if (!connector->base.encoder) |
| 1930 | continue; |
| 1931 | |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 1932 | encoder = to_intel_encoder(connector->base.encoder); |
| 1933 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 1934 | continue; |
| 1935 | |
| 1936 | intel_dp = enc_to_intel_dp(&encoder->base); |
| 1937 | |
| 1938 | ret = intel_dp_sink_crc(intel_dp, crc); |
| 1939 | if (ret) |
| 1940 | goto out; |
| 1941 | |
| 1942 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", |
| 1943 | crc[0], crc[1], crc[2], |
| 1944 | crc[3], crc[4], crc[5]); |
| 1945 | goto out; |
| 1946 | } |
| 1947 | ret = -ENODEV; |
| 1948 | out: |
| 1949 | drm_modeset_unlock_all(dev); |
| 1950 | return ret; |
| 1951 | } |
| 1952 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 1953 | static int i915_energy_uJ(struct seq_file *m, void *data) |
| 1954 | { |
| 1955 | struct drm_info_node *node = m->private; |
| 1956 | struct drm_device *dev = node->minor->dev; |
| 1957 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1958 | u64 power; |
| 1959 | u32 units; |
| 1960 | |
| 1961 | if (INTEL_INFO(dev)->gen < 6) |
| 1962 | return -ENODEV; |
| 1963 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1964 | intel_runtime_pm_get(dev_priv); |
| 1965 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 1966 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
| 1967 | power = (power & 0x1f00) >> 8; |
| 1968 | units = 1000000 / (1 << power); /* convert to uJ */ |
| 1969 | power = I915_READ(MCH_SECP_NRG_STTS); |
| 1970 | power *= units; |
| 1971 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1972 | intel_runtime_pm_put(dev_priv); |
| 1973 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 1974 | seq_printf(m, "%llu", (long long unsigned)power); |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 1975 | |
| 1976 | return 0; |
| 1977 | } |
| 1978 | |
| 1979 | static int i915_pc8_status(struct seq_file *m, void *unused) |
| 1980 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1981 | struct drm_info_node *node = m->private; |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 1982 | struct drm_device *dev = node->minor->dev; |
| 1983 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1984 | |
Zhenyu Wang | 85b8d5c | 2014-04-01 19:39:48 -0300 | [diff] [blame] | 1985 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 1986 | seq_puts(m, "not supported\n"); |
| 1987 | return 0; |
| 1988 | } |
| 1989 | |
Paulo Zanoni | 86c4ec0 | 2014-02-21 13:52:24 -0300 | [diff] [blame] | 1990 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 1991 | seq_printf(m, "IRQs disabled: %s\n", |
Paulo Zanoni | 5d584b2 | 2014-03-07 20:08:15 -0300 | [diff] [blame] | 1992 | yesno(dev_priv->pm.irqs_disabled)); |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 1993 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 1994 | return 0; |
| 1995 | } |
| 1996 | |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 1997 | static const char *power_domain_str(enum intel_display_power_domain domain) |
| 1998 | { |
| 1999 | switch (domain) { |
| 2000 | case POWER_DOMAIN_PIPE_A: |
| 2001 | return "PIPE_A"; |
| 2002 | case POWER_DOMAIN_PIPE_B: |
| 2003 | return "PIPE_B"; |
| 2004 | case POWER_DOMAIN_PIPE_C: |
| 2005 | return "PIPE_C"; |
| 2006 | case POWER_DOMAIN_PIPE_A_PANEL_FITTER: |
| 2007 | return "PIPE_A_PANEL_FITTER"; |
| 2008 | case POWER_DOMAIN_PIPE_B_PANEL_FITTER: |
| 2009 | return "PIPE_B_PANEL_FITTER"; |
| 2010 | case POWER_DOMAIN_PIPE_C_PANEL_FITTER: |
| 2011 | return "PIPE_C_PANEL_FITTER"; |
| 2012 | case POWER_DOMAIN_TRANSCODER_A: |
| 2013 | return "TRANSCODER_A"; |
| 2014 | case POWER_DOMAIN_TRANSCODER_B: |
| 2015 | return "TRANSCODER_B"; |
| 2016 | case POWER_DOMAIN_TRANSCODER_C: |
| 2017 | return "TRANSCODER_C"; |
| 2018 | case POWER_DOMAIN_TRANSCODER_EDP: |
| 2019 | return "TRANSCODER_EDP"; |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 2020 | case POWER_DOMAIN_PORT_DDI_A_2_LANES: |
| 2021 | return "PORT_DDI_A_2_LANES"; |
| 2022 | case POWER_DOMAIN_PORT_DDI_A_4_LANES: |
| 2023 | return "PORT_DDI_A_4_LANES"; |
| 2024 | case POWER_DOMAIN_PORT_DDI_B_2_LANES: |
| 2025 | return "PORT_DDI_B_2_LANES"; |
| 2026 | case POWER_DOMAIN_PORT_DDI_B_4_LANES: |
| 2027 | return "PORT_DDI_B_4_LANES"; |
| 2028 | case POWER_DOMAIN_PORT_DDI_C_2_LANES: |
| 2029 | return "PORT_DDI_C_2_LANES"; |
| 2030 | case POWER_DOMAIN_PORT_DDI_C_4_LANES: |
| 2031 | return "PORT_DDI_C_4_LANES"; |
| 2032 | case POWER_DOMAIN_PORT_DDI_D_2_LANES: |
| 2033 | return "PORT_DDI_D_2_LANES"; |
| 2034 | case POWER_DOMAIN_PORT_DDI_D_4_LANES: |
| 2035 | return "PORT_DDI_D_4_LANES"; |
| 2036 | case POWER_DOMAIN_PORT_DSI: |
| 2037 | return "PORT_DSI"; |
| 2038 | case POWER_DOMAIN_PORT_CRT: |
| 2039 | return "PORT_CRT"; |
| 2040 | case POWER_DOMAIN_PORT_OTHER: |
| 2041 | return "PORT_OTHER"; |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 2042 | case POWER_DOMAIN_VGA: |
| 2043 | return "VGA"; |
| 2044 | case POWER_DOMAIN_AUDIO: |
| 2045 | return "AUDIO"; |
Paulo Zanoni | bd2bb1b | 2014-07-04 11:27:38 -0300 | [diff] [blame^] | 2046 | case POWER_DOMAIN_PLLS: |
| 2047 | return "PLLS"; |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 2048 | case POWER_DOMAIN_INIT: |
| 2049 | return "INIT"; |
| 2050 | default: |
| 2051 | WARN_ON(1); |
| 2052 | return "?"; |
| 2053 | } |
| 2054 | } |
| 2055 | |
| 2056 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
| 2057 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2058 | struct drm_info_node *node = m->private; |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 2059 | struct drm_device *dev = node->minor->dev; |
| 2060 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2061 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 2062 | int i; |
| 2063 | |
| 2064 | mutex_lock(&power_domains->lock); |
| 2065 | |
| 2066 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); |
| 2067 | for (i = 0; i < power_domains->power_well_count; i++) { |
| 2068 | struct i915_power_well *power_well; |
| 2069 | enum intel_display_power_domain power_domain; |
| 2070 | |
| 2071 | power_well = &power_domains->power_wells[i]; |
| 2072 | seq_printf(m, "%-25s %d\n", power_well->name, |
| 2073 | power_well->count); |
| 2074 | |
| 2075 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; |
| 2076 | power_domain++) { |
| 2077 | if (!(BIT(power_domain) & power_well->domains)) |
| 2078 | continue; |
| 2079 | |
| 2080 | seq_printf(m, " %-23s %d\n", |
| 2081 | power_domain_str(power_domain), |
| 2082 | power_domains->domain_use_count[power_domain]); |
| 2083 | } |
| 2084 | } |
| 2085 | |
| 2086 | mutex_unlock(&power_domains->lock); |
| 2087 | |
| 2088 | return 0; |
| 2089 | } |
| 2090 | |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2091 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
| 2092 | struct drm_display_mode *mode) |
| 2093 | { |
| 2094 | int i; |
| 2095 | |
| 2096 | for (i = 0; i < tabs; i++) |
| 2097 | seq_putc(m, '\t'); |
| 2098 | |
| 2099 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", |
| 2100 | mode->base.id, mode->name, |
| 2101 | mode->vrefresh, mode->clock, |
| 2102 | mode->hdisplay, mode->hsync_start, |
| 2103 | mode->hsync_end, mode->htotal, |
| 2104 | mode->vdisplay, mode->vsync_start, |
| 2105 | mode->vsync_end, mode->vtotal, |
| 2106 | mode->type, mode->flags); |
| 2107 | } |
| 2108 | |
| 2109 | static void intel_encoder_info(struct seq_file *m, |
| 2110 | struct intel_crtc *intel_crtc, |
| 2111 | struct intel_encoder *intel_encoder) |
| 2112 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2113 | struct drm_info_node *node = m->private; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2114 | struct drm_device *dev = node->minor->dev; |
| 2115 | struct drm_crtc *crtc = &intel_crtc->base; |
| 2116 | struct intel_connector *intel_connector; |
| 2117 | struct drm_encoder *encoder; |
| 2118 | |
| 2119 | encoder = &intel_encoder->base; |
| 2120 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", |
Jani Nikula | 8e329a0 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 2121 | encoder->base.id, encoder->name); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2122 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
| 2123 | struct drm_connector *connector = &intel_connector->base; |
| 2124 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", |
| 2125 | connector->base.id, |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 2126 | connector->name, |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2127 | drm_get_connector_status_name(connector->status)); |
| 2128 | if (connector->status == connector_status_connected) { |
| 2129 | struct drm_display_mode *mode = &crtc->mode; |
| 2130 | seq_printf(m, ", mode:\n"); |
| 2131 | intel_seq_print_mode(m, 2, mode); |
| 2132 | } else { |
| 2133 | seq_putc(m, '\n'); |
| 2134 | } |
| 2135 | } |
| 2136 | } |
| 2137 | |
| 2138 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) |
| 2139 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2140 | struct drm_info_node *node = m->private; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2141 | struct drm_device *dev = node->minor->dev; |
| 2142 | struct drm_crtc *crtc = &intel_crtc->base; |
| 2143 | struct intel_encoder *intel_encoder; |
| 2144 | |
Matt Roper | 5aa8a93 | 2014-06-16 10:12:55 -0700 | [diff] [blame] | 2145 | if (crtc->primary->fb) |
| 2146 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
| 2147 | crtc->primary->fb->base.id, crtc->x, crtc->y, |
| 2148 | crtc->primary->fb->width, crtc->primary->fb->height); |
| 2149 | else |
| 2150 | seq_puts(m, "\tprimary plane disabled\n"); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2151 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
| 2152 | intel_encoder_info(m, intel_crtc, intel_encoder); |
| 2153 | } |
| 2154 | |
| 2155 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) |
| 2156 | { |
| 2157 | struct drm_display_mode *mode = panel->fixed_mode; |
| 2158 | |
| 2159 | seq_printf(m, "\tfixed mode:\n"); |
| 2160 | intel_seq_print_mode(m, 2, mode); |
| 2161 | } |
| 2162 | |
| 2163 | static void intel_dp_info(struct seq_file *m, |
| 2164 | struct intel_connector *intel_connector) |
| 2165 | { |
| 2166 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
| 2167 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
| 2168 | |
| 2169 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); |
| 2170 | seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" : |
| 2171 | "no"); |
| 2172 | if (intel_encoder->type == INTEL_OUTPUT_EDP) |
| 2173 | intel_panel_info(m, &intel_connector->panel); |
| 2174 | } |
| 2175 | |
| 2176 | static void intel_hdmi_info(struct seq_file *m, |
| 2177 | struct intel_connector *intel_connector) |
| 2178 | { |
| 2179 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
| 2180 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); |
| 2181 | |
| 2182 | seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" : |
| 2183 | "no"); |
| 2184 | } |
| 2185 | |
| 2186 | static void intel_lvds_info(struct seq_file *m, |
| 2187 | struct intel_connector *intel_connector) |
| 2188 | { |
| 2189 | intel_panel_info(m, &intel_connector->panel); |
| 2190 | } |
| 2191 | |
| 2192 | static void intel_connector_info(struct seq_file *m, |
| 2193 | struct drm_connector *connector) |
| 2194 | { |
| 2195 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 2196 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
Jesse Barnes | f103fc7 | 2014-02-20 12:39:57 -0800 | [diff] [blame] | 2197 | struct drm_display_mode *mode; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2198 | |
| 2199 | seq_printf(m, "connector %d: type %s, status: %s\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 2200 | connector->base.id, connector->name, |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2201 | drm_get_connector_status_name(connector->status)); |
| 2202 | if (connector->status == connector_status_connected) { |
| 2203 | seq_printf(m, "\tname: %s\n", connector->display_info.name); |
| 2204 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", |
| 2205 | connector->display_info.width_mm, |
| 2206 | connector->display_info.height_mm); |
| 2207 | seq_printf(m, "\tsubpixel order: %s\n", |
| 2208 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); |
| 2209 | seq_printf(m, "\tCEA rev: %d\n", |
| 2210 | connector->display_info.cea_rev); |
| 2211 | } |
| 2212 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
| 2213 | intel_encoder->type == INTEL_OUTPUT_EDP) |
| 2214 | intel_dp_info(m, intel_connector); |
| 2215 | else if (intel_encoder->type == INTEL_OUTPUT_HDMI) |
| 2216 | intel_hdmi_info(m, intel_connector); |
| 2217 | else if (intel_encoder->type == INTEL_OUTPUT_LVDS) |
| 2218 | intel_lvds_info(m, intel_connector); |
| 2219 | |
Jesse Barnes | f103fc7 | 2014-02-20 12:39:57 -0800 | [diff] [blame] | 2220 | seq_printf(m, "\tmodes:\n"); |
| 2221 | list_for_each_entry(mode, &connector->modes, head) |
| 2222 | intel_seq_print_mode(m, 2, mode); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2223 | } |
| 2224 | |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2225 | static bool cursor_active(struct drm_device *dev, int pipe) |
| 2226 | { |
| 2227 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2228 | u32 state; |
| 2229 | |
| 2230 | if (IS_845G(dev) || IS_I865G(dev)) |
| 2231 | state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2232 | else |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 2233 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2234 | |
| 2235 | return state; |
| 2236 | } |
| 2237 | |
| 2238 | static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) |
| 2239 | { |
| 2240 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2241 | u32 pos; |
| 2242 | |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 2243 | pos = I915_READ(CURPOS(pipe)); |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2244 | |
| 2245 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; |
| 2246 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) |
| 2247 | *x = -*x; |
| 2248 | |
| 2249 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; |
| 2250 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) |
| 2251 | *y = -*y; |
| 2252 | |
| 2253 | return cursor_active(dev, pipe); |
| 2254 | } |
| 2255 | |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2256 | static int i915_display_info(struct seq_file *m, void *unused) |
| 2257 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2258 | struct drm_info_node *node = m->private; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2259 | struct drm_device *dev = node->minor->dev; |
Paulo Zanoni | b0e5ddf | 2014-04-01 14:55:10 -0300 | [diff] [blame] | 2260 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2261 | struct intel_crtc *crtc; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2262 | struct drm_connector *connector; |
| 2263 | |
Paulo Zanoni | b0e5ddf | 2014-04-01 14:55:10 -0300 | [diff] [blame] | 2264 | intel_runtime_pm_get(dev_priv); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2265 | drm_modeset_lock_all(dev); |
| 2266 | seq_printf(m, "CRTC info\n"); |
| 2267 | seq_printf(m, "---------\n"); |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 2268 | for_each_intel_crtc(dev, crtc) { |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2269 | bool active; |
| 2270 | int x, y; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2271 | |
Chris Wilson | 57127ef | 2014-07-04 08:20:11 +0100 | [diff] [blame] | 2272 | seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n", |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2273 | crtc->base.base.id, pipe_name(crtc->pipe), |
Chris Wilson | 57127ef | 2014-07-04 08:20:11 +0100 | [diff] [blame] | 2274 | yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h); |
Paulo Zanoni | a23dc65 | 2014-04-01 14:55:11 -0300 | [diff] [blame] | 2275 | if (crtc->active) { |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2276 | intel_crtc_info(m, crtc); |
| 2277 | |
Paulo Zanoni | a23dc65 | 2014-04-01 14:55:11 -0300 | [diff] [blame] | 2278 | active = cursor_position(dev, crtc->pipe, &x, &y); |
Chris Wilson | 57127ef | 2014-07-04 08:20:11 +0100 | [diff] [blame] | 2279 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 2280 | yesno(crtc->cursor_base), |
Chris Wilson | 57127ef | 2014-07-04 08:20:11 +0100 | [diff] [blame] | 2281 | x, y, crtc->cursor_width, crtc->cursor_height, |
| 2282 | crtc->cursor_addr, yesno(active)); |
Paulo Zanoni | a23dc65 | 2014-04-01 14:55:11 -0300 | [diff] [blame] | 2283 | } |
Daniel Vetter | cace841 | 2014-05-22 17:56:31 +0200 | [diff] [blame] | 2284 | |
| 2285 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", |
| 2286 | yesno(!crtc->cpu_fifo_underrun_disabled), |
| 2287 | yesno(!crtc->pch_fifo_underrun_disabled)); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2288 | } |
| 2289 | |
| 2290 | seq_printf(m, "\n"); |
| 2291 | seq_printf(m, "Connector info\n"); |
| 2292 | seq_printf(m, "--------------\n"); |
| 2293 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 2294 | intel_connector_info(m, connector); |
| 2295 | } |
| 2296 | drm_modeset_unlock_all(dev); |
Paulo Zanoni | b0e5ddf | 2014-04-01 14:55:10 -0300 | [diff] [blame] | 2297 | intel_runtime_pm_put(dev_priv); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2298 | |
| 2299 | return 0; |
| 2300 | } |
| 2301 | |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 2302 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
| 2303 | { |
| 2304 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2305 | struct drm_device *dev = node->minor->dev; |
| 2306 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2307 | struct intel_engine_cs *ring; |
| 2308 | int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
| 2309 | int i, j, ret; |
| 2310 | |
| 2311 | if (!i915_semaphore_is_enabled(dev)) { |
| 2312 | seq_puts(m, "Semaphores are disabled\n"); |
| 2313 | return 0; |
| 2314 | } |
| 2315 | |
| 2316 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2317 | if (ret) |
| 2318 | return ret; |
Paulo Zanoni | 0387206 | 2014-07-09 14:31:57 -0300 | [diff] [blame] | 2319 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 2320 | |
| 2321 | if (IS_BROADWELL(dev)) { |
| 2322 | struct page *page; |
| 2323 | uint64_t *seqno; |
| 2324 | |
| 2325 | page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0); |
| 2326 | |
| 2327 | seqno = (uint64_t *)kmap_atomic(page); |
| 2328 | for_each_ring(ring, dev_priv, i) { |
| 2329 | uint64_t offset; |
| 2330 | |
| 2331 | seq_printf(m, "%s\n", ring->name); |
| 2332 | |
| 2333 | seq_puts(m, " Last signal:"); |
| 2334 | for (j = 0; j < num_rings; j++) { |
| 2335 | offset = i * I915_NUM_RINGS + j; |
| 2336 | seq_printf(m, "0x%08llx (0x%02llx) ", |
| 2337 | seqno[offset], offset * 8); |
| 2338 | } |
| 2339 | seq_putc(m, '\n'); |
| 2340 | |
| 2341 | seq_puts(m, " Last wait: "); |
| 2342 | for (j = 0; j < num_rings; j++) { |
| 2343 | offset = i + (j * I915_NUM_RINGS); |
| 2344 | seq_printf(m, "0x%08llx (0x%02llx) ", |
| 2345 | seqno[offset], offset * 8); |
| 2346 | } |
| 2347 | seq_putc(m, '\n'); |
| 2348 | |
| 2349 | } |
| 2350 | kunmap_atomic(seqno); |
| 2351 | } else { |
| 2352 | seq_puts(m, " Last signal:"); |
| 2353 | for_each_ring(ring, dev_priv, i) |
| 2354 | for (j = 0; j < num_rings; j++) |
| 2355 | seq_printf(m, "0x%08x\n", |
| 2356 | I915_READ(ring->semaphore.mbox.signal[j])); |
| 2357 | seq_putc(m, '\n'); |
| 2358 | } |
| 2359 | |
| 2360 | seq_puts(m, "\nSync seqno:\n"); |
| 2361 | for_each_ring(ring, dev_priv, i) { |
| 2362 | for (j = 0; j < num_rings; j++) { |
| 2363 | seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]); |
| 2364 | } |
| 2365 | seq_putc(m, '\n'); |
| 2366 | } |
| 2367 | seq_putc(m, '\n'); |
| 2368 | |
Paulo Zanoni | 0387206 | 2014-07-09 14:31:57 -0300 | [diff] [blame] | 2369 | intel_runtime_pm_put(dev_priv); |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 2370 | mutex_unlock(&dev->struct_mutex); |
| 2371 | return 0; |
| 2372 | } |
| 2373 | |
Daniel Vetter | 728e29d | 2014-06-25 22:01:53 +0300 | [diff] [blame] | 2374 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
| 2375 | { |
| 2376 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2377 | struct drm_device *dev = node->minor->dev; |
| 2378 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2379 | int i; |
| 2380 | |
| 2381 | drm_modeset_lock_all(dev); |
| 2382 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 2383 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
| 2384 | |
| 2385 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); |
| 2386 | seq_printf(m, " refcount: %i, active: %i, on: %s\n", pll->refcount, |
| 2387 | pll->active, yesno(pll->on)); |
| 2388 | seq_printf(m, " tracked hardware state:\n"); |
| 2389 | seq_printf(m, " dpll: 0x%08x\n", pll->hw_state.dpll); |
| 2390 | seq_printf(m, " dpll_md: 0x%08x\n", pll->hw_state.dpll_md); |
| 2391 | seq_printf(m, " fp0: 0x%08x\n", pll->hw_state.fp0); |
| 2392 | seq_printf(m, " fp1: 0x%08x\n", pll->hw_state.fp1); |
| 2393 | } |
| 2394 | drm_modeset_unlock_all(dev); |
| 2395 | |
| 2396 | return 0; |
| 2397 | } |
| 2398 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2399 | struct pipe_crc_info { |
| 2400 | const char *name; |
| 2401 | struct drm_device *dev; |
| 2402 | enum pipe pipe; |
| 2403 | }; |
| 2404 | |
| 2405 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 2406 | { |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 2407 | struct pipe_crc_info *info = inode->i_private; |
| 2408 | struct drm_i915_private *dev_priv = info->dev->dev_private; |
| 2409 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
| 2410 | |
Daniel Vetter | 7eb1c49 | 2013-11-14 11:30:43 +0100 | [diff] [blame] | 2411 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
| 2412 | return -ENODEV; |
| 2413 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2414 | spin_lock_irq(&pipe_crc->lock); |
| 2415 | |
| 2416 | if (pipe_crc->opened) { |
| 2417 | spin_unlock_irq(&pipe_crc->lock); |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 2418 | return -EBUSY; /* already open */ |
| 2419 | } |
| 2420 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2421 | pipe_crc->opened = true; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2422 | filep->private_data = inode->i_private; |
| 2423 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2424 | spin_unlock_irq(&pipe_crc->lock); |
| 2425 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2426 | return 0; |
| 2427 | } |
| 2428 | |
| 2429 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) |
| 2430 | { |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 2431 | struct pipe_crc_info *info = inode->i_private; |
| 2432 | struct drm_i915_private *dev_priv = info->dev->dev_private; |
| 2433 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
| 2434 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2435 | spin_lock_irq(&pipe_crc->lock); |
| 2436 | pipe_crc->opened = false; |
| 2437 | spin_unlock_irq(&pipe_crc->lock); |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 2438 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2439 | return 0; |
| 2440 | } |
| 2441 | |
| 2442 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ |
| 2443 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) |
| 2444 | /* account for \'0' */ |
| 2445 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) |
| 2446 | |
| 2447 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) |
| 2448 | { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2449 | assert_spin_locked(&pipe_crc->lock); |
| 2450 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
| 2451 | INTEL_PIPE_CRC_ENTRIES_NR); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2452 | } |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 2453 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2454 | static ssize_t |
| 2455 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, |
| 2456 | loff_t *pos) |
| 2457 | { |
| 2458 | struct pipe_crc_info *info = filep->private_data; |
| 2459 | struct drm_device *dev = info->dev; |
| 2460 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2461 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
| 2462 | char buf[PIPE_CRC_BUFFER_LEN]; |
| 2463 | int head, tail, n_entries, n; |
| 2464 | ssize_t bytes_read; |
| 2465 | |
| 2466 | /* |
| 2467 | * Don't allow user space to provide buffers not big enough to hold |
| 2468 | * a line of data. |
| 2469 | */ |
| 2470 | if (count < PIPE_CRC_LINE_LEN) |
| 2471 | return -EINVAL; |
| 2472 | |
| 2473 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) |
| 2474 | return 0; |
| 2475 | |
| 2476 | /* nothing to read */ |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2477 | spin_lock_irq(&pipe_crc->lock); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2478 | while (pipe_crc_data_count(pipe_crc) == 0) { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2479 | int ret; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2480 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2481 | if (filep->f_flags & O_NONBLOCK) { |
| 2482 | spin_unlock_irq(&pipe_crc->lock); |
| 2483 | return -EAGAIN; |
| 2484 | } |
| 2485 | |
| 2486 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
| 2487 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); |
| 2488 | if (ret) { |
| 2489 | spin_unlock_irq(&pipe_crc->lock); |
| 2490 | return ret; |
| 2491 | } |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2492 | } |
| 2493 | |
| 2494 | /* We now have one or more entries to read */ |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2495 | head = pipe_crc->head; |
| 2496 | tail = pipe_crc->tail; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2497 | n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR), |
| 2498 | count / PIPE_CRC_LINE_LEN); |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2499 | spin_unlock_irq(&pipe_crc->lock); |
| 2500 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2501 | bytes_read = 0; |
| 2502 | n = 0; |
| 2503 | do { |
| 2504 | struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail]; |
| 2505 | int ret; |
| 2506 | |
| 2507 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
| 2508 | "%8u %8x %8x %8x %8x %8x\n", |
| 2509 | entry->frame, entry->crc[0], |
| 2510 | entry->crc[1], entry->crc[2], |
| 2511 | entry->crc[3], entry->crc[4]); |
| 2512 | |
| 2513 | ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN, |
| 2514 | buf, PIPE_CRC_LINE_LEN); |
| 2515 | if (ret == PIPE_CRC_LINE_LEN) |
| 2516 | return -EFAULT; |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 2517 | |
| 2518 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); |
| 2519 | tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2520 | n++; |
| 2521 | } while (--n_entries); |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 2522 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2523 | spin_lock_irq(&pipe_crc->lock); |
| 2524 | pipe_crc->tail = tail; |
| 2525 | spin_unlock_irq(&pipe_crc->lock); |
| 2526 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2527 | return bytes_read; |
| 2528 | } |
| 2529 | |
| 2530 | static const struct file_operations i915_pipe_crc_fops = { |
| 2531 | .owner = THIS_MODULE, |
| 2532 | .open = i915_pipe_crc_open, |
| 2533 | .read = i915_pipe_crc_read, |
| 2534 | .release = i915_pipe_crc_release, |
| 2535 | }; |
| 2536 | |
| 2537 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { |
| 2538 | { |
| 2539 | .name = "i915_pipe_A_crc", |
| 2540 | .pipe = PIPE_A, |
| 2541 | }, |
| 2542 | { |
| 2543 | .name = "i915_pipe_B_crc", |
| 2544 | .pipe = PIPE_B, |
| 2545 | }, |
| 2546 | { |
| 2547 | .name = "i915_pipe_C_crc", |
| 2548 | .pipe = PIPE_C, |
| 2549 | }, |
| 2550 | }; |
| 2551 | |
| 2552 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, |
| 2553 | enum pipe pipe) |
| 2554 | { |
| 2555 | struct drm_device *dev = minor->dev; |
| 2556 | struct dentry *ent; |
| 2557 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; |
| 2558 | |
| 2559 | info->dev = dev; |
| 2560 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, |
| 2561 | &i915_pipe_crc_fops); |
Wei Yongjun | f3c5fe9 | 2013-12-16 14:13:25 +0800 | [diff] [blame] | 2562 | if (!ent) |
| 2563 | return -ENOMEM; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2564 | |
| 2565 | return drm_add_fake_info_node(minor, ent, info); |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 2566 | } |
| 2567 | |
Daniel Vetter | e8dfcf7 | 2013-10-16 11:51:54 +0200 | [diff] [blame] | 2568 | static const char * const pipe_crc_sources[] = { |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2569 | "none", |
| 2570 | "plane1", |
| 2571 | "plane2", |
| 2572 | "pf", |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2573 | "pipe", |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 2574 | "TV", |
| 2575 | "DP-B", |
| 2576 | "DP-C", |
| 2577 | "DP-D", |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2578 | "auto", |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2579 | }; |
| 2580 | |
| 2581 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) |
| 2582 | { |
| 2583 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); |
| 2584 | return pipe_crc_sources[source]; |
| 2585 | } |
| 2586 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2587 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2588 | { |
| 2589 | struct drm_device *dev = m->private; |
| 2590 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2591 | int i; |
| 2592 | |
| 2593 | for (i = 0; i < I915_MAX_PIPES; i++) |
| 2594 | seq_printf(m, "%c %s\n", pipe_name(i), |
| 2595 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); |
| 2596 | |
| 2597 | return 0; |
| 2598 | } |
| 2599 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2600 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2601 | { |
| 2602 | struct drm_device *dev = inode->i_private; |
| 2603 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2604 | return single_open(file, display_crc_ctl_show, dev); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2605 | } |
| 2606 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2607 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 2608 | uint32_t *val) |
| 2609 | { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2610 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
| 2611 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; |
| 2612 | |
| 2613 | switch (*source) { |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 2614 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 2615 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; |
| 2616 | break; |
| 2617 | case INTEL_PIPE_CRC_SOURCE_NONE: |
| 2618 | *val = 0; |
| 2619 | break; |
| 2620 | default: |
| 2621 | return -EINVAL; |
| 2622 | } |
| 2623 | |
| 2624 | return 0; |
| 2625 | } |
| 2626 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2627 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
| 2628 | enum intel_pipe_crc_source *source) |
| 2629 | { |
| 2630 | struct intel_encoder *encoder; |
| 2631 | struct intel_crtc *crtc; |
Daniel Vetter | 2675680 | 2013-11-01 10:50:23 +0100 | [diff] [blame] | 2632 | struct intel_digital_port *dig_port; |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2633 | int ret = 0; |
| 2634 | |
| 2635 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; |
| 2636 | |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 2637 | drm_modeset_lock_all(dev); |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2638 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
| 2639 | base.head) { |
| 2640 | if (!encoder->base.crtc) |
| 2641 | continue; |
| 2642 | |
| 2643 | crtc = to_intel_crtc(encoder->base.crtc); |
| 2644 | |
| 2645 | if (crtc->pipe != pipe) |
| 2646 | continue; |
| 2647 | |
| 2648 | switch (encoder->type) { |
| 2649 | case INTEL_OUTPUT_TVOUT: |
| 2650 | *source = INTEL_PIPE_CRC_SOURCE_TV; |
| 2651 | break; |
| 2652 | case INTEL_OUTPUT_DISPLAYPORT: |
| 2653 | case INTEL_OUTPUT_EDP: |
Daniel Vetter | 2675680 | 2013-11-01 10:50:23 +0100 | [diff] [blame] | 2654 | dig_port = enc_to_dig_port(&encoder->base); |
| 2655 | switch (dig_port->port) { |
| 2656 | case PORT_B: |
| 2657 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; |
| 2658 | break; |
| 2659 | case PORT_C: |
| 2660 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; |
| 2661 | break; |
| 2662 | case PORT_D: |
| 2663 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; |
| 2664 | break; |
| 2665 | default: |
| 2666 | WARN(1, "nonexisting DP port %c\n", |
| 2667 | port_name(dig_port->port)); |
| 2668 | break; |
| 2669 | } |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2670 | break; |
| 2671 | } |
| 2672 | } |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 2673 | drm_modeset_unlock_all(dev); |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2674 | |
| 2675 | return ret; |
| 2676 | } |
| 2677 | |
| 2678 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, |
| 2679 | enum pipe pipe, |
| 2680 | enum intel_pipe_crc_source *source, |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 2681 | uint32_t *val) |
| 2682 | { |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 2683 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2684 | bool need_stable_symbols = false; |
| 2685 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2686 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
| 2687 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); |
| 2688 | if (ret) |
| 2689 | return ret; |
| 2690 | } |
| 2691 | |
| 2692 | switch (*source) { |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 2693 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 2694 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; |
| 2695 | break; |
| 2696 | case INTEL_PIPE_CRC_SOURCE_DP_B: |
| 2697 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 2698 | need_stable_symbols = true; |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 2699 | break; |
| 2700 | case INTEL_PIPE_CRC_SOURCE_DP_C: |
| 2701 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 2702 | need_stable_symbols = true; |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 2703 | break; |
| 2704 | case INTEL_PIPE_CRC_SOURCE_NONE: |
| 2705 | *val = 0; |
| 2706 | break; |
| 2707 | default: |
| 2708 | return -EINVAL; |
| 2709 | } |
| 2710 | |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 2711 | /* |
| 2712 | * When the pipe CRC tap point is after the transcoders we need |
| 2713 | * to tweak symbol-level features to produce a deterministic series of |
| 2714 | * symbols for a given frame. We need to reset those features only once |
| 2715 | * a frame (instead of every nth symbol): |
| 2716 | * - DC-balance: used to ensure a better clock recovery from the data |
| 2717 | * link (SDVO) |
| 2718 | * - DisplayPort scrambling: used for EMI reduction |
| 2719 | */ |
| 2720 | if (need_stable_symbols) { |
| 2721 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 2722 | |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 2723 | tmp |= DC_BALANCE_RESET_VLV; |
| 2724 | if (pipe == PIPE_A) |
| 2725 | tmp |= PIPE_A_SCRAMBLE_RESET; |
| 2726 | else |
| 2727 | tmp |= PIPE_B_SCRAMBLE_RESET; |
| 2728 | |
| 2729 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 2730 | } |
| 2731 | |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 2732 | return 0; |
| 2733 | } |
| 2734 | |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 2735 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2736 | enum pipe pipe, |
| 2737 | enum intel_pipe_crc_source *source, |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 2738 | uint32_t *val) |
| 2739 | { |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 2740 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2741 | bool need_stable_symbols = false; |
| 2742 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2743 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
| 2744 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); |
| 2745 | if (ret) |
| 2746 | return ret; |
| 2747 | } |
| 2748 | |
| 2749 | switch (*source) { |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 2750 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 2751 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; |
| 2752 | break; |
| 2753 | case INTEL_PIPE_CRC_SOURCE_TV: |
| 2754 | if (!SUPPORTS_TV(dev)) |
| 2755 | return -EINVAL; |
| 2756 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; |
| 2757 | break; |
| 2758 | case INTEL_PIPE_CRC_SOURCE_DP_B: |
| 2759 | if (!IS_G4X(dev)) |
| 2760 | return -EINVAL; |
| 2761 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 2762 | need_stable_symbols = true; |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 2763 | break; |
| 2764 | case INTEL_PIPE_CRC_SOURCE_DP_C: |
| 2765 | if (!IS_G4X(dev)) |
| 2766 | return -EINVAL; |
| 2767 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 2768 | need_stable_symbols = true; |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 2769 | break; |
| 2770 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
| 2771 | if (!IS_G4X(dev)) |
| 2772 | return -EINVAL; |
| 2773 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 2774 | need_stable_symbols = true; |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 2775 | break; |
| 2776 | case INTEL_PIPE_CRC_SOURCE_NONE: |
| 2777 | *val = 0; |
| 2778 | break; |
| 2779 | default: |
| 2780 | return -EINVAL; |
| 2781 | } |
| 2782 | |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 2783 | /* |
| 2784 | * When the pipe CRC tap point is after the transcoders we need |
| 2785 | * to tweak symbol-level features to produce a deterministic series of |
| 2786 | * symbols for a given frame. We need to reset those features only once |
| 2787 | * a frame (instead of every nth symbol): |
| 2788 | * - DC-balance: used to ensure a better clock recovery from the data |
| 2789 | * link (SDVO) |
| 2790 | * - DisplayPort scrambling: used for EMI reduction |
| 2791 | */ |
| 2792 | if (need_stable_symbols) { |
| 2793 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 2794 | |
| 2795 | WARN_ON(!IS_G4X(dev)); |
| 2796 | |
| 2797 | I915_WRITE(PORT_DFT_I9XX, |
| 2798 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); |
| 2799 | |
| 2800 | if (pipe == PIPE_A) |
| 2801 | tmp |= PIPE_A_SCRAMBLE_RESET; |
| 2802 | else |
| 2803 | tmp |= PIPE_B_SCRAMBLE_RESET; |
| 2804 | |
| 2805 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 2806 | } |
| 2807 | |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 2808 | return 0; |
| 2809 | } |
| 2810 | |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 2811 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
| 2812 | enum pipe pipe) |
| 2813 | { |
| 2814 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2815 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 2816 | |
| 2817 | if (pipe == PIPE_A) |
| 2818 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
| 2819 | else |
| 2820 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
| 2821 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
| 2822 | tmp &= ~DC_BALANCE_RESET_VLV; |
| 2823 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 2824 | |
| 2825 | } |
| 2826 | |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 2827 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
| 2828 | enum pipe pipe) |
| 2829 | { |
| 2830 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2831 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 2832 | |
| 2833 | if (pipe == PIPE_A) |
| 2834 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
| 2835 | else |
| 2836 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
| 2837 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 2838 | |
| 2839 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { |
| 2840 | I915_WRITE(PORT_DFT_I9XX, |
| 2841 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); |
| 2842 | } |
| 2843 | } |
| 2844 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2845 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2846 | uint32_t *val) |
| 2847 | { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2848 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
| 2849 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; |
| 2850 | |
| 2851 | switch (*source) { |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2852 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
| 2853 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; |
| 2854 | break; |
| 2855 | case INTEL_PIPE_CRC_SOURCE_PLANE2: |
| 2856 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; |
| 2857 | break; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2858 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 2859 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; |
| 2860 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 2861 | case INTEL_PIPE_CRC_SOURCE_NONE: |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2862 | *val = 0; |
| 2863 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 2864 | default: |
| 2865 | return -EINVAL; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2866 | } |
| 2867 | |
| 2868 | return 0; |
| 2869 | } |
| 2870 | |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 2871 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev) |
| 2872 | { |
| 2873 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2874 | struct intel_crtc *crtc = |
| 2875 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); |
| 2876 | |
| 2877 | drm_modeset_lock_all(dev); |
| 2878 | /* |
| 2879 | * If we use the eDP transcoder we need to make sure that we don't |
| 2880 | * bypass the pfit, since otherwise the pipe CRC source won't work. Only |
| 2881 | * relevant on hsw with pipe A when using the always-on power well |
| 2882 | * routing. |
| 2883 | */ |
| 2884 | if (crtc->config.cpu_transcoder == TRANSCODER_EDP && |
| 2885 | !crtc->config.pch_pfit.enabled) { |
| 2886 | crtc->config.pch_pfit.force_thru = true; |
| 2887 | |
| 2888 | intel_display_power_get(dev_priv, |
| 2889 | POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); |
| 2890 | |
| 2891 | dev_priv->display.crtc_disable(&crtc->base); |
| 2892 | dev_priv->display.crtc_enable(&crtc->base); |
| 2893 | } |
| 2894 | drm_modeset_unlock_all(dev); |
| 2895 | } |
| 2896 | |
| 2897 | static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev) |
| 2898 | { |
| 2899 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2900 | struct intel_crtc *crtc = |
| 2901 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); |
| 2902 | |
| 2903 | drm_modeset_lock_all(dev); |
| 2904 | /* |
| 2905 | * If we use the eDP transcoder we need to make sure that we don't |
| 2906 | * bypass the pfit, since otherwise the pipe CRC source won't work. Only |
| 2907 | * relevant on hsw with pipe A when using the always-on power well |
| 2908 | * routing. |
| 2909 | */ |
| 2910 | if (crtc->config.pch_pfit.force_thru) { |
| 2911 | crtc->config.pch_pfit.force_thru = false; |
| 2912 | |
| 2913 | dev_priv->display.crtc_disable(&crtc->base); |
| 2914 | dev_priv->display.crtc_enable(&crtc->base); |
| 2915 | |
| 2916 | intel_display_power_put(dev_priv, |
| 2917 | POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); |
| 2918 | } |
| 2919 | drm_modeset_unlock_all(dev); |
| 2920 | } |
| 2921 | |
| 2922 | static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, |
| 2923 | enum pipe pipe, |
| 2924 | enum intel_pipe_crc_source *source, |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2925 | uint32_t *val) |
| 2926 | { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2927 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
| 2928 | *source = INTEL_PIPE_CRC_SOURCE_PF; |
| 2929 | |
| 2930 | switch (*source) { |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2931 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
| 2932 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; |
| 2933 | break; |
| 2934 | case INTEL_PIPE_CRC_SOURCE_PLANE2: |
| 2935 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; |
| 2936 | break; |
| 2937 | case INTEL_PIPE_CRC_SOURCE_PF: |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 2938 | if (IS_HASWELL(dev) && pipe == PIPE_A) |
| 2939 | hsw_trans_edp_pipe_A_crc_wa(dev); |
| 2940 | |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2941 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
| 2942 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 2943 | case INTEL_PIPE_CRC_SOURCE_NONE: |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2944 | *val = 0; |
| 2945 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 2946 | default: |
| 2947 | return -EINVAL; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2948 | } |
| 2949 | |
| 2950 | return 0; |
| 2951 | } |
| 2952 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2953 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
| 2954 | enum intel_pipe_crc_source source) |
| 2955 | { |
| 2956 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | cc3da17 | 2013-10-15 18:55:31 +0100 | [diff] [blame] | 2957 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
Borislav Petkov | 432f334 | 2013-11-21 16:49:46 +0100 | [diff] [blame] | 2958 | u32 val = 0; /* shut up gcc */ |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2959 | int ret; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2960 | |
Damien Lespiau | cc3da17 | 2013-10-15 18:55:31 +0100 | [diff] [blame] | 2961 | if (pipe_crc->source == source) |
| 2962 | return 0; |
| 2963 | |
Damien Lespiau | ae676fc | 2013-10-15 18:55:32 +0100 | [diff] [blame] | 2964 | /* forbid changing the source without going back to 'none' */ |
| 2965 | if (pipe_crc->source && source) |
| 2966 | return -EINVAL; |
| 2967 | |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 2968 | if (IS_GEN2(dev)) |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2969 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 2970 | else if (INTEL_INFO(dev)->gen < 5) |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2971 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 2972 | else if (IS_VALLEYVIEW(dev)) |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 2973 | ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 2974 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2975 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2976 | else |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 2977 | ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2978 | |
| 2979 | if (ret != 0) |
| 2980 | return ret; |
| 2981 | |
Damien Lespiau | 4b58436 | 2013-10-15 18:55:33 +0100 | [diff] [blame] | 2982 | /* none -> real source transition */ |
| 2983 | if (source) { |
Damien Lespiau | 7cd6ccf | 2013-10-15 18:55:38 +0100 | [diff] [blame] | 2984 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
| 2985 | pipe_name(pipe), pipe_crc_source_name(source)); |
| 2986 | |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 2987 | pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) * |
| 2988 | INTEL_PIPE_CRC_ENTRIES_NR, |
| 2989 | GFP_KERNEL); |
| 2990 | if (!pipe_crc->entries) |
| 2991 | return -ENOMEM; |
| 2992 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2993 | spin_lock_irq(&pipe_crc->lock); |
| 2994 | pipe_crc->head = 0; |
| 2995 | pipe_crc->tail = 0; |
| 2996 | spin_unlock_irq(&pipe_crc->lock); |
Damien Lespiau | 4b58436 | 2013-10-15 18:55:33 +0100 | [diff] [blame] | 2997 | } |
| 2998 | |
Damien Lespiau | cc3da17 | 2013-10-15 18:55:31 +0100 | [diff] [blame] | 2999 | pipe_crc->source = source; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3000 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3001 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
| 3002 | POSTING_READ(PIPE_CRC_CTL(pipe)); |
| 3003 | |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 3004 | /* real source -> none transition */ |
| 3005 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3006 | struct intel_pipe_crc_entry *entries; |
Daniel Vetter | a33d710 | 2014-06-06 08:22:08 +0200 | [diff] [blame] | 3007 | struct intel_crtc *crtc = |
| 3008 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3009 | |
Damien Lespiau | 7cd6ccf | 2013-10-15 18:55:38 +0100 | [diff] [blame] | 3010 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
| 3011 | pipe_name(pipe)); |
| 3012 | |
Daniel Vetter | a33d710 | 2014-06-06 08:22:08 +0200 | [diff] [blame] | 3013 | drm_modeset_lock(&crtc->base.mutex, NULL); |
| 3014 | if (crtc->active) |
| 3015 | intel_wait_for_vblank(dev, pipe); |
| 3016 | drm_modeset_unlock(&crtc->base.mutex); |
Daniel Vetter | bcf17ab | 2013-10-16 22:55:50 +0200 | [diff] [blame] | 3017 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3018 | spin_lock_irq(&pipe_crc->lock); |
| 3019 | entries = pipe_crc->entries; |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 3020 | pipe_crc->entries = NULL; |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3021 | spin_unlock_irq(&pipe_crc->lock); |
| 3022 | |
| 3023 | kfree(entries); |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3024 | |
| 3025 | if (IS_G4X(dev)) |
| 3026 | g4x_undo_pipe_scramble_reset(dev, pipe); |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3027 | else if (IS_VALLEYVIEW(dev)) |
| 3028 | vlv_undo_pipe_scramble_reset(dev, pipe); |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3029 | else if (IS_HASWELL(dev) && pipe == PIPE_A) |
| 3030 | hsw_undo_trans_edp_pipe_A_crc_wa(dev); |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 3031 | } |
| 3032 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3033 | return 0; |
| 3034 | } |
| 3035 | |
| 3036 | /* |
| 3037 | * Parse pipe CRC command strings: |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3038 | * command: wsp* object wsp+ name wsp+ source wsp* |
| 3039 | * object: 'pipe' |
| 3040 | * name: (A | B | C) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3041 | * source: (none | plane1 | plane2 | pf) |
| 3042 | * wsp: (#0x20 | #0x9 | #0xA)+ |
| 3043 | * |
| 3044 | * eg.: |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3045 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
| 3046 | * "pipe A none" -> Stop CRC |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3047 | */ |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3048 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3049 | { |
| 3050 | int n_words = 0; |
| 3051 | |
| 3052 | while (*buf) { |
| 3053 | char *end; |
| 3054 | |
| 3055 | /* skip leading white space */ |
| 3056 | buf = skip_spaces(buf); |
| 3057 | if (!*buf) |
| 3058 | break; /* end of buffer */ |
| 3059 | |
| 3060 | /* find end of word */ |
| 3061 | for (end = buf; *end && !isspace(*end); end++) |
| 3062 | ; |
| 3063 | |
| 3064 | if (n_words == max_words) { |
| 3065 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", |
| 3066 | max_words); |
| 3067 | return -EINVAL; /* ran out of words[] before bytes */ |
| 3068 | } |
| 3069 | |
| 3070 | if (*end) |
| 3071 | *end++ = '\0'; |
| 3072 | words[n_words++] = buf; |
| 3073 | buf = end; |
| 3074 | } |
| 3075 | |
| 3076 | return n_words; |
| 3077 | } |
| 3078 | |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3079 | enum intel_pipe_crc_object { |
| 3080 | PIPE_CRC_OBJECT_PIPE, |
| 3081 | }; |
| 3082 | |
Daniel Vetter | e8dfcf7 | 2013-10-16 11:51:54 +0200 | [diff] [blame] | 3083 | static const char * const pipe_crc_objects[] = { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3084 | "pipe", |
| 3085 | }; |
| 3086 | |
| 3087 | static int |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3088 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3089 | { |
| 3090 | int i; |
| 3091 | |
| 3092 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) |
| 3093 | if (!strcmp(buf, pipe_crc_objects[i])) { |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3094 | *o = i; |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3095 | return 0; |
| 3096 | } |
| 3097 | |
| 3098 | return -EINVAL; |
| 3099 | } |
| 3100 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3101 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3102 | { |
| 3103 | const char name = buf[0]; |
| 3104 | |
| 3105 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) |
| 3106 | return -EINVAL; |
| 3107 | |
| 3108 | *pipe = name - 'A'; |
| 3109 | |
| 3110 | return 0; |
| 3111 | } |
| 3112 | |
| 3113 | static int |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3114 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3115 | { |
| 3116 | int i; |
| 3117 | |
| 3118 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) |
| 3119 | if (!strcmp(buf, pipe_crc_sources[i])) { |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3120 | *s = i; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3121 | return 0; |
| 3122 | } |
| 3123 | |
| 3124 | return -EINVAL; |
| 3125 | } |
| 3126 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3127 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3128 | { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3129 | #define N_WORDS 3 |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3130 | int n_words; |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3131 | char *words[N_WORDS]; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3132 | enum pipe pipe; |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3133 | enum intel_pipe_crc_object object; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3134 | enum intel_pipe_crc_source source; |
| 3135 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3136 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3137 | if (n_words != N_WORDS) { |
| 3138 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", |
| 3139 | N_WORDS); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3140 | return -EINVAL; |
| 3141 | } |
| 3142 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3143 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3144 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3145 | return -EINVAL; |
| 3146 | } |
| 3147 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3148 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3149 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
| 3150 | return -EINVAL; |
| 3151 | } |
| 3152 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3153 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3154 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3155 | return -EINVAL; |
| 3156 | } |
| 3157 | |
| 3158 | return pipe_crc_set_source(dev, pipe, source); |
| 3159 | } |
| 3160 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3161 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
| 3162 | size_t len, loff_t *offp) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3163 | { |
| 3164 | struct seq_file *m = file->private_data; |
| 3165 | struct drm_device *dev = m->private; |
| 3166 | char *tmpbuf; |
| 3167 | int ret; |
| 3168 | |
| 3169 | if (len == 0) |
| 3170 | return 0; |
| 3171 | |
| 3172 | if (len > PAGE_SIZE - 1) { |
| 3173 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", |
| 3174 | PAGE_SIZE); |
| 3175 | return -E2BIG; |
| 3176 | } |
| 3177 | |
| 3178 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); |
| 3179 | if (!tmpbuf) |
| 3180 | return -ENOMEM; |
| 3181 | |
| 3182 | if (copy_from_user(tmpbuf, ubuf, len)) { |
| 3183 | ret = -EFAULT; |
| 3184 | goto out; |
| 3185 | } |
| 3186 | tmpbuf[len] = '\0'; |
| 3187 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3188 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3189 | |
| 3190 | out: |
| 3191 | kfree(tmpbuf); |
| 3192 | if (ret < 0) |
| 3193 | return ret; |
| 3194 | |
| 3195 | *offp += len; |
| 3196 | return len; |
| 3197 | } |
| 3198 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3199 | static const struct file_operations i915_display_crc_ctl_fops = { |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3200 | .owner = THIS_MODULE, |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3201 | .open = display_crc_ctl_open, |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3202 | .read = seq_read, |
| 3203 | .llseek = seq_lseek, |
| 3204 | .release = single_release, |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3205 | .write = display_crc_ctl_write |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3206 | }; |
| 3207 | |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3208 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[5]) |
| 3209 | { |
| 3210 | struct drm_device *dev = m->private; |
Damien Lespiau | 546c81f | 2014-05-13 15:30:26 +0100 | [diff] [blame] | 3211 | int num_levels = ilk_wm_max_level(dev) + 1; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3212 | int level; |
| 3213 | |
| 3214 | drm_modeset_lock_all(dev); |
| 3215 | |
| 3216 | for (level = 0; level < num_levels; level++) { |
| 3217 | unsigned int latency = wm[level]; |
| 3218 | |
| 3219 | /* WM1+ latency values in 0.5us units */ |
| 3220 | if (level > 0) |
| 3221 | latency *= 5; |
| 3222 | |
| 3223 | seq_printf(m, "WM%d %u (%u.%u usec)\n", |
| 3224 | level, wm[level], |
| 3225 | latency / 10, latency % 10); |
| 3226 | } |
| 3227 | |
| 3228 | drm_modeset_unlock_all(dev); |
| 3229 | } |
| 3230 | |
| 3231 | static int pri_wm_latency_show(struct seq_file *m, void *data) |
| 3232 | { |
| 3233 | struct drm_device *dev = m->private; |
| 3234 | |
| 3235 | wm_latency_show(m, to_i915(dev)->wm.pri_latency); |
| 3236 | |
| 3237 | return 0; |
| 3238 | } |
| 3239 | |
| 3240 | static int spr_wm_latency_show(struct seq_file *m, void *data) |
| 3241 | { |
| 3242 | struct drm_device *dev = m->private; |
| 3243 | |
| 3244 | wm_latency_show(m, to_i915(dev)->wm.spr_latency); |
| 3245 | |
| 3246 | return 0; |
| 3247 | } |
| 3248 | |
| 3249 | static int cur_wm_latency_show(struct seq_file *m, void *data) |
| 3250 | { |
| 3251 | struct drm_device *dev = m->private; |
| 3252 | |
| 3253 | wm_latency_show(m, to_i915(dev)->wm.cur_latency); |
| 3254 | |
| 3255 | return 0; |
| 3256 | } |
| 3257 | |
| 3258 | static int pri_wm_latency_open(struct inode *inode, struct file *file) |
| 3259 | { |
| 3260 | struct drm_device *dev = inode->i_private; |
| 3261 | |
| 3262 | if (!HAS_PCH_SPLIT(dev)) |
| 3263 | return -ENODEV; |
| 3264 | |
| 3265 | return single_open(file, pri_wm_latency_show, dev); |
| 3266 | } |
| 3267 | |
| 3268 | static int spr_wm_latency_open(struct inode *inode, struct file *file) |
| 3269 | { |
| 3270 | struct drm_device *dev = inode->i_private; |
| 3271 | |
| 3272 | if (!HAS_PCH_SPLIT(dev)) |
| 3273 | return -ENODEV; |
| 3274 | |
| 3275 | return single_open(file, spr_wm_latency_show, dev); |
| 3276 | } |
| 3277 | |
| 3278 | static int cur_wm_latency_open(struct inode *inode, struct file *file) |
| 3279 | { |
| 3280 | struct drm_device *dev = inode->i_private; |
| 3281 | |
| 3282 | if (!HAS_PCH_SPLIT(dev)) |
| 3283 | return -ENODEV; |
| 3284 | |
| 3285 | return single_open(file, cur_wm_latency_show, dev); |
| 3286 | } |
| 3287 | |
| 3288 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, |
| 3289 | size_t len, loff_t *offp, uint16_t wm[5]) |
| 3290 | { |
| 3291 | struct seq_file *m = file->private_data; |
| 3292 | struct drm_device *dev = m->private; |
| 3293 | uint16_t new[5] = { 0 }; |
Damien Lespiau | 546c81f | 2014-05-13 15:30:26 +0100 | [diff] [blame] | 3294 | int num_levels = ilk_wm_max_level(dev) + 1; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3295 | int level; |
| 3296 | int ret; |
| 3297 | char tmp[32]; |
| 3298 | |
| 3299 | if (len >= sizeof(tmp)) |
| 3300 | return -EINVAL; |
| 3301 | |
| 3302 | if (copy_from_user(tmp, ubuf, len)) |
| 3303 | return -EFAULT; |
| 3304 | |
| 3305 | tmp[len] = '\0'; |
| 3306 | |
| 3307 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]); |
| 3308 | if (ret != num_levels) |
| 3309 | return -EINVAL; |
| 3310 | |
| 3311 | drm_modeset_lock_all(dev); |
| 3312 | |
| 3313 | for (level = 0; level < num_levels; level++) |
| 3314 | wm[level] = new[level]; |
| 3315 | |
| 3316 | drm_modeset_unlock_all(dev); |
| 3317 | |
| 3318 | return len; |
| 3319 | } |
| 3320 | |
| 3321 | |
| 3322 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, |
| 3323 | size_t len, loff_t *offp) |
| 3324 | { |
| 3325 | struct seq_file *m = file->private_data; |
| 3326 | struct drm_device *dev = m->private; |
| 3327 | |
| 3328 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency); |
| 3329 | } |
| 3330 | |
| 3331 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, |
| 3332 | size_t len, loff_t *offp) |
| 3333 | { |
| 3334 | struct seq_file *m = file->private_data; |
| 3335 | struct drm_device *dev = m->private; |
| 3336 | |
| 3337 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency); |
| 3338 | } |
| 3339 | |
| 3340 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, |
| 3341 | size_t len, loff_t *offp) |
| 3342 | { |
| 3343 | struct seq_file *m = file->private_data; |
| 3344 | struct drm_device *dev = m->private; |
| 3345 | |
| 3346 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency); |
| 3347 | } |
| 3348 | |
| 3349 | static const struct file_operations i915_pri_wm_latency_fops = { |
| 3350 | .owner = THIS_MODULE, |
| 3351 | .open = pri_wm_latency_open, |
| 3352 | .read = seq_read, |
| 3353 | .llseek = seq_lseek, |
| 3354 | .release = single_release, |
| 3355 | .write = pri_wm_latency_write |
| 3356 | }; |
| 3357 | |
| 3358 | static const struct file_operations i915_spr_wm_latency_fops = { |
| 3359 | .owner = THIS_MODULE, |
| 3360 | .open = spr_wm_latency_open, |
| 3361 | .read = seq_read, |
| 3362 | .llseek = seq_lseek, |
| 3363 | .release = single_release, |
| 3364 | .write = spr_wm_latency_write |
| 3365 | }; |
| 3366 | |
| 3367 | static const struct file_operations i915_cur_wm_latency_fops = { |
| 3368 | .owner = THIS_MODULE, |
| 3369 | .open = cur_wm_latency_open, |
| 3370 | .read = seq_read, |
| 3371 | .llseek = seq_lseek, |
| 3372 | .release = single_release, |
| 3373 | .write = cur_wm_latency_write |
| 3374 | }; |
| 3375 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3376 | static int |
| 3377 | i915_wedged_get(void *data, u64 *val) |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3378 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3379 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 3380 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3381 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3382 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3383 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3384 | return 0; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3385 | } |
| 3386 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3387 | static int |
| 3388 | i915_wedged_set(void *data, u64 val) |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3389 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3390 | struct drm_device *dev = data; |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 3391 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3392 | |
| 3393 | intel_runtime_pm_get(dev_priv); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3394 | |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 3395 | i915_handle_error(dev, val, |
| 3396 | "Manually setting wedged to %llu", val); |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 3397 | |
| 3398 | intel_runtime_pm_put(dev_priv); |
| 3399 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3400 | return 0; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3401 | } |
| 3402 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3403 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
| 3404 | i915_wedged_get, i915_wedged_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 3405 | "%llu\n"); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3406 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3407 | static int |
| 3408 | i915_ring_stop_get(void *data, u64 *val) |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3409 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3410 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 3411 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3412 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3413 | *val = dev_priv->gpu_error.stop_rings; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3414 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3415 | return 0; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3416 | } |
| 3417 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3418 | static int |
| 3419 | i915_ring_stop_set(void *data, u64 val) |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3420 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3421 | struct drm_device *dev = data; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3422 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3423 | int ret; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3424 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3425 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3426 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 3427 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 3428 | if (ret) |
| 3429 | return ret; |
| 3430 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 3431 | dev_priv->gpu_error.stop_rings = val; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3432 | mutex_unlock(&dev->struct_mutex); |
| 3433 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3434 | return 0; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3435 | } |
| 3436 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3437 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
| 3438 | i915_ring_stop_get, i915_ring_stop_set, |
| 3439 | "0x%08llx\n"); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 3440 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 3441 | static int |
| 3442 | i915_ring_missed_irq_get(void *data, u64 *val) |
| 3443 | { |
| 3444 | struct drm_device *dev = data; |
| 3445 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3446 | |
| 3447 | *val = dev_priv->gpu_error.missed_irq_rings; |
| 3448 | return 0; |
| 3449 | } |
| 3450 | |
| 3451 | static int |
| 3452 | i915_ring_missed_irq_set(void *data, u64 val) |
| 3453 | { |
| 3454 | struct drm_device *dev = data; |
| 3455 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3456 | int ret; |
| 3457 | |
| 3458 | /* Lock against concurrent debugfs callers */ |
| 3459 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 3460 | if (ret) |
| 3461 | return ret; |
| 3462 | dev_priv->gpu_error.missed_irq_rings = val; |
| 3463 | mutex_unlock(&dev->struct_mutex); |
| 3464 | |
| 3465 | return 0; |
| 3466 | } |
| 3467 | |
| 3468 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, |
| 3469 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, |
| 3470 | "0x%08llx\n"); |
| 3471 | |
| 3472 | static int |
| 3473 | i915_ring_test_irq_get(void *data, u64 *val) |
| 3474 | { |
| 3475 | struct drm_device *dev = data; |
| 3476 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3477 | |
| 3478 | *val = dev_priv->gpu_error.test_irq_rings; |
| 3479 | |
| 3480 | return 0; |
| 3481 | } |
| 3482 | |
| 3483 | static int |
| 3484 | i915_ring_test_irq_set(void *data, u64 val) |
| 3485 | { |
| 3486 | struct drm_device *dev = data; |
| 3487 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3488 | int ret; |
| 3489 | |
| 3490 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
| 3491 | |
| 3492 | /* Lock against concurrent debugfs callers */ |
| 3493 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 3494 | if (ret) |
| 3495 | return ret; |
| 3496 | |
| 3497 | dev_priv->gpu_error.test_irq_rings = val; |
| 3498 | mutex_unlock(&dev->struct_mutex); |
| 3499 | |
| 3500 | return 0; |
| 3501 | } |
| 3502 | |
| 3503 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, |
| 3504 | i915_ring_test_irq_get, i915_ring_test_irq_set, |
| 3505 | "0x%08llx\n"); |
| 3506 | |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3507 | #define DROP_UNBOUND 0x1 |
| 3508 | #define DROP_BOUND 0x2 |
| 3509 | #define DROP_RETIRE 0x4 |
| 3510 | #define DROP_ACTIVE 0x8 |
| 3511 | #define DROP_ALL (DROP_UNBOUND | \ |
| 3512 | DROP_BOUND | \ |
| 3513 | DROP_RETIRE | \ |
| 3514 | DROP_ACTIVE) |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3515 | static int |
| 3516 | i915_drop_caches_get(void *data, u64 *val) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3517 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3518 | *val = DROP_ALL; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3519 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3520 | return 0; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3521 | } |
| 3522 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3523 | static int |
| 3524 | i915_drop_caches_set(void *data, u64 val) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3525 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3526 | struct drm_device *dev = data; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3527 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3528 | struct drm_i915_gem_object *obj, *next; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 3529 | struct i915_address_space *vm; |
| 3530 | struct i915_vma *vma, *x; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3531 | int ret; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3532 | |
Ben Widawsky | 2f9fe5f | 2013-11-25 09:54:37 -0800 | [diff] [blame] | 3533 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3534 | |
| 3535 | /* No need to check and wait for gpu resets, only libdrm auto-restarts |
| 3536 | * on ioctls on -EAGAIN. */ |
| 3537 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 3538 | if (ret) |
| 3539 | return ret; |
| 3540 | |
| 3541 | if (val & DROP_ACTIVE) { |
| 3542 | ret = i915_gpu_idle(dev); |
| 3543 | if (ret) |
| 3544 | goto unlock; |
| 3545 | } |
| 3546 | |
| 3547 | if (val & (DROP_RETIRE | DROP_ACTIVE)) |
| 3548 | i915_gem_retire_requests(dev); |
| 3549 | |
| 3550 | if (val & DROP_BOUND) { |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 3551 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
| 3552 | list_for_each_entry_safe(vma, x, &vm->inactive_list, |
| 3553 | mm_list) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3554 | if (vma->pin_count) |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 3555 | continue; |
Ben Widawsky | 31a46c9 | 2013-07-31 16:59:55 -0700 | [diff] [blame] | 3556 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 3557 | ret = i915_vma_unbind(vma); |
| 3558 | if (ret) |
| 3559 | goto unlock; |
| 3560 | } |
Ben Widawsky | 31a46c9 | 2013-07-31 16:59:55 -0700 | [diff] [blame] | 3561 | } |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3562 | } |
| 3563 | |
| 3564 | if (val & DROP_UNBOUND) { |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 3565 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
| 3566 | global_list) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3567 | if (obj->pages_pin_count == 0) { |
| 3568 | ret = i915_gem_object_put_pages(obj); |
| 3569 | if (ret) |
| 3570 | goto unlock; |
| 3571 | } |
| 3572 | } |
| 3573 | |
| 3574 | unlock: |
| 3575 | mutex_unlock(&dev->struct_mutex); |
| 3576 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3577 | return ret; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3578 | } |
| 3579 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3580 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
| 3581 | i915_drop_caches_get, i915_drop_caches_set, |
| 3582 | "0x%08llx\n"); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3583 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3584 | static int |
| 3585 | i915_max_freq_get(void *data, u64 *val) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3586 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3587 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 3588 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3589 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3590 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 3591 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3592 | return -ENODEV; |
| 3593 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 3594 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 3595 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3596 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3597 | if (ret) |
| 3598 | return ret; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3599 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3600 | if (IS_VALLEYVIEW(dev)) |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3601 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3602 | else |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3603 | *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3604 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3605 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3606 | return 0; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3607 | } |
| 3608 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3609 | static int |
| 3610 | i915_max_freq_set(void *data, u64 val) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3611 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3612 | struct drm_device *dev = data; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3613 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3614 | u32 rp_state_cap, hw_max, hw_min; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3615 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3616 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 3617 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3618 | return -ENODEV; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3619 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 3620 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 3621 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3622 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3623 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3624 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3625 | if (ret) |
| 3626 | return ret; |
| 3627 | |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3628 | /* |
| 3629 | * Turbo will still be enabled, but won't go above the set value. |
| 3630 | */ |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3631 | if (IS_VALLEYVIEW(dev)) { |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 3632 | val = vlv_freq_opcode(dev_priv, val); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3633 | |
| 3634 | hw_max = valleyview_rps_max_freq(dev_priv); |
| 3635 | hw_min = valleyview_rps_min_freq(dev_priv); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3636 | } else { |
| 3637 | do_div(val, GT_FREQUENCY_MULTIPLIER); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3638 | |
| 3639 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3640 | hw_max = dev_priv->rps.max_freq; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3641 | hw_min = (rp_state_cap >> 16) & 0xff; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3642 | } |
| 3643 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3644 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3645 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 3646 | return -EINVAL; |
| 3647 | } |
| 3648 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3649 | dev_priv->rps.max_freq_softlimit = val; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3650 | |
| 3651 | if (IS_VALLEYVIEW(dev)) |
| 3652 | valleyview_set_rps(dev, val); |
| 3653 | else |
| 3654 | gen6_set_rps(dev, val); |
| 3655 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3656 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3657 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3658 | return 0; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3659 | } |
| 3660 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3661 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
| 3662 | i915_max_freq_get, i915_max_freq_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 3663 | "%llu\n"); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3664 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3665 | static int |
| 3666 | i915_min_freq_get(void *data, u64 *val) |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3667 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3668 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 3669 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3670 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3671 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 3672 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3673 | return -ENODEV; |
| 3674 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 3675 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 3676 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3677 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3678 | if (ret) |
| 3679 | return ret; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3680 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3681 | if (IS_VALLEYVIEW(dev)) |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3682 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3683 | else |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3684 | *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3685 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3686 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3687 | return 0; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3688 | } |
| 3689 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3690 | static int |
| 3691 | i915_min_freq_set(void *data, u64 val) |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3692 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3693 | struct drm_device *dev = data; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3694 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3695 | u32 rp_state_cap, hw_max, hw_min; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3696 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3697 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 3698 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3699 | return -ENODEV; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3700 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 3701 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 3702 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3703 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3704 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3705 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3706 | if (ret) |
| 3707 | return ret; |
| 3708 | |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3709 | /* |
| 3710 | * Turbo will still be enabled, but won't go below the set value. |
| 3711 | */ |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3712 | if (IS_VALLEYVIEW(dev)) { |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 3713 | val = vlv_freq_opcode(dev_priv, val); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3714 | |
| 3715 | hw_max = valleyview_rps_max_freq(dev_priv); |
| 3716 | hw_min = valleyview_rps_min_freq(dev_priv); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3717 | } else { |
| 3718 | do_div(val, GT_FREQUENCY_MULTIPLIER); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3719 | |
| 3720 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3721 | hw_max = dev_priv->rps.max_freq; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3722 | hw_min = (rp_state_cap >> 16) & 0xff; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3723 | } |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3724 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3725 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3726 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 3727 | return -EINVAL; |
| 3728 | } |
| 3729 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3730 | dev_priv->rps.min_freq_softlimit = val; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3731 | |
| 3732 | if (IS_VALLEYVIEW(dev)) |
| 3733 | valleyview_set_rps(dev, val); |
| 3734 | else |
| 3735 | gen6_set_rps(dev, val); |
| 3736 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3737 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3738 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3739 | return 0; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3740 | } |
| 3741 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3742 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
| 3743 | i915_min_freq_get, i915_min_freq_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 3744 | "%llu\n"); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3745 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3746 | static int |
| 3747 | i915_cache_sharing_get(void *data, u64 *val) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 3748 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3749 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 3750 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 3751 | u32 snpcr; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3752 | int ret; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 3753 | |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3754 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 3755 | return -ENODEV; |
| 3756 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 3757 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 3758 | if (ret) |
| 3759 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 3760 | intel_runtime_pm_get(dev_priv); |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 3761 | |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 3762 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 3763 | |
| 3764 | intel_runtime_pm_put(dev_priv); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 3765 | mutex_unlock(&dev_priv->dev->struct_mutex); |
| 3766 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3767 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 3768 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3769 | return 0; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 3770 | } |
| 3771 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3772 | static int |
| 3773 | i915_cache_sharing_set(void *data, u64 val) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 3774 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3775 | struct drm_device *dev = data; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 3776 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 3777 | u32 snpcr; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 3778 | |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3779 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 3780 | return -ENODEV; |
| 3781 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3782 | if (val > 3) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 3783 | return -EINVAL; |
| 3784 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 3785 | intel_runtime_pm_get(dev_priv); |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3786 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 3787 | |
| 3788 | /* Update the cache sharing policy here as well */ |
| 3789 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
| 3790 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
| 3791 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); |
| 3792 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
| 3793 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 3794 | intel_runtime_pm_put(dev_priv); |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3795 | return 0; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 3796 | } |
| 3797 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3798 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
| 3799 | i915_cache_sharing_get, i915_cache_sharing_set, |
| 3800 | "%llu\n"); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 3801 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 3802 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
| 3803 | { |
| 3804 | struct drm_device *dev = inode->i_private; |
| 3805 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 3806 | |
Daniel Vetter | 075edca | 2012-01-24 09:44:28 +0100 | [diff] [blame] | 3807 | if (INTEL_INFO(dev)->gen < 6) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 3808 | return 0; |
| 3809 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 3810 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 3811 | |
| 3812 | return 0; |
| 3813 | } |
| 3814 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 3815 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 3816 | { |
| 3817 | struct drm_device *dev = inode->i_private; |
| 3818 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3819 | |
Daniel Vetter | 075edca | 2012-01-24 09:44:28 +0100 | [diff] [blame] | 3820 | if (INTEL_INFO(dev)->gen < 6) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 3821 | return 0; |
| 3822 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 3823 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 3824 | |
| 3825 | return 0; |
| 3826 | } |
| 3827 | |
| 3828 | static const struct file_operations i915_forcewake_fops = { |
| 3829 | .owner = THIS_MODULE, |
| 3830 | .open = i915_forcewake_open, |
| 3831 | .release = i915_forcewake_release, |
| 3832 | }; |
| 3833 | |
| 3834 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) |
| 3835 | { |
| 3836 | struct drm_device *dev = minor->dev; |
| 3837 | struct dentry *ent; |
| 3838 | |
| 3839 | ent = debugfs_create_file("i915_forcewake_user", |
Ben Widawsky | 8eb5729 | 2011-05-11 15:10:58 -0700 | [diff] [blame] | 3840 | S_IRUSR, |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 3841 | root, dev, |
| 3842 | &i915_forcewake_fops); |
Wei Yongjun | f3c5fe9 | 2013-12-16 14:13:25 +0800 | [diff] [blame] | 3843 | if (!ent) |
| 3844 | return -ENOMEM; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 3845 | |
Ben Widawsky | 8eb5729 | 2011-05-11 15:10:58 -0700 | [diff] [blame] | 3846 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 3847 | } |
| 3848 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 3849 | static int i915_debugfs_create(struct dentry *root, |
| 3850 | struct drm_minor *minor, |
| 3851 | const char *name, |
| 3852 | const struct file_operations *fops) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3853 | { |
| 3854 | struct drm_device *dev = minor->dev; |
| 3855 | struct dentry *ent; |
| 3856 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 3857 | ent = debugfs_create_file(name, |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3858 | S_IRUGO | S_IWUSR, |
| 3859 | root, dev, |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 3860 | fops); |
Wei Yongjun | f3c5fe9 | 2013-12-16 14:13:25 +0800 | [diff] [blame] | 3861 | if (!ent) |
| 3862 | return -ENOMEM; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3863 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 3864 | return drm_add_fake_info_node(minor, ent, fops); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 3865 | } |
| 3866 | |
Lespiau, Damien | 06c5bf8 | 2013-10-17 19:09:56 +0100 | [diff] [blame] | 3867 | static const struct drm_info_list i915_debugfs_list[] = { |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 3868 | {"i915_capabilities", i915_capabilities, 0}, |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3869 | {"i915_gem_objects", i915_gem_object_info, 0}, |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 3870 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 3871 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 3872 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 3873 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 3874 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 3875 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 3876 | {"i915_gem_request", i915_gem_request_info, 0}, |
| 3877 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 3878 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 3879 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3880 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
| 3881 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, |
| 3882 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, |
Xiang, Haihao | 9010ebf | 2013-05-29 09:22:36 -0700 | [diff] [blame] | 3883 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
Deepak S | adb4bd1 | 2014-03-31 11:30:02 +0530 | [diff] [blame] | 3884 | {"i915_frequency_info", i915_frequency_info, 0}, |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 3885 | {"i915_drpc_info", i915_drpc_info, 0}, |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 3886 | {"i915_emon_status", i915_emon_status, 0}, |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 3887 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 3888 | {"i915_fbc_status", i915_fbc_status, 0}, |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 3889 | {"i915_ips_status", i915_ips_status, 0}, |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 3890 | {"i915_sr_status", i915_sr_status, 0}, |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 3891 | {"i915_opregion", i915_opregion, 0}, |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 3892 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 3893 | {"i915_context_status", i915_context_status, 0}, |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 3894 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 3895 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 3896 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 3897 | {"i915_llc", i915_llc, 0}, |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 3898 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3899 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 3900 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 3901 | {"i915_pc8_status", i915_pc8_status, 0}, |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 3902 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 3903 | {"i915_display_info", i915_display_info, 0}, |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 3904 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
Daniel Vetter | 728e29d | 2014-06-25 22:01:53 +0300 | [diff] [blame] | 3905 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 3906 | }; |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 3907 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 3908 | |
Lespiau, Damien | 06c5bf8 | 2013-10-17 19:09:56 +0100 | [diff] [blame] | 3909 | static const struct i915_debugfs_files { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 3910 | const char *name; |
| 3911 | const struct file_operations *fops; |
| 3912 | } i915_debugfs_files[] = { |
| 3913 | {"i915_wedged", &i915_wedged_fops}, |
| 3914 | {"i915_max_freq", &i915_max_freq_fops}, |
| 3915 | {"i915_min_freq", &i915_min_freq_fops}, |
| 3916 | {"i915_cache_sharing", &i915_cache_sharing_fops}, |
| 3917 | {"i915_ring_stop", &i915_ring_stop_fops}, |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 3918 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
| 3919 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 3920 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
| 3921 | {"i915_error_state", &i915_error_state_fops}, |
| 3922 | {"i915_next_seqno", &i915_next_seqno_fops}, |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3923 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3924 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
| 3925 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, |
| 3926 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 3927 | }; |
| 3928 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3929 | void intel_display_crc_init(struct drm_device *dev) |
| 3930 | { |
| 3931 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | b378360 | 2013-11-14 11:30:42 +0100 | [diff] [blame] | 3932 | enum pipe pipe; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3933 | |
Daniel Vetter | b378360 | 2013-11-14 11:30:42 +0100 | [diff] [blame] | 3934 | for_each_pipe(pipe) { |
| 3935 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3936 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3937 | pipe_crc->opened = false; |
| 3938 | spin_lock_init(&pipe_crc->lock); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3939 | init_waitqueue_head(&pipe_crc->wq); |
| 3940 | } |
| 3941 | } |
| 3942 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 3943 | int i915_debugfs_init(struct drm_minor *minor) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 3944 | { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 3945 | int ret, i; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3946 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 3947 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
| 3948 | if (ret) |
| 3949 | return ret; |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 3950 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3951 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
| 3952 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); |
| 3953 | if (ret) |
| 3954 | return ret; |
| 3955 | } |
| 3956 | |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 3957 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
| 3958 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
| 3959 | i915_debugfs_files[i].name, |
| 3960 | i915_debugfs_files[i].fops); |
| 3961 | if (ret) |
| 3962 | return ret; |
| 3963 | } |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 3964 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 3965 | return drm_debugfs_create_files(i915_debugfs_list, |
| 3966 | I915_DEBUGFS_ENTRIES, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 3967 | minor->debugfs_root, minor); |
| 3968 | } |
| 3969 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 3970 | void i915_debugfs_cleanup(struct drm_minor *minor) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 3971 | { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 3972 | int i; |
| 3973 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 3974 | drm_debugfs_remove_files(i915_debugfs_list, |
| 3975 | I915_DEBUGFS_ENTRIES, minor); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3976 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 3977 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
| 3978 | 1, minor); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3979 | |
Daniel Vetter | e309a99 | 2013-10-16 22:55:51 +0200 | [diff] [blame] | 3980 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3981 | struct drm_info_list *info_list = |
| 3982 | (struct drm_info_list *)&i915_pipe_crc_data[i]; |
| 3983 | |
| 3984 | drm_debugfs_remove_files(info_list, 1, minor); |
| 3985 | } |
| 3986 | |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 3987 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
| 3988 | struct drm_info_list *info_list = |
| 3989 | (struct drm_info_list *) i915_debugfs_files[i].fops; |
| 3990 | |
| 3991 | drm_debugfs_remove_files(info_list, 1, minor); |
| 3992 | } |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 3993 | } |