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Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Jiri Pirko22a67762017-02-03 10:29:07 +01003 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +020056#include <linux/netlink.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020057#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020058#include <net/pkt_cls.h>
59#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020060#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010061#include <net/tc_act/tc_sample.h>
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +020062#include <net/addrconf.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020063
64#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020065#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020066#include "core.h"
67#include "reg.h"
68#include "port.h"
69#include "trap.h"
70#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010071#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020072#include "spectrum_dpipe.h"
Yotam Gigid3b939b2017-09-19 10:00:09 +020073#include "spectrum_acl_flex_actions.h"
Petr Machataa629ef22018-02-13 11:27:48 +010074#include "spectrum_span.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020075#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020076
Yotam Gigi6b742192017-05-23 21:56:29 +020077#define MLXSW_FWREV_MAJOR 13
Shalom Toledo2f53fbd2017-11-12 09:01:24 +010078#define MLXSW_FWREV_MINOR 1530
79#define MLXSW_FWREV_SUBMINOR 152
Yuval Mintzfd5204c2018-01-18 12:55:23 +010080#define MLXSW_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
Yotam Gigi6b742192017-05-23 21:56:29 +020081
82#define MLXSW_SP_FW_FILENAME \
Yotam Gigia4e1ce22017-06-04 16:49:58 +020083 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
Yotam Gigi6b742192017-05-23 21:56:29 +020084 "." __stringify(MLXSW_FWREV_MINOR) \
85 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
86
Jiri Pirko56ade8f2015-10-16 14:01:37 +020087static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
88static const char mlxsw_sp_driver_version[] = "1.0";
89
90/* tx_hdr_version
91 * Tx header version.
92 * Must be set to 1.
93 */
94MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
95
96/* tx_hdr_ctl
97 * Packet control type.
98 * 0 - Ethernet control (e.g. EMADs, LACP)
99 * 1 - Ethernet data
100 */
101MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
102
103/* tx_hdr_proto
104 * Packet protocol type. Must be set to 1 (Ethernet).
105 */
106MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
107
108/* tx_hdr_rx_is_router
109 * Packet is sent from the router. Valid for data packets only.
110 */
111MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
112
113/* tx_hdr_fid_valid
114 * Indicates if the 'fid' field is valid and should be used for
115 * forwarding lookup. Valid for data packets only.
116 */
117MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
118
119/* tx_hdr_swid
120 * Switch partition ID. Must be set to 0.
121 */
122MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
123
124/* tx_hdr_control_tclass
125 * Indicates if the packet should use the control TClass and not one
126 * of the data TClasses.
127 */
128MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
129
130/* tx_hdr_etclass
131 * Egress TClass to be used on the egress device on the egress port.
132 */
133MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
134
135/* tx_hdr_port_mid
136 * Destination local port for unicast packets.
137 * Destination multicast ID for multicast packets.
138 *
139 * Control packets are directed to a specific egress port, while data
140 * packets are transmitted through the CPU port (0) into the switch partition,
141 * where forwarding rules are applied.
142 */
143MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
144
145/* tx_hdr_fid
146 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
147 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
148 * Valid for data packets only.
149 */
150MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
151
152/* tx_hdr_type
153 * 0 - Data packets
154 * 6 - Control packets
155 */
156MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
157
Yotam Gigie5e5c882017-05-23 21:56:27 +0200158struct mlxsw_sp_mlxfw_dev {
159 struct mlxfw_dev mlxfw_dev;
160 struct mlxsw_sp *mlxsw_sp;
161};
162
163static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
164 u16 component_index, u32 *p_max_size,
165 u8 *p_align_bits, u16 *p_max_write_size)
166{
167 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
168 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
169 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
170 char mcqi_pl[MLXSW_REG_MCQI_LEN];
171 int err;
172
173 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
174 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
175 if (err)
176 return err;
177 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
178 p_max_write_size);
179
180 *p_align_bits = max_t(u8, *p_align_bits, 2);
181 *p_max_write_size = min_t(u16, *p_max_write_size,
182 MLXSW_REG_MCDA_MAX_DATA_LEN);
183 return 0;
184}
185
186static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
187{
188 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
189 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
190 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
191 char mcc_pl[MLXSW_REG_MCC_LEN];
192 u8 control_state;
193 int err;
194
195 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
196 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
197 if (err)
198 return err;
199
200 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
201 if (control_state != MLXFW_FSM_STATE_IDLE)
202 return -EBUSY;
203
204 mlxsw_reg_mcc_pack(mcc_pl,
205 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
206 0, *fwhandle, 0);
207 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
208}
209
210static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
211 u32 fwhandle, u16 component_index,
212 u32 component_size)
213{
214 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
215 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
217 char mcc_pl[MLXSW_REG_MCC_LEN];
218
219 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
220 component_index, fwhandle, component_size);
221 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
222}
223
224static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
225 u32 fwhandle, u8 *data, u16 size,
226 u32 offset)
227{
228 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
229 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
230 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
231 char mcda_pl[MLXSW_REG_MCDA_LEN];
232
233 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
234 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
235}
236
237static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
238 u32 fwhandle, u16 component_index)
239{
240 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
241 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
242 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
243 char mcc_pl[MLXSW_REG_MCC_LEN];
244
245 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
246 component_index, fwhandle, 0);
247 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
248}
249
250static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
251{
252 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
253 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
254 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
255 char mcc_pl[MLXSW_REG_MCC_LEN];
256
257 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
258 fwhandle, 0);
259 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
260}
261
262static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
263 enum mlxfw_fsm_state *fsm_state,
264 enum mlxfw_fsm_state_err *fsm_state_err)
265{
266 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
267 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
268 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
269 char mcc_pl[MLXSW_REG_MCC_LEN];
270 u8 control_state;
271 u8 error_code;
272 int err;
273
274 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
275 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
276 if (err)
277 return err;
278
279 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
280 *fsm_state = control_state;
281 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
282 MLXFW_FSM_STATE_ERR_MAX);
283 return 0;
284}
285
286static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
287{
288 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
289 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
290 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
291 char mcc_pl[MLXSW_REG_MCC_LEN];
292
293 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
294 fwhandle, 0);
295 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
296}
297
298static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
299{
300 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
301 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
302 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
303 char mcc_pl[MLXSW_REG_MCC_LEN];
304
305 mlxsw_reg_mcc_pack(mcc_pl,
306 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
307 fwhandle, 0);
308 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
309}
310
311static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
312 .component_query = mlxsw_sp_component_query,
313 .fsm_lock = mlxsw_sp_fsm_lock,
314 .fsm_component_update = mlxsw_sp_fsm_component_update,
315 .fsm_block_download = mlxsw_sp_fsm_block_download,
316 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
317 .fsm_activate = mlxsw_sp_fsm_activate,
318 .fsm_query_state = mlxsw_sp_fsm_query_state,
319 .fsm_cancel = mlxsw_sp_fsm_cancel,
320 .fsm_release = mlxsw_sp_fsm_release
321};
322
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300323static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
324 const struct firmware *firmware)
325{
326 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
327 .mlxfw_dev = {
328 .ops = &mlxsw_sp_mlxfw_dev_ops,
329 .psid = mlxsw_sp->bus_info->psid,
330 .psid_size = strlen(mlxsw_sp->bus_info->psid),
331 },
332 .mlxsw_sp = mlxsw_sp
333 };
334
335 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
336}
337
Yotam Gigi6b742192017-05-23 21:56:29 +0200338static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
339{
340 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
Yotam Gigi6b742192017-05-23 21:56:29 +0200341 const struct firmware *firmware;
342 int err;
343
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100344 /* Validate driver & FW are compatible */
345 if (rev->major != MLXSW_FWREV_MAJOR) {
346 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
347 rev->major, MLXSW_FWREV_MAJOR);
348 return -EINVAL;
349 }
350 if (MLXSW_FWREV_MINOR_TO_BRANCH(rev->minor) ==
351 MLXSW_FWREV_MINOR_TO_BRANCH(MLXSW_FWREV_MINOR))
Yotam Gigi6b742192017-05-23 21:56:29 +0200352 return 0;
353
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100354 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200355 rev->major, rev->minor, rev->subminor);
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100356 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200357 MLXSW_SP_FW_FILENAME);
358
359 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
360 mlxsw_sp->bus_info->dev);
361 if (err) {
362 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
363 MLXSW_SP_FW_FILENAME);
364 return err;
365 }
366
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300367 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
Yotam Gigi6b742192017-05-23 21:56:29 +0200368 release_firmware(firmware);
369 return err;
370}
371
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100372int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
373 unsigned int counter_index, u64 *packets,
374 u64 *bytes)
375{
376 char mgpc_pl[MLXSW_REG_MGPC_LEN];
377 int err;
378
379 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200380 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100381 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
382 if (err)
383 return err;
Arkadi Sharshevsky7cfcbc72017-08-24 08:40:08 +0200384 if (packets)
385 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
386 if (bytes)
387 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100388 return 0;
389}
390
391static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
392 unsigned int counter_index)
393{
394 char mgpc_pl[MLXSW_REG_MGPC_LEN];
395
396 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200397 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100398 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
399}
400
401int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
402 unsigned int *p_counter_index)
403{
404 int err;
405
406 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
407 p_counter_index);
408 if (err)
409 return err;
410 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
411 if (err)
412 goto err_counter_clear;
413 return 0;
414
415err_counter_clear:
416 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
417 *p_counter_index);
418 return err;
419}
420
421void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
422 unsigned int counter_index)
423{
424 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
425 counter_index);
426}
427
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200428static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
429 const struct mlxsw_tx_info *tx_info)
430{
431 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
432
433 memset(txhdr, 0, MLXSW_TXHDR_LEN);
434
435 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
436 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
437 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
438 mlxsw_tx_hdr_swid_set(txhdr, 0);
439 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
440 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
441 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
442}
443
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200444int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
445 u8 state)
446{
447 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
448 enum mlxsw_reg_spms_state spms_state;
449 char *spms_pl;
450 int err;
451
452 switch (state) {
453 case BR_STATE_FORWARDING:
454 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
455 break;
456 case BR_STATE_LEARNING:
457 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
458 break;
459 case BR_STATE_LISTENING: /* fall-through */
460 case BR_STATE_DISABLED: /* fall-through */
461 case BR_STATE_BLOCKING:
462 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
463 break;
464 default:
465 BUG();
466 }
467
468 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
469 if (!spms_pl)
470 return -ENOMEM;
471 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
472 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
473
474 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
475 kfree(spms_pl);
476 return err;
477}
478
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200479static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
480{
Elad Raz5b090742016-10-28 21:35:46 +0200481 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200482 int err;
483
484 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
485 if (err)
486 return err;
487 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
488 return 0;
489}
490
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100491static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
492 bool enable, u32 rate)
493{
494 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
495 char mpsc_pl[MLXSW_REG_MPSC_LEN];
496
497 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
498 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
499}
500
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200501static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
502 bool is_up)
503{
504 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
505 char paos_pl[MLXSW_REG_PAOS_LEN];
506
507 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
508 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
509 MLXSW_PORT_ADMIN_STATUS_DOWN);
510 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
511}
512
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200513static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
514 unsigned char *addr)
515{
516 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
517 char ppad_pl[MLXSW_REG_PPAD_LEN];
518
519 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
520 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
521 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
522}
523
524static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
525{
526 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
527 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
528
529 ether_addr_copy(addr, mlxsw_sp->base_mac);
530 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
531 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
532}
533
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200534static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
535{
536 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
537 char pmtu_pl[MLXSW_REG_PMTU_LEN];
538 int max_mtu;
539 int err;
540
541 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
542 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
543 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
544 if (err)
545 return err;
546 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
547
548 if (mtu > max_mtu)
549 return -EINVAL;
550
551 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
552 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
553}
554
555static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
556{
557 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel5b153852017-06-08 08:47:44 +0200558 char pspa_pl[MLXSW_REG_PSPA_LEN];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200559
Ido Schimmel5b153852017-06-08 08:47:44 +0200560 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
561 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200562}
563
Ido Schimmela1107482017-05-26 08:37:39 +0200564int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200565{
566 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
567 char svpe_pl[MLXSW_REG_SVPE_LEN];
568
569 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
570 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
571}
572
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200573int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
574 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200575{
576 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
577 char *spvmlr_pl;
578 int err;
579
580 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
581 if (!spvmlr_pl)
582 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200583 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
584 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200585 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
586 kfree(spvmlr_pl);
587 return err;
588}
589
Ido Schimmelb02eae92017-05-16 19:38:34 +0200590static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
591 u16 vid)
592{
593 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
594 char spvid_pl[MLXSW_REG_SPVID_LEN];
595
596 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
597 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
598}
599
600static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
601 bool allow)
602{
603 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
604 char spaft_pl[MLXSW_REG_SPAFT_LEN];
605
606 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
607 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
608}
609
610int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
611{
612 int err;
613
614 if (!vid) {
615 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
616 if (err)
617 return err;
618 } else {
619 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
620 if (err)
621 return err;
622 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
623 if (err)
624 goto err_port_allow_untagged_set;
625 }
626
627 mlxsw_sp_port->pvid = vid;
628 return 0;
629
630err_port_allow_untagged_set:
631 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
632 return err;
633}
634
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200635static int
636mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
637{
638 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
639 char sspr_pl[MLXSW_REG_SSPR_LEN];
640
641 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
642 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
643}
644
Ido Schimmeld664b412016-06-09 09:51:40 +0200645static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
646 u8 local_port, u8 *p_module,
647 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200648{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200649 char pmlp_pl[MLXSW_REG_PMLP_LEN];
650 int err;
651
Ido Schimmel558c2d52016-02-26 17:32:29 +0100652 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200653 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
654 if (err)
655 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100656 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
657 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200658 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200659 return 0;
660}
661
Ido Schimmel2e915e02017-06-08 08:47:45 +0200662static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100663 u8 module, u8 width, u8 lane)
664{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200665 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel18f1e702016-02-26 17:32:31 +0100666 char pmlp_pl[MLXSW_REG_PMLP_LEN];
667 int i;
668
Ido Schimmel2e915e02017-06-08 08:47:45 +0200669 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel18f1e702016-02-26 17:32:31 +0100670 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
671 for (i = 0; i < width; i++) {
672 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
673 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
674 }
675
676 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
677}
678
Ido Schimmel2e915e02017-06-08 08:47:45 +0200679static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100680{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200681 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100682 char pmlp_pl[MLXSW_REG_PMLP_LEN];
683
Ido Schimmel2e915e02017-06-08 08:47:45 +0200684 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100685 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
686 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
687}
688
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200689static int mlxsw_sp_port_open(struct net_device *dev)
690{
691 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
692 int err;
693
694 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
695 if (err)
696 return err;
697 netif_start_queue(dev);
698 return 0;
699}
700
701static int mlxsw_sp_port_stop(struct net_device *dev)
702{
703 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
704
705 netif_stop_queue(dev);
706 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
707}
708
709static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
710 struct net_device *dev)
711{
712 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
713 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
714 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
715 const struct mlxsw_tx_info tx_info = {
716 .local_port = mlxsw_sp_port->local_port,
717 .is_emad = false,
718 };
719 u64 len;
720 int err;
721
Jiri Pirko307c2432016-04-08 19:11:22 +0200722 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200723 return NETDEV_TX_BUSY;
724
725 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
726 struct sk_buff *skb_orig = skb;
727
728 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
729 if (!skb) {
730 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
731 dev_kfree_skb_any(skb_orig);
732 return NETDEV_TX_OK;
733 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +0100734 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200735 }
736
737 if (eth_skb_pad(skb)) {
738 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
739 return NETDEV_TX_OK;
740 }
741
742 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +0200743 /* TX header is consumed by HW on the way so we shouldn't count its
744 * bytes as being sent.
745 */
746 len = skb->len - MLXSW_TXHDR_LEN;
747
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200748 /* Due to a race we might fail here because of a full queue. In that
749 * unlikely case we simply drop the packet.
750 */
Jiri Pirko307c2432016-04-08 19:11:22 +0200751 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200752
753 if (!err) {
754 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
755 u64_stats_update_begin(&pcpu_stats->syncp);
756 pcpu_stats->tx_packets++;
757 pcpu_stats->tx_bytes += len;
758 u64_stats_update_end(&pcpu_stats->syncp);
759 } else {
760 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
761 dev_kfree_skb_any(skb);
762 }
763 return NETDEV_TX_OK;
764}
765
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100766static void mlxsw_sp_set_rx_mode(struct net_device *dev)
767{
768}
769
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200770static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
771{
772 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
773 struct sockaddr *addr = p;
774 int err;
775
776 if (!is_valid_ether_addr(addr->sa_data))
777 return -EADDRNOTAVAIL;
778
779 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
780 if (err)
781 return err;
782 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
783 return 0;
784}
785
Ido Schimmel18281f22017-03-24 08:02:51 +0100786static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
787 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200788{
Ido Schimmel18281f22017-03-24 08:02:51 +0100789 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100790}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200791
Ido Schimmelf417f042017-03-24 08:02:50 +0100792#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +0100793
794static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
795 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +0100796{
Ido Schimmel18281f22017-03-24 08:02:51 +0100797 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
798 BITS_PER_BYTE));
799 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
800 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100801}
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200802
Ido Schimmel18281f22017-03-24 08:02:51 +0100803/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +0100804 * Assumes 100m cable and maximum MTU.
805 */
Ido Schimmel18281f22017-03-24 08:02:51 +0100806#define MLXSW_SP_PAUSE_DELAY 58752
807
808static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
809 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +0100810{
811 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +0100812 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +0100813 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +0100814 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200815 else
Ido Schimmelf417f042017-03-24 08:02:50 +0100816 return 0;
817}
818
819static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
820 bool lossy)
821{
822 if (lossy)
823 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
824 else
825 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
826 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200827}
828
829int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200830 u8 *prio_tc, bool pause_en,
831 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +0200832{
833 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200834 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
835 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200836 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200837 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200838
839 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
840 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
841 if (err)
842 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200843
844 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
845 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200846 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +0100847 bool lossy;
848 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200849
850 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
851 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200852 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200853 configure = true;
854 break;
855 }
856 }
857
858 if (!configure)
859 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +0100860
861 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +0100862 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
863 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
864 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +0100865 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200866 }
867
Ido Schimmelff6551e2016-04-06 17:10:03 +0200868 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
869}
870
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200871static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200872 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200873{
874 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
875 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200876 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200877 u8 *prio_tc;
878
879 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200880 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200881
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200882 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200883 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200884}
885
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200886static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
887{
888 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200889 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200890 int err;
891
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200892 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200893 if (err)
894 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200895 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
896 if (err)
897 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200898 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
899 if (err)
900 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200901 dev->mtu = mtu;
902 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200903
904err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +0200905 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
906err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200907 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +0200908 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200909}
910
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +0300911static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200912mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
913 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200914{
915 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
916 struct mlxsw_sp_port_pcpu_stats *p;
917 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
918 u32 tx_dropped = 0;
919 unsigned int start;
920 int i;
921
922 for_each_possible_cpu(i) {
923 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
924 do {
925 start = u64_stats_fetch_begin_irq(&p->syncp);
926 rx_packets = p->rx_packets;
927 rx_bytes = p->rx_bytes;
928 tx_packets = p->tx_packets;
929 tx_bytes = p->tx_bytes;
930 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
931
932 stats->rx_packets += rx_packets;
933 stats->rx_bytes += rx_bytes;
934 stats->tx_packets += tx_packets;
935 stats->tx_bytes += tx_bytes;
936 /* tx_dropped is u32, updated without syncp protection. */
937 tx_dropped += p->tx_dropped;
938 }
939 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200940 return 0;
941}
942
Or Gerlitz3df5b3c2016-11-22 23:09:54 +0200943static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200944{
945 switch (attr_id) {
946 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
947 return true;
948 }
949
950 return false;
951}
952
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +0300953static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
954 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200955{
956 switch (attr_id) {
957 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
958 return mlxsw_sp_port_get_sw_stats64(dev, sp);
959 }
960
961 return -EINVAL;
962}
963
964static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
965 int prio, char *ppcnt_pl)
966{
967 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
968 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
969
970 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
971 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
972}
973
974static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
975 struct rtnl_link_stats64 *stats)
976{
977 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
978 int err;
979
980 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
981 0, ppcnt_pl);
982 if (err)
983 goto out;
984
985 stats->tx_packets =
986 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
987 stats->rx_packets =
988 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
989 stats->tx_bytes =
990 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
991 stats->rx_bytes =
992 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
993 stats->multicast =
994 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
995
996 stats->rx_crc_errors =
997 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
998 stats->rx_frame_errors =
999 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1000
1001 stats->rx_length_errors = (
1002 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1003 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1004 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1005
1006 stats->rx_errors = (stats->rx_crc_errors +
1007 stats->rx_frame_errors + stats->rx_length_errors);
1008
1009out:
1010 return err;
1011}
1012
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001013static void
1014mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1015 struct mlxsw_sp_port_xstats *xstats)
1016{
1017 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1018 int err, i;
1019
1020 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1021 ppcnt_pl);
1022 if (!err)
1023 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1024
1025 for (i = 0; i < TC_MAX_QUEUE; i++) {
1026 err = mlxsw_sp_port_get_stats_raw(dev,
1027 MLXSW_REG_PPCNT_TC_CONG_TC,
1028 i, ppcnt_pl);
1029 if (!err)
1030 xstats->wred_drop[i] =
1031 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1032
1033 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1034 i, ppcnt_pl);
1035 if (err)
1036 continue;
1037
1038 xstats->backlog[i] =
1039 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1040 xstats->tail_drop[i] =
1041 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1042 }
1043}
1044
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001045static void update_stats_cache(struct work_struct *work)
1046{
1047 struct mlxsw_sp_port *mlxsw_sp_port =
1048 container_of(work, struct mlxsw_sp_port,
Nogah Frankel9deef432017-10-26 10:55:32 +02001049 periodic_hw_stats.update_dw.work);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001050
1051 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1052 goto out;
1053
1054 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
Nogah Frankel9deef432017-10-26 10:55:32 +02001055 &mlxsw_sp_port->periodic_hw_stats.stats);
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001056 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1057 &mlxsw_sp_port->periodic_hw_stats.xstats);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001058
1059out:
Nogah Frankel9deef432017-10-26 10:55:32 +02001060 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001061 MLXSW_HW_STATS_UPDATE_TIME);
1062}
1063
1064/* Return the stats from a cache that is updated periodically,
1065 * as this function might get called in an atomic context.
1066 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001067static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001068mlxsw_sp_port_get_stats64(struct net_device *dev,
1069 struct rtnl_link_stats64 *stats)
1070{
1071 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1072
Nogah Frankel9deef432017-10-26 10:55:32 +02001073 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001074}
1075
Jiri Pirko93cd0812017-04-18 16:55:35 +02001076static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1077 u16 vid_begin, u16 vid_end,
1078 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001079{
1080 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1081 char *spvm_pl;
1082 int err;
1083
1084 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1085 if (!spvm_pl)
1086 return -ENOMEM;
1087
1088 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1089 vid_end, is_member, untagged);
1090 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1091 kfree(spvm_pl);
1092 return err;
1093}
1094
Jiri Pirko93cd0812017-04-18 16:55:35 +02001095int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1096 u16 vid_end, bool is_member, bool untagged)
1097{
1098 u16 vid, vid_e;
1099 int err;
1100
1101 for (vid = vid_begin; vid <= vid_end;
1102 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1103 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1104 vid_end);
1105
1106 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1107 is_member, untagged);
1108 if (err)
1109 return err;
1110 }
1111
1112 return 0;
1113}
1114
Ido Schimmelc57529e2017-05-26 08:37:31 +02001115static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001116{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001117 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001118
Ido Schimmelc57529e2017-05-26 08:37:31 +02001119 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1120 &mlxsw_sp_port->vlans_list, list)
1121 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001122}
1123
Ido Schimmel31a08a52017-05-26 08:37:26 +02001124static struct mlxsw_sp_port_vlan *
1125mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1126{
1127 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001128 bool untagged = vid == 1;
1129 int err;
1130
1131 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1132 if (err)
1133 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001134
1135 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001136 if (!mlxsw_sp_port_vlan) {
1137 err = -ENOMEM;
1138 goto err_port_vlan_alloc;
1139 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02001140
1141 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1142 mlxsw_sp_port_vlan->vid = vid;
1143 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1144
1145 return mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001146
1147err_port_vlan_alloc:
1148 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1149 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001150}
1151
1152static void
1153mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1154{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001155 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1156 u16 vid = mlxsw_sp_port_vlan->vid;
Ido Schimmel7cbecf22017-05-26 08:37:28 +02001157
Ido Schimmel31a08a52017-05-26 08:37:26 +02001158 list_del(&mlxsw_sp_port_vlan->list);
1159 kfree(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001160 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1161}
1162
1163struct mlxsw_sp_port_vlan *
1164mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1165{
1166 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1167
1168 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1169 if (mlxsw_sp_port_vlan)
1170 return mlxsw_sp_port_vlan;
1171
1172 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1173}
1174
1175void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1176{
Ido Schimmela1107482017-05-26 08:37:39 +02001177 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1178
Ido Schimmelc57529e2017-05-26 08:37:31 +02001179 if (mlxsw_sp_port_vlan->bridge_port)
1180 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
Ido Schimmela1107482017-05-26 08:37:39 +02001181 else if (fid)
1182 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001183
1184 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001185}
1186
Ido Schimmel05978482016-08-17 16:39:30 +02001187static int mlxsw_sp_port_add_vid(struct net_device *dev,
1188 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001189{
1190 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001191
1192 /* VLAN 0 is added to HW filter when device goes up, but it is
1193 * reserved in our case, so simply return.
1194 */
1195 if (!vid)
1196 return 0;
1197
Ido Schimmelc57529e2017-05-26 08:37:31 +02001198 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001199}
1200
Ido Schimmel32d863f2016-07-02 11:00:10 +02001201static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1202 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001203{
1204 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001205 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001206
1207 /* VLAN 0 is removed from HW filter when device goes down, but
1208 * it is reserved in our case, so simply return.
1209 */
1210 if (!vid)
1211 return 0;
1212
Ido Schimmel31a08a52017-05-26 08:37:26 +02001213 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001214 if (!mlxsw_sp_port_vlan)
Ido Schimmel31a08a52017-05-26 08:37:26 +02001215 return 0;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001216 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001217
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001218 return 0;
1219}
1220
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001221static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1222 size_t len)
1223{
1224 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +02001225 u8 module = mlxsw_sp_port->mapping.module;
1226 u8 width = mlxsw_sp_port->mapping.width;
1227 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001228 int err;
1229
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001230 if (!mlxsw_sp_port->split)
1231 err = snprintf(name, len, "p%d", module + 1);
1232 else
1233 err = snprintf(name, len, "p%ds%d", module + 1,
1234 lane / width);
1235
1236 if (err >= len)
1237 return -EINVAL;
1238
1239 return 0;
1240}
1241
Yotam Gigi763b4b72016-07-21 12:03:17 +02001242static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001243mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1244 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001245 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1246
1247 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1248 if (mall_tc_entry->cookie == cookie)
1249 return mall_tc_entry;
1250
1251 return NULL;
1252}
1253
1254static int
1255mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001256 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001257 const struct tc_action *a,
1258 bool ingress)
1259{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001260 enum mlxsw_sp_span_type span_type;
1261 struct mlxsw_sp_port *to_port;
1262 struct net_device *to_dev;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001263
Cong Wang9f8a7392017-12-05 16:17:26 -08001264 to_dev = tcf_mirred_dev(a);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001265 if (!to_dev) {
1266 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1267 return -EINVAL;
1268 }
1269
1270 if (!mlxsw_sp_port_dev_check(to_dev)) {
1271 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
Yotam Gigie915ac62017-01-09 11:25:48 +01001272 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001273 }
1274 to_port = netdev_priv(to_dev);
1275
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001276 mirror->to_local_port = to_port->local_port;
1277 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001278 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +01001279 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type,
1280 true);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001281}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001282
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001283static void
1284mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1285 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1286{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001287 enum mlxsw_sp_span_type span_type;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001288
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001289 span_type = mirror->ingress ?
1290 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +01001291 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->to_local_port,
1292 span_type, true);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001293}
1294
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001295static int
1296mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1297 struct tc_cls_matchall_offload *cls,
1298 const struct tc_action *a,
1299 bool ingress)
1300{
1301 int err;
1302
1303 if (!mlxsw_sp_port->sample)
1304 return -EOPNOTSUPP;
1305 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1306 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1307 return -EEXIST;
1308 }
1309 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1310 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1311 return -EOPNOTSUPP;
1312 }
1313
1314 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1315 tcf_sample_psample_group(a));
1316 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1317 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1318 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1319
1320 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1321 if (err)
1322 goto err_port_sample_set;
1323 return 0;
1324
1325err_port_sample_set:
1326 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1327 return err;
1328}
1329
1330static void
1331mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1332{
1333 if (!mlxsw_sp_port->sample)
1334 return;
1335
1336 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1337 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1338}
1339
Yotam Gigi763b4b72016-07-21 12:03:17 +02001340static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001341 struct tc_cls_matchall_offload *f,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001342 bool ingress)
1343{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001344 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001345 __be16 protocol = f->common.protocol;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001346 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001347 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001348 int err;
1349
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001350 if (!tcf_exts_has_one_action(f->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001351 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001352 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001353 }
1354
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001355 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1356 if (!mall_tc_entry)
1357 return -ENOMEM;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001358 mall_tc_entry->cookie = f->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001359
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001360 tcf_exts_to_list(f->exts, &actions);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001361 a = list_first_entry(&actions, struct tc_action, list);
1362
1363 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1364 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1365
1366 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1367 mirror = &mall_tc_entry->mirror;
1368 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1369 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001370 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1371 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001372 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001373 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001374 } else {
1375 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001376 }
1377
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001378 if (err)
1379 goto err_add_action;
1380
1381 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001382 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001383
1384err_add_action:
1385 kfree(mall_tc_entry);
1386 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001387}
1388
1389static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001390 struct tc_cls_matchall_offload *f)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001391{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001392 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001393
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001394 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001395 f->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001396 if (!mall_tc_entry) {
1397 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1398 return;
1399 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001400 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001401
1402 switch (mall_tc_entry->type) {
1403 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001404 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1405 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001406 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001407 case MLXSW_SP_PORT_MALL_SAMPLE:
1408 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1409 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001410 default:
1411 WARN_ON(1);
1412 }
1413
Yotam Gigi763b4b72016-07-21 12:03:17 +02001414 kfree(mall_tc_entry);
1415}
1416
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001417static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001418 struct tc_cls_matchall_offload *f,
1419 bool ingress)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001420{
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001421 switch (f->command) {
1422 case TC_CLSMATCHALL_REPLACE:
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001423 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001424 ingress);
1425 case TC_CLSMATCHALL_DESTROY:
1426 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1427 return 0;
1428 default:
1429 return -EOPNOTSUPP;
1430 }
1431}
1432
1433static int
Jiri Pirko3aaff322018-01-17 11:46:56 +01001434mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1435 struct tc_cls_flower_offload *f)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001436{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001437 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1438
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001439 switch (f->command) {
1440 case TC_CLSFLOWER_REPLACE:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001441 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001442 case TC_CLSFLOWER_DESTROY:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001443 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001444 return 0;
1445 case TC_CLSFLOWER_STATS:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001446 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001447 default:
1448 return -EOPNOTSUPP;
1449 }
1450}
1451
Jiri Pirko3aaff322018-01-17 11:46:56 +01001452static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1453 void *type_data,
1454 void *cb_priv, bool ingress)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001455{
1456 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1457
1458 switch (type) {
1459 case TC_SETUP_CLSMATCHALL:
Jakub Kicinski15f4edb2018-01-25 14:00:51 -08001460 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1461 type_data))
Jiri Pirko3aaff322018-01-17 11:46:56 +01001462 return -EOPNOTSUPP;
1463
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001464 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1465 ingress);
1466 case TC_SETUP_CLSFLOWER:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001467 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001468 default:
1469 return -EOPNOTSUPP;
1470 }
1471}
1472
Jiri Pirko3aaff322018-01-17 11:46:56 +01001473static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1474 void *type_data,
1475 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001476{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001477 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1478 cb_priv, true);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001479}
1480
Jiri Pirko3aaff322018-01-17 11:46:56 +01001481static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1482 void *type_data,
1483 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001484{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001485 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1486 cb_priv, false);
1487}
1488
1489static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1490 void *type_data, void *cb_priv)
1491{
1492 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1493
1494 switch (type) {
1495 case TC_SETUP_CLSMATCHALL:
1496 return 0;
1497 case TC_SETUP_CLSFLOWER:
1498 if (mlxsw_sp_acl_block_disabled(acl_block))
1499 return -EOPNOTSUPP;
1500
1501 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1502 default:
1503 return -EOPNOTSUPP;
1504 }
1505}
1506
1507static int
1508mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1509 struct tcf_block *block, bool ingress)
1510{
1511 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1512 struct mlxsw_sp_acl_block *acl_block;
1513 struct tcf_block_cb *block_cb;
1514 int err;
1515
1516 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1517 mlxsw_sp);
1518 if (!block_cb) {
1519 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1520 if (!acl_block)
1521 return -ENOMEM;
1522 block_cb = __tcf_block_cb_register(block,
1523 mlxsw_sp_setup_tc_block_cb_flower,
1524 mlxsw_sp, acl_block);
1525 if (IS_ERR(block_cb)) {
1526 err = PTR_ERR(block_cb);
1527 goto err_cb_register;
1528 }
1529 } else {
1530 acl_block = tcf_block_cb_priv(block_cb);
1531 }
1532 tcf_block_cb_incref(block_cb);
1533 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1534 mlxsw_sp_port, ingress);
1535 if (err)
1536 goto err_block_bind;
1537
1538 if (ingress)
1539 mlxsw_sp_port->ing_acl_block = acl_block;
1540 else
1541 mlxsw_sp_port->eg_acl_block = acl_block;
1542
1543 return 0;
1544
1545err_block_bind:
1546 if (!tcf_block_cb_decref(block_cb)) {
1547 __tcf_block_cb_unregister(block_cb);
1548err_cb_register:
1549 mlxsw_sp_acl_block_destroy(acl_block);
1550 }
1551 return err;
1552}
1553
1554static void
1555mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1556 struct tcf_block *block, bool ingress)
1557{
1558 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1559 struct mlxsw_sp_acl_block *acl_block;
1560 struct tcf_block_cb *block_cb;
1561 int err;
1562
1563 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1564 mlxsw_sp);
1565 if (!block_cb)
1566 return;
1567
1568 if (ingress)
1569 mlxsw_sp_port->ing_acl_block = NULL;
1570 else
1571 mlxsw_sp_port->eg_acl_block = NULL;
1572
1573 acl_block = tcf_block_cb_priv(block_cb);
1574 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1575 mlxsw_sp_port, ingress);
1576 if (!err && !tcf_block_cb_decref(block_cb)) {
1577 __tcf_block_cb_unregister(block_cb);
1578 mlxsw_sp_acl_block_destroy(acl_block);
1579 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001580}
1581
1582static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1583 struct tc_block_offload *f)
1584{
1585 tc_setup_cb_t *cb;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001586 bool ingress;
1587 int err;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001588
Jiri Pirko3aaff322018-01-17 11:46:56 +01001589 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1590 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1591 ingress = true;
1592 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1593 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1594 ingress = false;
1595 } else {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001596 return -EOPNOTSUPP;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001597 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001598
1599 switch (f->command) {
1600 case TC_BLOCK_BIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001601 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1602 mlxsw_sp_port);
1603 if (err)
1604 return err;
1605 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
1606 f->block, ingress);
1607 if (err) {
1608 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1609 return err;
1610 }
1611 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001612 case TC_BLOCK_UNBIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001613 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1614 f->block, ingress);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001615 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1616 return 0;
1617 default:
1618 return -EOPNOTSUPP;
1619 }
1620}
1621
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001622static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
Jiri Pirkode4784c2017-08-07 10:15:32 +02001623 void *type_data)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001624{
1625 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1626
Jiri Pirko2572ac52017-08-07 10:15:17 +02001627 switch (type) {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001628 case TC_SETUP_BLOCK:
1629 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
Nogah Frankel96f17e02017-11-06 07:23:45 +01001630 case TC_SETUP_QDISC_RED:
1631 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
Nogah Frankel46a36152018-01-14 12:33:16 +01001632 case TC_SETUP_QDISC_PRIO:
1633 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
Jiri Pirko2572ac52017-08-07 10:15:17 +02001634 default:
1635 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001636 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001637}
1638
Jiri Pirko9454d932017-12-06 09:41:12 +01001639
1640static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1641{
1642 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1643
Jiri Pirko3aaff322018-01-17 11:46:56 +01001644 if (!enable) {
1645 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1646 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1647 !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1648 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1649 return -EINVAL;
1650 }
1651 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1652 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1653 } else {
1654 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1655 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
Jiri Pirko9454d932017-12-06 09:41:12 +01001656 }
1657 return 0;
1658}
1659
1660typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1661
1662static int mlxsw_sp_handle_feature(struct net_device *dev,
1663 netdev_features_t wanted_features,
1664 netdev_features_t feature,
1665 mlxsw_sp_feature_handler feature_handler)
1666{
1667 netdev_features_t changes = wanted_features ^ dev->features;
1668 bool enable = !!(wanted_features & feature);
1669 int err;
1670
1671 if (!(changes & feature))
1672 return 0;
1673
1674 err = feature_handler(dev, enable);
1675 if (err) {
1676 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1677 enable ? "Enable" : "Disable", &feature, err);
1678 return err;
1679 }
1680
1681 if (enable)
1682 dev->features |= feature;
1683 else
1684 dev->features &= ~feature;
1685
1686 return 0;
1687}
1688static int mlxsw_sp_set_features(struct net_device *dev,
1689 netdev_features_t features)
1690{
1691 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1692 mlxsw_sp_feature_hw_tc);
1693}
1694
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001695static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1696 .ndo_open = mlxsw_sp_port_open,
1697 .ndo_stop = mlxsw_sp_port_stop,
1698 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001699 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001700 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001701 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1702 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1703 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001704 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1705 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001706 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1707 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001708 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko9454d932017-12-06 09:41:12 +01001709 .ndo_set_features = mlxsw_sp_set_features,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001710};
1711
1712static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1713 struct ethtool_drvinfo *drvinfo)
1714{
1715 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1716 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1717
1718 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1719 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1720 sizeof(drvinfo->version));
1721 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1722 "%d.%d.%d",
1723 mlxsw_sp->bus_info->fw_rev.major,
1724 mlxsw_sp->bus_info->fw_rev.minor,
1725 mlxsw_sp->bus_info->fw_rev.subminor);
1726 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1727 sizeof(drvinfo->bus_info));
1728}
1729
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001730static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1731 struct ethtool_pauseparam *pause)
1732{
1733 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1734
1735 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1736 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1737}
1738
1739static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1740 struct ethtool_pauseparam *pause)
1741{
1742 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1743
1744 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1745 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1746 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1747
1748 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1749 pfcc_pl);
1750}
1751
1752static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1753 struct ethtool_pauseparam *pause)
1754{
1755 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1756 bool pause_en = pause->tx_pause || pause->rx_pause;
1757 int err;
1758
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001759 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1760 netdev_err(dev, "PFC already enabled on port\n");
1761 return -EINVAL;
1762 }
1763
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001764 if (pause->autoneg) {
1765 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1766 return -EINVAL;
1767 }
1768
1769 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1770 if (err) {
1771 netdev_err(dev, "Failed to configure port's headroom\n");
1772 return err;
1773 }
1774
1775 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1776 if (err) {
1777 netdev_err(dev, "Failed to set PAUSE parameters\n");
1778 goto err_port_pause_configure;
1779 }
1780
1781 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1782 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1783
1784 return 0;
1785
1786err_port_pause_configure:
1787 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1788 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1789 return err;
1790}
1791
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001792struct mlxsw_sp_port_hw_stats {
1793 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02001794 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01001795 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001796};
1797
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001798static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001799 {
1800 .str = "a_frames_transmitted_ok",
1801 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1802 },
1803 {
1804 .str = "a_frames_received_ok",
1805 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1806 },
1807 {
1808 .str = "a_frame_check_sequence_errors",
1809 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1810 },
1811 {
1812 .str = "a_alignment_errors",
1813 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1814 },
1815 {
1816 .str = "a_octets_transmitted_ok",
1817 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1818 },
1819 {
1820 .str = "a_octets_received_ok",
1821 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1822 },
1823 {
1824 .str = "a_multicast_frames_xmitted_ok",
1825 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1826 },
1827 {
1828 .str = "a_broadcast_frames_xmitted_ok",
1829 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1830 },
1831 {
1832 .str = "a_multicast_frames_received_ok",
1833 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1834 },
1835 {
1836 .str = "a_broadcast_frames_received_ok",
1837 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1838 },
1839 {
1840 .str = "a_in_range_length_errors",
1841 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1842 },
1843 {
1844 .str = "a_out_of_range_length_field",
1845 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1846 },
1847 {
1848 .str = "a_frame_too_long_errors",
1849 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1850 },
1851 {
1852 .str = "a_symbol_error_during_carrier",
1853 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1854 },
1855 {
1856 .str = "a_mac_control_frames_transmitted",
1857 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1858 },
1859 {
1860 .str = "a_mac_control_frames_received",
1861 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1862 },
1863 {
1864 .str = "a_unsupported_opcodes_received",
1865 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1866 },
1867 {
1868 .str = "a_pause_mac_ctrl_frames_received",
1869 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1870 },
1871 {
1872 .str = "a_pause_mac_ctrl_frames_xmitted",
1873 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1874 },
1875};
1876
1877#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1878
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001879static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1880 {
1881 .str = "rx_octets_prio",
1882 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1883 },
1884 {
1885 .str = "rx_frames_prio",
1886 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1887 },
1888 {
1889 .str = "tx_octets_prio",
1890 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1891 },
1892 {
1893 .str = "tx_frames_prio",
1894 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1895 },
1896 {
1897 .str = "rx_pause_prio",
1898 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1899 },
1900 {
1901 .str = "rx_pause_duration_prio",
1902 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1903 },
1904 {
1905 .str = "tx_pause_prio",
1906 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1907 },
1908 {
1909 .str = "tx_pause_duration_prio",
1910 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1911 },
1912};
1913
1914#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1915
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001916static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1917 {
1918 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01001919 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1920 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001921 },
1922 {
1923 .str = "tc_no_buffer_discard_uc_tc",
1924 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1925 },
1926};
1927
1928#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1929
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001930#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001931 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1932 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001933 IEEE_8021QAZ_MAX_TCS)
1934
1935static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1936{
1937 int i;
1938
1939 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1940 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1941 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1942 *p += ETH_GSTRING_LEN;
1943 }
1944}
1945
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001946static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1947{
1948 int i;
1949
1950 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1951 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1952 mlxsw_sp_port_hw_tc_stats[i].str, tc);
1953 *p += ETH_GSTRING_LEN;
1954 }
1955}
1956
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001957static void mlxsw_sp_port_get_strings(struct net_device *dev,
1958 u32 stringset, u8 *data)
1959{
1960 u8 *p = data;
1961 int i;
1962
1963 switch (stringset) {
1964 case ETH_SS_STATS:
1965 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1966 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1967 ETH_GSTRING_LEN);
1968 p += ETH_GSTRING_LEN;
1969 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001970
1971 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1972 mlxsw_sp_port_get_prio_strings(&p, i);
1973
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001974 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1975 mlxsw_sp_port_get_tc_strings(&p, i);
1976
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001977 break;
1978 }
1979}
1980
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001981static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1982 enum ethtool_phys_id_state state)
1983{
1984 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1985 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1986 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1987 bool active;
1988
1989 switch (state) {
1990 case ETHTOOL_ID_ACTIVE:
1991 active = true;
1992 break;
1993 case ETHTOOL_ID_INACTIVE:
1994 active = false;
1995 break;
1996 default:
1997 return -EOPNOTSUPP;
1998 }
1999
2000 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2001 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2002}
2003
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002004static int
2005mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2006 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2007{
2008 switch (grp) {
2009 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2010 *p_hw_stats = mlxsw_sp_port_hw_stats;
2011 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2012 break;
2013 case MLXSW_REG_PPCNT_PRIO_CNT:
2014 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2015 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2016 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002017 case MLXSW_REG_PPCNT_TC_CNT:
2018 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2019 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2020 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002021 default:
2022 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002023 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002024 }
2025 return 0;
2026}
2027
2028static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2029 enum mlxsw_reg_ppcnt_grp grp, int prio,
2030 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002031{
Ido Schimmel18281f22017-03-24 08:02:51 +01002032 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2033 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002034 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002035 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002036 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002037 int err;
2038
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002039 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2040 if (err)
2041 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002042 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002043 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002044 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002045 if (!hw_stats[i].cells_bytes)
2046 continue;
2047 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2048 data[data_index + i]);
2049 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002050}
2051
2052static void mlxsw_sp_port_get_stats(struct net_device *dev,
2053 struct ethtool_stats *stats, u64 *data)
2054{
2055 int i, data_index = 0;
2056
2057 /* IEEE 802.3 Counters */
2058 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2059 data, data_index);
2060 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2061
2062 /* Per-Priority Counters */
2063 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2064 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2065 data, data_index);
2066 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2067 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002068
2069 /* Per-TC Counters */
2070 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2071 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2072 data, data_index);
2073 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2074 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002075}
2076
2077static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2078{
2079 switch (sset) {
2080 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002081 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002082 default:
2083 return -EOPNOTSUPP;
2084 }
2085}
2086
2087struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002088 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002089 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002090 u32 speed;
2091};
2092
2093static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2094 {
2095 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002096 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2097 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002098 },
2099 {
2100 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2101 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002102 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2103 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002104 },
2105 {
2106 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002107 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2108 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002109 },
2110 {
2111 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2112 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002113 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2114 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002115 },
2116 {
2117 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2118 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2119 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2120 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002121 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2122 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002123 },
2124 {
2125 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002126 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2127 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002128 },
2129 {
2130 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002131 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2132 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002133 },
2134 {
2135 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002136 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2137 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002138 },
2139 {
2140 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002141 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2142 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002143 },
2144 {
2145 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002146 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2147 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002148 },
2149 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002150 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2151 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2152 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002153 },
2154 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002155 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2156 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2157 .speed = SPEED_25000,
2158 },
2159 {
2160 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2161 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2162 .speed = SPEED_25000,
2163 },
2164 {
2165 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2166 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2167 .speed = SPEED_25000,
2168 },
2169 {
2170 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2171 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2172 .speed = SPEED_50000,
2173 },
2174 {
2175 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2176 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2177 .speed = SPEED_50000,
2178 },
2179 {
2180 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2181 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2182 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002183 },
2184 {
2185 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002186 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2187 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002188 },
2189 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002190 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2191 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2192 .speed = SPEED_56000,
2193 },
2194 {
2195 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2196 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2197 .speed = SPEED_56000,
2198 },
2199 {
2200 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2201 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2202 .speed = SPEED_56000,
2203 },
2204 {
2205 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2206 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2207 .speed = SPEED_100000,
2208 },
2209 {
2210 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2211 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2212 .speed = SPEED_100000,
2213 },
2214 {
2215 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2216 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2217 .speed = SPEED_100000,
2218 },
2219 {
2220 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2221 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2222 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002223 },
2224};
2225
2226#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2227
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002228static void
2229mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2230 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002231{
2232 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2233 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2234 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2235 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2236 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2237 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002238 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002239
2240 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2241 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2242 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2243 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2244 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002245 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002246}
2247
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002248static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002249{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002250 int i;
2251
2252 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2253 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002254 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2255 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002256 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002257}
2258
2259static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002260 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002261{
2262 u32 speed = SPEED_UNKNOWN;
2263 u8 duplex = DUPLEX_UNKNOWN;
2264 int i;
2265
2266 if (!carrier_ok)
2267 goto out;
2268
2269 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2270 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2271 speed = mlxsw_sp_port_link_mode[i].speed;
2272 duplex = DUPLEX_FULL;
2273 break;
2274 }
2275 }
2276out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002277 cmd->base.speed = speed;
2278 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002279}
2280
2281static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2282{
2283 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2284 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2285 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2286 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2287 return PORT_FIBRE;
2288
2289 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2290 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2291 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2292 return PORT_DA;
2293
2294 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2295 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2296 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2297 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2298 return PORT_NONE;
2299
2300 return PORT_OTHER;
2301}
2302
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002303static u32
2304mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002305{
2306 u32 ptys_proto = 0;
2307 int i;
2308
2309 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002310 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2311 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002312 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2313 }
2314 return ptys_proto;
2315}
2316
2317static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2318{
2319 u32 ptys_proto = 0;
2320 int i;
2321
2322 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2323 if (speed == mlxsw_sp_port_link_mode[i].speed)
2324 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2325 }
2326 return ptys_proto;
2327}
2328
Ido Schimmel18f1e702016-02-26 17:32:31 +01002329static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2330{
2331 u32 ptys_proto = 0;
2332 int i;
2333
2334 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2335 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2336 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2337 }
2338 return ptys_proto;
2339}
2340
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002341static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2342 struct ethtool_link_ksettings *cmd)
2343{
2344 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2345 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2346 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2347
2348 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2349 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2350}
2351
2352static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2353 struct ethtool_link_ksettings *cmd)
2354{
2355 if (!autoneg)
2356 return;
2357
2358 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2359 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2360}
2361
2362static void
2363mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2364 struct ethtool_link_ksettings *cmd)
2365{
2366 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2367 return;
2368
2369 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2370 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2371}
2372
2373static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2374 struct ethtool_link_ksettings *cmd)
2375{
2376 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2377 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2378 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2379 char ptys_pl[MLXSW_REG_PTYS_LEN];
2380 u8 autoneg_status;
2381 bool autoneg;
2382 int err;
2383
2384 autoneg = mlxsw_sp_port->link.autoneg;
Elad Raz401c8b42016-10-28 21:35:52 +02002385 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002386 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2387 if (err)
2388 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002389 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2390 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002391
2392 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2393
2394 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2395
2396 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2397 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2398 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2399
2400 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2401 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2402 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2403 cmd);
2404
2405 return 0;
2406}
2407
2408static int
2409mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2410 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002411{
2412 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2413 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2414 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002415 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002416 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002417 int err;
2418
Elad Raz401c8b42016-10-28 21:35:52 +02002419 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002420 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002421 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002422 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002423 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002424
2425 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2426 eth_proto_new = autoneg ?
2427 mlxsw_sp_to_ptys_advert_link(cmd) :
2428 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002429
2430 eth_proto_new = eth_proto_new & eth_proto_cap;
2431 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002432 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002433 return -EINVAL;
2434 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002435
Elad Raz401c8b42016-10-28 21:35:52 +02002436 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2437 eth_proto_new);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002438 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002439 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002440 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002441
Ido Schimmel6277d462016-07-15 11:14:58 +02002442 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002443 return 0;
2444
Ido Schimmel0c83f882016-09-12 13:26:23 +02002445 mlxsw_sp_port->link.autoneg = autoneg;
2446
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002447 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2448 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002449
2450 return 0;
2451}
2452
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002453static int mlxsw_sp_flash_device(struct net_device *dev,
2454 struct ethtool_flash *flash)
2455{
2456 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2457 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2458 const struct firmware *firmware;
2459 int err;
2460
2461 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2462 return -EOPNOTSUPP;
2463
2464 dev_hold(dev);
2465 rtnl_unlock();
2466
2467 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2468 if (err)
2469 goto out;
2470 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2471 release_firmware(firmware);
2472out:
2473 rtnl_lock();
2474 dev_put(dev);
2475 return err;
2476}
2477
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002478#define MLXSW_SP_I2C_ADDR_LOW 0x50
2479#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2480#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002481
2482static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2483 u16 offset, u16 size, void *data,
2484 unsigned int *p_read_size)
2485{
2486 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2487 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2488 char mcia_pl[MLXSW_REG_MCIA_LEN];
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002489 u16 i2c_addr;
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002490 int status;
2491 int err;
2492
2493 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002494
2495 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2496 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2497 /* Cross pages read, read until offset 256 in low page */
2498 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2499
2500 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2501 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2502 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2503 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2504 }
2505
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002506 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002507 0, 0, offset, size, i2c_addr);
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002508
2509 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2510 if (err)
2511 return err;
2512
2513 status = mlxsw_reg_mcia_status_get(mcia_pl);
2514 if (status)
2515 return -EIO;
2516
2517 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2518 memcpy(data, eeprom_tmp, size);
2519 *p_read_size = size;
2520
2521 return 0;
2522}
2523
2524enum mlxsw_sp_eeprom_module_info_rev_id {
2525 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2526 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2527 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2528};
2529
2530enum mlxsw_sp_eeprom_module_info_id {
2531 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2532 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2533 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2534 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2535};
2536
2537enum mlxsw_sp_eeprom_module_info {
2538 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2539 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2540 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2541};
2542
2543static int mlxsw_sp_get_module_info(struct net_device *netdev,
2544 struct ethtool_modinfo *modinfo)
2545{
2546 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2547 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2548 u8 module_rev_id, module_id;
2549 unsigned int read_size;
2550 int err;
2551
2552 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2553 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2554 module_info, &read_size);
2555 if (err)
2556 return err;
2557
2558 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2559 return -EIO;
2560
2561 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2562 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2563
2564 switch (module_id) {
2565 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2566 modinfo->type = ETH_MODULE_SFF_8436;
2567 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2568 break;
2569 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2570 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2571 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2572 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2573 modinfo->type = ETH_MODULE_SFF_8636;
2574 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2575 } else {
2576 modinfo->type = ETH_MODULE_SFF_8436;
2577 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2578 }
2579 break;
2580 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2581 modinfo->type = ETH_MODULE_SFF_8472;
2582 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2583 break;
2584 default:
2585 return -EINVAL;
2586 }
2587
2588 return 0;
2589}
2590
2591static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2592 struct ethtool_eeprom *ee,
2593 u8 *data)
2594{
2595 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2596 int offset = ee->offset;
2597 unsigned int read_size;
2598 int i = 0;
2599 int err;
2600
2601 if (!ee->len)
2602 return -EINVAL;
2603
2604 memset(data, 0, ee->len);
2605
2606 while (i < ee->len) {
2607 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2608 ee->len - i, data + i,
2609 &read_size);
2610 if (err) {
2611 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2612 return err;
2613 }
2614
2615 i += read_size;
2616 offset += read_size;
2617 }
2618
2619 return 0;
2620}
2621
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002622static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2623 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2624 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002625 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2626 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002627 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002628 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002629 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2630 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002631 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2632 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002633 .flash_device = mlxsw_sp_flash_device,
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002634 .get_module_info = mlxsw_sp_get_module_info,
2635 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002636};
2637
Ido Schimmel18f1e702016-02-26 17:32:31 +01002638static int
2639mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2640{
2641 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2642 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2643 char ptys_pl[MLXSW_REG_PTYS_LEN];
2644 u32 eth_proto_admin;
2645
2646 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002647 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2648 eth_proto_admin);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002649 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2650}
2651
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002652int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2653 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2654 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002655{
2656 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2657 char qeec_pl[MLXSW_REG_QEEC_LEN];
2658
2659 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2660 next_index);
2661 mlxsw_reg_qeec_de_set(qeec_pl, true);
2662 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2663 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2664 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2665}
2666
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002667int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2668 enum mlxsw_reg_qeec_hr hr, u8 index,
2669 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002670{
2671 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2672 char qeec_pl[MLXSW_REG_QEEC_LEN];
2673
2674 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2675 next_index);
2676 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2677 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2678 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2679}
2680
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002681int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2682 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002683{
2684 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2685 char qtct_pl[MLXSW_REG_QTCT_LEN];
2686
2687 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2688 tclass);
2689 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2690}
2691
2692static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2693{
2694 int err, i;
2695
2696 /* Setup the elements hierarcy, so that each TC is linked to
2697 * one subgroup, which are all member in the same group.
2698 */
2699 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2700 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2701 0);
2702 if (err)
2703 return err;
2704 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2705 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2706 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2707 0, false, 0);
2708 if (err)
2709 return err;
2710 }
2711 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2712 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2713 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2714 false, 0);
2715 if (err)
2716 return err;
2717 }
2718
2719 /* Make sure the max shaper is disabled in all hierarcies that
2720 * support it.
2721 */
2722 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2723 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2724 MLXSW_REG_QEEC_MAS_DIS);
2725 if (err)
2726 return err;
2727 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2728 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2729 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2730 i, 0,
2731 MLXSW_REG_QEEC_MAS_DIS);
2732 if (err)
2733 return err;
2734 }
2735 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2736 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2737 MLXSW_REG_QEEC_HIERARCY_TC,
2738 i, i,
2739 MLXSW_REG_QEEC_MAS_DIS);
2740 if (err)
2741 return err;
2742 }
2743
2744 /* Map all priorities to traffic class 0. */
2745 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2746 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2747 if (err)
2748 return err;
2749 }
2750
2751 return 0;
2752}
2753
Ido Schimmel5b153852017-06-08 08:47:44 +02002754static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2755 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002756{
Ido Schimmelc57529e2017-05-26 08:37:31 +02002757 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002758 struct mlxsw_sp_port *mlxsw_sp_port;
2759 struct net_device *dev;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002760 int err;
2761
Ido Schimmel5b153852017-06-08 08:47:44 +02002762 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2763 if (err) {
2764 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2765 local_port);
2766 return err;
2767 }
2768
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002769 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
Ido Schimmel5b153852017-06-08 08:47:44 +02002770 if (!dev) {
2771 err = -ENOMEM;
2772 goto err_alloc_etherdev;
2773 }
Jiri Pirkof20a91f2016-10-27 15:13:00 +02002774 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002775 mlxsw_sp_port = netdev_priv(dev);
2776 mlxsw_sp_port->dev = dev;
2777 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2778 mlxsw_sp_port->local_port = local_port;
Ido Schimmelc57529e2017-05-26 08:37:31 +02002779 mlxsw_sp_port->pvid = 1;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002780 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02002781 mlxsw_sp_port->mapping.module = module;
2782 mlxsw_sp_port->mapping.width = width;
2783 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002784 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02002785 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02002786 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002787
2788 mlxsw_sp_port->pcpu_stats =
2789 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2790 if (!mlxsw_sp_port->pcpu_stats) {
2791 err = -ENOMEM;
2792 goto err_alloc_stats;
2793 }
2794
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002795 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2796 GFP_KERNEL);
2797 if (!mlxsw_sp_port->sample) {
2798 err = -ENOMEM;
2799 goto err_alloc_sample;
2800 }
2801
Nogah Frankel9deef432017-10-26 10:55:32 +02002802 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002803 &update_stats_cache);
2804
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002805 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2806 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2807
Ido Schimmel2e915e02017-06-08 08:47:45 +02002808 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
Ido Schimmel5b153852017-06-08 08:47:44 +02002809 if (err) {
2810 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2811 mlxsw_sp_port->local_port);
2812 goto err_port_module_map;
2813 }
2814
Ido Schimmel3247ff22016-09-08 08:16:02 +02002815 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2816 if (err) {
2817 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2818 mlxsw_sp_port->local_port);
2819 goto err_port_swid_set;
2820 }
2821
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002822 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2823 if (err) {
2824 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2825 mlxsw_sp_port->local_port);
2826 goto err_dev_addr_init;
2827 }
2828
2829 netif_carrier_off(dev);
2830
2831 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02002832 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2833 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002834
Jarod Wilsond894be52016-10-20 13:55:16 -04002835 dev->min_mtu = 0;
2836 dev->max_mtu = ETH_MAX_MTU;
2837
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002838 /* Each packet needs to have a Tx header (metadata) on top all other
2839 * headers.
2840 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02002841 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002842
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002843 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2844 if (err) {
2845 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2846 mlxsw_sp_port->local_port);
2847 goto err_port_system_port_mapping_set;
2848 }
2849
Ido Schimmel18f1e702016-02-26 17:32:31 +01002850 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2851 if (err) {
2852 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2853 mlxsw_sp_port->local_port);
2854 goto err_port_speed_by_width_set;
2855 }
2856
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002857 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2858 if (err) {
2859 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2860 mlxsw_sp_port->local_port);
2861 goto err_port_mtu_set;
2862 }
2863
2864 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2865 if (err)
2866 goto err_port_admin_status_set;
2867
2868 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2869 if (err) {
2870 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2871 mlxsw_sp_port->local_port);
2872 goto err_port_buffers_init;
2873 }
2874
Ido Schimmel90183b92016-04-06 17:10:08 +02002875 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2876 if (err) {
2877 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2878 mlxsw_sp_port->local_port);
2879 goto err_port_ets_init;
2880 }
2881
Ido Schimmelf00817d2016-04-06 17:10:09 +02002882 /* ETS and buffers must be initialized before DCB. */
2883 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2884 if (err) {
2885 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2886 mlxsw_sp_port->local_port);
2887 goto err_port_dcb_init;
2888 }
2889
Ido Schimmela1107482017-05-26 08:37:39 +02002890 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
Ido Schimmel45a4a162017-05-16 19:38:35 +02002891 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02002892 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
Ido Schimmel45a4a162017-05-16 19:38:35 +02002893 mlxsw_sp_port->local_port);
Ido Schimmela1107482017-05-26 08:37:39 +02002894 goto err_port_fids_init;
Ido Schimmel45a4a162017-05-16 19:38:35 +02002895 }
2896
Nogah Frankel371b4372018-01-10 14:59:57 +01002897 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
2898 if (err) {
2899 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
2900 mlxsw_sp_port->local_port);
2901 goto err_port_qdiscs_init;
2902 }
2903
Ido Schimmelc57529e2017-05-26 08:37:31 +02002904 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
2905 if (IS_ERR(mlxsw_sp_port_vlan)) {
2906 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
Ido Schimmel05978482016-08-17 16:39:30 +02002907 mlxsw_sp_port->local_port);
Wei Yongjund86fd112017-11-06 11:11:28 +00002908 err = PTR_ERR(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002909 goto err_port_vlan_get;
Ido Schimmel05978482016-08-17 16:39:30 +02002910 }
2911
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002912 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02002913 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002914 err = register_netdev(dev);
2915 if (err) {
2916 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2917 mlxsw_sp_port->local_port);
2918 goto err_register_netdev;
2919 }
2920
Elad Razd808c7e2016-10-28 21:35:57 +02002921 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2922 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2923 module);
Nogah Frankel9deef432017-10-26 10:55:32 +02002924 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002925 return 0;
2926
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002927err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02002928 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002929 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002930 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
2931err_port_vlan_get:
Nogah Frankel371b4372018-01-10 14:59:57 +01002932 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
2933err_port_qdiscs_init:
Ido Schimmela1107482017-05-26 08:37:39 +02002934 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
2935err_port_fids_init:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03002936 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002937err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02002938err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002939err_port_buffers_init:
2940err_port_admin_status_set:
2941err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01002942err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002943err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002944err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02002945 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2946err_port_swid_set:
Ido Schimmel2e915e02017-06-08 08:47:45 +02002947 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Ido Schimmel5b153852017-06-08 08:47:44 +02002948err_port_module_map:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002949 kfree(mlxsw_sp_port->sample);
2950err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002951 free_percpu(mlxsw_sp_port->pcpu_stats);
2952err_alloc_stats:
2953 free_netdev(dev);
Ido Schimmel5b153852017-06-08 08:47:44 +02002954err_alloc_etherdev:
Jiri Pirko67963a32016-10-28 21:35:55 +02002955 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2956 return err;
2957}
2958
Ido Schimmel5b153852017-06-08 08:47:44 +02002959static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002960{
2961 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2962
Nogah Frankel9deef432017-10-26 10:55:32 +02002963 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02002964 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002965 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02002966 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002967 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002968 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Nogah Frankel371b4372018-01-10 14:59:57 +01002969 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
Ido Schimmela1107482017-05-26 08:37:39 +02002970 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002971 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01002972 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
Ido Schimmel2e915e02017-06-08 08:47:45 +02002973 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002974 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01002975 free_percpu(mlxsw_sp_port->pcpu_stats);
Ido Schimmel31a08a52017-05-26 08:37:26 +02002976 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002977 free_netdev(mlxsw_sp_port->dev);
Jiri Pirko67963a32016-10-28 21:35:55 +02002978 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2979}
2980
Jiri Pirkof83e2102016-10-28 21:35:49 +02002981static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2982{
2983 return mlxsw_sp->ports[local_port] != NULL;
2984}
2985
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002986static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2987{
2988 int i;
2989
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002990 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002991 if (mlxsw_sp_port_created(mlxsw_sp, i))
2992 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002993 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002994 kfree(mlxsw_sp->ports);
2995}
2996
2997static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2998{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002999 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02003000 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003001 size_t alloc_size;
3002 int i;
3003 int err;
3004
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003005 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003006 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3007 if (!mlxsw_sp->ports)
3008 return -ENOMEM;
3009
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003010 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3011 GFP_KERNEL);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003012 if (!mlxsw_sp->port_to_module) {
3013 err = -ENOMEM;
3014 goto err_port_to_module_alloc;
3015 }
3016
3017 for (i = 1; i < max_ports; i++) {
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003018 /* Mark as invalid */
3019 mlxsw_sp->port_to_module[i] = -1;
3020
Ido Schimmel558c2d52016-02-26 17:32:29 +01003021 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003022 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01003023 if (err)
3024 goto err_port_module_info_get;
3025 if (!width)
3026 continue;
3027 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02003028 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3029 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003030 if (err)
3031 goto err_port_create;
3032 }
3033 return 0;
3034
3035err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01003036err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003037 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003038 if (mlxsw_sp_port_created(mlxsw_sp, i))
3039 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003040 kfree(mlxsw_sp->port_to_module);
3041err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003042 kfree(mlxsw_sp->ports);
3043 return err;
3044}
3045
Ido Schimmel18f1e702016-02-26 17:32:31 +01003046static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3047{
3048 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3049
3050 return local_port - offset;
3051}
3052
Ido Schimmelbe945352016-06-09 09:51:39 +02003053static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3054 u8 module, unsigned int count)
3055{
3056 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3057 int err, i;
3058
3059 for (i = 0; i < count; i++) {
Ido Schimmelbe945352016-06-09 09:51:39 +02003060 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02003061 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02003062 if (err)
3063 goto err_port_create;
3064 }
3065
3066 return 0;
3067
3068err_port_create:
3069 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003070 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3071 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02003072 return err;
3073}
3074
3075static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3076 u8 base_port, unsigned int count)
3077{
3078 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3079 int i;
3080
3081 /* Split by four means we need to re-create two ports, otherwise
3082 * only one.
3083 */
3084 count = count / 2;
3085
3086 for (i = 0; i < count; i++) {
3087 local_port = base_port + i * 2;
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003088 if (mlxsw_sp->port_to_module[local_port] < 0)
3089 continue;
Ido Schimmelbe945352016-06-09 09:51:39 +02003090 module = mlxsw_sp->port_to_module[local_port];
3091
Ido Schimmelbe945352016-06-09 09:51:39 +02003092 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003093 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003094 }
3095}
3096
Jiri Pirkob2f10572016-04-08 19:11:23 +02003097static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3098 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003099{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003100 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003101 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003102 u8 module, cur_width, base_port;
3103 int i;
3104 int err;
3105
3106 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3107 if (!mlxsw_sp_port) {
3108 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3109 local_port);
3110 return -EINVAL;
3111 }
3112
Ido Schimmeld664b412016-06-09 09:51:40 +02003113 module = mlxsw_sp_port->mapping.module;
3114 cur_width = mlxsw_sp_port->mapping.width;
3115
Ido Schimmel18f1e702016-02-26 17:32:31 +01003116 if (count != 2 && count != 4) {
3117 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3118 return -EINVAL;
3119 }
3120
Ido Schimmel18f1e702016-02-26 17:32:31 +01003121 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3122 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3123 return -EINVAL;
3124 }
3125
3126 /* Make sure we have enough slave (even) ports for the split. */
3127 if (count == 2) {
3128 base_port = local_port;
3129 if (mlxsw_sp->ports[base_port + 1]) {
3130 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3131 return -EINVAL;
3132 }
3133 } else {
3134 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3135 if (mlxsw_sp->ports[base_port + 1] ||
3136 mlxsw_sp->ports[base_port + 3]) {
3137 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3138 return -EINVAL;
3139 }
3140 }
3141
3142 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003143 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3144 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003145
Ido Schimmelbe945352016-06-09 09:51:39 +02003146 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3147 if (err) {
3148 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3149 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003150 }
3151
3152 return 0;
3153
Ido Schimmelbe945352016-06-09 09:51:39 +02003154err_port_split_create:
3155 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003156 return err;
3157}
3158
Jiri Pirkob2f10572016-04-08 19:11:23 +02003159static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003160{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003161 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003162 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003163 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003164 unsigned int count;
3165 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003166
3167 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3168 if (!mlxsw_sp_port) {
3169 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3170 local_port);
3171 return -EINVAL;
3172 }
3173
3174 if (!mlxsw_sp_port->split) {
3175 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3176 return -EINVAL;
3177 }
3178
Ido Schimmeld664b412016-06-09 09:51:40 +02003179 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003180 count = cur_width == 1 ? 4 : 2;
3181
3182 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3183
3184 /* Determine which ports to remove. */
3185 if (count == 2 && local_port >= base_port + 2)
3186 base_port = base_port + 2;
3187
3188 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003189 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3190 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003191
Ido Schimmelbe945352016-06-09 09:51:39 +02003192 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003193
3194 return 0;
3195}
3196
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003197static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3198 char *pude_pl, void *priv)
3199{
3200 struct mlxsw_sp *mlxsw_sp = priv;
3201 struct mlxsw_sp_port *mlxsw_sp_port;
3202 enum mlxsw_reg_pude_oper_status status;
3203 u8 local_port;
3204
3205 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3206 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003207 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003208 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003209
3210 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3211 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3212 netdev_info(mlxsw_sp_port->dev, "link up\n");
3213 netif_carrier_on(mlxsw_sp_port->dev);
3214 } else {
3215 netdev_info(mlxsw_sp_port->dev, "link down\n");
3216 netif_carrier_off(mlxsw_sp_port->dev);
3217 }
3218}
3219
Nogah Frankel14eeda92016-11-25 10:33:32 +01003220static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3221 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003222{
3223 struct mlxsw_sp *mlxsw_sp = priv;
3224 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3225 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3226
3227 if (unlikely(!mlxsw_sp_port)) {
3228 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3229 local_port);
3230 return;
3231 }
3232
3233 skb->dev = mlxsw_sp_port->dev;
3234
3235 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3236 u64_stats_update_begin(&pcpu_stats->syncp);
3237 pcpu_stats->rx_packets++;
3238 pcpu_stats->rx_bytes += skb->len;
3239 u64_stats_update_end(&pcpu_stats->syncp);
3240
3241 skb->protocol = eth_type_trans(skb, skb->dev);
3242 netif_receive_skb(skb);
3243}
3244
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003245static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3246 void *priv)
3247{
3248 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003249 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003250}
3251
Yotam Gigia0040c82017-10-03 09:58:10 +02003252static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3253 u8 local_port, void *priv)
3254{
3255 skb->offload_mr_fwd_mark = 1;
3256 skb->offload_fwd_mark = 1;
3257 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3258}
3259
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003260static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3261 void *priv)
3262{
3263 struct mlxsw_sp *mlxsw_sp = priv;
3264 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3265 struct psample_group *psample_group;
3266 u32 size;
3267
3268 if (unlikely(!mlxsw_sp_port)) {
3269 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3270 local_port);
3271 goto out;
3272 }
3273 if (unlikely(!mlxsw_sp_port->sample)) {
3274 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3275 local_port);
3276 goto out;
3277 }
3278
3279 size = mlxsw_sp_port->sample->truncate ?
3280 mlxsw_sp_port->sample->trunc_size : skb->len;
3281
3282 rcu_read_lock();
3283 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3284 if (!psample_group)
3285 goto out_unlock;
3286 psample_sample_packet(psample_group, skb, size,
3287 mlxsw_sp_port->dev->ifindex, 0,
3288 mlxsw_sp_port->sample->rate);
3289out_unlock:
3290 rcu_read_unlock();
3291out:
3292 consume_skb(skb);
3293}
3294
Nogah Frankel117b0da2016-11-25 10:33:44 +01003295#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003296 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003297 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003298
Nogah Frankel117b0da2016-11-25 10:33:44 +01003299#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003300 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003301 _is_ctrl, SP_##_trap_group, DISCARD)
3302
Yotam Gigia0040c82017-10-03 09:58:10 +02003303#define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3304 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3305 _is_ctrl, SP_##_trap_group, DISCARD)
3306
Nogah Frankel117b0da2016-11-25 10:33:44 +01003307#define MLXSW_SP_EVENTL(_func, _trap_id) \
3308 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003309
Nogah Frankel45449132016-11-25 10:33:35 +01003310static const struct mlxsw_listener mlxsw_sp_listener[] = {
3311 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003312 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003313 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003314 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3315 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3316 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3317 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3318 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3319 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3320 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3321 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3322 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3323 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3324 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003325 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003326 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3327 false),
3328 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3329 false),
3330 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3331 false),
3332 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3333 false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003334 /* L3 traps */
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003335 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3336 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3337 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003338 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003339 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3340 false),
3341 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3342 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3343 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3344 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3345 false),
3346 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3347 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3348 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003349 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003350 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3351 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3352 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3353 false),
3354 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3355 false),
3356 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3357 false),
3358 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3359 false),
3360 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3361 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3362 false),
3363 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3364 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
Ido Schimmel7607dd32017-07-17 14:15:30 +02003365 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003366 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
Petr Machata86484de2017-09-02 23:49:27 +02003367 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003368 /* PKT Sample trap */
3369 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
Jiri Pirko0db7b382017-06-06 14:12:05 +02003370 false, SP_IP2ME, DISCARD),
3371 /* ACL trap */
3372 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
Yotam Gigib48cfc82017-09-19 10:00:20 +02003373 /* Multicast Router Traps */
3374 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3375 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3376 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
Yotam Gigia0040c82017-10-03 09:58:10 +02003377 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003378};
3379
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003380static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3381{
3382 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3383 enum mlxsw_reg_qpcr_ir_units ir_units;
3384 int max_cpu_policers;
3385 bool is_bytes;
3386 u8 burst_size;
3387 u32 rate;
3388 int i, err;
3389
3390 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3391 return -EIO;
3392
3393 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3394
3395 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3396 for (i = 0; i < max_cpu_policers; i++) {
3397 is_bytes = false;
3398 switch (i) {
3399 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3400 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3401 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3402 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003403 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3404 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003405 rate = 128;
3406 burst_size = 7;
3407 break;
3408 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003409 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003410 rate = 16 * 1024;
3411 burst_size = 10;
3412 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003413 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003414 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3415 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003416 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003417 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3418 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003419 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003420 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003421 rate = 1024;
3422 burst_size = 7;
3423 break;
3424 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3425 is_bytes = true;
3426 rate = 4 * 1024;
3427 burst_size = 4;
3428 break;
3429 default:
3430 continue;
3431 }
3432
3433 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3434 burst_size);
3435 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3436 if (err)
3437 return err;
3438 }
3439
3440 return 0;
3441}
3442
Nogah Frankel579c82e2016-11-25 10:33:42 +01003443static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003444{
3445 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003446 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003447 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003448 int max_trap_groups;
3449 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003450 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003451 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003452
3453 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3454 return -EIO;
3455
3456 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003457 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003458
3459 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003460 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003461 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003462 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3463 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3464 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3465 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003466 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003467 priority = 5;
3468 tc = 5;
3469 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003470 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003471 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3472 priority = 4;
3473 tc = 4;
3474 break;
3475 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3476 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003477 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003478 priority = 3;
3479 tc = 3;
3480 break;
3481 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003482 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003483 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003484 priority = 2;
3485 tc = 2;
3486 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003487 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003488 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3489 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003490 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003491 priority = 1;
3492 tc = 1;
3493 break;
3494 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003495 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3496 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003497 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003498 break;
3499 default:
3500 continue;
3501 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003502
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003503 if (max_cpu_policers <= policer_id &&
3504 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3505 return -EIO;
3506
3507 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003508 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3509 if (err)
3510 return err;
3511 }
3512
3513 return 0;
3514}
3515
3516static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3517{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003518 int i;
3519 int err;
3520
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003521 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3522 if (err)
3523 return err;
3524
Nogah Frankel579c82e2016-11-25 10:33:42 +01003525 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003526 if (err)
3527 return err;
3528
Nogah Frankel45449132016-11-25 10:33:35 +01003529 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003530 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003531 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003532 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003533 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003534 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003535
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003536 }
3537 return 0;
3538
Nogah Frankel45449132016-11-25 10:33:35 +01003539err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003540 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003541 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003542 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003543 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003544 }
3545 return err;
3546}
3547
3548static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3549{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003550 int i;
3551
Nogah Frankel45449132016-11-25 10:33:35 +01003552 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003553 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003554 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003555 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003556 }
3557}
3558
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003559static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3560{
3561 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003562 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003563
3564 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3565 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3566 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3567 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3568 MLXSW_REG_SLCR_LAG_HASH_SIP |
3569 MLXSW_REG_SLCR_LAG_HASH_DIP |
3570 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3571 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3572 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003573 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3574 if (err)
3575 return err;
3576
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003577 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3578 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003579 return -EIO;
3580
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003581 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003582 sizeof(struct mlxsw_sp_upper),
3583 GFP_KERNEL);
3584 if (!mlxsw_sp->lags)
3585 return -ENOMEM;
3586
3587 return 0;
3588}
3589
3590static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3591{
3592 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003593}
3594
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003595static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3596{
3597 char htgt_pl[MLXSW_REG_HTGT_LEN];
3598
Nogah Frankel579c82e2016-11-25 10:33:42 +01003599 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3600 MLXSW_REG_HTGT_INVALID_POLICER,
3601 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3602 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003603 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3604}
3605
Petr Machatac30f5d02017-10-16 16:26:35 +02003606static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3607 unsigned long event, void *ptr);
3608
Jiri Pirkob2f10572016-04-08 19:11:23 +02003609static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003610 const struct mlxsw_bus_info *mlxsw_bus_info)
3611{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003612 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003613 int err;
3614
3615 mlxsw_sp->core = mlxsw_core;
3616 mlxsw_sp->bus_info = mlxsw_bus_info;
3617
Yotam Gigi6b742192017-05-23 21:56:29 +02003618 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3619 if (err) {
3620 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3621 return err;
3622 }
3623
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003624 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3625 if (err) {
3626 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3627 return err;
3628 }
3629
Ido Schimmela875a2e2017-10-22 23:11:44 +02003630 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3631 if (err) {
3632 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3633 return err;
3634 }
3635
Ido Schimmela1107482017-05-26 08:37:39 +02003636 err = mlxsw_sp_fids_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003637 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003638 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
Ido Schimmela875a2e2017-10-22 23:11:44 +02003639 goto err_fids_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003640 }
3641
Ido Schimmela1107482017-05-26 08:37:39 +02003642 err = mlxsw_sp_traps_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003643 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003644 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3645 goto err_traps_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003646 }
3647
3648 err = mlxsw_sp_buffers_init(mlxsw_sp);
3649 if (err) {
3650 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3651 goto err_buffers_init;
3652 }
3653
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003654 err = mlxsw_sp_lag_init(mlxsw_sp);
3655 if (err) {
3656 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3657 goto err_lag_init;
3658 }
3659
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003660 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3661 if (err) {
3662 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3663 goto err_switchdev_init;
3664 }
3665
Yotam Gigie2b2d352017-09-19 10:00:08 +02003666 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3667 if (err) {
3668 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3669 goto err_counter_pool_init;
3670 }
3671
Yotam Gigid3b939b2017-09-19 10:00:09 +02003672 err = mlxsw_sp_afa_init(mlxsw_sp);
3673 if (err) {
3674 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3675 goto err_afa_init;
3676 }
3677
Ido Schimmel464dce12016-07-02 11:00:15 +02003678 err = mlxsw_sp_router_init(mlxsw_sp);
3679 if (err) {
3680 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3681 goto err_router_init;
3682 }
3683
Petr Machatac30f5d02017-10-16 16:26:35 +02003684 /* Initialize netdevice notifier after router is initialized, so that
3685 * the event handler can use router structures.
3686 */
3687 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3688 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3689 if (err) {
3690 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3691 goto err_netdev_notifier;
3692 }
3693
Yotam Gigi763b4b72016-07-21 12:03:17 +02003694 err = mlxsw_sp_span_init(mlxsw_sp);
3695 if (err) {
3696 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3697 goto err_span_init;
3698 }
3699
Jiri Pirko22a67762017-02-03 10:29:07 +01003700 err = mlxsw_sp_acl_init(mlxsw_sp);
3701 if (err) {
3702 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3703 goto err_acl_init;
3704 }
3705
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003706 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3707 if (err) {
3708 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3709 goto err_dpipe_init;
3710 }
3711
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003712 err = mlxsw_sp_ports_create(mlxsw_sp);
3713 if (err) {
3714 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3715 goto err_ports_create;
3716 }
3717
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003718 return 0;
3719
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003720err_ports_create:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003721 mlxsw_sp_dpipe_fini(mlxsw_sp);
3722err_dpipe_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01003723 mlxsw_sp_acl_fini(mlxsw_sp);
3724err_acl_init:
Yotam Gigi763b4b72016-07-21 12:03:17 +02003725 mlxsw_sp_span_fini(mlxsw_sp);
3726err_span_init:
Petr Machatac30f5d02017-10-16 16:26:35 +02003727 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3728err_netdev_notifier:
Ido Schimmel464dce12016-07-02 11:00:15 +02003729 mlxsw_sp_router_fini(mlxsw_sp);
3730err_router_init:
Yotam Gigid3b939b2017-09-19 10:00:09 +02003731 mlxsw_sp_afa_fini(mlxsw_sp);
3732err_afa_init:
Yotam Gigie2b2d352017-09-19 10:00:08 +02003733 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3734err_counter_pool_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003735 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003736err_switchdev_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003737 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003738err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02003739 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003740err_buffers_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003741 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003742err_traps_init:
3743 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003744err_fids_init:
3745 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003746 return err;
3747}
3748
Jiri Pirkob2f10572016-04-08 19:11:23 +02003749static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003750{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003751 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003752
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003753 mlxsw_sp_ports_remove(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003754 mlxsw_sp_dpipe_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01003755 mlxsw_sp_acl_fini(mlxsw_sp);
Yotam Gigi763b4b72016-07-21 12:03:17 +02003756 mlxsw_sp_span_fini(mlxsw_sp);
Petr Machatac30f5d02017-10-16 16:26:35 +02003757 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
Ido Schimmel464dce12016-07-02 11:00:15 +02003758 mlxsw_sp_router_fini(mlxsw_sp);
Yotam Gigid3b939b2017-09-19 10:00:09 +02003759 mlxsw_sp_afa_fini(mlxsw_sp);
Yotam Gigie2b2d352017-09-19 10:00:08 +02003760 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003761 mlxsw_sp_switchdev_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003762 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02003763 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003764 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003765 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003766 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003767}
3768
Bhumika Goyal159fe882017-08-11 19:10:42 +05303769static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003770 .used_max_vepa_channels = 1,
3771 .max_vepa_channels = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003772 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01003773 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003774 .used_max_pgt = 1,
3775 .max_pgt = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003776 .used_flood_tables = 1,
3777 .used_flood_mode = 1,
3778 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003779 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003780 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003781 .max_fid_flood_tables = 3,
Ido Schimmela1107482017-05-26 08:37:39 +02003782 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003783 .used_max_ib_mc = 1,
3784 .max_ib_mc = 0,
3785 .used_max_pkey = 1,
3786 .max_pkey = 0,
Nogah Frankel403547d2016-09-20 11:16:52 +02003787 .used_kvd_split_data = 1,
3788 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
Ido Schimmelf11fbaf2017-10-22 23:11:49 +02003789 .kvd_hash_single_parts = 59,
3790 .kvd_hash_double_parts = 41,
Jiri Pirkoc6022422016-07-05 11:27:46 +02003791 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003792 .swid_config = {
3793 {
3794 .used_type = 1,
3795 .type = MLXSW_PORT_SWID_TYPE_ETH,
3796 }
3797 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02003798 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003799};
3800
Arkadi Sharshevskyafadc262018-01-15 08:59:09 +01003801static u64 mlxsw_sp_resource_kvd_linear_occ_get(struct devlink *devlink)
3802{
3803 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
3804 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3805
3806 return mlxsw_sp_kvdl_occ_get(mlxsw_sp);
3807}
3808
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003809static struct devlink_resource_ops mlxsw_sp_resource_kvd_linear_ops = {
Arkadi Sharshevskyafadc262018-01-15 08:59:09 +01003810 .occ_get = mlxsw_sp_resource_kvd_linear_occ_get,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003811};
3812
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003813static struct devlink_resource_size_params mlxsw_sp_kvd_size_params;
3814static struct devlink_resource_size_params mlxsw_sp_linear_size_params;
3815static struct devlink_resource_size_params mlxsw_sp_hash_single_size_params;
3816static struct devlink_resource_size_params mlxsw_sp_hash_double_size_params;
3817
3818static void
3819mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core)
3820{
3821 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3822 KVD_SINGLE_MIN_SIZE);
3823 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3824 KVD_DOUBLE_MIN_SIZE);
3825 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3826 u32 linear_size_min = 0;
3827
3828 /* KVD top resource */
3829 mlxsw_sp_kvd_size_params.size_min = kvd_size;
3830 mlxsw_sp_kvd_size_params.size_max = kvd_size;
3831 mlxsw_sp_kvd_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
3832 mlxsw_sp_kvd_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
3833
3834 /* Linear part init */
3835 mlxsw_sp_linear_size_params.size_min = linear_size_min;
3836 mlxsw_sp_linear_size_params.size_max = kvd_size - single_size_min -
3837 double_size_min;
3838 mlxsw_sp_linear_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
3839 mlxsw_sp_linear_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
3840
3841 /* Hash double part init */
3842 mlxsw_sp_hash_double_size_params.size_min = double_size_min;
3843 mlxsw_sp_hash_double_size_params.size_max = kvd_size - single_size_min -
3844 linear_size_min;
3845 mlxsw_sp_hash_double_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
3846 mlxsw_sp_hash_double_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
3847
3848 /* Hash single part init */
3849 mlxsw_sp_hash_single_size_params.size_min = single_size_min;
3850 mlxsw_sp_hash_single_size_params.size_max = kvd_size - double_size_min -
3851 linear_size_min;
3852 mlxsw_sp_hash_single_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
3853 mlxsw_sp_hash_single_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
3854}
3855
3856static int mlxsw_sp_resources_register(struct mlxsw_core *mlxsw_core)
3857{
3858 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3859 u32 kvd_size, single_size, double_size, linear_size;
3860 const struct mlxsw_config_profile *profile;
3861 int err;
3862
3863 profile = &mlxsw_sp_config_profile;
3864 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
3865 return -EIO;
3866
3867 mlxsw_sp_resource_size_params_prepare(mlxsw_core);
3868 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3869 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
3870 true, kvd_size,
3871 MLXSW_SP_RESOURCE_KVD,
3872 DEVLINK_RESOURCE_ID_PARENT_TOP,
3873 &mlxsw_sp_kvd_size_params,
Arkadi Sharshevsky4f4bbf72018-02-20 08:44:21 +01003874 NULL);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003875 if (err)
3876 return err;
3877
3878 linear_size = profile->kvd_linear_size;
3879 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
3880 false, linear_size,
3881 MLXSW_SP_RESOURCE_KVD_LINEAR,
3882 MLXSW_SP_RESOURCE_KVD,
3883 &mlxsw_sp_linear_size_params,
3884 &mlxsw_sp_resource_kvd_linear_ops);
3885 if (err)
3886 return err;
3887
Arkadi Sharshevsky51d3c082018-02-20 08:44:22 +01003888 err = mlxsw_sp_kvdl_resources_register(devlink);
3889 if (err)
3890 return err;
3891
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003892 double_size = kvd_size - linear_size;
3893 double_size *= profile->kvd_hash_double_parts;
3894 double_size /= profile->kvd_hash_double_parts +
3895 profile->kvd_hash_single_parts;
3896 double_size = rounddown(double_size, profile->kvd_hash_granularity);
3897 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
3898 false, double_size,
3899 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3900 MLXSW_SP_RESOURCE_KVD,
3901 &mlxsw_sp_hash_double_size_params,
Arkadi Sharshevsky4f4bbf72018-02-20 08:44:21 +01003902 NULL);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003903 if (err)
3904 return err;
3905
3906 single_size = kvd_size - double_size - linear_size;
3907 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
3908 false, single_size,
3909 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3910 MLXSW_SP_RESOURCE_KVD,
3911 &mlxsw_sp_hash_single_size_params,
Arkadi Sharshevsky4f4bbf72018-02-20 08:44:21 +01003912 NULL);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003913 if (err)
3914 return err;
3915
3916 return 0;
3917}
3918
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01003919static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
3920 const struct mlxsw_config_profile *profile,
3921 u64 *p_single_size, u64 *p_double_size,
3922 u64 *p_linear_size)
3923{
3924 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3925 u32 double_size;
3926 int err;
3927
3928 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3929 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
3930 !profile->used_kvd_split_data)
3931 return -EIO;
3932
3933 /* The hash part is what left of the kvd without the
3934 * linear part. It is split to the single size and
3935 * double size by the parts ratio from the profile.
3936 * Both sizes must be a multiplications of the
3937 * granularity from the profile. In case the user
3938 * provided the sizes they are obtained via devlink.
3939 */
3940 err = devlink_resource_size_get(devlink,
3941 MLXSW_SP_RESOURCE_KVD_LINEAR,
3942 p_linear_size);
3943 if (err)
3944 *p_linear_size = profile->kvd_linear_size;
3945
3946 err = devlink_resource_size_get(devlink,
3947 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3948 p_double_size);
3949 if (err) {
3950 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3951 *p_linear_size;
3952 double_size *= profile->kvd_hash_double_parts;
3953 double_size /= profile->kvd_hash_double_parts +
3954 profile->kvd_hash_single_parts;
3955 *p_double_size = rounddown(double_size,
3956 profile->kvd_hash_granularity);
3957 }
3958
3959 err = devlink_resource_size_get(devlink,
3960 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3961 p_single_size);
3962 if (err)
3963 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3964 *p_double_size - *p_linear_size;
3965
3966 /* Check results are legal. */
3967 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3968 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
3969 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
3970 return -EIO;
3971
3972 return 0;
3973}
3974
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003975static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02003976 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003977 .priv_size = sizeof(struct mlxsw_sp),
3978 .init = mlxsw_sp_init,
3979 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003980 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003981 .port_split = mlxsw_sp_port_split,
3982 .port_unsplit = mlxsw_sp_port_unsplit,
3983 .sb_pool_get = mlxsw_sp_sb_pool_get,
3984 .sb_pool_set = mlxsw_sp_sb_pool_set,
3985 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3986 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3987 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3988 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3989 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3990 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3991 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3992 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3993 .txhdr_construct = mlxsw_sp_txhdr_construct,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003994 .resources_register = mlxsw_sp_resources_register,
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01003995 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003996 .txhdr_len = MLXSW_TXHDR_LEN,
3997 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003998};
3999
Jiri Pirko22a67762017-02-03 10:29:07 +01004000bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004001{
4002 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4003}
4004
Jiri Pirko1182e532017-03-06 21:25:20 +01004005static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07004006{
Jiri Pirko1182e532017-03-06 21:25:20 +01004007 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07004008 int ret = 0;
4009
4010 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01004011 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07004012 ret = 1;
4013 }
4014
4015 return ret;
4016}
4017
Ido Schimmelc57529e2017-05-26 08:37:31 +02004018struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004019{
Jiri Pirko1182e532017-03-06 21:25:20 +01004020 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004021
4022 if (mlxsw_sp_port_dev_check(dev))
4023 return netdev_priv(dev);
4024
Jiri Pirko1182e532017-03-06 21:25:20 +01004025 mlxsw_sp_port = NULL;
4026 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004027
Jiri Pirko1182e532017-03-06 21:25:20 +01004028 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004029}
4030
Ido Schimmel4724ba562017-03-10 08:53:39 +01004031struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004032{
4033 struct mlxsw_sp_port *mlxsw_sp_port;
4034
4035 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4036 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4037}
4038
Arkadi Sharshevskyaf0613782017-06-08 08:44:20 +02004039struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004040{
Jiri Pirko1182e532017-03-06 21:25:20 +01004041 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004042
4043 if (mlxsw_sp_port_dev_check(dev))
4044 return netdev_priv(dev);
4045
Jiri Pirko1182e532017-03-06 21:25:20 +01004046 mlxsw_sp_port = NULL;
4047 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4048 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004049
Jiri Pirko1182e532017-03-06 21:25:20 +01004050 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004051}
4052
4053struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4054{
4055 struct mlxsw_sp_port *mlxsw_sp_port;
4056
4057 rcu_read_lock();
4058 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4059 if (mlxsw_sp_port)
4060 dev_hold(mlxsw_sp_port->dev);
4061 rcu_read_unlock();
4062 return mlxsw_sp_port;
4063}
4064
4065void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4066{
4067 dev_put(mlxsw_sp_port->dev);
4068}
4069
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004070static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004071{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004072 char sldr_pl[MLXSW_REG_SLDR_LEN];
4073
4074 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4075 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4076}
4077
4078static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4079{
4080 char sldr_pl[MLXSW_REG_SLDR_LEN];
4081
4082 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4083 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4084}
4085
4086static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4087 u16 lag_id, u8 port_index)
4088{
4089 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4090 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4091
4092 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4093 lag_id, port_index);
4094 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4095}
4096
4097static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4098 u16 lag_id)
4099{
4100 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4101 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4102
4103 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4104 lag_id);
4105 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4106}
4107
4108static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4109 u16 lag_id)
4110{
4111 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4112 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4113
4114 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4115 lag_id);
4116 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4117}
4118
4119static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4120 u16 lag_id)
4121{
4122 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4123 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4124
4125 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4126 lag_id);
4127 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4128}
4129
4130static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4131 struct net_device *lag_dev,
4132 u16 *p_lag_id)
4133{
4134 struct mlxsw_sp_upper *lag;
4135 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004136 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004137 int i;
4138
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004139 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4140 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004141 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4142 if (lag->ref_count) {
4143 if (lag->dev == lag_dev) {
4144 *p_lag_id = i;
4145 return 0;
4146 }
4147 } else if (free_lag_id < 0) {
4148 free_lag_id = i;
4149 }
4150 }
4151 if (free_lag_id < 0)
4152 return -EBUSY;
4153 *p_lag_id = free_lag_id;
4154 return 0;
4155}
4156
4157static bool
4158mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4159 struct net_device *lag_dev,
David Aherne58376e2017-10-04 17:48:51 -07004160 struct netdev_lag_upper_info *lag_upper_info,
4161 struct netlink_ext_ack *extack)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004162{
4163 u16 lag_id;
4164
David Aherne58376e2017-10-04 17:48:51 -07004165 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004166 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004167 return false;
David Aherne58376e2017-10-04 17:48:51 -07004168 }
4169 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004170 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004171 return false;
David Aherne58376e2017-10-04 17:48:51 -07004172 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004173 return true;
4174}
4175
4176static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4177 u16 lag_id, u8 *p_port_index)
4178{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004179 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004180 int i;
4181
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004182 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4183 MAX_LAG_MEMBERS);
4184 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004185 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4186 *p_port_index = i;
4187 return 0;
4188 }
4189 }
4190 return -EBUSY;
4191}
4192
4193static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4194 struct net_device *lag_dev)
4195{
4196 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004197 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004198 struct mlxsw_sp_upper *lag;
4199 u16 lag_id;
4200 u8 port_index;
4201 int err;
4202
4203 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4204 if (err)
4205 return err;
4206 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4207 if (!lag->ref_count) {
4208 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4209 if (err)
4210 return err;
4211 lag->dev = lag_dev;
4212 }
4213
4214 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4215 if (err)
4216 return err;
4217 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4218 if (err)
4219 goto err_col_port_add;
4220 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4221 if (err)
4222 goto err_col_port_enable;
4223
4224 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4225 mlxsw_sp_port->local_port);
4226 mlxsw_sp_port->lag_id = lag_id;
4227 mlxsw_sp_port->lagged = 1;
4228 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004229
Ido Schimmelc57529e2017-05-26 08:37:31 +02004230 /* Port is no longer usable as a router interface */
4231 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4232 if (mlxsw_sp_port_vlan->fid)
Ido Schimmela1107482017-05-26 08:37:39 +02004233 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004234
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004235 return 0;
4236
Ido Schimmel51554db2016-05-06 22:18:39 +02004237err_col_port_enable:
4238 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004239err_col_port_add:
4240 if (!lag->ref_count)
4241 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004242 return err;
4243}
4244
Ido Schimmel82e6db02016-06-20 23:04:04 +02004245static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4246 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004247{
4248 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004249 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004250 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004251
4252 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004253 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004254 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4255 WARN_ON(lag->ref_count == 0);
4256
Ido Schimmel82e6db02016-06-20 23:04:04 +02004257 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4258 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004259
Ido Schimmelc57529e2017-05-26 08:37:31 +02004260 /* Any VLANs configured on the port are no longer valid */
4261 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004262
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004263 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004264 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004265
4266 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4267 mlxsw_sp_port->local_port);
4268 mlxsw_sp_port->lagged = 0;
4269 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004270
Ido Schimmelc57529e2017-05-26 08:37:31 +02004271 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4272 /* Make sure untagged frames are allowed to ingress */
4273 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004274}
4275
Jiri Pirko74581202015-12-03 12:12:30 +01004276static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4277 u16 lag_id)
4278{
4279 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4280 char sldr_pl[MLXSW_REG_SLDR_LEN];
4281
4282 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4283 mlxsw_sp_port->local_port);
4284 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4285}
4286
4287static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4288 u16 lag_id)
4289{
4290 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4291 char sldr_pl[MLXSW_REG_SLDR_LEN];
4292
4293 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4294 mlxsw_sp_port->local_port);
4295 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4296}
4297
4298static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4299 bool lag_tx_enabled)
4300{
4301 if (lag_tx_enabled)
4302 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4303 mlxsw_sp_port->lag_id);
4304 else
4305 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4306 mlxsw_sp_port->lag_id);
4307}
4308
4309static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4310 struct netdev_lag_lower_state_info *info)
4311{
4312 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4313}
4314
Jiri Pirko2b94e582017-04-18 16:55:37 +02004315static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4316 bool enable)
4317{
4318 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4319 enum mlxsw_reg_spms_state spms_state;
4320 char *spms_pl;
4321 u16 vid;
4322 int err;
4323
4324 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4325 MLXSW_REG_SPMS_STATE_DISCARDING;
4326
4327 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4328 if (!spms_pl)
4329 return -ENOMEM;
4330 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4331
4332 for (vid = 0; vid < VLAN_N_VID; vid++)
4333 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4334
4335 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4336 kfree(spms_pl);
4337 return err;
4338}
4339
4340static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4341{
Yuval Mintzfccff082017-12-15 08:44:21 +01004342 u16 vid = 1;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004343 int err;
4344
Ido Schimmel4aafc362017-05-26 08:37:25 +02004345 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004346 if (err)
4347 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02004348 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4349 if (err)
4350 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004351 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4352 true, false);
4353 if (err)
4354 goto err_port_vlan_set;
Yuval Mintzfccff082017-12-15 08:44:21 +01004355
4356 for (; vid <= VLAN_N_VID - 1; vid++) {
4357 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4358 vid, false);
4359 if (err)
4360 goto err_vid_learning_set;
4361 }
4362
Jiri Pirko2b94e582017-04-18 16:55:37 +02004363 return 0;
4364
Yuval Mintzfccff082017-12-15 08:44:21 +01004365err_vid_learning_set:
4366 for (vid--; vid >= 1; vid--)
4367 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004368err_port_vlan_set:
4369 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004370err_port_stp_set:
4371 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004372 return err;
4373}
4374
4375static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4376{
Yuval Mintzfccff082017-12-15 08:44:21 +01004377 u16 vid;
4378
4379 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4380 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4381 vid, true);
4382
Jiri Pirko2b94e582017-04-18 16:55:37 +02004383 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4384 false, false);
4385 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004386 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004387}
4388
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004389static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4390 struct net_device *dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004391 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004392{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004393 struct netdev_notifier_changeupper_info *info;
4394 struct mlxsw_sp_port *mlxsw_sp_port;
David Aherne58376e2017-10-04 17:48:51 -07004395 struct netlink_ext_ack *extack;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004396 struct net_device *upper_dev;
4397 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004398 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004399
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004400 mlxsw_sp_port = netdev_priv(dev);
4401 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4402 info = ptr;
David Aherne58376e2017-10-04 17:48:51 -07004403 extack = netdev_notifier_info_to_extack(&info->info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004404
4405 switch (event) {
4406 case NETDEV_PRECHANGEUPPER:
4407 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004408 if (!is_vlan_dev(upper_dev) &&
4409 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004410 !netif_is_bridge_master(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004411 !netif_is_ovs_master(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004412 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004413 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004414 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004415 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004416 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004417 if (netdev_has_any_upper_dev(upper_dev) &&
4418 (!netif_is_bridge_master(upper_dev) ||
4419 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4420 upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004421 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004422 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004423 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004424 if (netif_is_lag_master(upper_dev) &&
4425 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
David Aherne58376e2017-10-04 17:48:51 -07004426 info->upper_info, extack))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004427 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004428 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004429 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004430 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004431 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004432 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004433 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004434 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004435 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004436 }
4437 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004438 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004439 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004440 }
4441 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004442 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004443 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004444 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004445 break;
4446 case NETDEV_CHANGEUPPER:
4447 upper_dev = info->upper_dev;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004448 if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004449 if (info->linking)
4450 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004451 lower_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004452 upper_dev,
4453 extack);
Ido Schimmel7117a572016-06-20 23:04:06 +02004454 else
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004455 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4456 lower_dev,
4457 upper_dev);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004458 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004459 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004460 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4461 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004462 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004463 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4464 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004465 } else if (netif_is_ovs_master(upper_dev)) {
4466 if (info->linking)
4467 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4468 else
4469 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004470 }
4471 break;
4472 }
4473
Ido Schimmel80bedf12016-06-20 23:03:59 +02004474 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004475}
4476
Jiri Pirko74581202015-12-03 12:12:30 +01004477static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4478 unsigned long event, void *ptr)
4479{
4480 struct netdev_notifier_changelowerstate_info *info;
4481 struct mlxsw_sp_port *mlxsw_sp_port;
4482 int err;
4483
4484 mlxsw_sp_port = netdev_priv(dev);
4485 info = ptr;
4486
4487 switch (event) {
4488 case NETDEV_CHANGELOWERSTATE:
4489 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4490 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4491 info->lower_state_info);
4492 if (err)
4493 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4494 }
4495 break;
4496 }
4497
Ido Schimmel80bedf12016-06-20 23:03:59 +02004498 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004499}
4500
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004501static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4502 struct net_device *port_dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004503 unsigned long event, void *ptr)
4504{
4505 switch (event) {
4506 case NETDEV_PRECHANGEUPPER:
4507 case NETDEV_CHANGEUPPER:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004508 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4509 event, ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004510 case NETDEV_CHANGELOWERSTATE:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004511 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4512 ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004513 }
4514
Ido Schimmel80bedf12016-06-20 23:03:59 +02004515 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004516}
4517
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004518static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4519 unsigned long event, void *ptr)
4520{
4521 struct net_device *dev;
4522 struct list_head *iter;
4523 int ret;
4524
4525 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4526 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004527 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4528 ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004529 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004530 return ret;
4531 }
4532 }
4533
Ido Schimmel80bedf12016-06-20 23:03:59 +02004534 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004535}
4536
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004537static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4538 struct net_device *dev,
4539 unsigned long event, void *ptr,
4540 u16 vid)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004541{
4542 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel90045fc2017-12-25 09:05:33 +01004543 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004544 struct netdev_notifier_changeupper_info *info = ptr;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004545 struct netlink_ext_ack *extack;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004546 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004547 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004548
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004549 extack = netdev_notifier_info_to_extack(&info->info);
4550
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004551 switch (event) {
4552 case NETDEV_PRECHANGEUPPER:
4553 upper_dev = info->upper_dev;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004554 if (!netif_is_bridge_master(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004555 NL_SET_ERR_MSG_MOD(extack, "VLAN devices only support bridge and VRF uppers");
Ido Schimmel80bedf12016-06-20 23:03:59 +02004556 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004557 }
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004558 if (!info->linking)
4559 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004560 if (netdev_has_any_upper_dev(upper_dev) &&
4561 (!netif_is_bridge_master(upper_dev) ||
4562 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4563 upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004564 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004565 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004566 }
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004567 break;
4568 case NETDEV_CHANGEUPPER:
4569 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004570 if (netif_is_bridge_master(upper_dev)) {
4571 if (info->linking)
Ido Schimmelc57529e2017-05-26 08:37:31 +02004572 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4573 vlan_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004574 upper_dev,
4575 extack);
Ido Schimmel1f880612017-03-10 08:53:35 +01004576 else
Ido Schimmelc57529e2017-05-26 08:37:31 +02004577 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4578 vlan_dev,
4579 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004580 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004581 err = -EINVAL;
4582 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004583 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004584 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004585 }
4586
Ido Schimmel80bedf12016-06-20 23:03:59 +02004587 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004588}
4589
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004590static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4591 struct net_device *lag_dev,
4592 unsigned long event,
4593 void *ptr, u16 vid)
Ido Schimmel272c4472015-12-15 16:03:47 +01004594{
4595 struct net_device *dev;
4596 struct list_head *iter;
4597 int ret;
4598
4599 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4600 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004601 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4602 event, ptr,
4603 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004604 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004605 return ret;
4606 }
4607 }
4608
Ido Schimmel80bedf12016-06-20 23:03:59 +02004609 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004610}
4611
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004612static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4613 unsigned long event, void *ptr)
4614{
4615 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4616 u16 vid = vlan_dev_vlan_id(vlan_dev);
4617
Ido Schimmel272c4472015-12-15 16:03:47 +01004618 if (mlxsw_sp_port_dev_check(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004619 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4620 event, ptr, vid);
Ido Schimmel272c4472015-12-15 16:03:47 +01004621 else if (netif_is_lag_master(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004622 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4623 real_dev, event,
4624 ptr, vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004625
Ido Schimmel80bedf12016-06-20 23:03:59 +02004626 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004627}
4628
Ido Schimmelb1e45522017-04-30 19:47:14 +03004629static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4630{
4631 struct netdev_notifier_changeupper_info *info = ptr;
4632
4633 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4634 return false;
4635 return netif_is_l3_master(info->upper_dev);
4636}
4637
Petr Machata00635872017-10-16 16:26:37 +02004638static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004639 unsigned long event, void *ptr)
4640{
4641 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Petr Machata00635872017-10-16 16:26:37 +02004642 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004643 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004644
Petr Machata00635872017-10-16 16:26:37 +02004645 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
Petr Machata796ec772017-11-03 10:03:29 +01004646 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
4647 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
4648 event, ptr);
Petr Machata61481f22017-11-03 10:03:41 +01004649 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
4650 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
4651 event, ptr);
Petr Machata00635872017-10-16 16:26:37 +02004652 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004653 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03004654 else if (mlxsw_sp_is_vrf_event(event, ptr))
4655 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004656 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004657 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004658 else if (netif_is_lag_master(dev))
4659 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4660 else if (is_vlan_dev(dev))
4661 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004662
Ido Schimmel80bedf12016-06-20 23:03:59 +02004663 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004664}
4665
David Ahern89d5dd22017-10-18 09:56:55 -07004666static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
4667 .notifier_call = mlxsw_sp_inetaddr_valid_event,
4668};
4669
Ido Schimmel99724c12016-07-04 08:23:14 +02004670static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4671 .notifier_call = mlxsw_sp_inetaddr_event,
David Ahern89d5dd22017-10-18 09:56:55 -07004672};
4673
4674static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
4675 .notifier_call = mlxsw_sp_inet6addr_valid_event,
Ido Schimmel99724c12016-07-04 08:23:14 +02004676};
4677
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004678static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
4679 .notifier_call = mlxsw_sp_inet6addr_event,
4680};
4681
Jiri Pirko1d20d232016-10-27 15:12:59 +02004682static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4683 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4684 {0, },
4685};
4686
4687static struct pci_driver mlxsw_sp_pci_driver = {
4688 .name = mlxsw_sp_driver_name,
4689 .id_table = mlxsw_sp_pci_id_table,
4690};
4691
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004692static int __init mlxsw_sp_module_init(void)
4693{
4694 int err;
4695
David Ahern89d5dd22017-10-18 09:56:55 -07004696 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004697 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004698 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004699 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004700
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004701 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4702 if (err)
4703 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02004704
4705 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4706 if (err)
4707 goto err_pci_driver_register;
4708
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004709 return 0;
4710
Jiri Pirko1d20d232016-10-27 15:12:59 +02004711err_pci_driver_register:
4712 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004713err_core_driver_register:
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004714 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004715 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02004716 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004717 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004718 return err;
4719}
4720
4721static void __exit mlxsw_sp_module_exit(void)
4722{
Jiri Pirko1d20d232016-10-27 15:12:59 +02004723 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004724 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004725 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004726 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004727 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004728 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004729}
4730
4731module_init(mlxsw_sp_module_init);
4732module_exit(mlxsw_sp_module_exit);
4733
4734MODULE_LICENSE("Dual BSD/GPL");
4735MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4736MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02004737MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Yotam Gigi6b742192017-05-23 21:56:29 +02004738MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);