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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Jesse Barnes5669fca2009-02-17 15:13:31 -080030#include <linux/device.h>
Jesse Barnese5747e32014-06-12 08:35:47 -070031#include <linux/acpi.h>
David Howells760285e2012-10-02 18:01:07 +010032#include <drm/drmP.h>
33#include <drm/i915_drm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#include "i915_drv.h"
Chris Wilson990bbda2012-07-02 11:51:02 -030035#include "i915_trace.h"
Kenneth Graunkef49f0582010-09-11 01:19:14 -070036#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include <linux/console.h>
Paul Gortmakere0cd3602011-08-30 11:04:30 -040039#include <linux/module.h>
Imre Deakd6102972014-05-07 19:57:49 +030040#include <linux/pm_runtime.h>
David Howells760285e2012-10-02 18:01:07 +010041#include <drm/drm_crtc_helper.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080042
Kristian Høgsberg112b7152009-01-04 16:55:33 -050043static struct drm_driver driver;
44
Antti Koskipaaa57c7742014-02-04 14:22:24 +020045#define GEN_DEFAULT_PIPEOFFSETS \
46 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
47 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
48 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
49 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
Antti Koskipaaa57c7742014-02-04 14:22:24 +020050 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
51
Rafael Barbalho84fd4f42014-04-28 14:00:42 +030052#define GEN_CHV_PIPEOFFSETS \
53 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
54 CHV_PIPE_C_OFFSET }, \
55 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
56 CHV_TRANSCODER_C_OFFSET, }, \
Rafael Barbalho84fd4f42014-04-28 14:00:42 +030057 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
58 CHV_PALETTE_C_OFFSET }
Antti Koskipaaa57c7742014-02-04 14:22:24 +020059
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030060#define CURSOR_OFFSETS \
61 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
62
63#define IVB_CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
65
Tobias Klauser9a7e8492010-05-20 10:33:46 +020066static const struct intel_device_info intel_i830_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070067 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
Chris Wilson315781482010-08-12 09:42:51 +010068 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070069 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020070 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030071 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050072};
73
Tobias Klauser9a7e8492010-05-20 10:33:46 +020074static const struct intel_device_info intel_845g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070075 .gen = 2, .num_pipes = 1,
Chris Wilson315781482010-08-12 09:42:51 +010076 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070077 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020078 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030079 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050080};
81
Tobias Klauser9a7e8492010-05-20 10:33:46 +020082static const struct intel_device_info intel_i85x_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070083 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
Adam Jackson5ce8ba72010-04-15 14:03:30 -040084 .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +010085 .has_overlay = 1, .overlay_needs_physical = 1,
Ville Syrjäläfd70d522013-11-28 17:30:02 +020086 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070087 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020088 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030089 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050090};
91
Tobias Klauser9a7e8492010-05-20 10:33:46 +020092static const struct intel_device_info intel_i865g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070093 .gen = 2, .num_pipes = 1,
Chris Wilson315781482010-08-12 09:42:51 +010094 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070095 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020096 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030097 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050098};
99
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200100static const struct intel_device_info intel_i915g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700101 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
Chris Wilson315781482010-08-12 09:42:51 +0100102 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700103 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200104 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300105 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500106};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200107static const struct intel_device_info intel_i915gm_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700108 .gen = 3, .is_mobile = 1, .num_pipes = 2,
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -0500109 .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100110 .has_overlay = 1, .overlay_needs_physical = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100111 .supports_tv = 1,
Ville Syrjäläfd70d522013-11-28 17:30:02 +0200112 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700113 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200114 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300115 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500116};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200117static const struct intel_device_info intel_i945g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700118 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
Chris Wilson315781482010-08-12 09:42:51 +0100119 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700120 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200121 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300122 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500123};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200124static const struct intel_device_info intel_i945gm_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700125 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -0500126 .has_hotplug = 1, .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100127 .has_overlay = 1, .overlay_needs_physical = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100128 .supports_tv = 1,
Ville Syrjäläfd70d522013-11-28 17:30:02 +0200129 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700130 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200131 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300132 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500133};
134
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200135static const struct intel_device_info intel_i965g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700136 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100137 .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100138 .has_overlay = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700139 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200140 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300141 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500142};
143
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200144static const struct intel_device_info intel_i965gm_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700145 .gen = 4, .is_crestline = 1, .num_pipes = 2,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000146 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100147 .has_overlay = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100148 .supports_tv = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700149 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200150 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300151 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500152};
153
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200154static const struct intel_device_info intel_g33_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700155 .gen = 3, .is_g33 = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100156 .need_gfx_hws = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100157 .has_overlay = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700158 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200159 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300160 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500161};
162
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200163static const struct intel_device_info intel_g45_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700164 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100165 .has_pipe_cxsr = 1, .has_hotplug = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700166 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200167 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300168 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500169};
170
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200171static const struct intel_device_info intel_gm45_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700172 .gen = 4, .is_g4x = 1, .num_pipes = 2,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000173 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100174 .has_pipe_cxsr = 1, .has_hotplug = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100175 .supports_tv = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700176 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200177 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300178 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500179};
180
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200181static const struct intel_device_info intel_pineview_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700182 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100183 .need_gfx_hws = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100184 .has_overlay = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200185 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300186 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500187};
188
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200189static const struct intel_device_info intel_ironlake_d_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700190 .gen = 5, .num_pipes = 2,
Eugeni Dodonov5a117db2012-01-05 09:34:29 -0200191 .need_gfx_hws = 1, .has_hotplug = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700192 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200193 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300194 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500195};
196
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200197static const struct intel_device_info intel_ironlake_m_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700198 .gen = 5, .is_mobile = 1, .num_pipes = 2,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000199 .need_gfx_hws = 1, .has_hotplug = 1,
Jesse Barnesc1a9f042011-05-05 15:24:21 -0700200 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700201 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200202 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300203 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500204};
205
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200206static const struct intel_device_info intel_sandybridge_d_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700207 .gen = 6, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100208 .need_gfx_hws = 1, .has_hotplug = 1,
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200209 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700210 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200211 .has_llc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200212 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300213 CURSOR_OFFSETS,
Eric Anholtf6e450a2009-11-02 12:08:22 -0800214};
215
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200216static const struct intel_device_info intel_sandybridge_m_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700217 .gen = 6, .is_mobile = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100218 .need_gfx_hws = 1, .has_hotplug = 1,
Yuanhan Liu9c04f012010-12-15 15:42:32 +0800219 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700220 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200221 .has_llc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200222 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300223 CURSOR_OFFSETS,
Eric Anholta13e4092010-01-07 15:08:18 -0800224};
225
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700226#define GEN7_FEATURES \
227 .gen = 7, .num_pipes = 3, \
228 .need_gfx_hws = 1, .has_hotplug = 1, \
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200229 .has_fbc = 1, \
Ben Widawsky73ae4782013-10-15 10:02:57 -0700230 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
Ben Widawskyab484f82013-10-05 17:57:11 -0700231 .has_llc = 1
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700232
Jesse Barnesc76b6152011-04-28 14:32:07 -0700233static const struct intel_device_info intel_ivybridge_d_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700234 GEN7_FEATURES,
235 .is_ivybridge = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200236 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300237 IVB_CURSOR_OFFSETS,
Jesse Barnesc76b6152011-04-28 14:32:07 -0700238};
239
240static const struct intel_device_info intel_ivybridge_m_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700241 GEN7_FEATURES,
242 .is_ivybridge = 1,
243 .is_mobile = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200244 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300245 IVB_CURSOR_OFFSETS,
Jesse Barnesc76b6152011-04-28 14:32:07 -0700246};
247
Ben Widawsky999bcde2013-04-05 13:12:45 -0700248static const struct intel_device_info intel_ivybridge_q_info = {
249 GEN7_FEATURES,
250 .is_ivybridge = 1,
251 .num_pipes = 0, /* legal, last one wins */
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200252 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300253 IVB_CURSOR_OFFSETS,
Ben Widawsky999bcde2013-04-05 13:12:45 -0700254};
255
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700256static const struct intel_device_info intel_valleyview_m_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700257 GEN7_FEATURES,
258 .is_mobile = 1,
259 .num_pipes = 2,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700260 .is_valleyview = 1,
Ville Syrjäläfba5d532013-01-24 15:29:56 +0200261 .display_mmio_offset = VLV_DISPLAY_BASE,
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200262 .has_fbc = 0, /* legal, last one wins */
Ben Widawsky30ccd962013-04-15 21:48:03 -0700263 .has_llc = 0, /* legal, last one wins */
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200264 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300265 CURSOR_OFFSETS,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700266};
267
268static const struct intel_device_info intel_valleyview_d_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700269 GEN7_FEATURES,
270 .num_pipes = 2,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700271 .is_valleyview = 1,
Ville Syrjäläfba5d532013-01-24 15:29:56 +0200272 .display_mmio_offset = VLV_DISPLAY_BASE,
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200273 .has_fbc = 0, /* legal, last one wins */
Ben Widawsky30ccd962013-04-15 21:48:03 -0700274 .has_llc = 0, /* legal, last one wins */
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200275 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300276 CURSOR_OFFSETS,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700277};
278
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -0300279static const struct intel_device_info intel_haswell_d_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700280 GEN7_FEATURES,
281 .is_haswell = 1,
Damien Lespiaudd93be52013-04-22 18:40:39 +0100282 .has_ddi = 1,
Damien Lespiau30568c42013-04-22 18:40:41 +0100283 .has_fpga_dbg = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700284 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200285 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300286 IVB_CURSOR_OFFSETS,
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -0300287};
288
289static const struct intel_device_info intel_haswell_m_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700290 GEN7_FEATURES,
291 .is_haswell = 1,
292 .is_mobile = 1,
Damien Lespiaudd93be52013-04-22 18:40:39 +0100293 .has_ddi = 1,
Damien Lespiau30568c42013-04-22 18:40:41 +0100294 .has_fpga_dbg = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700295 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200296 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300297 IVB_CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500298};
299
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800300static const struct intel_device_info intel_broadwell_d_info = {
Damien Lespiau4b305532013-11-02 21:07:32 -0700301 .gen = 8, .num_pipes = 3,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800302 .need_gfx_hws = 1, .has_hotplug = 1,
303 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
304 .has_llc = 1,
305 .has_ddi = 1,
Paulo Zanoni66bc2ca2014-07-16 17:49:30 -0300306 .has_fpga_dbg = 1,
Ben Widawsky8f94d242014-02-20 16:01:20 -0800307 .has_fbc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200308 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300309 IVB_CURSOR_OFFSETS,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800310};
311
312static const struct intel_device_info intel_broadwell_m_info = {
Damien Lespiau4b305532013-11-02 21:07:32 -0700313 .gen = 8, .is_mobile = 1, .num_pipes = 3,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800314 .need_gfx_hws = 1, .has_hotplug = 1,
315 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
316 .has_llc = 1,
317 .has_ddi = 1,
Paulo Zanoni66bc2ca2014-07-16 17:49:30 -0300318 .has_fpga_dbg = 1,
Ben Widawsky8f94d242014-02-20 16:01:20 -0800319 .has_fbc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200320 GEN_DEFAULT_PIPEOFFSETS,
Rodrigo Vivi15d24aa2014-06-04 17:09:30 -0700321 IVB_CURSOR_OFFSETS,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800322};
323
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800324static const struct intel_device_info intel_broadwell_gt3d_info = {
325 .gen = 8, .num_pipes = 3,
326 .need_gfx_hws = 1, .has_hotplug = 1,
Zhao Yakui845f74a2014-04-17 10:37:37 +0800327 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800328 .has_llc = 1,
329 .has_ddi = 1,
Paulo Zanoni66bc2ca2014-07-16 17:49:30 -0300330 .has_fpga_dbg = 1,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800331 .has_fbc = 1,
332 GEN_DEFAULT_PIPEOFFSETS,
Rodrigo Vivi15d24aa2014-06-04 17:09:30 -0700333 IVB_CURSOR_OFFSETS,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800334};
335
336static const struct intel_device_info intel_broadwell_gt3m_info = {
337 .gen = 8, .is_mobile = 1, .num_pipes = 3,
338 .need_gfx_hws = 1, .has_hotplug = 1,
Zhao Yakui845f74a2014-04-17 10:37:37 +0800339 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800340 .has_llc = 1,
341 .has_ddi = 1,
Paulo Zanoni66bc2ca2014-07-16 17:49:30 -0300342 .has_fpga_dbg = 1,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800343 .has_fbc = 1,
344 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300345 IVB_CURSOR_OFFSETS,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800346};
347
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300348static const struct intel_device_info intel_cherryview_info = {
349 .is_preliminary = 1,
Ville Syrjälä07fddb12014-04-09 13:28:54 +0300350 .gen = 8, .num_pipes = 3,
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300351 .need_gfx_hws = 1, .has_hotplug = 1,
352 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
353 .is_valleyview = 1,
354 .display_mmio_offset = VLV_DISPLAY_BASE,
Rafael Barbalho84fd4f42014-04-28 14:00:42 +0300355 GEN_CHV_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300356 CURSOR_OFFSETS,
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300357};
358
Jesse Barnesa0a18072013-07-26 13:32:51 -0700359/*
360 * Make sure any device matches here are from most specific to most
361 * general. For example, since the Quanta match is based on the subsystem
362 * and subvendor IDs, we need it to come before the more general IVB
363 * PCI ID matches, otherwise we'll use the wrong info struct above.
364 */
365#define INTEL_PCI_IDS \
366 INTEL_I830_IDS(&intel_i830_info), \
367 INTEL_I845G_IDS(&intel_845g_info), \
368 INTEL_I85X_IDS(&intel_i85x_info), \
369 INTEL_I865G_IDS(&intel_i865g_info), \
370 INTEL_I915G_IDS(&intel_i915g_info), \
371 INTEL_I915GM_IDS(&intel_i915gm_info), \
372 INTEL_I945G_IDS(&intel_i945g_info), \
373 INTEL_I945GM_IDS(&intel_i945gm_info), \
374 INTEL_I965G_IDS(&intel_i965g_info), \
375 INTEL_G33_IDS(&intel_g33_info), \
376 INTEL_I965GM_IDS(&intel_i965gm_info), \
377 INTEL_GM45_IDS(&intel_gm45_info), \
378 INTEL_G45_IDS(&intel_g45_info), \
379 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
380 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
381 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
382 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
383 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
384 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
385 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
386 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
387 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
388 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
389 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800390 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800391 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
392 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
393 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300394 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
395 INTEL_CHV_IDS(&intel_cherryview_info)
Jesse Barnesa0a18072013-07-26 13:32:51 -0700396
Chris Wilson6103da02010-07-05 18:01:47 +0100397static const struct pci_device_id pciidlist[] = { /* aka */
Jesse Barnesa0a18072013-07-26 13:32:51 -0700398 INTEL_PCI_IDS,
Kristian Høgsberg49ae35f2009-12-16 15:16:15 -0500399 {0, 0, 0}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400};
401
Jesse Barnes79e53942008-11-07 14:24:08 -0800402#if defined(CONFIG_DRM_I915_KMS)
403MODULE_DEVICE_TABLE(pci, pciidlist);
404#endif
405
Akshay Joshi0206e352011-08-16 15:34:10 -0400406void intel_detect_pch(struct drm_device *dev)
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800407{
408 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deakbcdb72a2014-02-14 20:23:54 +0200409 struct pci_dev *pch = NULL;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800410
Ben Widawskyce1bb322013-04-05 13:12:44 -0700411 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
412 * (which really amounts to a PCH but no South Display).
413 */
414 if (INTEL_INFO(dev)->num_pipes == 0) {
415 dev_priv->pch_type = PCH_NOP;
Ben Widawskyce1bb322013-04-05 13:12:44 -0700416 return;
417 }
418
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800419 /*
420 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
421 * make graphics device passthrough work easy for VMM, that only
422 * need to expose ISA bridge to let driver know the real hardware
423 * underneath. This is a requirement from virtualization team.
Rui Guo6a9c4b32013-06-19 21:10:23 +0800424 *
425 * In some virtualized environments (e.g. XEN), there is irrelevant
426 * ISA bridge in the system. To work reliably, we should scan trhough
427 * all the ISA bridge devices and check for the first match, instead
428 * of only checking the first one.
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800429 */
Imre Deakbcdb72a2014-02-14 20:23:54 +0200430 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800431 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
Imre Deakbcdb72a2014-02-14 20:23:54 +0200432 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
Paulo Zanoni17a303e2012-11-20 15:12:07 -0200433 dev_priv->pch_id = id;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800434
Jesse Barnes90711d52011-04-28 14:48:02 -0700435 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
436 dev_priv->pch_type = PCH_IBX;
437 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100438 WARN_ON(!IS_GEN5(dev));
Jesse Barnes90711d52011-04-28 14:48:02 -0700439 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800440 dev_priv->pch_type = PCH_CPT;
441 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100442 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
Jesse Barnesc7925132011-04-07 12:33:56 -0700443 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
444 /* PantherPoint is CPT compatible */
445 dev_priv->pch_type = PCH_CPT;
Jani Nikula492ab662013-10-01 12:12:33 +0300446 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100447 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300448 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
449 dev_priv->pch_type = PCH_LPT;
450 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100451 WARN_ON(!IS_HASWELL(dev));
Paulo Zanoni08e14132013-04-12 18:16:54 -0300452 WARN_ON(IS_ULT(dev));
Paulo Zanoni018f52c2013-11-02 21:07:35 -0700453 } else if (IS_BROADWELL(dev)) {
454 dev_priv->pch_type = PCH_LPT;
455 dev_priv->pch_id =
456 INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
457 DRM_DEBUG_KMS("This is Broadwell, assuming "
458 "LynxPoint LP PCH\n");
Ben Widawskye76e0632013-11-07 21:40:41 -0800459 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
460 dev_priv->pch_type = PCH_LPT;
461 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
462 WARN_ON(!IS_HASWELL(dev));
463 WARN_ON(!IS_ULT(dev));
Imre Deakbcdb72a2014-02-14 20:23:54 +0200464 } else
465 continue;
466
Rui Guo6a9c4b32013-06-19 21:10:23 +0800467 break;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800468 }
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800469 }
Rui Guo6a9c4b32013-06-19 21:10:23 +0800470 if (!pch)
Imre Deakbcdb72a2014-02-14 20:23:54 +0200471 DRM_DEBUG_KMS("No PCH found.\n");
472
473 pci_dev_put(pch);
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800474}
475
Ben Widawsky2911a352012-04-05 14:47:36 -0700476bool i915_semaphore_is_enabled(struct drm_device *dev)
477{
478 if (INTEL_INFO(dev)->gen < 6)
Daniel Vettera08acaf2013-12-17 09:56:53 +0100479 return false;
Ben Widawsky2911a352012-04-05 14:47:36 -0700480
Jani Nikulad330a952014-01-21 11:24:25 +0200481 if (i915.semaphores >= 0)
482 return i915.semaphores;
Ben Widawsky2911a352012-04-05 14:47:36 -0700483
Rodrigo Vivibe71eab2014-08-04 11:15:19 -0700484 /* Until we get further testing... */
485 if (IS_GEN8(dev))
486 return false;
487
Daniel Vetter59de3292012-04-02 20:48:43 +0200488#ifdef CONFIG_INTEL_IOMMU
Ben Widawsky2911a352012-04-05 14:47:36 -0700489 /* Enable semaphores on SNB when IO remapping is off */
Daniel Vetter59de3292012-04-02 20:48:43 +0200490 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
491 return false;
492#endif
Ben Widawsky2911a352012-04-05 14:47:36 -0700493
Daniel Vettera08acaf2013-12-17 09:56:53 +0100494 return true;
Ben Widawsky2911a352012-04-05 14:47:36 -0700495}
496
Sagar Kambleebc32822014-08-13 23:07:05 +0530497
498static int intel_suspend_complete(struct drm_i915_private *dev_priv);
499static int intel_resume_prepare(struct drm_i915_private *dev_priv);
500
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100501static int i915_drm_freeze(struct drm_device *dev)
502{
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100503 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes24576d22013-03-26 09:25:45 -0700504 struct drm_crtc *crtc;
Jesse Barnese5747e32014-06-12 08:35:47 -0700505 pci_power_t opregion_target_state;
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100506
Zhang Ruib8efb172013-02-05 15:41:53 +0800507 /* ignore lid events during suspend */
508 mutex_lock(&dev_priv->modeset_restore_lock);
509 dev_priv->modeset_restore = MODESET_SUSPENDED;
510 mutex_unlock(&dev_priv->modeset_restore_lock);
511
Paulo Zanonic67a4702013-08-19 13:18:09 -0300512 /* We do a lot of poking in a lot of registers, make sure they work
513 * properly. */
Imre Deakda7e29b2014-02-18 00:02:02 +0200514 intel_display_set_init_power(dev_priv, true);
Paulo Zanonicb107992013-01-25 16:59:15 -0200515
Dave Airlie5bcf7192010-12-07 09:20:40 +1000516 drm_kms_helper_poll_disable(dev);
517
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100518 pci_save_state(dev->pdev);
519
520 /* If KMS is active, we do the leavevt stuff here */
521 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
Daniel Vetterdb1b76c2013-07-09 16:51:37 +0200522 int error;
523
Chris Wilson45c5f202013-10-16 11:50:01 +0100524 error = i915_gem_suspend(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100525 if (error) {
526 dev_err(&dev->pdev->dev,
527 "GEM idle failed, resume might fail\n");
528 return error;
529 }
Daniel Vettera261b242012-07-26 19:21:47 +0200530
Jesse Barnes24576d22013-03-26 09:25:45 -0700531 /*
532 * Disable CRTCs directly since we want to preserve sw state
Borun Fub04c5bd2014-07-12 10:02:27 +0530533 * for _thaw. Also, power gate the CRTC power wells.
Jesse Barnes24576d22013-03-26 09:25:45 -0700534 */
Daniel Vetter6e9f7982014-05-29 23:54:47 +0200535 drm_modeset_lock_all(dev);
Borun Fub04c5bd2014-07-12 10:02:27 +0530536 for_each_crtc(dev, crtc)
537 intel_crtc_control(crtc, false);
Daniel Vetter6e9f7982014-05-29 23:54:47 +0200538 drm_modeset_unlock_all(dev);
Imre Deak7d708ee2013-04-17 14:04:50 +0300539
Dave Airlie0e32b392014-05-02 14:02:48 +1000540 intel_dp_mst_suspend(dev);
Dave Airlie09b64262014-07-23 14:25:24 +1000541
542 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
543
Dave Airlie0e32b392014-05-02 14:02:48 +1000544 intel_runtime_pm_disable_interrupts(dev);
545
Dave Airlie09b64262014-07-23 14:25:24 +1000546 intel_suspend_gt_powersave(dev);
547
Imre Deak7d708ee2013-04-17 14:04:50 +0300548 intel_modeset_suspend_hw(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100549 }
550
Ben Widawsky828c7902013-10-16 09:21:30 -0700551 i915_gem_suspend_gtt_mappings(dev);
552
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100553 i915_save_state(dev);
554
Imre Deak95fa2ee2014-06-23 15:46:02 +0300555 opregion_target_state = PCI_D3cold;
556#if IS_ENABLED(CONFIG_ACPI_SLEEP)
557 if (acpi_target_system_state() < ACPI_STATE_S3)
Jesse Barnese5747e32014-06-12 08:35:47 -0700558 opregion_target_state = PCI_D1;
Imre Deak95fa2ee2014-06-23 15:46:02 +0300559#endif
Jesse Barnese5747e32014-06-12 08:35:47 -0700560 intel_opregion_notify_adapter(dev, opregion_target_state);
561
Jesse Barnes156c7ca2014-06-12 08:35:45 -0700562 intel_uncore_forcewake_reset(dev, false);
Chris Wilson44834a62010-08-19 16:09:23 +0100563 intel_opregion_fini(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100564
Chris Wilson82e3b8c2014-08-13 13:09:46 +0100565 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
Dave Airlie3fa016a2012-03-28 10:48:49 +0100566
Mika Kuoppala62d5d692014-02-25 17:11:28 +0200567 dev_priv->suspend_count++;
568
Kristen Carlson Accardi85e90672014-06-12 08:35:44 -0700569 intel_display_set_init_power(dev_priv, false);
570
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100571 return 0;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100572}
573
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000574int i915_suspend(struct drm_device *dev, pm_message_t state)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100575{
576 int error;
577
578 if (!dev || !dev->dev_private) {
579 DRM_ERROR("dev: %p\n", dev);
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700580 DRM_ERROR("DRM not initialized, aborting suspend.\n");
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000581 return -ENODEV;
582 }
583
Dave Airlieb932ccb2008-02-20 10:02:20 +1000584 if (state.event == PM_EVENT_PRETHAW)
585 return 0;
586
Dave Airlie5bcf7192010-12-07 09:20:40 +1000587
588 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
589 return 0;
Chris Wilson6eecba32010-09-08 09:45:11 +0100590
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100591 error = i915_drm_freeze(dev);
592 if (error)
593 return error;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000594
Dave Airlieb932ccb2008-02-20 10:02:20 +1000595 if (state.event == PM_EVENT_SUSPEND) {
596 /* Shut down the device */
597 pci_disable_device(dev->pdev);
598 pci_set_power_state(dev->pdev, PCI_D3hot);
599 }
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000600
601 return 0;
602}
603
Imre Deak76c4b252014-04-01 19:55:22 +0300604static int i915_drm_thaw_early(struct drm_device *dev)
605{
606 struct drm_i915_private *dev_priv = dev->dev_private;
607
Kristen Carlson Accardi8abdc172014-06-12 08:35:48 -0700608 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
609 hsw_disable_pc8(dev_priv);
610
Imre Deak10018602014-06-06 12:59:39 +0300611 intel_uncore_early_sanitize(dev, true);
Imre Deak76c4b252014-04-01 19:55:22 +0300612 intel_uncore_sanitize(dev);
613 intel_power_domains_init_hw(dev_priv);
614
615 return 0;
616}
617
Paulo Zanoni9d49c0e2013-09-12 18:06:43 -0300618static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000619{
Jesse Barnes5669fca2009-02-17 15:13:31 -0800620 struct drm_i915_private *dev_priv = dev->dev_private;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100621
Paulo Zanoni9d49c0e2013-09-12 18:06:43 -0300622 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
623 restore_gtt_mappings) {
624 mutex_lock(&dev->struct_mutex);
625 i915_gem_restore_gtt_mappings(dev);
626 mutex_unlock(&dev->struct_mutex);
627 }
628
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100629 i915_restore_state(dev);
Chris Wilson44834a62010-08-19 16:09:23 +0100630 intel_opregion_setup(dev);
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100631
Jesse Barnes5669fca2009-02-17 15:13:31 -0800632 /* KMS EnterVT equivalent */
633 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
Paulo Zanonidde86e22012-12-01 12:04:25 -0200634 intel_init_pch_refclk(dev);
Daniel Vetter754970ee2014-01-16 22:28:44 +0100635 drm_mode_config_reset(dev);
Chris Wilson1833b132012-05-09 11:56:28 +0100636
Jesse Barnes5669fca2009-02-17 15:13:31 -0800637 mutex_lock(&dev->struct_mutex);
Chris Wilson074c6ad2014-04-09 09:19:43 +0100638 if (i915_gem_init_hw(dev)) {
639 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
640 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
641 }
Jesse Barnes5669fca2009-02-17 15:13:31 -0800642 mutex_unlock(&dev->struct_mutex);
Jesse Barnes226485e2009-02-23 15:41:09 -0800643
Jesse Barnese11aa362014-06-18 09:52:55 -0700644 intel_runtime_pm_restore_interrupts(dev);
Daniel Vetter15239092013-03-05 09:50:58 +0100645
Chris Wilson1833b132012-05-09 11:56:28 +0100646 intel_modeset_init_hw(dev);
Jesse Barnes24576d22013-03-26 09:25:45 -0700647
Dave Airlie0e32b392014-05-02 14:02:48 +1000648 {
649 unsigned long irqflags;
650 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
651 if (dev_priv->display.hpd_irq_setup)
652 dev_priv->display.hpd_irq_setup(dev);
653 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
654 }
655
656 intel_dp_mst_resume(dev);
Jesse Barnes24576d22013-03-26 09:25:45 -0700657 drm_modeset_lock_all(dev);
658 intel_modeset_setup_hw_state(dev, true);
659 drm_modeset_unlock_all(dev);
Daniel Vetter15239092013-03-05 09:50:58 +0100660
661 /*
662 * ... but also need to make sure that hotplug processing
663 * doesn't cause havoc. Like in the driver load code we don't
664 * bother with the tiny race here where we might loose hotplug
665 * notifications.
666 * */
Daniel Vetter20afbda2012-12-11 14:05:07 +0100667 intel_hpd_init(dev);
Jesse Barnesbb60b962013-03-26 09:25:46 -0700668 /* Config may have changed between suspend and resume */
Jesse Barnes1ff74cf2014-05-20 15:25:33 -0700669 drm_helper_hpd_irq_event(dev);
Jesse Barnesd5bb0812011-01-05 12:01:26 -0800670 }
Jesse Barnes1daed3f2011-01-05 12:01:25 -0800671
Chris Wilson44834a62010-08-19 16:09:23 +0100672 intel_opregion_init(dev);
673
Chris Wilson82e3b8c2014-08-13 13:09:46 +0100674 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
Jesse Barnes073f34d2012-11-02 11:13:59 -0700675
Zhang Ruib8efb172013-02-05 15:41:53 +0800676 mutex_lock(&dev_priv->modeset_restore_lock);
677 dev_priv->modeset_restore = MODESET_DONE;
678 mutex_unlock(&dev_priv->modeset_restore_lock);
Paulo Zanoni8a187452013-12-06 20:32:13 -0200679
Jesse Barnese5747e32014-06-12 08:35:47 -0700680 intel_opregion_notify_adapter(dev, PCI_D0);
681
Chris Wilson074c6ad2014-04-09 09:19:43 +0100682 return 0;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100683}
684
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700685static int i915_drm_thaw(struct drm_device *dev)
686{
Daniel Vetter7f16e5c2013-11-04 16:28:47 +0100687 if (drm_core_check_feature(dev, DRIVER_MODESET))
Ben Widawsky828c7902013-10-16 09:21:30 -0700688 i915_check_and_clear_faults(dev);
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700689
Paulo Zanoni9d49c0e2013-09-12 18:06:43 -0300690 return __i915_drm_thaw(dev, true);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100691}
692
Imre Deak76c4b252014-04-01 19:55:22 +0300693static int i915_resume_early(struct drm_device *dev)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100694{
Dave Airlie5bcf7192010-12-07 09:20:40 +1000695 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
696 return 0;
697
Imre Deak76c4b252014-04-01 19:55:22 +0300698 /*
699 * We have a resume ordering issue with the snd-hda driver also
700 * requiring our device to be power up. Due to the lack of a
701 * parent/child relationship we currently solve this with an early
702 * resume hook.
703 *
704 * FIXME: This should be solved with a special hdmi sink device or
705 * similar so that power domains can be employed.
706 */
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100707 if (pci_enable_device(dev->pdev))
708 return -EIO;
709
710 pci_set_master(dev->pdev);
711
Imre Deak76c4b252014-04-01 19:55:22 +0300712 return i915_drm_thaw_early(dev);
713}
714
715int i915_resume(struct drm_device *dev)
716{
717 struct drm_i915_private *dev_priv = dev->dev_private;
718 int ret;
719
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700720 /*
721 * Platforms with opregion should have sane BIOS, older ones (gen3 and
Paulo Zanoni9d49c0e2013-09-12 18:06:43 -0300722 * earlier) need to restore the GTT mappings since the BIOS might clear
723 * all our scratch PTEs.
Jesse Barnes1abd02e2012-11-02 11:14:02 -0700724 */
Paulo Zanoni9d49c0e2013-09-12 18:06:43 -0300725 ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
Chris Wilson6eecba32010-09-08 09:45:11 +0100726 if (ret)
727 return ret;
728
729 drm_kms_helper_poll_enable(dev);
730 return 0;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000731}
732
Imre Deak76c4b252014-04-01 19:55:22 +0300733static int i915_resume_legacy(struct drm_device *dev)
734{
735 i915_resume_early(dev);
736 i915_resume(dev);
737
738 return 0;
739}
740
Ben Gamari11ed50e2009-09-14 17:48:45 -0400741/**
Eugeni Dodonovf3953dc2011-11-28 16:15:17 -0200742 * i915_reset - reset chip after a hang
Ben Gamari11ed50e2009-09-14 17:48:45 -0400743 * @dev: drm device to reset
Ben Gamari11ed50e2009-09-14 17:48:45 -0400744 *
745 * Reset the chip. Useful if a hang is detected. Returns zero on successful
746 * reset or otherwise an error code.
747 *
748 * Procedure is fairly simple:
749 * - reset the chip using the reset reg
750 * - re-init context state
751 * - re-init hardware status page
752 * - re-init ring buffer
753 * - re-init interrupt state
754 * - re-init display
755 */
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200756int i915_reset(struct drm_device *dev)
Ben Gamari11ed50e2009-09-14 17:48:45 -0400757{
Jani Nikula50227e12014-03-31 14:27:21 +0300758 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson2e7c8ee2013-05-28 10:38:44 +0100759 bool simulated;
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700760 int ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400761
Jani Nikulad330a952014-01-21 11:24:25 +0200762 if (!i915.reset)
Chris Wilsond78cb502010-12-23 13:33:15 +0000763 return 0;
764
Daniel Vetterd54a02c2012-07-04 22:18:39 +0200765 mutex_lock(&dev->struct_mutex);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400766
Chris Wilson069efc12010-09-30 16:53:18 +0100767 i915_gem_reset(dev);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400768
Chris Wilson2e7c8ee2013-05-28 10:38:44 +0100769 simulated = dev_priv->gpu_error.stop_rings != 0;
770
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300771 ret = intel_gpu_reset(dev);
Daniel Vetter350d2702012-04-27 15:17:42 +0200772
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300773 /* Also reset the gpu hangman. */
774 if (simulated) {
775 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
776 dev_priv->gpu_error.stop_rings = 0;
777 if (ret == -ENODEV) {
Daniel Vetterf2d91a22013-11-07 09:48:57 +0100778 DRM_INFO("Reset not implemented, but ignoring "
779 "error for simulated gpu hangs\n");
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300780 ret = 0;
781 }
Chris Wilson2e7c8ee2013-05-28 10:38:44 +0100782 }
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300783
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700784 if (ret) {
Daniel Vetterf2d91a22013-11-07 09:48:57 +0100785 DRM_ERROR("Failed to reset chip: %i\n", ret);
Daniel J Bluemanf953c932010-05-17 14:23:52 +0100786 mutex_unlock(&dev->struct_mutex);
Chris Wilsonf803aa52010-09-19 12:38:26 +0100787 return ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400788 }
789
790 /* Ok, now get things going again... */
791
792 /*
793 * Everything depends on having the GTT running, so we need to start
794 * there. Fortunately we don't need to do this unless we reset the
795 * chip at a PCI level.
796 *
797 * Next we need to restore the context, but we don't use those
798 * yet either...
799 *
800 * Ring buffer needs to be re-initialized in the KMS case, or if X
801 * was running at the time of the reset (i.e. we weren't VT
802 * switched away).
803 */
804 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
Daniel Vetterdb1b76c2013-07-09 16:51:37 +0200805 !dev_priv->ums.mm_suspended) {
Daniel Vetterdb1b76c2013-07-09 16:51:37 +0200806 dev_priv->ums.mm_suspended = 0;
Eric Anholt75a68982010-11-18 09:31:13 +0800807
Ben Widawsky3d57e5b2013-10-14 10:01:36 -0700808 ret = i915_gem_init_hw(dev);
Daniel Vetter8e88a2b2012-06-19 18:40:00 +0200809 mutex_unlock(&dev->struct_mutex);
Ben Widawsky3d57e5b2013-10-14 10:01:36 -0700810 if (ret) {
811 DRM_ERROR("Failed hw init on reset %d\n", ret);
812 return ret;
813 }
Daniel Vetterf8175862012-04-10 15:50:11 +0200814
Daniel Vettere090c532013-11-03 20:27:05 +0100815 /*
Daniel Vetter78ad4552014-05-22 22:18:21 +0200816 * FIXME: This races pretty badly against concurrent holders of
817 * ring interrupts. This is possible since we've started to drop
818 * dev->struct_mutex in select places when waiting for the gpu.
Daniel Vettere090c532013-11-03 20:27:05 +0100819 */
Jeff McGeedd0a1aa2014-02-04 11:32:31 -0600820
Daniel Vetter78ad4552014-05-22 22:18:21 +0200821 /*
822 * rps/rc6 re-init is necessary to restore state lost after the
823 * reset and the re-install of gt irqs. Skip for ironlake per
Jeff McGeedd0a1aa2014-02-04 11:32:31 -0600824 * previous concerns that it doesn't respond well to some forms
Daniel Vetter78ad4552014-05-22 22:18:21 +0200825 * of re-init after reset.
826 */
Imre Deakdc1d0132014-04-14 20:24:28 +0300827 if (INTEL_INFO(dev)->gen > 5)
Imre Deakc6df39b2014-04-14 20:24:29 +0300828 intel_reset_gt_powersave(dev);
Jeff McGeedd0a1aa2014-02-04 11:32:31 -0600829
Daniel Vetter20afbda2012-12-11 14:05:07 +0100830 intel_hpd_init(dev);
Daniel Vetterbcbc3242012-04-27 15:17:41 +0200831 } else {
832 mutex_unlock(&dev->struct_mutex);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400833 }
834
Ben Gamari11ed50e2009-09-14 17:48:45 -0400835 return 0;
836}
837
Greg Kroah-Hartman56550d92012-12-21 15:09:25 -0800838static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500839{
Daniel Vetter01a06852012-06-25 15:58:49 +0200840 struct intel_device_info *intel_info =
841 (struct intel_device_info *) ent->driver_data;
842
Jani Nikulad330a952014-01-21 11:24:25 +0200843 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
Ben Widawskyb833d682013-08-23 16:00:07 -0700844 DRM_INFO("This hardware requires preliminary hardware support.\n"
845 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
846 return -ENODEV;
847 }
848
Chris Wilson5fe49d82011-02-01 19:43:02 +0000849 /* Only bind to function 0 of the device. Early generations
850 * used function 1 as a placeholder for multi-head. This causes
851 * us confusion instead, especially on the systems where both
852 * functions have the same PCI-ID!
853 */
854 if (PCI_FUNC(pdev->devfn))
855 return -ENODEV;
856
Daniel Vetter24986ee2013-12-11 11:34:33 +0100857 driver.driver_features &= ~(DRIVER_USE_AGP);
Daniel Vetter01a06852012-06-25 15:58:49 +0200858
Jordan Crousedcdb1672010-05-27 13:40:25 -0600859 return drm_get_pci_dev(pdev, ent, &driver);
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500860}
861
862static void
863i915_pci_remove(struct pci_dev *pdev)
864{
865 struct drm_device *dev = pci_get_drvdata(pdev);
866
867 drm_put_dev(dev);
868}
869
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100870static int i915_pm_suspend(struct device *dev)
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500871{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100872 struct pci_dev *pdev = to_pci_dev(dev);
873 struct drm_device *drm_dev = pci_get_drvdata(pdev);
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500874
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100875 if (!drm_dev || !drm_dev->dev_private) {
876 dev_err(dev, "DRM not initialized, aborting suspend.\n");
877 return -ENODEV;
878 }
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500879
Dave Airlie5bcf7192010-12-07 09:20:40 +1000880 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
881 return 0;
882
Imre Deak76c4b252014-04-01 19:55:22 +0300883 return i915_drm_freeze(drm_dev);
884}
885
886static int i915_pm_suspend_late(struct device *dev)
887{
888 struct pci_dev *pdev = to_pci_dev(dev);
889 struct drm_device *drm_dev = pci_get_drvdata(pdev);
Kristen Carlson Accardi8abdc172014-06-12 08:35:48 -0700890 struct drm_i915_private *dev_priv = drm_dev->dev_private;
Imre Deak76c4b252014-04-01 19:55:22 +0300891
892 /*
893 * We have a suspedn ordering issue with the snd-hda driver also
894 * requiring our device to be power up. Due to the lack of a
895 * parent/child relationship we currently solve this with an late
896 * suspend hook.
897 *
898 * FIXME: This should be solved with a special hdmi sink device or
899 * similar so that power domains can be employed.
900 */
901 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
902 return 0;
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500903
Kristen Carlson Accardi8abdc172014-06-12 08:35:48 -0700904 if (IS_HASWELL(drm_dev) || IS_BROADWELL(drm_dev))
905 hsw_enable_pc8(dev_priv);
906
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100907 pci_disable_device(pdev);
908 pci_set_power_state(pdev, PCI_D3hot);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800909
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800910 return 0;
911}
912
Imre Deak76c4b252014-04-01 19:55:22 +0300913static int i915_pm_resume_early(struct device *dev)
914{
915 struct pci_dev *pdev = to_pci_dev(dev);
916 struct drm_device *drm_dev = pci_get_drvdata(pdev);
917
918 return i915_resume_early(drm_dev);
919}
920
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100921static int i915_pm_resume(struct device *dev)
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800922{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100923 struct pci_dev *pdev = to_pci_dev(dev);
924 struct drm_device *drm_dev = pci_get_drvdata(pdev);
925
926 return i915_resume(drm_dev);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800927}
928
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100929static int i915_pm_freeze(struct device *dev)
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800930{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100931 struct pci_dev *pdev = to_pci_dev(dev);
932 struct drm_device *drm_dev = pci_get_drvdata(pdev);
933
934 if (!drm_dev || !drm_dev->dev_private) {
935 dev_err(dev, "DRM not initialized, aborting suspend.\n");
936 return -ENODEV;
937 }
938
939 return i915_drm_freeze(drm_dev);
940}
941
Imre Deak76c4b252014-04-01 19:55:22 +0300942static int i915_pm_thaw_early(struct device *dev)
943{
944 struct pci_dev *pdev = to_pci_dev(dev);
945 struct drm_device *drm_dev = pci_get_drvdata(pdev);
946
947 return i915_drm_thaw_early(drm_dev);
948}
949
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100950static int i915_pm_thaw(struct device *dev)
951{
952 struct pci_dev *pdev = to_pci_dev(dev);
953 struct drm_device *drm_dev = pci_get_drvdata(pdev);
954
955 return i915_drm_thaw(drm_dev);
956}
957
958static int i915_pm_poweroff(struct device *dev)
959{
960 struct pci_dev *pdev = to_pci_dev(dev);
961 struct drm_device *drm_dev = pci_get_drvdata(pdev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100962
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100963 return i915_drm_freeze(drm_dev);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +0800964}
965
Sagar Kambleebc32822014-08-13 23:07:05 +0530966static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
Paulo Zanoni97bea202014-03-07 20:12:33 -0300967{
Paulo Zanoni414de7a2014-03-07 20:12:35 -0300968 hsw_enable_pc8(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +0300969
970 return 0;
Paulo Zanoni97bea202014-03-07 20:12:33 -0300971}
972
Sagar Kambleebc32822014-08-13 23:07:05 +0530973static int snb_resume_prepare(struct drm_i915_private *dev_priv)
Paulo Zanoni9a952a02014-03-07 20:12:34 -0300974{
975 struct drm_device *dev = dev_priv->dev;
976
Paulo Zanoni9a952a02014-03-07 20:12:34 -0300977 intel_init_pch_refclk(dev);
Imre Deak0ab9cfe2014-04-15 16:39:45 +0300978
979 return 0;
Paulo Zanoni9a952a02014-03-07 20:12:34 -0300980}
981
Sagar Kambleebc32822014-08-13 23:07:05 +0530982static int hsw_resume_prepare(struct drm_i915_private *dev_priv)
Paulo Zanoni97bea202014-03-07 20:12:33 -0300983{
Paulo Zanoni414de7a2014-03-07 20:12:35 -0300984 hsw_disable_pc8(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +0300985
986 return 0;
Paulo Zanoni97bea202014-03-07 20:12:33 -0300987}
988
Imre Deakddeea5b2014-05-05 15:19:56 +0300989/*
990 * Save all Gunit registers that may be lost after a D3 and a subsequent
991 * S0i[R123] transition. The list of registers needing a save/restore is
992 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
993 * registers in the following way:
994 * - Driver: saved/restored by the driver
995 * - Punit : saved/restored by the Punit firmware
996 * - No, w/o marking: no need to save/restore, since the register is R/O or
997 * used internally by the HW in a way that doesn't depend
998 * keeping the content across a suspend/resume.
999 * - Debug : used for debugging
1000 *
1001 * We save/restore all registers marked with 'Driver', with the following
1002 * exceptions:
1003 * - Registers out of use, including also registers marked with 'Debug'.
1004 * These have no effect on the driver's operation, so we don't save/restore
1005 * them to reduce the overhead.
1006 * - Registers that are fully setup by an initialization function called from
1007 * the resume path. For example many clock gating and RPS/RC6 registers.
1008 * - Registers that provide the right functionality with their reset defaults.
1009 *
1010 * TODO: Except for registers that based on the above 3 criteria can be safely
1011 * ignored, we save/restore all others, practically treating the HW context as
1012 * a black-box for the driver. Further investigation is needed to reduce the
1013 * saved/restored registers even further, by following the same 3 criteria.
1014 */
1015static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1016{
1017 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1018 int i;
1019
1020 /* GAM 0x4000-0x4770 */
1021 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1022 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1023 s->arb_mode = I915_READ(ARB_MODE);
1024 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1025 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1026
1027 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1028 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1029
1030 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1031 s->gfx_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1032
1033 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1034 s->ecochk = I915_READ(GAM_ECOCHK);
1035 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1036 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1037
1038 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1039
1040 /* MBC 0x9024-0x91D0, 0x8500 */
1041 s->g3dctl = I915_READ(VLV_G3DCTL);
1042 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1043 s->mbctl = I915_READ(GEN6_MBCTL);
1044
1045 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1046 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1047 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1048 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1049 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1050 s->rstctl = I915_READ(GEN6_RSTCTL);
1051 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1052
1053 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1054 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1055 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1056 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1057 s->ecobus = I915_READ(ECOBUS);
1058 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1059 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1060 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1061 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1062 s->rcedata = I915_READ(VLV_RCEDATA);
1063 s->spare2gh = I915_READ(VLV_SPAREG2H);
1064
1065 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1066 s->gt_imr = I915_READ(GTIMR);
1067 s->gt_ier = I915_READ(GTIER);
1068 s->pm_imr = I915_READ(GEN6_PMIMR);
1069 s->pm_ier = I915_READ(GEN6_PMIER);
1070
1071 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1072 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1073
1074 /* GT SA CZ domain, 0x100000-0x138124 */
1075 s->tilectl = I915_READ(TILECTL);
1076 s->gt_fifoctl = I915_READ(GTFIFOCTL);
1077 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1078 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1079 s->pmwgicz = I915_READ(VLV_PMWGICZ);
1080
1081 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1082 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1083 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
1084 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1085
1086 /*
1087 * Not saving any of:
1088 * DFT, 0x9800-0x9EC0
1089 * SARB, 0xB000-0xB1FC
1090 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1091 * PCI CFG
1092 */
1093}
1094
1095static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1096{
1097 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1098 u32 val;
1099 int i;
1100
1101 /* GAM 0x4000-0x4770 */
1102 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1103 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1104 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1105 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1106 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1107
1108 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1109 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1110
1111 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1112 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1113
1114 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1115 I915_WRITE(GAM_ECOCHK, s->ecochk);
1116 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1117 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1118
1119 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1120
1121 /* MBC 0x9024-0x91D0, 0x8500 */
1122 I915_WRITE(VLV_G3DCTL, s->g3dctl);
1123 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1124 I915_WRITE(GEN6_MBCTL, s->mbctl);
1125
1126 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1127 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1128 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1129 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1130 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1131 I915_WRITE(GEN6_RSTCTL, s->rstctl);
1132 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1133
1134 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1135 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1136 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1137 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1138 I915_WRITE(ECOBUS, s->ecobus);
1139 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1140 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1141 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1142 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1143 I915_WRITE(VLV_RCEDATA, s->rcedata);
1144 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1145
1146 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1147 I915_WRITE(GTIMR, s->gt_imr);
1148 I915_WRITE(GTIER, s->gt_ier);
1149 I915_WRITE(GEN6_PMIMR, s->pm_imr);
1150 I915_WRITE(GEN6_PMIER, s->pm_ier);
1151
1152 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1153 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1154
1155 /* GT SA CZ domain, 0x100000-0x138124 */
1156 I915_WRITE(TILECTL, s->tilectl);
1157 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1158 /*
1159 * Preserve the GT allow wake and GFX force clock bit, they are not
1160 * be restored, as they are used to control the s0ix suspend/resume
1161 * sequence by the caller.
1162 */
1163 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1164 val &= VLV_GTLC_ALLOWWAKEREQ;
1165 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1166 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1167
1168 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1169 val &= VLV_GFX_CLK_FORCE_ON_BIT;
1170 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1171 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1172
1173 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1174
1175 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1176 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1177 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
1178 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1179}
1180
Imre Deak650ad972014-04-18 16:35:02 +03001181int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1182{
1183 u32 val;
1184 int err;
1185
1186 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1187 WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1188
1189#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1190 /* Wait for a previous force-off to settle */
1191 if (force_on) {
Imre Deak8d4eee92014-04-14 20:24:43 +03001192 err = wait_for(!COND, 20);
Imre Deak650ad972014-04-18 16:35:02 +03001193 if (err) {
1194 DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1195 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1196 return err;
1197 }
1198 }
1199
1200 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1201 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1202 if (force_on)
1203 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1204 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1205
1206 if (!force_on)
1207 return 0;
1208
Imre Deak8d4eee92014-04-14 20:24:43 +03001209 err = wait_for(COND, 20);
Imre Deak650ad972014-04-18 16:35:02 +03001210 if (err)
1211 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1212 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1213
1214 return err;
1215#undef COND
1216}
1217
Imre Deakddeea5b2014-05-05 15:19:56 +03001218static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1219{
1220 u32 val;
1221 int err = 0;
1222
1223 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1224 val &= ~VLV_GTLC_ALLOWWAKEREQ;
1225 if (allow)
1226 val |= VLV_GTLC_ALLOWWAKEREQ;
1227 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1228 POSTING_READ(VLV_GTLC_WAKE_CTRL);
1229
1230#define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1231 allow)
1232 err = wait_for(COND, 1);
1233 if (err)
1234 DRM_ERROR("timeout disabling GT waking\n");
1235 return err;
1236#undef COND
1237}
1238
1239static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1240 bool wait_for_on)
1241{
1242 u32 mask;
1243 u32 val;
1244 int err;
1245
1246 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1247 val = wait_for_on ? mask : 0;
1248#define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1249 if (COND)
1250 return 0;
1251
1252 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1253 wait_for_on ? "on" : "off",
1254 I915_READ(VLV_GTLC_PW_STATUS));
1255
1256 /*
1257 * RC6 transitioning can be delayed up to 2 msec (see
1258 * valleyview_enable_rps), use 3 msec for safety.
1259 */
1260 err = wait_for(COND, 3);
1261 if (err)
1262 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1263 wait_for_on ? "on" : "off");
1264
1265 return err;
1266#undef COND
1267}
1268
1269static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1270{
1271 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1272 return;
1273
1274 DRM_ERROR("GT register access while GT waking disabled\n");
1275 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1276}
1277
Sagar Kambleebc32822014-08-13 23:07:05 +05301278static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
Imre Deakddeea5b2014-05-05 15:19:56 +03001279{
1280 u32 mask;
1281 int err;
1282
1283 /*
1284 * Bspec defines the following GT well on flags as debug only, so
1285 * don't treat them as hard failures.
1286 */
1287 (void)vlv_wait_for_gt_wells(dev_priv, false);
1288
1289 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1290 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1291
1292 vlv_check_no_gt_access(dev_priv);
1293
1294 err = vlv_force_gfx_clock(dev_priv, true);
1295 if (err)
1296 goto err1;
1297
1298 err = vlv_allow_gt_wake(dev_priv, false);
1299 if (err)
1300 goto err2;
1301 vlv_save_gunit_s0ix_state(dev_priv);
1302
1303 err = vlv_force_gfx_clock(dev_priv, false);
1304 if (err)
1305 goto err2;
1306
1307 return 0;
1308
1309err2:
1310 /* For safety always re-enable waking and disable gfx clock forcing */
1311 vlv_allow_gt_wake(dev_priv, true);
1312err1:
1313 vlv_force_gfx_clock(dev_priv, false);
1314
1315 return err;
1316}
1317
Sagar Kambleebc32822014-08-13 23:07:05 +05301318static int vlv_resume_prepare(struct drm_i915_private *dev_priv)
Imre Deakddeea5b2014-05-05 15:19:56 +03001319{
1320 struct drm_device *dev = dev_priv->dev;
1321 int err;
1322 int ret;
1323
1324 /*
1325 * If any of the steps fail just try to continue, that's the best we
1326 * can do at this point. Return the first error code (which will also
1327 * leave RPM permanently disabled).
1328 */
1329 ret = vlv_force_gfx_clock(dev_priv, true);
1330
1331 vlv_restore_gunit_s0ix_state(dev_priv);
1332
1333 err = vlv_allow_gt_wake(dev_priv, true);
1334 if (!ret)
1335 ret = err;
1336
1337 err = vlv_force_gfx_clock(dev_priv, false);
1338 if (!ret)
1339 ret = err;
1340
1341 vlv_check_no_gt_access(dev_priv);
1342
1343 intel_init_clock_gating(dev);
1344 i915_gem_restore_fences(dev);
1345
1346 return ret;
1347}
1348
Paulo Zanoni97bea202014-03-07 20:12:33 -03001349static int intel_runtime_suspend(struct device *device)
Paulo Zanoni8a187452013-12-06 20:32:13 -02001350{
1351 struct pci_dev *pdev = to_pci_dev(device);
1352 struct drm_device *dev = pci_get_drvdata(pdev);
1353 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001354 int ret;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001355
Imre Deakaeab0b52014-04-14 20:24:36 +03001356 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
Imre Deakc6df39b2014-04-14 20:24:29 +03001357 return -ENODEV;
1358
Paulo Zanoni8a187452013-12-06 20:32:13 -02001359 WARN_ON(!HAS_RUNTIME_PM(dev));
Paulo Zanonie998c402014-02-21 13:52:26 -03001360 assert_force_wake_inactive(dev_priv);
Paulo Zanoni8a187452013-12-06 20:32:13 -02001361
1362 DRM_DEBUG_KMS("Suspending device\n");
1363
Imre Deak9486db62014-04-22 20:21:07 +03001364 /*
Imre Deakd6102972014-05-07 19:57:49 +03001365 * We could deadlock here in case another thread holding struct_mutex
1366 * calls RPM suspend concurrently, since the RPM suspend will wait
1367 * first for this RPM suspend to finish. In this case the concurrent
1368 * RPM resume will be followed by its RPM suspend counterpart. Still
1369 * for consistency return -EAGAIN, which will reschedule this suspend.
1370 */
1371 if (!mutex_trylock(&dev->struct_mutex)) {
1372 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1373 /*
1374 * Bump the expiration timestamp, otherwise the suspend won't
1375 * be rescheduled.
1376 */
1377 pm_runtime_mark_last_busy(device);
1378
1379 return -EAGAIN;
1380 }
1381 /*
1382 * We are safe here against re-faults, since the fault handler takes
1383 * an RPM reference.
1384 */
1385 i915_gem_release_all_mmaps(dev_priv);
1386 mutex_unlock(&dev->struct_mutex);
1387
1388 /*
Imre Deak9486db62014-04-22 20:21:07 +03001389 * rps.work can't be rearmed here, since we get here only after making
1390 * sure the GPU is idle and the RPS freq is set to the minimum. See
1391 * intel_mark_idle().
1392 */
1393 cancel_work_sync(&dev_priv->rps.work);
Imre Deakb5478bc2014-04-14 20:24:37 +03001394 intel_runtime_pm_disable_interrupts(dev);
1395
Sagar Kambleebc32822014-08-13 23:07:05 +05301396 ret = intel_suspend_complete(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001397 if (ret) {
1398 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1399 intel_runtime_pm_restore_interrupts(dev);
1400
1401 return ret;
1402 }
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001403
Paulo Zanoni16a3d6e2013-12-13 15:22:30 -02001404 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
Paulo Zanoni8a187452013-12-06 20:32:13 -02001405 dev_priv->pm.suspended = true;
Kristen Carlson Accardi1fb23622014-01-14 15:36:15 -08001406
1407 /*
1408 * current versions of firmware which depend on this opregion
1409 * notification have repurposed the D1 definition to mean
1410 * "runtime suspended" vs. what you would normally expect (D3)
1411 * to distinguish it from notifications that might be sent
1412 * via the suspend path.
1413 */
1414 intel_opregion_notify_adapter(dev, PCI_D1);
Paulo Zanoni8a187452013-12-06 20:32:13 -02001415
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001416 DRM_DEBUG_KMS("Device suspended\n");
Paulo Zanoni8a187452013-12-06 20:32:13 -02001417 return 0;
1418}
1419
Paulo Zanoni97bea202014-03-07 20:12:33 -03001420static int intel_runtime_resume(struct device *device)
Paulo Zanoni8a187452013-12-06 20:32:13 -02001421{
1422 struct pci_dev *pdev = to_pci_dev(device);
1423 struct drm_device *dev = pci_get_drvdata(pdev);
1424 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001425 int ret;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001426
1427 WARN_ON(!HAS_RUNTIME_PM(dev));
1428
1429 DRM_DEBUG_KMS("Resuming device\n");
1430
Paulo Zanonicd2e9e92013-12-06 20:34:21 -02001431 intel_opregion_notify_adapter(dev, PCI_D0);
Paulo Zanoni8a187452013-12-06 20:32:13 -02001432 dev_priv->pm.suspended = false;
1433
Sagar Kambleebc32822014-08-13 23:07:05 +05301434 ret = intel_resume_prepare(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001435 /*
1436 * No point of rolling back things in case of an error, as the best
1437 * we can do is to hope that things will still work (and disable RPM).
1438 */
Imre Deak92b806d2014-04-14 20:24:39 +03001439 i915_gem_init_swizzling(dev);
1440 gen6_update_ring_freq(dev);
1441
Imre Deakb5478bc2014-04-14 20:24:37 +03001442 intel_runtime_pm_restore_interrupts(dev);
Imre Deak9486db62014-04-22 20:21:07 +03001443 intel_reset_gt_powersave(dev);
Imre Deakb5478bc2014-04-14 20:24:37 +03001444
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001445 if (ret)
1446 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1447 else
1448 DRM_DEBUG_KMS("Device resumed\n");
1449
1450 return ret;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001451}
1452
Sagar Kambleebc32822014-08-13 23:07:05 +05301453static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1454{
1455 struct drm_device *dev = dev_priv->dev;
1456 int ret;
1457
1458 if (IS_GEN6(dev)) {
1459 ret = 0;
1460 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1461 ret = hsw_suspend_complete(dev_priv);
1462 } else if (IS_VALLEYVIEW(dev)) {
1463 ret = vlv_suspend_complete(dev_priv);
1464 } else {
1465 ret = -ENODEV;
1466 WARN_ON(1);
1467 }
1468
1469 return ret;
1470}
1471
1472static int intel_resume_prepare(struct drm_i915_private *dev_priv)
1473{
1474 struct drm_device *dev = dev_priv->dev;
1475 int ret;
1476
1477 if (IS_GEN6(dev)) {
1478 ret = snb_resume_prepare(dev_priv);
1479 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1480 ret = hsw_resume_prepare(dev_priv);
1481 } else if (IS_VALLEYVIEW(dev)) {
1482 ret = vlv_resume_prepare(dev_priv);
1483 } else {
1484 WARN_ON(1);
1485 ret = -ENODEV;
1486 }
1487
1488 return ret;
1489}
1490
Chris Wilsonb4b78d12010-06-06 15:40:20 +01001491static const struct dev_pm_ops i915_pm_ops = {
Akshay Joshi0206e352011-08-16 15:34:10 -04001492 .suspend = i915_pm_suspend,
Imre Deak76c4b252014-04-01 19:55:22 +03001493 .suspend_late = i915_pm_suspend_late,
1494 .resume_early = i915_pm_resume_early,
Akshay Joshi0206e352011-08-16 15:34:10 -04001495 .resume = i915_pm_resume,
1496 .freeze = i915_pm_freeze,
Imre Deak76c4b252014-04-01 19:55:22 +03001497 .thaw_early = i915_pm_thaw_early,
Akshay Joshi0206e352011-08-16 15:34:10 -04001498 .thaw = i915_pm_thaw,
1499 .poweroff = i915_pm_poweroff,
Imre Deak76c4b252014-04-01 19:55:22 +03001500 .restore_early = i915_pm_resume_early,
Akshay Joshi0206e352011-08-16 15:34:10 -04001501 .restore = i915_pm_resume,
Paulo Zanoni97bea202014-03-07 20:12:33 -03001502 .runtime_suspend = intel_runtime_suspend,
1503 .runtime_resume = intel_runtime_resume,
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001504};
1505
Laurent Pinchart78b68552012-05-17 13:27:22 +02001506static const struct vm_operations_struct i915_gem_vm_ops = {
Jesse Barnesde151cf2008-11-12 10:03:55 -08001507 .fault = i915_gem_fault,
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001508 .open = drm_gem_vm_open,
1509 .close = drm_gem_vm_close,
Jesse Barnesde151cf2008-11-12 10:03:55 -08001510};
1511
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001512static const struct file_operations i915_driver_fops = {
1513 .owner = THIS_MODULE,
1514 .open = drm_open,
1515 .release = drm_release,
1516 .unlocked_ioctl = drm_ioctl,
1517 .mmap = drm_gem_mmap,
1518 .poll = drm_poll,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001519 .read = drm_read,
1520#ifdef CONFIG_COMPAT
1521 .compat_ioctl = i915_compat_ioctl,
1522#endif
1523 .llseek = noop_llseek,
1524};
1525
Linus Torvalds1da177e2005-04-16 15:20:36 -07001526static struct drm_driver driver = {
Michael Witten0c547812011-08-25 17:55:54 +00001527 /* Don't use MTRRs here; the Xserver or userspace app should
1528 * deal with them for Intel hardware.
Dave Airlie792d2b92005-11-11 23:30:27 +11001529 */
Eric Anholt673a3942008-07-30 12:06:12 -07001530 .driver_features =
Daniel Vetter24986ee2013-12-11 11:34:33 +01001531 DRIVER_USE_AGP |
Kristian Høgsberg10ba5012013-08-25 18:29:01 +02001532 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1533 DRIVER_RENDER,
Dave Airlie22eae942005-11-10 22:16:34 +11001534 .load = i915_driver_load,
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001535 .unload = i915_driver_unload,
Eric Anholt673a3942008-07-30 12:06:12 -07001536 .open = i915_driver_open,
Dave Airlie22eae942005-11-10 22:16:34 +11001537 .lastclose = i915_driver_lastclose,
1538 .preclose = i915_driver_preclose,
Eric Anholt673a3942008-07-30 12:06:12 -07001539 .postclose = i915_driver_postclose,
Rafael J. Wysockid8e29202010-01-09 00:45:33 +01001540
1541 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1542 .suspend = i915_suspend,
Imre Deak76c4b252014-04-01 19:55:22 +03001543 .resume = i915_resume_legacy,
Rafael J. Wysockid8e29202010-01-09 00:45:33 +01001544
Dave Airliecda17382005-07-10 17:31:26 +10001545 .device_is_agp = i915_driver_device_is_agp,
Dave Airlie7c1c2872008-11-28 14:22:24 +10001546 .master_create = i915_master_create,
1547 .master_destroy = i915_master_destroy,
Ben Gamari955b12d2009-02-17 20:08:49 -05001548#if defined(CONFIG_DEBUG_FS)
Ben Gamari27c202a2009-07-01 22:26:52 -04001549 .debugfs_init = i915_debugfs_init,
1550 .debugfs_cleanup = i915_debugfs_cleanup,
Ben Gamari955b12d2009-02-17 20:08:49 -05001551#endif
Eric Anholt673a3942008-07-30 12:06:12 -07001552 .gem_free_object = i915_gem_free_object,
Jesse Barnesde151cf2008-11-12 10:03:55 -08001553 .gem_vm_ops = &i915_gem_vm_ops,
Daniel Vetter1286ff72012-05-10 15:25:09 +02001554
1555 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1556 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1557 .gem_prime_export = i915_gem_prime_export,
1558 .gem_prime_import = i915_gem_prime_import,
1559
Dave Airlieff72145b2011-02-07 12:16:14 +10001560 .dumb_create = i915_gem_dumb_create,
1561 .dumb_map_offset = i915_gem_mmap_gtt,
Daniel Vetter43387b32013-07-16 09:12:04 +02001562 .dumb_destroy = drm_gem_dumb_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001563 .ioctls = i915_ioctls,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001564 .fops = &i915_driver_fops,
Dave Airlie22eae942005-11-10 22:16:34 +11001565 .name = DRIVER_NAME,
1566 .desc = DRIVER_DESC,
1567 .date = DRIVER_DATE,
1568 .major = DRIVER_MAJOR,
1569 .minor = DRIVER_MINOR,
1570 .patchlevel = DRIVER_PATCHLEVEL,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001571};
1572
Dave Airlie8410ea32010-12-15 03:16:38 +10001573static struct pci_driver i915_pci_driver = {
1574 .name = DRIVER_NAME,
1575 .id_table = pciidlist,
1576 .probe = i915_pci_probe,
1577 .remove = i915_pci_remove,
1578 .driver.pm = &i915_pm_ops,
1579};
1580
Linus Torvalds1da177e2005-04-16 15:20:36 -07001581static int __init i915_init(void)
1582{
1583 driver.num_ioctls = i915_max_ioctl;
Jesse Barnes79e53942008-11-07 14:24:08 -08001584
1585 /*
1586 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1587 * explicitly disabled with the module pararmeter.
1588 *
1589 * Otherwise, just follow the parameter (defaulting to off).
1590 *
1591 * Allow optional vga_text_mode_force boot option to override
1592 * the default behavior.
1593 */
1594#if defined(CONFIG_DRM_I915_KMS)
Jani Nikulad330a952014-01-21 11:24:25 +02001595 if (i915.modeset != 0)
Jesse Barnes79e53942008-11-07 14:24:08 -08001596 driver.driver_features |= DRIVER_MODESET;
1597#endif
Jani Nikulad330a952014-01-21 11:24:25 +02001598 if (i915.modeset == 1)
Jesse Barnes79e53942008-11-07 14:24:08 -08001599 driver.driver_features |= DRIVER_MODESET;
1600
1601#ifdef CONFIG_VGA_CONSOLE
Jani Nikulad330a952014-01-21 11:24:25 +02001602 if (vgacon_text_force() && i915.modeset == -1)
Jesse Barnes79e53942008-11-07 14:24:08 -08001603 driver.driver_features &= ~DRIVER_MODESET;
1604#endif
1605
Daniel Vetterb30324a2013-11-13 22:11:25 +01001606 if (!(driver.driver_features & DRIVER_MODESET)) {
Chris Wilson3885c6b2011-01-23 10:45:14 +00001607 driver.get_vblank_timestamp = NULL;
Daniel Vetterb30324a2013-11-13 22:11:25 +01001608#ifndef CONFIG_DRM_I915_UMS
1609 /* Silently fail loading to not upset userspace. */
Jani Nikulac9cd7b62014-06-02 16:58:30 +03001610 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
Daniel Vetterb30324a2013-11-13 22:11:25 +01001611 return 0;
1612#endif
1613 }
Chris Wilson3885c6b2011-01-23 10:45:14 +00001614
Dave Airlie8410ea32010-12-15 03:16:38 +10001615 return drm_pci_init(&driver, &i915_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001616}
1617
1618static void __exit i915_exit(void)
1619{
Daniel Vetterb33ecdd2013-11-15 17:16:33 +01001620#ifndef CONFIG_DRM_I915_UMS
1621 if (!(driver.driver_features & DRIVER_MODESET))
1622 return; /* Never loaded a driver. */
1623#endif
1624
Dave Airlie8410ea32010-12-15 03:16:38 +10001625 drm_pci_exit(&driver, &i915_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001626}
1627
1628module_init(i915_init);
1629module_exit(i915_exit);
1630
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001631MODULE_AUTHOR(DRIVER_AUTHOR);
1632MODULE_DESCRIPTION(DRIVER_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001633MODULE_LICENSE("GPL and additional rights");