blob: 8d2d140d79107f44383fe3f823349ca22cacaf37 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Petr Machata803335a2018-02-27 14:53:46 +01003 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
Jiri Pirko22a67762017-02-03 10:29:07 +01004 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +020056#include <linux/netlink.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020057#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020058#include <net/pkt_cls.h>
59#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020060#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010061#include <net/tc_act/tc_sample.h>
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +020062#include <net/addrconf.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020063
64#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020065#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020066#include "core.h"
67#include "reg.h"
68#include "port.h"
69#include "trap.h"
70#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010071#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020072#include "spectrum_dpipe.h"
Yotam Gigid3b939b2017-09-19 10:00:09 +020073#include "spectrum_acl_flex_actions.h"
Petr Machataa629ef22018-02-13 11:27:48 +010074#include "spectrum_span.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020075#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020076
Yotam Gigi6b742192017-05-23 21:56:29 +020077#define MLXSW_FWREV_MAJOR 13
Shalom Toledo2f53fbd2017-11-12 09:01:24 +010078#define MLXSW_FWREV_MINOR 1530
79#define MLXSW_FWREV_SUBMINOR 152
Yuval Mintzfd5204c2018-01-18 12:55:23 +010080#define MLXSW_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
Yotam Gigi6b742192017-05-23 21:56:29 +020081
82#define MLXSW_SP_FW_FILENAME \
Yotam Gigia4e1ce22017-06-04 16:49:58 +020083 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
Yotam Gigi6b742192017-05-23 21:56:29 +020084 "." __stringify(MLXSW_FWREV_MINOR) \
85 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
86
Jiri Pirko56ade8f2015-10-16 14:01:37 +020087static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
88static const char mlxsw_sp_driver_version[] = "1.0";
89
90/* tx_hdr_version
91 * Tx header version.
92 * Must be set to 1.
93 */
94MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
95
96/* tx_hdr_ctl
97 * Packet control type.
98 * 0 - Ethernet control (e.g. EMADs, LACP)
99 * 1 - Ethernet data
100 */
101MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
102
103/* tx_hdr_proto
104 * Packet protocol type. Must be set to 1 (Ethernet).
105 */
106MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
107
108/* tx_hdr_rx_is_router
109 * Packet is sent from the router. Valid for data packets only.
110 */
111MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
112
113/* tx_hdr_fid_valid
114 * Indicates if the 'fid' field is valid and should be used for
115 * forwarding lookup. Valid for data packets only.
116 */
117MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
118
119/* tx_hdr_swid
120 * Switch partition ID. Must be set to 0.
121 */
122MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
123
124/* tx_hdr_control_tclass
125 * Indicates if the packet should use the control TClass and not one
126 * of the data TClasses.
127 */
128MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
129
130/* tx_hdr_etclass
131 * Egress TClass to be used on the egress device on the egress port.
132 */
133MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
134
135/* tx_hdr_port_mid
136 * Destination local port for unicast packets.
137 * Destination multicast ID for multicast packets.
138 *
139 * Control packets are directed to a specific egress port, while data
140 * packets are transmitted through the CPU port (0) into the switch partition,
141 * where forwarding rules are applied.
142 */
143MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
144
145/* tx_hdr_fid
146 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
147 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
148 * Valid for data packets only.
149 */
150MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
151
152/* tx_hdr_type
153 * 0 - Data packets
154 * 6 - Control packets
155 */
156MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
157
Yotam Gigie5e5c882017-05-23 21:56:27 +0200158struct mlxsw_sp_mlxfw_dev {
159 struct mlxfw_dev mlxfw_dev;
160 struct mlxsw_sp *mlxsw_sp;
161};
162
163static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
164 u16 component_index, u32 *p_max_size,
165 u8 *p_align_bits, u16 *p_max_write_size)
166{
167 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
168 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
169 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
170 char mcqi_pl[MLXSW_REG_MCQI_LEN];
171 int err;
172
173 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
174 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
175 if (err)
176 return err;
177 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
178 p_max_write_size);
179
180 *p_align_bits = max_t(u8, *p_align_bits, 2);
181 *p_max_write_size = min_t(u16, *p_max_write_size,
182 MLXSW_REG_MCDA_MAX_DATA_LEN);
183 return 0;
184}
185
186static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
187{
188 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
189 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
190 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
191 char mcc_pl[MLXSW_REG_MCC_LEN];
192 u8 control_state;
193 int err;
194
195 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
196 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
197 if (err)
198 return err;
199
200 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
201 if (control_state != MLXFW_FSM_STATE_IDLE)
202 return -EBUSY;
203
204 mlxsw_reg_mcc_pack(mcc_pl,
205 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
206 0, *fwhandle, 0);
207 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
208}
209
210static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
211 u32 fwhandle, u16 component_index,
212 u32 component_size)
213{
214 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
215 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
217 char mcc_pl[MLXSW_REG_MCC_LEN];
218
219 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
220 component_index, fwhandle, component_size);
221 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
222}
223
224static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
225 u32 fwhandle, u8 *data, u16 size,
226 u32 offset)
227{
228 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
229 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
230 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
231 char mcda_pl[MLXSW_REG_MCDA_LEN];
232
233 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
234 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
235}
236
237static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
238 u32 fwhandle, u16 component_index)
239{
240 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
241 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
242 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
243 char mcc_pl[MLXSW_REG_MCC_LEN];
244
245 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
246 component_index, fwhandle, 0);
247 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
248}
249
250static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
251{
252 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
253 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
254 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
255 char mcc_pl[MLXSW_REG_MCC_LEN];
256
257 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
258 fwhandle, 0);
259 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
260}
261
262static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
263 enum mlxfw_fsm_state *fsm_state,
264 enum mlxfw_fsm_state_err *fsm_state_err)
265{
266 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
267 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
268 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
269 char mcc_pl[MLXSW_REG_MCC_LEN];
270 u8 control_state;
271 u8 error_code;
272 int err;
273
274 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
275 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
276 if (err)
277 return err;
278
279 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
280 *fsm_state = control_state;
281 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
282 MLXFW_FSM_STATE_ERR_MAX);
283 return 0;
284}
285
286static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
287{
288 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
289 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
290 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
291 char mcc_pl[MLXSW_REG_MCC_LEN];
292
293 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
294 fwhandle, 0);
295 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
296}
297
298static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
299{
300 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
301 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
302 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
303 char mcc_pl[MLXSW_REG_MCC_LEN];
304
305 mlxsw_reg_mcc_pack(mcc_pl,
306 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
307 fwhandle, 0);
308 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
309}
310
311static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
312 .component_query = mlxsw_sp_component_query,
313 .fsm_lock = mlxsw_sp_fsm_lock,
314 .fsm_component_update = mlxsw_sp_fsm_component_update,
315 .fsm_block_download = mlxsw_sp_fsm_block_download,
316 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
317 .fsm_activate = mlxsw_sp_fsm_activate,
318 .fsm_query_state = mlxsw_sp_fsm_query_state,
319 .fsm_cancel = mlxsw_sp_fsm_cancel,
320 .fsm_release = mlxsw_sp_fsm_release
321};
322
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300323static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
324 const struct firmware *firmware)
325{
326 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
327 .mlxfw_dev = {
328 .ops = &mlxsw_sp_mlxfw_dev_ops,
329 .psid = mlxsw_sp->bus_info->psid,
330 .psid_size = strlen(mlxsw_sp->bus_info->psid),
331 },
332 .mlxsw_sp = mlxsw_sp
333 };
334
335 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
336}
337
Yotam Gigi6b742192017-05-23 21:56:29 +0200338static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
339{
340 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
Yotam Gigi6b742192017-05-23 21:56:29 +0200341 const struct firmware *firmware;
342 int err;
343
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100344 /* Validate driver & FW are compatible */
345 if (rev->major != MLXSW_FWREV_MAJOR) {
346 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
347 rev->major, MLXSW_FWREV_MAJOR);
348 return -EINVAL;
349 }
350 if (MLXSW_FWREV_MINOR_TO_BRANCH(rev->minor) ==
351 MLXSW_FWREV_MINOR_TO_BRANCH(MLXSW_FWREV_MINOR))
Yotam Gigi6b742192017-05-23 21:56:29 +0200352 return 0;
353
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100354 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200355 rev->major, rev->minor, rev->subminor);
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100356 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200357 MLXSW_SP_FW_FILENAME);
358
359 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
360 mlxsw_sp->bus_info->dev);
361 if (err) {
362 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
363 MLXSW_SP_FW_FILENAME);
364 return err;
365 }
366
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300367 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
Yotam Gigi6b742192017-05-23 21:56:29 +0200368 release_firmware(firmware);
369 return err;
370}
371
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100372int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
373 unsigned int counter_index, u64 *packets,
374 u64 *bytes)
375{
376 char mgpc_pl[MLXSW_REG_MGPC_LEN];
377 int err;
378
379 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200380 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100381 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
382 if (err)
383 return err;
Arkadi Sharshevsky7cfcbc72017-08-24 08:40:08 +0200384 if (packets)
385 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
386 if (bytes)
387 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100388 return 0;
389}
390
391static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
392 unsigned int counter_index)
393{
394 char mgpc_pl[MLXSW_REG_MGPC_LEN];
395
396 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200397 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100398 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
399}
400
401int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
402 unsigned int *p_counter_index)
403{
404 int err;
405
406 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
407 p_counter_index);
408 if (err)
409 return err;
410 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
411 if (err)
412 goto err_counter_clear;
413 return 0;
414
415err_counter_clear:
416 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
417 *p_counter_index);
418 return err;
419}
420
421void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
422 unsigned int counter_index)
423{
424 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
425 counter_index);
426}
427
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200428static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
429 const struct mlxsw_tx_info *tx_info)
430{
431 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
432
433 memset(txhdr, 0, MLXSW_TXHDR_LEN);
434
435 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
436 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
437 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
438 mlxsw_tx_hdr_swid_set(txhdr, 0);
439 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
440 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
441 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
442}
443
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200444int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
445 u8 state)
446{
447 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
448 enum mlxsw_reg_spms_state spms_state;
449 char *spms_pl;
450 int err;
451
452 switch (state) {
453 case BR_STATE_FORWARDING:
454 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
455 break;
456 case BR_STATE_LEARNING:
457 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
458 break;
459 case BR_STATE_LISTENING: /* fall-through */
460 case BR_STATE_DISABLED: /* fall-through */
461 case BR_STATE_BLOCKING:
462 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
463 break;
464 default:
465 BUG();
466 }
467
468 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
469 if (!spms_pl)
470 return -ENOMEM;
471 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
472 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
473
474 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
475 kfree(spms_pl);
476 return err;
477}
478
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200479static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
480{
Elad Raz5b090742016-10-28 21:35:46 +0200481 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200482 int err;
483
484 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
485 if (err)
486 return err;
487 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
488 return 0;
489}
490
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100491static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
492 bool enable, u32 rate)
493{
494 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
495 char mpsc_pl[MLXSW_REG_MPSC_LEN];
496
497 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
498 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
499}
500
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200501static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
502 bool is_up)
503{
504 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
505 char paos_pl[MLXSW_REG_PAOS_LEN];
506
507 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
508 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
509 MLXSW_PORT_ADMIN_STATUS_DOWN);
510 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
511}
512
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200513static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
514 unsigned char *addr)
515{
516 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
517 char ppad_pl[MLXSW_REG_PPAD_LEN];
518
519 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
520 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
521 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
522}
523
524static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
525{
526 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
527 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
528
529 ether_addr_copy(addr, mlxsw_sp->base_mac);
530 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
531 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
532}
533
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200534static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
535{
536 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
537 char pmtu_pl[MLXSW_REG_PMTU_LEN];
538 int max_mtu;
539 int err;
540
541 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
542 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
543 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
544 if (err)
545 return err;
546 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
547
548 if (mtu > max_mtu)
549 return -EINVAL;
550
551 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
552 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
553}
554
555static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
556{
557 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel5b153852017-06-08 08:47:44 +0200558 char pspa_pl[MLXSW_REG_PSPA_LEN];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200559
Ido Schimmel5b153852017-06-08 08:47:44 +0200560 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
561 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200562}
563
Ido Schimmela1107482017-05-26 08:37:39 +0200564int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200565{
566 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
567 char svpe_pl[MLXSW_REG_SVPE_LEN];
568
569 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
570 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
571}
572
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200573int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
574 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200575{
576 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
577 char *spvmlr_pl;
578 int err;
579
580 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
581 if (!spvmlr_pl)
582 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200583 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
584 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200585 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
586 kfree(spvmlr_pl);
587 return err;
588}
589
Ido Schimmelb02eae92017-05-16 19:38:34 +0200590static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
591 u16 vid)
592{
593 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
594 char spvid_pl[MLXSW_REG_SPVID_LEN];
595
596 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
597 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
598}
599
600static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
601 bool allow)
602{
603 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
604 char spaft_pl[MLXSW_REG_SPAFT_LEN];
605
606 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
607 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
608}
609
610int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
611{
612 int err;
613
614 if (!vid) {
615 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
616 if (err)
617 return err;
618 } else {
619 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
620 if (err)
621 return err;
622 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
623 if (err)
624 goto err_port_allow_untagged_set;
625 }
626
627 mlxsw_sp_port->pvid = vid;
628 return 0;
629
630err_port_allow_untagged_set:
631 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
632 return err;
633}
634
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200635static int
636mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
637{
638 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
639 char sspr_pl[MLXSW_REG_SSPR_LEN];
640
641 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
642 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
643}
644
Ido Schimmeld664b412016-06-09 09:51:40 +0200645static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
646 u8 local_port, u8 *p_module,
647 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200648{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200649 char pmlp_pl[MLXSW_REG_PMLP_LEN];
650 int err;
651
Ido Schimmel558c2d52016-02-26 17:32:29 +0100652 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200653 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
654 if (err)
655 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100656 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
657 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200658 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200659 return 0;
660}
661
Ido Schimmel2e915e02017-06-08 08:47:45 +0200662static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100663 u8 module, u8 width, u8 lane)
664{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200665 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel18f1e702016-02-26 17:32:31 +0100666 char pmlp_pl[MLXSW_REG_PMLP_LEN];
667 int i;
668
Ido Schimmel2e915e02017-06-08 08:47:45 +0200669 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel18f1e702016-02-26 17:32:31 +0100670 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
671 for (i = 0; i < width; i++) {
672 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
673 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
674 }
675
676 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
677}
678
Ido Schimmel2e915e02017-06-08 08:47:45 +0200679static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100680{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200681 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100682 char pmlp_pl[MLXSW_REG_PMLP_LEN];
683
Ido Schimmel2e915e02017-06-08 08:47:45 +0200684 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100685 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
686 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
687}
688
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200689static int mlxsw_sp_port_open(struct net_device *dev)
690{
691 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
692 int err;
693
694 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
695 if (err)
696 return err;
697 netif_start_queue(dev);
698 return 0;
699}
700
701static int mlxsw_sp_port_stop(struct net_device *dev)
702{
703 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
704
705 netif_stop_queue(dev);
706 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
707}
708
709static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
710 struct net_device *dev)
711{
712 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
713 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
714 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
715 const struct mlxsw_tx_info tx_info = {
716 .local_port = mlxsw_sp_port->local_port,
717 .is_emad = false,
718 };
719 u64 len;
720 int err;
721
Jiri Pirko307c2432016-04-08 19:11:22 +0200722 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200723 return NETDEV_TX_BUSY;
724
725 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
726 struct sk_buff *skb_orig = skb;
727
728 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
729 if (!skb) {
730 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
731 dev_kfree_skb_any(skb_orig);
732 return NETDEV_TX_OK;
733 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +0100734 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200735 }
736
737 if (eth_skb_pad(skb)) {
738 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
739 return NETDEV_TX_OK;
740 }
741
742 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +0200743 /* TX header is consumed by HW on the way so we shouldn't count its
744 * bytes as being sent.
745 */
746 len = skb->len - MLXSW_TXHDR_LEN;
747
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200748 /* Due to a race we might fail here because of a full queue. In that
749 * unlikely case we simply drop the packet.
750 */
Jiri Pirko307c2432016-04-08 19:11:22 +0200751 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200752
753 if (!err) {
754 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
755 u64_stats_update_begin(&pcpu_stats->syncp);
756 pcpu_stats->tx_packets++;
757 pcpu_stats->tx_bytes += len;
758 u64_stats_update_end(&pcpu_stats->syncp);
759 } else {
760 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
761 dev_kfree_skb_any(skb);
762 }
763 return NETDEV_TX_OK;
764}
765
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100766static void mlxsw_sp_set_rx_mode(struct net_device *dev)
767{
768}
769
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200770static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
771{
772 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
773 struct sockaddr *addr = p;
774 int err;
775
776 if (!is_valid_ether_addr(addr->sa_data))
777 return -EADDRNOTAVAIL;
778
779 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
780 if (err)
781 return err;
782 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
783 return 0;
784}
785
Ido Schimmel18281f22017-03-24 08:02:51 +0100786static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
787 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200788{
Ido Schimmel18281f22017-03-24 08:02:51 +0100789 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100790}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200791
Ido Schimmelf417f042017-03-24 08:02:50 +0100792#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +0100793
794static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
795 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +0100796{
Ido Schimmel18281f22017-03-24 08:02:51 +0100797 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
798 BITS_PER_BYTE));
799 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
800 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100801}
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200802
Ido Schimmel18281f22017-03-24 08:02:51 +0100803/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +0100804 * Assumes 100m cable and maximum MTU.
805 */
Ido Schimmel18281f22017-03-24 08:02:51 +0100806#define MLXSW_SP_PAUSE_DELAY 58752
807
808static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
809 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +0100810{
811 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +0100812 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +0100813 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +0100814 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200815 else
Ido Schimmelf417f042017-03-24 08:02:50 +0100816 return 0;
817}
818
819static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
820 bool lossy)
821{
822 if (lossy)
823 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
824 else
825 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
826 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200827}
828
829int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200830 u8 *prio_tc, bool pause_en,
831 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +0200832{
833 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200834 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
835 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200836 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200837 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200838
839 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
840 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
841 if (err)
842 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200843
844 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
845 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200846 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +0100847 bool lossy;
848 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200849
850 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
851 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200852 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200853 configure = true;
854 break;
855 }
856 }
857
858 if (!configure)
859 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +0100860
861 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +0100862 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
863 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
864 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +0100865 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200866 }
867
Ido Schimmelff6551e2016-04-06 17:10:03 +0200868 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
869}
870
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200871static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200872 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200873{
874 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
875 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200876 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200877 u8 *prio_tc;
878
879 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200880 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200881
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200882 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200883 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200884}
885
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200886static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
887{
888 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200889 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200890 int err;
891
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200892 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200893 if (err)
894 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200895 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
896 if (err)
897 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200898 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
899 if (err)
900 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200901 dev->mtu = mtu;
902 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200903
904err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +0200905 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
906err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200907 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +0200908 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200909}
910
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +0300911static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200912mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
913 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200914{
915 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
916 struct mlxsw_sp_port_pcpu_stats *p;
917 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
918 u32 tx_dropped = 0;
919 unsigned int start;
920 int i;
921
922 for_each_possible_cpu(i) {
923 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
924 do {
925 start = u64_stats_fetch_begin_irq(&p->syncp);
926 rx_packets = p->rx_packets;
927 rx_bytes = p->rx_bytes;
928 tx_packets = p->tx_packets;
929 tx_bytes = p->tx_bytes;
930 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
931
932 stats->rx_packets += rx_packets;
933 stats->rx_bytes += rx_bytes;
934 stats->tx_packets += tx_packets;
935 stats->tx_bytes += tx_bytes;
936 /* tx_dropped is u32, updated without syncp protection. */
937 tx_dropped += p->tx_dropped;
938 }
939 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200940 return 0;
941}
942
Or Gerlitz3df5b3c2016-11-22 23:09:54 +0200943static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200944{
945 switch (attr_id) {
946 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
947 return true;
948 }
949
950 return false;
951}
952
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +0300953static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
954 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200955{
956 switch (attr_id) {
957 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
958 return mlxsw_sp_port_get_sw_stats64(dev, sp);
959 }
960
961 return -EINVAL;
962}
963
964static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
965 int prio, char *ppcnt_pl)
966{
967 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
968 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
969
970 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
971 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
972}
973
974static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
975 struct rtnl_link_stats64 *stats)
976{
977 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
978 int err;
979
980 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
981 0, ppcnt_pl);
982 if (err)
983 goto out;
984
985 stats->tx_packets =
986 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
987 stats->rx_packets =
988 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
989 stats->tx_bytes =
990 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
991 stats->rx_bytes =
992 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
993 stats->multicast =
994 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
995
996 stats->rx_crc_errors =
997 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
998 stats->rx_frame_errors =
999 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1000
1001 stats->rx_length_errors = (
1002 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1003 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1004 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1005
1006 stats->rx_errors = (stats->rx_crc_errors +
1007 stats->rx_frame_errors + stats->rx_length_errors);
1008
1009out:
1010 return err;
1011}
1012
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001013static void
1014mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1015 struct mlxsw_sp_port_xstats *xstats)
1016{
1017 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1018 int err, i;
1019
1020 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1021 ppcnt_pl);
1022 if (!err)
1023 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1024
1025 for (i = 0; i < TC_MAX_QUEUE; i++) {
1026 err = mlxsw_sp_port_get_stats_raw(dev,
1027 MLXSW_REG_PPCNT_TC_CONG_TC,
1028 i, ppcnt_pl);
1029 if (!err)
1030 xstats->wred_drop[i] =
1031 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1032
1033 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1034 i, ppcnt_pl);
1035 if (err)
1036 continue;
1037
1038 xstats->backlog[i] =
1039 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1040 xstats->tail_drop[i] =
1041 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1042 }
1043}
1044
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001045static void update_stats_cache(struct work_struct *work)
1046{
1047 struct mlxsw_sp_port *mlxsw_sp_port =
1048 container_of(work, struct mlxsw_sp_port,
Nogah Frankel9deef432017-10-26 10:55:32 +02001049 periodic_hw_stats.update_dw.work);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001050
1051 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1052 goto out;
1053
1054 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
Nogah Frankel9deef432017-10-26 10:55:32 +02001055 &mlxsw_sp_port->periodic_hw_stats.stats);
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001056 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1057 &mlxsw_sp_port->periodic_hw_stats.xstats);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001058
1059out:
Nogah Frankel9deef432017-10-26 10:55:32 +02001060 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001061 MLXSW_HW_STATS_UPDATE_TIME);
1062}
1063
1064/* Return the stats from a cache that is updated periodically,
1065 * as this function might get called in an atomic context.
1066 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001067static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001068mlxsw_sp_port_get_stats64(struct net_device *dev,
1069 struct rtnl_link_stats64 *stats)
1070{
1071 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1072
Nogah Frankel9deef432017-10-26 10:55:32 +02001073 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001074}
1075
Jiri Pirko93cd0812017-04-18 16:55:35 +02001076static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1077 u16 vid_begin, u16 vid_end,
1078 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001079{
1080 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1081 char *spvm_pl;
1082 int err;
1083
1084 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1085 if (!spvm_pl)
1086 return -ENOMEM;
1087
1088 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1089 vid_end, is_member, untagged);
1090 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1091 kfree(spvm_pl);
1092 return err;
1093}
1094
Jiri Pirko93cd0812017-04-18 16:55:35 +02001095int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1096 u16 vid_end, bool is_member, bool untagged)
1097{
1098 u16 vid, vid_e;
1099 int err;
1100
1101 for (vid = vid_begin; vid <= vid_end;
1102 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1103 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1104 vid_end);
1105
1106 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1107 is_member, untagged);
1108 if (err)
1109 return err;
1110 }
1111
1112 return 0;
1113}
1114
Ido Schimmelc57529e2017-05-26 08:37:31 +02001115static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001116{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001117 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001118
Ido Schimmelc57529e2017-05-26 08:37:31 +02001119 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1120 &mlxsw_sp_port->vlans_list, list)
1121 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001122}
1123
Ido Schimmel31a08a52017-05-26 08:37:26 +02001124static struct mlxsw_sp_port_vlan *
1125mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1126{
1127 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001128 bool untagged = vid == 1;
1129 int err;
1130
1131 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1132 if (err)
1133 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001134
1135 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001136 if (!mlxsw_sp_port_vlan) {
1137 err = -ENOMEM;
1138 goto err_port_vlan_alloc;
1139 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02001140
1141 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1142 mlxsw_sp_port_vlan->vid = vid;
1143 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1144
1145 return mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001146
1147err_port_vlan_alloc:
1148 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1149 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001150}
1151
1152static void
1153mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1154{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001155 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1156 u16 vid = mlxsw_sp_port_vlan->vid;
Ido Schimmel7cbecf22017-05-26 08:37:28 +02001157
Ido Schimmel31a08a52017-05-26 08:37:26 +02001158 list_del(&mlxsw_sp_port_vlan->list);
1159 kfree(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001160 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1161}
1162
1163struct mlxsw_sp_port_vlan *
1164mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1165{
1166 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1167
1168 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1169 if (mlxsw_sp_port_vlan)
1170 return mlxsw_sp_port_vlan;
1171
1172 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1173}
1174
1175void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1176{
Ido Schimmela1107482017-05-26 08:37:39 +02001177 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1178
Ido Schimmelc57529e2017-05-26 08:37:31 +02001179 if (mlxsw_sp_port_vlan->bridge_port)
1180 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
Ido Schimmela1107482017-05-26 08:37:39 +02001181 else if (fid)
1182 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001183
1184 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001185}
1186
Ido Schimmel05978482016-08-17 16:39:30 +02001187static int mlxsw_sp_port_add_vid(struct net_device *dev,
1188 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001189{
1190 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001191
1192 /* VLAN 0 is added to HW filter when device goes up, but it is
1193 * reserved in our case, so simply return.
1194 */
1195 if (!vid)
1196 return 0;
1197
Ido Schimmelc57529e2017-05-26 08:37:31 +02001198 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001199}
1200
Ido Schimmel32d863f2016-07-02 11:00:10 +02001201static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1202 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001203{
1204 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001205 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001206
1207 /* VLAN 0 is removed from HW filter when device goes down, but
1208 * it is reserved in our case, so simply return.
1209 */
1210 if (!vid)
1211 return 0;
1212
Ido Schimmel31a08a52017-05-26 08:37:26 +02001213 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001214 if (!mlxsw_sp_port_vlan)
Ido Schimmel31a08a52017-05-26 08:37:26 +02001215 return 0;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001216 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001217
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001218 return 0;
1219}
1220
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001221static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1222 size_t len)
1223{
1224 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +02001225 u8 module = mlxsw_sp_port->mapping.module;
1226 u8 width = mlxsw_sp_port->mapping.width;
1227 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001228 int err;
1229
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001230 if (!mlxsw_sp_port->split)
1231 err = snprintf(name, len, "p%d", module + 1);
1232 else
1233 err = snprintf(name, len, "p%ds%d", module + 1,
1234 lane / width);
1235
1236 if (err >= len)
1237 return -EINVAL;
1238
1239 return 0;
1240}
1241
Yotam Gigi763b4b72016-07-21 12:03:17 +02001242static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001243mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1244 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001245 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1246
1247 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1248 if (mall_tc_entry->cookie == cookie)
1249 return mall_tc_entry;
1250
1251 return NULL;
1252}
1253
1254static int
1255mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001256 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001257 const struct tc_action *a,
1258 bool ingress)
1259{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001260 enum mlxsw_sp_span_type span_type;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001261 struct net_device *to_dev;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001262
Cong Wang9f8a7392017-12-05 16:17:26 -08001263 to_dev = tcf_mirred_dev(a);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001264 if (!to_dev) {
1265 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1266 return -EINVAL;
1267 }
1268
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001269 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001270 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Petr Machata079c9f32018-02-27 14:53:44 +01001271 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type,
Petr Machata98977082018-02-27 14:53:41 +01001272 true, &mirror->span_id);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001273}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001274
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001275static void
1276mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1277 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1278{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001279 enum mlxsw_sp_span_type span_type;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001280
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001281 span_type = mirror->ingress ?
1282 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Petr Machata98977082018-02-27 14:53:41 +01001283 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +01001284 span_type, true);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001285}
1286
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001287static int
1288mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1289 struct tc_cls_matchall_offload *cls,
1290 const struct tc_action *a,
1291 bool ingress)
1292{
1293 int err;
1294
1295 if (!mlxsw_sp_port->sample)
1296 return -EOPNOTSUPP;
1297 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1298 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1299 return -EEXIST;
1300 }
1301 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1302 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1303 return -EOPNOTSUPP;
1304 }
1305
1306 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1307 tcf_sample_psample_group(a));
1308 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1309 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1310 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1311
1312 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1313 if (err)
1314 goto err_port_sample_set;
1315 return 0;
1316
1317err_port_sample_set:
1318 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1319 return err;
1320}
1321
1322static void
1323mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1324{
1325 if (!mlxsw_sp_port->sample)
1326 return;
1327
1328 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1329 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1330}
1331
Yotam Gigi763b4b72016-07-21 12:03:17 +02001332static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001333 struct tc_cls_matchall_offload *f,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001334 bool ingress)
1335{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001336 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001337 __be16 protocol = f->common.protocol;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001338 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001339 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001340 int err;
1341
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001342 if (!tcf_exts_has_one_action(f->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001343 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001344 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001345 }
1346
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001347 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1348 if (!mall_tc_entry)
1349 return -ENOMEM;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001350 mall_tc_entry->cookie = f->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001351
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001352 tcf_exts_to_list(f->exts, &actions);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001353 a = list_first_entry(&actions, struct tc_action, list);
1354
1355 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1356 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1357
1358 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1359 mirror = &mall_tc_entry->mirror;
1360 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1361 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001362 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1363 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001364 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001365 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001366 } else {
1367 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001368 }
1369
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001370 if (err)
1371 goto err_add_action;
1372
1373 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001374 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001375
1376err_add_action:
1377 kfree(mall_tc_entry);
1378 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001379}
1380
1381static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001382 struct tc_cls_matchall_offload *f)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001383{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001384 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001385
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001386 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001387 f->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001388 if (!mall_tc_entry) {
1389 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1390 return;
1391 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001392 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001393
1394 switch (mall_tc_entry->type) {
1395 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001396 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1397 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001398 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001399 case MLXSW_SP_PORT_MALL_SAMPLE:
1400 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1401 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001402 default:
1403 WARN_ON(1);
1404 }
1405
Yotam Gigi763b4b72016-07-21 12:03:17 +02001406 kfree(mall_tc_entry);
1407}
1408
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001409static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001410 struct tc_cls_matchall_offload *f,
1411 bool ingress)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001412{
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001413 switch (f->command) {
1414 case TC_CLSMATCHALL_REPLACE:
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001415 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001416 ingress);
1417 case TC_CLSMATCHALL_DESTROY:
1418 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1419 return 0;
1420 default:
1421 return -EOPNOTSUPP;
1422 }
1423}
1424
1425static int
Jiri Pirko3aaff322018-01-17 11:46:56 +01001426mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1427 struct tc_cls_flower_offload *f)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001428{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001429 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1430
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001431 switch (f->command) {
1432 case TC_CLSFLOWER_REPLACE:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001433 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001434 case TC_CLSFLOWER_DESTROY:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001435 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001436 return 0;
1437 case TC_CLSFLOWER_STATS:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001438 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001439 default:
1440 return -EOPNOTSUPP;
1441 }
1442}
1443
Jiri Pirko3aaff322018-01-17 11:46:56 +01001444static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1445 void *type_data,
1446 void *cb_priv, bool ingress)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001447{
1448 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1449
1450 switch (type) {
1451 case TC_SETUP_CLSMATCHALL:
Jakub Kicinski15f4edb2018-01-25 14:00:51 -08001452 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1453 type_data))
Jiri Pirko3aaff322018-01-17 11:46:56 +01001454 return -EOPNOTSUPP;
1455
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001456 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1457 ingress);
1458 case TC_SETUP_CLSFLOWER:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001459 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001460 default:
1461 return -EOPNOTSUPP;
1462 }
1463}
1464
Jiri Pirko3aaff322018-01-17 11:46:56 +01001465static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1466 void *type_data,
1467 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001468{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001469 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1470 cb_priv, true);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001471}
1472
Jiri Pirko3aaff322018-01-17 11:46:56 +01001473static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1474 void *type_data,
1475 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001476{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001477 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1478 cb_priv, false);
1479}
1480
1481static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1482 void *type_data, void *cb_priv)
1483{
1484 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1485
1486 switch (type) {
1487 case TC_SETUP_CLSMATCHALL:
1488 return 0;
1489 case TC_SETUP_CLSFLOWER:
1490 if (mlxsw_sp_acl_block_disabled(acl_block))
1491 return -EOPNOTSUPP;
1492
1493 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1494 default:
1495 return -EOPNOTSUPP;
1496 }
1497}
1498
1499static int
1500mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1501 struct tcf_block *block, bool ingress)
1502{
1503 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1504 struct mlxsw_sp_acl_block *acl_block;
1505 struct tcf_block_cb *block_cb;
1506 int err;
1507
1508 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1509 mlxsw_sp);
1510 if (!block_cb) {
1511 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1512 if (!acl_block)
1513 return -ENOMEM;
1514 block_cb = __tcf_block_cb_register(block,
1515 mlxsw_sp_setup_tc_block_cb_flower,
1516 mlxsw_sp, acl_block);
1517 if (IS_ERR(block_cb)) {
1518 err = PTR_ERR(block_cb);
1519 goto err_cb_register;
1520 }
1521 } else {
1522 acl_block = tcf_block_cb_priv(block_cb);
1523 }
1524 tcf_block_cb_incref(block_cb);
1525 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1526 mlxsw_sp_port, ingress);
1527 if (err)
1528 goto err_block_bind;
1529
1530 if (ingress)
1531 mlxsw_sp_port->ing_acl_block = acl_block;
1532 else
1533 mlxsw_sp_port->eg_acl_block = acl_block;
1534
1535 return 0;
1536
1537err_block_bind:
1538 if (!tcf_block_cb_decref(block_cb)) {
1539 __tcf_block_cb_unregister(block_cb);
1540err_cb_register:
1541 mlxsw_sp_acl_block_destroy(acl_block);
1542 }
1543 return err;
1544}
1545
1546static void
1547mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1548 struct tcf_block *block, bool ingress)
1549{
1550 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1551 struct mlxsw_sp_acl_block *acl_block;
1552 struct tcf_block_cb *block_cb;
1553 int err;
1554
1555 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1556 mlxsw_sp);
1557 if (!block_cb)
1558 return;
1559
1560 if (ingress)
1561 mlxsw_sp_port->ing_acl_block = NULL;
1562 else
1563 mlxsw_sp_port->eg_acl_block = NULL;
1564
1565 acl_block = tcf_block_cb_priv(block_cb);
1566 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1567 mlxsw_sp_port, ingress);
1568 if (!err && !tcf_block_cb_decref(block_cb)) {
1569 __tcf_block_cb_unregister(block_cb);
1570 mlxsw_sp_acl_block_destroy(acl_block);
1571 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001572}
1573
1574static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1575 struct tc_block_offload *f)
1576{
1577 tc_setup_cb_t *cb;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001578 bool ingress;
1579 int err;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001580
Jiri Pirko3aaff322018-01-17 11:46:56 +01001581 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1582 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1583 ingress = true;
1584 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1585 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1586 ingress = false;
1587 } else {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001588 return -EOPNOTSUPP;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001589 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001590
1591 switch (f->command) {
1592 case TC_BLOCK_BIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001593 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1594 mlxsw_sp_port);
1595 if (err)
1596 return err;
1597 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
1598 f->block, ingress);
1599 if (err) {
1600 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1601 return err;
1602 }
1603 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001604 case TC_BLOCK_UNBIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001605 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1606 f->block, ingress);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001607 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1608 return 0;
1609 default:
1610 return -EOPNOTSUPP;
1611 }
1612}
1613
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001614static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
Jiri Pirkode4784c2017-08-07 10:15:32 +02001615 void *type_data)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001616{
1617 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1618
Jiri Pirko2572ac52017-08-07 10:15:17 +02001619 switch (type) {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001620 case TC_SETUP_BLOCK:
1621 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
Nogah Frankel96f17e02017-11-06 07:23:45 +01001622 case TC_SETUP_QDISC_RED:
1623 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
Nogah Frankel46a36152018-01-14 12:33:16 +01001624 case TC_SETUP_QDISC_PRIO:
1625 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
Jiri Pirko2572ac52017-08-07 10:15:17 +02001626 default:
1627 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001628 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001629}
1630
Jiri Pirko9454d932017-12-06 09:41:12 +01001631
1632static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1633{
1634 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1635
Jiri Pirko3aaff322018-01-17 11:46:56 +01001636 if (!enable) {
1637 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1638 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1639 !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1640 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1641 return -EINVAL;
1642 }
1643 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1644 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1645 } else {
1646 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1647 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
Jiri Pirko9454d932017-12-06 09:41:12 +01001648 }
1649 return 0;
1650}
1651
1652typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1653
1654static int mlxsw_sp_handle_feature(struct net_device *dev,
1655 netdev_features_t wanted_features,
1656 netdev_features_t feature,
1657 mlxsw_sp_feature_handler feature_handler)
1658{
1659 netdev_features_t changes = wanted_features ^ dev->features;
1660 bool enable = !!(wanted_features & feature);
1661 int err;
1662
1663 if (!(changes & feature))
1664 return 0;
1665
1666 err = feature_handler(dev, enable);
1667 if (err) {
1668 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1669 enable ? "Enable" : "Disable", &feature, err);
1670 return err;
1671 }
1672
1673 if (enable)
1674 dev->features |= feature;
1675 else
1676 dev->features &= ~feature;
1677
1678 return 0;
1679}
1680static int mlxsw_sp_set_features(struct net_device *dev,
1681 netdev_features_t features)
1682{
1683 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1684 mlxsw_sp_feature_hw_tc);
1685}
1686
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001687static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1688 .ndo_open = mlxsw_sp_port_open,
1689 .ndo_stop = mlxsw_sp_port_stop,
1690 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001691 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001692 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001693 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1694 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1695 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001696 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1697 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001698 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1699 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001700 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko9454d932017-12-06 09:41:12 +01001701 .ndo_set_features = mlxsw_sp_set_features,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001702};
1703
1704static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1705 struct ethtool_drvinfo *drvinfo)
1706{
1707 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1708 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1709
1710 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1711 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1712 sizeof(drvinfo->version));
1713 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1714 "%d.%d.%d",
1715 mlxsw_sp->bus_info->fw_rev.major,
1716 mlxsw_sp->bus_info->fw_rev.minor,
1717 mlxsw_sp->bus_info->fw_rev.subminor);
1718 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1719 sizeof(drvinfo->bus_info));
1720}
1721
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001722static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1723 struct ethtool_pauseparam *pause)
1724{
1725 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1726
1727 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1728 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1729}
1730
1731static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1732 struct ethtool_pauseparam *pause)
1733{
1734 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1735
1736 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1737 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1738 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1739
1740 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1741 pfcc_pl);
1742}
1743
1744static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1745 struct ethtool_pauseparam *pause)
1746{
1747 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1748 bool pause_en = pause->tx_pause || pause->rx_pause;
1749 int err;
1750
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001751 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1752 netdev_err(dev, "PFC already enabled on port\n");
1753 return -EINVAL;
1754 }
1755
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001756 if (pause->autoneg) {
1757 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1758 return -EINVAL;
1759 }
1760
1761 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1762 if (err) {
1763 netdev_err(dev, "Failed to configure port's headroom\n");
1764 return err;
1765 }
1766
1767 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1768 if (err) {
1769 netdev_err(dev, "Failed to set PAUSE parameters\n");
1770 goto err_port_pause_configure;
1771 }
1772
1773 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1774 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1775
1776 return 0;
1777
1778err_port_pause_configure:
1779 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1780 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1781 return err;
1782}
1783
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001784struct mlxsw_sp_port_hw_stats {
1785 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02001786 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01001787 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001788};
1789
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001790static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001791 {
1792 .str = "a_frames_transmitted_ok",
1793 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1794 },
1795 {
1796 .str = "a_frames_received_ok",
1797 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1798 },
1799 {
1800 .str = "a_frame_check_sequence_errors",
1801 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1802 },
1803 {
1804 .str = "a_alignment_errors",
1805 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1806 },
1807 {
1808 .str = "a_octets_transmitted_ok",
1809 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1810 },
1811 {
1812 .str = "a_octets_received_ok",
1813 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1814 },
1815 {
1816 .str = "a_multicast_frames_xmitted_ok",
1817 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1818 },
1819 {
1820 .str = "a_broadcast_frames_xmitted_ok",
1821 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1822 },
1823 {
1824 .str = "a_multicast_frames_received_ok",
1825 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1826 },
1827 {
1828 .str = "a_broadcast_frames_received_ok",
1829 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1830 },
1831 {
1832 .str = "a_in_range_length_errors",
1833 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1834 },
1835 {
1836 .str = "a_out_of_range_length_field",
1837 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1838 },
1839 {
1840 .str = "a_frame_too_long_errors",
1841 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1842 },
1843 {
1844 .str = "a_symbol_error_during_carrier",
1845 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1846 },
1847 {
1848 .str = "a_mac_control_frames_transmitted",
1849 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1850 },
1851 {
1852 .str = "a_mac_control_frames_received",
1853 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1854 },
1855 {
1856 .str = "a_unsupported_opcodes_received",
1857 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1858 },
1859 {
1860 .str = "a_pause_mac_ctrl_frames_received",
1861 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1862 },
1863 {
1864 .str = "a_pause_mac_ctrl_frames_xmitted",
1865 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1866 },
1867};
1868
1869#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1870
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001871static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1872 {
1873 .str = "rx_octets_prio",
1874 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1875 },
1876 {
1877 .str = "rx_frames_prio",
1878 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1879 },
1880 {
1881 .str = "tx_octets_prio",
1882 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1883 },
1884 {
1885 .str = "tx_frames_prio",
1886 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1887 },
1888 {
1889 .str = "rx_pause_prio",
1890 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1891 },
1892 {
1893 .str = "rx_pause_duration_prio",
1894 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1895 },
1896 {
1897 .str = "tx_pause_prio",
1898 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1899 },
1900 {
1901 .str = "tx_pause_duration_prio",
1902 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1903 },
1904};
1905
1906#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1907
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001908static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1909 {
1910 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01001911 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1912 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001913 },
1914 {
1915 .str = "tc_no_buffer_discard_uc_tc",
1916 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1917 },
1918};
1919
1920#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1921
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001922#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001923 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1924 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001925 IEEE_8021QAZ_MAX_TCS)
1926
1927static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1928{
1929 int i;
1930
1931 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1932 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1933 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1934 *p += ETH_GSTRING_LEN;
1935 }
1936}
1937
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001938static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1939{
1940 int i;
1941
1942 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1943 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1944 mlxsw_sp_port_hw_tc_stats[i].str, tc);
1945 *p += ETH_GSTRING_LEN;
1946 }
1947}
1948
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001949static void mlxsw_sp_port_get_strings(struct net_device *dev,
1950 u32 stringset, u8 *data)
1951{
1952 u8 *p = data;
1953 int i;
1954
1955 switch (stringset) {
1956 case ETH_SS_STATS:
1957 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1958 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1959 ETH_GSTRING_LEN);
1960 p += ETH_GSTRING_LEN;
1961 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001962
1963 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1964 mlxsw_sp_port_get_prio_strings(&p, i);
1965
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001966 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1967 mlxsw_sp_port_get_tc_strings(&p, i);
1968
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001969 break;
1970 }
1971}
1972
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001973static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1974 enum ethtool_phys_id_state state)
1975{
1976 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1977 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1978 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1979 bool active;
1980
1981 switch (state) {
1982 case ETHTOOL_ID_ACTIVE:
1983 active = true;
1984 break;
1985 case ETHTOOL_ID_INACTIVE:
1986 active = false;
1987 break;
1988 default:
1989 return -EOPNOTSUPP;
1990 }
1991
1992 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1993 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1994}
1995
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001996static int
1997mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
1998 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
1999{
2000 switch (grp) {
2001 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2002 *p_hw_stats = mlxsw_sp_port_hw_stats;
2003 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2004 break;
2005 case MLXSW_REG_PPCNT_PRIO_CNT:
2006 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2007 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2008 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002009 case MLXSW_REG_PPCNT_TC_CNT:
2010 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2011 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2012 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002013 default:
2014 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002015 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002016 }
2017 return 0;
2018}
2019
2020static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2021 enum mlxsw_reg_ppcnt_grp grp, int prio,
2022 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002023{
Ido Schimmel18281f22017-03-24 08:02:51 +01002024 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2025 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002026 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002027 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002028 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002029 int err;
2030
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002031 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2032 if (err)
2033 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002034 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002035 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002036 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002037 if (!hw_stats[i].cells_bytes)
2038 continue;
2039 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2040 data[data_index + i]);
2041 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002042}
2043
2044static void mlxsw_sp_port_get_stats(struct net_device *dev,
2045 struct ethtool_stats *stats, u64 *data)
2046{
2047 int i, data_index = 0;
2048
2049 /* IEEE 802.3 Counters */
2050 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2051 data, data_index);
2052 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2053
2054 /* Per-Priority Counters */
2055 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2056 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2057 data, data_index);
2058 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2059 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002060
2061 /* Per-TC Counters */
2062 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2063 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2064 data, data_index);
2065 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2066 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002067}
2068
2069static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2070{
2071 switch (sset) {
2072 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002073 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002074 default:
2075 return -EOPNOTSUPP;
2076 }
2077}
2078
2079struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002080 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002081 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002082 u32 speed;
2083};
2084
2085static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2086 {
2087 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002088 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2089 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002090 },
2091 {
2092 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2093 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002094 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2095 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002096 },
2097 {
2098 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002099 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2100 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002101 },
2102 {
2103 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2104 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002105 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2106 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002107 },
2108 {
2109 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2110 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2111 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2112 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002113 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2114 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002115 },
2116 {
2117 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002118 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2119 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002120 },
2121 {
2122 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002123 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2124 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002125 },
2126 {
2127 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002128 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2129 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002130 },
2131 {
2132 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002133 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2134 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002135 },
2136 {
2137 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002138 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2139 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002140 },
2141 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002142 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2143 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2144 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002145 },
2146 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002147 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2148 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2149 .speed = SPEED_25000,
2150 },
2151 {
2152 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2153 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2154 .speed = SPEED_25000,
2155 },
2156 {
2157 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2158 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2159 .speed = SPEED_25000,
2160 },
2161 {
2162 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2163 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2164 .speed = SPEED_50000,
2165 },
2166 {
2167 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2168 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2169 .speed = SPEED_50000,
2170 },
2171 {
2172 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2173 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2174 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002175 },
2176 {
2177 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002178 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2179 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002180 },
2181 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002182 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2183 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2184 .speed = SPEED_56000,
2185 },
2186 {
2187 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2188 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2189 .speed = SPEED_56000,
2190 },
2191 {
2192 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2193 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2194 .speed = SPEED_56000,
2195 },
2196 {
2197 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2198 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2199 .speed = SPEED_100000,
2200 },
2201 {
2202 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2203 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2204 .speed = SPEED_100000,
2205 },
2206 {
2207 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2208 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2209 .speed = SPEED_100000,
2210 },
2211 {
2212 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2213 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2214 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002215 },
2216};
2217
2218#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2219
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002220static void
2221mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2222 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002223{
2224 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2225 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2226 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2227 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2228 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2229 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002230 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002231
2232 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2233 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2234 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2235 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2236 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002237 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002238}
2239
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002240static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002241{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002242 int i;
2243
2244 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2245 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002246 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2247 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002248 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002249}
2250
2251static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002252 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002253{
2254 u32 speed = SPEED_UNKNOWN;
2255 u8 duplex = DUPLEX_UNKNOWN;
2256 int i;
2257
2258 if (!carrier_ok)
2259 goto out;
2260
2261 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2262 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2263 speed = mlxsw_sp_port_link_mode[i].speed;
2264 duplex = DUPLEX_FULL;
2265 break;
2266 }
2267 }
2268out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002269 cmd->base.speed = speed;
2270 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002271}
2272
2273static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2274{
2275 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2276 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2277 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2278 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2279 return PORT_FIBRE;
2280
2281 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2282 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2283 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2284 return PORT_DA;
2285
2286 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2287 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2288 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2289 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2290 return PORT_NONE;
2291
2292 return PORT_OTHER;
2293}
2294
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002295static u32
2296mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002297{
2298 u32 ptys_proto = 0;
2299 int i;
2300
2301 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002302 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2303 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002304 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2305 }
2306 return ptys_proto;
2307}
2308
2309static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2310{
2311 u32 ptys_proto = 0;
2312 int i;
2313
2314 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2315 if (speed == mlxsw_sp_port_link_mode[i].speed)
2316 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2317 }
2318 return ptys_proto;
2319}
2320
Ido Schimmel18f1e702016-02-26 17:32:31 +01002321static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2322{
2323 u32 ptys_proto = 0;
2324 int i;
2325
2326 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2327 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2328 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2329 }
2330 return ptys_proto;
2331}
2332
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002333static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2334 struct ethtool_link_ksettings *cmd)
2335{
2336 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2337 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2338 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2339
2340 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2341 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2342}
2343
2344static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2345 struct ethtool_link_ksettings *cmd)
2346{
2347 if (!autoneg)
2348 return;
2349
2350 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2351 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2352}
2353
2354static void
2355mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2356 struct ethtool_link_ksettings *cmd)
2357{
2358 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2359 return;
2360
2361 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2362 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2363}
2364
2365static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2366 struct ethtool_link_ksettings *cmd)
2367{
2368 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2369 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2370 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2371 char ptys_pl[MLXSW_REG_PTYS_LEN];
2372 u8 autoneg_status;
2373 bool autoneg;
2374 int err;
2375
2376 autoneg = mlxsw_sp_port->link.autoneg;
Elad Raz401c8b42016-10-28 21:35:52 +02002377 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002378 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2379 if (err)
2380 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002381 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2382 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002383
2384 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2385
2386 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2387
2388 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2389 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2390 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2391
2392 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2393 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2394 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2395 cmd);
2396
2397 return 0;
2398}
2399
2400static int
2401mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2402 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002403{
2404 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2405 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2406 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002407 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002408 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002409 int err;
2410
Elad Raz401c8b42016-10-28 21:35:52 +02002411 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002412 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002413 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002414 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002415 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002416
2417 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2418 eth_proto_new = autoneg ?
2419 mlxsw_sp_to_ptys_advert_link(cmd) :
2420 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002421
2422 eth_proto_new = eth_proto_new & eth_proto_cap;
2423 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002424 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002425 return -EINVAL;
2426 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002427
Elad Raz401c8b42016-10-28 21:35:52 +02002428 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2429 eth_proto_new);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002430 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002431 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002432 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002433
Ido Schimmel6277d462016-07-15 11:14:58 +02002434 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002435 return 0;
2436
Ido Schimmel0c83f882016-09-12 13:26:23 +02002437 mlxsw_sp_port->link.autoneg = autoneg;
2438
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002439 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2440 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002441
2442 return 0;
2443}
2444
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002445static int mlxsw_sp_flash_device(struct net_device *dev,
2446 struct ethtool_flash *flash)
2447{
2448 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2449 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2450 const struct firmware *firmware;
2451 int err;
2452
2453 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2454 return -EOPNOTSUPP;
2455
2456 dev_hold(dev);
2457 rtnl_unlock();
2458
2459 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2460 if (err)
2461 goto out;
2462 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2463 release_firmware(firmware);
2464out:
2465 rtnl_lock();
2466 dev_put(dev);
2467 return err;
2468}
2469
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002470#define MLXSW_SP_I2C_ADDR_LOW 0x50
2471#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2472#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002473
2474static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2475 u16 offset, u16 size, void *data,
2476 unsigned int *p_read_size)
2477{
2478 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2479 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2480 char mcia_pl[MLXSW_REG_MCIA_LEN];
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002481 u16 i2c_addr;
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002482 int status;
2483 int err;
2484
2485 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002486
2487 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2488 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2489 /* Cross pages read, read until offset 256 in low page */
2490 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2491
2492 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2493 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2494 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2495 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2496 }
2497
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002498 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002499 0, 0, offset, size, i2c_addr);
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002500
2501 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2502 if (err)
2503 return err;
2504
2505 status = mlxsw_reg_mcia_status_get(mcia_pl);
2506 if (status)
2507 return -EIO;
2508
2509 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2510 memcpy(data, eeprom_tmp, size);
2511 *p_read_size = size;
2512
2513 return 0;
2514}
2515
2516enum mlxsw_sp_eeprom_module_info_rev_id {
2517 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2518 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2519 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2520};
2521
2522enum mlxsw_sp_eeprom_module_info_id {
2523 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2524 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2525 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2526 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2527};
2528
2529enum mlxsw_sp_eeprom_module_info {
2530 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2531 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2532 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2533};
2534
2535static int mlxsw_sp_get_module_info(struct net_device *netdev,
2536 struct ethtool_modinfo *modinfo)
2537{
2538 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2539 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2540 u8 module_rev_id, module_id;
2541 unsigned int read_size;
2542 int err;
2543
2544 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2545 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2546 module_info, &read_size);
2547 if (err)
2548 return err;
2549
2550 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2551 return -EIO;
2552
2553 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2554 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2555
2556 switch (module_id) {
2557 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2558 modinfo->type = ETH_MODULE_SFF_8436;
2559 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2560 break;
2561 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2562 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2563 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2564 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2565 modinfo->type = ETH_MODULE_SFF_8636;
2566 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2567 } else {
2568 modinfo->type = ETH_MODULE_SFF_8436;
2569 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2570 }
2571 break;
2572 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2573 modinfo->type = ETH_MODULE_SFF_8472;
2574 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2575 break;
2576 default:
2577 return -EINVAL;
2578 }
2579
2580 return 0;
2581}
2582
2583static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2584 struct ethtool_eeprom *ee,
2585 u8 *data)
2586{
2587 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2588 int offset = ee->offset;
2589 unsigned int read_size;
2590 int i = 0;
2591 int err;
2592
2593 if (!ee->len)
2594 return -EINVAL;
2595
2596 memset(data, 0, ee->len);
2597
2598 while (i < ee->len) {
2599 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2600 ee->len - i, data + i,
2601 &read_size);
2602 if (err) {
2603 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2604 return err;
2605 }
2606
2607 i += read_size;
2608 offset += read_size;
2609 }
2610
2611 return 0;
2612}
2613
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002614static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2615 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2616 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002617 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2618 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002619 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002620 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002621 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2622 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002623 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2624 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002625 .flash_device = mlxsw_sp_flash_device,
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002626 .get_module_info = mlxsw_sp_get_module_info,
2627 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002628};
2629
Ido Schimmel18f1e702016-02-26 17:32:31 +01002630static int
2631mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2632{
2633 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2634 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2635 char ptys_pl[MLXSW_REG_PTYS_LEN];
2636 u32 eth_proto_admin;
2637
2638 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002639 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2640 eth_proto_admin);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002641 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2642}
2643
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002644int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2645 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2646 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002647{
2648 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2649 char qeec_pl[MLXSW_REG_QEEC_LEN];
2650
2651 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2652 next_index);
2653 mlxsw_reg_qeec_de_set(qeec_pl, true);
2654 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2655 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2656 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2657}
2658
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002659int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2660 enum mlxsw_reg_qeec_hr hr, u8 index,
2661 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002662{
2663 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2664 char qeec_pl[MLXSW_REG_QEEC_LEN];
2665
2666 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2667 next_index);
2668 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2669 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2670 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2671}
2672
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002673int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2674 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002675{
2676 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2677 char qtct_pl[MLXSW_REG_QTCT_LEN];
2678
2679 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2680 tclass);
2681 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2682}
2683
2684static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2685{
2686 int err, i;
2687
2688 /* Setup the elements hierarcy, so that each TC is linked to
2689 * one subgroup, which are all member in the same group.
2690 */
2691 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2692 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2693 0);
2694 if (err)
2695 return err;
2696 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2697 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2698 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2699 0, false, 0);
2700 if (err)
2701 return err;
2702 }
2703 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2704 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2705 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2706 false, 0);
2707 if (err)
2708 return err;
2709 }
2710
2711 /* Make sure the max shaper is disabled in all hierarcies that
2712 * support it.
2713 */
2714 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2715 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2716 MLXSW_REG_QEEC_MAS_DIS);
2717 if (err)
2718 return err;
2719 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2720 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2721 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2722 i, 0,
2723 MLXSW_REG_QEEC_MAS_DIS);
2724 if (err)
2725 return err;
2726 }
2727 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2728 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2729 MLXSW_REG_QEEC_HIERARCY_TC,
2730 i, i,
2731 MLXSW_REG_QEEC_MAS_DIS);
2732 if (err)
2733 return err;
2734 }
2735
2736 /* Map all priorities to traffic class 0. */
2737 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2738 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2739 if (err)
2740 return err;
2741 }
2742
2743 return 0;
2744}
2745
Ido Schimmel5b153852017-06-08 08:47:44 +02002746static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2747 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002748{
Ido Schimmelc57529e2017-05-26 08:37:31 +02002749 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002750 struct mlxsw_sp_port *mlxsw_sp_port;
2751 struct net_device *dev;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002752 int err;
2753
Ido Schimmel5b153852017-06-08 08:47:44 +02002754 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2755 if (err) {
2756 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2757 local_port);
2758 return err;
2759 }
2760
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002761 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
Ido Schimmel5b153852017-06-08 08:47:44 +02002762 if (!dev) {
2763 err = -ENOMEM;
2764 goto err_alloc_etherdev;
2765 }
Jiri Pirkof20a91f2016-10-27 15:13:00 +02002766 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002767 mlxsw_sp_port = netdev_priv(dev);
2768 mlxsw_sp_port->dev = dev;
2769 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2770 mlxsw_sp_port->local_port = local_port;
Ido Schimmelc57529e2017-05-26 08:37:31 +02002771 mlxsw_sp_port->pvid = 1;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002772 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02002773 mlxsw_sp_port->mapping.module = module;
2774 mlxsw_sp_port->mapping.width = width;
2775 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002776 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02002777 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02002778 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002779
2780 mlxsw_sp_port->pcpu_stats =
2781 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2782 if (!mlxsw_sp_port->pcpu_stats) {
2783 err = -ENOMEM;
2784 goto err_alloc_stats;
2785 }
2786
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002787 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2788 GFP_KERNEL);
2789 if (!mlxsw_sp_port->sample) {
2790 err = -ENOMEM;
2791 goto err_alloc_sample;
2792 }
2793
Nogah Frankel9deef432017-10-26 10:55:32 +02002794 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002795 &update_stats_cache);
2796
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002797 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2798 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2799
Ido Schimmel2e915e02017-06-08 08:47:45 +02002800 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
Ido Schimmel5b153852017-06-08 08:47:44 +02002801 if (err) {
2802 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2803 mlxsw_sp_port->local_port);
2804 goto err_port_module_map;
2805 }
2806
Ido Schimmel3247ff22016-09-08 08:16:02 +02002807 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2808 if (err) {
2809 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2810 mlxsw_sp_port->local_port);
2811 goto err_port_swid_set;
2812 }
2813
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002814 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2815 if (err) {
2816 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2817 mlxsw_sp_port->local_port);
2818 goto err_dev_addr_init;
2819 }
2820
2821 netif_carrier_off(dev);
2822
2823 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02002824 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2825 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002826
Jarod Wilsond894be52016-10-20 13:55:16 -04002827 dev->min_mtu = 0;
2828 dev->max_mtu = ETH_MAX_MTU;
2829
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002830 /* Each packet needs to have a Tx header (metadata) on top all other
2831 * headers.
2832 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02002833 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002834
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002835 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2836 if (err) {
2837 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2838 mlxsw_sp_port->local_port);
2839 goto err_port_system_port_mapping_set;
2840 }
2841
Ido Schimmel18f1e702016-02-26 17:32:31 +01002842 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2843 if (err) {
2844 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2845 mlxsw_sp_port->local_port);
2846 goto err_port_speed_by_width_set;
2847 }
2848
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002849 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2850 if (err) {
2851 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2852 mlxsw_sp_port->local_port);
2853 goto err_port_mtu_set;
2854 }
2855
2856 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2857 if (err)
2858 goto err_port_admin_status_set;
2859
2860 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2861 if (err) {
2862 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2863 mlxsw_sp_port->local_port);
2864 goto err_port_buffers_init;
2865 }
2866
Ido Schimmel90183b92016-04-06 17:10:08 +02002867 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2868 if (err) {
2869 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2870 mlxsw_sp_port->local_port);
2871 goto err_port_ets_init;
2872 }
2873
Ido Schimmelf00817d2016-04-06 17:10:09 +02002874 /* ETS and buffers must be initialized before DCB. */
2875 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2876 if (err) {
2877 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2878 mlxsw_sp_port->local_port);
2879 goto err_port_dcb_init;
2880 }
2881
Ido Schimmela1107482017-05-26 08:37:39 +02002882 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
Ido Schimmel45a4a162017-05-16 19:38:35 +02002883 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02002884 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
Ido Schimmel45a4a162017-05-16 19:38:35 +02002885 mlxsw_sp_port->local_port);
Ido Schimmela1107482017-05-26 08:37:39 +02002886 goto err_port_fids_init;
Ido Schimmel45a4a162017-05-16 19:38:35 +02002887 }
2888
Nogah Frankel371b4372018-01-10 14:59:57 +01002889 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
2890 if (err) {
2891 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
2892 mlxsw_sp_port->local_port);
2893 goto err_port_qdiscs_init;
2894 }
2895
Ido Schimmelc57529e2017-05-26 08:37:31 +02002896 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
2897 if (IS_ERR(mlxsw_sp_port_vlan)) {
2898 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
Ido Schimmel05978482016-08-17 16:39:30 +02002899 mlxsw_sp_port->local_port);
Wei Yongjund86fd112017-11-06 11:11:28 +00002900 err = PTR_ERR(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002901 goto err_port_vlan_get;
Ido Schimmel05978482016-08-17 16:39:30 +02002902 }
2903
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002904 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02002905 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002906 err = register_netdev(dev);
2907 if (err) {
2908 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2909 mlxsw_sp_port->local_port);
2910 goto err_register_netdev;
2911 }
2912
Elad Razd808c7e2016-10-28 21:35:57 +02002913 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2914 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2915 module);
Nogah Frankel9deef432017-10-26 10:55:32 +02002916 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002917 return 0;
2918
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002919err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02002920 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002921 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002922 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
2923err_port_vlan_get:
Nogah Frankel371b4372018-01-10 14:59:57 +01002924 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
2925err_port_qdiscs_init:
Ido Schimmela1107482017-05-26 08:37:39 +02002926 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
2927err_port_fids_init:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03002928 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002929err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02002930err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002931err_port_buffers_init:
2932err_port_admin_status_set:
2933err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01002934err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002935err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002936err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02002937 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2938err_port_swid_set:
Ido Schimmel2e915e02017-06-08 08:47:45 +02002939 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Ido Schimmel5b153852017-06-08 08:47:44 +02002940err_port_module_map:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002941 kfree(mlxsw_sp_port->sample);
2942err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002943 free_percpu(mlxsw_sp_port->pcpu_stats);
2944err_alloc_stats:
2945 free_netdev(dev);
Ido Schimmel5b153852017-06-08 08:47:44 +02002946err_alloc_etherdev:
Jiri Pirko67963a32016-10-28 21:35:55 +02002947 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2948 return err;
2949}
2950
Ido Schimmel5b153852017-06-08 08:47:44 +02002951static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002952{
2953 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2954
Nogah Frankel9deef432017-10-26 10:55:32 +02002955 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02002956 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002957 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02002958 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002959 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002960 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Nogah Frankel371b4372018-01-10 14:59:57 +01002961 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
Ido Schimmela1107482017-05-26 08:37:39 +02002962 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002963 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01002964 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
Ido Schimmel2e915e02017-06-08 08:47:45 +02002965 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002966 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01002967 free_percpu(mlxsw_sp_port->pcpu_stats);
Ido Schimmel31a08a52017-05-26 08:37:26 +02002968 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002969 free_netdev(mlxsw_sp_port->dev);
Jiri Pirko67963a32016-10-28 21:35:55 +02002970 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2971}
2972
Jiri Pirkof83e2102016-10-28 21:35:49 +02002973static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2974{
2975 return mlxsw_sp->ports[local_port] != NULL;
2976}
2977
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002978static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2979{
2980 int i;
2981
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002982 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002983 if (mlxsw_sp_port_created(mlxsw_sp, i))
2984 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002985 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002986 kfree(mlxsw_sp->ports);
2987}
2988
2989static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2990{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002991 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02002992 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002993 size_t alloc_size;
2994 int i;
2995 int err;
2996
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002997 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002998 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
2999 if (!mlxsw_sp->ports)
3000 return -ENOMEM;
3001
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003002 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3003 GFP_KERNEL);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003004 if (!mlxsw_sp->port_to_module) {
3005 err = -ENOMEM;
3006 goto err_port_to_module_alloc;
3007 }
3008
3009 for (i = 1; i < max_ports; i++) {
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003010 /* Mark as invalid */
3011 mlxsw_sp->port_to_module[i] = -1;
3012
Ido Schimmel558c2d52016-02-26 17:32:29 +01003013 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003014 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01003015 if (err)
3016 goto err_port_module_info_get;
3017 if (!width)
3018 continue;
3019 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02003020 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3021 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003022 if (err)
3023 goto err_port_create;
3024 }
3025 return 0;
3026
3027err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01003028err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003029 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003030 if (mlxsw_sp_port_created(mlxsw_sp, i))
3031 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003032 kfree(mlxsw_sp->port_to_module);
3033err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003034 kfree(mlxsw_sp->ports);
3035 return err;
3036}
3037
Ido Schimmel18f1e702016-02-26 17:32:31 +01003038static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3039{
3040 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3041
3042 return local_port - offset;
3043}
3044
Ido Schimmelbe945352016-06-09 09:51:39 +02003045static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3046 u8 module, unsigned int count)
3047{
3048 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3049 int err, i;
3050
3051 for (i = 0; i < count; i++) {
Ido Schimmelbe945352016-06-09 09:51:39 +02003052 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02003053 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02003054 if (err)
3055 goto err_port_create;
3056 }
3057
3058 return 0;
3059
3060err_port_create:
3061 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003062 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3063 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02003064 return err;
3065}
3066
3067static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3068 u8 base_port, unsigned int count)
3069{
3070 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3071 int i;
3072
3073 /* Split by four means we need to re-create two ports, otherwise
3074 * only one.
3075 */
3076 count = count / 2;
3077
3078 for (i = 0; i < count; i++) {
3079 local_port = base_port + i * 2;
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003080 if (mlxsw_sp->port_to_module[local_port] < 0)
3081 continue;
Ido Schimmelbe945352016-06-09 09:51:39 +02003082 module = mlxsw_sp->port_to_module[local_port];
3083
Ido Schimmelbe945352016-06-09 09:51:39 +02003084 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003085 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003086 }
3087}
3088
Jiri Pirkob2f10572016-04-08 19:11:23 +02003089static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3090 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003091{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003092 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003093 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003094 u8 module, cur_width, base_port;
3095 int i;
3096 int err;
3097
3098 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3099 if (!mlxsw_sp_port) {
3100 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3101 local_port);
3102 return -EINVAL;
3103 }
3104
Ido Schimmeld664b412016-06-09 09:51:40 +02003105 module = mlxsw_sp_port->mapping.module;
3106 cur_width = mlxsw_sp_port->mapping.width;
3107
Ido Schimmel18f1e702016-02-26 17:32:31 +01003108 if (count != 2 && count != 4) {
3109 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3110 return -EINVAL;
3111 }
3112
Ido Schimmel18f1e702016-02-26 17:32:31 +01003113 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3114 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3115 return -EINVAL;
3116 }
3117
3118 /* Make sure we have enough slave (even) ports for the split. */
3119 if (count == 2) {
3120 base_port = local_port;
3121 if (mlxsw_sp->ports[base_port + 1]) {
3122 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3123 return -EINVAL;
3124 }
3125 } else {
3126 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3127 if (mlxsw_sp->ports[base_port + 1] ||
3128 mlxsw_sp->ports[base_port + 3]) {
3129 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3130 return -EINVAL;
3131 }
3132 }
3133
3134 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003135 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3136 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003137
Ido Schimmelbe945352016-06-09 09:51:39 +02003138 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3139 if (err) {
3140 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3141 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003142 }
3143
3144 return 0;
3145
Ido Schimmelbe945352016-06-09 09:51:39 +02003146err_port_split_create:
3147 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003148 return err;
3149}
3150
Jiri Pirkob2f10572016-04-08 19:11:23 +02003151static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003152{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003153 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003154 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003155 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003156 unsigned int count;
3157 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003158
3159 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3160 if (!mlxsw_sp_port) {
3161 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3162 local_port);
3163 return -EINVAL;
3164 }
3165
3166 if (!mlxsw_sp_port->split) {
3167 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3168 return -EINVAL;
3169 }
3170
Ido Schimmeld664b412016-06-09 09:51:40 +02003171 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003172 count = cur_width == 1 ? 4 : 2;
3173
3174 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3175
3176 /* Determine which ports to remove. */
3177 if (count == 2 && local_port >= base_port + 2)
3178 base_port = base_port + 2;
3179
3180 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003181 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3182 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003183
Ido Schimmelbe945352016-06-09 09:51:39 +02003184 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003185
3186 return 0;
3187}
3188
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003189static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3190 char *pude_pl, void *priv)
3191{
3192 struct mlxsw_sp *mlxsw_sp = priv;
3193 struct mlxsw_sp_port *mlxsw_sp_port;
3194 enum mlxsw_reg_pude_oper_status status;
3195 u8 local_port;
3196
3197 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3198 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003199 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003200 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003201
3202 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3203 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3204 netdev_info(mlxsw_sp_port->dev, "link up\n");
3205 netif_carrier_on(mlxsw_sp_port->dev);
3206 } else {
3207 netdev_info(mlxsw_sp_port->dev, "link down\n");
3208 netif_carrier_off(mlxsw_sp_port->dev);
3209 }
3210}
3211
Nogah Frankel14eeda92016-11-25 10:33:32 +01003212static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3213 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003214{
3215 struct mlxsw_sp *mlxsw_sp = priv;
3216 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3217 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3218
3219 if (unlikely(!mlxsw_sp_port)) {
3220 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3221 local_port);
3222 return;
3223 }
3224
3225 skb->dev = mlxsw_sp_port->dev;
3226
3227 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3228 u64_stats_update_begin(&pcpu_stats->syncp);
3229 pcpu_stats->rx_packets++;
3230 pcpu_stats->rx_bytes += skb->len;
3231 u64_stats_update_end(&pcpu_stats->syncp);
3232
3233 skb->protocol = eth_type_trans(skb, skb->dev);
3234 netif_receive_skb(skb);
3235}
3236
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003237static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3238 void *priv)
3239{
3240 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003241 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003242}
3243
Yotam Gigia0040c82017-10-03 09:58:10 +02003244static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3245 u8 local_port, void *priv)
3246{
3247 skb->offload_mr_fwd_mark = 1;
3248 skb->offload_fwd_mark = 1;
3249 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3250}
3251
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003252static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3253 void *priv)
3254{
3255 struct mlxsw_sp *mlxsw_sp = priv;
3256 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3257 struct psample_group *psample_group;
3258 u32 size;
3259
3260 if (unlikely(!mlxsw_sp_port)) {
3261 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3262 local_port);
3263 goto out;
3264 }
3265 if (unlikely(!mlxsw_sp_port->sample)) {
3266 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3267 local_port);
3268 goto out;
3269 }
3270
3271 size = mlxsw_sp_port->sample->truncate ?
3272 mlxsw_sp_port->sample->trunc_size : skb->len;
3273
3274 rcu_read_lock();
3275 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3276 if (!psample_group)
3277 goto out_unlock;
3278 psample_sample_packet(psample_group, skb, size,
3279 mlxsw_sp_port->dev->ifindex, 0,
3280 mlxsw_sp_port->sample->rate);
3281out_unlock:
3282 rcu_read_unlock();
3283out:
3284 consume_skb(skb);
3285}
3286
Nogah Frankel117b0da2016-11-25 10:33:44 +01003287#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003288 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003289 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003290
Nogah Frankel117b0da2016-11-25 10:33:44 +01003291#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003292 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003293 _is_ctrl, SP_##_trap_group, DISCARD)
3294
Yotam Gigia0040c82017-10-03 09:58:10 +02003295#define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3296 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3297 _is_ctrl, SP_##_trap_group, DISCARD)
3298
Nogah Frankel117b0da2016-11-25 10:33:44 +01003299#define MLXSW_SP_EVENTL(_func, _trap_id) \
3300 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003301
Nogah Frankel45449132016-11-25 10:33:35 +01003302static const struct mlxsw_listener mlxsw_sp_listener[] = {
3303 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003304 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003305 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003306 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3307 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3308 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3309 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3310 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3311 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3312 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3313 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3314 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3315 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3316 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003317 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003318 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3319 false),
3320 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3321 false),
3322 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3323 false),
3324 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3325 false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003326 /* L3 traps */
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003327 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3328 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3329 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003330 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003331 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3332 false),
3333 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3334 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3335 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3336 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3337 false),
3338 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3339 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3340 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003341 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003342 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3343 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3344 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3345 false),
3346 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3347 false),
3348 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3349 false),
3350 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3351 false),
3352 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3353 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3354 false),
3355 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3356 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
Ido Schimmel7607dd32017-07-17 14:15:30 +02003357 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003358 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
Petr Machata86484de2017-09-02 23:49:27 +02003359 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003360 /* PKT Sample trap */
3361 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
Jiri Pirko0db7b382017-06-06 14:12:05 +02003362 false, SP_IP2ME, DISCARD),
3363 /* ACL trap */
3364 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
Yotam Gigib48cfc82017-09-19 10:00:20 +02003365 /* Multicast Router Traps */
3366 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3367 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3368 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
Yotam Gigia0040c82017-10-03 09:58:10 +02003369 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003370};
3371
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003372static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3373{
3374 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3375 enum mlxsw_reg_qpcr_ir_units ir_units;
3376 int max_cpu_policers;
3377 bool is_bytes;
3378 u8 burst_size;
3379 u32 rate;
3380 int i, err;
3381
3382 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3383 return -EIO;
3384
3385 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3386
3387 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3388 for (i = 0; i < max_cpu_policers; i++) {
3389 is_bytes = false;
3390 switch (i) {
3391 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3392 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3393 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3394 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003395 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3396 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003397 rate = 128;
3398 burst_size = 7;
3399 break;
3400 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003401 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003402 rate = 16 * 1024;
3403 burst_size = 10;
3404 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003405 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003406 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3407 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003408 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003409 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3410 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003411 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003412 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003413 rate = 1024;
3414 burst_size = 7;
3415 break;
3416 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3417 is_bytes = true;
3418 rate = 4 * 1024;
3419 burst_size = 4;
3420 break;
3421 default:
3422 continue;
3423 }
3424
3425 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3426 burst_size);
3427 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3428 if (err)
3429 return err;
3430 }
3431
3432 return 0;
3433}
3434
Nogah Frankel579c82e2016-11-25 10:33:42 +01003435static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003436{
3437 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003438 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003439 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003440 int max_trap_groups;
3441 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003442 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003443 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003444
3445 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3446 return -EIO;
3447
3448 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003449 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003450
3451 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003452 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003453 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003454 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3455 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3456 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3457 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003458 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003459 priority = 5;
3460 tc = 5;
3461 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003462 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003463 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3464 priority = 4;
3465 tc = 4;
3466 break;
3467 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3468 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003469 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003470 priority = 3;
3471 tc = 3;
3472 break;
3473 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003474 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003475 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003476 priority = 2;
3477 tc = 2;
3478 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003479 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003480 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3481 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003482 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003483 priority = 1;
3484 tc = 1;
3485 break;
3486 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003487 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3488 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003489 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003490 break;
3491 default:
3492 continue;
3493 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003494
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003495 if (max_cpu_policers <= policer_id &&
3496 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3497 return -EIO;
3498
3499 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003500 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3501 if (err)
3502 return err;
3503 }
3504
3505 return 0;
3506}
3507
3508static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3509{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003510 int i;
3511 int err;
3512
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003513 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3514 if (err)
3515 return err;
3516
Nogah Frankel579c82e2016-11-25 10:33:42 +01003517 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003518 if (err)
3519 return err;
3520
Nogah Frankel45449132016-11-25 10:33:35 +01003521 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003522 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003523 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003524 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003525 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003526 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003527
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003528 }
3529 return 0;
3530
Nogah Frankel45449132016-11-25 10:33:35 +01003531err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003532 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003533 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003534 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003535 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003536 }
3537 return err;
3538}
3539
3540static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3541{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003542 int i;
3543
Nogah Frankel45449132016-11-25 10:33:35 +01003544 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003545 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003546 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003547 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003548 }
3549}
3550
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003551static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3552{
3553 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003554 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003555
3556 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3557 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3558 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3559 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3560 MLXSW_REG_SLCR_LAG_HASH_SIP |
3561 MLXSW_REG_SLCR_LAG_HASH_DIP |
3562 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3563 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3564 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003565 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3566 if (err)
3567 return err;
3568
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003569 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3570 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003571 return -EIO;
3572
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003573 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003574 sizeof(struct mlxsw_sp_upper),
3575 GFP_KERNEL);
3576 if (!mlxsw_sp->lags)
3577 return -ENOMEM;
3578
3579 return 0;
3580}
3581
3582static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3583{
3584 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003585}
3586
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003587static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3588{
3589 char htgt_pl[MLXSW_REG_HTGT_LEN];
3590
Nogah Frankel579c82e2016-11-25 10:33:42 +01003591 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3592 MLXSW_REG_HTGT_INVALID_POLICER,
3593 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3594 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003595 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3596}
3597
Petr Machatac30f5d02017-10-16 16:26:35 +02003598static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3599 unsigned long event, void *ptr);
3600
Jiri Pirkob2f10572016-04-08 19:11:23 +02003601static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003602 const struct mlxsw_bus_info *mlxsw_bus_info)
3603{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003604 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003605 int err;
3606
3607 mlxsw_sp->core = mlxsw_core;
3608 mlxsw_sp->bus_info = mlxsw_bus_info;
3609
Yotam Gigi6b742192017-05-23 21:56:29 +02003610 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3611 if (err) {
3612 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3613 return err;
3614 }
3615
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003616 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3617 if (err) {
3618 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3619 return err;
3620 }
3621
Ido Schimmela875a2e2017-10-22 23:11:44 +02003622 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3623 if (err) {
3624 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3625 return err;
3626 }
3627
Ido Schimmela1107482017-05-26 08:37:39 +02003628 err = mlxsw_sp_fids_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003629 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003630 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
Ido Schimmela875a2e2017-10-22 23:11:44 +02003631 goto err_fids_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003632 }
3633
Ido Schimmela1107482017-05-26 08:37:39 +02003634 err = mlxsw_sp_traps_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003635 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003636 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3637 goto err_traps_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003638 }
3639
3640 err = mlxsw_sp_buffers_init(mlxsw_sp);
3641 if (err) {
3642 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3643 goto err_buffers_init;
3644 }
3645
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003646 err = mlxsw_sp_lag_init(mlxsw_sp);
3647 if (err) {
3648 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3649 goto err_lag_init;
3650 }
3651
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003652 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3653 if (err) {
3654 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3655 goto err_switchdev_init;
3656 }
3657
Yotam Gigie2b2d352017-09-19 10:00:08 +02003658 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3659 if (err) {
3660 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3661 goto err_counter_pool_init;
3662 }
3663
Yotam Gigid3b939b2017-09-19 10:00:09 +02003664 err = mlxsw_sp_afa_init(mlxsw_sp);
3665 if (err) {
3666 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3667 goto err_afa_init;
3668 }
3669
Petr Machata803335a2018-02-27 14:53:46 +01003670 err = mlxsw_sp_span_init(mlxsw_sp);
3671 if (err) {
3672 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3673 goto err_span_init;
3674 }
3675
3676 /* Initialize router after SPAN is initialized, so that the FIB and
3677 * neighbor event handlers can issue SPAN respin.
3678 */
Ido Schimmel464dce12016-07-02 11:00:15 +02003679 err = mlxsw_sp_router_init(mlxsw_sp);
3680 if (err) {
3681 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3682 goto err_router_init;
3683 }
3684
Petr Machata803335a2018-02-27 14:53:46 +01003685 /* Initialize netdevice notifier after router and SPAN is initialized,
3686 * so that the event handler can use router structures and call SPAN
3687 * respin.
Petr Machatac30f5d02017-10-16 16:26:35 +02003688 */
3689 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3690 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3691 if (err) {
3692 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3693 goto err_netdev_notifier;
3694 }
3695
Jiri Pirko22a67762017-02-03 10:29:07 +01003696 err = mlxsw_sp_acl_init(mlxsw_sp);
3697 if (err) {
3698 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3699 goto err_acl_init;
3700 }
3701
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003702 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3703 if (err) {
3704 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3705 goto err_dpipe_init;
3706 }
3707
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003708 err = mlxsw_sp_ports_create(mlxsw_sp);
3709 if (err) {
3710 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3711 goto err_ports_create;
3712 }
3713
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003714 return 0;
3715
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003716err_ports_create:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003717 mlxsw_sp_dpipe_fini(mlxsw_sp);
3718err_dpipe_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01003719 mlxsw_sp_acl_fini(mlxsw_sp);
3720err_acl_init:
Petr Machatac30f5d02017-10-16 16:26:35 +02003721 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3722err_netdev_notifier:
Ido Schimmel464dce12016-07-02 11:00:15 +02003723 mlxsw_sp_router_fini(mlxsw_sp);
3724err_router_init:
Petr Machata803335a2018-02-27 14:53:46 +01003725 mlxsw_sp_span_fini(mlxsw_sp);
3726err_span_init:
Yotam Gigid3b939b2017-09-19 10:00:09 +02003727 mlxsw_sp_afa_fini(mlxsw_sp);
3728err_afa_init:
Yotam Gigie2b2d352017-09-19 10:00:08 +02003729 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3730err_counter_pool_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003731 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003732err_switchdev_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003733 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003734err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02003735 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003736err_buffers_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003737 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003738err_traps_init:
3739 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003740err_fids_init:
3741 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003742 return err;
3743}
3744
Jiri Pirkob2f10572016-04-08 19:11:23 +02003745static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003746{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003747 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003748
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003749 mlxsw_sp_ports_remove(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003750 mlxsw_sp_dpipe_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01003751 mlxsw_sp_acl_fini(mlxsw_sp);
Petr Machatac30f5d02017-10-16 16:26:35 +02003752 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
Ido Schimmel464dce12016-07-02 11:00:15 +02003753 mlxsw_sp_router_fini(mlxsw_sp);
Petr Machata803335a2018-02-27 14:53:46 +01003754 mlxsw_sp_span_fini(mlxsw_sp);
Yotam Gigid3b939b2017-09-19 10:00:09 +02003755 mlxsw_sp_afa_fini(mlxsw_sp);
Yotam Gigie2b2d352017-09-19 10:00:08 +02003756 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003757 mlxsw_sp_switchdev_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003758 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02003759 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003760 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003761 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003762 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003763}
3764
Bhumika Goyal159fe882017-08-11 19:10:42 +05303765static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003766 .used_max_vepa_channels = 1,
3767 .max_vepa_channels = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003768 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01003769 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003770 .used_max_pgt = 1,
3771 .max_pgt = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003772 .used_flood_tables = 1,
3773 .used_flood_mode = 1,
3774 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003775 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003776 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003777 .max_fid_flood_tables = 3,
Ido Schimmela1107482017-05-26 08:37:39 +02003778 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003779 .used_max_ib_mc = 1,
3780 .max_ib_mc = 0,
3781 .used_max_pkey = 1,
3782 .max_pkey = 0,
Nogah Frankel403547d2016-09-20 11:16:52 +02003783 .used_kvd_split_data = 1,
3784 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
Ido Schimmelf11fbaf2017-10-22 23:11:49 +02003785 .kvd_hash_single_parts = 59,
3786 .kvd_hash_double_parts = 41,
Jiri Pirkoc6022422016-07-05 11:27:46 +02003787 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003788 .swid_config = {
3789 {
3790 .used_type = 1,
3791 .type = MLXSW_PORT_SWID_TYPE_ETH,
3792 }
3793 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02003794 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003795};
3796
Arkadi Sharshevskyafadc262018-01-15 08:59:09 +01003797static u64 mlxsw_sp_resource_kvd_linear_occ_get(struct devlink *devlink)
3798{
3799 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
3800 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3801
3802 return mlxsw_sp_kvdl_occ_get(mlxsw_sp);
3803}
3804
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003805static struct devlink_resource_ops mlxsw_sp_resource_kvd_linear_ops = {
Arkadi Sharshevskyafadc262018-01-15 08:59:09 +01003806 .occ_get = mlxsw_sp_resource_kvd_linear_occ_get,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003807};
3808
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003809static struct devlink_resource_size_params mlxsw_sp_kvd_size_params;
3810static struct devlink_resource_size_params mlxsw_sp_linear_size_params;
3811static struct devlink_resource_size_params mlxsw_sp_hash_single_size_params;
3812static struct devlink_resource_size_params mlxsw_sp_hash_double_size_params;
3813
3814static void
3815mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core)
3816{
3817 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3818 KVD_SINGLE_MIN_SIZE);
3819 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3820 KVD_DOUBLE_MIN_SIZE);
3821 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3822 u32 linear_size_min = 0;
3823
3824 /* KVD top resource */
3825 mlxsw_sp_kvd_size_params.size_min = kvd_size;
3826 mlxsw_sp_kvd_size_params.size_max = kvd_size;
3827 mlxsw_sp_kvd_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
3828 mlxsw_sp_kvd_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
3829
3830 /* Linear part init */
3831 mlxsw_sp_linear_size_params.size_min = linear_size_min;
3832 mlxsw_sp_linear_size_params.size_max = kvd_size - single_size_min -
3833 double_size_min;
3834 mlxsw_sp_linear_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
3835 mlxsw_sp_linear_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
3836
3837 /* Hash double part init */
3838 mlxsw_sp_hash_double_size_params.size_min = double_size_min;
3839 mlxsw_sp_hash_double_size_params.size_max = kvd_size - single_size_min -
3840 linear_size_min;
3841 mlxsw_sp_hash_double_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
3842 mlxsw_sp_hash_double_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
3843
3844 /* Hash single part init */
3845 mlxsw_sp_hash_single_size_params.size_min = single_size_min;
3846 mlxsw_sp_hash_single_size_params.size_max = kvd_size - double_size_min -
3847 linear_size_min;
3848 mlxsw_sp_hash_single_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
3849 mlxsw_sp_hash_single_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
3850}
3851
3852static int mlxsw_sp_resources_register(struct mlxsw_core *mlxsw_core)
3853{
3854 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3855 u32 kvd_size, single_size, double_size, linear_size;
3856 const struct mlxsw_config_profile *profile;
3857 int err;
3858
3859 profile = &mlxsw_sp_config_profile;
3860 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
3861 return -EIO;
3862
3863 mlxsw_sp_resource_size_params_prepare(mlxsw_core);
3864 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3865 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
3866 true, kvd_size,
3867 MLXSW_SP_RESOURCE_KVD,
3868 DEVLINK_RESOURCE_ID_PARENT_TOP,
3869 &mlxsw_sp_kvd_size_params,
Arkadi Sharshevsky4f4bbf72018-02-20 08:44:21 +01003870 NULL);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003871 if (err)
3872 return err;
3873
3874 linear_size = profile->kvd_linear_size;
3875 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
3876 false, linear_size,
3877 MLXSW_SP_RESOURCE_KVD_LINEAR,
3878 MLXSW_SP_RESOURCE_KVD,
3879 &mlxsw_sp_linear_size_params,
3880 &mlxsw_sp_resource_kvd_linear_ops);
3881 if (err)
3882 return err;
3883
Arkadi Sharshevsky51d3c082018-02-20 08:44:22 +01003884 err = mlxsw_sp_kvdl_resources_register(devlink);
3885 if (err)
3886 return err;
3887
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003888 double_size = kvd_size - linear_size;
3889 double_size *= profile->kvd_hash_double_parts;
3890 double_size /= profile->kvd_hash_double_parts +
3891 profile->kvd_hash_single_parts;
3892 double_size = rounddown(double_size, profile->kvd_hash_granularity);
3893 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
3894 false, double_size,
3895 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3896 MLXSW_SP_RESOURCE_KVD,
3897 &mlxsw_sp_hash_double_size_params,
Arkadi Sharshevsky4f4bbf72018-02-20 08:44:21 +01003898 NULL);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003899 if (err)
3900 return err;
3901
3902 single_size = kvd_size - double_size - linear_size;
3903 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
3904 false, single_size,
3905 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3906 MLXSW_SP_RESOURCE_KVD,
3907 &mlxsw_sp_hash_single_size_params,
Arkadi Sharshevsky4f4bbf72018-02-20 08:44:21 +01003908 NULL);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003909 if (err)
3910 return err;
3911
3912 return 0;
3913}
3914
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01003915static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
3916 const struct mlxsw_config_profile *profile,
3917 u64 *p_single_size, u64 *p_double_size,
3918 u64 *p_linear_size)
3919{
3920 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3921 u32 double_size;
3922 int err;
3923
3924 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3925 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
3926 !profile->used_kvd_split_data)
3927 return -EIO;
3928
3929 /* The hash part is what left of the kvd without the
3930 * linear part. It is split to the single size and
3931 * double size by the parts ratio from the profile.
3932 * Both sizes must be a multiplications of the
3933 * granularity from the profile. In case the user
3934 * provided the sizes they are obtained via devlink.
3935 */
3936 err = devlink_resource_size_get(devlink,
3937 MLXSW_SP_RESOURCE_KVD_LINEAR,
3938 p_linear_size);
3939 if (err)
3940 *p_linear_size = profile->kvd_linear_size;
3941
3942 err = devlink_resource_size_get(devlink,
3943 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3944 p_double_size);
3945 if (err) {
3946 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3947 *p_linear_size;
3948 double_size *= profile->kvd_hash_double_parts;
3949 double_size /= profile->kvd_hash_double_parts +
3950 profile->kvd_hash_single_parts;
3951 *p_double_size = rounddown(double_size,
3952 profile->kvd_hash_granularity);
3953 }
3954
3955 err = devlink_resource_size_get(devlink,
3956 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3957 p_single_size);
3958 if (err)
3959 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3960 *p_double_size - *p_linear_size;
3961
3962 /* Check results are legal. */
3963 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3964 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
3965 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
3966 return -EIO;
3967
3968 return 0;
3969}
3970
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003971static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02003972 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003973 .priv_size = sizeof(struct mlxsw_sp),
3974 .init = mlxsw_sp_init,
3975 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003976 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003977 .port_split = mlxsw_sp_port_split,
3978 .port_unsplit = mlxsw_sp_port_unsplit,
3979 .sb_pool_get = mlxsw_sp_sb_pool_get,
3980 .sb_pool_set = mlxsw_sp_sb_pool_set,
3981 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3982 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3983 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3984 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3985 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3986 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3987 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3988 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3989 .txhdr_construct = mlxsw_sp_txhdr_construct,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003990 .resources_register = mlxsw_sp_resources_register,
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01003991 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003992 .txhdr_len = MLXSW_TXHDR_LEN,
3993 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003994};
3995
Jiri Pirko22a67762017-02-03 10:29:07 +01003996bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003997{
3998 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3999}
4000
Jiri Pirko1182e532017-03-06 21:25:20 +01004001static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07004002{
Jiri Pirko1182e532017-03-06 21:25:20 +01004003 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07004004 int ret = 0;
4005
4006 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01004007 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07004008 ret = 1;
4009 }
4010
4011 return ret;
4012}
4013
Ido Schimmelc57529e2017-05-26 08:37:31 +02004014struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004015{
Jiri Pirko1182e532017-03-06 21:25:20 +01004016 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004017
4018 if (mlxsw_sp_port_dev_check(dev))
4019 return netdev_priv(dev);
4020
Jiri Pirko1182e532017-03-06 21:25:20 +01004021 mlxsw_sp_port = NULL;
4022 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004023
Jiri Pirko1182e532017-03-06 21:25:20 +01004024 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004025}
4026
Ido Schimmel4724ba562017-03-10 08:53:39 +01004027struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004028{
4029 struct mlxsw_sp_port *mlxsw_sp_port;
4030
4031 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4032 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4033}
4034
Arkadi Sharshevskyaf0613782017-06-08 08:44:20 +02004035struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004036{
Jiri Pirko1182e532017-03-06 21:25:20 +01004037 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004038
4039 if (mlxsw_sp_port_dev_check(dev))
4040 return netdev_priv(dev);
4041
Jiri Pirko1182e532017-03-06 21:25:20 +01004042 mlxsw_sp_port = NULL;
4043 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4044 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004045
Jiri Pirko1182e532017-03-06 21:25:20 +01004046 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004047}
4048
4049struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4050{
4051 struct mlxsw_sp_port *mlxsw_sp_port;
4052
4053 rcu_read_lock();
4054 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4055 if (mlxsw_sp_port)
4056 dev_hold(mlxsw_sp_port->dev);
4057 rcu_read_unlock();
4058 return mlxsw_sp_port;
4059}
4060
4061void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4062{
4063 dev_put(mlxsw_sp_port->dev);
4064}
4065
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004066static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004067{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004068 char sldr_pl[MLXSW_REG_SLDR_LEN];
4069
4070 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4071 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4072}
4073
4074static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4075{
4076 char sldr_pl[MLXSW_REG_SLDR_LEN];
4077
4078 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4079 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4080}
4081
4082static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4083 u16 lag_id, u8 port_index)
4084{
4085 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4086 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4087
4088 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4089 lag_id, port_index);
4090 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4091}
4092
4093static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4094 u16 lag_id)
4095{
4096 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4097 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4098
4099 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4100 lag_id);
4101 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4102}
4103
4104static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4105 u16 lag_id)
4106{
4107 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4108 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4109
4110 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4111 lag_id);
4112 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4113}
4114
4115static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4116 u16 lag_id)
4117{
4118 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4119 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4120
4121 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4122 lag_id);
4123 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4124}
4125
4126static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4127 struct net_device *lag_dev,
4128 u16 *p_lag_id)
4129{
4130 struct mlxsw_sp_upper *lag;
4131 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004132 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004133 int i;
4134
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004135 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4136 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004137 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4138 if (lag->ref_count) {
4139 if (lag->dev == lag_dev) {
4140 *p_lag_id = i;
4141 return 0;
4142 }
4143 } else if (free_lag_id < 0) {
4144 free_lag_id = i;
4145 }
4146 }
4147 if (free_lag_id < 0)
4148 return -EBUSY;
4149 *p_lag_id = free_lag_id;
4150 return 0;
4151}
4152
4153static bool
4154mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4155 struct net_device *lag_dev,
David Aherne58376e2017-10-04 17:48:51 -07004156 struct netdev_lag_upper_info *lag_upper_info,
4157 struct netlink_ext_ack *extack)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004158{
4159 u16 lag_id;
4160
David Aherne58376e2017-10-04 17:48:51 -07004161 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004162 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004163 return false;
David Aherne58376e2017-10-04 17:48:51 -07004164 }
4165 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004166 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004167 return false;
David Aherne58376e2017-10-04 17:48:51 -07004168 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004169 return true;
4170}
4171
4172static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4173 u16 lag_id, u8 *p_port_index)
4174{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004175 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004176 int i;
4177
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004178 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4179 MAX_LAG_MEMBERS);
4180 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004181 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4182 *p_port_index = i;
4183 return 0;
4184 }
4185 }
4186 return -EBUSY;
4187}
4188
4189static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4190 struct net_device *lag_dev)
4191{
4192 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004193 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004194 struct mlxsw_sp_upper *lag;
4195 u16 lag_id;
4196 u8 port_index;
4197 int err;
4198
4199 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4200 if (err)
4201 return err;
4202 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4203 if (!lag->ref_count) {
4204 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4205 if (err)
4206 return err;
4207 lag->dev = lag_dev;
4208 }
4209
4210 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4211 if (err)
4212 return err;
4213 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4214 if (err)
4215 goto err_col_port_add;
4216 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4217 if (err)
4218 goto err_col_port_enable;
4219
4220 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4221 mlxsw_sp_port->local_port);
4222 mlxsw_sp_port->lag_id = lag_id;
4223 mlxsw_sp_port->lagged = 1;
4224 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004225
Ido Schimmelc57529e2017-05-26 08:37:31 +02004226 /* Port is no longer usable as a router interface */
4227 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4228 if (mlxsw_sp_port_vlan->fid)
Ido Schimmela1107482017-05-26 08:37:39 +02004229 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004230
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004231 return 0;
4232
Ido Schimmel51554db2016-05-06 22:18:39 +02004233err_col_port_enable:
4234 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004235err_col_port_add:
4236 if (!lag->ref_count)
4237 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004238 return err;
4239}
4240
Ido Schimmel82e6db02016-06-20 23:04:04 +02004241static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4242 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004243{
4244 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004245 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004246 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004247
4248 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004249 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004250 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4251 WARN_ON(lag->ref_count == 0);
4252
Ido Schimmel82e6db02016-06-20 23:04:04 +02004253 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4254 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004255
Ido Schimmelc57529e2017-05-26 08:37:31 +02004256 /* Any VLANs configured on the port are no longer valid */
4257 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004258
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004259 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004260 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004261
4262 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4263 mlxsw_sp_port->local_port);
4264 mlxsw_sp_port->lagged = 0;
4265 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004266
Ido Schimmelc57529e2017-05-26 08:37:31 +02004267 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4268 /* Make sure untagged frames are allowed to ingress */
4269 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004270}
4271
Jiri Pirko74581202015-12-03 12:12:30 +01004272static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4273 u16 lag_id)
4274{
4275 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4276 char sldr_pl[MLXSW_REG_SLDR_LEN];
4277
4278 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4279 mlxsw_sp_port->local_port);
4280 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4281}
4282
4283static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4284 u16 lag_id)
4285{
4286 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4287 char sldr_pl[MLXSW_REG_SLDR_LEN];
4288
4289 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4290 mlxsw_sp_port->local_port);
4291 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4292}
4293
4294static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4295 bool lag_tx_enabled)
4296{
4297 if (lag_tx_enabled)
4298 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4299 mlxsw_sp_port->lag_id);
4300 else
4301 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4302 mlxsw_sp_port->lag_id);
4303}
4304
4305static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4306 struct netdev_lag_lower_state_info *info)
4307{
4308 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4309}
4310
Jiri Pirko2b94e582017-04-18 16:55:37 +02004311static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4312 bool enable)
4313{
4314 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4315 enum mlxsw_reg_spms_state spms_state;
4316 char *spms_pl;
4317 u16 vid;
4318 int err;
4319
4320 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4321 MLXSW_REG_SPMS_STATE_DISCARDING;
4322
4323 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4324 if (!spms_pl)
4325 return -ENOMEM;
4326 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4327
4328 for (vid = 0; vid < VLAN_N_VID; vid++)
4329 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4330
4331 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4332 kfree(spms_pl);
4333 return err;
4334}
4335
4336static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4337{
Yuval Mintzfccff082017-12-15 08:44:21 +01004338 u16 vid = 1;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004339 int err;
4340
Ido Schimmel4aafc362017-05-26 08:37:25 +02004341 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004342 if (err)
4343 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02004344 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4345 if (err)
4346 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004347 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4348 true, false);
4349 if (err)
4350 goto err_port_vlan_set;
Yuval Mintzfccff082017-12-15 08:44:21 +01004351
4352 for (; vid <= VLAN_N_VID - 1; vid++) {
4353 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4354 vid, false);
4355 if (err)
4356 goto err_vid_learning_set;
4357 }
4358
Jiri Pirko2b94e582017-04-18 16:55:37 +02004359 return 0;
4360
Yuval Mintzfccff082017-12-15 08:44:21 +01004361err_vid_learning_set:
4362 for (vid--; vid >= 1; vid--)
4363 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004364err_port_vlan_set:
4365 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004366err_port_stp_set:
4367 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004368 return err;
4369}
4370
4371static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4372{
Yuval Mintzfccff082017-12-15 08:44:21 +01004373 u16 vid;
4374
4375 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4376 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4377 vid, true);
4378
Jiri Pirko2b94e582017-04-18 16:55:37 +02004379 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4380 false, false);
4381 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004382 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004383}
4384
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004385static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4386 struct net_device *dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004387 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004388{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004389 struct netdev_notifier_changeupper_info *info;
4390 struct mlxsw_sp_port *mlxsw_sp_port;
David Aherne58376e2017-10-04 17:48:51 -07004391 struct netlink_ext_ack *extack;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004392 struct net_device *upper_dev;
4393 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004394 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004395
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004396 mlxsw_sp_port = netdev_priv(dev);
4397 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4398 info = ptr;
David Aherne58376e2017-10-04 17:48:51 -07004399 extack = netdev_notifier_info_to_extack(&info->info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004400
4401 switch (event) {
4402 case NETDEV_PRECHANGEUPPER:
4403 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004404 if (!is_vlan_dev(upper_dev) &&
4405 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004406 !netif_is_bridge_master(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004407 !netif_is_ovs_master(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004408 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004409 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004410 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004411 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004412 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004413 if (netdev_has_any_upper_dev(upper_dev) &&
4414 (!netif_is_bridge_master(upper_dev) ||
4415 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4416 upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004417 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004418 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004419 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004420 if (netif_is_lag_master(upper_dev) &&
4421 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
David Aherne58376e2017-10-04 17:48:51 -07004422 info->upper_info, extack))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004423 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004424 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004425 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004426 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004427 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004428 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004429 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004430 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004431 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004432 }
4433 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004434 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004435 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004436 }
4437 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004438 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004439 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004440 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004441 break;
4442 case NETDEV_CHANGEUPPER:
4443 upper_dev = info->upper_dev;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004444 if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004445 if (info->linking)
4446 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004447 lower_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004448 upper_dev,
4449 extack);
Ido Schimmel7117a572016-06-20 23:04:06 +02004450 else
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004451 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4452 lower_dev,
4453 upper_dev);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004454 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004455 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004456 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4457 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004458 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004459 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4460 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004461 } else if (netif_is_ovs_master(upper_dev)) {
4462 if (info->linking)
4463 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4464 else
4465 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004466 }
4467 break;
4468 }
4469
Ido Schimmel80bedf12016-06-20 23:03:59 +02004470 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004471}
4472
Jiri Pirko74581202015-12-03 12:12:30 +01004473static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4474 unsigned long event, void *ptr)
4475{
4476 struct netdev_notifier_changelowerstate_info *info;
4477 struct mlxsw_sp_port *mlxsw_sp_port;
4478 int err;
4479
4480 mlxsw_sp_port = netdev_priv(dev);
4481 info = ptr;
4482
4483 switch (event) {
4484 case NETDEV_CHANGELOWERSTATE:
4485 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4486 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4487 info->lower_state_info);
4488 if (err)
4489 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4490 }
4491 break;
4492 }
4493
Ido Schimmel80bedf12016-06-20 23:03:59 +02004494 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004495}
4496
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004497static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4498 struct net_device *port_dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004499 unsigned long event, void *ptr)
4500{
4501 switch (event) {
4502 case NETDEV_PRECHANGEUPPER:
4503 case NETDEV_CHANGEUPPER:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004504 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4505 event, ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004506 case NETDEV_CHANGELOWERSTATE:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004507 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4508 ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004509 }
4510
Ido Schimmel80bedf12016-06-20 23:03:59 +02004511 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004512}
4513
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004514static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4515 unsigned long event, void *ptr)
4516{
4517 struct net_device *dev;
4518 struct list_head *iter;
4519 int ret;
4520
4521 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4522 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004523 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4524 ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004525 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004526 return ret;
4527 }
4528 }
4529
Ido Schimmel80bedf12016-06-20 23:03:59 +02004530 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004531}
4532
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004533static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4534 struct net_device *dev,
4535 unsigned long event, void *ptr,
4536 u16 vid)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004537{
4538 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel90045fc2017-12-25 09:05:33 +01004539 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004540 struct netdev_notifier_changeupper_info *info = ptr;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004541 struct netlink_ext_ack *extack;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004542 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004543 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004544
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004545 extack = netdev_notifier_info_to_extack(&info->info);
4546
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004547 switch (event) {
4548 case NETDEV_PRECHANGEUPPER:
4549 upper_dev = info->upper_dev;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004550 if (!netif_is_bridge_master(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004551 NL_SET_ERR_MSG_MOD(extack, "VLAN devices only support bridge and VRF uppers");
Ido Schimmel80bedf12016-06-20 23:03:59 +02004552 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004553 }
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004554 if (!info->linking)
4555 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004556 if (netdev_has_any_upper_dev(upper_dev) &&
4557 (!netif_is_bridge_master(upper_dev) ||
4558 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4559 upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004560 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004561 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004562 }
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004563 break;
4564 case NETDEV_CHANGEUPPER:
4565 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004566 if (netif_is_bridge_master(upper_dev)) {
4567 if (info->linking)
Ido Schimmelc57529e2017-05-26 08:37:31 +02004568 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4569 vlan_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004570 upper_dev,
4571 extack);
Ido Schimmel1f880612017-03-10 08:53:35 +01004572 else
Ido Schimmelc57529e2017-05-26 08:37:31 +02004573 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4574 vlan_dev,
4575 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004576 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004577 err = -EINVAL;
4578 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004579 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004580 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004581 }
4582
Ido Schimmel80bedf12016-06-20 23:03:59 +02004583 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004584}
4585
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004586static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4587 struct net_device *lag_dev,
4588 unsigned long event,
4589 void *ptr, u16 vid)
Ido Schimmel272c4472015-12-15 16:03:47 +01004590{
4591 struct net_device *dev;
4592 struct list_head *iter;
4593 int ret;
4594
4595 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4596 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004597 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4598 event, ptr,
4599 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004600 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004601 return ret;
4602 }
4603 }
4604
Ido Schimmel80bedf12016-06-20 23:03:59 +02004605 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004606}
4607
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004608static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4609 unsigned long event, void *ptr)
4610{
4611 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4612 u16 vid = vlan_dev_vlan_id(vlan_dev);
4613
Ido Schimmel272c4472015-12-15 16:03:47 +01004614 if (mlxsw_sp_port_dev_check(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004615 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4616 event, ptr, vid);
Ido Schimmel272c4472015-12-15 16:03:47 +01004617 else if (netif_is_lag_master(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004618 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4619 real_dev, event,
4620 ptr, vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004621
Ido Schimmel80bedf12016-06-20 23:03:59 +02004622 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004623}
4624
Ido Schimmelb1e45522017-04-30 19:47:14 +03004625static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4626{
4627 struct netdev_notifier_changeupper_info *info = ptr;
4628
4629 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4630 return false;
4631 return netif_is_l3_master(info->upper_dev);
4632}
4633
Petr Machata00635872017-10-16 16:26:37 +02004634static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004635 unsigned long event, void *ptr)
4636{
4637 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Petr Machata079c9f32018-02-27 14:53:44 +01004638 struct mlxsw_sp_span_entry *span_entry;
Petr Machata00635872017-10-16 16:26:37 +02004639 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004640 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004641
Petr Machata00635872017-10-16 16:26:37 +02004642 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
Petr Machata079c9f32018-02-27 14:53:44 +01004643 if (event == NETDEV_UNREGISTER) {
4644 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
4645 if (span_entry)
4646 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
4647 }
Petr Machata803335a2018-02-27 14:53:46 +01004648 mlxsw_sp_span_respin(mlxsw_sp);
Petr Machata079c9f32018-02-27 14:53:44 +01004649
Petr Machata796ec772017-11-03 10:03:29 +01004650 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
4651 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
4652 event, ptr);
Petr Machata61481f22017-11-03 10:03:41 +01004653 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
4654 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
4655 event, ptr);
Petr Machata00635872017-10-16 16:26:37 +02004656 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004657 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03004658 else if (mlxsw_sp_is_vrf_event(event, ptr))
4659 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004660 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004661 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004662 else if (netif_is_lag_master(dev))
4663 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4664 else if (is_vlan_dev(dev))
4665 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004666
Ido Schimmel80bedf12016-06-20 23:03:59 +02004667 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004668}
4669
David Ahern89d5dd22017-10-18 09:56:55 -07004670static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
4671 .notifier_call = mlxsw_sp_inetaddr_valid_event,
4672};
4673
Ido Schimmel99724c12016-07-04 08:23:14 +02004674static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4675 .notifier_call = mlxsw_sp_inetaddr_event,
David Ahern89d5dd22017-10-18 09:56:55 -07004676};
4677
4678static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
4679 .notifier_call = mlxsw_sp_inet6addr_valid_event,
Ido Schimmel99724c12016-07-04 08:23:14 +02004680};
4681
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004682static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
4683 .notifier_call = mlxsw_sp_inet6addr_event,
4684};
4685
Jiri Pirko1d20d232016-10-27 15:12:59 +02004686static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4687 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4688 {0, },
4689};
4690
4691static struct pci_driver mlxsw_sp_pci_driver = {
4692 .name = mlxsw_sp_driver_name,
4693 .id_table = mlxsw_sp_pci_id_table,
4694};
4695
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004696static int __init mlxsw_sp_module_init(void)
4697{
4698 int err;
4699
David Ahern89d5dd22017-10-18 09:56:55 -07004700 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004701 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004702 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004703 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004704
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004705 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4706 if (err)
4707 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02004708
4709 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4710 if (err)
4711 goto err_pci_driver_register;
4712
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004713 return 0;
4714
Jiri Pirko1d20d232016-10-27 15:12:59 +02004715err_pci_driver_register:
4716 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004717err_core_driver_register:
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004718 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004719 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02004720 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004721 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004722 return err;
4723}
4724
4725static void __exit mlxsw_sp_module_exit(void)
4726{
Jiri Pirko1d20d232016-10-27 15:12:59 +02004727 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004728 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004729 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004730 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004731 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004732 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004733}
4734
4735module_init(mlxsw_sp_module_init);
4736module_exit(mlxsw_sp_module_exit);
4737
4738MODULE_LICENSE("Dual BSD/GPL");
4739MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4740MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02004741MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Yotam Gigi6b742192017-05-23 21:56:29 +02004742MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);