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gerrit-public.fairphone.software / platform / external / llvm / a8512edb6d1c52209bad2d6b989599bc4872c913 / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 3d33ce2c2c2fdcb43ef974bf5f7f69f8a4b121cc [file] [log] [blame]
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "ARM.h"
13#include "ARMRegisterInfo.h"
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]14#include "ARMSubtarget.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]17#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]18#include "llvm/MC/MCInst.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]21#include "llvm/MC/MCDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]22#include "llvm/Support/Debug.h"
23#include "llvm/Support/MemoryObject.h"
24#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]25#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]26#include "llvm/Support/raw_ostream.h"
27
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]28using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]29
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]32namespace {
33/// ARMDisassembler - ARM disassembler for all ARM platforms.
34class ARMDisassembler : public MCDisassembler {
35public:
36 /// Constructor - Initializes the disassembler.
37 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]38 ARMDisassembler(const MCSubtargetInfo &STI) :
39 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]40 }
41
42 ~ARMDisassembler() {
43 }
44
45 /// getInstruction - See MCDisassembler.
46 DecodeStatus getInstruction(MCInst &instr,
47 uint64_t &size,
48 const MemoryObject &region,
49 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]50 raw_ostream &vStream,
51 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]52
53 /// getEDInfo - See MCDisassembler.
54 EDInstInfo *getEDInfo() const;
55private:
56};
57
58/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
59class ThumbDisassembler : public MCDisassembler {
60public:
61 /// Constructor - Initializes the disassembler.
62 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]63 ThumbDisassembler(const MCSubtargetInfo &STI) :
64 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]65 }
66
67 ~ThumbDisassembler() {
68 }
69
70 /// getInstruction - See MCDisassembler.
71 DecodeStatus getInstruction(MCInst &instr,
72 uint64_t &size,
73 const MemoryObject &region,
74 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]75 raw_ostream &vStream,
76 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]77
78 /// getEDInfo - See MCDisassembler.
79 EDInstInfo *getEDInfo() const;
80private:
81 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]82 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]83 void UpdateThumbVFPPredicate(MCInst&) const;
84};
85}
86
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]87static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]88 switch (In) {
89 case MCDisassembler::Success:
90 // Out stays the same.
91 return true;
92 case MCDisassembler::SoftFail:
93 Out = In;
94 return true;
95 case MCDisassembler::Fail:
96 Out = In;
97 return false;
98 }
99 return false;
100}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]101
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]102
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]103// Forward declare these because the autogenerated code will reference them.
104// Definitions are further down.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]105static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]106 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]107static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]108 unsigned RegNo, uint64_t Address,
109 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]110static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]111 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]112static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]113 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]114static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]115 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]116static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]117 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]118static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]119 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]120static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]121 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]122static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]123 unsigned RegNo,
124 uint64_t Address,
125 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]126static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]127 uint64_t Address, const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]128
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]129static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]130 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]131static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]132 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]133static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]134 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]135static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]136 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]137static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]138 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]139static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]140 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]141
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]142static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]143 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]144static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]145 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]146static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]147 unsigned Insn,
148 uint64_t Address,
149 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]150static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]151 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]152static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]153 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]154static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]155 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]156static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]157 uint64_t Address, const void *Decoder);
158
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]159static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]160 unsigned Insn,
161 uint64_t Adddress,
162 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]163static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]164 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]165static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]166 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]167static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]168 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]169static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]170 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]171static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]172 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]173static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]174 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]175static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]176 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]177static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]178 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]179static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]180 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]181static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]182 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]183static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]184 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]185static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]186 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]187static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]188 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]189static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]190 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]191static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]192 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]193static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]194 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]195static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]196 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]197static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]198 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]199static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]200 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]201static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]202 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]203static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]204 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]205static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]206 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]207static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]208 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]209static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]210 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]211static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]212 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]213static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]214 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]215static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]216 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]217static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]218 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]219static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]220 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]221static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]222 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]223static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]224 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]225static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]226 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]227static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]228 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]229static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]230 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]231static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]232 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]233static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]234 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]235static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]236 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]237static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]238 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]239static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]240 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]241static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]242 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]243static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]244 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]245static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]246 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]247
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]248static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]250static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]252static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]253 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]254static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]255 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]256static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]257 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]258static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]259 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]260static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]261 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]262static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]263 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]264static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]265 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]266static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]267 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]268static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]269 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]270static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]271 uint64_t Address, const void *Decoder);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]272static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
273 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]274static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]275 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]276static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]277 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]278static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]279 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]280static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]281 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]282static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]283 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]284static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]285 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]286static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]287 uint64_t Address, const void *Decoder);
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]288static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val,
289 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]290static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]291 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]292static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]293 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]294static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]295 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]296static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]297 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]298static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]299 uint64_t Address, const void *Decoder);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]300static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
301 uint64_t Address, const void *Decoder);
302static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
303 uint64_t Address, const void *Decoder);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]304static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
305 uint64_t Address, const void *Decoder);
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]306static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
307 uint64_t Address, const void *Decoder);
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]308static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
309 uint64_t Address, const void *Decoder);
310
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]311
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]312
313#include "ARMGenDisassemblerTables.inc"
314#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]315#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]316
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]317static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
318 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]319}
320
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]321static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
322 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]323}
324
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]325EDInstInfo *ARMDisassembler::getEDInfo() const {
326 return instInfoARM;
327}
328
329EDInstInfo *ThumbDisassembler::getEDInfo() const {
330 return instInfoARM;
331}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]332
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]333DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]334 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]335 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]336 raw_ostream &os,
337 raw_ostream &cs) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]338 uint8_t bytes[4];
339
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]340 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
341 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
342
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]343 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]344 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
345 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]346 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]347 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]348
349 // Encoded as a small-endian 32-bit word in the stream.
350 uint32_t insn = (bytes[3] << 24) |
351 (bytes[2] << 16) |
352 (bytes[1] << 8) |
353 (bytes[0] << 0);
354
355 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]356 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]357 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]358 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]359 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]360 }
361
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]362 // VFP and NEON instructions, similarly, are shared between ARM
363 // and Thumb modes.
364 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]365 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]366 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]367 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]368 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]369 }
370
371 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]372 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]373 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]374 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]375 // Add a fake predicate operand, because we share these instruction
376 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]377 if (!DecodePredicateOperand(MI, 0xE, Address, this))
378 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]379 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]380 }
381
382 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]383 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]384 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]385 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]386 // Add a fake predicate operand, because we share these instruction
387 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]388 if (!DecodePredicateOperand(MI, 0xE, Address, this))
389 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]390 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]391 }
392
393 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]394 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]395 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]396 Size = 4;
397 // Add a fake predicate operand, because we share these instruction
398 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]399 if (!DecodePredicateOperand(MI, 0xE, Address, this))
400 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]401 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]402 }
403
404 MI.clear();
405
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]406 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]407 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]408}
409
410namespace llvm {
411extern MCInstrDesc ARMInsts[];
412}
413
414// Thumb1 instructions don't have explicit S bits. Rather, they
415// implicitly set CPSR. Since it's not represented in the encoding, the
416// auto-generated decoder won't inject the CPSR operand. We need to fix
417// that as a post-pass.
418static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
419 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]420 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]421 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]422 for (unsigned i = 0; i < NumOps; ++i, ++I) {
423 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]424 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]425 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]426 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
427 return;
428 }
429 }
430
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]431 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]432}
433
434// Most Thumb instructions don't have explicit predicates in the
435// encoding, but rather get their predicates from IT context. We need
436// to fix up the predicate operands using this context information as a
437// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]438MCDisassembler::DecodeStatus
439ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]440 MCDisassembler::DecodeStatus S = Success;
441
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]442 // A few instructions actually have predicates encoded in them. Don't
443 // try to overwrite it if we're seeing one of those.
444 switch (MI.getOpcode()) {
445 case ARM::tBcc:
446 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]447 case ARM::tCBZ:
448 case ARM::tCBNZ:
Owen Anderson9f666b52011-09-19 23:47:10 +0000[diff] [blame]449 case ARM::tCPS:
450 case ARM::t2CPS3p:
451 case ARM::t2CPS2p:
452 case ARM::t2CPS1p:
Owen Andersond9346fb2011-09-19 23:57:20 +0000[diff] [blame]453 case ARM::tMOVSr:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]454 // Some instructions (mostly conditional branches) are not
455 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]456 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]457 S = SoftFail;
458 else
459 return Success;
460 break;
461 case ARM::tB:
462 case ARM::t2B:
Owen Anderson04c78772011-09-19 22:34:23 +0000[diff] [blame]463 case ARM::t2TBB:
464 case ARM::t2TBH:
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]465 // Some instructions (mostly unconditional branches) can
466 // only appears at the end of, or outside of, an IT.
467 if (ITBlock.size() > 1)
468 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]469 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]470 default:
471 break;
472 }
473
474 // If we're in an IT block, base the predicate on that. Otherwise,
475 // assume a predicate of AL.
476 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]477 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]478 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]479 if (CC == 0xF)
480 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]481 ITBlock.pop_back();
482 } else
483 CC = ARMCC::AL;
484
485 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]486 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]487 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]488 for (unsigned i = 0; i < NumOps; ++i, ++I) {
489 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]490 if (OpInfo[i].isPredicate()) {
491 I = MI.insert(I, MCOperand::CreateImm(CC));
492 ++I;
493 if (CC == ARMCC::AL)
494 MI.insert(I, MCOperand::CreateReg(0));
495 else
496 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]497 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]498 }
499 }
500
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]501 I = MI.insert(I, MCOperand::CreateImm(CC));
502 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]503 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]504 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]505 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]506 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]507
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]508 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]509}
510
511// Thumb VFP instructions are a special case. Because we share their
512// encodings between ARM and Thumb modes, and they are predicable in ARM
513// mode, the auto-generated decoder will give them an (incorrect)
514// predicate operand. We need to rewrite these operands based on the IT
515// context as a post-pass.
516void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
517 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]518 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]519 CC = ITBlock.back();
520 ITBlock.pop_back();
521 } else
522 CC = ARMCC::AL;
523
524 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
525 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]526 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
527 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]528 if (OpInfo[i].isPredicate() ) {
529 I->setImm(CC);
530 ++I;
531 if (CC == ARMCC::AL)
532 I->setReg(0);
533 else
534 I->setReg(ARM::CPSR);
535 return;
536 }
537 }
538}
539
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]540DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]541 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]542 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]543 raw_ostream &os,
544 raw_ostream &cs) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]545 uint8_t bytes[4];
546
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]547 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
548 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
549
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]550 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]551 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
552 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]553 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]554 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]555
556 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]557 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]558 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]559 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]560 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]561 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]562 }
563
564 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]565 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]566 if (result) {
567 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]568 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]569 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]570 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]571 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]572 }
573
574 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]575 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]576 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]577 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]578 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]579
580 // If we find an IT instruction, we need to parse its condition
581 // code and mask operands so that we can apply them correctly
582 // to the subsequent instructions.
583 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]584 // Nested IT blocks are UNPREDICTABLE.
585 if (!ITBlock.empty())
586 return MCDisassembler::SoftFail;
587
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]588 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]589 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]590 unsigned Mask = MI.getOperand(1).getImm();
591 unsigned CondBit0 = Mask >> 4 & 1;
592 unsigned NumTZ = CountTrailingZeros_32(Mask);
593 assert(NumTZ <= 3 && "Invalid IT mask!");
594 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
595 bool T = ((Mask >> Pos) & 1) == CondBit0;
596 if (T)
597 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]598 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]599 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]600 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]601
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]602 ITBlock.push_back(firstcond);
603 }
604
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]605 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]606 }
607
608 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]609 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
610 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]611 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]612 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]613
614 uint32_t insn32 = (bytes[3] << 8) |
615 (bytes[2] << 0) |
616 (bytes[1] << 24) |
617 (bytes[0] << 16);
618 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]619 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]620 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]621 Size = 4;
622 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]623 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]624 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]625 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]626 }
627
628 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]629 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]630 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]631 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]632 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]633 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]634 }
635
636 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]637 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]638 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]639 Size = 4;
640 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]641 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]642 }
643
644 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]645 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]646 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]647 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]648 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]649 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]650 }
651
652 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
653 MI.clear();
654 uint32_t NEONLdStInsn = insn32;
655 NEONLdStInsn &= 0xF0FFFFFF;
656 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]657 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]658 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]659 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]660 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]661 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]662 }
663 }
664
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]665 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]666 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]667 uint32_t NEONDataInsn = insn32;
668 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
669 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
670 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]671 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]672 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]673 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]674 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]675 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]676 }
677 }
678
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]679 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]680 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]681}
682
683
684extern "C" void LLVMInitializeARMDisassembler() {
685 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
686 createARMDisassembler);
687 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
688 createThumbDisassembler);
689}
690
691static const unsigned GPRDecoderTable[] = {
692 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
693 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
694 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
695 ARM::R12, ARM::SP, ARM::LR, ARM::PC
696};
697
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]698static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]699 uint64_t Address, const void *Decoder) {
700 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]701 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]702
703 unsigned Register = GPRDecoderTable[RegNo];
704 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]705 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]706}
707
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]708static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]709DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
710 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]711 if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]712 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
713}
714
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]715static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]716 uint64_t Address, const void *Decoder) {
717 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]718 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]719 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
720}
721
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]722static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]723 uint64_t Address, const void *Decoder) {
724 unsigned Register = 0;
725 switch (RegNo) {
726 case 0:
727 Register = ARM::R0;
728 break;
729 case 1:
730 Register = ARM::R1;
731 break;
732 case 2:
733 Register = ARM::R2;
734 break;
735 case 3:
736 Register = ARM::R3;
737 break;
738 case 9:
739 Register = ARM::R9;
740 break;
741 case 12:
742 Register = ARM::R12;
743 break;
744 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]745 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]746 }
747
748 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]749 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]750}
751
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]752static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]753 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]754 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]755 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
756}
757
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]758static const unsigned SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]759 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
760 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
761 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
762 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
763 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
764 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
765 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
766 ARM::S28, ARM::S29, ARM::S30, ARM::S31
767};
768
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]769static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]770 uint64_t Address, const void *Decoder) {
771 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]772 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]773
774 unsigned Register = SPRDecoderTable[RegNo];
775 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]776 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]777}
778
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]779static const unsigned DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]780 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
781 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
782 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
783 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
784 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
785 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
786 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
787 ARM::D28, ARM::D29, ARM::D30, ARM::D31
788};
789
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]790static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]791 uint64_t Address, const void *Decoder) {
792 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]793 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]794
795 unsigned Register = DPRDecoderTable[RegNo];
796 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]797 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]798}
799
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]800static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]801 uint64_t Address, const void *Decoder) {
802 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]803 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]804 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
805}
806
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]807static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]808DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
809 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]810 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]811 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]812 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
813}
814
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]815static const unsigned QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]816 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
817 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
818 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
819 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
820};
821
822
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]823static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]824 uint64_t Address, const void *Decoder) {
825 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]826 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]827 RegNo >>= 1;
828
829 unsigned Register = QPRDecoderTable[RegNo];
830 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]831 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]832}
833
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]834static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]835 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]836 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]837 // AL predicate is not allowed on Thumb1 branches.
838 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]839 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]840 Inst.addOperand(MCOperand::CreateImm(Val));
841 if (Val == ARMCC::AL) {
842 Inst.addOperand(MCOperand::CreateReg(0));
843 } else
844 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]845 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]846}
847
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]848static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]849 uint64_t Address, const void *Decoder) {
850 if (Val)
851 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
852 else
853 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]854 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]855}
856
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]857static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]858 uint64_t Address, const void *Decoder) {
859 uint32_t imm = Val & 0xFF;
860 uint32_t rot = (Val & 0xF00) >> 7;
861 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
862 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]863 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]864}
865
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]866static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]867 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]868 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]869
870 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
871 unsigned type = fieldFromInstruction32(Val, 5, 2);
872 unsigned imm = fieldFromInstruction32(Val, 7, 5);
873
874 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
876 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]877
878 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
879 switch (type) {
880 case 0:
881 Shift = ARM_AM::lsl;
882 break;
883 case 1:
884 Shift = ARM_AM::lsr;
885 break;
886 case 2:
887 Shift = ARM_AM::asr;
888 break;
889 case 3:
890 Shift = ARM_AM::ror;
891 break;
892 }
893
894 if (Shift == ARM_AM::ror && imm == 0)
895 Shift = ARM_AM::rrx;
896
897 unsigned Op = Shift | (imm << 3);
898 Inst.addOperand(MCOperand::CreateImm(Op));
899
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]900 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]901}
902
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]903static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]904 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]905 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]906
907 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
908 unsigned type = fieldFromInstruction32(Val, 5, 2);
909 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
910
911 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]912 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
913 return MCDisassembler::Fail;
914 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
915 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]916
917 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
918 switch (type) {
919 case 0:
920 Shift = ARM_AM::lsl;
921 break;
922 case 1:
923 Shift = ARM_AM::lsr;
924 break;
925 case 2:
926 Shift = ARM_AM::asr;
927 break;
928 case 3:
929 Shift = ARM_AM::ror;
930 break;
931 }
932
933 Inst.addOperand(MCOperand::CreateImm(Shift));
934
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]935 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]936}
937
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]938static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]939 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]940 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]941
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]942 bool writebackLoad = false;
943 unsigned writebackReg = 0;
944 switch (Inst.getOpcode()) {
945 default:
946 break;
947 case ARM::LDMIA_UPD:
948 case ARM::LDMDB_UPD:
949 case ARM::LDMIB_UPD:
950 case ARM::LDMDA_UPD:
951 case ARM::t2LDMIA_UPD:
952 case ARM::t2LDMDB_UPD:
953 writebackLoad = true;
954 writebackReg = Inst.getOperand(0).getReg();
955 break;
956 }
957
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]958 // Empty register lists are not allowed.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]959 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]960 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]961 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]962 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
963 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]964 // Writeback not allowed if Rn is in the target list.
965 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
966 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]967 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]968 }
969
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]970 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]971}
972
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]973static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]974 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]975 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]976
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]977 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
978 unsigned regs = Val & 0xFF;
979
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]980 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
981 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]982 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]983 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
984 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]985 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]986
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]987 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]988}
989
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]990static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]991 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]992 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]993
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]994 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
995 unsigned regs = (Val & 0xFF) / 2;
996
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]997 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
998 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]999 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1000 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1001 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1002 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1003
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1004 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1005}
1006
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1007static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1008 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1009 // This operand encodes a mask of contiguous zeros between a specified MSB
1010 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1011 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1012 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1013 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1014 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1015 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1016
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1017 DecodeStatus S = MCDisassembler::Success;
1018 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1019
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1020 uint32_t msb_mask = 0xFFFFFFFF;
1021 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1022 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1023
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1024 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1025 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1026}
1027
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1028static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1029 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1030 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1031
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1032 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1033 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1034 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1035 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1036 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1037 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1038
1039 switch (Inst.getOpcode()) {
1040 case ARM::LDC_OFFSET:
1041 case ARM::LDC_PRE:
1042 case ARM::LDC_POST:
1043 case ARM::LDC_OPTION:
1044 case ARM::LDCL_OFFSET:
1045 case ARM::LDCL_PRE:
1046 case ARM::LDCL_POST:
1047 case ARM::LDCL_OPTION:
1048 case ARM::STC_OFFSET:
1049 case ARM::STC_PRE:
1050 case ARM::STC_POST:
1051 case ARM::STC_OPTION:
1052 case ARM::STCL_OFFSET:
1053 case ARM::STCL_PRE:
1054 case ARM::STCL_POST:
1055 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1056 case ARM::t2LDC_OFFSET:
1057 case ARM::t2LDC_PRE:
1058 case ARM::t2LDC_POST:
1059 case ARM::t2LDC_OPTION:
1060 case ARM::t2LDCL_OFFSET:
1061 case ARM::t2LDCL_PRE:
1062 case ARM::t2LDCL_POST:
1063 case ARM::t2LDCL_OPTION:
1064 case ARM::t2STC_OFFSET:
1065 case ARM::t2STC_PRE:
1066 case ARM::t2STC_POST:
1067 case ARM::t2STC_OPTION:
1068 case ARM::t2STCL_OFFSET:
1069 case ARM::t2STCL_PRE:
1070 case ARM::t2STCL_POST:
1071 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1072 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1073 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1074 break;
1075 default:
1076 break;
1077 }
1078
1079 Inst.addOperand(MCOperand::CreateImm(coproc));
1080 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1081 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1082 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1083 switch (Inst.getOpcode()) {
1084 case ARM::LDC_OPTION:
1085 case ARM::LDCL_OPTION:
1086 case ARM::LDC2_OPTION:
1087 case ARM::LDC2L_OPTION:
1088 case ARM::STC_OPTION:
1089 case ARM::STCL_OPTION:
1090 case ARM::STC2_OPTION:
1091 case ARM::STC2L_OPTION:
1092 case ARM::LDCL_POST:
1093 case ARM::STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1094 case ARM::LDC2L_POST:
1095 case ARM::STC2L_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1096 case ARM::t2LDC_OPTION:
1097 case ARM::t2LDCL_OPTION:
1098 case ARM::t2STC_OPTION:
1099 case ARM::t2STCL_OPTION:
1100 case ARM::t2LDCL_POST:
1101 case ARM::t2STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1102 break;
1103 default:
1104 Inst.addOperand(MCOperand::CreateReg(0));
1105 break;
1106 }
1107
1108 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1109 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1110
1111 bool writeback = (P == 0) || (W == 1);
1112 unsigned idx_mode = 0;
1113 if (P && writeback)
1114 idx_mode = ARMII::IndexModePre;
1115 else if (!P && writeback)
1116 idx_mode = ARMII::IndexModePost;
1117
1118 switch (Inst.getOpcode()) {
1119 case ARM::LDCL_POST:
1120 case ARM::STCL_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1121 case ARM::t2LDCL_POST:
1122 case ARM::t2STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1123 case ARM::LDC2L_POST:
1124 case ARM::STC2L_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1125 imm |= U << 8;
1126 case ARM::LDC_OPTION:
1127 case ARM::LDCL_OPTION:
1128 case ARM::LDC2_OPTION:
1129 case ARM::LDC2L_OPTION:
1130 case ARM::STC_OPTION:
1131 case ARM::STCL_OPTION:
1132 case ARM::STC2_OPTION:
1133 case ARM::STC2L_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1134 case ARM::t2LDC_OPTION:
1135 case ARM::t2LDCL_OPTION:
1136 case ARM::t2STC_OPTION:
1137 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1138 Inst.addOperand(MCOperand::CreateImm(imm));
1139 break;
1140 default:
1141 if (U)
1142 Inst.addOperand(MCOperand::CreateImm(
1143 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
1144 else
1145 Inst.addOperand(MCOperand::CreateImm(
1146 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
1147 break;
1148 }
1149
1150 switch (Inst.getOpcode()) {
1151 case ARM::LDC_OFFSET:
1152 case ARM::LDC_PRE:
1153 case ARM::LDC_POST:
1154 case ARM::LDC_OPTION:
1155 case ARM::LDCL_OFFSET:
1156 case ARM::LDCL_PRE:
1157 case ARM::LDCL_POST:
1158 case ARM::LDCL_OPTION:
1159 case ARM::STC_OFFSET:
1160 case ARM::STC_PRE:
1161 case ARM::STC_POST:
1162 case ARM::STC_OPTION:
1163 case ARM::STCL_OFFSET:
1164 case ARM::STCL_PRE:
1165 case ARM::STCL_POST:
1166 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1167 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1168 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1169 break;
1170 default:
1171 break;
1172 }
1173
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1174 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1175}
1176
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1177static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1178DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1179 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1180 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1181
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1182 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1183 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1184 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1185 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1186 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1187 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1188 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1189 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1190
1191 // On stores, the writeback operand precedes Rt.
1192 switch (Inst.getOpcode()) {
1193 case ARM::STR_POST_IMM:
1194 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1195 case ARM::STRB_POST_IMM:
1196 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1197 case ARM::STRT_POST_REG:
1198 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1199 case ARM::STRBT_POST_REG:
1200 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1201 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1202 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1203 break;
1204 default:
1205 break;
1206 }
1207
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1208 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1209 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1210
1211 // On loads, the writeback operand comes after Rt.
1212 switch (Inst.getOpcode()) {
1213 case ARM::LDR_POST_IMM:
1214 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1215 case ARM::LDRB_POST_IMM:
1216 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1217 case ARM::LDRBT_POST_REG:
1218 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1219 case ARM::LDRT_POST_REG:
1220 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1221 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1222 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1223 break;
1224 default:
1225 break;
1226 }
1227
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1229 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1230
1231 ARM_AM::AddrOpc Op = ARM_AM::add;
1232 if (!fieldFromInstruction32(Insn, 23, 1))
1233 Op = ARM_AM::sub;
1234
1235 bool writeback = (P == 0) || (W == 1);
1236 unsigned idx_mode = 0;
1237 if (P && writeback)
1238 idx_mode = ARMII::IndexModePre;
1239 else if (!P && writeback)
1240 idx_mode = ARMII::IndexModePost;
1241
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1242 if (writeback && (Rn == 15 || Rn == Rt))
1243 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1244
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1245 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1246 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1247 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1248 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1249 switch( fieldFromInstruction32(Insn, 5, 2)) {
1250 case 0:
1251 Opc = ARM_AM::lsl;
1252 break;
1253 case 1:
1254 Opc = ARM_AM::lsr;
1255 break;
1256 case 2:
1257 Opc = ARM_AM::asr;
1258 break;
1259 case 3:
1260 Opc = ARM_AM::ror;
1261 break;
1262 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1263 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1264 }
1265 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1266 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1267
1268 Inst.addOperand(MCOperand::CreateImm(imm));
1269 } else {
1270 Inst.addOperand(MCOperand::CreateReg(0));
1271 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1272 Inst.addOperand(MCOperand::CreateImm(tmp));
1273 }
1274
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1275 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1276 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1277
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1278 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1279}
1280
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1281static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1282 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1283 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1284
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1285 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1286 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1287 unsigned type = fieldFromInstruction32(Val, 5, 2);
1288 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1289 unsigned U = fieldFromInstruction32(Val, 12, 1);
1290
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1291 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1292 switch (type) {
1293 case 0:
1294 ShOp = ARM_AM::lsl;
1295 break;
1296 case 1:
1297 ShOp = ARM_AM::lsr;
1298 break;
1299 case 2:
1300 ShOp = ARM_AM::asr;
1301 break;
1302 case 3:
1303 ShOp = ARM_AM::ror;
1304 break;
1305 }
1306
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1308 return MCDisassembler::Fail;
1309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1310 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1311 unsigned shift;
1312 if (U)
1313 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1314 else
1315 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1316 Inst.addOperand(MCOperand::CreateImm(shift));
1317
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1318 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1319}
1320
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1321static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1322DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1323 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1324 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1325
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1326 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1327 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1328 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1329 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1330 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1331 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1332 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1333 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1334 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1335
1336 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1337
1338 // For {LD,ST}RD, Rt must be even, else undefined.
1339 switch (Inst.getOpcode()) {
1340 case ARM::STRD:
1341 case ARM::STRD_PRE:
1342 case ARM::STRD_POST:
1343 case ARM::LDRD:
1344 case ARM::LDRD_PRE:
1345 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1346 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1347 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1348 default:
1349 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1350 }
1351
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1352 if (writeback) { // Writeback
1353 if (P)
1354 U |= ARMII::IndexModePre << 9;
1355 else
1356 U |= ARMII::IndexModePost << 9;
1357
1358 // On stores, the writeback operand precedes Rt.
1359 switch (Inst.getOpcode()) {
1360 case ARM::STRD:
1361 case ARM::STRD_PRE:
1362 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1363 case ARM::STRH:
1364 case ARM::STRH_PRE:
1365 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1367 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1368 break;
1369 default:
1370 break;
1371 }
1372 }
1373
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1374 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1375 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1376 switch (Inst.getOpcode()) {
1377 case ARM::STRD:
1378 case ARM::STRD_PRE:
1379 case ARM::STRD_POST:
1380 case ARM::LDRD:
1381 case ARM::LDRD_PRE:
1382 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1383 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1384 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1385 break;
1386 default:
1387 break;
1388 }
1389
1390 if (writeback) {
1391 // On loads, the writeback operand comes after Rt.
1392 switch (Inst.getOpcode()) {
1393 case ARM::LDRD:
1394 case ARM::LDRD_PRE:
1395 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1396 case ARM::LDRH:
1397 case ARM::LDRH_PRE:
1398 case ARM::LDRH_POST:
1399 case ARM::LDRSH:
1400 case ARM::LDRSH_PRE:
1401 case ARM::LDRSH_POST:
1402 case ARM::LDRSB:
1403 case ARM::LDRSB_PRE:
1404 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1405 case ARM::LDRHTr:
1406 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1407 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1408 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1409 break;
1410 default:
1411 break;
1412 }
1413 }
1414
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1415 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1416 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1417
1418 if (type) {
1419 Inst.addOperand(MCOperand::CreateReg(0));
1420 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1421 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1422 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1423 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1424 Inst.addOperand(MCOperand::CreateImm(U));
1425 }
1426
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1427 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1428 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1429
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1430 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1431}
1432
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1433static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1434 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1435 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1436
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1437 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1438 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1439
1440 switch (mode) {
1441 case 0:
1442 mode = ARM_AM::da;
1443 break;
1444 case 1:
1445 mode = ARM_AM::ia;
1446 break;
1447 case 2:
1448 mode = ARM_AM::db;
1449 break;
1450 case 3:
1451 mode = ARM_AM::ib;
1452 break;
1453 }
1454
1455 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1456 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1457 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1458
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1459 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1460}
1461
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1462static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1463 unsigned Insn,
1464 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1465 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1466
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1467 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1468 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1469 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1470
1471 if (pred == 0xF) {
1472 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1473 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1474 Inst.setOpcode(ARM::RFEDA);
1475 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1476 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1477 Inst.setOpcode(ARM::RFEDA_UPD);
1478 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1479 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1480 Inst.setOpcode(ARM::RFEDB);
1481 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1482 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1483 Inst.setOpcode(ARM::RFEDB_UPD);
1484 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1485 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1486 Inst.setOpcode(ARM::RFEIA);
1487 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1488 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1489 Inst.setOpcode(ARM::RFEIA_UPD);
1490 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1491 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1492 Inst.setOpcode(ARM::RFEIB);
1493 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1494 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1495 Inst.setOpcode(ARM::RFEIB_UPD);
1496 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1497 case ARM::STMDA:
1498 Inst.setOpcode(ARM::SRSDA);
1499 break;
1500 case ARM::STMDA_UPD:
1501 Inst.setOpcode(ARM::SRSDA_UPD);
1502 break;
1503 case ARM::STMDB:
1504 Inst.setOpcode(ARM::SRSDB);
1505 break;
1506 case ARM::STMDB_UPD:
1507 Inst.setOpcode(ARM::SRSDB_UPD);
1508 break;
1509 case ARM::STMIA:
1510 Inst.setOpcode(ARM::SRSIA);
1511 break;
1512 case ARM::STMIA_UPD:
1513 Inst.setOpcode(ARM::SRSIA_UPD);
1514 break;
1515 case ARM::STMIB:
1516 Inst.setOpcode(ARM::SRSIB);
1517 break;
1518 case ARM::STMIB_UPD:
1519 Inst.setOpcode(ARM::SRSIB_UPD);
1520 break;
1521 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1522 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1523 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1524
1525 // For stores (which become SRS's, the only operand is the mode.
1526 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1527 Inst.addOperand(
1528 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1529 return S;
1530 }
1531
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1532 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1533 }
1534
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1535 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1536 return MCDisassembler::Fail;
1537 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1538 return MCDisassembler::Fail; // Tied
1539 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1540 return MCDisassembler::Fail;
1541 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1542 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1543
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1544 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1545}
1546
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1547static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1548 uint64_t Address, const void *Decoder) {
1549 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1550 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1551 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1552 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1553
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1554 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1555
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1556 // imod == '01' --> UNPREDICTABLE
1557 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1558 // return failure here. The '01' imod value is unprintable, so there's
1559 // nothing useful we could do even if we returned UNPREDICTABLE.
1560
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1561 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1562
1563 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1564 Inst.setOpcode(ARM::CPS3p);
1565 Inst.addOperand(MCOperand::CreateImm(imod));
1566 Inst.addOperand(MCOperand::CreateImm(iflags));
1567 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1568 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1569 Inst.setOpcode(ARM::CPS2p);
1570 Inst.addOperand(MCOperand::CreateImm(imod));
1571 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1572 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1573 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1574 Inst.setOpcode(ARM::CPS1p);
1575 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1576 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1577 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1578 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1579 Inst.setOpcode(ARM::CPS1p);
1580 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1581 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1582 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1583
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1584 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1585}
1586
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1587static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1588 uint64_t Address, const void *Decoder) {
1589 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1590 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1591 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1592 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1593
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1594 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1595
1596 // imod == '01' --> UNPREDICTABLE
1597 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1598 // return failure here. The '01' imod value is unprintable, so there's
1599 // nothing useful we could do even if we returned UNPREDICTABLE.
1600
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1601 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1602
1603 if (imod && M) {
1604 Inst.setOpcode(ARM::t2CPS3p);
1605 Inst.addOperand(MCOperand::CreateImm(imod));
1606 Inst.addOperand(MCOperand::CreateImm(iflags));
1607 Inst.addOperand(MCOperand::CreateImm(mode));
1608 } else if (imod && !M) {
1609 Inst.setOpcode(ARM::t2CPS2p);
1610 Inst.addOperand(MCOperand::CreateImm(imod));
1611 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1612 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1613 } else if (!imod && M) {
1614 Inst.setOpcode(ARM::t2CPS1p);
1615 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1616 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1617 } else {
1618 // imod == '00' && M == '0' --> UNPREDICTABLE
1619 Inst.setOpcode(ARM::t2CPS1p);
1620 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1621 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1622 }
1623
1624 return S;
1625}
1626
1627
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1628static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1629 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1630 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1631
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1632 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1633 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1634 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1635 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1636 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1637
1638 if (pred == 0xF)
1639 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1640
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1641 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1642 return MCDisassembler::Fail;
1643 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1644 return MCDisassembler::Fail;
1645 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1646 return MCDisassembler::Fail;
1647 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1648 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1649
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1650 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1651 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1652
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1653 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1654}
1655
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1656static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1657 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1658 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1659
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1660 unsigned add = fieldFromInstruction32(Val, 12, 1);
1661 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1662 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1663
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1664 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1665 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1666
1667 if (!add) imm *= -1;
1668 if (imm == 0 && !add) imm = INT32_MIN;
1669 Inst.addOperand(MCOperand::CreateImm(imm));
1670
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1671 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1672}
1673
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1674static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1675 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1676 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1677
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1678 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1679 unsigned U = fieldFromInstruction32(Val, 8, 1);
1680 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1681
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1682 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1683 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1684
1685 if (U)
1686 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1687 else
1688 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1689
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1690 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1691}
1692
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1693static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1694 uint64_t Address, const void *Decoder) {
1695 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1696}
1697
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1698static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1699DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1700 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1701 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1702
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1703 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1704 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1705
1706 if (pred == 0xF) {
1707 Inst.setOpcode(ARM::BLXi);
1708 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1709 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1710 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1711 }
1712
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1713 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1714 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1715 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1716
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1717 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1718}
1719
1720
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1721static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1722 uint64_t Address, const void *Decoder) {
1723 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1724 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1725}
1726
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1727static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1728 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1729 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1730
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1731 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1732 unsigned align = fieldFromInstruction32(Val, 4, 2);
1733
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1734 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1735 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1736 if (!align)
1737 Inst.addOperand(MCOperand::CreateImm(0));
1738 else
1739 Inst.addOperand(MCOperand::CreateImm(4 << align));
1740
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1741 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1742}
1743
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1744static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1745 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1746 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1747
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1748 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1749 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1750 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1751 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1752 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1753 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1754
1755 // First output register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1756 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1757 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1758
1759 // Second output register
1760 switch (Inst.getOpcode()) {
1761 case ARM::VLD1q8:
1762 case ARM::VLD1q16:
1763 case ARM::VLD1q32:
1764 case ARM::VLD1q64:
1765 case ARM::VLD1q8_UPD:
1766 case ARM::VLD1q16_UPD:
1767 case ARM::VLD1q32_UPD:
1768 case ARM::VLD1q64_UPD:
1769 case ARM::VLD1d8T:
1770 case ARM::VLD1d16T:
1771 case ARM::VLD1d32T:
1772 case ARM::VLD1d64T:
1773 case ARM::VLD1d8T_UPD:
1774 case ARM::VLD1d16T_UPD:
1775 case ARM::VLD1d32T_UPD:
1776 case ARM::VLD1d64T_UPD:
1777 case ARM::VLD1d8Q:
1778 case ARM::VLD1d16Q:
1779 case ARM::VLD1d32Q:
1780 case ARM::VLD1d64Q:
1781 case ARM::VLD1d8Q_UPD:
1782 case ARM::VLD1d16Q_UPD:
1783 case ARM::VLD1d32Q_UPD:
1784 case ARM::VLD1d64Q_UPD:
1785 case ARM::VLD2d8:
1786 case ARM::VLD2d16:
1787 case ARM::VLD2d32:
1788 case ARM::VLD2d8_UPD:
1789 case ARM::VLD2d16_UPD:
1790 case ARM::VLD2d32_UPD:
1791 case ARM::VLD2q8:
1792 case ARM::VLD2q16:
1793 case ARM::VLD2q32:
1794 case ARM::VLD2q8_UPD:
1795 case ARM::VLD2q16_UPD:
1796 case ARM::VLD2q32_UPD:
1797 case ARM::VLD3d8:
1798 case ARM::VLD3d16:
1799 case ARM::VLD3d32:
1800 case ARM::VLD3d8_UPD:
1801 case ARM::VLD3d16_UPD:
1802 case ARM::VLD3d32_UPD:
1803 case ARM::VLD4d8:
1804 case ARM::VLD4d16:
1805 case ARM::VLD4d32:
1806 case ARM::VLD4d8_UPD:
1807 case ARM::VLD4d16_UPD:
1808 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1809 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
1810 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1811 break;
1812 case ARM::VLD2b8:
1813 case ARM::VLD2b16:
1814 case ARM::VLD2b32:
1815 case ARM::VLD2b8_UPD:
1816 case ARM::VLD2b16_UPD:
1817 case ARM::VLD2b32_UPD:
1818 case ARM::VLD3q8:
1819 case ARM::VLD3q16:
1820 case ARM::VLD3q32:
1821 case ARM::VLD3q8_UPD:
1822 case ARM::VLD3q16_UPD:
1823 case ARM::VLD3q32_UPD:
1824 case ARM::VLD4q8:
1825 case ARM::VLD4q16:
1826 case ARM::VLD4q32:
1827 case ARM::VLD4q8_UPD:
1828 case ARM::VLD4q16_UPD:
1829 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1830 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1831 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1832 default:
1833 break;
1834 }
1835
1836 // Third output register
1837 switch(Inst.getOpcode()) {
1838 case ARM::VLD1d8T:
1839 case ARM::VLD1d16T:
1840 case ARM::VLD1d32T:
1841 case ARM::VLD1d64T:
1842 case ARM::VLD1d8T_UPD:
1843 case ARM::VLD1d16T_UPD:
1844 case ARM::VLD1d32T_UPD:
1845 case ARM::VLD1d64T_UPD:
1846 case ARM::VLD1d8Q:
1847 case ARM::VLD1d16Q:
1848 case ARM::VLD1d32Q:
1849 case ARM::VLD1d64Q:
1850 case ARM::VLD1d8Q_UPD:
1851 case ARM::VLD1d16Q_UPD:
1852 case ARM::VLD1d32Q_UPD:
1853 case ARM::VLD1d64Q_UPD:
1854 case ARM::VLD2q8:
1855 case ARM::VLD2q16:
1856 case ARM::VLD2q32:
1857 case ARM::VLD2q8_UPD:
1858 case ARM::VLD2q16_UPD:
1859 case ARM::VLD2q32_UPD:
1860 case ARM::VLD3d8:
1861 case ARM::VLD3d16:
1862 case ARM::VLD3d32:
1863 case ARM::VLD3d8_UPD:
1864 case ARM::VLD3d16_UPD:
1865 case ARM::VLD3d32_UPD:
1866 case ARM::VLD4d8:
1867 case ARM::VLD4d16:
1868 case ARM::VLD4d32:
1869 case ARM::VLD4d8_UPD:
1870 case ARM::VLD4d16_UPD:
1871 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1872 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1873 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1874 break;
1875 case ARM::VLD3q8:
1876 case ARM::VLD3q16:
1877 case ARM::VLD3q32:
1878 case ARM::VLD3q8_UPD:
1879 case ARM::VLD3q16_UPD:
1880 case ARM::VLD3q32_UPD:
1881 case ARM::VLD4q8:
1882 case ARM::VLD4q16:
1883 case ARM::VLD4q32:
1884 case ARM::VLD4q8_UPD:
1885 case ARM::VLD4q16_UPD:
1886 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1887 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
1888 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1889 break;
1890 default:
1891 break;
1892 }
1893
1894 // Fourth output register
1895 switch (Inst.getOpcode()) {
1896 case ARM::VLD1d8Q:
1897 case ARM::VLD1d16Q:
1898 case ARM::VLD1d32Q:
1899 case ARM::VLD1d64Q:
1900 case ARM::VLD1d8Q_UPD:
1901 case ARM::VLD1d16Q_UPD:
1902 case ARM::VLD1d32Q_UPD:
1903 case ARM::VLD1d64Q_UPD:
1904 case ARM::VLD2q8:
1905 case ARM::VLD2q16:
1906 case ARM::VLD2q32:
1907 case ARM::VLD2q8_UPD:
1908 case ARM::VLD2q16_UPD:
1909 case ARM::VLD2q32_UPD:
1910 case ARM::VLD4d8:
1911 case ARM::VLD4d16:
1912 case ARM::VLD4d32:
1913 case ARM::VLD4d8_UPD:
1914 case ARM::VLD4d16_UPD:
1915 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1916 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
1917 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1918 break;
1919 case ARM::VLD4q8:
1920 case ARM::VLD4q16:
1921 case ARM::VLD4q32:
1922 case ARM::VLD4q8_UPD:
1923 case ARM::VLD4q16_UPD:
1924 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1925 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
1926 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1927 break;
1928 default:
1929 break;
1930 }
1931
1932 // Writeback operand
1933 switch (Inst.getOpcode()) {
1934 case ARM::VLD1d8_UPD:
1935 case ARM::VLD1d16_UPD:
1936 case ARM::VLD1d32_UPD:
1937 case ARM::VLD1d64_UPD:
1938 case ARM::VLD1q8_UPD:
1939 case ARM::VLD1q16_UPD:
1940 case ARM::VLD1q32_UPD:
1941 case ARM::VLD1q64_UPD:
1942 case ARM::VLD1d8T_UPD:
1943 case ARM::VLD1d16T_UPD:
1944 case ARM::VLD1d32T_UPD:
1945 case ARM::VLD1d64T_UPD:
1946 case ARM::VLD1d8Q_UPD:
1947 case ARM::VLD1d16Q_UPD:
1948 case ARM::VLD1d32Q_UPD:
1949 case ARM::VLD1d64Q_UPD:
1950 case ARM::VLD2d8_UPD:
1951 case ARM::VLD2d16_UPD:
1952 case ARM::VLD2d32_UPD:
1953 case ARM::VLD2q8_UPD:
1954 case ARM::VLD2q16_UPD:
1955 case ARM::VLD2q32_UPD:
1956 case ARM::VLD2b8_UPD:
1957 case ARM::VLD2b16_UPD:
1958 case ARM::VLD2b32_UPD:
1959 case ARM::VLD3d8_UPD:
1960 case ARM::VLD3d16_UPD:
1961 case ARM::VLD3d32_UPD:
1962 case ARM::VLD3q8_UPD:
1963 case ARM::VLD3q16_UPD:
1964 case ARM::VLD3q32_UPD:
1965 case ARM::VLD4d8_UPD:
1966 case ARM::VLD4d16_UPD:
1967 case ARM::VLD4d32_UPD:
1968 case ARM::VLD4q8_UPD:
1969 case ARM::VLD4q16_UPD:
1970 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1971 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
1972 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1973 break;
1974 default:
1975 break;
1976 }
1977
1978 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1979 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
1980 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1981
1982 // AddrMode6 Offset (register)
1983 if (Rm == 0xD)
1984 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1985 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1986 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1987 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1988 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1989
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1990 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1991}
1992
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1993static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1994 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1995 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1996
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1997 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1998 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1999 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2000 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2001 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2002 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2003
2004 // Writeback Operand
2005 switch (Inst.getOpcode()) {
2006 case ARM::VST1d8_UPD:
2007 case ARM::VST1d16_UPD:
2008 case ARM::VST1d32_UPD:
2009 case ARM::VST1d64_UPD:
2010 case ARM::VST1q8_UPD:
2011 case ARM::VST1q16_UPD:
2012 case ARM::VST1q32_UPD:
2013 case ARM::VST1q64_UPD:
2014 case ARM::VST1d8T_UPD:
2015 case ARM::VST1d16T_UPD:
2016 case ARM::VST1d32T_UPD:
2017 case ARM::VST1d64T_UPD:
2018 case ARM::VST1d8Q_UPD:
2019 case ARM::VST1d16Q_UPD:
2020 case ARM::VST1d32Q_UPD:
2021 case ARM::VST1d64Q_UPD:
2022 case ARM::VST2d8_UPD:
2023 case ARM::VST2d16_UPD:
2024 case ARM::VST2d32_UPD:
2025 case ARM::VST2q8_UPD:
2026 case ARM::VST2q16_UPD:
2027 case ARM::VST2q32_UPD:
2028 case ARM::VST2b8_UPD:
2029 case ARM::VST2b16_UPD:
2030 case ARM::VST2b32_UPD:
2031 case ARM::VST3d8_UPD:
2032 case ARM::VST3d16_UPD:
2033 case ARM::VST3d32_UPD:
2034 case ARM::VST3q8_UPD:
2035 case ARM::VST3q16_UPD:
2036 case ARM::VST3q32_UPD:
2037 case ARM::VST4d8_UPD:
2038 case ARM::VST4d16_UPD:
2039 case ARM::VST4d32_UPD:
2040 case ARM::VST4q8_UPD:
2041 case ARM::VST4q16_UPD:
2042 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2043 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2044 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2045 break;
2046 default:
2047 break;
2048 }
2049
2050 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2051 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2052 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2053
2054 // AddrMode6 Offset (register)
2055 if (Rm == 0xD)
2056 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2057 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2058 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2059 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2060 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2061
2062 // First input register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2063 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2064 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2065
2066 // Second input register
2067 switch (Inst.getOpcode()) {
2068 case ARM::VST1q8:
2069 case ARM::VST1q16:
2070 case ARM::VST1q32:
2071 case ARM::VST1q64:
2072 case ARM::VST1q8_UPD:
2073 case ARM::VST1q16_UPD:
2074 case ARM::VST1q32_UPD:
2075 case ARM::VST1q64_UPD:
2076 case ARM::VST1d8T:
2077 case ARM::VST1d16T:
2078 case ARM::VST1d32T:
2079 case ARM::VST1d64T:
2080 case ARM::VST1d8T_UPD:
2081 case ARM::VST1d16T_UPD:
2082 case ARM::VST1d32T_UPD:
2083 case ARM::VST1d64T_UPD:
2084 case ARM::VST1d8Q:
2085 case ARM::VST1d16Q:
2086 case ARM::VST1d32Q:
2087 case ARM::VST1d64Q:
2088 case ARM::VST1d8Q_UPD:
2089 case ARM::VST1d16Q_UPD:
2090 case ARM::VST1d32Q_UPD:
2091 case ARM::VST1d64Q_UPD:
2092 case ARM::VST2d8:
2093 case ARM::VST2d16:
2094 case ARM::VST2d32:
2095 case ARM::VST2d8_UPD:
2096 case ARM::VST2d16_UPD:
2097 case ARM::VST2d32_UPD:
2098 case ARM::VST2q8:
2099 case ARM::VST2q16:
2100 case ARM::VST2q32:
2101 case ARM::VST2q8_UPD:
2102 case ARM::VST2q16_UPD:
2103 case ARM::VST2q32_UPD:
2104 case ARM::VST3d8:
2105 case ARM::VST3d16:
2106 case ARM::VST3d32:
2107 case ARM::VST3d8_UPD:
2108 case ARM::VST3d16_UPD:
2109 case ARM::VST3d32_UPD:
2110 case ARM::VST4d8:
2111 case ARM::VST4d16:
2112 case ARM::VST4d32:
2113 case ARM::VST4d8_UPD:
2114 case ARM::VST4d16_UPD:
2115 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2116 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2117 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2118 break;
2119 case ARM::VST2b8:
2120 case ARM::VST2b16:
2121 case ARM::VST2b32:
2122 case ARM::VST2b8_UPD:
2123 case ARM::VST2b16_UPD:
2124 case ARM::VST2b32_UPD:
2125 case ARM::VST3q8:
2126 case ARM::VST3q16:
2127 case ARM::VST3q32:
2128 case ARM::VST3q8_UPD:
2129 case ARM::VST3q16_UPD:
2130 case ARM::VST3q32_UPD:
2131 case ARM::VST4q8:
2132 case ARM::VST4q16:
2133 case ARM::VST4q32:
2134 case ARM::VST4q8_UPD:
2135 case ARM::VST4q16_UPD:
2136 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2137 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2138 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2139 break;
2140 default:
2141 break;
2142 }
2143
2144 // Third input register
2145 switch (Inst.getOpcode()) {
2146 case ARM::VST1d8T:
2147 case ARM::VST1d16T:
2148 case ARM::VST1d32T:
2149 case ARM::VST1d64T:
2150 case ARM::VST1d8T_UPD:
2151 case ARM::VST1d16T_UPD:
2152 case ARM::VST1d32T_UPD:
2153 case ARM::VST1d64T_UPD:
2154 case ARM::VST1d8Q:
2155 case ARM::VST1d16Q:
2156 case ARM::VST1d32Q:
2157 case ARM::VST1d64Q:
2158 case ARM::VST1d8Q_UPD:
2159 case ARM::VST1d16Q_UPD:
2160 case ARM::VST1d32Q_UPD:
2161 case ARM::VST1d64Q_UPD:
2162 case ARM::VST2q8:
2163 case ARM::VST2q16:
2164 case ARM::VST2q32:
2165 case ARM::VST2q8_UPD:
2166 case ARM::VST2q16_UPD:
2167 case ARM::VST2q32_UPD:
2168 case ARM::VST3d8:
2169 case ARM::VST3d16:
2170 case ARM::VST3d32:
2171 case ARM::VST3d8_UPD:
2172 case ARM::VST3d16_UPD:
2173 case ARM::VST3d32_UPD:
2174 case ARM::VST4d8:
2175 case ARM::VST4d16:
2176 case ARM::VST4d32:
2177 case ARM::VST4d8_UPD:
2178 case ARM::VST4d16_UPD:
2179 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2180 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2181 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2182 break;
2183 case ARM::VST3q8:
2184 case ARM::VST3q16:
2185 case ARM::VST3q32:
2186 case ARM::VST3q8_UPD:
2187 case ARM::VST3q16_UPD:
2188 case ARM::VST3q32_UPD:
2189 case ARM::VST4q8:
2190 case ARM::VST4q16:
2191 case ARM::VST4q32:
2192 case ARM::VST4q8_UPD:
2193 case ARM::VST4q16_UPD:
2194 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2195 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2196 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2197 break;
2198 default:
2199 break;
2200 }
2201
2202 // Fourth input register
2203 switch (Inst.getOpcode()) {
2204 case ARM::VST1d8Q:
2205 case ARM::VST1d16Q:
2206 case ARM::VST1d32Q:
2207 case ARM::VST1d64Q:
2208 case ARM::VST1d8Q_UPD:
2209 case ARM::VST1d16Q_UPD:
2210 case ARM::VST1d32Q_UPD:
2211 case ARM::VST1d64Q_UPD:
2212 case ARM::VST2q8:
2213 case ARM::VST2q16:
2214 case ARM::VST2q32:
2215 case ARM::VST2q8_UPD:
2216 case ARM::VST2q16_UPD:
2217 case ARM::VST2q32_UPD:
2218 case ARM::VST4d8:
2219 case ARM::VST4d16:
2220 case ARM::VST4d32:
2221 case ARM::VST4d8_UPD:
2222 case ARM::VST4d16_UPD:
2223 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2224 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2225 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2226 break;
2227 case ARM::VST4q8:
2228 case ARM::VST4q16:
2229 case ARM::VST4q32:
2230 case ARM::VST4q8_UPD:
2231 case ARM::VST4q16_UPD:
2232 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2233 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2234 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2235 break;
2236 default:
2237 break;
2238 }
2239
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2240 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2241}
2242
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2243static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2244 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2245 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2246
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2247 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2248 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2249 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2250 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2251 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2252 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2253 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2254
2255 align *= (1 << size);
2256
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2257 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2258 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2259 if (regs == 2) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2260 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2261 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2262 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2263 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2264 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2265 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2266 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2267
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2268 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2269 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2270 Inst.addOperand(MCOperand::CreateImm(align));
2271
2272 if (Rm == 0xD)
2273 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2274 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2275 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2276 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2277 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2278
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2279 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2280}
2281
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2282static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2283 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2284 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2285
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2286 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2287 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2288 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2289 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2290 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2291 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2292 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2293 align *= 2*size;
2294
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2295 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2296 return MCDisassembler::Fail;
2297 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2298 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2299 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2300 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2301 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2302 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2303
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2304 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2305 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2306 Inst.addOperand(MCOperand::CreateImm(align));
2307
2308 if (Rm == 0xD)
2309 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2310 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2311 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2312 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2313 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2314
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2315 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2316}
2317
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2318static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2319 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2320 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2321
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2322 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2323 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2324 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2325 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2326 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2327
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2328 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2329 return MCDisassembler::Fail;
2330 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2331 return MCDisassembler::Fail;
2332 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2333 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2334 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2335 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2336 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2337 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2338
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2339 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2340 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2341 Inst.addOperand(MCOperand::CreateImm(0));
2342
2343 if (Rm == 0xD)
2344 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2345 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2346 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2347 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2348 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2349
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2350 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2351}
2352
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2353static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2354 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2355 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2356
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2357 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2358 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2359 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2360 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2361 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2362 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2363 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2364
2365 if (size == 0x3) {
2366 size = 4;
2367 align = 16;
2368 } else {
2369 if (size == 2) {
2370 size = 1 << size;
2371 align *= 8;
2372 } else {
2373 size = 1 << size;
2374 align *= 4*size;
2375 }
2376 }
2377
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2378 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2379 return MCDisassembler::Fail;
2380 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2381 return MCDisassembler::Fail;
2382 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2383 return MCDisassembler::Fail;
2384 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2385 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2386 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2387 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2388 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2389 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2390
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2391 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2392 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2393 Inst.addOperand(MCOperand::CreateImm(align));
2394
2395 if (Rm == 0xD)
2396 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2397 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2398 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2399 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2400 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2401
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2402 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2403}
2404
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2405static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2406DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2407 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2408 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2409
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2410 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2411 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2412 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2413 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2414 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2415 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2416 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2417 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2418
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2419 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2420 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2421 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2422 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2423 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2424 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2425 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2426
2427 Inst.addOperand(MCOperand::CreateImm(imm));
2428
2429 switch (Inst.getOpcode()) {
2430 case ARM::VORRiv4i16:
2431 case ARM::VORRiv2i32:
2432 case ARM::VBICiv4i16:
2433 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2434 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2435 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2436 break;
2437 case ARM::VORRiv8i16:
2438 case ARM::VORRiv4i32:
2439 case ARM::VBICiv8i16:
2440 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2441 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2442 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2443 break;
2444 default:
2445 break;
2446 }
2447
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2448 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2449}
2450
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2451static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2452 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2453 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2454
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2455 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2456 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2457 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2458 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2459 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2460
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2461 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2462 return MCDisassembler::Fail;
2463 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2464 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2465 Inst.addOperand(MCOperand::CreateImm(8 << size));
2466
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2467 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2468}
2469
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2470static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2471 uint64_t Address, const void *Decoder) {
2472 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2473 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2474}
2475
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2476static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2477 uint64_t Address, const void *Decoder) {
2478 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2479 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2480}
2481
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2482static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2483 uint64_t Address, const void *Decoder) {
2484 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2485 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2486}
2487
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2488static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2489 uint64_t Address, const void *Decoder) {
2490 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2491 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2492}
2493
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2494static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2495 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2496 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2497
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2498 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2499 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2500 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2501 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2502 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2503 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2504 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2505 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2506
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2507 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2508 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2509 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2510 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2511 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2512 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2513
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2514 for (unsigned i = 0; i < length; ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2515 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2516 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2517 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2518
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2519 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2520 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2521
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2522 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2523}
2524
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2525static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2526 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2527 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2528
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2529 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2530 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2531
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2532 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2533 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2534
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2535 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2536 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2537 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2538 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2539 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2540 case ARM::tADDrSPi:
2541 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2542 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2543 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2544
2545 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2546 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2547}
2548
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2549static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2550 uint64_t Address, const void *Decoder) {
2551 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2552 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2553}
2554
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2555static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2556 uint64_t Address, const void *Decoder) {
2557 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2558 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2559}
2560
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2561static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2562 uint64_t Address, const void *Decoder) {
2563 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2564 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2565}
2566
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2567static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2568 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2569 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2570
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2571 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2572 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2573
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2574 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2575 return MCDisassembler::Fail;
2576 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2577 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2578
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2579 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2580}
2581
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2582static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2583 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2584 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2585
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2586 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2587 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2588
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2589 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2590 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2591 Inst.addOperand(MCOperand::CreateImm(imm));
2592
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2593 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2594}
2595
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2596static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2597 uint64_t Address, const void *Decoder) {
2598 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2599
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2600 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2601}
2602
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2603static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2604 uint64_t Address, const void *Decoder) {
2605 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2606 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2607
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2608 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2609}
2610
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2611static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2612 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2613 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2614
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2615 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2616 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2617 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2618
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2619 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2620 return MCDisassembler::Fail;
2621 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2622 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2623 Inst.addOperand(MCOperand::CreateImm(imm));
2624
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2625 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2626}
2627
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2628static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2629 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2630 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2631
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2632 switch (Inst.getOpcode()) {
2633 case ARM::t2PLDs:
2634 case ARM::t2PLDWs:
2635 case ARM::t2PLIs:
2636 break;
2637 default: {
2638 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Anderson31d485e2011-09-23 21:07:25 +0000[diff] [blame]2639 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2640 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2641 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2642 }
2643
2644 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2645 if (Rn == 0xF) {
2646 switch (Inst.getOpcode()) {
2647 case ARM::t2LDRBs:
2648 Inst.setOpcode(ARM::t2LDRBpci);
2649 break;
2650 case ARM::t2LDRHs:
2651 Inst.setOpcode(ARM::t2LDRHpci);
2652 break;
2653 case ARM::t2LDRSHs:
2654 Inst.setOpcode(ARM::t2LDRSHpci);
2655 break;
2656 case ARM::t2LDRSBs:
2657 Inst.setOpcode(ARM::t2LDRSBpci);
2658 break;
2659 case ARM::t2PLDs:
2660 Inst.setOpcode(ARM::t2PLDi12);
2661 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2662 break;
2663 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2664 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2665 }
2666
2667 int imm = fieldFromInstruction32(Insn, 0, 12);
2668 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2669 Inst.addOperand(MCOperand::CreateImm(imm));
2670
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2671 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2672 }
2673
2674 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2675 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2676 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2677 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2678 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2679
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2680 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2681}
2682
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2683static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2684 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2685 int imm = Val & 0xFF;
2686 if (!(Val & 0x100)) imm *= -1;
2687 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2688
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2689 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2690}
2691
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2692static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2693 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2694 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2695
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2696 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2697 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2698
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2699 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2700 return MCDisassembler::Fail;
2701 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2702 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2703
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2704 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2705}
2706
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]2707static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2708 uint64_t Address, const void *Decoder) {
2709 DecodeStatus S = MCDisassembler::Success;
2710
2711 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2712 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2713
2714 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2715 return MCDisassembler::Fail;
2716
2717 Inst.addOperand(MCOperand::CreateImm(imm));
2718
2719 return S;
2720}
2721
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2722static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2723 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2724 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]2725 if (Val == 0)
2726 imm = INT32_MIN;
2727 else if (!(Val & 0x100))
2728 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2729 Inst.addOperand(MCOperand::CreateImm(imm));
2730
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2731 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2732}
2733
2734
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2735static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2736 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2737 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2738
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2739 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2740 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2741
2742 // Some instructions always use an additive offset.
2743 switch (Inst.getOpcode()) {
2744 case ARM::t2LDRT:
2745 case ARM::t2LDRBT:
2746 case ARM::t2LDRHT:
2747 case ARM::t2LDRSBT:
2748 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]2749 case ARM::t2STRT:
2750 case ARM::t2STRBT:
2751 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2752 imm |= 0x100;
2753 break;
2754 default:
2755 break;
2756 }
2757
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2758 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2759 return MCDisassembler::Fail;
2760 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2761 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2762
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2763 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2764}
2765
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2766static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
2767 uint64_t Address, const void *Decoder) {
2768 DecodeStatus S = MCDisassembler::Success;
2769
2770 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2771 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2772 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
2773 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
2774 addr |= Rn << 9;
2775 unsigned load = fieldFromInstruction32(Insn, 20, 1);
2776
2777 if (!load) {
2778 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2779 return MCDisassembler::Fail;
2780 }
2781
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]2782 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2783 return MCDisassembler::Fail;
2784
2785 if (load) {
2786 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2787 return MCDisassembler::Fail;
2788 }
2789
2790 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
2791 return MCDisassembler::Fail;
2792
2793 return S;
2794}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2795
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2796static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2797 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2798 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2799
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2800 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2801 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2802
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2803 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2804 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2805 Inst.addOperand(MCOperand::CreateImm(imm));
2806
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2807 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2808}
2809
2810
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2811static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2812 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2813 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2814
2815 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2816 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2817 Inst.addOperand(MCOperand::CreateImm(imm));
2818
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2819 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2820}
2821
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2822static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2823 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2824 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2825
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2826 if (Inst.getOpcode() == ARM::tADDrSP) {
2827 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2828 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2829
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2830 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2831 return MCDisassembler::Fail;
2832 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2833 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]2834 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2835 } else if (Inst.getOpcode() == ARM::tADDspr) {
2836 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2837
2838 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2839 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2840 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2841 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2842 }
2843
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2844 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2845}
2846
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2847static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2848 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2849 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2850 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2851
2852 Inst.addOperand(MCOperand::CreateImm(imod));
2853 Inst.addOperand(MCOperand::CreateImm(flags));
2854
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2855 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2856}
2857
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2858static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2859 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2860 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2861 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2862 unsigned add = fieldFromInstruction32(Insn, 4, 1);
2863
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2864 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2865 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2866 Inst.addOperand(MCOperand::CreateImm(add));
2867
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2868 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2869}
2870
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2871static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2872 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2873 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2874 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2875}
2876
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2877static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2878 uint64_t Address, const void *Decoder) {
2879 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2880 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2881
2882 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2883 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2884}
2885
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2886static DecodeStatus
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]2887DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn,
2888 uint64_t Address, const void *Decoder) {
2889 DecodeStatus S = MCDisassembler::Success;
2890
2891 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2892 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2893
2894 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
2895 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2896 return MCDisassembler::Fail;
2897 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2898 return MCDisassembler::Fail;
2899 return S;
2900}
2901
2902static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2903DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2904 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2905 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2906
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2907 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2908 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2909 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2910 switch (opc) {
2911 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2912 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2913 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2914 Inst.setOpcode(ARM::t2DSB);
2915 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2916 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2917 Inst.setOpcode(ARM::t2DMB);
2918 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2919 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2920 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]2921 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2922 }
2923
2924 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2925 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2926 }
2927
2928 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2929 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2930 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2931 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2932 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2933
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2934 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
2935 return MCDisassembler::Fail;
2936 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2937 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2938
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2939 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2940}
2941
2942// Decode a shifted immediate operand. These basically consist
2943// of an 8-bit value, and a 4-bit directive that specifies either
2944// a splat operation or a rotation.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2945static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2946 uint64_t Address, const void *Decoder) {
2947 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2948 if (ctrl == 0) {
2949 unsigned byte = fieldFromInstruction32(Val, 8, 2);
2950 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2951 switch (byte) {
2952 case 0:
2953 Inst.addOperand(MCOperand::CreateImm(imm));
2954 break;
2955 case 1:
2956 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2957 break;
2958 case 2:
2959 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2960 break;
2961 case 3:
2962 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2963 (imm << 8) | imm));
2964 break;
2965 }
2966 } else {
2967 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2968 unsigned rot = fieldFromInstruction32(Val, 7, 5);
2969 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2970 Inst.addOperand(MCOperand::CreateImm(imm));
2971 }
2972
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2973 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2974}
2975
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2976static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2977DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
2978 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2979 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2980 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2981}
2982
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2983static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2984 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2985 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2986 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2987}
2988
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2989static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2990 uint64_t Address, const void *Decoder) {
2991 switch (Val) {
2992 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2993 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2994 case 0xF: // SY
2995 case 0xE: // ST
2996 case 0xB: // ISH
2997 case 0xA: // ISHST
2998 case 0x7: // NSH
2999 case 0x6: // NSHST
3000 case 0x3: // OSH
3001 case 0x2: // OSHST
3002 break;
3003 }
3004
3005 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3006 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3007}
3008
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3009static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3010 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3011 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3012 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3013 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3014}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3015
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3016static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3017 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3018 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3019
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3020 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3021 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3022 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3023
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3024 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3025
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3026 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3027 return MCDisassembler::Fail;
3028 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3029 return MCDisassembler::Fail;
3030 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3031 return MCDisassembler::Fail;
3032 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3033 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3034
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3035 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3036}
3037
3038
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3039static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3040 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3041 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3042
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3043 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3044 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3045 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3046 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3047
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3048 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3049 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3050
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3051 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3052 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3053
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3054 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3055 return MCDisassembler::Fail;
3056 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3057 return MCDisassembler::Fail;
3058 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3059 return MCDisassembler::Fail;
3060 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3061 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3062
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3063 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3064}
3065
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3066static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3067 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3068 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3069
3070 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3071 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3072 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3073 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3074 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3075 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3076
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3077 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3078
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3079 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3080 return MCDisassembler::Fail;
3081 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3082 return MCDisassembler::Fail;
3083 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3084 return MCDisassembler::Fail;
3085 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3086 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3087
3088 return S;
3089}
3090
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3091static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3092 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3093 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3094
3095 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3096 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3097 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3098 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3099 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3100 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3101 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3102
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3103 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3104 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3105
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3106 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3107 return MCDisassembler::Fail;
3108 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3109 return MCDisassembler::Fail;
3110 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3111 return MCDisassembler::Fail;
3112 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3113 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3114
3115 return S;
3116}
3117
3118
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3119static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3120 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3121 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3122
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3123 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3124 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3125 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3126 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3127 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3128 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3129
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3130 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3131
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3132 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3133 return MCDisassembler::Fail;
3134 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3135 return MCDisassembler::Fail;
3136 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3137 return MCDisassembler::Fail;
3138 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3139 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3140
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3141 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3142}
3143
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3144static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3145 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3146 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3147
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3148 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3149 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3150 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3151 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3152 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3153 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3154
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3155 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3156
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3157 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3158 return MCDisassembler::Fail;
3159 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3160 return MCDisassembler::Fail;
3161 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3162 return MCDisassembler::Fail;
3163 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3164 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3165
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3166 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3167}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3168
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3169static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3170 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3171 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3172
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3173 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3174 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3175 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3176 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3177 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3178
3179 unsigned align = 0;
3180 unsigned index = 0;
3181 switch (size) {
3182 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3183 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3184 case 0:
3185 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3186 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3187 index = fieldFromInstruction32(Insn, 5, 3);
3188 break;
3189 case 1:
3190 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3191 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3192 index = fieldFromInstruction32(Insn, 6, 2);
3193 if (fieldFromInstruction32(Insn, 4, 1))
3194 align = 2;
3195 break;
3196 case 2:
3197 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3198 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3199 index = fieldFromInstruction32(Insn, 7, 1);
3200 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3201 align = 4;
3202 }
3203
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3204 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3205 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3206 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3207 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3208 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3209 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3210 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3211 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3212 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3213 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3214 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3215 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3216 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3217 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3218 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3219 }
3220
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3221 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3222 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3223 Inst.addOperand(MCOperand::CreateImm(index));
3224
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3225 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3226}
3227
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3228static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3229 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3230 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3231
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3232 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3233 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3234 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3235 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3236 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3237
3238 unsigned align = 0;
3239 unsigned index = 0;
3240 switch (size) {
3241 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3242 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3243 case 0:
3244 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3245 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3246 index = fieldFromInstruction32(Insn, 5, 3);
3247 break;
3248 case 1:
3249 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3250 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3251 index = fieldFromInstruction32(Insn, 6, 2);
3252 if (fieldFromInstruction32(Insn, 4, 1))
3253 align = 2;
3254 break;
3255 case 2:
3256 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3257 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3258 index = fieldFromInstruction32(Insn, 7, 1);
3259 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3260 align = 4;
3261 }
3262
3263 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3264 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3265 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3266 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3267 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3268 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3269 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3270 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3271 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3272 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3273 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3274 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3275 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3276 }
3277
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3278 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3279 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3280 Inst.addOperand(MCOperand::CreateImm(index));
3281
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3282 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3283}
3284
3285
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3286static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3287 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3288 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3289
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3290 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3291 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3292 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3293 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3294 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3295
3296 unsigned align = 0;
3297 unsigned index = 0;
3298 unsigned inc = 1;
3299 switch (size) {
3300 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3301 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3302 case 0:
3303 index = fieldFromInstruction32(Insn, 5, 3);
3304 if (fieldFromInstruction32(Insn, 4, 1))
3305 align = 2;
3306 break;
3307 case 1:
3308 index = fieldFromInstruction32(Insn, 6, 2);
3309 if (fieldFromInstruction32(Insn, 4, 1))
3310 align = 4;
3311 if (fieldFromInstruction32(Insn, 5, 1))
3312 inc = 2;
3313 break;
3314 case 2:
3315 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3316 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3317 index = fieldFromInstruction32(Insn, 7, 1);
3318 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3319 align = 8;
3320 if (fieldFromInstruction32(Insn, 6, 1))
3321 inc = 2;
3322 break;
3323 }
3324
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3325 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3326 return MCDisassembler::Fail;
3327 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3328 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3329 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3330 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3331 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3332 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3334 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3335 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3336 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3337 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3338 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3339 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3340 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3341 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3342 }
3343
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3344 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3345 return MCDisassembler::Fail;
3346 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3347 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3348 Inst.addOperand(MCOperand::CreateImm(index));
3349
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3350 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3351}
3352
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3353static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3354 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3355 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3356
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3357 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3358 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3359 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3360 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3361 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3362
3363 unsigned align = 0;
3364 unsigned index = 0;
3365 unsigned inc = 1;
3366 switch (size) {
3367 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3368 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3369 case 0:
3370 index = fieldFromInstruction32(Insn, 5, 3);
3371 if (fieldFromInstruction32(Insn, 4, 1))
3372 align = 2;
3373 break;
3374 case 1:
3375 index = fieldFromInstruction32(Insn, 6, 2);
3376 if (fieldFromInstruction32(Insn, 4, 1))
3377 align = 4;
3378 if (fieldFromInstruction32(Insn, 5, 1))
3379 inc = 2;
3380 break;
3381 case 2:
3382 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3383 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3384 index = fieldFromInstruction32(Insn, 7, 1);
3385 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3386 align = 8;
3387 if (fieldFromInstruction32(Insn, 6, 1))
3388 inc = 2;
3389 break;
3390 }
3391
3392 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3393 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3394 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3395 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3396 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3397 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3398 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3399 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3400 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3401 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3402 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3403 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3404 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3405 }
3406
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3407 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3408 return MCDisassembler::Fail;
3409 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3410 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3411 Inst.addOperand(MCOperand::CreateImm(index));
3412
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3413 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3414}
3415
3416
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3417static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3418 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3419 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3420
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3421 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3422 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3423 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3424 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3425 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3426
3427 unsigned align = 0;
3428 unsigned index = 0;
3429 unsigned inc = 1;
3430 switch (size) {
3431 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3432 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3433 case 0:
3434 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3435 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3436 index = fieldFromInstruction32(Insn, 5, 3);
3437 break;
3438 case 1:
3439 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3440 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3441 index = fieldFromInstruction32(Insn, 6, 2);
3442 if (fieldFromInstruction32(Insn, 5, 1))
3443 inc = 2;
3444 break;
3445 case 2:
3446 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3447 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3448 index = fieldFromInstruction32(Insn, 7, 1);
3449 if (fieldFromInstruction32(Insn, 6, 1))
3450 inc = 2;
3451 break;
3452 }
3453
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3454 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3455 return MCDisassembler::Fail;
3456 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3457 return MCDisassembler::Fail;
3458 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3459 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3460
3461 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3463 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3464 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3465 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3466 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3467 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3468 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3469 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3470 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3471 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3472 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3473 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3474 }
3475
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3476 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3477 return MCDisassembler::Fail;
3478 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3479 return MCDisassembler::Fail;
3480 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3481 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3482 Inst.addOperand(MCOperand::CreateImm(index));
3483
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3484 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3485}
3486
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3487static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3488 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3489 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3490
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3491 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3492 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3493 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3494 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3495 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3496
3497 unsigned align = 0;
3498 unsigned index = 0;
3499 unsigned inc = 1;
3500 switch (size) {
3501 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3502 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3503 case 0:
3504 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3505 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3506 index = fieldFromInstruction32(Insn, 5, 3);
3507 break;
3508 case 1:
3509 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3510 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3511 index = fieldFromInstruction32(Insn, 6, 2);
3512 if (fieldFromInstruction32(Insn, 5, 1))
3513 inc = 2;
3514 break;
3515 case 2:
3516 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3517 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3518 index = fieldFromInstruction32(Insn, 7, 1);
3519 if (fieldFromInstruction32(Insn, 6, 1))
3520 inc = 2;
3521 break;
3522 }
3523
3524 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3525 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3526 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3527 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3528 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3529 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3530 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3531 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3532 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3533 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3534 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3535 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3536 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3537 }
3538
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3539 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3540 return MCDisassembler::Fail;
3541 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3542 return MCDisassembler::Fail;
3543 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3544 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3545 Inst.addOperand(MCOperand::CreateImm(index));
3546
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3547 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3548}
3549
3550
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3551static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3552 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3553 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3554
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3555 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3556 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3557 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3558 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3559 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3560
3561 unsigned align = 0;
3562 unsigned index = 0;
3563 unsigned inc = 1;
3564 switch (size) {
3565 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3566 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3567 case 0:
3568 if (fieldFromInstruction32(Insn, 4, 1))
3569 align = 4;
3570 index = fieldFromInstruction32(Insn, 5, 3);
3571 break;
3572 case 1:
3573 if (fieldFromInstruction32(Insn, 4, 1))
3574 align = 8;
3575 index = fieldFromInstruction32(Insn, 6, 2);
3576 if (fieldFromInstruction32(Insn, 5, 1))
3577 inc = 2;
3578 break;
3579 case 2:
3580 if (fieldFromInstruction32(Insn, 4, 2))
3581 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3582 index = fieldFromInstruction32(Insn, 7, 1);
3583 if (fieldFromInstruction32(Insn, 6, 1))
3584 inc = 2;
3585 break;
3586 }
3587
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3588 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3589 return MCDisassembler::Fail;
3590 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3591 return MCDisassembler::Fail;
3592 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3593 return MCDisassembler::Fail;
3594 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3595 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3596
3597 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3598 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3599 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3600 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3601 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3602 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3603 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3604 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3605 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3606 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3607 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3608 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3609 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3610 }
3611
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3612 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3613 return MCDisassembler::Fail;
3614 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3615 return MCDisassembler::Fail;
3616 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3617 return MCDisassembler::Fail;
3618 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3619 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3620 Inst.addOperand(MCOperand::CreateImm(index));
3621
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3622 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3623}
3624
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3625static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3626 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3627 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3628
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3629 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3630 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3631 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3632 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3633 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3634
3635 unsigned align = 0;
3636 unsigned index = 0;
3637 unsigned inc = 1;
3638 switch (size) {
3639 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3640 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3641 case 0:
3642 if (fieldFromInstruction32(Insn, 4, 1))
3643 align = 4;
3644 index = fieldFromInstruction32(Insn, 5, 3);
3645 break;
3646 case 1:
3647 if (fieldFromInstruction32(Insn, 4, 1))
3648 align = 8;
3649 index = fieldFromInstruction32(Insn, 6, 2);
3650 if (fieldFromInstruction32(Insn, 5, 1))
3651 inc = 2;
3652 break;
3653 case 2:
3654 if (fieldFromInstruction32(Insn, 4, 2))
3655 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3656 index = fieldFromInstruction32(Insn, 7, 1);
3657 if (fieldFromInstruction32(Insn, 6, 1))
3658 inc = 2;
3659 break;
3660 }
3661
3662 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3663 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3664 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3665 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3667 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3668 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3669 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3670 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3671 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3672 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3673 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3674 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3675 }
3676
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3677 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3678 return MCDisassembler::Fail;
3679 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3680 return MCDisassembler::Fail;
3681 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3682 return MCDisassembler::Fail;
3683 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3684 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3685 Inst.addOperand(MCOperand::CreateImm(index));
3686
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3687 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3688}
3689
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3690static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3691 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3692 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3693 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3694 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3695 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3696 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3697 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3698
3699 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3700 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3701
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3702 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3703 return MCDisassembler::Fail;
3704 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3705 return MCDisassembler::Fail;
3706 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3707 return MCDisassembler::Fail;
3708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3709 return MCDisassembler::Fail;
3710 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3711 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3712
3713 return S;
3714}
3715
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3716static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3717 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3718 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3719 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3720 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3721 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3722 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3723 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3724
3725 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3726 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3727
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3728 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3729 return MCDisassembler::Fail;
3730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3731 return MCDisassembler::Fail;
3732 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3733 return MCDisassembler::Fail;
3734 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3735 return MCDisassembler::Fail;
3736 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3737 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3738
3739 return S;
3740}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]3741
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3742static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3743 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3744 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3745 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3746 // The InstPrinter needs to have the low bit of the predicate in
3747 // the mask operand to be able to print it properly.
3748 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3749
3750 if (pred == 0xF) {
3751 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3752 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]3753 }
3754
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3755 if ((mask & 0xF) == 0) {
3756 // Preserve the high bit of the mask, which is the low bit of
3757 // the predicate.
3758 mask &= 0x10;
3759 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3760 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3761 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3762
3763 Inst.addOperand(MCOperand::CreateImm(pred));
3764 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3765 return S;
3766}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]3767
3768static DecodeStatus
3769DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3770 uint64_t Address, const void *Decoder) {
3771 DecodeStatus S = MCDisassembler::Success;
3772
3773 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3774 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3775 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3776 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3777 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3778 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3779 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3780 bool writeback = (W == 1) | (P == 0);
3781
3782 addr |= (U << 8) | (Rn << 9);
3783
3784 if (writeback && (Rn == Rt || Rn == Rt2))
3785 Check(S, MCDisassembler::SoftFail);
3786 if (Rt == Rt2)
3787 Check(S, MCDisassembler::SoftFail);
3788
3789 // Rt
3790 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3791 return MCDisassembler::Fail;
3792 // Rt2
3793 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3794 return MCDisassembler::Fail;
3795 // Writeback operand
3796 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3797 return MCDisassembler::Fail;
3798 // addr
3799 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3800 return MCDisassembler::Fail;
3801
3802 return S;
3803}
3804
3805static DecodeStatus
3806DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3807 uint64_t Address, const void *Decoder) {
3808 DecodeStatus S = MCDisassembler::Success;
3809
3810 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3811 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3812 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3813 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3814 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3815 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3816 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3817 bool writeback = (W == 1) | (P == 0);
3818
3819 addr |= (U << 8) | (Rn << 9);
3820
3821 if (writeback && (Rn == Rt || Rn == Rt2))
3822 Check(S, MCDisassembler::SoftFail);
3823
3824 // Writeback operand
3825 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3826 return MCDisassembler::Fail;
3827 // Rt
3828 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3829 return MCDisassembler::Fail;
3830 // Rt2
3831 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3832 return MCDisassembler::Fail;
3833 // addr
3834 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3835 return MCDisassembler::Fail;
3836
3837 return S;
3838}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]3839
3840static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
3841 uint64_t Address, const void *Decoder) {
3842 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
3843 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
3844 if (sign1 != sign2) return MCDisassembler::Fail;
3845
3846 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
3847 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
3848 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
3849 Val |= sign1 << 12;
3850 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
3851
3852 return MCDisassembler::Success;
3853}
3854
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]3855static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val,
3856 uint64_t Address,
3857 const void *Decoder) {
3858 DecodeStatus S = MCDisassembler::Success;
3859
3860 // Shift of "asr #32" is not allowed in Thumb2 mode.
3861 if (Val == 0x20) S = MCDisassembler::SoftFail;
3862 Inst.addOperand(MCOperand::CreateImm(Val));
3863 return S;
3864}
3865