blob: 138b95216d8d0c469a9924e6d272b31b97fda34e [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
Jerome Glisse771fe6b2009-06-05 14:42:42 +020031/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
Jerome Glissed39c3b82009-09-28 18:34:43 +020045/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
Arun Sharma600634972011-07-26 16:09:06 -070063#include <linux/atomic.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020064#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
Jerome Glisse4c788672009-11-20 14:29:23 +010068#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
Thomas Hellstrom147666f2010-11-17 12:38:32 +000072#include <ttm/ttm_execbuf_util.h>
Jerome Glisse4c788672009-11-20 14:29:23 +010073
Dave Airliec2142712009-09-22 08:50:10 +100074#include "radeon_family.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020075#include "radeon_mode.h"
76#include "radeon_reg.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020077
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
Michel Dänzerecc0b322009-07-21 11:23:57 +020089extern int radeon_testing;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020090extern int radeon_connector_table;
Dave Airlie4ce001a2009-08-13 16:32:14 +100091extern int radeon_tv;
Christian Koenigdafc3bd2009-10-11 23:49:13 +020092extern int radeon_audio;
Alex Deucherf46c0122010-03-31 00:33:27 -040093extern int radeon_disp_priority;
Alex Deuchere2b0a8e2010-03-17 02:07:37 -040094extern int radeon_hw_i2c;
Alex Deucherd42dd572011-01-12 20:05:11 -050095extern int radeon_pcie_gen2;
Alex Deuchera18cee12011-11-01 14:20:30 -040096extern int radeon_msi;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020097
98/*
99 * Copy from radeon_drv.h so we don't have to include both and have conflicting
100 * symbol;
101 */
102#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
Jerome Glisse225758d2010-03-09 14:45:10 +0000103#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
Jerome Glissee8217672010-02-15 21:36:13 +0100104/* RADEON_IB_POOL_SIZE must be a power of 2 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200105#define RADEON_IB_POOL_SIZE 16
Michael Wittenc245cb92011-09-16 20:45:30 +0000106#define RADEON_DEBUGFS_MAX_COMPONENTS 32
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200107#define RADEONFB_CONN_LIMIT 4
Yang Zhaof657c2a2009-09-15 12:21:01 +1000108#define RADEON_BIOS_NUM_SCRATCH 8
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200109
Alex Deucher1b370782011-11-17 20:13:28 -0500110/* max number of rings */
111#define RADEON_NUM_RINGS 3
112
113/* internal ring indices */
114/* r1xx+ has gfx CP ring */
115#define RADEON_RING_TYPE_GFX_INDEX 0
116
117/* cayman has 2 compute CP rings */
118#define CAYMAN_RING_TYPE_CP1_INDEX 1
119#define CAYMAN_RING_TYPE_CP2_INDEX 2
120
Jerome Glisse721604a2012-01-05 22:11:05 -0500121/* hardcode those limit for now */
122#define RADEON_VA_RESERVED_SIZE (8 << 20)
123#define RADEON_IB_VM_MAX_SIZE (64 << 10)
124
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200125/*
126 * Errata workarounds.
127 */
128enum radeon_pll_errata {
129 CHIP_ERRATA_R300_CG = 0x00000001,
130 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
131 CHIP_ERRATA_PLL_DELAY = 0x00000004
132};
133
134
135struct radeon_device;
136
137
138/*
139 * BIOS.
140 */
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000141#define ATRM_BIOS_PAGE 4096
142
Dave Airlie8edb3812010-03-01 21:50:01 +1100143#if defined(CONFIG_VGA_SWITCHEROO)
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000144bool radeon_atrm_supported(struct pci_dev *pdev);
145int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
Dave Airlie8edb3812010-03-01 21:50:01 +1100146#else
147static inline bool radeon_atrm_supported(struct pci_dev *pdev)
148{
149 return false;
150}
151
152static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
153 return -EINVAL;
154}
155#endif
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200156bool radeon_get_bios(struct radeon_device *rdev);
157
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000158
159/*
Jerome Glisse9fc04b52012-01-23 11:52:15 -0500160 * Mutex which allows recursive locking from the same process.
161 */
162struct radeon_mutex {
163 struct mutex mutex;
164 struct task_struct *owner;
165 int level;
166};
167
168static inline void radeon_mutex_init(struct radeon_mutex *mutex)
169{
170 mutex_init(&mutex->mutex);
171 mutex->owner = NULL;
172 mutex->level = 0;
173}
174
175static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
176{
177 if (mutex_trylock(&mutex->mutex)) {
178 /* The mutex was unlocked before, so it's ours now */
179 mutex->owner = current;
180 } else if (mutex->owner != current) {
181 /* Another process locked the mutex, take it */
182 mutex_lock(&mutex->mutex);
183 mutex->owner = current;
184 }
185 /* Otherwise the mutex was already locked by this process */
186
187 mutex->level++;
188}
189
190static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
191{
192 if (--mutex->level > 0)
193 return;
194
195 mutex->owner = NULL;
196 mutex_unlock(&mutex->mutex);
197}
198
199
200/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000201 * Dummy page
202 */
203struct radeon_dummy_page {
204 struct page *page;
205 dma_addr_t addr;
206};
207int radeon_dummy_page_init(struct radeon_device *rdev);
208void radeon_dummy_page_fini(struct radeon_device *rdev);
209
210
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200211/*
212 * Clocks
213 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200214struct radeon_clock {
215 struct radeon_pll p1pll;
216 struct radeon_pll p2pll;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500217 struct radeon_pll dcpll;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200218 struct radeon_pll spll;
219 struct radeon_pll mpll;
220 /* 10 Khz units */
221 uint32_t default_mclk;
222 uint32_t default_sclk;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500223 uint32_t default_dispclk;
224 uint32_t dp_extclk;
Alex Deucherb20f9be2011-06-08 13:01:11 -0400225 uint32_t max_pixel_clock;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200226};
227
Rafał Miłecki74338742009-11-03 00:53:02 +0100228/*
229 * Power management
230 */
231int radeon_pm_init(struct radeon_device *rdev);
Alex Deucher29fb52c2010-03-11 10:01:17 -0500232void radeon_pm_fini(struct radeon_device *rdev);
Rafał Miłeckic913e232009-12-22 23:02:16 +0100233void radeon_pm_compute_clocks(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400234void radeon_pm_suspend(struct radeon_device *rdev);
235void radeon_pm_resume(struct radeon_device *rdev);
Alex Deucher56278a82009-12-28 13:58:44 -0500236void radeon_combios_get_power_modes(struct radeon_device *rdev);
237void radeon_atombios_get_power_modes(struct radeon_device *rdev);
Alex Deucher8a83ec52011-04-12 14:49:23 -0400238void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
Alex Deucherf8920342010-06-30 12:02:03 -0400239void rs690_pm_info(struct radeon_device *rdev);
Alex Deucher20d391d2011-02-01 16:12:34 -0500240extern int rv6xx_get_temp(struct radeon_device *rdev);
241extern int rv770_get_temp(struct radeon_device *rdev);
242extern int evergreen_get_temp(struct radeon_device *rdev);
243extern int sumo_get_temp(struct radeon_device *rdev);
Alex Deucher1bd47d22012-03-20 17:18:10 -0400244extern int si_get_temp(struct radeon_device *rdev);
Jerome Glisse285484e2011-12-16 17:03:42 -0500245extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
246 unsigned *bankh, unsigned *mtaspect,
247 unsigned *tile_split);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000248
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200249/*
250 * Fences.
251 */
252struct radeon_fence_driver {
253 uint32_t scratch_reg;
Jerome Glisse30eb77f2011-11-20 20:45:34 +0000254 uint64_t gpu_addr;
255 volatile uint32_t *cpu_addr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200256 atomic_t seq;
257 uint32_t last_seq;
Jerome Glisse225758d2010-03-09 14:45:10 +0000258 unsigned long last_jiffies;
259 unsigned long last_timeout;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200260 wait_queue_head_t queue;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200261 struct list_head created;
Christian König851a6bd2011-10-24 15:05:29 +0200262 struct list_head emitted;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200263 struct list_head signaled;
Jerome Glisse0a0c7592009-12-11 20:36:19 +0100264 bool initialized;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200265};
266
267struct radeon_fence {
268 struct radeon_device *rdev;
269 struct kref kref;
270 struct list_head list;
271 /* protected by radeon_fence.lock */
272 uint32_t seq;
Christian König851a6bd2011-10-24 15:05:29 +0200273 bool emitted;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200274 bool signaled;
Alex Deucher74652802011-08-25 13:39:48 -0400275 /* RB, DMA, etc. */
276 int ring;
Christian König93504fc2012-01-05 22:11:06 -0500277 struct radeon_semaphore *semaphore;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200278};
279
Jerome Glisse30eb77f2011-11-20 20:45:34 +0000280int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
281int radeon_fence_driver_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200282void radeon_fence_driver_fini(struct radeon_device *rdev);
Alex Deucher74652802011-08-25 13:39:48 -0400283int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200284int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
Alex Deucher74652802011-08-25 13:39:48 -0400285void radeon_fence_process(struct radeon_device *rdev, int ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200286bool radeon_fence_signaled(struct radeon_fence *fence);
287int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
Alex Deucher74652802011-08-25 13:39:48 -0400288int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
289int radeon_fence_wait_last(struct radeon_device *rdev, int ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200290struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
291void radeon_fence_unref(struct radeon_fence **fence);
Christian König47492a22011-10-20 12:38:09 +0200292int radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200293
Dave Airliee024e112009-06-24 09:48:08 +1000294/*
295 * Tiling registers
296 */
297struct radeon_surface_reg {
Jerome Glisse4c788672009-11-20 14:29:23 +0100298 struct radeon_bo *bo;
Dave Airliee024e112009-06-24 09:48:08 +1000299};
300
301#define RADEON_GEM_MAX_SURFACES 8
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200302
303/*
Jerome Glisse4c788672009-11-20 14:29:23 +0100304 * TTM.
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200305 */
Jerome Glisse4c788672009-11-20 14:29:23 +0100306struct radeon_mman {
307 struct ttm_bo_global_ref bo_global_ref;
Dave Airlieba4420c2010-03-09 10:56:52 +1000308 struct drm_global_reference mem_global_ref;
Jerome Glisse4c788672009-11-20 14:29:23 +0100309 struct ttm_bo_device bdev;
Jerome Glisse0a0c7592009-12-11 20:36:19 +0100310 bool mem_global_referenced;
311 bool initialized;
Jerome Glisse4c788672009-11-20 14:29:23 +0100312};
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200313
Jerome Glisse721604a2012-01-05 22:11:05 -0500314/* bo virtual address in a specific vm */
315struct radeon_bo_va {
316 /* bo list is protected by bo being reserved */
317 struct list_head bo_list;
318 /* vm list is protected by vm mutex */
319 struct list_head vm_list;
320 /* constant after initialization */
321 struct radeon_vm *vm;
322 struct radeon_bo *bo;
323 uint64_t soffset;
324 uint64_t eoffset;
325 uint32_t flags;
326 bool valid;
327};
328
Jerome Glisse4c788672009-11-20 14:29:23 +0100329struct radeon_bo {
330 /* Protected by gem.mutex */
331 struct list_head list;
332 /* Protected by tbo.reserved */
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100333 u32 placements[3];
334 struct ttm_placement placement;
Jerome Glisse4c788672009-11-20 14:29:23 +0100335 struct ttm_buffer_object tbo;
336 struct ttm_bo_kmap_obj kmap;
337 unsigned pin_count;
338 void *kptr;
339 u32 tiling_flags;
340 u32 pitch;
341 int surface_reg;
Jerome Glisse721604a2012-01-05 22:11:05 -0500342 /* list of all virtual address to which this bo
343 * is associated to
344 */
345 struct list_head va;
Jerome Glisse4c788672009-11-20 14:29:23 +0100346 /* Constant after initialization */
347 struct radeon_device *rdev;
Daniel Vetter441921d2011-02-18 17:59:16 +0100348 struct drm_gem_object gem_base;
Jerome Glisse4c788672009-11-20 14:29:23 +0100349};
Daniel Vetter7e4d15d2011-02-18 17:59:17 +0100350#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
Jerome Glisse4c788672009-11-20 14:29:23 +0100351
352struct radeon_bo_list {
Thomas Hellstrom147666f2010-11-17 12:38:32 +0000353 struct ttm_validate_buffer tv;
Jerome Glisse4c788672009-11-20 14:29:23 +0100354 struct radeon_bo *bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200355 uint64_t gpu_offset;
356 unsigned rdomain;
357 unsigned wdomain;
Jerome Glisse4c788672009-11-20 14:29:23 +0100358 u32 tiling_flags;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200359};
360
Jerome Glisseb15ba512011-11-15 11:48:34 -0500361/* sub-allocation manager, it has to be protected by another lock.
362 * By conception this is an helper for other part of the driver
363 * like the indirect buffer or semaphore, which both have their
364 * locking.
365 *
366 * Principe is simple, we keep a list of sub allocation in offset
367 * order (first entry has offset == 0, last entry has the highest
368 * offset).
369 *
370 * When allocating new object we first check if there is room at
371 * the end total_size - (last_object_offset + last_object_size) >=
372 * alloc_size. If so we allocate new object there.
373 *
374 * When there is not enough room at the end, we start waiting for
375 * each sub object until we reach object_offset+object_size >=
376 * alloc_size, this object then become the sub object we return.
377 *
378 * Alignment can't be bigger than page size.
379 *
380 * Hole are not considered for allocation to keep things simple.
381 * Assumption is that there won't be hole (all object on same
382 * alignment).
383 */
384struct radeon_sa_manager {
385 struct radeon_bo *bo;
386 struct list_head sa_bo;
387 unsigned size;
388 uint64_t gpu_addr;
389 void *cpu_ptr;
390 uint32_t domain;
391};
392
393struct radeon_sa_bo;
394
395/* sub-allocation buffer */
396struct radeon_sa_bo {
397 struct list_head list;
398 struct radeon_sa_manager *manager;
399 unsigned offset;
400 unsigned size;
401};
402
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200403/*
404 * GEM objects.
405 */
406struct radeon_gem {
Jerome Glisse4c788672009-11-20 14:29:23 +0100407 struct mutex mutex;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200408 struct list_head objects;
409};
410
411int radeon_gem_init(struct radeon_device *rdev);
412void radeon_gem_fini(struct radeon_device *rdev);
413int radeon_gem_object_create(struct radeon_device *rdev, int size,
Jerome Glisse4c788672009-11-20 14:29:23 +0100414 int alignment, int initial_domain,
415 bool discardable, bool kernel,
416 struct drm_gem_object **obj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200417
Dave Airlieff72145b2011-02-07 12:16:14 +1000418int radeon_mode_dumb_create(struct drm_file *file_priv,
419 struct drm_device *dev,
420 struct drm_mode_create_dumb *args);
421int radeon_mode_dumb_mmap(struct drm_file *filp,
422 struct drm_device *dev,
423 uint32_t handle, uint64_t *offset_p);
424int radeon_mode_dumb_destroy(struct drm_file *file_priv,
425 struct drm_device *dev,
426 uint32_t handle);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200427
428/*
Jerome Glissec1341e52011-12-21 12:13:47 -0500429 * Semaphores.
430 */
431struct radeon_ring;
432
433#define RADEON_SEMAPHORE_BO_SIZE 256
434
435struct radeon_semaphore_driver {
436 rwlock_t lock;
437 struct list_head bo;
438};
439
440struct radeon_semaphore_bo;
441
442/* everything here is constant */
443struct radeon_semaphore {
444 struct list_head list;
445 uint64_t gpu_addr;
446 uint32_t *cpu_ptr;
447 struct radeon_semaphore_bo *bo;
448};
449
450struct radeon_semaphore_bo {
451 struct list_head list;
452 struct radeon_ib *ib;
453 struct list_head free;
454 struct radeon_semaphore semaphores[RADEON_SEMAPHORE_BO_SIZE/8];
455 unsigned nused;
456};
457
458void radeon_semaphore_driver_fini(struct radeon_device *rdev);
459int radeon_semaphore_create(struct radeon_device *rdev,
460 struct radeon_semaphore **semaphore);
461void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
462 struct radeon_semaphore *semaphore);
463void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
464 struct radeon_semaphore *semaphore);
465void radeon_semaphore_free(struct radeon_device *rdev,
466 struct radeon_semaphore *semaphore);
467
468/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200469 * GART structures, functions & helpers
470 */
471struct radeon_mc;
472
Matt Turnera77f1712009-10-14 00:34:41 -0400473#define RADEON_GPU_PAGE_SIZE 4096
Jerome Glissed594e462010-02-17 21:54:29 +0000474#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
Alex Deucher003cefe2011-09-16 12:04:08 -0400475#define RADEON_GPU_PAGE_SHIFT 12
Jerome Glisse721604a2012-01-05 22:11:05 -0500476#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
Matt Turnera77f1712009-10-14 00:34:41 -0400477
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200478struct radeon_gart {
479 dma_addr_t table_addr;
Jerome Glissec9a1be92011-11-03 11:16:49 -0400480 struct radeon_bo *robj;
481 void *ptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200482 unsigned num_gpu_pages;
483 unsigned num_cpu_pages;
484 unsigned table_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200485 struct page **pages;
486 dma_addr_t *pages_addr;
487 bool ready;
488};
489
490int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
491void radeon_gart_table_ram_free(struct radeon_device *rdev);
492int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
493void radeon_gart_table_vram_free(struct radeon_device *rdev);
Jerome Glissec9a1be92011-11-03 11:16:49 -0400494int radeon_gart_table_vram_pin(struct radeon_device *rdev);
495void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200496int radeon_gart_init(struct radeon_device *rdev);
497void radeon_gart_fini(struct radeon_device *rdev);
498void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
499 int pages);
500int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
Konrad Rzeszutek Wilkc39d3512010-12-02 11:04:29 -0500501 int pages, struct page **pagelist,
502 dma_addr_t *dma_addr);
Jerome Glissec9a1be92011-11-03 11:16:49 -0400503void radeon_gart_restore(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200504
505
506/*
507 * GPU MC structures, functions & helpers
508 */
509struct radeon_mc {
510 resource_size_t aper_size;
511 resource_size_t aper_base;
512 resource_size_t agp_base;
Dave Airlie7a50f012009-07-21 20:39:30 +1000513 /* for some chips with <= 32MB we need to lie
514 * about vram size near mc fb location */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000515 u64 mc_vram_size;
Jerome Glissed594e462010-02-17 21:54:29 +0000516 u64 visible_vram_size;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000517 u64 gtt_size;
518 u64 gtt_start;
519 u64 gtt_end;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000520 u64 vram_start;
521 u64 vram_end;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200522 unsigned vram_width;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000523 u64 real_vram_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200524 int vram_mtrr;
525 bool vram_is_ddr;
Jerome Glissed594e462010-02-17 21:54:29 +0000526 bool igp_sideport_enabled;
Alex Deucher8d369bb2010-07-15 10:51:10 -0400527 u64 gtt_base_align;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200528};
529
Alex Deucher06b64762010-01-05 11:27:29 -0500530bool radeon_combios_sideport_present(struct radeon_device *rdev);
531bool radeon_atombios_sideport_present(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200532
533/*
534 * GPU scratch registers structures, functions & helpers
535 */
536struct radeon_scratch {
537 unsigned num_reg;
Alex Deucher724c80e2010-08-27 18:25:25 -0400538 uint32_t reg_base;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200539 bool free[32];
540 uint32_t reg[32];
541};
542
543int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
544void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
545
546
547/*
548 * IRQS.
549 */
Alex Deucher6f34be52010-11-21 10:59:01 -0500550
551struct radeon_unpin_work {
552 struct work_struct work;
553 struct radeon_device *rdev;
554 int crtc_id;
555 struct radeon_fence *fence;
556 struct drm_pending_vblank_event *event;
557 struct radeon_bo *old_rbo;
558 u64 new_crtc_base;
559};
560
561struct r500_irq_stat_regs {
562 u32 disp_int;
563};
564
565struct r600_irq_stat_regs {
566 u32 disp_int;
567 u32 disp_int_cont;
568 u32 disp_int_cont2;
569 u32 d1grph_int;
570 u32 d2grph_int;
571};
572
573struct evergreen_irq_stat_regs {
574 u32 disp_int;
575 u32 disp_int_cont;
576 u32 disp_int_cont2;
577 u32 disp_int_cont3;
578 u32 disp_int_cont4;
579 u32 disp_int_cont5;
580 u32 d1grph_int;
581 u32 d2grph_int;
582 u32 d3grph_int;
583 u32 d4grph_int;
584 u32 d5grph_int;
585 u32 d6grph_int;
586};
587
588union radeon_irq_stat_regs {
589 struct r500_irq_stat_regs r500;
590 struct r600_irq_stat_regs r600;
591 struct evergreen_irq_stat_regs evergreen;
592};
593
Ilija Hadzic54bd52062011-10-26 15:43:58 -0400594#define RADEON_MAX_HPD_PINS 6
595#define RADEON_MAX_CRTCS 6
596#define RADEON_MAX_HDMI_BLOCKS 2
597
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200598struct radeon_irq {
599 bool installed;
Alex Deucher1b370782011-11-17 20:13:28 -0500600 bool sw_int[RADEON_NUM_RINGS];
Ilija Hadzic54bd52062011-10-26 15:43:58 -0400601 bool crtc_vblank_int[RADEON_MAX_CRTCS];
602 bool pflip[RADEON_MAX_CRTCS];
Rafał Miłecki73a6d3f2010-01-08 00:22:47 +0100603 wait_queue_head_t vblank_queue;
Ilija Hadzic54bd52062011-10-26 15:43:58 -0400604 bool hpd[RADEON_MAX_HPD_PINS];
Alex Deucher2031f772010-04-22 12:52:11 -0400605 bool gui_idle;
606 bool gui_idle_acked;
607 wait_queue_head_t idle_queue;
Ilija Hadzic54bd52062011-10-26 15:43:58 -0400608 bool hdmi[RADEON_MAX_HDMI_BLOCKS];
Dave Airlie1614f8b2009-12-01 16:04:56 +1000609 spinlock_t sw_lock;
Alex Deucher1b370782011-11-17 20:13:28 -0500610 int sw_refcount[RADEON_NUM_RINGS];
Alex Deucher6f34be52010-11-21 10:59:01 -0500611 union radeon_irq_stat_regs stat_regs;
Ilija Hadzic54bd52062011-10-26 15:43:58 -0400612 spinlock_t pflip_lock[RADEON_MAX_CRTCS];
613 int pflip_refcount[RADEON_MAX_CRTCS];
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200614};
615
616int radeon_irq_kms_init(struct radeon_device *rdev);
617void radeon_irq_kms_fini(struct radeon_device *rdev);
Alex Deucher1b370782011-11-17 20:13:28 -0500618void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
619void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
Alex Deucher6f34be52010-11-21 10:59:01 -0500620void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
621void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200622
623/*
Christian Könige32eb502011-10-23 12:56:27 +0200624 * CP & rings.
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200625 */
Alex Deucher74652802011-08-25 13:39:48 -0400626
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200627struct radeon_ib {
Jerome Glisseb15ba512011-11-15 11:48:34 -0500628 struct radeon_sa_bo sa_bo;
Jerome Glissee8217672010-02-15 21:36:13 +0100629 unsigned idx;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200630 uint32_t length_dw;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500631 uint64_t gpu_addr;
632 uint32_t *ptr;
633 struct radeon_fence *fence;
Jerome Glisse721604a2012-01-05 22:11:05 -0500634 unsigned vm_id;
Alex Deucherdfcf5f32012-03-20 17:18:14 -0400635 bool is_const_ib;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200636};
637
Dave Airlieecb114a2009-09-15 11:12:56 +1000638/*
639 * locking -
640 * mutex protects scheduled_ibs, ready, alloc_bm
641 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200642struct radeon_ib_pool {
Jerome Glisse9fc04b52012-01-23 11:52:15 -0500643 struct radeon_mutex mutex;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500644 struct radeon_sa_manager sa_manager;
645 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
646 bool ready;
647 unsigned head_id;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200648};
649
Christian Könige32eb502011-10-23 12:56:27 +0200650struct radeon_ring {
Jerome Glisse4c788672009-11-20 14:29:23 +0100651 struct radeon_bo *ring_obj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200652 volatile uint32_t *ring;
653 unsigned rptr;
Christian König5596a9d2011-10-13 12:48:45 +0200654 unsigned rptr_offs;
655 unsigned rptr_reg;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200656 unsigned wptr;
657 unsigned wptr_old;
Christian König5596a9d2011-10-13 12:48:45 +0200658 unsigned wptr_reg;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200659 unsigned ring_size;
660 unsigned ring_free_dw;
661 int count_dw;
662 uint64_t gpu_addr;
663 uint32_t align_mask;
664 uint32_t ptr_mask;
665 struct mutex mutex;
666 bool ready;
Alex Deucher78c55602011-11-17 14:25:56 -0500667 u32 ptr_reg_shift;
668 u32 ptr_reg_mask;
669 u32 nop;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200670};
671
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500672/*
Jerome Glisse721604a2012-01-05 22:11:05 -0500673 * VM
674 */
675struct radeon_vm {
676 struct list_head list;
677 struct list_head va;
678 int id;
679 unsigned last_pfn;
680 u64 pt_gpu_addr;
681 u64 *pt;
682 struct radeon_sa_bo sa_bo;
683 struct mutex mutex;
684 /* last fence for cs using this vm */
685 struct radeon_fence *fence;
686};
687
688struct radeon_vm_funcs {
689 int (*init)(struct radeon_device *rdev);
690 void (*fini)(struct radeon_device *rdev);
691 /* cs mutex must be lock for schedule_ib */
692 int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id);
693 void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm);
694 void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm);
695 uint32_t (*page_flags)(struct radeon_device *rdev,
696 struct radeon_vm *vm,
697 uint32_t flags);
698 void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm,
699 unsigned pfn, uint64_t addr, uint32_t flags);
700};
701
702struct radeon_vm_manager {
703 struct list_head lru_vm;
704 uint32_t use_bitmap;
705 struct radeon_sa_manager sa_manager;
706 uint32_t max_pfn;
707 /* fields constant after init */
708 const struct radeon_vm_funcs *funcs;
709 /* number of VMIDs */
710 unsigned nvm;
711 /* vram base address for page table entry */
712 u64 vram_base_offset;
Alex Deucher67e915e2012-01-06 09:38:15 -0500713 /* is vm enabled? */
714 bool enabled;
Jerome Glisse721604a2012-01-05 22:11:05 -0500715};
716
717/*
718 * file private structure
719 */
720struct radeon_fpriv {
721 struct radeon_vm vm;
722};
723
724/*
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500725 * R6xx+ IH ring
726 */
727struct r600_ih {
Jerome Glisse4c788672009-11-20 14:29:23 +0100728 struct radeon_bo *ring_obj;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500729 volatile uint32_t *ring;
730 unsigned rptr;
Christian Königbf852792011-10-13 13:19:22 +0200731 unsigned rptr_offs;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500732 unsigned wptr;
733 unsigned wptr_old;
734 unsigned ring_size;
735 uint64_t gpu_addr;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500736 uint32_t ptr_mask;
737 spinlock_t lock;
738 bool enabled;
739};
740
Ilija Hadzic8eec9d62011-10-12 23:29:40 -0400741struct r600_blit_cp_primitives {
742 void (*set_render_target)(struct radeon_device *rdev, int format,
743 int w, int h, u64 gpu_addr);
744 void (*cp_set_surface_sync)(struct radeon_device *rdev,
745 u32 sync_type, u32 size,
746 u64 mc_addr);
747 void (*set_shaders)(struct radeon_device *rdev);
748 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
749 void (*set_tex_resource)(struct radeon_device *rdev,
750 int format, int w, int h, int pitch,
Alex Deucher9bb77032011-10-22 10:07:09 -0400751 u64 gpu_addr, u32 size);
Ilija Hadzic8eec9d62011-10-12 23:29:40 -0400752 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
753 int x2, int y2);
754 void (*draw_auto)(struct radeon_device *rdev);
755 void (*set_default_state)(struct radeon_device *rdev);
756};
757
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000758struct r600_blit {
Jerome Glisseff82f052010-01-22 15:19:00 +0100759 struct mutex mutex;
Jerome Glisse4c788672009-11-20 14:29:23 +0100760 struct radeon_bo *shader_obj;
Ilija Hadzic8eec9d62011-10-12 23:29:40 -0400761 struct r600_blit_cp_primitives primitives;
762 int max_dim;
763 int ring_size_common;
764 int ring_size_per_loop;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000765 u64 shader_gpu_addr;
766 u32 vs_offset, ps_offset;
767 u32 state_offset;
768 u32 state_len;
769 u32 vb_used, vb_total;
770 struct radeon_ib *vb_ib;
771};
772
Alex Deucher6ddddfe2011-10-14 10:51:22 -0400773void r600_blit_suspend(struct radeon_device *rdev);
774
Alex Deucher347e7592012-03-20 17:18:21 -0400775/*
776 * SI RLC stuff
777 */
778struct si_rlc {
779 /* for power gating */
780 struct radeon_bo *save_restore_obj;
781 uint64_t save_restore_gpu_addr;
782 /* for clear state */
783 struct radeon_bo *clear_state_obj;
784 uint64_t clear_state_gpu_addr;
785};
786
Jerome Glisse69e130a2011-12-21 12:13:46 -0500787int radeon_ib_get(struct radeon_device *rdev, int ring,
788 struct radeon_ib **ib, unsigned size);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200789void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
Jerome Glissec1341e52011-12-21 12:13:47 -0500790bool radeon_ib_try_free(struct radeon_device *rdev, struct radeon_ib *ib);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200791int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
792int radeon_ib_pool_init(struct radeon_device *rdev);
793void radeon_ib_pool_fini(struct radeon_device *rdev);
Jerome Glisseb15ba512011-11-15 11:48:34 -0500794int radeon_ib_pool_start(struct radeon_device *rdev);
795int radeon_ib_pool_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200796/* Ring access between begin & end cannot sleep */
Christian Könige32eb502011-10-23 12:56:27 +0200797int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *cp);
798void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
799int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
800int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
801void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
802void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
803void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
804int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
805int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
Alex Deucher78c55602011-11-17 14:25:56 -0500806 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
807 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
Christian Könige32eb502011-10-23 12:56:27 +0200808void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200809
810
811/*
812 * CS.
813 */
814struct radeon_cs_reloc {
815 struct drm_gem_object *gobj;
Jerome Glisse4c788672009-11-20 14:29:23 +0100816 struct radeon_bo *robj;
817 struct radeon_bo_list lobj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200818 uint32_t handle;
819 uint32_t flags;
820};
821
822struct radeon_cs_chunk {
823 uint32_t chunk_id;
824 uint32_t length_dw;
Jerome Glisse721604a2012-01-05 22:11:05 -0500825 int kpage_idx[2];
826 uint32_t *kpage[2];
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200827 uint32_t *kdata;
Jerome Glisse721604a2012-01-05 22:11:05 -0500828 void __user *user_ptr;
829 int last_copied_page;
830 int last_page_index;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200831};
832
833struct radeon_cs_parser {
Jerome Glissec8c15ff2010-01-18 13:01:36 +0100834 struct device *dev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200835 struct radeon_device *rdev;
836 struct drm_file *filp;
837 /* chunks */
838 unsigned nchunks;
839 struct radeon_cs_chunk *chunks;
840 uint64_t *chunks_array;
841 /* IB */
842 unsigned idx;
843 /* relocations */
844 unsigned nrelocs;
845 struct radeon_cs_reloc *relocs;
846 struct radeon_cs_reloc **relocs_ptr;
847 struct list_head validated;
848 /* indices of various chunks */
849 int chunk_ib_idx;
850 int chunk_relocs_idx;
Jerome Glisse721604a2012-01-05 22:11:05 -0500851 int chunk_flags_idx;
Alex Deucherdfcf5f32012-03-20 17:18:14 -0400852 int chunk_const_ib_idx;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200853 struct radeon_ib *ib;
Alex Deucherdfcf5f32012-03-20 17:18:14 -0400854 struct radeon_ib *const_ib;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200855 void *track;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000856 unsigned family;
Marek Olšáke70f2242011-10-25 01:38:45 +0200857 int parser_error;
Jerome Glisse721604a2012-01-05 22:11:05 -0500858 u32 cs_flags;
859 u32 ring;
860 s32 priority;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200861};
862
Dave Airlie513bcb42009-09-23 16:56:27 +1000863extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
864extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
Andi Kleence580fa2011-10-13 16:08:47 -0700865extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
Dave Airlie513bcb42009-09-23 16:56:27 +1000866
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200867struct radeon_cs_packet {
868 unsigned idx;
869 unsigned type;
870 unsigned reg;
871 unsigned opcode;
872 int count;
873 unsigned one_reg_wr;
874};
875
876typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
877 struct radeon_cs_packet *pkt,
878 unsigned idx, unsigned reg);
879typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
880 struct radeon_cs_packet *pkt);
881
882
883/*
884 * AGP
885 */
886int radeon_agp_init(struct radeon_device *rdev);
Dave Airlie0ebf1712009-11-05 15:39:10 +1000887void radeon_agp_resume(struct radeon_device *rdev);
Jerome Glisse10b06122010-05-21 18:48:54 +0200888void radeon_agp_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200889void radeon_agp_fini(struct radeon_device *rdev);
890
891
892/*
893 * Writeback
894 */
895struct radeon_wb {
Jerome Glisse4c788672009-11-20 14:29:23 +0100896 struct radeon_bo *wb_obj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200897 volatile uint32_t *wb;
898 uint64_t gpu_addr;
Alex Deucher724c80e2010-08-27 18:25:25 -0400899 bool enabled;
Alex Deucherd0f8a852010-09-04 05:04:34 -0400900 bool use_event;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200901};
902
Alex Deucher724c80e2010-08-27 18:25:25 -0400903#define RADEON_WB_SCRATCH_OFFSET 0
904#define RADEON_WB_CP_RPTR_OFFSET 1024
Alex Deucher0c88a022011-03-02 20:07:31 -0500905#define RADEON_WB_CP1_RPTR_OFFSET 1280
906#define RADEON_WB_CP2_RPTR_OFFSET 1536
Alex Deucher724c80e2010-08-27 18:25:25 -0400907#define R600_WB_IH_WPTR_OFFSET 2048
Alex Deucherd0f8a852010-09-04 05:04:34 -0400908#define R600_WB_EVENT_OFFSET 3072
Alex Deucher724c80e2010-08-27 18:25:25 -0400909
Jerome Glissec93bb852009-07-13 21:04:08 +0200910/**
911 * struct radeon_pm - power management datas
912 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
913 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
914 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
915 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
916 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
917 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
918 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
919 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
920 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300921 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
Jerome Glissec93bb852009-07-13 21:04:08 +0200922 * @needed_bandwidth: current bandwidth needs
923 *
924 * It keeps track of various data needed to take powermanagement decision.
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300925 * Bandwidth need is used to determine minimun clock of the GPU and memory.
Jerome Glissec93bb852009-07-13 21:04:08 +0200926 * Equation between gpu/memory clock and available bandwidth is hw dependent
927 * (type of memory, bus size, efficiency, ...)
928 */
Alex Deucherce8f5372010-05-07 15:10:16 -0400929
930enum radeon_pm_method {
931 PM_METHOD_PROFILE,
932 PM_METHOD_DYNPM,
Rafał Miłeckic913e232009-12-22 23:02:16 +0100933};
Alex Deucherce8f5372010-05-07 15:10:16 -0400934
935enum radeon_dynpm_state {
936 DYNPM_STATE_DISABLED,
937 DYNPM_STATE_MINIMUM,
938 DYNPM_STATE_PAUSED,
Rafael J. Wysocki3f53eb62010-06-17 23:02:27 +0000939 DYNPM_STATE_ACTIVE,
940 DYNPM_STATE_SUSPENDED,
Alex Deucherce8f5372010-05-07 15:10:16 -0400941};
942enum radeon_dynpm_action {
943 DYNPM_ACTION_NONE,
944 DYNPM_ACTION_MINIMUM,
945 DYNPM_ACTION_DOWNCLOCK,
946 DYNPM_ACTION_UPCLOCK,
947 DYNPM_ACTION_DEFAULT
Rafał Miłeckic913e232009-12-22 23:02:16 +0100948};
Alex Deucher56278a82009-12-28 13:58:44 -0500949
950enum radeon_voltage_type {
951 VOLTAGE_NONE = 0,
952 VOLTAGE_GPIO,
953 VOLTAGE_VDDC,
954 VOLTAGE_SW
955};
956
Alex Deucher0ec0e742009-12-23 13:21:58 -0500957enum radeon_pm_state_type {
958 POWER_STATE_TYPE_DEFAULT,
959 POWER_STATE_TYPE_POWERSAVE,
960 POWER_STATE_TYPE_BATTERY,
961 POWER_STATE_TYPE_BALANCED,
962 POWER_STATE_TYPE_PERFORMANCE,
963};
964
Alex Deucherce8f5372010-05-07 15:10:16 -0400965enum radeon_pm_profile_type {
966 PM_PROFILE_DEFAULT,
967 PM_PROFILE_AUTO,
968 PM_PROFILE_LOW,
Alex Deucherc9e75b22010-06-02 17:56:01 -0400969 PM_PROFILE_MID,
Alex Deucherce8f5372010-05-07 15:10:16 -0400970 PM_PROFILE_HIGH,
971};
972
973#define PM_PROFILE_DEFAULT_IDX 0
974#define PM_PROFILE_LOW_SH_IDX 1
Alex Deucherc9e75b22010-06-02 17:56:01 -0400975#define PM_PROFILE_MID_SH_IDX 2
976#define PM_PROFILE_HIGH_SH_IDX 3
977#define PM_PROFILE_LOW_MH_IDX 4
978#define PM_PROFILE_MID_MH_IDX 5
979#define PM_PROFILE_HIGH_MH_IDX 6
980#define PM_PROFILE_MAX 7
Alex Deucherce8f5372010-05-07 15:10:16 -0400981
982struct radeon_pm_profile {
983 int dpms_off_ps_idx;
984 int dpms_on_ps_idx;
985 int dpms_off_cm_idx;
986 int dpms_on_cm_idx;
Alex Deucher516d0e42009-12-23 14:28:05 -0500987};
988
Alex Deucher21a81222010-07-02 12:58:16 -0400989enum radeon_int_thermal_type {
990 THERMAL_TYPE_NONE,
991 THERMAL_TYPE_RV6XX,
992 THERMAL_TYPE_RV770,
993 THERMAL_TYPE_EVERGREEN,
Alex Deuchere33df252010-11-22 17:56:32 -0500994 THERMAL_TYPE_SUMO,
Alex Deucher4fddba12011-01-06 21:19:22 -0500995 THERMAL_TYPE_NI,
Alex Deucher14607d02012-03-20 17:18:09 -0400996 THERMAL_TYPE_SI,
Alex Deucher21a81222010-07-02 12:58:16 -0400997};
998
Alex Deucher56278a82009-12-28 13:58:44 -0500999struct radeon_voltage {
1000 enum radeon_voltage_type type;
1001 /* gpio voltage */
1002 struct radeon_gpio_rec gpio;
1003 u32 delay; /* delay in usec from voltage drop to sclk change */
1004 bool active_high; /* voltage drop is active when bit is high */
1005 /* VDDC voltage */
1006 u8 vddc_id; /* index into vddc voltage table */
1007 u8 vddci_id; /* index into vddci voltage table */
1008 bool vddci_enabled;
1009 /* r6xx+ sw */
Alex Deucher2feea492011-04-12 14:49:24 -04001010 u16 voltage;
1011 /* evergreen+ vddci */
1012 u16 vddci;
Alex Deucher56278a82009-12-28 13:58:44 -05001013};
1014
Alex Deucherd7311172010-05-03 01:13:14 -04001015/* clock mode flags */
1016#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1017
Alex Deucher56278a82009-12-28 13:58:44 -05001018struct radeon_pm_clock_info {
1019 /* memory clock */
1020 u32 mclk;
1021 /* engine clock */
1022 u32 sclk;
1023 /* voltage info */
1024 struct radeon_voltage voltage;
Alex Deucherd7311172010-05-03 01:13:14 -04001025 /* standardized clock flags */
Alex Deucher56278a82009-12-28 13:58:44 -05001026 u32 flags;
1027};
1028
Alex Deuchera48b9b42010-04-22 14:03:55 -04001029/* state flags */
Alex Deucherd7311172010-05-03 01:13:14 -04001030#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
Alex Deuchera48b9b42010-04-22 14:03:55 -04001031
Alex Deucher56278a82009-12-28 13:58:44 -05001032struct radeon_power_state {
Alex Deucher0ec0e742009-12-23 13:21:58 -05001033 enum radeon_pm_state_type type;
Alex Deucher8f3f1c92011-11-04 10:09:43 -04001034 struct radeon_pm_clock_info *clock_info;
Alex Deucher56278a82009-12-28 13:58:44 -05001035 /* number of valid clock modes in this power state */
1036 int num_clock_modes;
Alex Deucher56278a82009-12-28 13:58:44 -05001037 struct radeon_pm_clock_info *default_clock_mode;
Alex Deuchera48b9b42010-04-22 14:03:55 -04001038 /* standardized state flags */
1039 u32 flags;
Alex Deucher79daedc2010-04-22 14:25:19 -04001040 u32 misc; /* vbios specific flags */
1041 u32 misc2; /* vbios specific flags */
1042 int pcie_lanes; /* pcie lanes */
Alex Deucher56278a82009-12-28 13:58:44 -05001043};
1044
Rafał Miłecki27459322010-02-11 22:16:36 +00001045/*
1046 * Some modes are overclocked by very low value, accept them
1047 */
1048#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1049
Jerome Glissec93bb852009-07-13 21:04:08 +02001050struct radeon_pm {
Rafał Miłeckic913e232009-12-22 23:02:16 +01001051 struct mutex mutex;
Alex Deuchera48b9b42010-04-22 14:03:55 -04001052 u32 active_crtcs;
1053 int active_crtc_count;
Rafał Miłeckic913e232009-12-22 23:02:16 +01001054 int req_vblank;
Rafał Miłecki839461d2010-03-02 22:06:51 +01001055 bool vblank_sync;
Alex Deucher2031f772010-04-22 12:52:11 -04001056 bool gui_idle;
Jerome Glissec93bb852009-07-13 21:04:08 +02001057 fixed20_12 max_bandwidth;
1058 fixed20_12 igp_sideport_mclk;
1059 fixed20_12 igp_system_mclk;
1060 fixed20_12 igp_ht_link_clk;
1061 fixed20_12 igp_ht_link_width;
1062 fixed20_12 k8_bandwidth;
1063 fixed20_12 sideport_bandwidth;
1064 fixed20_12 ht_bandwidth;
1065 fixed20_12 core_bandwidth;
1066 fixed20_12 sclk;
Alex Deucherf47299c2010-03-16 20:54:38 -04001067 fixed20_12 mclk;
Jerome Glissec93bb852009-07-13 21:04:08 +02001068 fixed20_12 needed_bandwidth;
Alex Deucher0975b162011-02-02 18:42:03 -05001069 struct radeon_power_state *power_state;
Alex Deucher56278a82009-12-28 13:58:44 -05001070 /* number of valid power states */
1071 int num_power_states;
Alex Deuchera48b9b42010-04-22 14:03:55 -04001072 int current_power_state_index;
1073 int current_clock_mode_index;
1074 int requested_power_state_index;
1075 int requested_clock_mode_index;
1076 int default_power_state_index;
1077 u32 current_sclk;
1078 u32 current_mclk;
Alex Deucher2feea492011-04-12 14:49:24 -04001079 u16 current_vddc;
1080 u16 current_vddci;
Alex Deucher9ace9f72011-01-06 21:19:26 -05001081 u32 default_sclk;
1082 u32 default_mclk;
Alex Deucher2feea492011-04-12 14:49:24 -04001083 u16 default_vddc;
1084 u16 default_vddci;
Alex Deucher29fb52c2010-03-11 10:01:17 -05001085 struct radeon_i2c_chan *i2c_bus;
Alex Deucherce8f5372010-05-07 15:10:16 -04001086 /* selected pm method */
1087 enum radeon_pm_method pm_method;
1088 /* dynpm power management */
1089 struct delayed_work dynpm_idle_work;
1090 enum radeon_dynpm_state dynpm_state;
1091 enum radeon_dynpm_action dynpm_planned_action;
1092 unsigned long dynpm_action_timeout;
1093 bool dynpm_can_upclock;
1094 bool dynpm_can_downclock;
1095 /* profile-based power management */
1096 enum radeon_pm_profile_type profile;
1097 int profile_index;
1098 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
Alex Deucher21a81222010-07-02 12:58:16 -04001099 /* internal thermal controller on rv6xx+ */
1100 enum radeon_int_thermal_type int_thermal_type;
1101 struct device *int_hwmon_dev;
Jerome Glissec93bb852009-07-13 21:04:08 +02001102};
1103
Alex Deuchera4c9e2e2011-11-04 10:09:41 -04001104int radeon_pm_get_type_index(struct radeon_device *rdev,
1105 enum radeon_pm_state_type ps_type,
1106 int instance);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001107
1108/*
1109 * Benchmarking
1110 */
Ilija Hadzic638dd7d2011-10-12 23:29:39 -04001111void radeon_benchmark(struct radeon_device *rdev, int test_number);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001112
1113
1114/*
Michel Dänzerecc0b322009-07-21 11:23:57 +02001115 * Testing
1116 */
1117void radeon_test_moves(struct radeon_device *rdev);
Christian König60a7e392011-09-27 12:31:00 +02001118void radeon_test_ring_sync(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +02001119 struct radeon_ring *cpA,
1120 struct radeon_ring *cpB);
Christian König60a7e392011-09-27 12:31:00 +02001121void radeon_test_syncing(struct radeon_device *rdev);
Michel Dänzerecc0b322009-07-21 11:23:57 +02001122
1123
1124/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001125 * Debugfs
1126 */
Christian König4d8bf9a2011-10-24 14:54:54 +02001127struct radeon_debugfs {
1128 struct drm_info_list *files;
1129 unsigned num_files;
1130};
1131
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001132int radeon_debugfs_add_files(struct radeon_device *rdev,
1133 struct drm_info_list *files,
1134 unsigned nfiles);
1135int radeon_debugfs_fence_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001136
1137
1138/*
1139 * ASIC specific functions.
1140 */
1141struct radeon_asic {
Jerome Glisse068a1172009-06-17 13:28:30 +02001142 int (*init)(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001143 void (*fini)(struct radeon_device *rdev);
1144 int (*resume)(struct radeon_device *rdev);
1145 int (*suspend)(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +10001146 void (*vga_set_state)(struct radeon_device *rdev, bool state);
Christian Könige32eb502011-10-23 12:56:27 +02001147 bool (*gpu_is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +00001148 int (*asic_reset)(struct radeon_device *rdev);
Alex Deucher54e88e02012-02-23 18:10:29 -05001149 /* ioctl hw specific callback. Some hw might want to perform special
1150 * operation on specific ioctl. For instance on wait idle some hw
1151 * might want to perform and HDP flush through MMIO as it seems that
1152 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1153 * through ring.
1154 */
1155 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1156 /* check if 3D engine is idle */
1157 bool (*gui_idle)(struct radeon_device *rdev);
1158 /* wait for mc_idle */
1159 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1160 /* gart */
Alex Deucherc5b3b852012-02-23 17:53:46 -05001161 struct {
1162 void (*tlb_flush)(struct radeon_device *rdev);
1163 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1164 } gart;
Alex Deucher54e88e02012-02-23 18:10:29 -05001165 /* ring specific callbacks */
Christian König4c87bc22011-10-19 19:02:21 +02001166 struct {
1167 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
Jerome Glisse721604a2012-01-05 22:11:05 -05001168 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
Christian König4c87bc22011-10-19 19:02:21 +02001169 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
Christian Könige32eb502011-10-23 12:56:27 +02001170 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
Christian König4c87bc22011-10-19 19:02:21 +02001171 struct radeon_semaphore *semaphore, bool emit_wait);
Christian Königeb0c19c2012-02-23 15:18:44 +01001172 int (*cs_parse)(struct radeon_cs_parser *p);
Alex Deucherf7128122012-02-23 17:53:45 -05001173 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1174 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1175 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
Christian König4c87bc22011-10-19 19:02:21 +02001176 } ring[RADEON_NUM_RINGS];
Alex Deucher54e88e02012-02-23 18:10:29 -05001177 /* irqs */
Alex Deucherb35ea4a2012-02-23 17:53:43 -05001178 struct {
1179 int (*set)(struct radeon_device *rdev);
1180 int (*process)(struct radeon_device *rdev);
1181 } irq;
Alex Deucher54e88e02012-02-23 18:10:29 -05001182 /* displays */
Alex Deucherc79a49c2012-02-23 17:53:47 -05001183 struct {
1184 /* display watermarks */
1185 void (*bandwidth_update)(struct radeon_device *rdev);
1186 /* get frame count */
1187 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1188 /* wait for vblank */
1189 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1190 } display;
Alex Deucher54e88e02012-02-23 18:10:29 -05001191 /* copy functions for bo handling */
Alex Deucher27cd7762012-02-23 17:53:42 -05001192 struct {
1193 int (*blit)(struct radeon_device *rdev,
1194 uint64_t src_offset,
1195 uint64_t dst_offset,
1196 unsigned num_gpu_pages,
1197 struct radeon_fence *fence);
1198 u32 blit_ring_index;
1199 int (*dma)(struct radeon_device *rdev,
1200 uint64_t src_offset,
1201 uint64_t dst_offset,
1202 unsigned num_gpu_pages,
1203 struct radeon_fence *fence);
1204 u32 dma_ring_index;
1205 /* method used for bo copy */
1206 int (*copy)(struct radeon_device *rdev,
1207 uint64_t src_offset,
1208 uint64_t dst_offset,
1209 unsigned num_gpu_pages,
1210 struct radeon_fence *fence);
1211 /* ring used for bo copies */
1212 u32 copy_ring_index;
1213 } copy;
Alex Deucher54e88e02012-02-23 18:10:29 -05001214 /* surfaces */
Alex Deucher9e6f3d02012-02-23 17:53:49 -05001215 struct {
1216 int (*set_reg)(struct radeon_device *rdev, int reg,
1217 uint32_t tiling_flags, uint32_t pitch,
1218 uint32_t offset, uint32_t obj_size);
1219 void (*clear_reg)(struct radeon_device *rdev, int reg);
1220 } surface;
Alex Deucher54e88e02012-02-23 18:10:29 -05001221 /* hotplug detect */
Alex Deucher901ea572012-02-23 17:53:39 -05001222 struct {
1223 void (*init)(struct radeon_device *rdev);
1224 void (*fini)(struct radeon_device *rdev);
1225 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1226 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1227 } hpd;
Alex Deucherce8f5372010-05-07 15:10:16 -04001228 /* power management */
Alex Deuchera02fa392012-02-23 17:53:41 -05001229 struct {
1230 void (*misc)(struct radeon_device *rdev);
1231 void (*prepare)(struct radeon_device *rdev);
1232 void (*finish)(struct radeon_device *rdev);
1233 void (*init_profile)(struct radeon_device *rdev);
1234 void (*get_dynpm_state)(struct radeon_device *rdev);
Alex Deucher798bcf72012-02-23 17:53:48 -05001235 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1236 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1237 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1238 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1239 int (*get_pcie_lanes)(struct radeon_device *rdev);
1240 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1241 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
Alex Deuchera02fa392012-02-23 17:53:41 -05001242 } pm;
Alex Deucher6f34be52010-11-21 10:59:01 -05001243 /* pageflipping */
Alex Deucher0f9e0062012-02-23 17:53:40 -05001244 struct {
1245 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1246 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1247 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1248 } pflip;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001249};
1250
Jerome Glisse21f9a432009-09-11 15:55:33 +02001251/*
1252 * Asic structures
1253 */
Jerome Glisse225758d2010-03-09 14:45:10 +00001254struct r100_gpu_lockup {
1255 unsigned long last_jiffies;
1256 u32 last_cp_rptr;
1257};
1258
Dave Airlie551ebd82009-09-01 15:25:57 +10001259struct r100_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001260 const unsigned *reg_safe_bm;
1261 unsigned reg_safe_bm_size;
1262 u32 hdp_cntl;
1263 struct r100_gpu_lockup lockup;
Dave Airlie551ebd82009-09-01 15:25:57 +10001264};
1265
Jerome Glisse21f9a432009-09-11 15:55:33 +02001266struct r300_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001267 const unsigned *reg_safe_bm;
1268 unsigned reg_safe_bm_size;
1269 u32 resync_scratch;
1270 u32 hdp_cntl;
1271 struct r100_gpu_lockup lockup;
Jerome Glisse21f9a432009-09-11 15:55:33 +02001272};
1273
1274struct r600_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001275 unsigned max_pipes;
1276 unsigned max_tile_pipes;
1277 unsigned max_simds;
1278 unsigned max_backends;
1279 unsigned max_gprs;
1280 unsigned max_threads;
1281 unsigned max_stack_entries;
1282 unsigned max_hw_contexts;
1283 unsigned max_gs_threads;
1284 unsigned sx_max_export_size;
1285 unsigned sx_max_export_pos_size;
1286 unsigned sx_max_export_smx_size;
1287 unsigned sq_num_cf_insts;
1288 unsigned tiling_nbanks;
1289 unsigned tiling_npipes;
1290 unsigned tiling_group_size;
Alex Deuchere7aeeba2010-06-04 13:10:12 -04001291 unsigned tile_config;
Alex Deuchere55b9422011-07-15 19:53:52 +00001292 unsigned backend_map;
Jerome Glisse225758d2010-03-09 14:45:10 +00001293 struct r100_gpu_lockup lockup;
Jerome Glisse21f9a432009-09-11 15:55:33 +02001294};
1295
1296struct rv770_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001297 unsigned max_pipes;
1298 unsigned max_tile_pipes;
1299 unsigned max_simds;
1300 unsigned max_backends;
1301 unsigned max_gprs;
1302 unsigned max_threads;
1303 unsigned max_stack_entries;
1304 unsigned max_hw_contexts;
1305 unsigned max_gs_threads;
1306 unsigned sx_max_export_size;
1307 unsigned sx_max_export_pos_size;
1308 unsigned sx_max_export_smx_size;
1309 unsigned sq_num_cf_insts;
1310 unsigned sx_num_of_sets;
1311 unsigned sc_prim_fifo_size;
1312 unsigned sc_hiz_tile_fifo_size;
1313 unsigned sc_earlyz_tile_fifo_fize;
1314 unsigned tiling_nbanks;
1315 unsigned tiling_npipes;
1316 unsigned tiling_group_size;
Alex Deuchere7aeeba2010-06-04 13:10:12 -04001317 unsigned tile_config;
Alex Deuchere55b9422011-07-15 19:53:52 +00001318 unsigned backend_map;
Jerome Glisse225758d2010-03-09 14:45:10 +00001319 struct r100_gpu_lockup lockup;
Jerome Glisse21f9a432009-09-11 15:55:33 +02001320};
1321
Alex Deucher32fcdbf2010-03-24 13:33:47 -04001322struct evergreen_asic {
1323 unsigned num_ses;
1324 unsigned max_pipes;
1325 unsigned max_tile_pipes;
1326 unsigned max_simds;
1327 unsigned max_backends;
1328 unsigned max_gprs;
1329 unsigned max_threads;
1330 unsigned max_stack_entries;
1331 unsigned max_hw_contexts;
1332 unsigned max_gs_threads;
1333 unsigned sx_max_export_size;
1334 unsigned sx_max_export_pos_size;
1335 unsigned sx_max_export_smx_size;
1336 unsigned sq_num_cf_insts;
1337 unsigned sx_num_of_sets;
1338 unsigned sc_prim_fifo_size;
1339 unsigned sc_hiz_tile_fifo_size;
1340 unsigned sc_earlyz_tile_fifo_size;
1341 unsigned tiling_nbanks;
1342 unsigned tiling_npipes;
1343 unsigned tiling_group_size;
Alex Deuchere7aeeba2010-06-04 13:10:12 -04001344 unsigned tile_config;
Alex Deuchere55b9422011-07-15 19:53:52 +00001345 unsigned backend_map;
Alex Deucher17db7042010-12-21 16:05:39 -05001346 struct r100_gpu_lockup lockup;
Alex Deucher32fcdbf2010-03-24 13:33:47 -04001347};
1348
Alex Deucherfecf1d02011-03-02 20:07:29 -05001349struct cayman_asic {
1350 unsigned max_shader_engines;
1351 unsigned max_pipes_per_simd;
1352 unsigned max_tile_pipes;
1353 unsigned max_simds_per_se;
1354 unsigned max_backends_per_se;
1355 unsigned max_texture_channel_caches;
1356 unsigned max_gprs;
1357 unsigned max_threads;
1358 unsigned max_gs_threads;
1359 unsigned max_stack_entries;
1360 unsigned sx_num_of_sets;
1361 unsigned sx_max_export_size;
1362 unsigned sx_max_export_pos_size;
1363 unsigned sx_max_export_smx_size;
1364 unsigned max_hw_contexts;
1365 unsigned sq_num_cf_insts;
1366 unsigned sc_prim_fifo_size;
1367 unsigned sc_hiz_tile_fifo_size;
1368 unsigned sc_earlyz_tile_fifo_size;
1369
1370 unsigned num_shader_engines;
1371 unsigned num_shader_pipes_per_simd;
1372 unsigned num_tile_pipes;
1373 unsigned num_simds_per_se;
1374 unsigned num_backends_per_se;
1375 unsigned backend_disable_mask_per_asic;
1376 unsigned backend_map;
1377 unsigned num_texture_channel_caches;
1378 unsigned mem_max_burst_length_bytes;
1379 unsigned mem_row_size_in_kb;
1380 unsigned shader_engine_tile_size;
1381 unsigned num_gpus;
1382 unsigned multi_gpu_tile_size;
1383
1384 unsigned tile_config;
1385 struct r100_gpu_lockup lockup;
1386};
1387
Alex Deucher0a96d722012-03-20 17:18:11 -04001388struct si_asic {
1389 unsigned max_shader_engines;
1390 unsigned max_pipes_per_simd;
1391 unsigned max_tile_pipes;
1392 unsigned max_simds_per_se;
1393 unsigned max_backends_per_se;
1394 unsigned max_texture_channel_caches;
1395 unsigned max_gprs;
1396 unsigned max_gs_threads;
1397 unsigned max_hw_contexts;
1398 unsigned sc_prim_fifo_size_frontend;
1399 unsigned sc_prim_fifo_size_backend;
1400 unsigned sc_hiz_tile_fifo_size;
1401 unsigned sc_earlyz_tile_fifo_size;
1402
1403 unsigned num_shader_engines;
1404 unsigned num_tile_pipes;
1405 unsigned num_backends_per_se;
1406 unsigned backend_disable_mask_per_asic;
1407 unsigned backend_map;
1408 unsigned num_texture_channel_caches;
1409 unsigned mem_max_burst_length_bytes;
1410 unsigned mem_row_size_in_kb;
1411 unsigned shader_engine_tile_size;
1412 unsigned num_gpus;
1413 unsigned multi_gpu_tile_size;
1414
1415 unsigned tile_config;
1416 struct r100_gpu_lockup lockup;
1417};
1418
Jerome Glisse068a1172009-06-17 13:28:30 +02001419union radeon_asic_config {
1420 struct r300_asic r300;
Dave Airlie551ebd82009-09-01 15:25:57 +10001421 struct r100_asic r100;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001422 struct r600_asic r600;
1423 struct rv770_asic rv770;
Alex Deucher32fcdbf2010-03-24 13:33:47 -04001424 struct evergreen_asic evergreen;
Alex Deucherfecf1d02011-03-02 20:07:29 -05001425 struct cayman_asic cayman;
Alex Deucher0a96d722012-03-20 17:18:11 -04001426 struct si_asic si;
Jerome Glisse068a1172009-06-17 13:28:30 +02001427};
1428
Daniel Vetter0a10c852010-03-11 21:19:14 +00001429/*
1430 * asic initizalization from radeon_asic.c
1431 */
1432void radeon_agp_disable(struct radeon_device *rdev);
1433int radeon_asic_init(struct radeon_device *rdev);
1434
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001435
1436/*
1437 * IOCTL.
1438 */
1439int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1440 struct drm_file *filp);
1441int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1442 struct drm_file *filp);
1443int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1444 struct drm_file *file_priv);
1445int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1446 struct drm_file *file_priv);
1447int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1448 struct drm_file *file_priv);
1449int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1450 struct drm_file *file_priv);
1451int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1452 struct drm_file *filp);
1453int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1454 struct drm_file *filp);
1455int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1456 struct drm_file *filp);
1457int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1458 struct drm_file *filp);
Jerome Glisse721604a2012-01-05 22:11:05 -05001459int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1460 struct drm_file *filp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001461int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
Dave Airliee024e112009-06-24 09:48:08 +10001462int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1463 struct drm_file *filp);
1464int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1465 struct drm_file *filp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001466
Alex Deucher16cdf042011-10-28 10:30:02 -04001467/* VRAM scratch page for HDP bug, default vram page */
1468struct r600_vram_scratch {
Alex Deucher87cbf8f2010-08-27 13:59:54 -04001469 struct radeon_bo *robj;
1470 volatile uint32_t *ptr;
Alex Deucher16cdf042011-10-28 10:30:02 -04001471 u64 gpu_addr;
Alex Deucher87cbf8f2010-08-27 13:59:54 -04001472};
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001473
Michel Dänzer7a1619b2011-11-10 18:57:26 +01001474
1475/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001476 * Core structure, functions and helpers.
1477 */
1478typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1479typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1480
1481struct radeon_device {
Jerome Glisse9f022dd2009-09-11 15:35:22 +02001482 struct device *dev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001483 struct drm_device *ddev;
1484 struct pci_dev *pdev;
1485 /* ASIC */
Jerome Glisse068a1172009-06-17 13:28:30 +02001486 union radeon_asic_config config;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001487 enum radeon_family family;
1488 unsigned long flags;
1489 int usec_timeout;
1490 enum radeon_pll_errata pll_errata;
1491 int num_gb_pipes;
Alex Deucherf779b3e2009-08-19 19:11:39 -04001492 int num_z_pipes;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001493 int disp_priority;
1494 /* BIOS */
1495 uint8_t *bios;
1496 bool is_atom_bios;
1497 uint16_t bios_header_start;
Jerome Glisse4c788672009-11-20 14:29:23 +01001498 struct radeon_bo *stollen_vga_memory;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001499 /* Register mmio */
Dave Airlie4c9bc752009-06-29 18:29:12 +10001500 resource_size_t rmmio_base;
1501 resource_size_t rmmio_size;
Benjamin Herrenschmidta0533fb2011-07-13 06:28:12 +00001502 void __iomem *rmmio;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001503 radeon_rreg_t mc_rreg;
1504 radeon_wreg_t mc_wreg;
1505 radeon_rreg_t pll_rreg;
1506 radeon_wreg_t pll_wreg;
Dave Airliede1b2892009-08-12 18:43:14 +10001507 uint32_t pcie_reg_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001508 radeon_rreg_t pciep_rreg;
1509 radeon_wreg_t pciep_wreg;
Alex Deucher351a52a2010-06-30 11:52:50 -04001510 /* io port */
1511 void __iomem *rio_mem;
1512 resource_size_t rio_mem_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001513 struct radeon_clock clock;
1514 struct radeon_mc mc;
1515 struct radeon_gart gart;
1516 struct radeon_mode_info mode_info;
1517 struct radeon_scratch scratch;
1518 struct radeon_mman mman;
Alex Deucher74652802011-08-25 13:39:48 -04001519 rwlock_t fence_lock;
1520 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
Christian König15d33322011-09-15 19:02:22 +02001521 struct radeon_semaphore_driver semaphore_drv;
Christian Könige32eb502011-10-23 12:56:27 +02001522 struct radeon_ring ring[RADEON_NUM_RINGS];
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001523 struct radeon_ib_pool ib_pool;
1524 struct radeon_irq irq;
1525 struct radeon_asic *asic;
1526 struct radeon_gem gem;
Jerome Glissec93bb852009-07-13 21:04:08 +02001527 struct radeon_pm pm;
Yang Zhaof657c2a2009-09-15 12:21:01 +10001528 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
Michel Dänzer7a1619b2011-11-10 18:57:26 +01001529 struct radeon_mutex cs_mutex;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001530 struct radeon_wb wb;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001531 struct radeon_dummy_page dummy_page;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001532 bool gpu_lockup;
1533 bool shutdown;
1534 bool suspend;
Dave Airliead49f502009-07-10 22:36:26 +10001535 bool need_dma32;
Jerome Glisse733289c2009-09-16 15:24:21 +02001536 bool accel_working;
Dave Airliee024e112009-06-24 09:48:08 +10001537 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001538 const struct firmware *me_fw; /* all family ME firmware */
1539 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001540 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
Alex Deucher0af62b02011-01-06 21:19:31 -05001541 const struct firmware *mc_fw; /* NI MC firmware */
Alex Deucher0f0de062012-03-20 17:18:17 -04001542 const struct firmware *ce_fw; /* SI CE firmware */
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001543 struct r600_blit r600_blit;
Alex Deucher16cdf042011-10-28 10:30:02 -04001544 struct r600_vram_scratch vram_scratch;
Alex Deucher3e5cb982009-10-16 12:21:24 -04001545 int msi_enabled; /* msi enabled */
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001546 struct r600_ih ih; /* r6/700 interrupt ring */
Alex Deucher347e7592012-03-20 17:18:21 -04001547 struct si_rlc rlc;
Alex Deucherd4877cf2009-12-04 16:56:37 -05001548 struct work_struct hotplug_work;
Alex Deucher18917b62010-02-01 16:02:25 -05001549 int num_crtc; /* number of crtcs */
Alex Deucher40bacf12009-12-23 03:23:21 -05001550 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
Matthew Garrett5876dd22010-04-26 15:52:20 -04001551 struct mutex vram_mutex;
Christian Koenigdafc3bd2009-10-11 23:49:13 +02001552
1553 /* audio stuff */
Rafał Miłecki7eea7e92010-06-19 12:24:56 +02001554 bool audio_enabled;
Christian Koenigdafc3bd2009-10-11 23:49:13 +02001555 struct timer_list audio_timer;
1556 int audio_channels;
1557 int audio_rate;
1558 int audio_bits_per_sample;
1559 uint8_t audio_status_bits;
1560 uint8_t audio_category_code;
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001561
Alex Deucherce8f5372010-05-07 15:10:16 -04001562 struct notifier_block acpi_nb;
Marek Olšák9eba4a92011-01-05 05:46:48 +01001563 /* only one userspace can use Hyperz features or CMASK at a time */
Dave Airlieab9e1f52010-07-13 11:11:11 +10001564 struct drm_file *hyperz_filp;
Marek Olšák9eba4a92011-01-05 05:46:48 +01001565 struct drm_file *cmask_filp;
Alex Deucherf376b942010-08-05 21:21:16 -04001566 /* i2c buses */
1567 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
Christian König4d8bf9a2011-10-24 14:54:54 +02001568 /* debugfs */
1569 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1570 unsigned debugfs_count;
Jerome Glisse721604a2012-01-05 22:11:05 -05001571 /* virtual memory */
1572 struct radeon_vm_manager vm_manager;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001573};
1574
1575int radeon_device_init(struct radeon_device *rdev,
1576 struct drm_device *ddev,
1577 struct pci_dev *pdev,
1578 uint32_t flags);
1579void radeon_device_fini(struct radeon_device *rdev);
1580int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1581
Andi Kleen6fcbef72011-10-13 16:08:42 -07001582uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1583void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1584u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1585void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
Alex Deucher351a52a2010-06-30 11:52:50 -04001586
Jerome Glisse4c788672009-11-20 14:29:23 +01001587/*
1588 * Cast helper
1589 */
1590#define to_radeon_fence(p) ((struct radeon_fence *)(p))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001591
1592/*
1593 * Registers read & write functions.
1594 */
Benjamin Herrenschmidta0533fb2011-07-13 06:28:12 +00001595#define RREG8(reg) readb((rdev->rmmio) + (reg))
1596#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1597#define RREG16(reg) readw((rdev->rmmio) + (reg))
1598#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
Dave Airliede1b2892009-08-12 18:43:14 +10001599#define RREG32(reg) r100_mm_rreg(rdev, (reg))
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001600#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
Dave Airliede1b2892009-08-12 18:43:14 +10001601#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001602#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1603#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1604#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1605#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1606#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1607#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
Dave Airliede1b2892009-08-12 18:43:14 +10001608#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1609#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
Rafał Miłeckiaa5120d2010-02-18 20:24:28 +00001610#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1611#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001612#define WREG32_P(reg, val, mask) \
1613 do { \
1614 uint32_t tmp_ = RREG32(reg); \
1615 tmp_ &= (mask); \
1616 tmp_ |= ((val) & ~(mask)); \
1617 WREG32(reg, tmp_); \
1618 } while (0)
1619#define WREG32_PLL_P(reg, val, mask) \
1620 do { \
1621 uint32_t tmp_ = RREG32_PLL(reg); \
1622 tmp_ &= (mask); \
1623 tmp_ |= ((val) & ~(mask)); \
1624 WREG32_PLL(reg, tmp_); \
1625 } while (0)
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001626#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
Alex Deucher351a52a2010-06-30 11:52:50 -04001627#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1628#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001629
Dave Airliede1b2892009-08-12 18:43:14 +10001630/*
1631 * Indirect registers accessor
1632 */
1633static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1634{
1635 uint32_t r;
1636
1637 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1638 r = RREG32(RADEON_PCIE_DATA);
1639 return r;
1640}
1641
1642static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1643{
1644 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1645 WREG32(RADEON_PCIE_DATA, (v));
1646}
1647
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001648void r100_pll_errata_after_index(struct radeon_device *rdev);
1649
1650
1651/*
1652 * ASICs helpers.
1653 */
Dave Airlieb995e432009-07-14 02:02:32 +10001654#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1655 (rdev->pdev->device == 0x5969))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001656#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1657 (rdev->family == CHIP_RV200) || \
1658 (rdev->family == CHIP_RS100) || \
1659 (rdev->family == CHIP_RS200) || \
1660 (rdev->family == CHIP_RV250) || \
1661 (rdev->family == CHIP_RV280) || \
1662 (rdev->family == CHIP_RS300))
1663#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1664 (rdev->family == CHIP_RV350) || \
1665 (rdev->family == CHIP_R350) || \
1666 (rdev->family == CHIP_RV380) || \
1667 (rdev->family == CHIP_R420) || \
1668 (rdev->family == CHIP_R423) || \
1669 (rdev->family == CHIP_RV410) || \
1670 (rdev->family == CHIP_RS400) || \
1671 (rdev->family == CHIP_RS480))
Alex Deucher3313e3d2011-01-06 18:49:34 -05001672#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1673 (rdev->ddev->pdev->device == 0x9443) || \
1674 (rdev->ddev->pdev->device == 0x944B) || \
1675 (rdev->ddev->pdev->device == 0x9506) || \
1676 (rdev->ddev->pdev->device == 0x9509) || \
1677 (rdev->ddev->pdev->device == 0x950F) || \
1678 (rdev->ddev->pdev->device == 0x689C) || \
1679 (rdev->ddev->pdev->device == 0x689D))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001680#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
Alex Deucher99999aa2010-11-16 12:09:41 -05001681#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1682 (rdev->family == CHIP_RS690) || \
1683 (rdev->family == CHIP_RS740) || \
1684 (rdev->family >= CHIP_R600))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001685#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1686#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
Alex Deucherbcc1c2a2010-01-12 17:54:34 -05001687#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
Alex Deucher633b9162011-01-06 21:19:11 -05001688#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1689 (rdev->flags & RADEON_IS_IGP))
Alex Deucher1fe18302011-01-06 21:19:12 -05001690#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
Alex Deucher8848f752012-03-20 17:18:28 -04001691#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1692#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1693 (rdev->flags & RADEON_IS_IGP))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001694
1695/*
1696 * BIOS helpers.
1697 */
1698#define RBIOS8(i) (rdev->bios[i])
1699#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1700#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1701
1702int radeon_combios_init(struct radeon_device *rdev);
1703void radeon_combios_fini(struct radeon_device *rdev);
1704int radeon_atombios_init(struct radeon_device *rdev);
1705void radeon_atombios_fini(struct radeon_device *rdev);
1706
1707
1708/*
1709 * RING helpers.
1710 */
Andi Kleence580fa2011-10-13 16:08:47 -07001711#if DRM_DEBUG_CODE == 0
Christian Könige32eb502011-10-23 12:56:27 +02001712static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001713{
Christian Könige32eb502011-10-23 12:56:27 +02001714 ring->ring[ring->wptr++] = v;
1715 ring->wptr &= ring->ptr_mask;
1716 ring->count_dw--;
1717 ring->ring_free_dw--;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001718}
Andi Kleence580fa2011-10-13 16:08:47 -07001719#else
1720/* With debugging this is just too big to inline */
Christian Könige32eb502011-10-23 12:56:27 +02001721void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
Andi Kleence580fa2011-10-13 16:08:47 -07001722#endif
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001723
1724/*
1725 * ASICs macro.
1726 */
Jerome Glisse068a1172009-06-17 13:28:30 +02001727#define radeon_init(rdev) (rdev)->asic->init((rdev))
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001728#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1729#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1730#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
Christian Königeb0c19c2012-02-23 15:18:44 +01001731#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
Dave Airlie28d52042009-09-21 14:33:58 +10001732#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
Christian König7b1f2482011-09-23 15:11:23 +02001733#define radeon_gpu_is_lockup(rdev, cp) (rdev)->asic->gpu_is_lockup((rdev), (cp))
Jerome Glissea2d07b72010-03-09 14:45:11 +00001734#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
Alex Deucherc5b3b852012-02-23 17:53:46 -05001735#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1736#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
Alex Deucherf7128122012-02-23 17:53:45 -05001737#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1738#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1739#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
Christian König4c87bc22011-10-19 19:02:21 +02001740#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
Jerome Glisse721604a2012-01-05 22:11:05 -05001741#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
Alex Deucherb35ea4a2012-02-23 17:53:43 -05001742#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1743#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
Alex Deucherc79a49c2012-02-23 17:53:47 -05001744#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
Christian König4c87bc22011-10-19 19:02:21 +02001745#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1746#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
Alex Deucher27cd7762012-02-23 17:53:42 -05001747#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1748#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1749#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1750#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1751#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1752#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
Alex Deucher798bcf72012-02-23 17:53:48 -05001753#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1754#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1755#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1756#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1757#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1758#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1759#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
Alex Deucher9e6f3d02012-02-23 17:53:49 -05001760#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1761#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
Alex Deucherc79a49c2012-02-23 17:53:47 -05001762#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
Alex Deucher901ea572012-02-23 17:53:39 -05001763#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1764#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1765#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1766#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
Alex Deucherdef9ba92010-04-22 12:39:58 -04001767#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
Alex Deuchera02fa392012-02-23 17:53:41 -05001768#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1769#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1770#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1771#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1772#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
Alex Deucher0f9e0062012-02-23 17:53:40 -05001773#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pflip.pre_page_flip((rdev), (crtc))
1774#define radeon_page_flip(rdev, crtc, base) rdev->asic->pflip.page_flip((rdev), (crtc), (base))
1775#define radeon_post_page_flip(rdev, crtc) rdev->asic->pflip.post_page_flip((rdev), (crtc))
Alex Deucherc79a49c2012-02-23 17:53:47 -05001776#define radeon_wait_for_vblank(rdev, crtc) rdev->asic->display.wait_for_vblank((rdev), (crtc))
Alex Deucher89e51812012-02-23 17:53:38 -05001777#define radeon_mc_wait_for_idle(rdev) rdev->asic->mc_wait_for_idle((rdev))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001778
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +02001779/* Common functions */
Jerome Glisse700a0cc2010-01-13 15:16:38 +01001780/* AGP */
Jerome Glisse90aca4d2010-03-09 14:45:12 +00001781extern int radeon_gpu_reset(struct radeon_device *rdev);
Jerome Glisse700a0cc2010-01-13 15:16:38 +01001782extern void radeon_agp_disable(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001783extern int radeon_modeset_init(struct radeon_device *rdev);
1784extern void radeon_modeset_fini(struct radeon_device *rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +02001785extern bool radeon_card_posted(struct radeon_device *rdev);
Alex Deucherf47299c2010-03-16 20:54:38 -04001786extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
Alex Deucherf46c0122010-03-31 00:33:27 -04001787extern void radeon_update_display_priority(struct radeon_device *rdev);
Dave Airlie72542d72009-12-01 14:06:31 +10001788extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001789extern void radeon_scratch_init(struct radeon_device *rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -04001790extern void radeon_wb_fini(struct radeon_device *rdev);
1791extern int radeon_wb_init(struct radeon_device *rdev);
1792extern void radeon_wb_disable(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001793extern void radeon_surface_init(struct radeon_device *rdev);
1794extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
Jerome Glisseca6ffc62009-10-01 10:20:52 +02001795extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
Jerome Glissed39c3b82009-09-28 18:34:43 +02001796extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
Jerome Glisse312ea8d2009-12-07 15:52:58 +01001797extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
Jerome Glissed03d8582009-12-14 21:02:09 +01001798extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
Jerome Glissed594e462010-02-17 21:54:29 +00001799extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1800extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001801extern int radeon_resume_kms(struct drm_device *dev);
1802extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
Dave Airlie53595332011-03-14 09:47:24 +10001803extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +02001804
Daniel Vetter3574dda2011-02-18 17:59:19 +01001805/*
Jerome Glisse721604a2012-01-05 22:11:05 -05001806 * vm
1807 */
1808int radeon_vm_manager_init(struct radeon_device *rdev);
1809void radeon_vm_manager_fini(struct radeon_device *rdev);
1810int radeon_vm_manager_start(struct radeon_device *rdev);
1811int radeon_vm_manager_suspend(struct radeon_device *rdev);
1812int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1813void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1814int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm);
1815void radeon_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
1816int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1817 struct radeon_vm *vm,
1818 struct radeon_bo *bo,
1819 struct ttm_mem_reg *mem);
1820void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1821 struct radeon_bo *bo);
1822int radeon_vm_bo_add(struct radeon_device *rdev,
1823 struct radeon_vm *vm,
1824 struct radeon_bo *bo,
1825 uint64_t offset,
1826 uint32_t flags);
1827int radeon_vm_bo_rmv(struct radeon_device *rdev,
1828 struct radeon_vm *vm,
1829 struct radeon_bo *bo);
1830
1831
1832/*
Alex Deucher16cdf042011-10-28 10:30:02 -04001833 * R600 vram scratch functions
1834 */
1835int r600_vram_scratch_init(struct radeon_device *rdev);
1836void r600_vram_scratch_fini(struct radeon_device *rdev);
1837
1838/*
Jerome Glisse285484e2011-12-16 17:03:42 -05001839 * r600 cs checking helper
1840 */
1841unsigned r600_mip_minify(unsigned size, unsigned level);
1842bool r600_fmt_is_valid_color(u32 format);
1843bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1844int r600_fmt_get_blocksize(u32 format);
1845int r600_fmt_get_nblocksx(u32 format, u32 w);
1846int r600_fmt_get_nblocksy(u32 format, u32 h);
1847
1848/*
Daniel Vetter3574dda2011-02-18 17:59:19 +01001849 * r600 functions used by radeon_encoder.c
1850 */
Rafał Miłecki2cd6218c2010-03-08 22:14:01 +00001851extern void r600_hdmi_enable(struct drm_encoder *encoder);
1852extern void r600_hdmi_disable(struct drm_encoder *encoder);
Christian Koenigdafc3bd2009-10-11 23:49:13 +02001853extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucherfe251e22010-03-24 13:36:43 -04001854
Alex Deucher0af62b02011-01-06 21:19:31 -05001855extern int ni_init_microcode(struct radeon_device *rdev);
Alex Deucher755d8192011-03-02 20:07:34 -05001856extern int ni_mc_load_microcode(struct radeon_device *rdev);
Alex Deucher0af62b02011-01-06 21:19:31 -05001857
Alberto Miloned7a29522010-07-06 11:40:24 -04001858/* radeon_acpi.c */
1859#if defined(CONFIG_ACPI)
1860extern int radeon_acpi_init(struct radeon_device *rdev);
1861#else
1862static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1863#endif
1864
Jerome Glisse4c788672009-11-20 14:29:23 +01001865#include "radeon_object.h"
1866
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001867#endif