Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Keith Packard <keithp@keithp.com> |
| 26 | * |
| 27 | */ |
| 28 | |
| 29 | #include <linux/seq_file.h> |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 30 | #include <linux/circ_buf.h> |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 31 | #include <linux/ctype.h> |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 32 | #include <linux/debugfs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 33 | #include <linux/slab.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 34 | #include <linux/export.h> |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 35 | #include <linux/list_sort.h> |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 36 | #include <asm/msr-index.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 37 | #include <drm/drmP.h> |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 38 | #include "intel_drv.h" |
Chris Wilson | e5c6526 | 2010-11-01 11:35:28 +0000 | [diff] [blame] | 39 | #include "intel_ringbuffer.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 40 | #include <drm/i915_drm.h> |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 41 | #include "i915_drv.h" |
| 42 | |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 43 | enum { |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 44 | ACTIVE_LIST, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 45 | INACTIVE_LIST, |
Chris Wilson | d21d597 | 2010-09-26 11:19:33 +0100 | [diff] [blame] | 46 | PINNED_LIST, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 47 | }; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 48 | |
Damien Lespiau | 497666d | 2013-10-15 18:55:39 +0100 | [diff] [blame] | 49 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
| 50 | * allocated we need to hook into the minor for release. */ |
| 51 | static int |
| 52 | drm_add_fake_info_node(struct drm_minor *minor, |
| 53 | struct dentry *ent, |
| 54 | const void *key) |
| 55 | { |
| 56 | struct drm_info_node *node; |
| 57 | |
| 58 | node = kmalloc(sizeof(*node), GFP_KERNEL); |
| 59 | if (node == NULL) { |
| 60 | debugfs_remove(ent); |
| 61 | return -ENOMEM; |
| 62 | } |
| 63 | |
| 64 | node->minor = minor; |
| 65 | node->dent = ent; |
| 66 | node->info_ent = (void *) key; |
| 67 | |
| 68 | mutex_lock(&minor->debugfs_lock); |
| 69 | list_add(&node->list, &minor->debugfs_list); |
| 70 | mutex_unlock(&minor->debugfs_lock); |
| 71 | |
| 72 | return 0; |
| 73 | } |
| 74 | |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 75 | static int i915_capabilities(struct seq_file *m, void *data) |
| 76 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 77 | struct drm_info_node *node = m->private; |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 78 | struct drm_device *dev = node->minor->dev; |
| 79 | const struct intel_device_info *info = INTEL_INFO(dev); |
| 80 | |
| 81 | seq_printf(m, "gen: %d\n", info->gen); |
Paulo Zanoni | 03d00ac | 2011-10-14 18:17:41 -0300 | [diff] [blame] | 82 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 83 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
| 84 | #define SEP_SEMICOLON ; |
| 85 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); |
| 86 | #undef PRINT_FLAG |
| 87 | #undef SEP_SEMICOLON |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 88 | |
| 89 | return 0; |
| 90 | } |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 91 | |
Imre Deak | a7363de | 2016-05-12 16:18:52 +0300 | [diff] [blame] | 92 | static char get_active_flag(struct drm_i915_gem_object *obj) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 93 | { |
Tvrtko Ursulin | be12a86 | 2016-04-15 11:34:52 +0100 | [diff] [blame] | 94 | return obj->active ? '*' : ' '; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 95 | } |
| 96 | |
Imre Deak | a7363de | 2016-05-12 16:18:52 +0300 | [diff] [blame] | 97 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
Tvrtko Ursulin | be12a86 | 2016-04-15 11:34:52 +0100 | [diff] [blame] | 98 | { |
| 99 | return obj->pin_display ? 'p' : ' '; |
| 100 | } |
| 101 | |
Imre Deak | a7363de | 2016-05-12 16:18:52 +0300 | [diff] [blame] | 102 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 103 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 104 | switch (obj->tiling_mode) { |
| 105 | default: |
Tvrtko Ursulin | be12a86 | 2016-04-15 11:34:52 +0100 | [diff] [blame] | 106 | case I915_TILING_NONE: return ' '; |
| 107 | case I915_TILING_X: return 'X'; |
| 108 | case I915_TILING_Y: return 'Y'; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 109 | } |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 110 | } |
| 111 | |
Imre Deak | a7363de | 2016-05-12 16:18:52 +0300 | [diff] [blame] | 112 | static char get_global_flag(struct drm_i915_gem_object *obj) |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 113 | { |
Tvrtko Ursulin | be12a86 | 2016-04-15 11:34:52 +0100 | [diff] [blame] | 114 | return i915_gem_obj_to_ggtt(obj) ? 'g' : ' '; |
| 115 | } |
| 116 | |
Imre Deak | a7363de | 2016-05-12 16:18:52 +0300 | [diff] [blame] | 117 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
Tvrtko Ursulin | be12a86 | 2016-04-15 11:34:52 +0100 | [diff] [blame] | 118 | { |
| 119 | return obj->mapping ? 'M' : ' '; |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 120 | } |
| 121 | |
Tvrtko Ursulin | ca1543b | 2015-07-01 11:51:10 +0100 | [diff] [blame] | 122 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
| 123 | { |
| 124 | u64 size = 0; |
| 125 | struct i915_vma *vma; |
| 126 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 127 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
Chris Wilson | 596c592 | 2016-02-26 11:03:20 +0000 | [diff] [blame] | 128 | if (vma->is_ggtt && drm_mm_node_allocated(&vma->node)) |
Tvrtko Ursulin | ca1543b | 2015-07-01 11:51:10 +0100 | [diff] [blame] | 129 | size += vma->node.size; |
| 130 | } |
| 131 | |
| 132 | return size; |
| 133 | } |
| 134 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 135 | static void |
| 136 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) |
| 137 | { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 138 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 139 | struct intel_engine_cs *engine; |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 140 | struct i915_vma *vma; |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 141 | int pin_count = 0; |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 142 | enum intel_engine_id id; |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 143 | |
Chris Wilson | 188c1ab | 2016-04-03 14:14:20 +0100 | [diff] [blame] | 144 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
| 145 | |
Tvrtko Ursulin | be12a86 | 2016-04-15 11:34:52 +0100 | [diff] [blame] | 146 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 147 | &obj->base, |
Tvrtko Ursulin | be12a86 | 2016-04-15 11:34:52 +0100 | [diff] [blame] | 148 | get_active_flag(obj), |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 149 | get_pin_flag(obj), |
| 150 | get_tiling_flag(obj), |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 151 | get_global_flag(obj), |
Tvrtko Ursulin | be12a86 | 2016-04-15 11:34:52 +0100 | [diff] [blame] | 152 | get_pin_mapped_flag(obj), |
Eric Anholt | a05a586 | 2011-12-20 08:54:15 -0800 | [diff] [blame] | 153 | obj->base.size / 1024, |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 154 | obj->base.read_domains, |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 155 | obj->base.write_domain); |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 156 | for_each_engine_id(engine, dev_priv, id) |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 157 | seq_printf(m, "%x ", |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 158 | i915_gem_request_get_seqno(obj->last_read_req[id])); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 159 | seq_printf(m, "] %x %x%s%s%s", |
John Harrison | 97b2a6a | 2014-11-24 18:49:26 +0000 | [diff] [blame] | 160 | i915_gem_request_get_seqno(obj->last_write_req), |
| 161 | i915_gem_request_get_seqno(obj->last_fenced_req), |
Chris Wilson | 0a4cd7c | 2014-08-22 14:41:39 +0100 | [diff] [blame] | 162 | i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level), |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 163 | obj->dirty ? " dirty" : "", |
| 164 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); |
| 165 | if (obj->base.name) |
| 166 | seq_printf(m, " (name: %d)", obj->base.name); |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 167 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 168 | if (vma->pin_count > 0) |
| 169 | pin_count++; |
Dan Carpenter | ba0635f | 2015-02-25 16:17:48 +0300 | [diff] [blame] | 170 | } |
| 171 | seq_printf(m, " (pinned x %d)", pin_count); |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 172 | if (obj->pin_display) |
| 173 | seq_printf(m, " (display)"); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 174 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
| 175 | seq_printf(m, " (fence: %d)", obj->fence_reg); |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 176 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
Tvrtko Ursulin | 8d2fdc3 | 2015-05-27 10:52:32 +0100 | [diff] [blame] | 177 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
Chris Wilson | 596c592 | 2016-02-26 11:03:20 +0000 | [diff] [blame] | 178 | vma->is_ggtt ? "g" : "pp", |
Tvrtko Ursulin | 8d2fdc3 | 2015-05-27 10:52:32 +0100 | [diff] [blame] | 179 | vma->node.start, vma->node.size); |
Chris Wilson | 596c592 | 2016-02-26 11:03:20 +0000 | [diff] [blame] | 180 | if (vma->is_ggtt) |
| 181 | seq_printf(m, ", type: %u", vma->ggtt_view.type); |
| 182 | seq_puts(m, ")"); |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 183 | } |
Chris Wilson | c1ad11f | 2012-11-15 11:32:21 +0000 | [diff] [blame] | 184 | if (obj->stolen) |
Thierry Reding | 440fd52 | 2015-01-23 09:05:06 +0100 | [diff] [blame] | 185 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
Chris Wilson | 3015465 | 2015-04-07 17:28:24 +0100 | [diff] [blame] | 186 | if (obj->pin_display || obj->fault_mappable) { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 187 | char s[3], *t = s; |
Chris Wilson | 3015465 | 2015-04-07 17:28:24 +0100 | [diff] [blame] | 188 | if (obj->pin_display) |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 189 | *t++ = 'p'; |
| 190 | if (obj->fault_mappable) |
| 191 | *t++ = 'f'; |
| 192 | *t = '\0'; |
| 193 | seq_printf(m, " (%s mappable)", s); |
| 194 | } |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 195 | if (obj->last_write_req != NULL) |
John Harrison | 41c5241 | 2014-11-24 18:49:43 +0000 | [diff] [blame] | 196 | seq_printf(m, " (%s)", |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 197 | i915_gem_request_get_engine(obj->last_write_req)->name); |
Daniel Vetter | d5a81ef | 2014-06-18 14:46:49 +0200 | [diff] [blame] | 198 | if (obj->frontbuffer_bits) |
| 199 | seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 200 | } |
| 201 | |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 202 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 203 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 204 | struct drm_info_node *node = m->private; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 205 | uintptr_t list = (uintptr_t) node->info_ent->data; |
| 206 | struct list_head *head; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 207 | struct drm_device *dev = node->minor->dev; |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 208 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 209 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 210 | struct i915_vma *vma; |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 211 | u64 total_obj_size, total_gtt_size; |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 212 | int count, ret; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 213 | |
| 214 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 215 | if (ret) |
| 216 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 217 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 218 | /* FIXME: the user of this interface might want more than just GGTT */ |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 219 | switch (list) { |
| 220 | case ACTIVE_LIST: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 221 | seq_puts(m, "Active:\n"); |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 222 | head = &ggtt->base.active_list; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 223 | break; |
| 224 | case INACTIVE_LIST: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 225 | seq_puts(m, "Inactive:\n"); |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 226 | head = &ggtt->base.inactive_list; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 227 | break; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 228 | default: |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 229 | mutex_unlock(&dev->struct_mutex); |
| 230 | return -EINVAL; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 231 | } |
| 232 | |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 233 | total_obj_size = total_gtt_size = count = 0; |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 234 | list_for_each_entry(vma, head, vm_link) { |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 235 | seq_printf(m, " "); |
| 236 | describe_obj(m, vma->obj); |
| 237 | seq_printf(m, "\n"); |
| 238 | total_obj_size += vma->obj->base.size; |
| 239 | total_gtt_size += vma->node.size; |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 240 | count++; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 241 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 242 | mutex_unlock(&dev->struct_mutex); |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 243 | |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 244 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 245 | count, total_obj_size, total_gtt_size); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 246 | return 0; |
| 247 | } |
| 248 | |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 249 | static int obj_rank_by_stolen(void *priv, |
| 250 | struct list_head *A, struct list_head *B) |
| 251 | { |
| 252 | struct drm_i915_gem_object *a = |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 253 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 254 | struct drm_i915_gem_object *b = |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 255 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 256 | |
Rasmus Villemoes | 2d05fa1 | 2015-09-28 23:08:50 +0200 | [diff] [blame] | 257 | if (a->stolen->start < b->stolen->start) |
| 258 | return -1; |
| 259 | if (a->stolen->start > b->stolen->start) |
| 260 | return 1; |
| 261 | return 0; |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 262 | } |
| 263 | |
| 264 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) |
| 265 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 266 | struct drm_info_node *node = m->private; |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 267 | struct drm_device *dev = node->minor->dev; |
| 268 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 269 | struct drm_i915_gem_object *obj; |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 270 | u64 total_obj_size, total_gtt_size; |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 271 | LIST_HEAD(stolen); |
| 272 | int count, ret; |
| 273 | |
| 274 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 275 | if (ret) |
| 276 | return ret; |
| 277 | |
| 278 | total_obj_size = total_gtt_size = count = 0; |
| 279 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
| 280 | if (obj->stolen == NULL) |
| 281 | continue; |
| 282 | |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 283 | list_add(&obj->obj_exec_link, &stolen); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 284 | |
| 285 | total_obj_size += obj->base.size; |
Tvrtko Ursulin | ca1543b | 2015-07-01 11:51:10 +0100 | [diff] [blame] | 286 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 287 | count++; |
| 288 | } |
| 289 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
| 290 | if (obj->stolen == NULL) |
| 291 | continue; |
| 292 | |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 293 | list_add(&obj->obj_exec_link, &stolen); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 294 | |
| 295 | total_obj_size += obj->base.size; |
| 296 | count++; |
| 297 | } |
| 298 | list_sort(NULL, &stolen, obj_rank_by_stolen); |
| 299 | seq_puts(m, "Stolen:\n"); |
| 300 | while (!list_empty(&stolen)) { |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 301 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 302 | seq_puts(m, " "); |
| 303 | describe_obj(m, obj); |
| 304 | seq_putc(m, '\n'); |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 305 | list_del_init(&obj->obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 306 | } |
| 307 | mutex_unlock(&dev->struct_mutex); |
| 308 | |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 309 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 310 | count, total_obj_size, total_gtt_size); |
| 311 | return 0; |
| 312 | } |
| 313 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 314 | #define count_objects(list, member) do { \ |
| 315 | list_for_each_entry(obj, list, member) { \ |
Tvrtko Ursulin | ca1543b | 2015-07-01 11:51:10 +0100 | [diff] [blame] | 316 | size += i915_gem_obj_total_ggtt_size(obj); \ |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 317 | ++count; \ |
| 318 | if (obj->map_and_fenceable) { \ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 319 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 320 | ++mappable_count; \ |
| 321 | } \ |
| 322 | } \ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 323 | } while (0) |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 324 | |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 325 | struct file_stats { |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 326 | struct drm_i915_file_private *file_priv; |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 327 | unsigned long count; |
| 328 | u64 total, unbound; |
| 329 | u64 global, shared; |
| 330 | u64 active, inactive; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 331 | }; |
| 332 | |
| 333 | static int per_file_stats(int id, void *ptr, void *data) |
| 334 | { |
| 335 | struct drm_i915_gem_object *obj = ptr; |
| 336 | struct file_stats *stats = data; |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 337 | struct i915_vma *vma; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 338 | |
| 339 | stats->count++; |
| 340 | stats->total += obj->base.size; |
| 341 | |
Chris Wilson | c67a17e | 2014-03-19 13:45:46 +0000 | [diff] [blame] | 342 | if (obj->base.name || obj->base.dma_buf) |
| 343 | stats->shared += obj->base.size; |
| 344 | |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 345 | if (USES_FULL_PPGTT(obj->base.dev)) { |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 346 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 347 | struct i915_hw_ppgtt *ppgtt; |
| 348 | |
| 349 | if (!drm_mm_node_allocated(&vma->node)) |
| 350 | continue; |
| 351 | |
Chris Wilson | 596c592 | 2016-02-26 11:03:20 +0000 | [diff] [blame] | 352 | if (vma->is_ggtt) { |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 353 | stats->global += obj->base.size; |
| 354 | continue; |
| 355 | } |
| 356 | |
| 357 | ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base); |
Daniel Vetter | 4d88470 | 2014-08-06 15:04:47 +0200 | [diff] [blame] | 358 | if (ppgtt->file_priv != stats->file_priv) |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 359 | continue; |
| 360 | |
John Harrison | 41c5241 | 2014-11-24 18:49:43 +0000 | [diff] [blame] | 361 | if (obj->active) /* XXX per-vma statistic */ |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 362 | stats->active += obj->base.size; |
| 363 | else |
| 364 | stats->inactive += obj->base.size; |
| 365 | |
| 366 | return 0; |
| 367 | } |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 368 | } else { |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 369 | if (i915_gem_obj_ggtt_bound(obj)) { |
| 370 | stats->global += obj->base.size; |
John Harrison | 41c5241 | 2014-11-24 18:49:43 +0000 | [diff] [blame] | 371 | if (obj->active) |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 372 | stats->active += obj->base.size; |
| 373 | else |
| 374 | stats->inactive += obj->base.size; |
| 375 | return 0; |
| 376 | } |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 377 | } |
| 378 | |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 379 | if (!list_empty(&obj->global_list)) |
| 380 | stats->unbound += obj->base.size; |
| 381 | |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 382 | return 0; |
| 383 | } |
| 384 | |
Chris Wilson | b0da1b7 | 2015-04-07 16:20:40 +0100 | [diff] [blame] | 385 | #define print_file_stats(m, name, stats) do { \ |
| 386 | if (stats.count) \ |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 387 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
Chris Wilson | b0da1b7 | 2015-04-07 16:20:40 +0100 | [diff] [blame] | 388 | name, \ |
| 389 | stats.count, \ |
| 390 | stats.total, \ |
| 391 | stats.active, \ |
| 392 | stats.inactive, \ |
| 393 | stats.global, \ |
| 394 | stats.shared, \ |
| 395 | stats.unbound); \ |
| 396 | } while (0) |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 397 | |
| 398 | static void print_batch_pool_stats(struct seq_file *m, |
| 399 | struct drm_i915_private *dev_priv) |
| 400 | { |
| 401 | struct drm_i915_gem_object *obj; |
| 402 | struct file_stats stats; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 403 | struct intel_engine_cs *engine; |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 404 | int j; |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 405 | |
| 406 | memset(&stats, 0, sizeof(stats)); |
| 407 | |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 408 | for_each_engine(engine, dev_priv) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 409 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
Chris Wilson | 8d9d574 | 2015-04-07 16:20:38 +0100 | [diff] [blame] | 410 | list_for_each_entry(obj, |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 411 | &engine->batch_pool.cache_list[j], |
Chris Wilson | 8d9d574 | 2015-04-07 16:20:38 +0100 | [diff] [blame] | 412 | batch_pool_link) |
| 413 | per_file_stats(0, obj, &stats); |
| 414 | } |
Chris Wilson | 06fbca7 | 2015-04-07 16:20:36 +0100 | [diff] [blame] | 415 | } |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 416 | |
Chris Wilson | b0da1b7 | 2015-04-07 16:20:40 +0100 | [diff] [blame] | 417 | print_file_stats(m, "[k]batch pool", stats); |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 418 | } |
| 419 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 420 | #define count_vmas(list, member) do { \ |
| 421 | list_for_each_entry(vma, list, member) { \ |
Tvrtko Ursulin | ca1543b | 2015-07-01 11:51:10 +0100 | [diff] [blame] | 422 | size += i915_gem_obj_total_ggtt_size(vma->obj); \ |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 423 | ++count; \ |
| 424 | if (vma->obj->map_and_fenceable) { \ |
| 425 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ |
| 426 | ++mappable_count; \ |
| 427 | } \ |
| 428 | } \ |
| 429 | } while (0) |
| 430 | |
| 431 | static int i915_gem_object_info(struct seq_file *m, void* data) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 432 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 433 | struct drm_info_node *node = m->private; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 434 | struct drm_device *dev = node->minor->dev; |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 435 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 436 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 437 | u32 count, mappable_count, purgeable_count; |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 438 | u64 size, mappable_size, purgeable_size; |
Tvrtko Ursulin | be19b10 | 2016-04-15 11:34:53 +0100 | [diff] [blame] | 439 | unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0; |
| 440 | u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 441 | struct drm_i915_gem_object *obj; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 442 | struct drm_file *file; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 443 | struct i915_vma *vma; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 444 | int ret; |
| 445 | |
| 446 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 447 | if (ret) |
| 448 | return ret; |
| 449 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 450 | seq_printf(m, "%u objects, %zu bytes\n", |
| 451 | dev_priv->mm.object_count, |
| 452 | dev_priv->mm.object_memory); |
| 453 | |
| 454 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 455 | count_objects(&dev_priv->mm.bound_list, global_list); |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 456 | seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n", |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 457 | count, mappable_count, size, mappable_size); |
| 458 | |
| 459 | size = count = mappable_size = mappable_count = 0; |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 460 | count_vmas(&ggtt->base.active_list, vm_link); |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 461 | seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n", |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 462 | count, mappable_count, size, mappable_size); |
| 463 | |
| 464 | size = count = mappable_size = mappable_count = 0; |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 465 | count_vmas(&ggtt->base.inactive_list, vm_link); |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 466 | seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n", |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 467 | count, mappable_count, size, mappable_size); |
| 468 | |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 469 | size = count = purgeable_size = purgeable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 470 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 471 | size += obj->base.size, ++count; |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 472 | if (obj->madv == I915_MADV_DONTNEED) |
| 473 | purgeable_size += obj->base.size, ++purgeable_count; |
Tvrtko Ursulin | be19b10 | 2016-04-15 11:34:53 +0100 | [diff] [blame] | 474 | if (obj->mapping) { |
| 475 | pin_mapped_count++; |
| 476 | pin_mapped_size += obj->base.size; |
| 477 | if (obj->pages_pin_count == 0) { |
| 478 | pin_mapped_purgeable_count++; |
| 479 | pin_mapped_purgeable_size += obj->base.size; |
| 480 | } |
| 481 | } |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 482 | } |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 483 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 484 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 485 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 486 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 487 | if (obj->fault_mappable) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 488 | size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 489 | ++count; |
| 490 | } |
Chris Wilson | 3015465 | 2015-04-07 17:28:24 +0100 | [diff] [blame] | 491 | if (obj->pin_display) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 492 | mappable_size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 493 | ++mappable_count; |
| 494 | } |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 495 | if (obj->madv == I915_MADV_DONTNEED) { |
| 496 | purgeable_size += obj->base.size; |
| 497 | ++purgeable_count; |
| 498 | } |
Tvrtko Ursulin | be19b10 | 2016-04-15 11:34:53 +0100 | [diff] [blame] | 499 | if (obj->mapping) { |
| 500 | pin_mapped_count++; |
| 501 | pin_mapped_size += obj->base.size; |
| 502 | if (obj->pages_pin_count == 0) { |
| 503 | pin_mapped_purgeable_count++; |
| 504 | pin_mapped_purgeable_size += obj->base.size; |
| 505 | } |
| 506 | } |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 507 | } |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 508 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 509 | purgeable_count, purgeable_size); |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 510 | seq_printf(m, "%u pinned mappable objects, %llu bytes\n", |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 511 | mappable_count, mappable_size); |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 512 | seq_printf(m, "%u fault mappable objects, %llu bytes\n", |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 513 | count, size); |
Tvrtko Ursulin | be19b10 | 2016-04-15 11:34:53 +0100 | [diff] [blame] | 514 | seq_printf(m, |
| 515 | "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n", |
| 516 | pin_mapped_count, pin_mapped_purgeable_count, |
| 517 | pin_mapped_size, pin_mapped_purgeable_size); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 518 | |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 519 | seq_printf(m, "%llu [%llu] gtt total\n", |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 520 | ggtt->base.total, ggtt->mappable_end - ggtt->base.start); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 521 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 522 | seq_putc(m, '\n'); |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 523 | print_batch_pool_stats(m, dev_priv); |
Daniel Vetter | 1d2ac40 | 2016-04-26 19:29:41 +0200 | [diff] [blame] | 524 | |
| 525 | mutex_unlock(&dev->struct_mutex); |
| 526 | |
| 527 | mutex_lock(&dev->filelist_mutex); |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 528 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
| 529 | struct file_stats stats; |
Tetsuo Handa | 3ec2f42 | 2014-01-03 20:42:18 +0900 | [diff] [blame] | 530 | struct task_struct *task; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 531 | |
| 532 | memset(&stats, 0, sizeof(stats)); |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 533 | stats.file_priv = file->driver_priv; |
Chris Wilson | 5b5ffff | 2014-06-17 09:56:24 +0100 | [diff] [blame] | 534 | spin_lock(&file->table_lock); |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 535 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
Chris Wilson | 5b5ffff | 2014-06-17 09:56:24 +0100 | [diff] [blame] | 536 | spin_unlock(&file->table_lock); |
Tetsuo Handa | 3ec2f42 | 2014-01-03 20:42:18 +0900 | [diff] [blame] | 537 | /* |
| 538 | * Although we have a valid reference on file->pid, that does |
| 539 | * not guarantee that the task_struct who called get_pid() is |
| 540 | * still alive (e.g. get_pid(current) => fork() => exit()). |
| 541 | * Therefore, we need to protect this ->comm access using RCU. |
| 542 | */ |
| 543 | rcu_read_lock(); |
| 544 | task = pid_task(file->pid, PIDTYPE_PID); |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 545 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
Tetsuo Handa | 3ec2f42 | 2014-01-03 20:42:18 +0900 | [diff] [blame] | 546 | rcu_read_unlock(); |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 547 | } |
Daniel Vetter | 1d2ac40 | 2016-04-26 19:29:41 +0200 | [diff] [blame] | 548 | mutex_unlock(&dev->filelist_mutex); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 549 | |
| 550 | return 0; |
| 551 | } |
| 552 | |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 553 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 554 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 555 | struct drm_info_node *node = m->private; |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 556 | struct drm_device *dev = node->minor->dev; |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 557 | uintptr_t list = (uintptr_t) node->info_ent->data; |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 558 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 559 | struct drm_i915_gem_object *obj; |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 560 | u64 total_obj_size, total_gtt_size; |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 561 | int count, ret; |
| 562 | |
| 563 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 564 | if (ret) |
| 565 | return ret; |
| 566 | |
| 567 | total_obj_size = total_gtt_size = count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 568 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 569 | if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 570 | continue; |
| 571 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 572 | seq_puts(m, " "); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 573 | describe_obj(m, obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 574 | seq_putc(m, '\n'); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 575 | total_obj_size += obj->base.size; |
Tvrtko Ursulin | ca1543b | 2015-07-01 11:51:10 +0100 | [diff] [blame] | 576 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 577 | count++; |
| 578 | } |
| 579 | |
| 580 | mutex_unlock(&dev->struct_mutex); |
| 581 | |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 582 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 583 | count, total_obj_size, total_gtt_size); |
| 584 | |
| 585 | return 0; |
| 586 | } |
| 587 | |
Maarten Lankhorst | 6885843 | 2016-05-17 15:07:52 +0200 | [diff] [blame] | 588 | static void i915_dump_pageflip(struct seq_file *m, |
| 589 | struct drm_i915_private *dev_priv, |
| 590 | struct intel_crtc *crtc, |
| 591 | struct intel_flip_work *work) |
| 592 | { |
| 593 | const char pipe = pipe_name(crtc->pipe); |
Maarten Lankhorst | 6885843 | 2016-05-17 15:07:52 +0200 | [diff] [blame] | 594 | u32 pending; |
Maarten Lankhorst | 143f73b | 2016-05-17 15:07:54 +0200 | [diff] [blame] | 595 | int i; |
Maarten Lankhorst | 6885843 | 2016-05-17 15:07:52 +0200 | [diff] [blame] | 596 | |
| 597 | pending = atomic_read(&work->pending); |
| 598 | if (pending) { |
| 599 | seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", |
Maarten Lankhorst | 143f73b | 2016-05-17 15:07:54 +0200 | [diff] [blame] | 600 | pipe, plane_name(crtc->plane)); |
Maarten Lankhorst | 6885843 | 2016-05-17 15:07:52 +0200 | [diff] [blame] | 601 | } else { |
| 602 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
Maarten Lankhorst | 143f73b | 2016-05-17 15:07:54 +0200 | [diff] [blame] | 603 | pipe, plane_name(crtc->plane)); |
Maarten Lankhorst | 6885843 | 2016-05-17 15:07:52 +0200 | [diff] [blame] | 604 | } |
Maarten Lankhorst | 6885843 | 2016-05-17 15:07:52 +0200 | [diff] [blame] | 605 | |
Maarten Lankhorst | 143f73b | 2016-05-17 15:07:54 +0200 | [diff] [blame] | 606 | for (i = 0; i < work->num_planes; i++) { |
| 607 | struct intel_plane_state *old_plane_state = work->old_plane_state[i]; |
| 608 | struct drm_plane *plane = old_plane_state->base.plane; |
| 609 | struct drm_i915_gem_request *req = old_plane_state->wait_req; |
| 610 | struct intel_engine_cs *engine; |
| 611 | |
| 612 | seq_printf(m, "[PLANE:%i] part of flip.\n", plane->base.id); |
| 613 | |
| 614 | if (!req) { |
| 615 | seq_printf(m, "Plane not associated with any engine\n"); |
| 616 | continue; |
| 617 | } |
| 618 | |
| 619 | engine = i915_gem_request_get_engine(req); |
| 620 | |
| 621 | seq_printf(m, "Plane blocked on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", |
Maarten Lankhorst | 6885843 | 2016-05-17 15:07:52 +0200 | [diff] [blame] | 622 | engine->name, |
Maarten Lankhorst | 143f73b | 2016-05-17 15:07:54 +0200 | [diff] [blame] | 623 | i915_gem_request_get_seqno(req), |
Maarten Lankhorst | 6885843 | 2016-05-17 15:07:52 +0200 | [diff] [blame] | 624 | dev_priv->next_seqno, |
| 625 | engine->get_seqno(engine), |
Maarten Lankhorst | 143f73b | 2016-05-17 15:07:54 +0200 | [diff] [blame] | 626 | i915_gem_request_completed(req, true)); |
| 627 | } |
| 628 | |
Maarten Lankhorst | 8dd634d | 2016-05-17 15:07:55 +0200 | [diff] [blame] | 629 | seq_printf(m, "Flip queued on frame %d, now %d\n", |
| 630 | pending ? work->flip_queued_vblank : -1, |
Maarten Lankhorst | 6885843 | 2016-05-17 15:07:52 +0200 | [diff] [blame] | 631 | intel_crtc_get_vblank_counter(crtc)); |
Maarten Lankhorst | 6885843 | 2016-05-17 15:07:52 +0200 | [diff] [blame] | 632 | } |
| 633 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 634 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
| 635 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 636 | struct drm_info_node *node = m->private; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 637 | struct drm_device *dev = node->minor->dev; |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 638 | struct drm_i915_private *dev_priv = dev->dev_private; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 639 | struct intel_crtc *crtc; |
Daniel Vetter | 8a270eb | 2014-06-17 22:34:37 +0200 | [diff] [blame] | 640 | int ret; |
| 641 | |
| 642 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 643 | if (ret) |
| 644 | return ret; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 645 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 646 | for_each_intel_crtc(dev, crtc) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 647 | const char pipe = pipe_name(crtc->pipe); |
| 648 | const char plane = plane_name(crtc->plane); |
Maarten Lankhorst | 51cbaf0 | 2016-05-17 15:07:49 +0200 | [diff] [blame] | 649 | struct intel_flip_work *work; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 650 | |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 651 | spin_lock_irq(&dev->event_lock); |
Maarten Lankhorst | 6885843 | 2016-05-17 15:07:52 +0200 | [diff] [blame] | 652 | if (list_empty(&crtc->flip_work)) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 653 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 654 | pipe, plane); |
| 655 | } else { |
Maarten Lankhorst | 6885843 | 2016-05-17 15:07:52 +0200 | [diff] [blame] | 656 | list_for_each_entry(work, &crtc->flip_work, head) { |
| 657 | i915_dump_pageflip(m, dev_priv, crtc, work); |
| 658 | seq_puts(m, "\n"); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 659 | } |
| 660 | } |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 661 | spin_unlock_irq(&dev->event_lock); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 662 | } |
| 663 | |
Daniel Vetter | 8a270eb | 2014-06-17 22:34:37 +0200 | [diff] [blame] | 664 | mutex_unlock(&dev->struct_mutex); |
| 665 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 666 | return 0; |
| 667 | } |
| 668 | |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 669 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
| 670 | { |
| 671 | struct drm_info_node *node = m->private; |
| 672 | struct drm_device *dev = node->minor->dev; |
| 673 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 674 | struct drm_i915_gem_object *obj; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 675 | struct intel_engine_cs *engine; |
Chris Wilson | 8d9d574 | 2015-04-07 16:20:38 +0100 | [diff] [blame] | 676 | int total = 0; |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 677 | int ret, j; |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 678 | |
| 679 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 680 | if (ret) |
| 681 | return ret; |
| 682 | |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 683 | for_each_engine(engine, dev_priv) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 684 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
Chris Wilson | 8d9d574 | 2015-04-07 16:20:38 +0100 | [diff] [blame] | 685 | int count; |
| 686 | |
| 687 | count = 0; |
| 688 | list_for_each_entry(obj, |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 689 | &engine->batch_pool.cache_list[j], |
Chris Wilson | 8d9d574 | 2015-04-07 16:20:38 +0100 | [diff] [blame] | 690 | batch_pool_link) |
| 691 | count++; |
| 692 | seq_printf(m, "%s cache[%d]: %d objects\n", |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 693 | engine->name, j, count); |
Chris Wilson | 8d9d574 | 2015-04-07 16:20:38 +0100 | [diff] [blame] | 694 | |
| 695 | list_for_each_entry(obj, |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 696 | &engine->batch_pool.cache_list[j], |
Chris Wilson | 8d9d574 | 2015-04-07 16:20:38 +0100 | [diff] [blame] | 697 | batch_pool_link) { |
| 698 | seq_puts(m, " "); |
| 699 | describe_obj(m, obj); |
| 700 | seq_putc(m, '\n'); |
| 701 | } |
| 702 | |
| 703 | total += count; |
Chris Wilson | 06fbca7 | 2015-04-07 16:20:36 +0100 | [diff] [blame] | 704 | } |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 705 | } |
| 706 | |
Chris Wilson | 8d9d574 | 2015-04-07 16:20:38 +0100 | [diff] [blame] | 707 | seq_printf(m, "total: %d\n", total); |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 708 | |
| 709 | mutex_unlock(&dev->struct_mutex); |
| 710 | |
| 711 | return 0; |
| 712 | } |
| 713 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 714 | static int i915_gem_request_info(struct seq_file *m, void *data) |
| 715 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 716 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 717 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 718 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 719 | struct intel_engine_cs *engine; |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 720 | struct drm_i915_gem_request *req; |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 721 | int ret, any; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 722 | |
| 723 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 724 | if (ret) |
| 725 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 726 | |
Chris Wilson | 2d1070b | 2015-04-01 10:36:56 +0100 | [diff] [blame] | 727 | any = 0; |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 728 | for_each_engine(engine, dev_priv) { |
Chris Wilson | 2d1070b | 2015-04-01 10:36:56 +0100 | [diff] [blame] | 729 | int count; |
| 730 | |
| 731 | count = 0; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 732 | list_for_each_entry(req, &engine->request_list, list) |
Chris Wilson | 2d1070b | 2015-04-01 10:36:56 +0100 | [diff] [blame] | 733 | count++; |
| 734 | if (count == 0) |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 735 | continue; |
| 736 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 737 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
| 738 | list_for_each_entry(req, &engine->request_list, list) { |
Chris Wilson | 2d1070b | 2015-04-01 10:36:56 +0100 | [diff] [blame] | 739 | struct task_struct *task; |
| 740 | |
| 741 | rcu_read_lock(); |
| 742 | task = NULL; |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 743 | if (req->pid) |
| 744 | task = pid_task(req->pid, PIDTYPE_PID); |
Chris Wilson | 2d1070b | 2015-04-01 10:36:56 +0100 | [diff] [blame] | 745 | seq_printf(m, " %x @ %d: %s [%d]\n", |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 746 | req->seqno, |
| 747 | (int) (jiffies - req->emitted_jiffies), |
Chris Wilson | 2d1070b | 2015-04-01 10:36:56 +0100 | [diff] [blame] | 748 | task ? task->comm : "<unknown>", |
| 749 | task ? task->pid : -1); |
| 750 | rcu_read_unlock(); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 751 | } |
Chris Wilson | 2d1070b | 2015-04-01 10:36:56 +0100 | [diff] [blame] | 752 | |
| 753 | any++; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 754 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 755 | mutex_unlock(&dev->struct_mutex); |
| 756 | |
Chris Wilson | 2d1070b | 2015-04-01 10:36:56 +0100 | [diff] [blame] | 757 | if (any == 0) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 758 | seq_puts(m, "No requests\n"); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 759 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 760 | return 0; |
| 761 | } |
| 762 | |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 763 | static void i915_ring_seqno_info(struct seq_file *m, |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 764 | struct intel_engine_cs *engine) |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 765 | { |
Chris Wilson | 12471ba | 2016-04-09 10:57:55 +0100 | [diff] [blame] | 766 | seq_printf(m, "Current sequence (%s): %x\n", |
| 767 | engine->name, engine->get_seqno(engine)); |
| 768 | seq_printf(m, "Current user interrupts (%s): %x\n", |
| 769 | engine->name, READ_ONCE(engine->user_interrupts)); |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 770 | } |
| 771 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 772 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
| 773 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 774 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 775 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 776 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 777 | struct intel_engine_cs *engine; |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 778 | int ret; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 779 | |
| 780 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 781 | if (ret) |
| 782 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 783 | intel_runtime_pm_get(dev_priv); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 784 | |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 785 | for_each_engine(engine, dev_priv) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 786 | i915_ring_seqno_info(m, engine); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 787 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 788 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 789 | mutex_unlock(&dev->struct_mutex); |
| 790 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 791 | return 0; |
| 792 | } |
| 793 | |
| 794 | |
| 795 | static int i915_interrupt_info(struct seq_file *m, void *data) |
| 796 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 797 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 798 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 799 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 800 | struct intel_engine_cs *engine; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 801 | int ret, i, pipe; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 802 | |
| 803 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 804 | if (ret) |
| 805 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 806 | intel_runtime_pm_get(dev_priv); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 807 | |
Ville Syrjälä | 74e1ca8 | 2014-04-09 13:28:09 +0300 | [diff] [blame] | 808 | if (IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | 74e1ca8 | 2014-04-09 13:28:09 +0300 | [diff] [blame] | 809 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
| 810 | I915_READ(GEN8_MASTER_IRQ)); |
| 811 | |
| 812 | seq_printf(m, "Display IER:\t%08x\n", |
| 813 | I915_READ(VLV_IER)); |
| 814 | seq_printf(m, "Display IIR:\t%08x\n", |
| 815 | I915_READ(VLV_IIR)); |
| 816 | seq_printf(m, "Display IIR_RW:\t%08x\n", |
| 817 | I915_READ(VLV_IIR_RW)); |
| 818 | seq_printf(m, "Display IMR:\t%08x\n", |
| 819 | I915_READ(VLV_IMR)); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 820 | for_each_pipe(dev_priv, pipe) |
Ville Syrjälä | 74e1ca8 | 2014-04-09 13:28:09 +0300 | [diff] [blame] | 821 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
| 822 | pipe_name(pipe), |
| 823 | I915_READ(PIPESTAT(pipe))); |
| 824 | |
| 825 | seq_printf(m, "Port hotplug:\t%08x\n", |
| 826 | I915_READ(PORT_HOTPLUG_EN)); |
| 827 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", |
| 828 | I915_READ(VLV_DPFLIPSTAT)); |
| 829 | seq_printf(m, "DPINVGTT:\t%08x\n", |
| 830 | I915_READ(DPINVGTT)); |
| 831 | |
| 832 | for (i = 0; i < 4; i++) { |
| 833 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", |
| 834 | i, I915_READ(GEN8_GT_IMR(i))); |
| 835 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", |
| 836 | i, I915_READ(GEN8_GT_IIR(i))); |
| 837 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", |
| 838 | i, I915_READ(GEN8_GT_IER(i))); |
| 839 | } |
| 840 | |
| 841 | seq_printf(m, "PCU interrupt mask:\t%08x\n", |
| 842 | I915_READ(GEN8_PCU_IMR)); |
| 843 | seq_printf(m, "PCU interrupt identity:\t%08x\n", |
| 844 | I915_READ(GEN8_PCU_IIR)); |
| 845 | seq_printf(m, "PCU interrupt enable:\t%08x\n", |
| 846 | I915_READ(GEN8_PCU_IER)); |
| 847 | } else if (INTEL_INFO(dev)->gen >= 8) { |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 848 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
| 849 | I915_READ(GEN8_MASTER_IRQ)); |
| 850 | |
| 851 | for (i = 0; i < 4; i++) { |
| 852 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", |
| 853 | i, I915_READ(GEN8_GT_IMR(i))); |
| 854 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", |
| 855 | i, I915_READ(GEN8_GT_IIR(i))); |
| 856 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", |
| 857 | i, I915_READ(GEN8_GT_IER(i))); |
| 858 | } |
| 859 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 860 | for_each_pipe(dev_priv, pipe) { |
Imre Deak | e129649 | 2016-02-12 18:55:17 +0200 | [diff] [blame] | 861 | enum intel_display_power_domain power_domain; |
| 862 | |
| 863 | power_domain = POWER_DOMAIN_PIPE(pipe); |
| 864 | if (!intel_display_power_get_if_enabled(dev_priv, |
| 865 | power_domain)) { |
Paulo Zanoni | 22c5996 | 2014-08-08 17:45:32 -0300 | [diff] [blame] | 866 | seq_printf(m, "Pipe %c power disabled\n", |
| 867 | pipe_name(pipe)); |
| 868 | continue; |
| 869 | } |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 870 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 871 | pipe_name(pipe), |
| 872 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 873 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 874 | pipe_name(pipe), |
| 875 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 876 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 877 | pipe_name(pipe), |
| 878 | I915_READ(GEN8_DE_PIPE_IER(pipe))); |
Imre Deak | e129649 | 2016-02-12 18:55:17 +0200 | [diff] [blame] | 879 | |
| 880 | intel_display_power_put(dev_priv, power_domain); |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 881 | } |
| 882 | |
| 883 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", |
| 884 | I915_READ(GEN8_DE_PORT_IMR)); |
| 885 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", |
| 886 | I915_READ(GEN8_DE_PORT_IIR)); |
| 887 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", |
| 888 | I915_READ(GEN8_DE_PORT_IER)); |
| 889 | |
| 890 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", |
| 891 | I915_READ(GEN8_DE_MISC_IMR)); |
| 892 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", |
| 893 | I915_READ(GEN8_DE_MISC_IIR)); |
| 894 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", |
| 895 | I915_READ(GEN8_DE_MISC_IER)); |
| 896 | |
| 897 | seq_printf(m, "PCU interrupt mask:\t%08x\n", |
| 898 | I915_READ(GEN8_PCU_IMR)); |
| 899 | seq_printf(m, "PCU interrupt identity:\t%08x\n", |
| 900 | I915_READ(GEN8_PCU_IIR)); |
| 901 | seq_printf(m, "PCU interrupt enable:\t%08x\n", |
| 902 | I915_READ(GEN8_PCU_IER)); |
| 903 | } else if (IS_VALLEYVIEW(dev)) { |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 904 | seq_printf(m, "Display IER:\t%08x\n", |
| 905 | I915_READ(VLV_IER)); |
| 906 | seq_printf(m, "Display IIR:\t%08x\n", |
| 907 | I915_READ(VLV_IIR)); |
| 908 | seq_printf(m, "Display IIR_RW:\t%08x\n", |
| 909 | I915_READ(VLV_IIR_RW)); |
| 910 | seq_printf(m, "Display IMR:\t%08x\n", |
| 911 | I915_READ(VLV_IMR)); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 912 | for_each_pipe(dev_priv, pipe) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 913 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
| 914 | pipe_name(pipe), |
| 915 | I915_READ(PIPESTAT(pipe))); |
| 916 | |
| 917 | seq_printf(m, "Master IER:\t%08x\n", |
| 918 | I915_READ(VLV_MASTER_IER)); |
| 919 | |
| 920 | seq_printf(m, "Render IER:\t%08x\n", |
| 921 | I915_READ(GTIER)); |
| 922 | seq_printf(m, "Render IIR:\t%08x\n", |
| 923 | I915_READ(GTIIR)); |
| 924 | seq_printf(m, "Render IMR:\t%08x\n", |
| 925 | I915_READ(GTIMR)); |
| 926 | |
| 927 | seq_printf(m, "PM IER:\t\t%08x\n", |
| 928 | I915_READ(GEN6_PMIER)); |
| 929 | seq_printf(m, "PM IIR:\t\t%08x\n", |
| 930 | I915_READ(GEN6_PMIIR)); |
| 931 | seq_printf(m, "PM IMR:\t\t%08x\n", |
| 932 | I915_READ(GEN6_PMIMR)); |
| 933 | |
| 934 | seq_printf(m, "Port hotplug:\t%08x\n", |
| 935 | I915_READ(PORT_HOTPLUG_EN)); |
| 936 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", |
| 937 | I915_READ(VLV_DPFLIPSTAT)); |
| 938 | seq_printf(m, "DPINVGTT:\t%08x\n", |
| 939 | I915_READ(DPINVGTT)); |
| 940 | |
| 941 | } else if (!HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 5f6a169 | 2009-08-10 21:37:24 +0800 | [diff] [blame] | 942 | seq_printf(m, "Interrupt enable: %08x\n", |
| 943 | I915_READ(IER)); |
| 944 | seq_printf(m, "Interrupt identity: %08x\n", |
| 945 | I915_READ(IIR)); |
| 946 | seq_printf(m, "Interrupt mask: %08x\n", |
| 947 | I915_READ(IMR)); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 948 | for_each_pipe(dev_priv, pipe) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 949 | seq_printf(m, "Pipe %c stat: %08x\n", |
| 950 | pipe_name(pipe), |
| 951 | I915_READ(PIPESTAT(pipe))); |
Zhenyu Wang | 5f6a169 | 2009-08-10 21:37:24 +0800 | [diff] [blame] | 952 | } else { |
| 953 | seq_printf(m, "North Display Interrupt enable: %08x\n", |
| 954 | I915_READ(DEIER)); |
| 955 | seq_printf(m, "North Display Interrupt identity: %08x\n", |
| 956 | I915_READ(DEIIR)); |
| 957 | seq_printf(m, "North Display Interrupt mask: %08x\n", |
| 958 | I915_READ(DEIMR)); |
| 959 | seq_printf(m, "South Display Interrupt enable: %08x\n", |
| 960 | I915_READ(SDEIER)); |
| 961 | seq_printf(m, "South Display Interrupt identity: %08x\n", |
| 962 | I915_READ(SDEIIR)); |
| 963 | seq_printf(m, "South Display Interrupt mask: %08x\n", |
| 964 | I915_READ(SDEIMR)); |
| 965 | seq_printf(m, "Graphics Interrupt enable: %08x\n", |
| 966 | I915_READ(GTIER)); |
| 967 | seq_printf(m, "Graphics Interrupt identity: %08x\n", |
| 968 | I915_READ(GTIIR)); |
| 969 | seq_printf(m, "Graphics Interrupt mask: %08x\n", |
| 970 | I915_READ(GTIMR)); |
| 971 | } |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 972 | for_each_engine(engine, dev_priv) { |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 973 | if (INTEL_INFO(dev)->gen >= 6) { |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 974 | seq_printf(m, |
| 975 | "Graphics Interrupt mask (%s): %08x\n", |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 976 | engine->name, I915_READ_IMR(engine)); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 977 | } |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 978 | i915_ring_seqno_info(m, engine); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 979 | } |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 980 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 981 | mutex_unlock(&dev->struct_mutex); |
| 982 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 983 | return 0; |
| 984 | } |
| 985 | |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 986 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
| 987 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 988 | struct drm_info_node *node = m->private; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 989 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 990 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 991 | int i, ret; |
| 992 | |
| 993 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 994 | if (ret) |
| 995 | return ret; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 996 | |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 997 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
| 998 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 999 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 1000 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1001 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
| 1002 | i, dev_priv->fence_regs[i].pin_count); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 1003 | if (obj == NULL) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1004 | seq_puts(m, "unused"); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 1005 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1006 | describe_obj(m, obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1007 | seq_putc(m, '\n'); |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 1008 | } |
| 1009 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1010 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 1011 | return 0; |
| 1012 | } |
| 1013 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 1014 | static int i915_hws_info(struct seq_file *m, void *data) |
| 1015 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1016 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 1017 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1018 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1019 | struct intel_engine_cs *engine; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 1020 | const u32 *hws; |
Chris Wilson | 4066c0a | 2010-10-29 21:00:54 +0100 | [diff] [blame] | 1021 | int i; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 1022 | |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 1023 | engine = &dev_priv->engine[(uintptr_t)node->info_ent->data]; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1024 | hws = engine->status_page.page_addr; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 1025 | if (hws == NULL) |
| 1026 | return 0; |
| 1027 | |
| 1028 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { |
| 1029 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 1030 | i * 4, |
| 1031 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); |
| 1032 | } |
| 1033 | return 0; |
| 1034 | } |
| 1035 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 1036 | static ssize_t |
| 1037 | i915_error_state_write(struct file *filp, |
| 1038 | const char __user *ubuf, |
| 1039 | size_t cnt, |
| 1040 | loff_t *ppos) |
| 1041 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1042 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 1043 | struct drm_device *dev = error_priv->dev; |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1044 | int ret; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 1045 | |
| 1046 | DRM_DEBUG_DRIVER("Resetting error state\n"); |
| 1047 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1048 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1049 | if (ret) |
| 1050 | return ret; |
| 1051 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 1052 | i915_destroy_error_state(dev); |
| 1053 | mutex_unlock(&dev->struct_mutex); |
| 1054 | |
| 1055 | return cnt; |
| 1056 | } |
| 1057 | |
| 1058 | static int i915_error_state_open(struct inode *inode, struct file *file) |
| 1059 | { |
| 1060 | struct drm_device *dev = inode->i_private; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 1061 | struct i915_error_state_file_priv *error_priv; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 1062 | |
| 1063 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); |
| 1064 | if (!error_priv) |
| 1065 | return -ENOMEM; |
| 1066 | |
| 1067 | error_priv->dev = dev; |
| 1068 | |
Mika Kuoppala | 95d5bfb | 2013-06-06 15:18:40 +0300 | [diff] [blame] | 1069 | i915_error_state_get(dev, error_priv); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 1070 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1071 | file->private_data = error_priv; |
| 1072 | |
| 1073 | return 0; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 1074 | } |
| 1075 | |
| 1076 | static int i915_error_state_release(struct inode *inode, struct file *file) |
| 1077 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1078 | struct i915_error_state_file_priv *error_priv = file->private_data; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 1079 | |
Mika Kuoppala | 95d5bfb | 2013-06-06 15:18:40 +0300 | [diff] [blame] | 1080 | i915_error_state_put(error_priv); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 1081 | kfree(error_priv); |
| 1082 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1083 | return 0; |
| 1084 | } |
| 1085 | |
| 1086 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
| 1087 | size_t count, loff_t *pos) |
| 1088 | { |
| 1089 | struct i915_error_state_file_priv *error_priv = file->private_data; |
| 1090 | struct drm_i915_error_state_buf error_str; |
| 1091 | loff_t tmp_pos = 0; |
| 1092 | ssize_t ret_count = 0; |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 1093 | int ret; |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1094 | |
Chris Wilson | 0a4cd7c | 2014-08-22 14:41:39 +0100 | [diff] [blame] | 1095 | ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos); |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 1096 | if (ret) |
| 1097 | return ret; |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1098 | |
Mika Kuoppala | fc16b48 | 2013-06-06 15:18:39 +0300 | [diff] [blame] | 1099 | ret = i915_error_state_to_str(&error_str, error_priv); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1100 | if (ret) |
| 1101 | goto out; |
| 1102 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1103 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
| 1104 | error_str.buf, |
| 1105 | error_str.bytes); |
| 1106 | |
| 1107 | if (ret_count < 0) |
| 1108 | ret = ret_count; |
| 1109 | else |
| 1110 | *pos = error_str.start + ret_count; |
| 1111 | out: |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 1112 | i915_error_state_buf_release(&error_str); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1113 | return ret ?: ret_count; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 1114 | } |
| 1115 | |
| 1116 | static const struct file_operations i915_error_state_fops = { |
| 1117 | .owner = THIS_MODULE, |
| 1118 | .open = i915_error_state_open, |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1119 | .read = i915_error_state_read, |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 1120 | .write = i915_error_state_write, |
| 1121 | .llseek = default_llseek, |
| 1122 | .release = i915_error_state_release, |
| 1123 | }; |
| 1124 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1125 | static int |
| 1126 | i915_next_seqno_get(void *data, u64 *val) |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1127 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1128 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1129 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1130 | int ret; |
| 1131 | |
| 1132 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1133 | if (ret) |
| 1134 | return ret; |
| 1135 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1136 | *val = dev_priv->next_seqno; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1137 | mutex_unlock(&dev->struct_mutex); |
| 1138 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1139 | return 0; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1140 | } |
| 1141 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1142 | static int |
| 1143 | i915_next_seqno_set(void *data, u64 val) |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1144 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1145 | struct drm_device *dev = data; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1146 | int ret; |
| 1147 | |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1148 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1149 | if (ret) |
| 1150 | return ret; |
| 1151 | |
Mika Kuoppala | e94fbaa | 2012-12-19 11:13:09 +0200 | [diff] [blame] | 1152 | ret = i915_gem_set_seqno(dev, val); |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1153 | mutex_unlock(&dev->struct_mutex); |
| 1154 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1155 | return ret; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1156 | } |
| 1157 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1158 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
| 1159 | i915_next_seqno_get, i915_next_seqno_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 1160 | "0x%llx\n"); |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1161 | |
Deepak S | adb4bd1 | 2014-03-31 11:30:02 +0530 | [diff] [blame] | 1162 | static int i915_frequency_info(struct seq_file *m, void *unused) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1163 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1164 | struct drm_info_node *node = m->private; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1165 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1166 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1167 | int ret = 0; |
| 1168 | |
| 1169 | intel_runtime_pm_get(dev_priv); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1170 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 1171 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 1172 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1173 | if (IS_GEN5(dev)) { |
| 1174 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
| 1175 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); |
| 1176 | |
| 1177 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); |
| 1178 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); |
| 1179 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> |
| 1180 | MEMSTAT_VID_SHIFT); |
| 1181 | seq_printf(m, "Current P-state: %d\n", |
| 1182 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 1183 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
| 1184 | u32 freq_sts; |
| 1185 | |
| 1186 | mutex_lock(&dev_priv->rps.hw_lock); |
| 1187 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
| 1188 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
| 1189 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); |
| 1190 | |
| 1191 | seq_printf(m, "actual GPU freq: %d MHz\n", |
| 1192 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); |
| 1193 | |
| 1194 | seq_printf(m, "current GPU freq: %d MHz\n", |
| 1195 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); |
| 1196 | |
| 1197 | seq_printf(m, "max GPU freq: %d MHz\n", |
| 1198 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
| 1199 | |
| 1200 | seq_printf(m, "min GPU freq: %d MHz\n", |
| 1201 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); |
| 1202 | |
| 1203 | seq_printf(m, "idle GPU freq: %d MHz\n", |
| 1204 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); |
| 1205 | |
| 1206 | seq_printf(m, |
| 1207 | "efficient (RPe) frequency: %d MHz\n", |
| 1208 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); |
| 1209 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 1210 | } else if (INTEL_INFO(dev)->gen >= 6) { |
Bob Paauwe | 3504056 | 2015-06-25 14:54:07 -0700 | [diff] [blame] | 1211 | u32 rp_state_limits; |
| 1212 | u32 gt_perf_status; |
| 1213 | u32 rp_state_cap; |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1214 | u32 rpmodectl, rpinclimit, rpdeclimit; |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1215 | u32 rpstat, cagf, reqf; |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1216 | u32 rpupei, rpcurup, rpprevup; |
| 1217 | u32 rpdownei, rpcurdown, rpprevdown; |
Paulo Zanoni | 9dd3c60 | 2014-08-01 18:14:48 -0300 | [diff] [blame] | 1218 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1219 | int max_freq; |
| 1220 | |
Bob Paauwe | 3504056 | 2015-06-25 14:54:07 -0700 | [diff] [blame] | 1221 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
| 1222 | if (IS_BROXTON(dev)) { |
| 1223 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
| 1224 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); |
| 1225 | } else { |
| 1226 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
| 1227 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
| 1228 | } |
| 1229 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1230 | /* RPSTAT1 is in the GT power well */ |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 1231 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1232 | if (ret) |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1233 | goto out; |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 1234 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 1235 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1236 | |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1237 | reqf = I915_READ(GEN6_RPNSWREQ); |
Akash Goel | 60260a5 | 2015-03-06 11:07:21 +0530 | [diff] [blame] | 1238 | if (IS_GEN9(dev)) |
| 1239 | reqf >>= 23; |
| 1240 | else { |
| 1241 | reqf &= ~GEN6_TURBO_DISABLE; |
| 1242 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 1243 | reqf >>= 24; |
| 1244 | else |
| 1245 | reqf >>= 25; |
| 1246 | } |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 1247 | reqf = intel_gpu_freq(dev_priv, reqf); |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1248 | |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1249 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
| 1250 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); |
| 1251 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); |
| 1252 | |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1253 | rpstat = I915_READ(GEN6_RPSTAT1); |
Akash Goel | d6cda9c | 2016-04-23 00:05:46 +0530 | [diff] [blame] | 1254 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
| 1255 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; |
| 1256 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; |
| 1257 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; |
| 1258 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; |
| 1259 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; |
Akash Goel | 60260a5 | 2015-03-06 11:07:21 +0530 | [diff] [blame] | 1260 | if (IS_GEN9(dev)) |
| 1261 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; |
| 1262 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 1263 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
| 1264 | else |
| 1265 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 1266 | cagf = intel_gpu_freq(dev_priv, cagf); |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1267 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 1268 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 1269 | mutex_unlock(&dev->struct_mutex); |
| 1270 | |
Paulo Zanoni | 9dd3c60 | 2014-08-01 18:14:48 -0300 | [diff] [blame] | 1271 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
| 1272 | pm_ier = I915_READ(GEN6_PMIER); |
| 1273 | pm_imr = I915_READ(GEN6_PMIMR); |
| 1274 | pm_isr = I915_READ(GEN6_PMISR); |
| 1275 | pm_iir = I915_READ(GEN6_PMIIR); |
| 1276 | pm_mask = I915_READ(GEN6_PMINTRMSK); |
| 1277 | } else { |
| 1278 | pm_ier = I915_READ(GEN8_GT_IER(2)); |
| 1279 | pm_imr = I915_READ(GEN8_GT_IMR(2)); |
| 1280 | pm_isr = I915_READ(GEN8_GT_ISR(2)); |
| 1281 | pm_iir = I915_READ(GEN8_GT_IIR(2)); |
| 1282 | pm_mask = I915_READ(GEN6_PMINTRMSK); |
| 1283 | } |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1284 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
Paulo Zanoni | 9dd3c60 | 2014-08-01 18:14:48 -0300 | [diff] [blame] | 1285 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1286 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1287 | seq_printf(m, "Render p-state ratio: %d\n", |
Akash Goel | 60260a5 | 2015-03-06 11:07:21 +0530 | [diff] [blame] | 1288 | (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1289 | seq_printf(m, "Render p-state VID: %d\n", |
| 1290 | gt_perf_status & 0xff); |
| 1291 | seq_printf(m, "Render p-state limit: %d\n", |
| 1292 | rp_state_limits & 0xff); |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1293 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
| 1294 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); |
| 1295 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); |
| 1296 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1297 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 1298 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
Akash Goel | d6cda9c | 2016-04-23 00:05:46 +0530 | [diff] [blame] | 1299 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
| 1300 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); |
| 1301 | seq_printf(m, "RP CUR UP: %d (%dus)\n", |
| 1302 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); |
| 1303 | seq_printf(m, "RP PREV UP: %d (%dus)\n", |
| 1304 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); |
Chris Wilson | d86ed34 | 2015-04-27 13:41:19 +0100 | [diff] [blame] | 1305 | seq_printf(m, "Up threshold: %d%%\n", |
| 1306 | dev_priv->rps.up_threshold); |
| 1307 | |
Akash Goel | d6cda9c | 2016-04-23 00:05:46 +0530 | [diff] [blame] | 1308 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
| 1309 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); |
| 1310 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", |
| 1311 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); |
| 1312 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", |
| 1313 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); |
Chris Wilson | d86ed34 | 2015-04-27 13:41:19 +0100 | [diff] [blame] | 1314 | seq_printf(m, "Down threshold: %d%%\n", |
| 1315 | dev_priv->rps.down_threshold); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1316 | |
Bob Paauwe | 3504056 | 2015-06-25 14:54:07 -0700 | [diff] [blame] | 1317 | max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 : |
| 1318 | rp_state_cap >> 16) & 0xff; |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 1319 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
| 1320 | GEN9_FREQ_SCALER : 1); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1321 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 1322 | intel_gpu_freq(dev_priv, max_freq)); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1323 | |
| 1324 | max_freq = (rp_state_cap & 0xff00) >> 8; |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 1325 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
| 1326 | GEN9_FREQ_SCALER : 1); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1327 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 1328 | intel_gpu_freq(dev_priv, max_freq)); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1329 | |
Bob Paauwe | 3504056 | 2015-06-25 14:54:07 -0700 | [diff] [blame] | 1330 | max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 : |
| 1331 | rp_state_cap >> 0) & 0xff; |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 1332 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
| 1333 | GEN9_FREQ_SCALER : 1); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1334 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 1335 | intel_gpu_freq(dev_priv, max_freq)); |
Ben Widawsky | 31c7738 | 2013-04-05 14:29:22 -0700 | [diff] [blame] | 1336 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 1337 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
Chris Wilson | aed242f | 2015-03-18 09:48:21 +0000 | [diff] [blame] | 1338 | |
Chris Wilson | d86ed34 | 2015-04-27 13:41:19 +0100 | [diff] [blame] | 1339 | seq_printf(m, "Current freq: %d MHz\n", |
| 1340 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); |
| 1341 | seq_printf(m, "Actual freq: %d MHz\n", cagf); |
Chris Wilson | aed242f | 2015-03-18 09:48:21 +0000 | [diff] [blame] | 1342 | seq_printf(m, "Idle freq: %d MHz\n", |
| 1343 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); |
Chris Wilson | d86ed34 | 2015-04-27 13:41:19 +0100 | [diff] [blame] | 1344 | seq_printf(m, "Min freq: %d MHz\n", |
| 1345 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); |
| 1346 | seq_printf(m, "Max freq: %d MHz\n", |
| 1347 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
| 1348 | seq_printf(m, |
| 1349 | "efficient (RPe) frequency: %d MHz\n", |
| 1350 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1351 | } else { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1352 | seq_puts(m, "no P-state info available\n"); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1353 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1354 | |
Mika Kahola | 1170f28 | 2015-09-25 14:00:32 +0300 | [diff] [blame] | 1355 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq); |
| 1356 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); |
| 1357 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); |
| 1358 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1359 | out: |
| 1360 | intel_runtime_pm_put(dev_priv); |
| 1361 | return ret; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1362 | } |
| 1363 | |
Chris Wilson | f654449a | 2015-01-26 18:03:04 +0200 | [diff] [blame] | 1364 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
| 1365 | { |
| 1366 | struct drm_info_node *node = m->private; |
Mika Kuoppala | ebbc754 | 2015-02-05 18:41:48 +0200 | [diff] [blame] | 1367 | struct drm_device *dev = node->minor->dev; |
| 1368 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1369 | struct intel_engine_cs *engine; |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 1370 | u64 acthd[I915_NUM_ENGINES]; |
| 1371 | u32 seqno[I915_NUM_ENGINES]; |
Mika Kuoppala | 61642ff | 2015-12-01 17:56:12 +0200 | [diff] [blame] | 1372 | u32 instdone[I915_NUM_INSTDONE_REG]; |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 1373 | enum intel_engine_id id; |
| 1374 | int j; |
Chris Wilson | f654449a | 2015-01-26 18:03:04 +0200 | [diff] [blame] | 1375 | |
| 1376 | if (!i915.enable_hangcheck) { |
| 1377 | seq_printf(m, "Hangcheck disabled\n"); |
| 1378 | return 0; |
| 1379 | } |
| 1380 | |
Mika Kuoppala | ebbc754 | 2015-02-05 18:41:48 +0200 | [diff] [blame] | 1381 | intel_runtime_pm_get(dev_priv); |
| 1382 | |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 1383 | for_each_engine_id(engine, dev_priv, id) { |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 1384 | acthd[id] = intel_ring_get_active_head(engine); |
Chris Wilson | c04e0f3 | 2016-04-09 10:57:54 +0100 | [diff] [blame] | 1385 | seqno[id] = engine->get_seqno(engine); |
Mika Kuoppala | ebbc754 | 2015-02-05 18:41:48 +0200 | [diff] [blame] | 1386 | } |
| 1387 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1388 | i915_get_extra_instdone(dev_priv, instdone); |
Mika Kuoppala | 61642ff | 2015-12-01 17:56:12 +0200 | [diff] [blame] | 1389 | |
Mika Kuoppala | ebbc754 | 2015-02-05 18:41:48 +0200 | [diff] [blame] | 1390 | intel_runtime_pm_put(dev_priv); |
| 1391 | |
Chris Wilson | f654449a | 2015-01-26 18:03:04 +0200 | [diff] [blame] | 1392 | if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { |
| 1393 | seq_printf(m, "Hangcheck active, fires in %dms\n", |
| 1394 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - |
| 1395 | jiffies)); |
| 1396 | } else |
| 1397 | seq_printf(m, "Hangcheck inactive\n"); |
| 1398 | |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 1399 | for_each_engine_id(engine, dev_priv, id) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1400 | seq_printf(m, "%s:\n", engine->name); |
Chris Wilson | 14fd0d6 | 2016-04-07 07:29:10 +0100 | [diff] [blame] | 1401 | seq_printf(m, "\tseqno = %x [current %x, last %x]\n", |
| 1402 | engine->hangcheck.seqno, |
| 1403 | seqno[id], |
| 1404 | engine->last_submitted_seqno); |
Chris Wilson | 12471ba | 2016-04-09 10:57:55 +0100 | [diff] [blame] | 1405 | seq_printf(m, "\tuser interrupts = %x [current %x]\n", |
| 1406 | engine->hangcheck.user_interrupts, |
| 1407 | READ_ONCE(engine->user_interrupts)); |
Chris Wilson | f654449a | 2015-01-26 18:03:04 +0200 | [diff] [blame] | 1408 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1409 | (long long)engine->hangcheck.acthd, |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 1410 | (long long)acthd[id]); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1411 | seq_printf(m, "\tscore = %d\n", engine->hangcheck.score); |
| 1412 | seq_printf(m, "\taction = %d\n", engine->hangcheck.action); |
Mika Kuoppala | 61642ff | 2015-12-01 17:56:12 +0200 | [diff] [blame] | 1413 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1414 | if (engine->id == RCS) { |
Mika Kuoppala | 61642ff | 2015-12-01 17:56:12 +0200 | [diff] [blame] | 1415 | seq_puts(m, "\tinstdone read ="); |
| 1416 | |
| 1417 | for (j = 0; j < I915_NUM_INSTDONE_REG; j++) |
| 1418 | seq_printf(m, " 0x%08x", instdone[j]); |
| 1419 | |
| 1420 | seq_puts(m, "\n\tinstdone accu ="); |
| 1421 | |
| 1422 | for (j = 0; j < I915_NUM_INSTDONE_REG; j++) |
| 1423 | seq_printf(m, " 0x%08x", |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1424 | engine->hangcheck.instdone[j]); |
Mika Kuoppala | 61642ff | 2015-12-01 17:56:12 +0200 | [diff] [blame] | 1425 | |
| 1426 | seq_puts(m, "\n"); |
| 1427 | } |
Chris Wilson | f654449a | 2015-01-26 18:03:04 +0200 | [diff] [blame] | 1428 | } |
| 1429 | |
| 1430 | return 0; |
| 1431 | } |
| 1432 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1433 | static int ironlake_drpc_info(struct seq_file *m) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1434 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1435 | struct drm_info_node *node = m->private; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1436 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1437 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1438 | u32 rgvmodectl, rstdbyctl; |
| 1439 | u16 crstandvid; |
| 1440 | int ret; |
| 1441 | |
| 1442 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1443 | if (ret) |
| 1444 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1445 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1446 | |
| 1447 | rgvmodectl = I915_READ(MEMMODECTL); |
| 1448 | rstdbyctl = I915_READ(RSTDBYCTL); |
| 1449 | crstandvid = I915_READ16(CRSTANDVID); |
| 1450 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1451 | intel_runtime_pm_put(dev_priv); |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1452 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1453 | |
Jani Nikula | 742f491 | 2015-09-03 11:16:09 +0300 | [diff] [blame] | 1454 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1455 | seq_printf(m, "Boost freq: %d\n", |
| 1456 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> |
| 1457 | MEMMODE_BOOST_FREQ_SHIFT); |
| 1458 | seq_printf(m, "HW control enabled: %s\n", |
Jani Nikula | 742f491 | 2015-09-03 11:16:09 +0300 | [diff] [blame] | 1459 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1460 | seq_printf(m, "SW control enabled: %s\n", |
Jani Nikula | 742f491 | 2015-09-03 11:16:09 +0300 | [diff] [blame] | 1461 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1462 | seq_printf(m, "Gated voltage change: %s\n", |
Jani Nikula | 742f491 | 2015-09-03 11:16:09 +0300 | [diff] [blame] | 1463 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1464 | seq_printf(m, "Starting frequency: P%d\n", |
| 1465 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1466 | seq_printf(m, "Max P-state: P%d\n", |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1467 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1468 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
| 1469 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); |
| 1470 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); |
| 1471 | seq_printf(m, "Render standby enabled: %s\n", |
Jani Nikula | 742f491 | 2015-09-03 11:16:09 +0300 | [diff] [blame] | 1472 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1473 | seq_puts(m, "Current RS state: "); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1474 | switch (rstdbyctl & RSX_STATUS_MASK) { |
| 1475 | case RSX_STATUS_ON: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1476 | seq_puts(m, "on\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1477 | break; |
| 1478 | case RSX_STATUS_RC1: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1479 | seq_puts(m, "RC1\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1480 | break; |
| 1481 | case RSX_STATUS_RC1E: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1482 | seq_puts(m, "RC1E\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1483 | break; |
| 1484 | case RSX_STATUS_RS1: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1485 | seq_puts(m, "RS1\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1486 | break; |
| 1487 | case RSX_STATUS_RS2: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1488 | seq_puts(m, "RS2 (RC6)\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1489 | break; |
| 1490 | case RSX_STATUS_RS3: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1491 | seq_puts(m, "RC3 (RC6+)\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1492 | break; |
| 1493 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1494 | seq_puts(m, "unknown\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1495 | break; |
| 1496 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1497 | |
| 1498 | return 0; |
| 1499 | } |
| 1500 | |
Mika Kuoppala | f65367b | 2015-01-16 11:34:42 +0200 | [diff] [blame] | 1501 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
Chris Wilson | b2cff0d | 2015-01-16 11:34:37 +0200 | [diff] [blame] | 1502 | { |
| 1503 | struct drm_info_node *node = m->private; |
| 1504 | struct drm_device *dev = node->minor->dev; |
| 1505 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1506 | struct intel_uncore_forcewake_domain *fw_domain; |
Chris Wilson | b2cff0d | 2015-01-16 11:34:37 +0200 | [diff] [blame] | 1507 | |
| 1508 | spin_lock_irq(&dev_priv->uncore.lock); |
Tvrtko Ursulin | 33c582c | 2016-04-07 17:04:33 +0100 | [diff] [blame] | 1509 | for_each_fw_domain(fw_domain, dev_priv) { |
Chris Wilson | b2cff0d | 2015-01-16 11:34:37 +0200 | [diff] [blame] | 1510 | seq_printf(m, "%s.wake_count = %u\n", |
Tvrtko Ursulin | 33c582c | 2016-04-07 17:04:33 +0100 | [diff] [blame] | 1511 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
Chris Wilson | b2cff0d | 2015-01-16 11:34:37 +0200 | [diff] [blame] | 1512 | fw_domain->wake_count); |
| 1513 | } |
| 1514 | spin_unlock_irq(&dev_priv->uncore.lock); |
| 1515 | |
| 1516 | return 0; |
| 1517 | } |
| 1518 | |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1519 | static int vlv_drpc_info(struct seq_file *m) |
| 1520 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1521 | struct drm_info_node *node = m->private; |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1522 | struct drm_device *dev = node->minor->dev; |
| 1523 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 6b312cd | 2014-11-19 20:07:42 +0200 | [diff] [blame] | 1524 | u32 rpmodectl1, rcctl1, pw_status; |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1525 | |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 1526 | intel_runtime_pm_get(dev_priv); |
| 1527 | |
Ville Syrjälä | 6b312cd | 2014-11-19 20:07:42 +0200 | [diff] [blame] | 1528 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1529 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
| 1530 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
| 1531 | |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 1532 | intel_runtime_pm_put(dev_priv); |
| 1533 | |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1534 | seq_printf(m, "Video Turbo Mode: %s\n", |
| 1535 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); |
| 1536 | seq_printf(m, "Turbo enabled: %s\n", |
| 1537 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); |
| 1538 | seq_printf(m, "HW control enabled: %s\n", |
| 1539 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); |
| 1540 | seq_printf(m, "SW control enabled: %s\n", |
| 1541 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == |
| 1542 | GEN6_RP_MEDIA_SW_MODE)); |
| 1543 | seq_printf(m, "RC6 Enabled: %s\n", |
| 1544 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | |
| 1545 | GEN6_RC_CTL_EI_MODE(1)))); |
| 1546 | seq_printf(m, "Render Power Well: %s\n", |
Ville Syrjälä | 6b312cd | 2014-11-19 20:07:42 +0200 | [diff] [blame] | 1547 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1548 | seq_printf(m, "Media Power Well: %s\n", |
Ville Syrjälä | 6b312cd | 2014-11-19 20:07:42 +0200 | [diff] [blame] | 1549 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1550 | |
Imre Deak | 9cc19be | 2014-04-14 20:24:24 +0300 | [diff] [blame] | 1551 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
| 1552 | I915_READ(VLV_GT_RENDER_RC6)); |
| 1553 | seq_printf(m, "Media RC6 residency since boot: %u\n", |
| 1554 | I915_READ(VLV_GT_MEDIA_RC6)); |
| 1555 | |
Mika Kuoppala | f65367b | 2015-01-16 11:34:42 +0200 | [diff] [blame] | 1556 | return i915_forcewake_domains(m, NULL); |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1557 | } |
| 1558 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1559 | static int gen6_drpc_info(struct seq_file *m) |
| 1560 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1561 | struct drm_info_node *node = m->private; |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1562 | struct drm_device *dev = node->minor->dev; |
| 1563 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | ecd8fae | 2012-09-26 10:34:02 -0700 | [diff] [blame] | 1564 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
Daniel Vetter | 93b525d | 2012-01-25 13:52:43 +0100 | [diff] [blame] | 1565 | unsigned forcewake_count; |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 1566 | int count = 0, ret; |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1567 | |
| 1568 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1569 | if (ret) |
| 1570 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1571 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1572 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1573 | spin_lock_irq(&dev_priv->uncore.lock); |
Chris Wilson | b2cff0d | 2015-01-16 11:34:37 +0200 | [diff] [blame] | 1574 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1575 | spin_unlock_irq(&dev_priv->uncore.lock); |
Daniel Vetter | 93b525d | 2012-01-25 13:52:43 +0100 | [diff] [blame] | 1576 | |
| 1577 | if (forcewake_count) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1578 | seq_puts(m, "RC information inaccurate because somebody " |
| 1579 | "holds a forcewake reference \n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1580 | } else { |
| 1581 | /* NB: we cannot use forcewake, else we read the wrong values */ |
| 1582 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) |
| 1583 | udelay(10); |
| 1584 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); |
| 1585 | } |
| 1586 | |
Ville Syrjälä | 75aa3f6 | 2015-10-22 15:34:56 +0300 | [diff] [blame] | 1587 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
Chris Wilson | ed71f1b | 2013-07-19 20:36:56 +0100 | [diff] [blame] | 1588 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1589 | |
| 1590 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
| 1591 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
| 1592 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | 44cbd33 | 2012-11-06 14:36:36 +0000 | [diff] [blame] | 1593 | mutex_lock(&dev_priv->rps.hw_lock); |
| 1594 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
| 1595 | mutex_unlock(&dev_priv->rps.hw_lock); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1596 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1597 | intel_runtime_pm_put(dev_priv); |
| 1598 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1599 | seq_printf(m, "Video Turbo Mode: %s\n", |
| 1600 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); |
| 1601 | seq_printf(m, "HW control enabled: %s\n", |
| 1602 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); |
| 1603 | seq_printf(m, "SW control enabled: %s\n", |
| 1604 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == |
| 1605 | GEN6_RP_MEDIA_SW_MODE)); |
Eric Anholt | fff24e2 | 2012-01-23 16:14:05 -0800 | [diff] [blame] | 1606 | seq_printf(m, "RC1e Enabled: %s\n", |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1607 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
| 1608 | seq_printf(m, "RC6 Enabled: %s\n", |
| 1609 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); |
| 1610 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
| 1611 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); |
| 1612 | seq_printf(m, "Deepest RC6 Enabled: %s\n", |
| 1613 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1614 | seq_puts(m, "Current RC state: "); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1615 | switch (gt_core_status & GEN6_RCn_MASK) { |
| 1616 | case GEN6_RC0: |
| 1617 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1618 | seq_puts(m, "Core Power Down\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1619 | else |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1620 | seq_puts(m, "on\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1621 | break; |
| 1622 | case GEN6_RC3: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1623 | seq_puts(m, "RC3\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1624 | break; |
| 1625 | case GEN6_RC6: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1626 | seq_puts(m, "RC6\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1627 | break; |
| 1628 | case GEN6_RC7: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1629 | seq_puts(m, "RC7\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1630 | break; |
| 1631 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1632 | seq_puts(m, "Unknown\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1633 | break; |
| 1634 | } |
| 1635 | |
| 1636 | seq_printf(m, "Core Power Down: %s\n", |
| 1637 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); |
Ben Widawsky | cce66a2 | 2012-03-27 18:59:38 -0700 | [diff] [blame] | 1638 | |
| 1639 | /* Not exactly sure what this is */ |
| 1640 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", |
| 1641 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); |
| 1642 | seq_printf(m, "RC6 residency since boot: %u\n", |
| 1643 | I915_READ(GEN6_GT_GFX_RC6)); |
| 1644 | seq_printf(m, "RC6+ residency since boot: %u\n", |
| 1645 | I915_READ(GEN6_GT_GFX_RC6p)); |
| 1646 | seq_printf(m, "RC6++ residency since boot: %u\n", |
| 1647 | I915_READ(GEN6_GT_GFX_RC6pp)); |
| 1648 | |
Ben Widawsky | ecd8fae | 2012-09-26 10:34:02 -0700 | [diff] [blame] | 1649 | seq_printf(m, "RC6 voltage: %dmV\n", |
| 1650 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); |
| 1651 | seq_printf(m, "RC6+ voltage: %dmV\n", |
| 1652 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); |
| 1653 | seq_printf(m, "RC6++ voltage: %dmV\n", |
| 1654 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1655 | return 0; |
| 1656 | } |
| 1657 | |
| 1658 | static int i915_drpc_info(struct seq_file *m, void *unused) |
| 1659 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1660 | struct drm_info_node *node = m->private; |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1661 | struct drm_device *dev = node->minor->dev; |
| 1662 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 1663 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1664 | return vlv_drpc_info(m); |
Vedang Patel | ac66cf4 | 2014-08-26 10:42:51 -0700 | [diff] [blame] | 1665 | else if (INTEL_INFO(dev)->gen >= 6) |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1666 | return gen6_drpc_info(m); |
| 1667 | else |
| 1668 | return ironlake_drpc_info(m); |
| 1669 | } |
| 1670 | |
Daniel Vetter | 9a85178 | 2015-06-18 10:30:22 +0200 | [diff] [blame] | 1671 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
| 1672 | { |
| 1673 | struct drm_info_node *node = m->private; |
| 1674 | struct drm_device *dev = node->minor->dev; |
| 1675 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1676 | |
| 1677 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", |
| 1678 | dev_priv->fb_tracking.busy_bits); |
| 1679 | |
| 1680 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", |
| 1681 | dev_priv->fb_tracking.flip_bits); |
| 1682 | |
| 1683 | return 0; |
| 1684 | } |
| 1685 | |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1686 | static int i915_fbc_status(struct seq_file *m, void *unused) |
| 1687 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1688 | struct drm_info_node *node = m->private; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1689 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1690 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1691 | |
Daniel Vetter | 3a77c4c | 2014-01-10 08:50:12 +0100 | [diff] [blame] | 1692 | if (!HAS_FBC(dev)) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1693 | seq_puts(m, "FBC unsupported on this chipset\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1694 | return 0; |
| 1695 | } |
| 1696 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1697 | intel_runtime_pm_get(dev_priv); |
Paulo Zanoni | 25ad93f | 2015-07-02 19:25:10 -0300 | [diff] [blame] | 1698 | mutex_lock(&dev_priv->fbc.lock); |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1699 | |
Paulo Zanoni | 0e631ad | 2015-10-14 17:45:36 -0300 | [diff] [blame] | 1700 | if (intel_fbc_is_active(dev_priv)) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1701 | seq_puts(m, "FBC enabled\n"); |
Paulo Zanoni | 2e8144a | 2015-06-12 14:36:20 -0300 | [diff] [blame] | 1702 | else |
| 1703 | seq_printf(m, "FBC disabled: %s\n", |
Paulo Zanoni | bf6189c | 2015-10-27 14:50:03 -0200 | [diff] [blame] | 1704 | dev_priv->fbc.no_fbc_reason); |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1705 | |
Paulo Zanoni | 31b9df1 | 2015-06-12 14:36:18 -0300 | [diff] [blame] | 1706 | if (INTEL_INFO(dev_priv)->gen >= 7) |
| 1707 | seq_printf(m, "Compressing: %s\n", |
| 1708 | yesno(I915_READ(FBC_STATUS2) & |
| 1709 | FBC_COMPRESSION_MASK)); |
| 1710 | |
Paulo Zanoni | 25ad93f | 2015-07-02 19:25:10 -0300 | [diff] [blame] | 1711 | mutex_unlock(&dev_priv->fbc.lock); |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1712 | intel_runtime_pm_put(dev_priv); |
| 1713 | |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1714 | return 0; |
| 1715 | } |
| 1716 | |
Rodrigo Vivi | da46f93 | 2014-08-01 02:04:45 -0700 | [diff] [blame] | 1717 | static int i915_fbc_fc_get(void *data, u64 *val) |
| 1718 | { |
| 1719 | struct drm_device *dev = data; |
| 1720 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1721 | |
| 1722 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) |
| 1723 | return -ENODEV; |
| 1724 | |
Rodrigo Vivi | da46f93 | 2014-08-01 02:04:45 -0700 | [diff] [blame] | 1725 | *val = dev_priv->fbc.false_color; |
Rodrigo Vivi | da46f93 | 2014-08-01 02:04:45 -0700 | [diff] [blame] | 1726 | |
| 1727 | return 0; |
| 1728 | } |
| 1729 | |
| 1730 | static int i915_fbc_fc_set(void *data, u64 val) |
| 1731 | { |
| 1732 | struct drm_device *dev = data; |
| 1733 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1734 | u32 reg; |
| 1735 | |
| 1736 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) |
| 1737 | return -ENODEV; |
| 1738 | |
Paulo Zanoni | 25ad93f | 2015-07-02 19:25:10 -0300 | [diff] [blame] | 1739 | mutex_lock(&dev_priv->fbc.lock); |
Rodrigo Vivi | da46f93 | 2014-08-01 02:04:45 -0700 | [diff] [blame] | 1740 | |
| 1741 | reg = I915_READ(ILK_DPFC_CONTROL); |
| 1742 | dev_priv->fbc.false_color = val; |
| 1743 | |
| 1744 | I915_WRITE(ILK_DPFC_CONTROL, val ? |
| 1745 | (reg | FBC_CTL_FALSE_COLOR) : |
| 1746 | (reg & ~FBC_CTL_FALSE_COLOR)); |
| 1747 | |
Paulo Zanoni | 25ad93f | 2015-07-02 19:25:10 -0300 | [diff] [blame] | 1748 | mutex_unlock(&dev_priv->fbc.lock); |
Rodrigo Vivi | da46f93 | 2014-08-01 02:04:45 -0700 | [diff] [blame] | 1749 | return 0; |
| 1750 | } |
| 1751 | |
| 1752 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, |
| 1753 | i915_fbc_fc_get, i915_fbc_fc_set, |
| 1754 | "%llu\n"); |
| 1755 | |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1756 | static int i915_ips_status(struct seq_file *m, void *unused) |
| 1757 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1758 | struct drm_info_node *node = m->private; |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1759 | struct drm_device *dev = node->minor->dev; |
| 1760 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1761 | |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 1762 | if (!HAS_IPS(dev)) { |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1763 | seq_puts(m, "not supported\n"); |
| 1764 | return 0; |
| 1765 | } |
| 1766 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1767 | intel_runtime_pm_get(dev_priv); |
| 1768 | |
Rodrigo Vivi | 0eaa53f | 2014-06-30 04:45:01 -0700 | [diff] [blame] | 1769 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
| 1770 | yesno(i915.enable_ips)); |
| 1771 | |
| 1772 | if (INTEL_INFO(dev)->gen >= 8) { |
| 1773 | seq_puts(m, "Currently: unknown\n"); |
| 1774 | } else { |
| 1775 | if (I915_READ(IPS_CTL) & IPS_ENABLE) |
| 1776 | seq_puts(m, "Currently: enabled\n"); |
| 1777 | else |
| 1778 | seq_puts(m, "Currently: disabled\n"); |
| 1779 | } |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1780 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1781 | intel_runtime_pm_put(dev_priv); |
| 1782 | |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1783 | return 0; |
| 1784 | } |
| 1785 | |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1786 | static int i915_sr_status(struct seq_file *m, void *unused) |
| 1787 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1788 | struct drm_info_node *node = m->private; |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1789 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1790 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1791 | bool sr_enabled = false; |
| 1792 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1793 | intel_runtime_pm_get(dev_priv); |
| 1794 | |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 1795 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 5ba2aaa | 2010-08-19 18:04:08 +0100 | [diff] [blame] | 1796 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
Ander Conselvan de Oliveira | 77b6455 | 2015-06-02 14:17:47 +0300 | [diff] [blame] | 1797 | else if (IS_CRESTLINE(dev) || IS_G4X(dev) || |
| 1798 | IS_I945G(dev) || IS_I945GM(dev)) |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1799 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
| 1800 | else if (IS_I915GM(dev)) |
| 1801 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
| 1802 | else if (IS_PINEVIEW(dev)) |
| 1803 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 1804 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Ander Conselvan de Oliveira | 77b6455 | 2015-06-02 14:17:47 +0300 | [diff] [blame] | 1805 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1806 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1807 | intel_runtime_pm_put(dev_priv); |
| 1808 | |
Chris Wilson | 5ba2aaa | 2010-08-19 18:04:08 +0100 | [diff] [blame] | 1809 | seq_printf(m, "self-refresh: %s\n", |
| 1810 | sr_enabled ? "enabled" : "disabled"); |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1811 | |
| 1812 | return 0; |
| 1813 | } |
| 1814 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1815 | static int i915_emon_status(struct seq_file *m, void *unused) |
| 1816 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1817 | struct drm_info_node *node = m->private; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1818 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1819 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1820 | unsigned long temp, chipset, gfx; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1821 | int ret; |
| 1822 | |
Chris Wilson | 582be6b | 2012-04-30 19:35:02 +0100 | [diff] [blame] | 1823 | if (!IS_GEN5(dev)) |
| 1824 | return -ENODEV; |
| 1825 | |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1826 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1827 | if (ret) |
| 1828 | return ret; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1829 | |
| 1830 | temp = i915_mch_val(dev_priv); |
| 1831 | chipset = i915_chipset_val(dev_priv); |
| 1832 | gfx = i915_gfx_val(dev_priv); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1833 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1834 | |
| 1835 | seq_printf(m, "GMCH temp: %ld\n", temp); |
| 1836 | seq_printf(m, "Chipset power: %ld\n", chipset); |
| 1837 | seq_printf(m, "GFX power: %ld\n", gfx); |
| 1838 | seq_printf(m, "Total power: %ld\n", chipset + gfx); |
| 1839 | |
| 1840 | return 0; |
| 1841 | } |
| 1842 | |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1843 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
| 1844 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1845 | struct drm_info_node *node = m->private; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1846 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1847 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1848 | int ret = 0; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1849 | int gpu_freq, ia_freq; |
Akash Goel | f936ec3 | 2015-06-29 14:50:22 +0530 | [diff] [blame] | 1850 | unsigned int max_gpu_freq, min_gpu_freq; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1851 | |
Akash Goel | 97d3308 | 2015-06-29 14:50:23 +0530 | [diff] [blame] | 1852 | if (!HAS_CORE_RING_FREQ(dev)) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1853 | seq_puts(m, "unsupported on this chipset\n"); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1854 | return 0; |
| 1855 | } |
| 1856 | |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1857 | intel_runtime_pm_get(dev_priv); |
| 1858 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 1859 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 1860 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1861 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1862 | if (ret) |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1863 | goto out; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1864 | |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 1865 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
Akash Goel | f936ec3 | 2015-06-29 14:50:22 +0530 | [diff] [blame] | 1866 | /* Convert GT frequency to 50 HZ units */ |
| 1867 | min_gpu_freq = |
| 1868 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; |
| 1869 | max_gpu_freq = |
| 1870 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; |
| 1871 | } else { |
| 1872 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; |
| 1873 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; |
| 1874 | } |
| 1875 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1876 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1877 | |
Akash Goel | f936ec3 | 2015-06-29 14:50:22 +0530 | [diff] [blame] | 1878 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 1879 | ia_freq = gpu_freq; |
| 1880 | sandybridge_pcode_read(dev_priv, |
| 1881 | GEN6_PCODE_READ_MIN_FREQ_TABLE, |
| 1882 | &ia_freq); |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 1883 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
Akash Goel | f936ec3 | 2015-06-29 14:50:22 +0530 | [diff] [blame] | 1884 | intel_gpu_freq(dev_priv, (gpu_freq * |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 1885 | (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
| 1886 | GEN9_FREQ_SCALER : 1))), |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 1887 | ((ia_freq >> 0) & 0xff) * 100, |
| 1888 | ((ia_freq >> 8) & 0xff) * 100); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1889 | } |
| 1890 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1891 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1892 | |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1893 | out: |
| 1894 | intel_runtime_pm_put(dev_priv); |
| 1895 | return ret; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1896 | } |
| 1897 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1898 | static int i915_opregion(struct seq_file *m, void *unused) |
| 1899 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1900 | struct drm_info_node *node = m->private; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1901 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1902 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1903 | struct intel_opregion *opregion = &dev_priv->opregion; |
| 1904 | int ret; |
| 1905 | |
| 1906 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1907 | if (ret) |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1908 | goto out; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1909 | |
Jani Nikula | 2455a8e | 2015-12-14 12:50:53 +0200 | [diff] [blame] | 1910 | if (opregion->header) |
| 1911 | seq_write(m, opregion->header, OPREGION_SIZE); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1912 | |
| 1913 | mutex_unlock(&dev->struct_mutex); |
| 1914 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1915 | out: |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1916 | return 0; |
| 1917 | } |
| 1918 | |
Jani Nikula | ada8f95 | 2015-12-15 13:17:12 +0200 | [diff] [blame] | 1919 | static int i915_vbt(struct seq_file *m, void *unused) |
| 1920 | { |
| 1921 | struct drm_info_node *node = m->private; |
| 1922 | struct drm_device *dev = node->minor->dev; |
| 1923 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1924 | struct intel_opregion *opregion = &dev_priv->opregion; |
| 1925 | |
| 1926 | if (opregion->vbt) |
| 1927 | seq_write(m, opregion->vbt, opregion->vbt_size); |
| 1928 | |
| 1929 | return 0; |
| 1930 | } |
| 1931 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1932 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
| 1933 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1934 | struct drm_info_node *node = m->private; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1935 | struct drm_device *dev = node->minor->dev; |
Namrta Salonie | b13b840 | 2015-11-27 13:43:11 +0530 | [diff] [blame] | 1936 | struct intel_framebuffer *fbdev_fb = NULL; |
Daniel Vetter | 3a58ee1 | 2015-07-10 19:02:51 +0200 | [diff] [blame] | 1937 | struct drm_framebuffer *drm_fb; |
Chris Wilson | 188c1ab | 2016-04-03 14:14:20 +0100 | [diff] [blame] | 1938 | int ret; |
| 1939 | |
| 1940 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1941 | if (ret) |
| 1942 | return ret; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1943 | |
Daniel Vetter | 0695726 | 2015-08-10 13:34:08 +0200 | [diff] [blame] | 1944 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
Namrta Salonie | b13b840 | 2015-11-27 13:43:11 +0530 | [diff] [blame] | 1945 | if (to_i915(dev)->fbdev) { |
| 1946 | fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1947 | |
Namrta Salonie | b13b840 | 2015-11-27 13:43:11 +0530 | [diff] [blame] | 1948 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
| 1949 | fbdev_fb->base.width, |
| 1950 | fbdev_fb->base.height, |
| 1951 | fbdev_fb->base.depth, |
| 1952 | fbdev_fb->base.bits_per_pixel, |
| 1953 | fbdev_fb->base.modifier[0], |
Dave Airlie | 747a598 | 2016-04-15 15:10:35 +1000 | [diff] [blame] | 1954 | drm_framebuffer_read_refcount(&fbdev_fb->base)); |
Namrta Salonie | b13b840 | 2015-11-27 13:43:11 +0530 | [diff] [blame] | 1955 | describe_obj(m, fbdev_fb->obj); |
| 1956 | seq_putc(m, '\n'); |
| 1957 | } |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1958 | #endif |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1959 | |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1960 | mutex_lock(&dev->mode_config.fb_lock); |
Daniel Vetter | 3a58ee1 | 2015-07-10 19:02:51 +0200 | [diff] [blame] | 1961 | drm_for_each_fb(drm_fb, dev) { |
Namrta Salonie | b13b840 | 2015-11-27 13:43:11 +0530 | [diff] [blame] | 1962 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
| 1963 | if (fb == fbdev_fb) |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1964 | continue; |
| 1965 | |
Tvrtko Ursulin | c1ca506 | 2015-02-10 17:16:07 +0000 | [diff] [blame] | 1966 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1967 | fb->base.width, |
| 1968 | fb->base.height, |
| 1969 | fb->base.depth, |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1970 | fb->base.bits_per_pixel, |
Tvrtko Ursulin | c1ca506 | 2015-02-10 17:16:07 +0000 | [diff] [blame] | 1971 | fb->base.modifier[0], |
Dave Airlie | 747a598 | 2016-04-15 15:10:35 +1000 | [diff] [blame] | 1972 | drm_framebuffer_read_refcount(&fb->base)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1973 | describe_obj(m, fb->obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1974 | seq_putc(m, '\n'); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1975 | } |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1976 | mutex_unlock(&dev->mode_config.fb_lock); |
Chris Wilson | 188c1ab | 2016-04-03 14:14:20 +0100 | [diff] [blame] | 1977 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1978 | |
| 1979 | return 0; |
| 1980 | } |
| 1981 | |
Oscar Mateo | c9fe99b | 2014-07-24 17:04:46 +0100 | [diff] [blame] | 1982 | static void describe_ctx_ringbuf(struct seq_file *m, |
| 1983 | struct intel_ringbuffer *ringbuf) |
| 1984 | { |
| 1985 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", |
| 1986 | ringbuf->space, ringbuf->head, ringbuf->tail, |
| 1987 | ringbuf->last_retired_head); |
| 1988 | } |
| 1989 | |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1990 | static int i915_context_status(struct seq_file *m, void *unused) |
| 1991 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1992 | struct drm_info_node *node = m->private; |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1993 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1994 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1995 | struct intel_engine_cs *engine; |
Chris Wilson | e2efd13 | 2016-05-24 14:53:34 +0100 | [diff] [blame] | 1996 | struct i915_gem_context *ctx; |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 1997 | int ret; |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1998 | |
Daniel Vetter | f3d2887 | 2014-05-29 23:23:08 +0200 | [diff] [blame] | 1999 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 2000 | if (ret) |
| 2001 | return ret; |
| 2002 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 2003 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
Chris Wilson | 5d1808e | 2016-04-28 09:56:51 +0100 | [diff] [blame] | 2004 | seq_printf(m, "HW context %u ", ctx->hw_id); |
Chris Wilson | d28b99a | 2016-05-24 14:53:39 +0100 | [diff] [blame] | 2005 | if (IS_ERR(ctx->file_priv)) { |
| 2006 | seq_puts(m, "(deleted) "); |
| 2007 | } else if (ctx->file_priv) { |
| 2008 | struct pid *pid = ctx->file_priv->file->pid; |
| 2009 | struct task_struct *task; |
| 2010 | |
| 2011 | task = get_pid_task(pid, PIDTYPE_PID); |
| 2012 | if (task) { |
| 2013 | seq_printf(m, "(%s [%d]) ", |
| 2014 | task->comm, task->pid); |
| 2015 | put_task_struct(task); |
| 2016 | } |
| 2017 | } else { |
| 2018 | seq_puts(m, "(kernel) "); |
| 2019 | } |
| 2020 | |
Chris Wilson | bca44d8 | 2016-05-24 14:53:41 +0100 | [diff] [blame^] | 2021 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
| 2022 | seq_putc(m, '\n'); |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 2023 | |
Chris Wilson | bca44d8 | 2016-05-24 14:53:41 +0100 | [diff] [blame^] | 2024 | for_each_engine(engine, dev_priv) { |
| 2025 | struct intel_context *ce = &ctx->engine[engine->id]; |
| 2026 | |
| 2027 | seq_printf(m, "%s: ", engine->name); |
| 2028 | seq_putc(m, ce->initialised ? 'I' : 'i'); |
| 2029 | if (ce->state) |
| 2030 | describe_obj(m, ce->state); |
| 2031 | if (ce->ringbuf) |
| 2032 | describe_ctx_ringbuf(m, ce->ringbuf); |
Oscar Mateo | c9fe99b | 2014-07-24 17:04:46 +0100 | [diff] [blame] | 2033 | seq_putc(m, '\n'); |
Oscar Mateo | c9fe99b | 2014-07-24 17:04:46 +0100 | [diff] [blame] | 2034 | } |
| 2035 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 2036 | seq_putc(m, '\n'); |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 2037 | } |
| 2038 | |
Daniel Vetter | f3d2887 | 2014-05-29 23:23:08 +0200 | [diff] [blame] | 2039 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 2040 | |
| 2041 | return 0; |
| 2042 | } |
| 2043 | |
Thomas Daniel | 064ca1d | 2014-12-02 13:21:18 +0000 | [diff] [blame] | 2044 | static void i915_dump_lrc_obj(struct seq_file *m, |
Chris Wilson | e2efd13 | 2016-05-24 14:53:34 +0100 | [diff] [blame] | 2045 | struct i915_gem_context *ctx, |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2046 | struct intel_engine_cs *engine) |
Thomas Daniel | 064ca1d | 2014-12-02 13:21:18 +0000 | [diff] [blame] | 2047 | { |
Chris Wilson | bca44d8 | 2016-05-24 14:53:41 +0100 | [diff] [blame^] | 2048 | struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state; |
Thomas Daniel | 064ca1d | 2014-12-02 13:21:18 +0000 | [diff] [blame] | 2049 | struct page *page; |
| 2050 | uint32_t *reg_state; |
| 2051 | int j; |
| 2052 | unsigned long ggtt_offset = 0; |
| 2053 | |
Chris Wilson | 7069b14 | 2016-04-28 09:56:52 +0100 | [diff] [blame] | 2054 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); |
| 2055 | |
Thomas Daniel | 064ca1d | 2014-12-02 13:21:18 +0000 | [diff] [blame] | 2056 | if (ctx_obj == NULL) { |
Chris Wilson | 7069b14 | 2016-04-28 09:56:52 +0100 | [diff] [blame] | 2057 | seq_puts(m, "\tNot allocated\n"); |
Thomas Daniel | 064ca1d | 2014-12-02 13:21:18 +0000 | [diff] [blame] | 2058 | return; |
| 2059 | } |
| 2060 | |
Thomas Daniel | 064ca1d | 2014-12-02 13:21:18 +0000 | [diff] [blame] | 2061 | if (!i915_gem_obj_ggtt_bound(ctx_obj)) |
| 2062 | seq_puts(m, "\tNot bound in GGTT\n"); |
| 2063 | else |
| 2064 | ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj); |
| 2065 | |
| 2066 | if (i915_gem_object_get_pages(ctx_obj)) { |
| 2067 | seq_puts(m, "\tFailed to get pages for context object\n"); |
| 2068 | return; |
| 2069 | } |
| 2070 | |
Alex Dai | d167519 | 2015-08-12 15:43:43 +0100 | [diff] [blame] | 2071 | page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); |
Thomas Daniel | 064ca1d | 2014-12-02 13:21:18 +0000 | [diff] [blame] | 2072 | if (!WARN_ON(page == NULL)) { |
| 2073 | reg_state = kmap_atomic(page); |
| 2074 | |
| 2075 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { |
| 2076 | seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 2077 | ggtt_offset + 4096 + (j * 4), |
| 2078 | reg_state[j], reg_state[j + 1], |
| 2079 | reg_state[j + 2], reg_state[j + 3]); |
| 2080 | } |
| 2081 | kunmap_atomic(reg_state); |
| 2082 | } |
| 2083 | |
| 2084 | seq_putc(m, '\n'); |
| 2085 | } |
| 2086 | |
Ben Widawsky | c0ab1ae | 2014-08-07 13:24:26 +0100 | [diff] [blame] | 2087 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
| 2088 | { |
| 2089 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2090 | struct drm_device *dev = node->minor->dev; |
| 2091 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2092 | struct intel_engine_cs *engine; |
Chris Wilson | e2efd13 | 2016-05-24 14:53:34 +0100 | [diff] [blame] | 2093 | struct i915_gem_context *ctx; |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 2094 | int ret; |
Ben Widawsky | c0ab1ae | 2014-08-07 13:24:26 +0100 | [diff] [blame] | 2095 | |
| 2096 | if (!i915.enable_execlists) { |
| 2097 | seq_printf(m, "Logical Ring Contexts are disabled\n"); |
| 2098 | return 0; |
| 2099 | } |
| 2100 | |
| 2101 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2102 | if (ret) |
| 2103 | return ret; |
| 2104 | |
Dave Gordon | e28e404 | 2016-01-19 19:02:55 +0000 | [diff] [blame] | 2105 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
Chris Wilson | 24f1d3cc | 2016-04-28 09:56:53 +0100 | [diff] [blame] | 2106 | for_each_engine(engine, dev_priv) |
| 2107 | i915_dump_lrc_obj(m, ctx, engine); |
Ben Widawsky | c0ab1ae | 2014-08-07 13:24:26 +0100 | [diff] [blame] | 2108 | |
| 2109 | mutex_unlock(&dev->struct_mutex); |
| 2110 | |
| 2111 | return 0; |
| 2112 | } |
| 2113 | |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 2114 | static int i915_execlists(struct seq_file *m, void *data) |
| 2115 | { |
| 2116 | struct drm_info_node *node = (struct drm_info_node *)m->private; |
| 2117 | struct drm_device *dev = node->minor->dev; |
| 2118 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2119 | struct intel_engine_cs *engine; |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 2120 | u32 status_pointer; |
| 2121 | u8 read_pointer; |
| 2122 | u8 write_pointer; |
| 2123 | u32 status; |
| 2124 | u32 ctx_id; |
| 2125 | struct list_head *cursor; |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 2126 | int i, ret; |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 2127 | |
| 2128 | if (!i915.enable_execlists) { |
| 2129 | seq_puts(m, "Logical Ring Contexts are disabled\n"); |
| 2130 | return 0; |
| 2131 | } |
| 2132 | |
| 2133 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2134 | if (ret) |
| 2135 | return ret; |
| 2136 | |
Michel Thierry | fc0412e | 2014-10-16 16:13:38 +0100 | [diff] [blame] | 2137 | intel_runtime_pm_get(dev_priv); |
| 2138 | |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 2139 | for_each_engine(engine, dev_priv) { |
Nick Hoath | 6d3d827 | 2015-01-15 13:10:39 +0000 | [diff] [blame] | 2140 | struct drm_i915_gem_request *head_req = NULL; |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 2141 | int count = 0; |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 2142 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2143 | seq_printf(m, "%s\n", engine->name); |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 2144 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2145 | status = I915_READ(RING_EXECLIST_STATUS_LO(engine)); |
| 2146 | ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine)); |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 2147 | seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n", |
| 2148 | status, ctx_id); |
| 2149 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2150 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 2151 | seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer); |
| 2152 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2153 | read_pointer = engine->next_context_status_buffer; |
Ben Widawsky | 5590a5f | 2016-01-05 10:30:05 -0800 | [diff] [blame] | 2154 | write_pointer = GEN8_CSB_WRITE_PTR(status_pointer); |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 2155 | if (read_pointer > write_pointer) |
Ben Widawsky | 5590a5f | 2016-01-05 10:30:05 -0800 | [diff] [blame] | 2156 | write_pointer += GEN8_CSB_ENTRIES; |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 2157 | seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n", |
| 2158 | read_pointer, write_pointer); |
| 2159 | |
Ben Widawsky | 5590a5f | 2016-01-05 10:30:05 -0800 | [diff] [blame] | 2160 | for (i = 0; i < GEN8_CSB_ENTRIES; i++) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2161 | status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i)); |
| 2162 | ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i)); |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 2163 | |
| 2164 | seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n", |
| 2165 | i, status, ctx_id); |
| 2166 | } |
| 2167 | |
Tvrtko Ursulin | 27af5ee | 2016-04-04 12:11:56 +0100 | [diff] [blame] | 2168 | spin_lock_bh(&engine->execlist_lock); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2169 | list_for_each(cursor, &engine->execlist_queue) |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 2170 | count++; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2171 | head_req = list_first_entry_or_null(&engine->execlist_queue, |
| 2172 | struct drm_i915_gem_request, |
| 2173 | execlist_link); |
Tvrtko Ursulin | 27af5ee | 2016-04-04 12:11:56 +0100 | [diff] [blame] | 2174 | spin_unlock_bh(&engine->execlist_lock); |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 2175 | |
| 2176 | seq_printf(m, "\t%d requests in queue\n", count); |
| 2177 | if (head_req) { |
Chris Wilson | 7069b14 | 2016-04-28 09:56:52 +0100 | [diff] [blame] | 2178 | seq_printf(m, "\tHead request context: %u\n", |
| 2179 | head_req->ctx->hw_id); |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 2180 | seq_printf(m, "\tHead request tail: %u\n", |
Nick Hoath | 6d3d827 | 2015-01-15 13:10:39 +0000 | [diff] [blame] | 2181 | head_req->tail); |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 2182 | } |
| 2183 | |
| 2184 | seq_putc(m, '\n'); |
| 2185 | } |
| 2186 | |
Michel Thierry | fc0412e | 2014-10-16 16:13:38 +0100 | [diff] [blame] | 2187 | intel_runtime_pm_put(dev_priv); |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 2188 | mutex_unlock(&dev->struct_mutex); |
| 2189 | |
| 2190 | return 0; |
| 2191 | } |
| 2192 | |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2193 | static const char *swizzle_string(unsigned swizzle) |
| 2194 | { |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 2195 | switch (swizzle) { |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2196 | case I915_BIT_6_SWIZZLE_NONE: |
| 2197 | return "none"; |
| 2198 | case I915_BIT_6_SWIZZLE_9: |
| 2199 | return "bit9"; |
| 2200 | case I915_BIT_6_SWIZZLE_9_10: |
| 2201 | return "bit9/bit10"; |
| 2202 | case I915_BIT_6_SWIZZLE_9_11: |
| 2203 | return "bit9/bit11"; |
| 2204 | case I915_BIT_6_SWIZZLE_9_10_11: |
| 2205 | return "bit9/bit10/bit11"; |
| 2206 | case I915_BIT_6_SWIZZLE_9_17: |
| 2207 | return "bit9/bit17"; |
| 2208 | case I915_BIT_6_SWIZZLE_9_10_17: |
| 2209 | return "bit9/bit10/bit17"; |
| 2210 | case I915_BIT_6_SWIZZLE_UNKNOWN: |
Masanari Iida | 8a168ca | 2012-12-29 02:00:09 +0900 | [diff] [blame] | 2211 | return "unknown"; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2212 | } |
| 2213 | |
| 2214 | return "bug"; |
| 2215 | } |
| 2216 | |
| 2217 | static int i915_swizzle_info(struct seq_file *m, void *data) |
| 2218 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2219 | struct drm_info_node *node = m->private; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2220 | struct drm_device *dev = node->minor->dev; |
| 2221 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 2222 | int ret; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2223 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 2224 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2225 | if (ret) |
| 2226 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2227 | intel_runtime_pm_get(dev_priv); |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 2228 | |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2229 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
| 2230 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); |
| 2231 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", |
| 2232 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); |
| 2233 | |
| 2234 | if (IS_GEN3(dev) || IS_GEN4(dev)) { |
| 2235 | seq_printf(m, "DDC = 0x%08x\n", |
| 2236 | I915_READ(DCC)); |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 2237 | seq_printf(m, "DDC2 = 0x%08x\n", |
| 2238 | I915_READ(DCC2)); |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2239 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
| 2240 | I915_READ16(C0DRB3)); |
| 2241 | seq_printf(m, "C1DRB3 = 0x%04x\n", |
| 2242 | I915_READ16(C1DRB3)); |
Ben Widawsky | 9d3203e | 2013-11-02 21:07:14 -0700 | [diff] [blame] | 2243 | } else if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | 3fa7d23 | 2012-01-31 16:47:56 +0100 | [diff] [blame] | 2244 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
| 2245 | I915_READ(MAD_DIMM_C0)); |
| 2246 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", |
| 2247 | I915_READ(MAD_DIMM_C1)); |
| 2248 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", |
| 2249 | I915_READ(MAD_DIMM_C2)); |
| 2250 | seq_printf(m, "TILECTL = 0x%08x\n", |
| 2251 | I915_READ(TILECTL)); |
Robert Beckett | 5907f5f | 2014-01-23 14:23:14 +0000 | [diff] [blame] | 2252 | if (INTEL_INFO(dev)->gen >= 8) |
Ben Widawsky | 9d3203e | 2013-11-02 21:07:14 -0700 | [diff] [blame] | 2253 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
| 2254 | I915_READ(GAMTARBMODE)); |
| 2255 | else |
| 2256 | seq_printf(m, "ARB_MODE = 0x%08x\n", |
| 2257 | I915_READ(ARB_MODE)); |
Daniel Vetter | 3fa7d23 | 2012-01-31 16:47:56 +0100 | [diff] [blame] | 2258 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
| 2259 | I915_READ(DISP_ARB_CTL)); |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2260 | } |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 2261 | |
| 2262 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) |
| 2263 | seq_puts(m, "L-shaped memory detected\n"); |
| 2264 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2265 | intel_runtime_pm_put(dev_priv); |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2266 | mutex_unlock(&dev->struct_mutex); |
| 2267 | |
| 2268 | return 0; |
| 2269 | } |
| 2270 | |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2271 | static int per_file_ctx(int id, void *ptr, void *data) |
| 2272 | { |
Chris Wilson | e2efd13 | 2016-05-24 14:53:34 +0100 | [diff] [blame] | 2273 | struct i915_gem_context *ctx = ptr; |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2274 | struct seq_file *m = data; |
Daniel Vetter | ae6c480 | 2014-08-06 15:04:53 +0200 | [diff] [blame] | 2275 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
| 2276 | |
| 2277 | if (!ppgtt) { |
| 2278 | seq_printf(m, " no ppgtt for context %d\n", |
| 2279 | ctx->user_handle); |
| 2280 | return 0; |
| 2281 | } |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2282 | |
Oscar Mateo | f83d651 | 2014-05-22 14:13:38 +0100 | [diff] [blame] | 2283 | if (i915_gem_context_is_default(ctx)) |
| 2284 | seq_puts(m, " default context:\n"); |
| 2285 | else |
Oscar Mateo | 821d66d | 2014-07-03 16:28:00 +0100 | [diff] [blame] | 2286 | seq_printf(m, " context %d:\n", ctx->user_handle); |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2287 | ppgtt->debug_dump(ppgtt, m); |
| 2288 | |
| 2289 | return 0; |
| 2290 | } |
| 2291 | |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2292 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2293 | { |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2294 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2295 | struct intel_engine_cs *engine; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2296 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 2297 | int i; |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2298 | |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2299 | if (!ppgtt) |
| 2300 | return; |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2301 | |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 2302 | for_each_engine(engine, dev_priv) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2303 | seq_printf(m, "%s\n", engine->name); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2304 | for (i = 0; i < 4; i++) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2305 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2306 | pdp <<= 32; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2307 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
Ville Syrjälä | a2a5b15 | 2014-03-31 18:17:16 +0300 | [diff] [blame] | 2308 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2309 | } |
| 2310 | } |
| 2311 | } |
| 2312 | |
| 2313 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
| 2314 | { |
| 2315 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2316 | struct intel_engine_cs *engine; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2317 | |
Tvrtko Ursulin | 7e22dbb | 2016-05-10 10:57:06 +0100 | [diff] [blame] | 2318 | if (IS_GEN6(dev_priv)) |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2319 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
| 2320 | |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 2321 | for_each_engine(engine, dev_priv) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2322 | seq_printf(m, "%s\n", engine->name); |
Tvrtko Ursulin | 7e22dbb | 2016-05-10 10:57:06 +0100 | [diff] [blame] | 2323 | if (IS_GEN7(dev_priv)) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2324 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
| 2325 | I915_READ(RING_MODE_GEN7(engine))); |
| 2326 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", |
| 2327 | I915_READ(RING_PP_DIR_BASE(engine))); |
| 2328 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", |
| 2329 | I915_READ(RING_PP_DIR_BASE_READ(engine))); |
| 2330 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", |
| 2331 | I915_READ(RING_PP_DIR_DCLV(engine))); |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2332 | } |
| 2333 | if (dev_priv->mm.aliasing_ppgtt) { |
| 2334 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 2335 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 2336 | seq_puts(m, "aliasing PPGTT:\n"); |
Mika Kuoppala | 44159dd | 2015-06-25 18:35:07 +0300 | [diff] [blame] | 2337 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2338 | |
Ben Widawsky | 87d60b6 | 2013-12-06 14:11:29 -0800 | [diff] [blame] | 2339 | ppgtt->debug_dump(ppgtt, m); |
Daniel Vetter | ae6c480 | 2014-08-06 15:04:53 +0200 | [diff] [blame] | 2340 | } |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2341 | |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2342 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2343 | } |
| 2344 | |
| 2345 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
| 2346 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2347 | struct drm_info_node *node = m->private; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2348 | struct drm_device *dev = node->minor->dev; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2349 | struct drm_i915_private *dev_priv = dev->dev_private; |
Michel Thierry | ea91e40 | 2015-07-29 17:23:57 +0100 | [diff] [blame] | 2350 | struct drm_file *file; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2351 | |
| 2352 | int ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2353 | if (ret) |
| 2354 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2355 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2356 | |
| 2357 | if (INTEL_INFO(dev)->gen >= 8) |
| 2358 | gen8_ppgtt_info(m, dev); |
| 2359 | else if (INTEL_INFO(dev)->gen >= 6) |
| 2360 | gen6_ppgtt_info(m, dev); |
| 2361 | |
Daniel Vetter | 1d2ac40 | 2016-04-26 19:29:41 +0200 | [diff] [blame] | 2362 | mutex_lock(&dev->filelist_mutex); |
Michel Thierry | ea91e40 | 2015-07-29 17:23:57 +0100 | [diff] [blame] | 2363 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
| 2364 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Geliang Tang | 7cb5dff | 2015-09-25 03:58:11 -0700 | [diff] [blame] | 2365 | struct task_struct *task; |
Michel Thierry | ea91e40 | 2015-07-29 17:23:57 +0100 | [diff] [blame] | 2366 | |
Geliang Tang | 7cb5dff | 2015-09-25 03:58:11 -0700 | [diff] [blame] | 2367 | task = get_pid_task(file->pid, PIDTYPE_PID); |
Dan Carpenter | 0681276 | 2015-10-02 18:14:22 +0300 | [diff] [blame] | 2368 | if (!task) { |
| 2369 | ret = -ESRCH; |
| 2370 | goto out_put; |
| 2371 | } |
Geliang Tang | 7cb5dff | 2015-09-25 03:58:11 -0700 | [diff] [blame] | 2372 | seq_printf(m, "\nproc: %s\n", task->comm); |
| 2373 | put_task_struct(task); |
Michel Thierry | ea91e40 | 2015-07-29 17:23:57 +0100 | [diff] [blame] | 2374 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
| 2375 | (void *)(unsigned long)m); |
| 2376 | } |
Daniel Vetter | 1d2ac40 | 2016-04-26 19:29:41 +0200 | [diff] [blame] | 2377 | mutex_unlock(&dev->filelist_mutex); |
Michel Thierry | ea91e40 | 2015-07-29 17:23:57 +0100 | [diff] [blame] | 2378 | |
Dan Carpenter | 0681276 | 2015-10-02 18:14:22 +0300 | [diff] [blame] | 2379 | out_put: |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2380 | intel_runtime_pm_put(dev_priv); |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2381 | mutex_unlock(&dev->struct_mutex); |
| 2382 | |
Dan Carpenter | 0681276 | 2015-10-02 18:14:22 +0300 | [diff] [blame] | 2383 | return ret; |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2384 | } |
| 2385 | |
Chris Wilson | f5a4c67 | 2015-04-27 13:41:23 +0100 | [diff] [blame] | 2386 | static int count_irq_waiters(struct drm_i915_private *i915) |
| 2387 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2388 | struct intel_engine_cs *engine; |
Chris Wilson | f5a4c67 | 2015-04-27 13:41:23 +0100 | [diff] [blame] | 2389 | int count = 0; |
Chris Wilson | f5a4c67 | 2015-04-27 13:41:23 +0100 | [diff] [blame] | 2390 | |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 2391 | for_each_engine(engine, i915) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2392 | count += engine->irq_refcount; |
Chris Wilson | f5a4c67 | 2015-04-27 13:41:23 +0100 | [diff] [blame] | 2393 | |
| 2394 | return count; |
| 2395 | } |
| 2396 | |
Chris Wilson | 1854d5c | 2015-04-07 16:20:32 +0100 | [diff] [blame] | 2397 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
| 2398 | { |
| 2399 | struct drm_info_node *node = m->private; |
| 2400 | struct drm_device *dev = node->minor->dev; |
| 2401 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2402 | struct drm_file *file; |
Chris Wilson | 1854d5c | 2015-04-07 16:20:32 +0100 | [diff] [blame] | 2403 | |
Chris Wilson | f5a4c67 | 2015-04-27 13:41:23 +0100 | [diff] [blame] | 2404 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
| 2405 | seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy); |
| 2406 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); |
| 2407 | seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n", |
| 2408 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
| 2409 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
| 2410 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), |
| 2411 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), |
| 2412 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
Daniel Vetter | 1d2ac40 | 2016-04-26 19:29:41 +0200 | [diff] [blame] | 2413 | |
| 2414 | mutex_lock(&dev->filelist_mutex); |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 2415 | spin_lock(&dev_priv->rps.client_lock); |
Chris Wilson | 1854d5c | 2015-04-07 16:20:32 +0100 | [diff] [blame] | 2416 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
| 2417 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 2418 | struct task_struct *task; |
| 2419 | |
| 2420 | rcu_read_lock(); |
| 2421 | task = pid_task(file->pid, PIDTYPE_PID); |
| 2422 | seq_printf(m, "%s [%d]: %d boosts%s\n", |
| 2423 | task ? task->comm : "<unknown>", |
| 2424 | task ? task->pid : -1, |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 2425 | file_priv->rps.boosts, |
| 2426 | list_empty(&file_priv->rps.link) ? "" : ", active"); |
Chris Wilson | 1854d5c | 2015-04-07 16:20:32 +0100 | [diff] [blame] | 2427 | rcu_read_unlock(); |
| 2428 | } |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 2429 | seq_printf(m, "Semaphore boosts: %d%s\n", |
| 2430 | dev_priv->rps.semaphores.boosts, |
| 2431 | list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active"); |
| 2432 | seq_printf(m, "MMIO flip boosts: %d%s\n", |
| 2433 | dev_priv->rps.mmioflips.boosts, |
| 2434 | list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active"); |
Chris Wilson | 1854d5c | 2015-04-07 16:20:32 +0100 | [diff] [blame] | 2435 | seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts); |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 2436 | spin_unlock(&dev_priv->rps.client_lock); |
Daniel Vetter | 1d2ac40 | 2016-04-26 19:29:41 +0200 | [diff] [blame] | 2437 | mutex_unlock(&dev->filelist_mutex); |
Chris Wilson | 1854d5c | 2015-04-07 16:20:32 +0100 | [diff] [blame] | 2438 | |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 2439 | return 0; |
Chris Wilson | 1854d5c | 2015-04-07 16:20:32 +0100 | [diff] [blame] | 2440 | } |
| 2441 | |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 2442 | static int i915_llc(struct seq_file *m, void *data) |
| 2443 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2444 | struct drm_info_node *node = m->private; |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 2445 | struct drm_device *dev = node->minor->dev; |
| 2446 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | 3accaf7 | 2016-04-13 17:26:43 +0300 | [diff] [blame] | 2447 | const bool edram = INTEL_GEN(dev_priv) > 8; |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 2448 | |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 2449 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); |
Mika Kuoppala | 3accaf7 | 2016-04-13 17:26:43 +0300 | [diff] [blame] | 2450 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
| 2451 | intel_uncore_edram_size(dev_priv)/1024/1024); |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 2452 | |
| 2453 | return 0; |
| 2454 | } |
| 2455 | |
Alex Dai | fdf5d35 | 2015-08-12 15:43:37 +0100 | [diff] [blame] | 2456 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
| 2457 | { |
| 2458 | struct drm_info_node *node = m->private; |
| 2459 | struct drm_i915_private *dev_priv = node->minor->dev->dev_private; |
| 2460 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
| 2461 | u32 tmp, i; |
| 2462 | |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 2463 | if (!HAS_GUC_UCODE(dev_priv)) |
Alex Dai | fdf5d35 | 2015-08-12 15:43:37 +0100 | [diff] [blame] | 2464 | return 0; |
| 2465 | |
| 2466 | seq_printf(m, "GuC firmware status:\n"); |
| 2467 | seq_printf(m, "\tpath: %s\n", |
| 2468 | guc_fw->guc_fw_path); |
| 2469 | seq_printf(m, "\tfetch: %s\n", |
| 2470 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); |
| 2471 | seq_printf(m, "\tload: %s\n", |
| 2472 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); |
| 2473 | seq_printf(m, "\tversion wanted: %d.%d\n", |
| 2474 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); |
| 2475 | seq_printf(m, "\tversion found: %d.%d\n", |
| 2476 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found); |
Alex Dai | feda33e | 2015-10-19 16:10:54 -0700 | [diff] [blame] | 2477 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
| 2478 | guc_fw->header_offset, guc_fw->header_size); |
| 2479 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", |
| 2480 | guc_fw->ucode_offset, guc_fw->ucode_size); |
| 2481 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", |
| 2482 | guc_fw->rsa_offset, guc_fw->rsa_size); |
Alex Dai | fdf5d35 | 2015-08-12 15:43:37 +0100 | [diff] [blame] | 2483 | |
| 2484 | tmp = I915_READ(GUC_STATUS); |
| 2485 | |
| 2486 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); |
| 2487 | seq_printf(m, "\tBootrom status = 0x%x\n", |
| 2488 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); |
| 2489 | seq_printf(m, "\tuKernel status = 0x%x\n", |
| 2490 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); |
| 2491 | seq_printf(m, "\tMIA Core status = 0x%x\n", |
| 2492 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); |
| 2493 | seq_puts(m, "\nScratch registers:\n"); |
| 2494 | for (i = 0; i < 16; i++) |
| 2495 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); |
| 2496 | |
| 2497 | return 0; |
| 2498 | } |
| 2499 | |
Dave Gordon | 8b417c2 | 2015-08-12 15:43:44 +0100 | [diff] [blame] | 2500 | static void i915_guc_client_info(struct seq_file *m, |
| 2501 | struct drm_i915_private *dev_priv, |
| 2502 | struct i915_guc_client *client) |
| 2503 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2504 | struct intel_engine_cs *engine; |
Dave Gordon | 8b417c2 | 2015-08-12 15:43:44 +0100 | [diff] [blame] | 2505 | uint64_t tot = 0; |
Dave Gordon | 8b417c2 | 2015-08-12 15:43:44 +0100 | [diff] [blame] | 2506 | |
| 2507 | seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", |
| 2508 | client->priority, client->ctx_index, client->proc_desc_offset); |
| 2509 | seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", |
| 2510 | client->doorbell_id, client->doorbell_offset, client->cookie); |
| 2511 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", |
| 2512 | client->wq_size, client->wq_offset, client->wq_tail); |
| 2513 | |
Dave Gordon | 551aaec | 2016-05-13 15:36:33 +0100 | [diff] [blame] | 2514 | seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space); |
Dave Gordon | 8b417c2 | 2015-08-12 15:43:44 +0100 | [diff] [blame] | 2515 | seq_printf(m, "\tFailed to queue: %u\n", client->q_fail); |
| 2516 | seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); |
| 2517 | seq_printf(m, "\tLast submission result: %d\n", client->retcode); |
| 2518 | |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 2519 | for_each_engine(engine, dev_priv) { |
Dave Gordon | 8b417c2 | 2015-08-12 15:43:44 +0100 | [diff] [blame] | 2520 | seq_printf(m, "\tSubmissions: %llu %s\n", |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2521 | client->submissions[engine->guc_id], |
| 2522 | engine->name); |
| 2523 | tot += client->submissions[engine->guc_id]; |
Dave Gordon | 8b417c2 | 2015-08-12 15:43:44 +0100 | [diff] [blame] | 2524 | } |
| 2525 | seq_printf(m, "\tTotal: %llu\n", tot); |
| 2526 | } |
| 2527 | |
| 2528 | static int i915_guc_info(struct seq_file *m, void *data) |
| 2529 | { |
| 2530 | struct drm_info_node *node = m->private; |
| 2531 | struct drm_device *dev = node->minor->dev; |
| 2532 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2533 | struct intel_guc guc; |
Ville Syrjälä | 0a0b457 | 2015-08-21 20:45:27 +0300 | [diff] [blame] | 2534 | struct i915_guc_client client = {}; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2535 | struct intel_engine_cs *engine; |
Dave Gordon | 8b417c2 | 2015-08-12 15:43:44 +0100 | [diff] [blame] | 2536 | u64 total = 0; |
| 2537 | |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 2538 | if (!HAS_GUC_SCHED(dev_priv)) |
Dave Gordon | 8b417c2 | 2015-08-12 15:43:44 +0100 | [diff] [blame] | 2539 | return 0; |
| 2540 | |
Alex Dai | 5a84330 | 2015-12-02 16:56:29 -0800 | [diff] [blame] | 2541 | if (mutex_lock_interruptible(&dev->struct_mutex)) |
| 2542 | return 0; |
| 2543 | |
Dave Gordon | 8b417c2 | 2015-08-12 15:43:44 +0100 | [diff] [blame] | 2544 | /* Take a local copy of the GuC data, so we can dump it at leisure */ |
Dave Gordon | 8b417c2 | 2015-08-12 15:43:44 +0100 | [diff] [blame] | 2545 | guc = dev_priv->guc; |
Alex Dai | 5a84330 | 2015-12-02 16:56:29 -0800 | [diff] [blame] | 2546 | if (guc.execbuf_client) |
Dave Gordon | 8b417c2 | 2015-08-12 15:43:44 +0100 | [diff] [blame] | 2547 | client = *guc.execbuf_client; |
Alex Dai | 5a84330 | 2015-12-02 16:56:29 -0800 | [diff] [blame] | 2548 | |
| 2549 | mutex_unlock(&dev->struct_mutex); |
Dave Gordon | 8b417c2 | 2015-08-12 15:43:44 +0100 | [diff] [blame] | 2550 | |
| 2551 | seq_printf(m, "GuC total action count: %llu\n", guc.action_count); |
| 2552 | seq_printf(m, "GuC action failure count: %u\n", guc.action_fail); |
| 2553 | seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd); |
| 2554 | seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status); |
| 2555 | seq_printf(m, "GuC last action error code: %d\n", guc.action_err); |
| 2556 | |
| 2557 | seq_printf(m, "\nGuC submissions:\n"); |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 2558 | for_each_engine(engine, dev_priv) { |
Alex Dai | 397097b | 2016-01-23 11:58:14 -0800 | [diff] [blame] | 2559 | seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2560 | engine->name, guc.submissions[engine->guc_id], |
| 2561 | guc.last_seqno[engine->guc_id]); |
| 2562 | total += guc.submissions[engine->guc_id]; |
Dave Gordon | 8b417c2 | 2015-08-12 15:43:44 +0100 | [diff] [blame] | 2563 | } |
| 2564 | seq_printf(m, "\t%s: %llu\n", "Total", total); |
| 2565 | |
| 2566 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client); |
| 2567 | i915_guc_client_info(m, dev_priv, &client); |
| 2568 | |
| 2569 | /* Add more as required ... */ |
| 2570 | |
| 2571 | return 0; |
| 2572 | } |
| 2573 | |
Alex Dai | 4c7e77f | 2015-08-12 15:43:40 +0100 | [diff] [blame] | 2574 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
| 2575 | { |
| 2576 | struct drm_info_node *node = m->private; |
| 2577 | struct drm_device *dev = node->minor->dev; |
| 2578 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2579 | struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj; |
| 2580 | u32 *log; |
| 2581 | int i = 0, pg; |
| 2582 | |
| 2583 | if (!log_obj) |
| 2584 | return 0; |
| 2585 | |
| 2586 | for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) { |
| 2587 | log = kmap_atomic(i915_gem_object_get_page(log_obj, pg)); |
| 2588 | |
| 2589 | for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) |
| 2590 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 2591 | *(log + i), *(log + i + 1), |
| 2592 | *(log + i + 2), *(log + i + 3)); |
| 2593 | |
| 2594 | kunmap_atomic(log); |
| 2595 | } |
| 2596 | |
| 2597 | seq_putc(m, '\n'); |
| 2598 | |
| 2599 | return 0; |
| 2600 | } |
| 2601 | |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2602 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
| 2603 | { |
| 2604 | struct drm_info_node *node = m->private; |
| 2605 | struct drm_device *dev = node->minor->dev; |
| 2606 | struct drm_i915_private *dev_priv = dev->dev_private; |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 2607 | u32 psrperf = 0; |
Rodrigo Vivi | a6cbdb8 | 2014-11-14 08:52:40 -0800 | [diff] [blame] | 2608 | u32 stat[3]; |
| 2609 | enum pipe pipe; |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 2610 | bool enabled = false; |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2611 | |
Damien Lespiau | 3553a8e | 2015-03-09 14:17:58 +0000 | [diff] [blame] | 2612 | if (!HAS_PSR(dev)) { |
| 2613 | seq_puts(m, "PSR not supported\n"); |
| 2614 | return 0; |
| 2615 | } |
| 2616 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2617 | intel_runtime_pm_get(dev_priv); |
| 2618 | |
Daniel Vetter | fa128fa | 2014-07-11 10:30:17 -0700 | [diff] [blame] | 2619 | mutex_lock(&dev_priv->psr.lock); |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 2620 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
| 2621 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); |
Daniel Vetter | 2807cf6 | 2014-07-11 10:30:11 -0700 | [diff] [blame] | 2622 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
Rodrigo Vivi | 5755c78 | 2014-06-12 10:16:45 -0700 | [diff] [blame] | 2623 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
Daniel Vetter | fa128fa | 2014-07-11 10:30:17 -0700 | [diff] [blame] | 2624 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
| 2625 | dev_priv->psr.busy_frontbuffer_bits); |
| 2626 | seq_printf(m, "Re-enable work scheduled: %s\n", |
| 2627 | yesno(work_busy(&dev_priv->psr.work.work))); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2628 | |
Damien Lespiau | 3553a8e | 2015-03-09 14:17:58 +0000 | [diff] [blame] | 2629 | if (HAS_DDI(dev)) |
Ville Syrjälä | 443a389 | 2015-11-11 20:34:15 +0200 | [diff] [blame] | 2630 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; |
Damien Lespiau | 3553a8e | 2015-03-09 14:17:58 +0000 | [diff] [blame] | 2631 | else { |
| 2632 | for_each_pipe(dev_priv, pipe) { |
| 2633 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & |
| 2634 | VLV_EDP_PSR_CURR_STATE_MASK; |
| 2635 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || |
| 2636 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) |
| 2637 | enabled = true; |
Rodrigo Vivi | a6cbdb8 | 2014-11-14 08:52:40 -0800 | [diff] [blame] | 2638 | } |
| 2639 | } |
Rodrigo Vivi | 60e5ffe | 2016-02-01 12:02:07 -0800 | [diff] [blame] | 2640 | |
| 2641 | seq_printf(m, "Main link in standby mode: %s\n", |
| 2642 | yesno(dev_priv->psr.link_standby)); |
| 2643 | |
Rodrigo Vivi | a6cbdb8 | 2014-11-14 08:52:40 -0800 | [diff] [blame] | 2644 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2645 | |
Rodrigo Vivi | a6cbdb8 | 2014-11-14 08:52:40 -0800 | [diff] [blame] | 2646 | if (!HAS_DDI(dev)) |
| 2647 | for_each_pipe(dev_priv, pipe) { |
| 2648 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || |
| 2649 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) |
| 2650 | seq_printf(m, " pipe %c", pipe_name(pipe)); |
| 2651 | } |
| 2652 | seq_puts(m, "\n"); |
| 2653 | |
Rodrigo Vivi | 05eec3c | 2015-11-23 14:16:40 -0800 | [diff] [blame] | 2654 | /* |
| 2655 | * VLV/CHV PSR has no kind of performance counter |
| 2656 | * SKL+ Perf counter is reset to 0 everytime DC state is entered |
| 2657 | */ |
| 2658 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Ville Syrjälä | 443a389 | 2015-11-11 20:34:15 +0200 | [diff] [blame] | 2659 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 2660 | EDP_PSR_PERF_CNT_MASK; |
Rodrigo Vivi | a6cbdb8 | 2014-11-14 08:52:40 -0800 | [diff] [blame] | 2661 | |
| 2662 | seq_printf(m, "Performance_Counter: %u\n", psrperf); |
| 2663 | } |
Daniel Vetter | fa128fa | 2014-07-11 10:30:17 -0700 | [diff] [blame] | 2664 | mutex_unlock(&dev_priv->psr.lock); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2665 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2666 | intel_runtime_pm_put(dev_priv); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2667 | return 0; |
| 2668 | } |
| 2669 | |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 2670 | static int i915_sink_crc(struct seq_file *m, void *data) |
| 2671 | { |
| 2672 | struct drm_info_node *node = m->private; |
| 2673 | struct drm_device *dev = node->minor->dev; |
| 2674 | struct intel_encoder *encoder; |
| 2675 | struct intel_connector *connector; |
| 2676 | struct intel_dp *intel_dp = NULL; |
| 2677 | int ret; |
| 2678 | u8 crc[6]; |
| 2679 | |
| 2680 | drm_modeset_lock_all(dev); |
Rodrigo Vivi | aca5e36 | 2015-03-13 16:13:59 -0700 | [diff] [blame] | 2681 | for_each_intel_connector(dev, connector) { |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 2682 | |
| 2683 | if (connector->base.dpms != DRM_MODE_DPMS_ON) |
| 2684 | continue; |
| 2685 | |
Paulo Zanoni | b6ae3c7 | 2014-02-13 17:51:33 -0200 | [diff] [blame] | 2686 | if (!connector->base.encoder) |
| 2687 | continue; |
| 2688 | |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 2689 | encoder = to_intel_encoder(connector->base.encoder); |
| 2690 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 2691 | continue; |
| 2692 | |
| 2693 | intel_dp = enc_to_intel_dp(&encoder->base); |
| 2694 | |
| 2695 | ret = intel_dp_sink_crc(intel_dp, crc); |
| 2696 | if (ret) |
| 2697 | goto out; |
| 2698 | |
| 2699 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", |
| 2700 | crc[0], crc[1], crc[2], |
| 2701 | crc[3], crc[4], crc[5]); |
| 2702 | goto out; |
| 2703 | } |
| 2704 | ret = -ENODEV; |
| 2705 | out: |
| 2706 | drm_modeset_unlock_all(dev); |
| 2707 | return ret; |
| 2708 | } |
| 2709 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 2710 | static int i915_energy_uJ(struct seq_file *m, void *data) |
| 2711 | { |
| 2712 | struct drm_info_node *node = m->private; |
| 2713 | struct drm_device *dev = node->minor->dev; |
| 2714 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2715 | u64 power; |
| 2716 | u32 units; |
| 2717 | |
| 2718 | if (INTEL_INFO(dev)->gen < 6) |
| 2719 | return -ENODEV; |
| 2720 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 2721 | intel_runtime_pm_get(dev_priv); |
| 2722 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 2723 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
| 2724 | power = (power & 0x1f00) >> 8; |
| 2725 | units = 1000000 / (1 << power); /* convert to uJ */ |
| 2726 | power = I915_READ(MCH_SECP_NRG_STTS); |
| 2727 | power *= units; |
| 2728 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 2729 | intel_runtime_pm_put(dev_priv); |
| 2730 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 2731 | seq_printf(m, "%llu", (long long unsigned)power); |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2732 | |
| 2733 | return 0; |
| 2734 | } |
| 2735 | |
Damien Lespiau | 6455c87 | 2015-06-04 18:23:57 +0100 | [diff] [blame] | 2736 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2737 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2738 | struct drm_info_node *node = m->private; |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2739 | struct drm_device *dev = node->minor->dev; |
| 2740 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2741 | |
Chris Wilson | a156e64 | 2016-04-03 14:14:21 +0100 | [diff] [blame] | 2742 | if (!HAS_RUNTIME_PM(dev_priv)) |
| 2743 | seq_puts(m, "Runtime power management not supported\n"); |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2744 | |
Paulo Zanoni | 86c4ec0 | 2014-02-21 13:52:24 -0300 | [diff] [blame] | 2745 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2746 | seq_printf(m, "IRQs disabled: %s\n", |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 2747 | yesno(!intel_irqs_enabled(dev_priv))); |
Chris Wilson | 0d80418 | 2015-06-15 12:52:28 +0100 | [diff] [blame] | 2748 | #ifdef CONFIG_PM |
Damien Lespiau | a6aaec8 | 2015-06-04 18:23:58 +0100 | [diff] [blame] | 2749 | seq_printf(m, "Usage count: %d\n", |
| 2750 | atomic_read(&dev->dev->power.usage_count)); |
Chris Wilson | 0d80418 | 2015-06-15 12:52:28 +0100 | [diff] [blame] | 2751 | #else |
| 2752 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); |
| 2753 | #endif |
Chris Wilson | a156e64 | 2016-04-03 14:14:21 +0100 | [diff] [blame] | 2754 | seq_printf(m, "PCI device power state: %s [%d]\n", |
| 2755 | pci_power_name(dev_priv->dev->pdev->current_state), |
| 2756 | dev_priv->dev->pdev->current_state); |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2757 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 2758 | return 0; |
| 2759 | } |
| 2760 | |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 2761 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
| 2762 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2763 | struct drm_info_node *node = m->private; |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 2764 | struct drm_device *dev = node->minor->dev; |
| 2765 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2766 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 2767 | int i; |
| 2768 | |
| 2769 | mutex_lock(&power_domains->lock); |
| 2770 | |
| 2771 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); |
| 2772 | for (i = 0; i < power_domains->power_well_count; i++) { |
| 2773 | struct i915_power_well *power_well; |
| 2774 | enum intel_display_power_domain power_domain; |
| 2775 | |
| 2776 | power_well = &power_domains->power_wells[i]; |
| 2777 | seq_printf(m, "%-25s %d\n", power_well->name, |
| 2778 | power_well->count); |
| 2779 | |
| 2780 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; |
| 2781 | power_domain++) { |
| 2782 | if (!(BIT(power_domain) & power_well->domains)) |
| 2783 | continue; |
| 2784 | |
| 2785 | seq_printf(m, " %-23s %d\n", |
Daniel Stone | 9895ad0 | 2015-11-20 15:55:33 +0000 | [diff] [blame] | 2786 | intel_display_power_domain_str(power_domain), |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 2787 | power_domains->domain_use_count[power_domain]); |
| 2788 | } |
| 2789 | } |
| 2790 | |
| 2791 | mutex_unlock(&power_domains->lock); |
| 2792 | |
| 2793 | return 0; |
| 2794 | } |
| 2795 | |
Damien Lespiau | b7cec66 | 2015-10-27 14:47:01 +0200 | [diff] [blame] | 2796 | static int i915_dmc_info(struct seq_file *m, void *unused) |
| 2797 | { |
| 2798 | struct drm_info_node *node = m->private; |
| 2799 | struct drm_device *dev = node->minor->dev; |
| 2800 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2801 | struct intel_csr *csr; |
| 2802 | |
| 2803 | if (!HAS_CSR(dev)) { |
| 2804 | seq_puts(m, "not supported\n"); |
| 2805 | return 0; |
| 2806 | } |
| 2807 | |
| 2808 | csr = &dev_priv->csr; |
| 2809 | |
Mika Kuoppala | 6fb403d | 2015-10-30 17:54:47 +0200 | [diff] [blame] | 2810 | intel_runtime_pm_get(dev_priv); |
| 2811 | |
Damien Lespiau | b7cec66 | 2015-10-27 14:47:01 +0200 | [diff] [blame] | 2812 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
| 2813 | seq_printf(m, "path: %s\n", csr->fw_path); |
| 2814 | |
| 2815 | if (!csr->dmc_payload) |
Mika Kuoppala | 6fb403d | 2015-10-30 17:54:47 +0200 | [diff] [blame] | 2816 | goto out; |
Damien Lespiau | b7cec66 | 2015-10-27 14:47:01 +0200 | [diff] [blame] | 2817 | |
| 2818 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), |
| 2819 | CSR_VERSION_MINOR(csr->version)); |
| 2820 | |
Damien Lespiau | 8337206 | 2015-10-30 17:53:32 +0200 | [diff] [blame] | 2821 | if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) { |
| 2822 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
| 2823 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); |
| 2824 | seq_printf(m, "DC5 -> DC6 count: %d\n", |
| 2825 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); |
Mika Kuoppala | 16e11b9 | 2015-10-27 14:47:03 +0200 | [diff] [blame] | 2826 | } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) { |
| 2827 | seq_printf(m, "DC3 -> DC5 count: %d\n", |
| 2828 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); |
Damien Lespiau | 8337206 | 2015-10-30 17:53:32 +0200 | [diff] [blame] | 2829 | } |
| 2830 | |
Mika Kuoppala | 6fb403d | 2015-10-30 17:54:47 +0200 | [diff] [blame] | 2831 | out: |
| 2832 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); |
| 2833 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); |
| 2834 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); |
| 2835 | |
Damien Lespiau | 8337206 | 2015-10-30 17:53:32 +0200 | [diff] [blame] | 2836 | intel_runtime_pm_put(dev_priv); |
| 2837 | |
Damien Lespiau | b7cec66 | 2015-10-27 14:47:01 +0200 | [diff] [blame] | 2838 | return 0; |
| 2839 | } |
| 2840 | |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2841 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
| 2842 | struct drm_display_mode *mode) |
| 2843 | { |
| 2844 | int i; |
| 2845 | |
| 2846 | for (i = 0; i < tabs; i++) |
| 2847 | seq_putc(m, '\t'); |
| 2848 | |
| 2849 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", |
| 2850 | mode->base.id, mode->name, |
| 2851 | mode->vrefresh, mode->clock, |
| 2852 | mode->hdisplay, mode->hsync_start, |
| 2853 | mode->hsync_end, mode->htotal, |
| 2854 | mode->vdisplay, mode->vsync_start, |
| 2855 | mode->vsync_end, mode->vtotal, |
| 2856 | mode->type, mode->flags); |
| 2857 | } |
| 2858 | |
| 2859 | static void intel_encoder_info(struct seq_file *m, |
| 2860 | struct intel_crtc *intel_crtc, |
| 2861 | struct intel_encoder *intel_encoder) |
| 2862 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2863 | struct drm_info_node *node = m->private; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2864 | struct drm_device *dev = node->minor->dev; |
| 2865 | struct drm_crtc *crtc = &intel_crtc->base; |
| 2866 | struct intel_connector *intel_connector; |
| 2867 | struct drm_encoder *encoder; |
| 2868 | |
| 2869 | encoder = &intel_encoder->base; |
| 2870 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", |
Jani Nikula | 8e329a0 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 2871 | encoder->base.id, encoder->name); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2872 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
| 2873 | struct drm_connector *connector = &intel_connector->base; |
| 2874 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", |
| 2875 | connector->base.id, |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 2876 | connector->name, |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2877 | drm_get_connector_status_name(connector->status)); |
| 2878 | if (connector->status == connector_status_connected) { |
| 2879 | struct drm_display_mode *mode = &crtc->mode; |
| 2880 | seq_printf(m, ", mode:\n"); |
| 2881 | intel_seq_print_mode(m, 2, mode); |
| 2882 | } else { |
| 2883 | seq_putc(m, '\n'); |
| 2884 | } |
| 2885 | } |
| 2886 | } |
| 2887 | |
| 2888 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) |
| 2889 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2890 | struct drm_info_node *node = m->private; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2891 | struct drm_device *dev = node->minor->dev; |
| 2892 | struct drm_crtc *crtc = &intel_crtc->base; |
| 2893 | struct intel_encoder *intel_encoder; |
Maarten Lankhorst | 23a48d5 | 2015-09-10 16:07:57 +0200 | [diff] [blame] | 2894 | struct drm_plane_state *plane_state = crtc->primary->state; |
| 2895 | struct drm_framebuffer *fb = plane_state->fb; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2896 | |
Maarten Lankhorst | 23a48d5 | 2015-09-10 16:07:57 +0200 | [diff] [blame] | 2897 | if (fb) |
Matt Roper | 5aa8a93 | 2014-06-16 10:12:55 -0700 | [diff] [blame] | 2898 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
Maarten Lankhorst | 23a48d5 | 2015-09-10 16:07:57 +0200 | [diff] [blame] | 2899 | fb->base.id, plane_state->src_x >> 16, |
| 2900 | plane_state->src_y >> 16, fb->width, fb->height); |
Matt Roper | 5aa8a93 | 2014-06-16 10:12:55 -0700 | [diff] [blame] | 2901 | else |
| 2902 | seq_puts(m, "\tprimary plane disabled\n"); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2903 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
| 2904 | intel_encoder_info(m, intel_crtc, intel_encoder); |
| 2905 | } |
| 2906 | |
| 2907 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) |
| 2908 | { |
| 2909 | struct drm_display_mode *mode = panel->fixed_mode; |
| 2910 | |
| 2911 | seq_printf(m, "\tfixed mode:\n"); |
| 2912 | intel_seq_print_mode(m, 2, mode); |
| 2913 | } |
| 2914 | |
| 2915 | static void intel_dp_info(struct seq_file *m, |
| 2916 | struct intel_connector *intel_connector) |
| 2917 | { |
| 2918 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
| 2919 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
| 2920 | |
| 2921 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); |
Jani Nikula | 742f491 | 2015-09-03 11:16:09 +0300 | [diff] [blame] | 2922 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2923 | if (intel_encoder->type == INTEL_OUTPUT_EDP) |
| 2924 | intel_panel_info(m, &intel_connector->panel); |
| 2925 | } |
| 2926 | |
| 2927 | static void intel_hdmi_info(struct seq_file *m, |
| 2928 | struct intel_connector *intel_connector) |
| 2929 | { |
| 2930 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
| 2931 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); |
| 2932 | |
Jani Nikula | 742f491 | 2015-09-03 11:16:09 +0300 | [diff] [blame] | 2933 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2934 | } |
| 2935 | |
| 2936 | static void intel_lvds_info(struct seq_file *m, |
| 2937 | struct intel_connector *intel_connector) |
| 2938 | { |
| 2939 | intel_panel_info(m, &intel_connector->panel); |
| 2940 | } |
| 2941 | |
| 2942 | static void intel_connector_info(struct seq_file *m, |
| 2943 | struct drm_connector *connector) |
| 2944 | { |
| 2945 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 2946 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
Jesse Barnes | f103fc7 | 2014-02-20 12:39:57 -0800 | [diff] [blame] | 2947 | struct drm_display_mode *mode; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2948 | |
| 2949 | seq_printf(m, "connector %d: type %s, status: %s\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 2950 | connector->base.id, connector->name, |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2951 | drm_get_connector_status_name(connector->status)); |
| 2952 | if (connector->status == connector_status_connected) { |
| 2953 | seq_printf(m, "\tname: %s\n", connector->display_info.name); |
| 2954 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", |
| 2955 | connector->display_info.width_mm, |
| 2956 | connector->display_info.height_mm); |
| 2957 | seq_printf(m, "\tsubpixel order: %s\n", |
| 2958 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); |
| 2959 | seq_printf(m, "\tCEA rev: %d\n", |
| 2960 | connector->display_info.cea_rev); |
| 2961 | } |
Dave Airlie | 36cd744 | 2014-05-02 13:44:18 +1000 | [diff] [blame] | 2962 | if (intel_encoder) { |
| 2963 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
| 2964 | intel_encoder->type == INTEL_OUTPUT_EDP) |
| 2965 | intel_dp_info(m, intel_connector); |
| 2966 | else if (intel_encoder->type == INTEL_OUTPUT_HDMI) |
| 2967 | intel_hdmi_info(m, intel_connector); |
| 2968 | else if (intel_encoder->type == INTEL_OUTPUT_LVDS) |
| 2969 | intel_lvds_info(m, intel_connector); |
| 2970 | } |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2971 | |
Jesse Barnes | f103fc7 | 2014-02-20 12:39:57 -0800 | [diff] [blame] | 2972 | seq_printf(m, "\tmodes:\n"); |
| 2973 | list_for_each_entry(mode, &connector->modes, head) |
| 2974 | intel_seq_print_mode(m, 2, mode); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2975 | } |
| 2976 | |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2977 | static bool cursor_active(struct drm_device *dev, int pipe) |
| 2978 | { |
| 2979 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2980 | u32 state; |
| 2981 | |
| 2982 | if (IS_845G(dev) || IS_I865G(dev)) |
Ville Syrjälä | 0b87c24 | 2015-09-22 19:47:51 +0300 | [diff] [blame] | 2983 | state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2984 | else |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 2985 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2986 | |
| 2987 | return state; |
| 2988 | } |
| 2989 | |
| 2990 | static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) |
| 2991 | { |
| 2992 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2993 | u32 pos; |
| 2994 | |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 2995 | pos = I915_READ(CURPOS(pipe)); |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2996 | |
| 2997 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; |
| 2998 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) |
| 2999 | *x = -*x; |
| 3000 | |
| 3001 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; |
| 3002 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) |
| 3003 | *y = -*y; |
| 3004 | |
| 3005 | return cursor_active(dev, pipe); |
| 3006 | } |
| 3007 | |
Robert Fekete | 3abc4e0 | 2015-10-27 16:58:32 +0100 | [diff] [blame] | 3008 | static const char *plane_type(enum drm_plane_type type) |
| 3009 | { |
| 3010 | switch (type) { |
| 3011 | case DRM_PLANE_TYPE_OVERLAY: |
| 3012 | return "OVL"; |
| 3013 | case DRM_PLANE_TYPE_PRIMARY: |
| 3014 | return "PRI"; |
| 3015 | case DRM_PLANE_TYPE_CURSOR: |
| 3016 | return "CUR"; |
| 3017 | /* |
| 3018 | * Deliberately omitting default: to generate compiler warnings |
| 3019 | * when a new drm_plane_type gets added. |
| 3020 | */ |
| 3021 | } |
| 3022 | |
| 3023 | return "unknown"; |
| 3024 | } |
| 3025 | |
| 3026 | static const char *plane_rotation(unsigned int rotation) |
| 3027 | { |
| 3028 | static char buf[48]; |
| 3029 | /* |
| 3030 | * According to doc only one DRM_ROTATE_ is allowed but this |
| 3031 | * will print them all to visualize if the values are misused |
| 3032 | */ |
| 3033 | snprintf(buf, sizeof(buf), |
| 3034 | "%s%s%s%s%s%s(0x%08x)", |
| 3035 | (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "", |
| 3036 | (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "", |
| 3037 | (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "", |
| 3038 | (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "", |
| 3039 | (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "", |
| 3040 | (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "", |
| 3041 | rotation); |
| 3042 | |
| 3043 | return buf; |
| 3044 | } |
| 3045 | |
| 3046 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) |
| 3047 | { |
| 3048 | struct drm_info_node *node = m->private; |
| 3049 | struct drm_device *dev = node->minor->dev; |
| 3050 | struct intel_plane *intel_plane; |
| 3051 | |
| 3052 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
| 3053 | struct drm_plane_state *state; |
| 3054 | struct drm_plane *plane = &intel_plane->base; |
| 3055 | |
| 3056 | if (!plane->state) { |
| 3057 | seq_puts(m, "plane->state is NULL!\n"); |
| 3058 | continue; |
| 3059 | } |
| 3060 | |
| 3061 | state = plane->state; |
| 3062 | |
| 3063 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", |
| 3064 | plane->base.id, |
| 3065 | plane_type(intel_plane->base.type), |
| 3066 | state->crtc_x, state->crtc_y, |
| 3067 | state->crtc_w, state->crtc_h, |
| 3068 | (state->src_x >> 16), |
| 3069 | ((state->src_x & 0xffff) * 15625) >> 10, |
| 3070 | (state->src_y >> 16), |
| 3071 | ((state->src_y & 0xffff) * 15625) >> 10, |
| 3072 | (state->src_w >> 16), |
| 3073 | ((state->src_w & 0xffff) * 15625) >> 10, |
| 3074 | (state->src_h >> 16), |
| 3075 | ((state->src_h & 0xffff) * 15625) >> 10, |
| 3076 | state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A", |
| 3077 | plane_rotation(state->rotation)); |
| 3078 | } |
| 3079 | } |
| 3080 | |
| 3081 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) |
| 3082 | { |
| 3083 | struct intel_crtc_state *pipe_config; |
| 3084 | int num_scalers = intel_crtc->num_scalers; |
| 3085 | int i; |
| 3086 | |
| 3087 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); |
| 3088 | |
| 3089 | /* Not all platformas have a scaler */ |
| 3090 | if (num_scalers) { |
| 3091 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", |
| 3092 | num_scalers, |
| 3093 | pipe_config->scaler_state.scaler_users, |
| 3094 | pipe_config->scaler_state.scaler_id); |
| 3095 | |
| 3096 | for (i = 0; i < SKL_NUM_SCALERS; i++) { |
| 3097 | struct intel_scaler *sc = |
| 3098 | &pipe_config->scaler_state.scalers[i]; |
| 3099 | |
| 3100 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", |
| 3101 | i, yesno(sc->in_use), sc->mode); |
| 3102 | } |
| 3103 | seq_puts(m, "\n"); |
| 3104 | } else { |
| 3105 | seq_puts(m, "\tNo scalers available on this platform\n"); |
| 3106 | } |
| 3107 | } |
| 3108 | |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 3109 | static int i915_display_info(struct seq_file *m, void *unused) |
| 3110 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 3111 | struct drm_info_node *node = m->private; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 3112 | struct drm_device *dev = node->minor->dev; |
Paulo Zanoni | b0e5ddf | 2014-04-01 14:55:10 -0300 | [diff] [blame] | 3113 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 3114 | struct intel_crtc *crtc; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 3115 | struct drm_connector *connector; |
| 3116 | |
Paulo Zanoni | b0e5ddf | 2014-04-01 14:55:10 -0300 | [diff] [blame] | 3117 | intel_runtime_pm_get(dev_priv); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 3118 | drm_modeset_lock_all(dev); |
| 3119 | seq_printf(m, "CRTC info\n"); |
| 3120 | seq_printf(m, "---------\n"); |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 3121 | for_each_intel_crtc(dev, crtc) { |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 3122 | bool active; |
Maarten Lankhorst | f77076c | 2015-06-01 12:50:08 +0200 | [diff] [blame] | 3123 | struct intel_crtc_state *pipe_config; |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 3124 | int x, y; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 3125 | |
Maarten Lankhorst | f77076c | 2015-06-01 12:50:08 +0200 | [diff] [blame] | 3126 | pipe_config = to_intel_crtc_state(crtc->base.state); |
| 3127 | |
Robert Fekete | 3abc4e0 | 2015-10-27 16:58:32 +0100 | [diff] [blame] | 3128 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 3129 | crtc->base.base.id, pipe_name(crtc->pipe), |
Maarten Lankhorst | f77076c | 2015-06-01 12:50:08 +0200 | [diff] [blame] | 3130 | yesno(pipe_config->base.active), |
Robert Fekete | 3abc4e0 | 2015-10-27 16:58:32 +0100 | [diff] [blame] | 3131 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
| 3132 | yesno(pipe_config->dither), pipe_config->pipe_bpp); |
| 3133 | |
Maarten Lankhorst | f77076c | 2015-06-01 12:50:08 +0200 | [diff] [blame] | 3134 | if (pipe_config->base.active) { |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 3135 | intel_crtc_info(m, crtc); |
| 3136 | |
Paulo Zanoni | a23dc65 | 2014-04-01 14:55:11 -0300 | [diff] [blame] | 3137 | active = cursor_position(dev, crtc->pipe, &x, &y); |
Chris Wilson | 57127ef | 2014-07-04 08:20:11 +0100 | [diff] [blame] | 3138 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 3139 | yesno(crtc->cursor_base), |
Matt Roper | 3dd512f | 2015-02-27 10:12:00 -0800 | [diff] [blame] | 3140 | x, y, crtc->base.cursor->state->crtc_w, |
| 3141 | crtc->base.cursor->state->crtc_h, |
Chris Wilson | 57127ef | 2014-07-04 08:20:11 +0100 | [diff] [blame] | 3142 | crtc->cursor_addr, yesno(active)); |
Robert Fekete | 3abc4e0 | 2015-10-27 16:58:32 +0100 | [diff] [blame] | 3143 | intel_scaler_info(m, crtc); |
| 3144 | intel_plane_info(m, crtc); |
Paulo Zanoni | a23dc65 | 2014-04-01 14:55:11 -0300 | [diff] [blame] | 3145 | } |
Daniel Vetter | cace841 | 2014-05-22 17:56:31 +0200 | [diff] [blame] | 3146 | |
| 3147 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", |
| 3148 | yesno(!crtc->cpu_fifo_underrun_disabled), |
| 3149 | yesno(!crtc->pch_fifo_underrun_disabled)); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 3150 | } |
| 3151 | |
| 3152 | seq_printf(m, "\n"); |
| 3153 | seq_printf(m, "Connector info\n"); |
| 3154 | seq_printf(m, "--------------\n"); |
| 3155 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 3156 | intel_connector_info(m, connector); |
| 3157 | } |
| 3158 | drm_modeset_unlock_all(dev); |
Paulo Zanoni | b0e5ddf | 2014-04-01 14:55:10 -0300 | [diff] [blame] | 3159 | intel_runtime_pm_put(dev_priv); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 3160 | |
| 3161 | return 0; |
| 3162 | } |
| 3163 | |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 3164 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
| 3165 | { |
| 3166 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 3167 | struct drm_device *dev = node->minor->dev; |
| 3168 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3169 | struct intel_engine_cs *engine; |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 3170 | int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 3171 | enum intel_engine_id id; |
| 3172 | int j, ret; |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 3173 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3174 | if (!i915_semaphore_is_enabled(dev_priv)) { |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 3175 | seq_puts(m, "Semaphores are disabled\n"); |
| 3176 | return 0; |
| 3177 | } |
| 3178 | |
| 3179 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 3180 | if (ret) |
| 3181 | return ret; |
Paulo Zanoni | 0387206 | 2014-07-09 14:31:57 -0300 | [diff] [blame] | 3182 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 3183 | |
| 3184 | if (IS_BROADWELL(dev)) { |
| 3185 | struct page *page; |
| 3186 | uint64_t *seqno; |
| 3187 | |
| 3188 | page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0); |
| 3189 | |
| 3190 | seqno = (uint64_t *)kmap_atomic(page); |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 3191 | for_each_engine_id(engine, dev_priv, id) { |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 3192 | uint64_t offset; |
| 3193 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3194 | seq_printf(m, "%s\n", engine->name); |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 3195 | |
| 3196 | seq_puts(m, " Last signal:"); |
| 3197 | for (j = 0; j < num_rings; j++) { |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 3198 | offset = id * I915_NUM_ENGINES + j; |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 3199 | seq_printf(m, "0x%08llx (0x%02llx) ", |
| 3200 | seqno[offset], offset * 8); |
| 3201 | } |
| 3202 | seq_putc(m, '\n'); |
| 3203 | |
| 3204 | seq_puts(m, " Last wait: "); |
| 3205 | for (j = 0; j < num_rings; j++) { |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 3206 | offset = id + (j * I915_NUM_ENGINES); |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 3207 | seq_printf(m, "0x%08llx (0x%02llx) ", |
| 3208 | seqno[offset], offset * 8); |
| 3209 | } |
| 3210 | seq_putc(m, '\n'); |
| 3211 | |
| 3212 | } |
| 3213 | kunmap_atomic(seqno); |
| 3214 | } else { |
| 3215 | seq_puts(m, " Last signal:"); |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 3216 | for_each_engine(engine, dev_priv) |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 3217 | for (j = 0; j < num_rings; j++) |
| 3218 | seq_printf(m, "0x%08x\n", |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3219 | I915_READ(engine->semaphore.mbox.signal[j])); |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 3220 | seq_putc(m, '\n'); |
| 3221 | } |
| 3222 | |
| 3223 | seq_puts(m, "\nSync seqno:\n"); |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 3224 | for_each_engine(engine, dev_priv) { |
| 3225 | for (j = 0; j < num_rings; j++) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3226 | seq_printf(m, " 0x%08x ", |
| 3227 | engine->semaphore.sync_seqno[j]); |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 3228 | seq_putc(m, '\n'); |
| 3229 | } |
| 3230 | seq_putc(m, '\n'); |
| 3231 | |
Paulo Zanoni | 0387206 | 2014-07-09 14:31:57 -0300 | [diff] [blame] | 3232 | intel_runtime_pm_put(dev_priv); |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 3233 | mutex_unlock(&dev->struct_mutex); |
| 3234 | return 0; |
| 3235 | } |
| 3236 | |
Daniel Vetter | 728e29d | 2014-06-25 22:01:53 +0300 | [diff] [blame] | 3237 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
| 3238 | { |
| 3239 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 3240 | struct drm_device *dev = node->minor->dev; |
| 3241 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3242 | int i; |
| 3243 | |
| 3244 | drm_modeset_lock_all(dev); |
| 3245 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 3246 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
| 3247 | |
| 3248 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); |
Maarten Lankhorst | 2dd66ebd | 2016-03-14 09:27:52 +0100 | [diff] [blame] | 3249 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
| 3250 | pll->config.crtc_mask, pll->active_mask, yesno(pll->on)); |
Daniel Vetter | 728e29d | 2014-06-25 22:01:53 +0300 | [diff] [blame] | 3251 | seq_printf(m, " tracked hardware state:\n"); |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 3252 | seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); |
| 3253 | seq_printf(m, " dpll_md: 0x%08x\n", |
| 3254 | pll->config.hw_state.dpll_md); |
| 3255 | seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); |
| 3256 | seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); |
| 3257 | seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); |
Daniel Vetter | 728e29d | 2014-06-25 22:01:53 +0300 | [diff] [blame] | 3258 | } |
| 3259 | drm_modeset_unlock_all(dev); |
| 3260 | |
| 3261 | return 0; |
| 3262 | } |
| 3263 | |
Damien Lespiau | 1ed1ef9 | 2014-08-30 16:50:59 +0100 | [diff] [blame] | 3264 | static int i915_wa_registers(struct seq_file *m, void *unused) |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 3265 | { |
| 3266 | int i; |
| 3267 | int ret; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3268 | struct intel_engine_cs *engine; |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 3269 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 3270 | struct drm_device *dev = node->minor->dev; |
| 3271 | struct drm_i915_private *dev_priv = dev->dev_private; |
Arun Siluvery | 33136b0 | 2016-01-21 21:43:47 +0000 | [diff] [blame] | 3272 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 3273 | enum intel_engine_id id; |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 3274 | |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 3275 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 3276 | if (ret) |
| 3277 | return ret; |
| 3278 | |
| 3279 | intel_runtime_pm_get(dev_priv); |
| 3280 | |
Arun Siluvery | 33136b0 | 2016-01-21 21:43:47 +0000 | [diff] [blame] | 3281 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 3282 | for_each_engine_id(engine, dev_priv, id) |
Arun Siluvery | 33136b0 | 2016-01-21 21:43:47 +0000 | [diff] [blame] | 3283 | seq_printf(m, "HW whitelist count for %s: %d\n", |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 3284 | engine->name, workarounds->hw_whitelist_count[id]); |
Arun Siluvery | 33136b0 | 2016-01-21 21:43:47 +0000 | [diff] [blame] | 3285 | for (i = 0; i < workarounds->count; ++i) { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3286 | i915_reg_t addr; |
| 3287 | u32 mask, value, read; |
Mika Kuoppala | 2fa60f6 | 2014-10-07 17:21:27 +0300 | [diff] [blame] | 3288 | bool ok; |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 3289 | |
Arun Siluvery | 33136b0 | 2016-01-21 21:43:47 +0000 | [diff] [blame] | 3290 | addr = workarounds->reg[i].addr; |
| 3291 | mask = workarounds->reg[i].mask; |
| 3292 | value = workarounds->reg[i].value; |
Mika Kuoppala | 2fa60f6 | 2014-10-07 17:21:27 +0300 | [diff] [blame] | 3293 | read = I915_READ(addr); |
| 3294 | ok = (value & mask) == (read & mask); |
| 3295 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 3296 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 3297 | } |
| 3298 | |
| 3299 | intel_runtime_pm_put(dev_priv); |
| 3300 | mutex_unlock(&dev->struct_mutex); |
| 3301 | |
| 3302 | return 0; |
| 3303 | } |
| 3304 | |
Damien Lespiau | c5511e4 | 2014-11-04 17:06:51 +0000 | [diff] [blame] | 3305 | static int i915_ddb_info(struct seq_file *m, void *unused) |
| 3306 | { |
| 3307 | struct drm_info_node *node = m->private; |
| 3308 | struct drm_device *dev = node->minor->dev; |
| 3309 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3310 | struct skl_ddb_allocation *ddb; |
| 3311 | struct skl_ddb_entry *entry; |
| 3312 | enum pipe pipe; |
| 3313 | int plane; |
| 3314 | |
Damien Lespiau | 2fcffe1 | 2014-12-03 17:33:24 +0000 | [diff] [blame] | 3315 | if (INTEL_INFO(dev)->gen < 9) |
| 3316 | return 0; |
| 3317 | |
Damien Lespiau | c5511e4 | 2014-11-04 17:06:51 +0000 | [diff] [blame] | 3318 | drm_modeset_lock_all(dev); |
| 3319 | |
| 3320 | ddb = &dev_priv->wm.skl_hw.ddb; |
| 3321 | |
| 3322 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); |
| 3323 | |
| 3324 | for_each_pipe(dev_priv, pipe) { |
| 3325 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); |
| 3326 | |
Damien Lespiau | dd74078 | 2015-02-28 14:54:08 +0000 | [diff] [blame] | 3327 | for_each_plane(dev_priv, pipe, plane) { |
Damien Lespiau | c5511e4 | 2014-11-04 17:06:51 +0000 | [diff] [blame] | 3328 | entry = &ddb->plane[pipe][plane]; |
| 3329 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, |
| 3330 | entry->start, entry->end, |
| 3331 | skl_ddb_entry_size(entry)); |
| 3332 | } |
| 3333 | |
Matt Roper | 4969d33 | 2015-09-24 15:53:10 -0700 | [diff] [blame] | 3334 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
Damien Lespiau | c5511e4 | 2014-11-04 17:06:51 +0000 | [diff] [blame] | 3335 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
| 3336 | entry->end, skl_ddb_entry_size(entry)); |
| 3337 | } |
| 3338 | |
| 3339 | drm_modeset_unlock_all(dev); |
| 3340 | |
| 3341 | return 0; |
| 3342 | } |
| 3343 | |
Vandana Kannan | a54746e | 2015-03-03 20:53:10 +0530 | [diff] [blame] | 3344 | static void drrs_status_per_crtc(struct seq_file *m, |
| 3345 | struct drm_device *dev, struct intel_crtc *intel_crtc) |
| 3346 | { |
| 3347 | struct intel_encoder *intel_encoder; |
| 3348 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3349 | struct i915_drrs *drrs = &dev_priv->drrs; |
| 3350 | int vrefresh = 0; |
| 3351 | |
| 3352 | for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) { |
| 3353 | /* Encoder connected on this CRTC */ |
| 3354 | switch (intel_encoder->type) { |
| 3355 | case INTEL_OUTPUT_EDP: |
| 3356 | seq_puts(m, "eDP:\n"); |
| 3357 | break; |
| 3358 | case INTEL_OUTPUT_DSI: |
| 3359 | seq_puts(m, "DSI:\n"); |
| 3360 | break; |
| 3361 | case INTEL_OUTPUT_HDMI: |
| 3362 | seq_puts(m, "HDMI:\n"); |
| 3363 | break; |
| 3364 | case INTEL_OUTPUT_DISPLAYPORT: |
| 3365 | seq_puts(m, "DP:\n"); |
| 3366 | break; |
| 3367 | default: |
| 3368 | seq_printf(m, "Other encoder (id=%d).\n", |
| 3369 | intel_encoder->type); |
| 3370 | return; |
| 3371 | } |
| 3372 | } |
| 3373 | |
| 3374 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) |
| 3375 | seq_puts(m, "\tVBT: DRRS_type: Static"); |
| 3376 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) |
| 3377 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); |
| 3378 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) |
| 3379 | seq_puts(m, "\tVBT: DRRS_type: None"); |
| 3380 | else |
| 3381 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); |
| 3382 | |
| 3383 | seq_puts(m, "\n\n"); |
| 3384 | |
Maarten Lankhorst | f77076c | 2015-06-01 12:50:08 +0200 | [diff] [blame] | 3385 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
Vandana Kannan | a54746e | 2015-03-03 20:53:10 +0530 | [diff] [blame] | 3386 | struct intel_panel *panel; |
| 3387 | |
| 3388 | mutex_lock(&drrs->mutex); |
| 3389 | /* DRRS Supported */ |
| 3390 | seq_puts(m, "\tDRRS Supported: Yes\n"); |
| 3391 | |
| 3392 | /* disable_drrs() will make drrs->dp NULL */ |
| 3393 | if (!drrs->dp) { |
| 3394 | seq_puts(m, "Idleness DRRS: Disabled"); |
| 3395 | mutex_unlock(&drrs->mutex); |
| 3396 | return; |
| 3397 | } |
| 3398 | |
| 3399 | panel = &drrs->dp->attached_connector->panel; |
| 3400 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", |
| 3401 | drrs->busy_frontbuffer_bits); |
| 3402 | |
| 3403 | seq_puts(m, "\n\t\t"); |
| 3404 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { |
| 3405 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); |
| 3406 | vrefresh = panel->fixed_mode->vrefresh; |
| 3407 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { |
| 3408 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); |
| 3409 | vrefresh = panel->downclock_mode->vrefresh; |
| 3410 | } else { |
| 3411 | seq_printf(m, "DRRS_State: Unknown(%d)\n", |
| 3412 | drrs->refresh_rate_type); |
| 3413 | mutex_unlock(&drrs->mutex); |
| 3414 | return; |
| 3415 | } |
| 3416 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); |
| 3417 | |
| 3418 | seq_puts(m, "\n\t\t"); |
| 3419 | mutex_unlock(&drrs->mutex); |
| 3420 | } else { |
| 3421 | /* DRRS not supported. Print the VBT parameter*/ |
| 3422 | seq_puts(m, "\tDRRS Supported : No"); |
| 3423 | } |
| 3424 | seq_puts(m, "\n"); |
| 3425 | } |
| 3426 | |
| 3427 | static int i915_drrs_status(struct seq_file *m, void *unused) |
| 3428 | { |
| 3429 | struct drm_info_node *node = m->private; |
| 3430 | struct drm_device *dev = node->minor->dev; |
| 3431 | struct intel_crtc *intel_crtc; |
| 3432 | int active_crtc_cnt = 0; |
| 3433 | |
| 3434 | for_each_intel_crtc(dev, intel_crtc) { |
| 3435 | drm_modeset_lock(&intel_crtc->base.mutex, NULL); |
| 3436 | |
Maarten Lankhorst | f77076c | 2015-06-01 12:50:08 +0200 | [diff] [blame] | 3437 | if (intel_crtc->base.state->active) { |
Vandana Kannan | a54746e | 2015-03-03 20:53:10 +0530 | [diff] [blame] | 3438 | active_crtc_cnt++; |
| 3439 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); |
| 3440 | |
| 3441 | drrs_status_per_crtc(m, dev, intel_crtc); |
| 3442 | } |
| 3443 | |
| 3444 | drm_modeset_unlock(&intel_crtc->base.mutex); |
| 3445 | } |
| 3446 | |
| 3447 | if (!active_crtc_cnt) |
| 3448 | seq_puts(m, "No active crtc found\n"); |
| 3449 | |
| 3450 | return 0; |
| 3451 | } |
| 3452 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3453 | struct pipe_crc_info { |
| 3454 | const char *name; |
| 3455 | struct drm_device *dev; |
| 3456 | enum pipe pipe; |
| 3457 | }; |
| 3458 | |
Dave Airlie | 11bed958 | 2014-05-12 15:22:27 +1000 | [diff] [blame] | 3459 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
| 3460 | { |
| 3461 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 3462 | struct drm_device *dev = node->minor->dev; |
| 3463 | struct drm_encoder *encoder; |
| 3464 | struct intel_encoder *intel_encoder; |
| 3465 | struct intel_digital_port *intel_dig_port; |
| 3466 | drm_modeset_lock_all(dev); |
| 3467 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 3468 | intel_encoder = to_intel_encoder(encoder); |
| 3469 | if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT) |
| 3470 | continue; |
| 3471 | intel_dig_port = enc_to_dig_port(encoder); |
| 3472 | if (!intel_dig_port->dp.can_mst) |
| 3473 | continue; |
Jim Bride | 40ae80c | 2016-04-14 10:18:37 -0700 | [diff] [blame] | 3474 | seq_printf(m, "MST Source Port %c\n", |
| 3475 | port_name(intel_dig_port->port)); |
Dave Airlie | 11bed958 | 2014-05-12 15:22:27 +1000 | [diff] [blame] | 3476 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
| 3477 | } |
| 3478 | drm_modeset_unlock_all(dev); |
| 3479 | return 0; |
| 3480 | } |
| 3481 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3482 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 3483 | { |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 3484 | struct pipe_crc_info *info = inode->i_private; |
| 3485 | struct drm_i915_private *dev_priv = info->dev->dev_private; |
| 3486 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
| 3487 | |
Daniel Vetter | 7eb1c49 | 2013-11-14 11:30:43 +0100 | [diff] [blame] | 3488 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
| 3489 | return -ENODEV; |
| 3490 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3491 | spin_lock_irq(&pipe_crc->lock); |
| 3492 | |
| 3493 | if (pipe_crc->opened) { |
| 3494 | spin_unlock_irq(&pipe_crc->lock); |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 3495 | return -EBUSY; /* already open */ |
| 3496 | } |
| 3497 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3498 | pipe_crc->opened = true; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3499 | filep->private_data = inode->i_private; |
| 3500 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3501 | spin_unlock_irq(&pipe_crc->lock); |
| 3502 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3503 | return 0; |
| 3504 | } |
| 3505 | |
| 3506 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) |
| 3507 | { |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 3508 | struct pipe_crc_info *info = inode->i_private; |
| 3509 | struct drm_i915_private *dev_priv = info->dev->dev_private; |
| 3510 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
| 3511 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3512 | spin_lock_irq(&pipe_crc->lock); |
| 3513 | pipe_crc->opened = false; |
| 3514 | spin_unlock_irq(&pipe_crc->lock); |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 3515 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3516 | return 0; |
| 3517 | } |
| 3518 | |
| 3519 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ |
| 3520 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) |
| 3521 | /* account for \'0' */ |
| 3522 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) |
| 3523 | |
| 3524 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) |
| 3525 | { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3526 | assert_spin_locked(&pipe_crc->lock); |
| 3527 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
| 3528 | INTEL_PIPE_CRC_ENTRIES_NR); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3529 | } |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 3530 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3531 | static ssize_t |
| 3532 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, |
| 3533 | loff_t *pos) |
| 3534 | { |
| 3535 | struct pipe_crc_info *info = filep->private_data; |
| 3536 | struct drm_device *dev = info->dev; |
| 3537 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3538 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
| 3539 | char buf[PIPE_CRC_BUFFER_LEN]; |
Ville Syrjälä | 9ad6d99 | 2014-12-09 21:28:32 +0200 | [diff] [blame] | 3540 | int n_entries; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3541 | ssize_t bytes_read; |
| 3542 | |
| 3543 | /* |
| 3544 | * Don't allow user space to provide buffers not big enough to hold |
| 3545 | * a line of data. |
| 3546 | */ |
| 3547 | if (count < PIPE_CRC_LINE_LEN) |
| 3548 | return -EINVAL; |
| 3549 | |
| 3550 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) |
| 3551 | return 0; |
| 3552 | |
| 3553 | /* nothing to read */ |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3554 | spin_lock_irq(&pipe_crc->lock); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3555 | while (pipe_crc_data_count(pipe_crc) == 0) { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3556 | int ret; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3557 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3558 | if (filep->f_flags & O_NONBLOCK) { |
| 3559 | spin_unlock_irq(&pipe_crc->lock); |
| 3560 | return -EAGAIN; |
| 3561 | } |
| 3562 | |
| 3563 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
| 3564 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); |
| 3565 | if (ret) { |
| 3566 | spin_unlock_irq(&pipe_crc->lock); |
| 3567 | return ret; |
| 3568 | } |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3569 | } |
| 3570 | |
| 3571 | /* We now have one or more entries to read */ |
Ville Syrjälä | 9ad6d99 | 2014-12-09 21:28:32 +0200 | [diff] [blame] | 3572 | n_entries = count / PIPE_CRC_LINE_LEN; |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3573 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3574 | bytes_read = 0; |
Ville Syrjälä | 9ad6d99 | 2014-12-09 21:28:32 +0200 | [diff] [blame] | 3575 | while (n_entries > 0) { |
| 3576 | struct intel_pipe_crc_entry *entry = |
| 3577 | &pipe_crc->entries[pipe_crc->tail]; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3578 | int ret; |
| 3579 | |
Ville Syrjälä | 9ad6d99 | 2014-12-09 21:28:32 +0200 | [diff] [blame] | 3580 | if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
| 3581 | INTEL_PIPE_CRC_ENTRIES_NR) < 1) |
| 3582 | break; |
| 3583 | |
| 3584 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); |
| 3585 | pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); |
| 3586 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3587 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
| 3588 | "%8u %8x %8x %8x %8x %8x\n", |
| 3589 | entry->frame, entry->crc[0], |
| 3590 | entry->crc[1], entry->crc[2], |
| 3591 | entry->crc[3], entry->crc[4]); |
| 3592 | |
Ville Syrjälä | 9ad6d99 | 2014-12-09 21:28:32 +0200 | [diff] [blame] | 3593 | spin_unlock_irq(&pipe_crc->lock); |
| 3594 | |
| 3595 | ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3596 | if (ret == PIPE_CRC_LINE_LEN) |
| 3597 | return -EFAULT; |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 3598 | |
Ville Syrjälä | 9ad6d99 | 2014-12-09 21:28:32 +0200 | [diff] [blame] | 3599 | user_buf += PIPE_CRC_LINE_LEN; |
| 3600 | n_entries--; |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 3601 | |
Ville Syrjälä | 9ad6d99 | 2014-12-09 21:28:32 +0200 | [diff] [blame] | 3602 | spin_lock_irq(&pipe_crc->lock); |
| 3603 | } |
| 3604 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3605 | spin_unlock_irq(&pipe_crc->lock); |
| 3606 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3607 | return bytes_read; |
| 3608 | } |
| 3609 | |
| 3610 | static const struct file_operations i915_pipe_crc_fops = { |
| 3611 | .owner = THIS_MODULE, |
| 3612 | .open = i915_pipe_crc_open, |
| 3613 | .read = i915_pipe_crc_read, |
| 3614 | .release = i915_pipe_crc_release, |
| 3615 | }; |
| 3616 | |
| 3617 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { |
| 3618 | { |
| 3619 | .name = "i915_pipe_A_crc", |
| 3620 | .pipe = PIPE_A, |
| 3621 | }, |
| 3622 | { |
| 3623 | .name = "i915_pipe_B_crc", |
| 3624 | .pipe = PIPE_B, |
| 3625 | }, |
| 3626 | { |
| 3627 | .name = "i915_pipe_C_crc", |
| 3628 | .pipe = PIPE_C, |
| 3629 | }, |
| 3630 | }; |
| 3631 | |
| 3632 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, |
| 3633 | enum pipe pipe) |
| 3634 | { |
| 3635 | struct drm_device *dev = minor->dev; |
| 3636 | struct dentry *ent; |
| 3637 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; |
| 3638 | |
| 3639 | info->dev = dev; |
| 3640 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, |
| 3641 | &i915_pipe_crc_fops); |
Wei Yongjun | f3c5fe9 | 2013-12-16 14:13:25 +0800 | [diff] [blame] | 3642 | if (!ent) |
| 3643 | return -ENOMEM; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3644 | |
| 3645 | return drm_add_fake_info_node(minor, ent, info); |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 3646 | } |
| 3647 | |
Daniel Vetter | e8dfcf7 | 2013-10-16 11:51:54 +0200 | [diff] [blame] | 3648 | static const char * const pipe_crc_sources[] = { |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3649 | "none", |
| 3650 | "plane1", |
| 3651 | "plane2", |
| 3652 | "pf", |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3653 | "pipe", |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 3654 | "TV", |
| 3655 | "DP-B", |
| 3656 | "DP-C", |
| 3657 | "DP-D", |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3658 | "auto", |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3659 | }; |
| 3660 | |
| 3661 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) |
| 3662 | { |
| 3663 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); |
| 3664 | return pipe_crc_sources[source]; |
| 3665 | } |
| 3666 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3667 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3668 | { |
| 3669 | struct drm_device *dev = m->private; |
| 3670 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3671 | int i; |
| 3672 | |
| 3673 | for (i = 0; i < I915_MAX_PIPES; i++) |
| 3674 | seq_printf(m, "%c %s\n", pipe_name(i), |
| 3675 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); |
| 3676 | |
| 3677 | return 0; |
| 3678 | } |
| 3679 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3680 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3681 | { |
| 3682 | struct drm_device *dev = inode->i_private; |
| 3683 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3684 | return single_open(file, display_crc_ctl_show, dev); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3685 | } |
| 3686 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3687 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 3688 | uint32_t *val) |
| 3689 | { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3690 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
| 3691 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; |
| 3692 | |
| 3693 | switch (*source) { |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 3694 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 3695 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; |
| 3696 | break; |
| 3697 | case INTEL_PIPE_CRC_SOURCE_NONE: |
| 3698 | *val = 0; |
| 3699 | break; |
| 3700 | default: |
| 3701 | return -EINVAL; |
| 3702 | } |
| 3703 | |
| 3704 | return 0; |
| 3705 | } |
| 3706 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3707 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
| 3708 | enum intel_pipe_crc_source *source) |
| 3709 | { |
| 3710 | struct intel_encoder *encoder; |
| 3711 | struct intel_crtc *crtc; |
Daniel Vetter | 2675680 | 2013-11-01 10:50:23 +0100 | [diff] [blame] | 3712 | struct intel_digital_port *dig_port; |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3713 | int ret = 0; |
| 3714 | |
| 3715 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; |
| 3716 | |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 3717 | drm_modeset_lock_all(dev); |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 3718 | for_each_intel_encoder(dev, encoder) { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3719 | if (!encoder->base.crtc) |
| 3720 | continue; |
| 3721 | |
| 3722 | crtc = to_intel_crtc(encoder->base.crtc); |
| 3723 | |
| 3724 | if (crtc->pipe != pipe) |
| 3725 | continue; |
| 3726 | |
| 3727 | switch (encoder->type) { |
| 3728 | case INTEL_OUTPUT_TVOUT: |
| 3729 | *source = INTEL_PIPE_CRC_SOURCE_TV; |
| 3730 | break; |
| 3731 | case INTEL_OUTPUT_DISPLAYPORT: |
| 3732 | case INTEL_OUTPUT_EDP: |
Daniel Vetter | 2675680 | 2013-11-01 10:50:23 +0100 | [diff] [blame] | 3733 | dig_port = enc_to_dig_port(&encoder->base); |
| 3734 | switch (dig_port->port) { |
| 3735 | case PORT_B: |
| 3736 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; |
| 3737 | break; |
| 3738 | case PORT_C: |
| 3739 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; |
| 3740 | break; |
| 3741 | case PORT_D: |
| 3742 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; |
| 3743 | break; |
| 3744 | default: |
| 3745 | WARN(1, "nonexisting DP port %c\n", |
| 3746 | port_name(dig_port->port)); |
| 3747 | break; |
| 3748 | } |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3749 | break; |
Paulo Zanoni | 6847d71 | 2014-10-27 17:47:52 -0200 | [diff] [blame] | 3750 | default: |
| 3751 | break; |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3752 | } |
| 3753 | } |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 3754 | drm_modeset_unlock_all(dev); |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3755 | |
| 3756 | return ret; |
| 3757 | } |
| 3758 | |
| 3759 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, |
| 3760 | enum pipe pipe, |
| 3761 | enum intel_pipe_crc_source *source, |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3762 | uint32_t *val) |
| 3763 | { |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3764 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3765 | bool need_stable_symbols = false; |
| 3766 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3767 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
| 3768 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); |
| 3769 | if (ret) |
| 3770 | return ret; |
| 3771 | } |
| 3772 | |
| 3773 | switch (*source) { |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3774 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 3775 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; |
| 3776 | break; |
| 3777 | case INTEL_PIPE_CRC_SOURCE_DP_B: |
| 3778 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3779 | need_stable_symbols = true; |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3780 | break; |
| 3781 | case INTEL_PIPE_CRC_SOURCE_DP_C: |
| 3782 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3783 | need_stable_symbols = true; |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3784 | break; |
Ville Syrjälä | 2be5792 | 2014-12-09 21:28:29 +0200 | [diff] [blame] | 3785 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
| 3786 | if (!IS_CHERRYVIEW(dev)) |
| 3787 | return -EINVAL; |
| 3788 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; |
| 3789 | need_stable_symbols = true; |
| 3790 | break; |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3791 | case INTEL_PIPE_CRC_SOURCE_NONE: |
| 3792 | *val = 0; |
| 3793 | break; |
| 3794 | default: |
| 3795 | return -EINVAL; |
| 3796 | } |
| 3797 | |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3798 | /* |
| 3799 | * When the pipe CRC tap point is after the transcoders we need |
| 3800 | * to tweak symbol-level features to produce a deterministic series of |
| 3801 | * symbols for a given frame. We need to reset those features only once |
| 3802 | * a frame (instead of every nth symbol): |
| 3803 | * - DC-balance: used to ensure a better clock recovery from the data |
| 3804 | * link (SDVO) |
| 3805 | * - DisplayPort scrambling: used for EMI reduction |
| 3806 | */ |
| 3807 | if (need_stable_symbols) { |
| 3808 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 3809 | |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3810 | tmp |= DC_BALANCE_RESET_VLV; |
Ville Syrjälä | eb73667 | 2014-12-09 21:28:28 +0200 | [diff] [blame] | 3811 | switch (pipe) { |
| 3812 | case PIPE_A: |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3813 | tmp |= PIPE_A_SCRAMBLE_RESET; |
Ville Syrjälä | eb73667 | 2014-12-09 21:28:28 +0200 | [diff] [blame] | 3814 | break; |
| 3815 | case PIPE_B: |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3816 | tmp |= PIPE_B_SCRAMBLE_RESET; |
Ville Syrjälä | eb73667 | 2014-12-09 21:28:28 +0200 | [diff] [blame] | 3817 | break; |
| 3818 | case PIPE_C: |
| 3819 | tmp |= PIPE_C_SCRAMBLE_RESET; |
| 3820 | break; |
| 3821 | default: |
| 3822 | return -EINVAL; |
| 3823 | } |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3824 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 3825 | } |
| 3826 | |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3827 | return 0; |
| 3828 | } |
| 3829 | |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3830 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3831 | enum pipe pipe, |
| 3832 | enum intel_pipe_crc_source *source, |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3833 | uint32_t *val) |
| 3834 | { |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3835 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3836 | bool need_stable_symbols = false; |
| 3837 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3838 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
| 3839 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); |
| 3840 | if (ret) |
| 3841 | return ret; |
| 3842 | } |
| 3843 | |
| 3844 | switch (*source) { |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3845 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 3846 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; |
| 3847 | break; |
| 3848 | case INTEL_PIPE_CRC_SOURCE_TV: |
| 3849 | if (!SUPPORTS_TV(dev)) |
| 3850 | return -EINVAL; |
| 3851 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; |
| 3852 | break; |
| 3853 | case INTEL_PIPE_CRC_SOURCE_DP_B: |
| 3854 | if (!IS_G4X(dev)) |
| 3855 | return -EINVAL; |
| 3856 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3857 | need_stable_symbols = true; |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3858 | break; |
| 3859 | case INTEL_PIPE_CRC_SOURCE_DP_C: |
| 3860 | if (!IS_G4X(dev)) |
| 3861 | return -EINVAL; |
| 3862 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3863 | need_stable_symbols = true; |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3864 | break; |
| 3865 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
| 3866 | if (!IS_G4X(dev)) |
| 3867 | return -EINVAL; |
| 3868 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3869 | need_stable_symbols = true; |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3870 | break; |
| 3871 | case INTEL_PIPE_CRC_SOURCE_NONE: |
| 3872 | *val = 0; |
| 3873 | break; |
| 3874 | default: |
| 3875 | return -EINVAL; |
| 3876 | } |
| 3877 | |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3878 | /* |
| 3879 | * When the pipe CRC tap point is after the transcoders we need |
| 3880 | * to tweak symbol-level features to produce a deterministic series of |
| 3881 | * symbols for a given frame. We need to reset those features only once |
| 3882 | * a frame (instead of every nth symbol): |
| 3883 | * - DC-balance: used to ensure a better clock recovery from the data |
| 3884 | * link (SDVO) |
| 3885 | * - DisplayPort scrambling: used for EMI reduction |
| 3886 | */ |
| 3887 | if (need_stable_symbols) { |
| 3888 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 3889 | |
| 3890 | WARN_ON(!IS_G4X(dev)); |
| 3891 | |
| 3892 | I915_WRITE(PORT_DFT_I9XX, |
| 3893 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); |
| 3894 | |
| 3895 | if (pipe == PIPE_A) |
| 3896 | tmp |= PIPE_A_SCRAMBLE_RESET; |
| 3897 | else |
| 3898 | tmp |= PIPE_B_SCRAMBLE_RESET; |
| 3899 | |
| 3900 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 3901 | } |
| 3902 | |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3903 | return 0; |
| 3904 | } |
| 3905 | |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3906 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
| 3907 | enum pipe pipe) |
| 3908 | { |
| 3909 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3910 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 3911 | |
Ville Syrjälä | eb73667 | 2014-12-09 21:28:28 +0200 | [diff] [blame] | 3912 | switch (pipe) { |
| 3913 | case PIPE_A: |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3914 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
Ville Syrjälä | eb73667 | 2014-12-09 21:28:28 +0200 | [diff] [blame] | 3915 | break; |
| 3916 | case PIPE_B: |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3917 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
Ville Syrjälä | eb73667 | 2014-12-09 21:28:28 +0200 | [diff] [blame] | 3918 | break; |
| 3919 | case PIPE_C: |
| 3920 | tmp &= ~PIPE_C_SCRAMBLE_RESET; |
| 3921 | break; |
| 3922 | default: |
| 3923 | return; |
| 3924 | } |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3925 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
| 3926 | tmp &= ~DC_BALANCE_RESET_VLV; |
| 3927 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 3928 | |
| 3929 | } |
| 3930 | |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3931 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
| 3932 | enum pipe pipe) |
| 3933 | { |
| 3934 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3935 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 3936 | |
| 3937 | if (pipe == PIPE_A) |
| 3938 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
| 3939 | else |
| 3940 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
| 3941 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 3942 | |
| 3943 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { |
| 3944 | I915_WRITE(PORT_DFT_I9XX, |
| 3945 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); |
| 3946 | } |
| 3947 | } |
| 3948 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3949 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3950 | uint32_t *val) |
| 3951 | { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3952 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
| 3953 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; |
| 3954 | |
| 3955 | switch (*source) { |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3956 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
| 3957 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; |
| 3958 | break; |
| 3959 | case INTEL_PIPE_CRC_SOURCE_PLANE2: |
| 3960 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; |
| 3961 | break; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3962 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 3963 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; |
| 3964 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 3965 | case INTEL_PIPE_CRC_SOURCE_NONE: |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3966 | *val = 0; |
| 3967 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 3968 | default: |
| 3969 | return -EINVAL; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3970 | } |
| 3971 | |
| 3972 | return 0; |
| 3973 | } |
| 3974 | |
Maarten Lankhorst | c4e2d04 | 2015-08-05 12:36:59 +0200 | [diff] [blame] | 3975 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable) |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3976 | { |
| 3977 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3978 | struct intel_crtc *crtc = |
| 3979 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); |
Maarten Lankhorst | f77076c | 2015-06-01 12:50:08 +0200 | [diff] [blame] | 3980 | struct intel_crtc_state *pipe_config; |
Maarten Lankhorst | c4e2d04 | 2015-08-05 12:36:59 +0200 | [diff] [blame] | 3981 | struct drm_atomic_state *state; |
| 3982 | int ret = 0; |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3983 | |
| 3984 | drm_modeset_lock_all(dev); |
Maarten Lankhorst | c4e2d04 | 2015-08-05 12:36:59 +0200 | [diff] [blame] | 3985 | state = drm_atomic_state_alloc(dev); |
| 3986 | if (!state) { |
| 3987 | ret = -ENOMEM; |
| 3988 | goto out; |
| 3989 | } |
Maarten Lankhorst | f77076c | 2015-06-01 12:50:08 +0200 | [diff] [blame] | 3990 | |
Maarten Lankhorst | c4e2d04 | 2015-08-05 12:36:59 +0200 | [diff] [blame] | 3991 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base); |
| 3992 | pipe_config = intel_atomic_get_crtc_state(state, crtc); |
| 3993 | if (IS_ERR(pipe_config)) { |
| 3994 | ret = PTR_ERR(pipe_config); |
| 3995 | goto out; |
| 3996 | } |
| 3997 | |
| 3998 | pipe_config->pch_pfit.force_thru = enable; |
Maarten Lankhorst | f77076c | 2015-06-01 12:50:08 +0200 | [diff] [blame] | 3999 | if (pipe_config->cpu_transcoder == TRANSCODER_EDP && |
Maarten Lankhorst | c4e2d04 | 2015-08-05 12:36:59 +0200 | [diff] [blame] | 4000 | pipe_config->pch_pfit.enabled != enable) |
| 4001 | pipe_config->base.connectors_changed = true; |
Maarten Lankhorst | 1b50925 | 2015-06-01 12:49:48 +0200 | [diff] [blame] | 4002 | |
Maarten Lankhorst | c4e2d04 | 2015-08-05 12:36:59 +0200 | [diff] [blame] | 4003 | ret = drm_atomic_commit(state); |
| 4004 | out: |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 4005 | drm_modeset_unlock_all(dev); |
Maarten Lankhorst | c4e2d04 | 2015-08-05 12:36:59 +0200 | [diff] [blame] | 4006 | WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret); |
| 4007 | if (ret) |
| 4008 | drm_atomic_state_free(state); |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 4009 | } |
| 4010 | |
| 4011 | static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, |
| 4012 | enum pipe pipe, |
| 4013 | enum intel_pipe_crc_source *source, |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 4014 | uint32_t *val) |
| 4015 | { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 4016 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
| 4017 | *source = INTEL_PIPE_CRC_SOURCE_PF; |
| 4018 | |
| 4019 | switch (*source) { |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 4020 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
| 4021 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; |
| 4022 | break; |
| 4023 | case INTEL_PIPE_CRC_SOURCE_PLANE2: |
| 4024 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; |
| 4025 | break; |
| 4026 | case INTEL_PIPE_CRC_SOURCE_PF: |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 4027 | if (IS_HASWELL(dev) && pipe == PIPE_A) |
Maarten Lankhorst | c4e2d04 | 2015-08-05 12:36:59 +0200 | [diff] [blame] | 4028 | hsw_trans_edp_pipe_A_crc_wa(dev, true); |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 4029 | |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 4030 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
| 4031 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 4032 | case INTEL_PIPE_CRC_SOURCE_NONE: |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 4033 | *val = 0; |
| 4034 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 4035 | default: |
| 4036 | return -EINVAL; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 4037 | } |
| 4038 | |
| 4039 | return 0; |
| 4040 | } |
| 4041 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4042 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
| 4043 | enum intel_pipe_crc_source source) |
| 4044 | { |
| 4045 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | cc3da17 | 2013-10-15 18:55:31 +0100 | [diff] [blame] | 4046 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
Paulo Zanoni | 8c740dc | 2014-10-17 18:42:03 -0300 | [diff] [blame] | 4047 | struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, |
| 4048 | pipe)); |
Imre Deak | e129649 | 2016-02-12 18:55:17 +0200 | [diff] [blame] | 4049 | enum intel_display_power_domain power_domain; |
Borislav Petkov | 432f334 | 2013-11-21 16:49:46 +0100 | [diff] [blame] | 4050 | u32 val = 0; /* shut up gcc */ |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 4051 | int ret; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4052 | |
Damien Lespiau | cc3da17 | 2013-10-15 18:55:31 +0100 | [diff] [blame] | 4053 | if (pipe_crc->source == source) |
| 4054 | return 0; |
| 4055 | |
Damien Lespiau | ae676fc | 2013-10-15 18:55:32 +0100 | [diff] [blame] | 4056 | /* forbid changing the source without going back to 'none' */ |
| 4057 | if (pipe_crc->source && source) |
| 4058 | return -EINVAL; |
| 4059 | |
Imre Deak | e129649 | 2016-02-12 18:55:17 +0200 | [diff] [blame] | 4060 | power_domain = POWER_DOMAIN_PIPE(pipe); |
| 4061 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) { |
Daniel Vetter | 9d8b058 | 2014-11-25 14:00:40 +0100 | [diff] [blame] | 4062 | DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); |
| 4063 | return -EIO; |
| 4064 | } |
| 4065 | |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 4066 | if (IS_GEN2(dev)) |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 4067 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 4068 | else if (INTEL_INFO(dev)->gen < 5) |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 4069 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 4070 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 4071 | ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 4072 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 4073 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 4074 | else |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 4075 | ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 4076 | |
| 4077 | if (ret != 0) |
Imre Deak | e129649 | 2016-02-12 18:55:17 +0200 | [diff] [blame] | 4078 | goto out; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 4079 | |
Damien Lespiau | 4b58436 | 2013-10-15 18:55:33 +0100 | [diff] [blame] | 4080 | /* none -> real source transition */ |
| 4081 | if (source) { |
Ville Syrjälä | 4252fbc | 2014-12-09 21:28:30 +0200 | [diff] [blame] | 4082 | struct intel_pipe_crc_entry *entries; |
| 4083 | |
Damien Lespiau | 7cd6ccf | 2013-10-15 18:55:38 +0100 | [diff] [blame] | 4084 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
| 4085 | pipe_name(pipe), pipe_crc_source_name(source)); |
| 4086 | |
Ville Syrjälä | 3cf54b3 | 2014-12-09 21:28:31 +0200 | [diff] [blame] | 4087 | entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, |
| 4088 | sizeof(pipe_crc->entries[0]), |
Ville Syrjälä | 4252fbc | 2014-12-09 21:28:30 +0200 | [diff] [blame] | 4089 | GFP_KERNEL); |
Imre Deak | e129649 | 2016-02-12 18:55:17 +0200 | [diff] [blame] | 4090 | if (!entries) { |
| 4091 | ret = -ENOMEM; |
| 4092 | goto out; |
| 4093 | } |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 4094 | |
Paulo Zanoni | 8c740dc | 2014-10-17 18:42:03 -0300 | [diff] [blame] | 4095 | /* |
| 4096 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets |
| 4097 | * enabled and disabled dynamically based on package C states, |
| 4098 | * user space can't make reliable use of the CRCs, so let's just |
| 4099 | * completely disable it. |
| 4100 | */ |
| 4101 | hsw_disable_ips(crtc); |
| 4102 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 4103 | spin_lock_irq(&pipe_crc->lock); |
Daniel Vetter | 64387b6 | 2014-12-10 11:00:29 +0100 | [diff] [blame] | 4104 | kfree(pipe_crc->entries); |
Ville Syrjälä | 4252fbc | 2014-12-09 21:28:30 +0200 | [diff] [blame] | 4105 | pipe_crc->entries = entries; |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 4106 | pipe_crc->head = 0; |
| 4107 | pipe_crc->tail = 0; |
| 4108 | spin_unlock_irq(&pipe_crc->lock); |
Damien Lespiau | 4b58436 | 2013-10-15 18:55:33 +0100 | [diff] [blame] | 4109 | } |
| 4110 | |
Damien Lespiau | cc3da17 | 2013-10-15 18:55:31 +0100 | [diff] [blame] | 4111 | pipe_crc->source = source; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4112 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4113 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
| 4114 | POSTING_READ(PIPE_CRC_CTL(pipe)); |
| 4115 | |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 4116 | /* real source -> none transition */ |
| 4117 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 4118 | struct intel_pipe_crc_entry *entries; |
Daniel Vetter | a33d710 | 2014-06-06 08:22:08 +0200 | [diff] [blame] | 4119 | struct intel_crtc *crtc = |
| 4120 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 4121 | |
Damien Lespiau | 7cd6ccf | 2013-10-15 18:55:38 +0100 | [diff] [blame] | 4122 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
| 4123 | pipe_name(pipe)); |
| 4124 | |
Daniel Vetter | a33d710 | 2014-06-06 08:22:08 +0200 | [diff] [blame] | 4125 | drm_modeset_lock(&crtc->base.mutex, NULL); |
Maarten Lankhorst | f77076c | 2015-06-01 12:50:08 +0200 | [diff] [blame] | 4126 | if (crtc->base.state->active) |
Daniel Vetter | a33d710 | 2014-06-06 08:22:08 +0200 | [diff] [blame] | 4127 | intel_wait_for_vblank(dev, pipe); |
| 4128 | drm_modeset_unlock(&crtc->base.mutex); |
Daniel Vetter | bcf17ab | 2013-10-16 22:55:50 +0200 | [diff] [blame] | 4129 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 4130 | spin_lock_irq(&pipe_crc->lock); |
| 4131 | entries = pipe_crc->entries; |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 4132 | pipe_crc->entries = NULL; |
Ville Syrjälä | 9ad6d99 | 2014-12-09 21:28:32 +0200 | [diff] [blame] | 4133 | pipe_crc->head = 0; |
| 4134 | pipe_crc->tail = 0; |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 4135 | spin_unlock_irq(&pipe_crc->lock); |
| 4136 | |
| 4137 | kfree(entries); |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 4138 | |
| 4139 | if (IS_G4X(dev)) |
| 4140 | g4x_undo_pipe_scramble_reset(dev, pipe); |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 4141 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 4142 | vlv_undo_pipe_scramble_reset(dev, pipe); |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 4143 | else if (IS_HASWELL(dev) && pipe == PIPE_A) |
Maarten Lankhorst | c4e2d04 | 2015-08-05 12:36:59 +0200 | [diff] [blame] | 4144 | hsw_trans_edp_pipe_A_crc_wa(dev, false); |
Paulo Zanoni | 8c740dc | 2014-10-17 18:42:03 -0300 | [diff] [blame] | 4145 | |
| 4146 | hsw_enable_ips(crtc); |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 4147 | } |
| 4148 | |
Imre Deak | e129649 | 2016-02-12 18:55:17 +0200 | [diff] [blame] | 4149 | ret = 0; |
| 4150 | |
| 4151 | out: |
| 4152 | intel_display_power_put(dev_priv, power_domain); |
| 4153 | |
| 4154 | return ret; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4155 | } |
| 4156 | |
| 4157 | /* |
| 4158 | * Parse pipe CRC command strings: |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 4159 | * command: wsp* object wsp+ name wsp+ source wsp* |
| 4160 | * object: 'pipe' |
| 4161 | * name: (A | B | C) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4162 | * source: (none | plane1 | plane2 | pf) |
| 4163 | * wsp: (#0x20 | #0x9 | #0xA)+ |
| 4164 | * |
| 4165 | * eg.: |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 4166 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
| 4167 | * "pipe A none" -> Stop CRC |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4168 | */ |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 4169 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4170 | { |
| 4171 | int n_words = 0; |
| 4172 | |
| 4173 | while (*buf) { |
| 4174 | char *end; |
| 4175 | |
| 4176 | /* skip leading white space */ |
| 4177 | buf = skip_spaces(buf); |
| 4178 | if (!*buf) |
| 4179 | break; /* end of buffer */ |
| 4180 | |
| 4181 | /* find end of word */ |
| 4182 | for (end = buf; *end && !isspace(*end); end++) |
| 4183 | ; |
| 4184 | |
| 4185 | if (n_words == max_words) { |
| 4186 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", |
| 4187 | max_words); |
| 4188 | return -EINVAL; /* ran out of words[] before bytes */ |
| 4189 | } |
| 4190 | |
| 4191 | if (*end) |
| 4192 | *end++ = '\0'; |
| 4193 | words[n_words++] = buf; |
| 4194 | buf = end; |
| 4195 | } |
| 4196 | |
| 4197 | return n_words; |
| 4198 | } |
| 4199 | |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 4200 | enum intel_pipe_crc_object { |
| 4201 | PIPE_CRC_OBJECT_PIPE, |
| 4202 | }; |
| 4203 | |
Daniel Vetter | e8dfcf7 | 2013-10-16 11:51:54 +0200 | [diff] [blame] | 4204 | static const char * const pipe_crc_objects[] = { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 4205 | "pipe", |
| 4206 | }; |
| 4207 | |
| 4208 | static int |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 4209 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 4210 | { |
| 4211 | int i; |
| 4212 | |
| 4213 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) |
| 4214 | if (!strcmp(buf, pipe_crc_objects[i])) { |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 4215 | *o = i; |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 4216 | return 0; |
| 4217 | } |
| 4218 | |
| 4219 | return -EINVAL; |
| 4220 | } |
| 4221 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 4222 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4223 | { |
| 4224 | const char name = buf[0]; |
| 4225 | |
| 4226 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) |
| 4227 | return -EINVAL; |
| 4228 | |
| 4229 | *pipe = name - 'A'; |
| 4230 | |
| 4231 | return 0; |
| 4232 | } |
| 4233 | |
| 4234 | static int |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 4235 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4236 | { |
| 4237 | int i; |
| 4238 | |
| 4239 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) |
| 4240 | if (!strcmp(buf, pipe_crc_sources[i])) { |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 4241 | *s = i; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4242 | return 0; |
| 4243 | } |
| 4244 | |
| 4245 | return -EINVAL; |
| 4246 | } |
| 4247 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 4248 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4249 | { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 4250 | #define N_WORDS 3 |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4251 | int n_words; |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 4252 | char *words[N_WORDS]; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4253 | enum pipe pipe; |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 4254 | enum intel_pipe_crc_object object; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4255 | enum intel_pipe_crc_source source; |
| 4256 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 4257 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 4258 | if (n_words != N_WORDS) { |
| 4259 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", |
| 4260 | N_WORDS); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4261 | return -EINVAL; |
| 4262 | } |
| 4263 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 4264 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 4265 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4266 | return -EINVAL; |
| 4267 | } |
| 4268 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 4269 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 4270 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
| 4271 | return -EINVAL; |
| 4272 | } |
| 4273 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 4274 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 4275 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4276 | return -EINVAL; |
| 4277 | } |
| 4278 | |
| 4279 | return pipe_crc_set_source(dev, pipe, source); |
| 4280 | } |
| 4281 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 4282 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
| 4283 | size_t len, loff_t *offp) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4284 | { |
| 4285 | struct seq_file *m = file->private_data; |
| 4286 | struct drm_device *dev = m->private; |
| 4287 | char *tmpbuf; |
| 4288 | int ret; |
| 4289 | |
| 4290 | if (len == 0) |
| 4291 | return 0; |
| 4292 | |
| 4293 | if (len > PAGE_SIZE - 1) { |
| 4294 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", |
| 4295 | PAGE_SIZE); |
| 4296 | return -E2BIG; |
| 4297 | } |
| 4298 | |
| 4299 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); |
| 4300 | if (!tmpbuf) |
| 4301 | return -ENOMEM; |
| 4302 | |
| 4303 | if (copy_from_user(tmpbuf, ubuf, len)) { |
| 4304 | ret = -EFAULT; |
| 4305 | goto out; |
| 4306 | } |
| 4307 | tmpbuf[len] = '\0'; |
| 4308 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 4309 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4310 | |
| 4311 | out: |
| 4312 | kfree(tmpbuf); |
| 4313 | if (ret < 0) |
| 4314 | return ret; |
| 4315 | |
| 4316 | *offp += len; |
| 4317 | return len; |
| 4318 | } |
| 4319 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 4320 | static const struct file_operations i915_display_crc_ctl_fops = { |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4321 | .owner = THIS_MODULE, |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 4322 | .open = display_crc_ctl_open, |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4323 | .read = seq_read, |
| 4324 | .llseek = seq_lseek, |
| 4325 | .release = single_release, |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 4326 | .write = display_crc_ctl_write |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 4327 | }; |
| 4328 | |
Todd Previte | eb3394fa | 2015-04-18 00:04:19 -0700 | [diff] [blame] | 4329 | static ssize_t i915_displayport_test_active_write(struct file *file, |
| 4330 | const char __user *ubuf, |
| 4331 | size_t len, loff_t *offp) |
| 4332 | { |
| 4333 | char *input_buffer; |
| 4334 | int status = 0; |
Todd Previte | eb3394fa | 2015-04-18 00:04:19 -0700 | [diff] [blame] | 4335 | struct drm_device *dev; |
| 4336 | struct drm_connector *connector; |
| 4337 | struct list_head *connector_list; |
| 4338 | struct intel_dp *intel_dp; |
| 4339 | int val = 0; |
| 4340 | |
Sudip Mukherjee | 9aaffa3 | 2015-07-21 17:36:45 +0530 | [diff] [blame] | 4341 | dev = ((struct seq_file *)file->private_data)->private; |
Todd Previte | eb3394fa | 2015-04-18 00:04:19 -0700 | [diff] [blame] | 4342 | |
Todd Previte | eb3394fa | 2015-04-18 00:04:19 -0700 | [diff] [blame] | 4343 | connector_list = &dev->mode_config.connector_list; |
| 4344 | |
| 4345 | if (len == 0) |
| 4346 | return 0; |
| 4347 | |
| 4348 | input_buffer = kmalloc(len + 1, GFP_KERNEL); |
| 4349 | if (!input_buffer) |
| 4350 | return -ENOMEM; |
| 4351 | |
| 4352 | if (copy_from_user(input_buffer, ubuf, len)) { |
| 4353 | status = -EFAULT; |
| 4354 | goto out; |
| 4355 | } |
| 4356 | |
| 4357 | input_buffer[len] = '\0'; |
| 4358 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); |
| 4359 | |
| 4360 | list_for_each_entry(connector, connector_list, head) { |
| 4361 | |
| 4362 | if (connector->connector_type != |
| 4363 | DRM_MODE_CONNECTOR_DisplayPort) |
| 4364 | continue; |
| 4365 | |
Sudip Mukherjee | b8bb08e | 2015-07-21 17:36:46 +0530 | [diff] [blame] | 4366 | if (connector->status == connector_status_connected && |
Todd Previte | eb3394fa | 2015-04-18 00:04:19 -0700 | [diff] [blame] | 4367 | connector->encoder != NULL) { |
| 4368 | intel_dp = enc_to_intel_dp(connector->encoder); |
| 4369 | status = kstrtoint(input_buffer, 10, &val); |
| 4370 | if (status < 0) |
| 4371 | goto out; |
| 4372 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); |
| 4373 | /* To prevent erroneous activation of the compliance |
| 4374 | * testing code, only accept an actual value of 1 here |
| 4375 | */ |
| 4376 | if (val == 1) |
| 4377 | intel_dp->compliance_test_active = 1; |
| 4378 | else |
| 4379 | intel_dp->compliance_test_active = 0; |
| 4380 | } |
| 4381 | } |
| 4382 | out: |
| 4383 | kfree(input_buffer); |
| 4384 | if (status < 0) |
| 4385 | return status; |
| 4386 | |
| 4387 | *offp += len; |
| 4388 | return len; |
| 4389 | } |
| 4390 | |
| 4391 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) |
| 4392 | { |
| 4393 | struct drm_device *dev = m->private; |
| 4394 | struct drm_connector *connector; |
| 4395 | struct list_head *connector_list = &dev->mode_config.connector_list; |
| 4396 | struct intel_dp *intel_dp; |
| 4397 | |
Todd Previte | eb3394fa | 2015-04-18 00:04:19 -0700 | [diff] [blame] | 4398 | list_for_each_entry(connector, connector_list, head) { |
| 4399 | |
| 4400 | if (connector->connector_type != |
| 4401 | DRM_MODE_CONNECTOR_DisplayPort) |
| 4402 | continue; |
| 4403 | |
| 4404 | if (connector->status == connector_status_connected && |
| 4405 | connector->encoder != NULL) { |
| 4406 | intel_dp = enc_to_intel_dp(connector->encoder); |
| 4407 | if (intel_dp->compliance_test_active) |
| 4408 | seq_puts(m, "1"); |
| 4409 | else |
| 4410 | seq_puts(m, "0"); |
| 4411 | } else |
| 4412 | seq_puts(m, "0"); |
| 4413 | } |
| 4414 | |
| 4415 | return 0; |
| 4416 | } |
| 4417 | |
| 4418 | static int i915_displayport_test_active_open(struct inode *inode, |
| 4419 | struct file *file) |
| 4420 | { |
| 4421 | struct drm_device *dev = inode->i_private; |
| 4422 | |
| 4423 | return single_open(file, i915_displayport_test_active_show, dev); |
| 4424 | } |
| 4425 | |
| 4426 | static const struct file_operations i915_displayport_test_active_fops = { |
| 4427 | .owner = THIS_MODULE, |
| 4428 | .open = i915_displayport_test_active_open, |
| 4429 | .read = seq_read, |
| 4430 | .llseek = seq_lseek, |
| 4431 | .release = single_release, |
| 4432 | .write = i915_displayport_test_active_write |
| 4433 | }; |
| 4434 | |
| 4435 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) |
| 4436 | { |
| 4437 | struct drm_device *dev = m->private; |
| 4438 | struct drm_connector *connector; |
| 4439 | struct list_head *connector_list = &dev->mode_config.connector_list; |
| 4440 | struct intel_dp *intel_dp; |
| 4441 | |
Todd Previte | eb3394fa | 2015-04-18 00:04:19 -0700 | [diff] [blame] | 4442 | list_for_each_entry(connector, connector_list, head) { |
| 4443 | |
| 4444 | if (connector->connector_type != |
| 4445 | DRM_MODE_CONNECTOR_DisplayPort) |
| 4446 | continue; |
| 4447 | |
| 4448 | if (connector->status == connector_status_connected && |
| 4449 | connector->encoder != NULL) { |
| 4450 | intel_dp = enc_to_intel_dp(connector->encoder); |
| 4451 | seq_printf(m, "%lx", intel_dp->compliance_test_data); |
| 4452 | } else |
| 4453 | seq_puts(m, "0"); |
| 4454 | } |
| 4455 | |
| 4456 | return 0; |
| 4457 | } |
| 4458 | static int i915_displayport_test_data_open(struct inode *inode, |
| 4459 | struct file *file) |
| 4460 | { |
| 4461 | struct drm_device *dev = inode->i_private; |
| 4462 | |
| 4463 | return single_open(file, i915_displayport_test_data_show, dev); |
| 4464 | } |
| 4465 | |
| 4466 | static const struct file_operations i915_displayport_test_data_fops = { |
| 4467 | .owner = THIS_MODULE, |
| 4468 | .open = i915_displayport_test_data_open, |
| 4469 | .read = seq_read, |
| 4470 | .llseek = seq_lseek, |
| 4471 | .release = single_release |
| 4472 | }; |
| 4473 | |
| 4474 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) |
| 4475 | { |
| 4476 | struct drm_device *dev = m->private; |
| 4477 | struct drm_connector *connector; |
| 4478 | struct list_head *connector_list = &dev->mode_config.connector_list; |
| 4479 | struct intel_dp *intel_dp; |
| 4480 | |
Todd Previte | eb3394fa | 2015-04-18 00:04:19 -0700 | [diff] [blame] | 4481 | list_for_each_entry(connector, connector_list, head) { |
| 4482 | |
| 4483 | if (connector->connector_type != |
| 4484 | DRM_MODE_CONNECTOR_DisplayPort) |
| 4485 | continue; |
| 4486 | |
| 4487 | if (connector->status == connector_status_connected && |
| 4488 | connector->encoder != NULL) { |
| 4489 | intel_dp = enc_to_intel_dp(connector->encoder); |
| 4490 | seq_printf(m, "%02lx", intel_dp->compliance_test_type); |
| 4491 | } else |
| 4492 | seq_puts(m, "0"); |
| 4493 | } |
| 4494 | |
| 4495 | return 0; |
| 4496 | } |
| 4497 | |
| 4498 | static int i915_displayport_test_type_open(struct inode *inode, |
| 4499 | struct file *file) |
| 4500 | { |
| 4501 | struct drm_device *dev = inode->i_private; |
| 4502 | |
| 4503 | return single_open(file, i915_displayport_test_type_show, dev); |
| 4504 | } |
| 4505 | |
| 4506 | static const struct file_operations i915_displayport_test_type_fops = { |
| 4507 | .owner = THIS_MODULE, |
| 4508 | .open = i915_displayport_test_type_open, |
| 4509 | .read = seq_read, |
| 4510 | .llseek = seq_lseek, |
| 4511 | .release = single_release |
| 4512 | }; |
| 4513 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4514 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4515 | { |
| 4516 | struct drm_device *dev = m->private; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4517 | int level; |
Ville Syrjälä | de38b95 | 2015-06-24 22:00:09 +0300 | [diff] [blame] | 4518 | int num_levels; |
| 4519 | |
| 4520 | if (IS_CHERRYVIEW(dev)) |
| 4521 | num_levels = 3; |
| 4522 | else if (IS_VALLEYVIEW(dev)) |
| 4523 | num_levels = 1; |
| 4524 | else |
| 4525 | num_levels = ilk_wm_max_level(dev) + 1; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4526 | |
| 4527 | drm_modeset_lock_all(dev); |
| 4528 | |
| 4529 | for (level = 0; level < num_levels; level++) { |
| 4530 | unsigned int latency = wm[level]; |
| 4531 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4532 | /* |
| 4533 | * - WM1+ latency values in 0.5us units |
Ville Syrjälä | de38b95 | 2015-06-24 22:00:09 +0300 | [diff] [blame] | 4534 | * - latencies are in us on gen9/vlv/chv |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4535 | */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 4536 | if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) || |
| 4537 | IS_CHERRYVIEW(dev)) |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4538 | latency *= 10; |
| 4539 | else if (level > 0) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4540 | latency *= 5; |
| 4541 | |
| 4542 | seq_printf(m, "WM%d %u (%u.%u usec)\n", |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4543 | level, wm[level], latency / 10, latency % 10); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4544 | } |
| 4545 | |
| 4546 | drm_modeset_unlock_all(dev); |
| 4547 | } |
| 4548 | |
| 4549 | static int pri_wm_latency_show(struct seq_file *m, void *data) |
| 4550 | { |
| 4551 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4552 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4553 | const uint16_t *latencies; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4554 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4555 | if (INTEL_INFO(dev)->gen >= 9) |
| 4556 | latencies = dev_priv->wm.skl_latency; |
| 4557 | else |
| 4558 | latencies = to_i915(dev)->wm.pri_latency; |
| 4559 | |
| 4560 | wm_latency_show(m, latencies); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4561 | |
| 4562 | return 0; |
| 4563 | } |
| 4564 | |
| 4565 | static int spr_wm_latency_show(struct seq_file *m, void *data) |
| 4566 | { |
| 4567 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4568 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4569 | const uint16_t *latencies; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4570 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4571 | if (INTEL_INFO(dev)->gen >= 9) |
| 4572 | latencies = dev_priv->wm.skl_latency; |
| 4573 | else |
| 4574 | latencies = to_i915(dev)->wm.spr_latency; |
| 4575 | |
| 4576 | wm_latency_show(m, latencies); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4577 | |
| 4578 | return 0; |
| 4579 | } |
| 4580 | |
| 4581 | static int cur_wm_latency_show(struct seq_file *m, void *data) |
| 4582 | { |
| 4583 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4584 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4585 | const uint16_t *latencies; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4586 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4587 | if (INTEL_INFO(dev)->gen >= 9) |
| 4588 | latencies = dev_priv->wm.skl_latency; |
| 4589 | else |
| 4590 | latencies = to_i915(dev)->wm.cur_latency; |
| 4591 | |
| 4592 | wm_latency_show(m, latencies); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4593 | |
| 4594 | return 0; |
| 4595 | } |
| 4596 | |
| 4597 | static int pri_wm_latency_open(struct inode *inode, struct file *file) |
| 4598 | { |
| 4599 | struct drm_device *dev = inode->i_private; |
| 4600 | |
Ville Syrjälä | de38b95 | 2015-06-24 22:00:09 +0300 | [diff] [blame] | 4601 | if (INTEL_INFO(dev)->gen < 5) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4602 | return -ENODEV; |
| 4603 | |
| 4604 | return single_open(file, pri_wm_latency_show, dev); |
| 4605 | } |
| 4606 | |
| 4607 | static int spr_wm_latency_open(struct inode *inode, struct file *file) |
| 4608 | { |
| 4609 | struct drm_device *dev = inode->i_private; |
| 4610 | |
Sonika Jindal | 9ad0257 | 2014-07-21 15:23:39 +0530 | [diff] [blame] | 4611 | if (HAS_GMCH_DISPLAY(dev)) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4612 | return -ENODEV; |
| 4613 | |
| 4614 | return single_open(file, spr_wm_latency_show, dev); |
| 4615 | } |
| 4616 | |
| 4617 | static int cur_wm_latency_open(struct inode *inode, struct file *file) |
| 4618 | { |
| 4619 | struct drm_device *dev = inode->i_private; |
| 4620 | |
Sonika Jindal | 9ad0257 | 2014-07-21 15:23:39 +0530 | [diff] [blame] | 4621 | if (HAS_GMCH_DISPLAY(dev)) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4622 | return -ENODEV; |
| 4623 | |
| 4624 | return single_open(file, cur_wm_latency_show, dev); |
| 4625 | } |
| 4626 | |
| 4627 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4628 | size_t len, loff_t *offp, uint16_t wm[8]) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4629 | { |
| 4630 | struct seq_file *m = file->private_data; |
| 4631 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4632 | uint16_t new[8] = { 0 }; |
Ville Syrjälä | de38b95 | 2015-06-24 22:00:09 +0300 | [diff] [blame] | 4633 | int num_levels; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4634 | int level; |
| 4635 | int ret; |
| 4636 | char tmp[32]; |
| 4637 | |
Ville Syrjälä | de38b95 | 2015-06-24 22:00:09 +0300 | [diff] [blame] | 4638 | if (IS_CHERRYVIEW(dev)) |
| 4639 | num_levels = 3; |
| 4640 | else if (IS_VALLEYVIEW(dev)) |
| 4641 | num_levels = 1; |
| 4642 | else |
| 4643 | num_levels = ilk_wm_max_level(dev) + 1; |
| 4644 | |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4645 | if (len >= sizeof(tmp)) |
| 4646 | return -EINVAL; |
| 4647 | |
| 4648 | if (copy_from_user(tmp, ubuf, len)) |
| 4649 | return -EFAULT; |
| 4650 | |
| 4651 | tmp[len] = '\0'; |
| 4652 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4653 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
| 4654 | &new[0], &new[1], &new[2], &new[3], |
| 4655 | &new[4], &new[5], &new[6], &new[7]); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4656 | if (ret != num_levels) |
| 4657 | return -EINVAL; |
| 4658 | |
| 4659 | drm_modeset_lock_all(dev); |
| 4660 | |
| 4661 | for (level = 0; level < num_levels; level++) |
| 4662 | wm[level] = new[level]; |
| 4663 | |
| 4664 | drm_modeset_unlock_all(dev); |
| 4665 | |
| 4666 | return len; |
| 4667 | } |
| 4668 | |
| 4669 | |
| 4670 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, |
| 4671 | size_t len, loff_t *offp) |
| 4672 | { |
| 4673 | struct seq_file *m = file->private_data; |
| 4674 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4675 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4676 | uint16_t *latencies; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4677 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4678 | if (INTEL_INFO(dev)->gen >= 9) |
| 4679 | latencies = dev_priv->wm.skl_latency; |
| 4680 | else |
| 4681 | latencies = to_i915(dev)->wm.pri_latency; |
| 4682 | |
| 4683 | return wm_latency_write(file, ubuf, len, offp, latencies); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4684 | } |
| 4685 | |
| 4686 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, |
| 4687 | size_t len, loff_t *offp) |
| 4688 | { |
| 4689 | struct seq_file *m = file->private_data; |
| 4690 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4691 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4692 | uint16_t *latencies; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4693 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4694 | if (INTEL_INFO(dev)->gen >= 9) |
| 4695 | latencies = dev_priv->wm.skl_latency; |
| 4696 | else |
| 4697 | latencies = to_i915(dev)->wm.spr_latency; |
| 4698 | |
| 4699 | return wm_latency_write(file, ubuf, len, offp, latencies); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4700 | } |
| 4701 | |
| 4702 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, |
| 4703 | size_t len, loff_t *offp) |
| 4704 | { |
| 4705 | struct seq_file *m = file->private_data; |
| 4706 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4707 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4708 | uint16_t *latencies; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4709 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 4710 | if (INTEL_INFO(dev)->gen >= 9) |
| 4711 | latencies = dev_priv->wm.skl_latency; |
| 4712 | else |
| 4713 | latencies = to_i915(dev)->wm.cur_latency; |
| 4714 | |
| 4715 | return wm_latency_write(file, ubuf, len, offp, latencies); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4716 | } |
| 4717 | |
| 4718 | static const struct file_operations i915_pri_wm_latency_fops = { |
| 4719 | .owner = THIS_MODULE, |
| 4720 | .open = pri_wm_latency_open, |
| 4721 | .read = seq_read, |
| 4722 | .llseek = seq_lseek, |
| 4723 | .release = single_release, |
| 4724 | .write = pri_wm_latency_write |
| 4725 | }; |
| 4726 | |
| 4727 | static const struct file_operations i915_spr_wm_latency_fops = { |
| 4728 | .owner = THIS_MODULE, |
| 4729 | .open = spr_wm_latency_open, |
| 4730 | .read = seq_read, |
| 4731 | .llseek = seq_lseek, |
| 4732 | .release = single_release, |
| 4733 | .write = spr_wm_latency_write |
| 4734 | }; |
| 4735 | |
| 4736 | static const struct file_operations i915_cur_wm_latency_fops = { |
| 4737 | .owner = THIS_MODULE, |
| 4738 | .open = cur_wm_latency_open, |
| 4739 | .read = seq_read, |
| 4740 | .llseek = seq_lseek, |
| 4741 | .release = single_release, |
| 4742 | .write = cur_wm_latency_write |
| 4743 | }; |
| 4744 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4745 | static int |
| 4746 | i915_wedged_get(void *data, u64 *val) |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 4747 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4748 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 4749 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 4750 | |
Chris Wilson | d98c52c | 2016-04-13 17:35:05 +0100 | [diff] [blame] | 4751 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 4752 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4753 | return 0; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 4754 | } |
| 4755 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4756 | static int |
| 4757 | i915_wedged_set(void *data, u64 val) |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 4758 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4759 | struct drm_device *dev = data; |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 4760 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4761 | |
Mika Kuoppala | b8d24a0 | 2015-01-28 17:03:14 +0200 | [diff] [blame] | 4762 | /* |
| 4763 | * There is no safeguard against this debugfs entry colliding |
| 4764 | * with the hangcheck calling same i915_handle_error() in |
| 4765 | * parallel, causing an explosion. For now we assume that the |
| 4766 | * test harness is responsible enough not to inject gpu hangs |
| 4767 | * while it is writing to 'i915_wedged' |
| 4768 | */ |
| 4769 | |
Chris Wilson | d98c52c | 2016-04-13 17:35:05 +0100 | [diff] [blame] | 4770 | if (i915_reset_in_progress(&dev_priv->gpu_error)) |
Mika Kuoppala | b8d24a0 | 2015-01-28 17:03:14 +0200 | [diff] [blame] | 4771 | return -EAGAIN; |
| 4772 | |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 4773 | intel_runtime_pm_get(dev_priv); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 4774 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 4775 | i915_handle_error(dev_priv, val, |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 4776 | "Manually setting wedged to %llu", val); |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 4777 | |
| 4778 | intel_runtime_pm_put(dev_priv); |
| 4779 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4780 | return 0; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 4781 | } |
| 4782 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4783 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
| 4784 | i915_wedged_get, i915_wedged_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 4785 | "%llu\n"); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 4786 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4787 | static int |
| 4788 | i915_ring_stop_get(void *data, u64 *val) |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 4789 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4790 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 4791 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 4792 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4793 | *val = dev_priv->gpu_error.stop_rings; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 4794 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4795 | return 0; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 4796 | } |
| 4797 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4798 | static int |
| 4799 | i915_ring_stop_set(void *data, u64 val) |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 4800 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4801 | struct drm_device *dev = data; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 4802 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4803 | int ret; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 4804 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4805 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 4806 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 4807 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 4808 | if (ret) |
| 4809 | return ret; |
| 4810 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 4811 | dev_priv->gpu_error.stop_rings = val; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 4812 | mutex_unlock(&dev->struct_mutex); |
| 4813 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4814 | return 0; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 4815 | } |
| 4816 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4817 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
| 4818 | i915_ring_stop_get, i915_ring_stop_set, |
| 4819 | "0x%08llx\n"); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 4820 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 4821 | static int |
| 4822 | i915_ring_missed_irq_get(void *data, u64 *val) |
| 4823 | { |
| 4824 | struct drm_device *dev = data; |
| 4825 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4826 | |
| 4827 | *val = dev_priv->gpu_error.missed_irq_rings; |
| 4828 | return 0; |
| 4829 | } |
| 4830 | |
| 4831 | static int |
| 4832 | i915_ring_missed_irq_set(void *data, u64 val) |
| 4833 | { |
| 4834 | struct drm_device *dev = data; |
| 4835 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4836 | int ret; |
| 4837 | |
| 4838 | /* Lock against concurrent debugfs callers */ |
| 4839 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 4840 | if (ret) |
| 4841 | return ret; |
| 4842 | dev_priv->gpu_error.missed_irq_rings = val; |
| 4843 | mutex_unlock(&dev->struct_mutex); |
| 4844 | |
| 4845 | return 0; |
| 4846 | } |
| 4847 | |
| 4848 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, |
| 4849 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, |
| 4850 | "0x%08llx\n"); |
| 4851 | |
| 4852 | static int |
| 4853 | i915_ring_test_irq_get(void *data, u64 *val) |
| 4854 | { |
| 4855 | struct drm_device *dev = data; |
| 4856 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4857 | |
| 4858 | *val = dev_priv->gpu_error.test_irq_rings; |
| 4859 | |
| 4860 | return 0; |
| 4861 | } |
| 4862 | |
| 4863 | static int |
| 4864 | i915_ring_test_irq_set(void *data, u64 val) |
| 4865 | { |
| 4866 | struct drm_device *dev = data; |
| 4867 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4868 | int ret; |
| 4869 | |
| 4870 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
| 4871 | |
| 4872 | /* Lock against concurrent debugfs callers */ |
| 4873 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 4874 | if (ret) |
| 4875 | return ret; |
| 4876 | |
| 4877 | dev_priv->gpu_error.test_irq_rings = val; |
| 4878 | mutex_unlock(&dev->struct_mutex); |
| 4879 | |
| 4880 | return 0; |
| 4881 | } |
| 4882 | |
| 4883 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, |
| 4884 | i915_ring_test_irq_get, i915_ring_test_irq_set, |
| 4885 | "0x%08llx\n"); |
| 4886 | |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4887 | #define DROP_UNBOUND 0x1 |
| 4888 | #define DROP_BOUND 0x2 |
| 4889 | #define DROP_RETIRE 0x4 |
| 4890 | #define DROP_ACTIVE 0x8 |
| 4891 | #define DROP_ALL (DROP_UNBOUND | \ |
| 4892 | DROP_BOUND | \ |
| 4893 | DROP_RETIRE | \ |
| 4894 | DROP_ACTIVE) |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4895 | static int |
| 4896 | i915_drop_caches_get(void *data, u64 *val) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4897 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4898 | *val = DROP_ALL; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4899 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4900 | return 0; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4901 | } |
| 4902 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4903 | static int |
| 4904 | i915_drop_caches_set(void *data, u64 val) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4905 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4906 | struct drm_device *dev = data; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4907 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4908 | int ret; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4909 | |
Ben Widawsky | 2f9fe5f | 2013-11-25 09:54:37 -0800 | [diff] [blame] | 4910 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4911 | |
| 4912 | /* No need to check and wait for gpu resets, only libdrm auto-restarts |
| 4913 | * on ioctls on -EAGAIN. */ |
| 4914 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 4915 | if (ret) |
| 4916 | return ret; |
| 4917 | |
| 4918 | if (val & DROP_ACTIVE) { |
| 4919 | ret = i915_gpu_idle(dev); |
| 4920 | if (ret) |
| 4921 | goto unlock; |
| 4922 | } |
| 4923 | |
| 4924 | if (val & (DROP_RETIRE | DROP_ACTIVE)) |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 4925 | i915_gem_retire_requests(dev_priv); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4926 | |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 4927 | if (val & DROP_BOUND) |
| 4928 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); |
Chris Wilson | 4ad72b7 | 2014-09-03 19:23:37 +0100 | [diff] [blame] | 4929 | |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 4930 | if (val & DROP_UNBOUND) |
| 4931 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4932 | |
| 4933 | unlock: |
| 4934 | mutex_unlock(&dev->struct_mutex); |
| 4935 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4936 | return ret; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4937 | } |
| 4938 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4939 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
| 4940 | i915_drop_caches_get, i915_drop_caches_set, |
| 4941 | "0x%08llx\n"); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4942 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4943 | static int |
| 4944 | i915_max_freq_get(void *data, u64 *val) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4945 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4946 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 4947 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4948 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4949 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 4950 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4951 | return -ENODEV; |
| 4952 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 4953 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 4954 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4955 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4956 | if (ret) |
| 4957 | return ret; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4958 | |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 4959 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4960 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4961 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4962 | return 0; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4963 | } |
| 4964 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4965 | static int |
| 4966 | i915_max_freq_set(void *data, u64 val) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4967 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4968 | struct drm_device *dev = data; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4969 | struct drm_i915_private *dev_priv = dev->dev_private; |
Akash Goel | bc4d91f | 2015-02-26 16:09:47 +0530 | [diff] [blame] | 4970 | u32 hw_max, hw_min; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4971 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4972 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 4973 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4974 | return -ENODEV; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4975 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 4976 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 4977 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4978 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4979 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4980 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4981 | if (ret) |
| 4982 | return ret; |
| 4983 | |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4984 | /* |
| 4985 | * Turbo will still be enabled, but won't go above the set value. |
| 4986 | */ |
Akash Goel | bc4d91f | 2015-02-26 16:09:47 +0530 | [diff] [blame] | 4987 | val = intel_freq_opcode(dev_priv, val); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4988 | |
Akash Goel | bc4d91f | 2015-02-26 16:09:47 +0530 | [diff] [blame] | 4989 | hw_max = dev_priv->rps.max_freq; |
| 4990 | hw_min = dev_priv->rps.min_freq; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4991 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4992 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4993 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 4994 | return -EINVAL; |
| 4995 | } |
| 4996 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4997 | dev_priv->rps.max_freq_softlimit = val; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4998 | |
Chris Wilson | dc97997 | 2016-05-10 14:10:04 +0100 | [diff] [blame] | 4999 | intel_set_rps(dev_priv, val); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 5000 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 5001 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 5002 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5003 | return 0; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 5004 | } |
| 5005 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5006 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
| 5007 | i915_max_freq_get, i915_max_freq_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 5008 | "%llu\n"); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 5009 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5010 | static int |
| 5011 | i915_min_freq_get(void *data, u64 *val) |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 5012 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5013 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 5014 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5015 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 5016 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 5017 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 5018 | return -ENODEV; |
| 5019 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 5020 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 5021 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 5022 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 5023 | if (ret) |
| 5024 | return ret; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 5025 | |
Ville Syrjälä | 7c59a9c1 | 2015-01-23 21:04:26 +0200 | [diff] [blame] | 5026 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 5027 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 5028 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5029 | return 0; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 5030 | } |
| 5031 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5032 | static int |
| 5033 | i915_min_freq_set(void *data, u64 val) |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 5034 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5035 | struct drm_device *dev = data; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 5036 | struct drm_i915_private *dev_priv = dev->dev_private; |
Akash Goel | bc4d91f | 2015-02-26 16:09:47 +0530 | [diff] [blame] | 5037 | u32 hw_max, hw_min; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5038 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 5039 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 5040 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 5041 | return -ENODEV; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 5042 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 5043 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 5044 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5045 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 5046 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 5047 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 5048 | if (ret) |
| 5049 | return ret; |
| 5050 | |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 5051 | /* |
| 5052 | * Turbo will still be enabled, but won't go below the set value. |
| 5053 | */ |
Akash Goel | bc4d91f | 2015-02-26 16:09:47 +0530 | [diff] [blame] | 5054 | val = intel_freq_opcode(dev_priv, val); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 5055 | |
Akash Goel | bc4d91f | 2015-02-26 16:09:47 +0530 | [diff] [blame] | 5056 | hw_max = dev_priv->rps.max_freq; |
| 5057 | hw_min = dev_priv->rps.min_freq; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 5058 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 5059 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 5060 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 5061 | return -EINVAL; |
| 5062 | } |
| 5063 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 5064 | dev_priv->rps.min_freq_softlimit = val; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 5065 | |
Chris Wilson | dc97997 | 2016-05-10 14:10:04 +0100 | [diff] [blame] | 5066 | intel_set_rps(dev_priv, val); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 5067 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 5068 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 5069 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5070 | return 0; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 5071 | } |
| 5072 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5073 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
| 5074 | i915_min_freq_get, i915_min_freq_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 5075 | "%llu\n"); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 5076 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5077 | static int |
| 5078 | i915_cache_sharing_get(void *data, u64 *val) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 5079 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5080 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 5081 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 5082 | u32 snpcr; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5083 | int ret; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 5084 | |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 5085 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 5086 | return -ENODEV; |
| 5087 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 5088 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 5089 | if (ret) |
| 5090 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 5091 | intel_runtime_pm_get(dev_priv); |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 5092 | |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 5093 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 5094 | |
| 5095 | intel_runtime_pm_put(dev_priv); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 5096 | mutex_unlock(&dev_priv->dev->struct_mutex); |
| 5097 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5098 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 5099 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5100 | return 0; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 5101 | } |
| 5102 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5103 | static int |
| 5104 | i915_cache_sharing_set(void *data, u64 val) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 5105 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5106 | struct drm_device *dev = data; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 5107 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 5108 | u32 snpcr; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 5109 | |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 5110 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 5111 | return -ENODEV; |
| 5112 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5113 | if (val > 3) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 5114 | return -EINVAL; |
| 5115 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 5116 | intel_runtime_pm_get(dev_priv); |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5117 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 5118 | |
| 5119 | /* Update the cache sharing policy here as well */ |
| 5120 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
| 5121 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
| 5122 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); |
| 5123 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
| 5124 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 5125 | intel_runtime_pm_put(dev_priv); |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5126 | return 0; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 5127 | } |
| 5128 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 5129 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
| 5130 | i915_cache_sharing_get, i915_cache_sharing_set, |
| 5131 | "%llu\n"); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 5132 | |
Jeff McGee | 5d39525 | 2015-04-03 18:13:17 -0700 | [diff] [blame] | 5133 | struct sseu_dev_status { |
| 5134 | unsigned int slice_total; |
| 5135 | unsigned int subslice_total; |
| 5136 | unsigned int subslice_per_slice; |
| 5137 | unsigned int eu_total; |
| 5138 | unsigned int eu_per_subslice; |
| 5139 | }; |
| 5140 | |
| 5141 | static void cherryview_sseu_device_status(struct drm_device *dev, |
| 5142 | struct sseu_dev_status *stat) |
| 5143 | { |
| 5144 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 0a0b457 | 2015-08-21 20:45:27 +0300 | [diff] [blame] | 5145 | int ss_max = 2; |
Jeff McGee | 5d39525 | 2015-04-03 18:13:17 -0700 | [diff] [blame] | 5146 | int ss; |
| 5147 | u32 sig1[ss_max], sig2[ss_max]; |
| 5148 | |
| 5149 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); |
| 5150 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); |
| 5151 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); |
| 5152 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); |
| 5153 | |
| 5154 | for (ss = 0; ss < ss_max; ss++) { |
| 5155 | unsigned int eu_cnt; |
| 5156 | |
| 5157 | if (sig1[ss] & CHV_SS_PG_ENABLE) |
| 5158 | /* skip disabled subslice */ |
| 5159 | continue; |
| 5160 | |
| 5161 | stat->slice_total = 1; |
| 5162 | stat->subslice_per_slice++; |
| 5163 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + |
| 5164 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + |
| 5165 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + |
| 5166 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); |
| 5167 | stat->eu_total += eu_cnt; |
| 5168 | stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt); |
| 5169 | } |
| 5170 | stat->subslice_total = stat->subslice_per_slice; |
| 5171 | } |
| 5172 | |
| 5173 | static void gen9_sseu_device_status(struct drm_device *dev, |
| 5174 | struct sseu_dev_status *stat) |
| 5175 | { |
| 5176 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jeff McGee | 1c046bc | 2015-04-03 18:13:18 -0700 | [diff] [blame] | 5177 | int s_max = 3, ss_max = 4; |
Jeff McGee | 5d39525 | 2015-04-03 18:13:17 -0700 | [diff] [blame] | 5178 | int s, ss; |
| 5179 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; |
| 5180 | |
Jeff McGee | 1c046bc | 2015-04-03 18:13:18 -0700 | [diff] [blame] | 5181 | /* BXT has a single slice and at most 3 subslices. */ |
| 5182 | if (IS_BROXTON(dev)) { |
| 5183 | s_max = 1; |
| 5184 | ss_max = 3; |
| 5185 | } |
| 5186 | |
| 5187 | for (s = 0; s < s_max; s++) { |
| 5188 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); |
| 5189 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); |
| 5190 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); |
| 5191 | } |
| 5192 | |
Jeff McGee | 5d39525 | 2015-04-03 18:13:17 -0700 | [diff] [blame] | 5193 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
| 5194 | GEN9_PGCTL_SSA_EU19_ACK | |
| 5195 | GEN9_PGCTL_SSA_EU210_ACK | |
| 5196 | GEN9_PGCTL_SSA_EU311_ACK; |
| 5197 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | |
| 5198 | GEN9_PGCTL_SSB_EU19_ACK | |
| 5199 | GEN9_PGCTL_SSB_EU210_ACK | |
| 5200 | GEN9_PGCTL_SSB_EU311_ACK; |
| 5201 | |
| 5202 | for (s = 0; s < s_max; s++) { |
Jeff McGee | 1c046bc | 2015-04-03 18:13:18 -0700 | [diff] [blame] | 5203 | unsigned int ss_cnt = 0; |
| 5204 | |
Jeff McGee | 5d39525 | 2015-04-03 18:13:17 -0700 | [diff] [blame] | 5205 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) |
| 5206 | /* skip disabled slice */ |
| 5207 | continue; |
| 5208 | |
| 5209 | stat->slice_total++; |
Jeff McGee | 1c046bc | 2015-04-03 18:13:18 -0700 | [diff] [blame] | 5210 | |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 5211 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
Jeff McGee | 1c046bc | 2015-04-03 18:13:18 -0700 | [diff] [blame] | 5212 | ss_cnt = INTEL_INFO(dev)->subslice_per_slice; |
| 5213 | |
Jeff McGee | 5d39525 | 2015-04-03 18:13:17 -0700 | [diff] [blame] | 5214 | for (ss = 0; ss < ss_max; ss++) { |
| 5215 | unsigned int eu_cnt; |
| 5216 | |
Jeff McGee | 1c046bc | 2015-04-03 18:13:18 -0700 | [diff] [blame] | 5217 | if (IS_BROXTON(dev) && |
| 5218 | !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) |
| 5219 | /* skip disabled subslice */ |
| 5220 | continue; |
| 5221 | |
| 5222 | if (IS_BROXTON(dev)) |
| 5223 | ss_cnt++; |
| 5224 | |
Jeff McGee | 5d39525 | 2015-04-03 18:13:17 -0700 | [diff] [blame] | 5225 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
| 5226 | eu_mask[ss%2]); |
| 5227 | stat->eu_total += eu_cnt; |
| 5228 | stat->eu_per_subslice = max(stat->eu_per_subslice, |
| 5229 | eu_cnt); |
| 5230 | } |
Jeff McGee | 1c046bc | 2015-04-03 18:13:18 -0700 | [diff] [blame] | 5231 | |
| 5232 | stat->subslice_total += ss_cnt; |
| 5233 | stat->subslice_per_slice = max(stat->subslice_per_slice, |
| 5234 | ss_cnt); |
Jeff McGee | 5d39525 | 2015-04-03 18:13:17 -0700 | [diff] [blame] | 5235 | } |
| 5236 | } |
| 5237 | |
Łukasz Daniluk | 91bedd3 | 2015-09-25 11:54:58 +0200 | [diff] [blame] | 5238 | static void broadwell_sseu_device_status(struct drm_device *dev, |
| 5239 | struct sseu_dev_status *stat) |
| 5240 | { |
| 5241 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5242 | int s; |
| 5243 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); |
| 5244 | |
| 5245 | stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK); |
| 5246 | |
| 5247 | if (stat->slice_total) { |
| 5248 | stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice; |
| 5249 | stat->subslice_total = stat->slice_total * |
| 5250 | stat->subslice_per_slice; |
| 5251 | stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice; |
| 5252 | stat->eu_total = stat->eu_per_subslice * stat->subslice_total; |
| 5253 | |
| 5254 | /* subtract fused off EU(s) from enabled slice(s) */ |
| 5255 | for (s = 0; s < stat->slice_total; s++) { |
| 5256 | u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s]; |
| 5257 | |
| 5258 | stat->eu_total -= hweight8(subslice_7eu); |
| 5259 | } |
| 5260 | } |
| 5261 | } |
| 5262 | |
Jeff McGee | 3873218 | 2015-02-13 10:27:54 -0600 | [diff] [blame] | 5263 | static int i915_sseu_status(struct seq_file *m, void *unused) |
| 5264 | { |
| 5265 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 5266 | struct drm_device *dev = node->minor->dev; |
Jeff McGee | 5d39525 | 2015-04-03 18:13:17 -0700 | [diff] [blame] | 5267 | struct sseu_dev_status stat; |
Jeff McGee | 3873218 | 2015-02-13 10:27:54 -0600 | [diff] [blame] | 5268 | |
Łukasz Daniluk | 91bedd3 | 2015-09-25 11:54:58 +0200 | [diff] [blame] | 5269 | if (INTEL_INFO(dev)->gen < 8) |
Jeff McGee | 3873218 | 2015-02-13 10:27:54 -0600 | [diff] [blame] | 5270 | return -ENODEV; |
| 5271 | |
| 5272 | seq_puts(m, "SSEU Device Info\n"); |
| 5273 | seq_printf(m, " Available Slice Total: %u\n", |
| 5274 | INTEL_INFO(dev)->slice_total); |
| 5275 | seq_printf(m, " Available Subslice Total: %u\n", |
| 5276 | INTEL_INFO(dev)->subslice_total); |
| 5277 | seq_printf(m, " Available Subslice Per Slice: %u\n", |
| 5278 | INTEL_INFO(dev)->subslice_per_slice); |
| 5279 | seq_printf(m, " Available EU Total: %u\n", |
| 5280 | INTEL_INFO(dev)->eu_total); |
| 5281 | seq_printf(m, " Available EU Per Subslice: %u\n", |
| 5282 | INTEL_INFO(dev)->eu_per_subslice); |
| 5283 | seq_printf(m, " Has Slice Power Gating: %s\n", |
| 5284 | yesno(INTEL_INFO(dev)->has_slice_pg)); |
| 5285 | seq_printf(m, " Has Subslice Power Gating: %s\n", |
| 5286 | yesno(INTEL_INFO(dev)->has_subslice_pg)); |
| 5287 | seq_printf(m, " Has EU Power Gating: %s\n", |
| 5288 | yesno(INTEL_INFO(dev)->has_eu_pg)); |
| 5289 | |
Jeff McGee | 7f992ab | 2015-02-13 10:27:55 -0600 | [diff] [blame] | 5290 | seq_puts(m, "SSEU Device Status\n"); |
Jeff McGee | 5d39525 | 2015-04-03 18:13:17 -0700 | [diff] [blame] | 5291 | memset(&stat, 0, sizeof(stat)); |
Jeff McGee | 5575f03 | 2015-02-27 10:22:32 -0800 | [diff] [blame] | 5292 | if (IS_CHERRYVIEW(dev)) { |
Jeff McGee | 5d39525 | 2015-04-03 18:13:17 -0700 | [diff] [blame] | 5293 | cherryview_sseu_device_status(dev, &stat); |
Łukasz Daniluk | 91bedd3 | 2015-09-25 11:54:58 +0200 | [diff] [blame] | 5294 | } else if (IS_BROADWELL(dev)) { |
| 5295 | broadwell_sseu_device_status(dev, &stat); |
Jeff McGee | 1c046bc | 2015-04-03 18:13:18 -0700 | [diff] [blame] | 5296 | } else if (INTEL_INFO(dev)->gen >= 9) { |
Jeff McGee | 5d39525 | 2015-04-03 18:13:17 -0700 | [diff] [blame] | 5297 | gen9_sseu_device_status(dev, &stat); |
Jeff McGee | 7f992ab | 2015-02-13 10:27:55 -0600 | [diff] [blame] | 5298 | } |
Jeff McGee | 5d39525 | 2015-04-03 18:13:17 -0700 | [diff] [blame] | 5299 | seq_printf(m, " Enabled Slice Total: %u\n", |
| 5300 | stat.slice_total); |
| 5301 | seq_printf(m, " Enabled Subslice Total: %u\n", |
| 5302 | stat.subslice_total); |
| 5303 | seq_printf(m, " Enabled Subslice Per Slice: %u\n", |
| 5304 | stat.subslice_per_slice); |
| 5305 | seq_printf(m, " Enabled EU Total: %u\n", |
| 5306 | stat.eu_total); |
| 5307 | seq_printf(m, " Enabled EU Per Subslice: %u\n", |
| 5308 | stat.eu_per_subslice); |
Jeff McGee | 7f992ab | 2015-02-13 10:27:55 -0600 | [diff] [blame] | 5309 | |
Jeff McGee | 3873218 | 2015-02-13 10:27:54 -0600 | [diff] [blame] | 5310 | return 0; |
| 5311 | } |
| 5312 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 5313 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
| 5314 | { |
| 5315 | struct drm_device *dev = inode->i_private; |
| 5316 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 5317 | |
Daniel Vetter | 075edca | 2012-01-24 09:44:28 +0100 | [diff] [blame] | 5318 | if (INTEL_INFO(dev)->gen < 6) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 5319 | return 0; |
| 5320 | |
Chris Wilson | 6daccb0 | 2015-01-16 11:34:35 +0200 | [diff] [blame] | 5321 | intel_runtime_pm_get(dev_priv); |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 5322 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 5323 | |
| 5324 | return 0; |
| 5325 | } |
| 5326 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 5327 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 5328 | { |
| 5329 | struct drm_device *dev = inode->i_private; |
| 5330 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5331 | |
Daniel Vetter | 075edca | 2012-01-24 09:44:28 +0100 | [diff] [blame] | 5332 | if (INTEL_INFO(dev)->gen < 6) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 5333 | return 0; |
| 5334 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 5335 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Chris Wilson | 6daccb0 | 2015-01-16 11:34:35 +0200 | [diff] [blame] | 5336 | intel_runtime_pm_put(dev_priv); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 5337 | |
| 5338 | return 0; |
| 5339 | } |
| 5340 | |
| 5341 | static const struct file_operations i915_forcewake_fops = { |
| 5342 | .owner = THIS_MODULE, |
| 5343 | .open = i915_forcewake_open, |
| 5344 | .release = i915_forcewake_release, |
| 5345 | }; |
| 5346 | |
| 5347 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) |
| 5348 | { |
| 5349 | struct drm_device *dev = minor->dev; |
| 5350 | struct dentry *ent; |
| 5351 | |
| 5352 | ent = debugfs_create_file("i915_forcewake_user", |
Ben Widawsky | 8eb5729 | 2011-05-11 15:10:58 -0700 | [diff] [blame] | 5353 | S_IRUSR, |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 5354 | root, dev, |
| 5355 | &i915_forcewake_fops); |
Wei Yongjun | f3c5fe9 | 2013-12-16 14:13:25 +0800 | [diff] [blame] | 5356 | if (!ent) |
| 5357 | return -ENOMEM; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 5358 | |
Ben Widawsky | 8eb5729 | 2011-05-11 15:10:58 -0700 | [diff] [blame] | 5359 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 5360 | } |
| 5361 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 5362 | static int i915_debugfs_create(struct dentry *root, |
| 5363 | struct drm_minor *minor, |
| 5364 | const char *name, |
| 5365 | const struct file_operations *fops) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 5366 | { |
| 5367 | struct drm_device *dev = minor->dev; |
| 5368 | struct dentry *ent; |
| 5369 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 5370 | ent = debugfs_create_file(name, |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 5371 | S_IRUGO | S_IWUSR, |
| 5372 | root, dev, |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 5373 | fops); |
Wei Yongjun | f3c5fe9 | 2013-12-16 14:13:25 +0800 | [diff] [blame] | 5374 | if (!ent) |
| 5375 | return -ENOMEM; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 5376 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 5377 | return drm_add_fake_info_node(minor, ent, fops); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 5378 | } |
| 5379 | |
Lespiau, Damien | 06c5bf8 | 2013-10-17 19:09:56 +0100 | [diff] [blame] | 5380 | static const struct drm_info_list i915_debugfs_list[] = { |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 5381 | {"i915_capabilities", i915_capabilities, 0}, |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 5382 | {"i915_gem_objects", i915_gem_object_info, 0}, |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 5383 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 5384 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 5385 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 5386 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 5387 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 5388 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 5389 | {"i915_gem_request", i915_gem_request_info, 0}, |
| 5390 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 5391 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 5392 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 5393 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
| 5394 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, |
| 5395 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, |
Xiang, Haihao | 9010ebf | 2013-05-29 09:22:36 -0700 | [diff] [blame] | 5396 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 5397 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
Dave Gordon | 8b417c2 | 2015-08-12 15:43:44 +0100 | [diff] [blame] | 5398 | {"i915_guc_info", i915_guc_info, 0}, |
Alex Dai | fdf5d35 | 2015-08-12 15:43:37 +0100 | [diff] [blame] | 5399 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
Alex Dai | 4c7e77f | 2015-08-12 15:43:40 +0100 | [diff] [blame] | 5400 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
Deepak S | adb4bd1 | 2014-03-31 11:30:02 +0530 | [diff] [blame] | 5401 | {"i915_frequency_info", i915_frequency_info, 0}, |
Chris Wilson | f654449a | 2015-01-26 18:03:04 +0200 | [diff] [blame] | 5402 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5403 | {"i915_drpc_info", i915_drpc_info, 0}, |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5404 | {"i915_emon_status", i915_emon_status, 0}, |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 5405 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
Daniel Vetter | 9a85178 | 2015-06-18 10:30:22 +0200 | [diff] [blame] | 5406 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 5407 | {"i915_fbc_status", i915_fbc_status, 0}, |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 5408 | {"i915_ips_status", i915_ips_status, 0}, |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 5409 | {"i915_sr_status", i915_sr_status, 0}, |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 5410 | {"i915_opregion", i915_opregion, 0}, |
Jani Nikula | ada8f95 | 2015-12-15 13:17:12 +0200 | [diff] [blame] | 5411 | {"i915_vbt", i915_vbt, 0}, |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 5412 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 5413 | {"i915_context_status", i915_context_status, 0}, |
Ben Widawsky | c0ab1ae | 2014-08-07 13:24:26 +0100 | [diff] [blame] | 5414 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 5415 | {"i915_execlists", i915_execlists, 0}, |
Mika Kuoppala | f65367b | 2015-01-16 11:34:42 +0200 | [diff] [blame] | 5416 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 5417 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 5418 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 5419 | {"i915_llc", i915_llc, 0}, |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 5420 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 5421 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 5422 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
Damien Lespiau | 6455c87 | 2015-06-04 18:23:57 +0100 | [diff] [blame] | 5423 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 5424 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
Damien Lespiau | b7cec66 | 2015-10-27 14:47:01 +0200 | [diff] [blame] | 5425 | {"i915_dmc_info", i915_dmc_info, 0}, |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 5426 | {"i915_display_info", i915_display_info, 0}, |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 5427 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
Daniel Vetter | 728e29d | 2014-06-25 22:01:53 +0300 | [diff] [blame] | 5428 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
Dave Airlie | 11bed958 | 2014-05-12 15:22:27 +1000 | [diff] [blame] | 5429 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
Damien Lespiau | 1ed1ef9 | 2014-08-30 16:50:59 +0100 | [diff] [blame] | 5430 | {"i915_wa_registers", i915_wa_registers, 0}, |
Damien Lespiau | c5511e4 | 2014-11-04 17:06:51 +0000 | [diff] [blame] | 5431 | {"i915_ddb_info", i915_ddb_info, 0}, |
Jeff McGee | 3873218 | 2015-02-13 10:27:54 -0600 | [diff] [blame] | 5432 | {"i915_sseu_status", i915_sseu_status, 0}, |
Vandana Kannan | a54746e | 2015-03-03 20:53:10 +0530 | [diff] [blame] | 5433 | {"i915_drrs_status", i915_drrs_status, 0}, |
Chris Wilson | 1854d5c | 2015-04-07 16:20:32 +0100 | [diff] [blame] | 5434 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 5435 | }; |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 5436 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 5437 | |
Lespiau, Damien | 06c5bf8 | 2013-10-17 19:09:56 +0100 | [diff] [blame] | 5438 | static const struct i915_debugfs_files { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 5439 | const char *name; |
| 5440 | const struct file_operations *fops; |
| 5441 | } i915_debugfs_files[] = { |
| 5442 | {"i915_wedged", &i915_wedged_fops}, |
| 5443 | {"i915_max_freq", &i915_max_freq_fops}, |
| 5444 | {"i915_min_freq", &i915_min_freq_fops}, |
| 5445 | {"i915_cache_sharing", &i915_cache_sharing_fops}, |
| 5446 | {"i915_ring_stop", &i915_ring_stop_fops}, |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 5447 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
| 5448 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 5449 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
| 5450 | {"i915_error_state", &i915_error_state_fops}, |
| 5451 | {"i915_next_seqno", &i915_next_seqno_fops}, |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 5452 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 5453 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
| 5454 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, |
| 5455 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, |
Rodrigo Vivi | da46f93 | 2014-08-01 02:04:45 -0700 | [diff] [blame] | 5456 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
Todd Previte | eb3394fa | 2015-04-18 00:04:19 -0700 | [diff] [blame] | 5457 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
| 5458 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, |
| 5459 | {"i915_dp_test_active", &i915_displayport_test_active_fops} |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 5460 | }; |
| 5461 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 5462 | void intel_display_crc_init(struct drm_device *dev) |
| 5463 | { |
| 5464 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | b378360 | 2013-11-14 11:30:42 +0100 | [diff] [blame] | 5465 | enum pipe pipe; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 5466 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 5467 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | b378360 | 2013-11-14 11:30:42 +0100 | [diff] [blame] | 5468 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 5469 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 5470 | pipe_crc->opened = false; |
| 5471 | spin_lock_init(&pipe_crc->lock); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 5472 | init_waitqueue_head(&pipe_crc->wq); |
| 5473 | } |
| 5474 | } |
| 5475 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 5476 | int i915_debugfs_init(struct drm_minor *minor) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 5477 | { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 5478 | int ret, i; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 5479 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 5480 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
| 5481 | if (ret) |
| 5482 | return ret; |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 5483 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 5484 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
| 5485 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); |
| 5486 | if (ret) |
| 5487 | return ret; |
| 5488 | } |
| 5489 | |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 5490 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
| 5491 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
| 5492 | i915_debugfs_files[i].name, |
| 5493 | i915_debugfs_files[i].fops); |
| 5494 | if (ret) |
| 5495 | return ret; |
| 5496 | } |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 5497 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 5498 | return drm_debugfs_create_files(i915_debugfs_list, |
| 5499 | I915_DEBUGFS_ENTRIES, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 5500 | minor->debugfs_root, minor); |
| 5501 | } |
| 5502 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 5503 | void i915_debugfs_cleanup(struct drm_minor *minor) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 5504 | { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 5505 | int i; |
| 5506 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 5507 | drm_debugfs_remove_files(i915_debugfs_list, |
| 5508 | I915_DEBUGFS_ENTRIES, minor); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 5509 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 5510 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
| 5511 | 1, minor); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 5512 | |
Daniel Vetter | e309a99 | 2013-10-16 22:55:51 +0200 | [diff] [blame] | 5513 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 5514 | struct drm_info_list *info_list = |
| 5515 | (struct drm_info_list *)&i915_pipe_crc_data[i]; |
| 5516 | |
| 5517 | drm_debugfs_remove_files(info_list, 1, minor); |
| 5518 | } |
| 5519 | |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 5520 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
| 5521 | struct drm_info_list *info_list = |
| 5522 | (struct drm_info_list *) i915_debugfs_files[i].fops; |
| 5523 | |
| 5524 | drm_debugfs_remove_files(info_list, 1, minor); |
| 5525 | } |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 5526 | } |
Jani Nikula | aa7471d | 2015-04-01 11:15:21 +0300 | [diff] [blame] | 5527 | |
| 5528 | struct dpcd_block { |
| 5529 | /* DPCD dump start address. */ |
| 5530 | unsigned int offset; |
| 5531 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ |
| 5532 | unsigned int end; |
| 5533 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ |
| 5534 | size_t size; |
| 5535 | /* Only valid for eDP. */ |
| 5536 | bool edp; |
| 5537 | }; |
| 5538 | |
| 5539 | static const struct dpcd_block i915_dpcd_debug[] = { |
| 5540 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, |
| 5541 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, |
| 5542 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, |
| 5543 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, |
| 5544 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, |
| 5545 | { .offset = DP_SET_POWER }, |
| 5546 | { .offset = DP_EDP_DPCD_REV }, |
| 5547 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, |
| 5548 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, |
| 5549 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, |
| 5550 | }; |
| 5551 | |
| 5552 | static int i915_dpcd_show(struct seq_file *m, void *data) |
| 5553 | { |
| 5554 | struct drm_connector *connector = m->private; |
| 5555 | struct intel_dp *intel_dp = |
| 5556 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
| 5557 | uint8_t buf[16]; |
| 5558 | ssize_t err; |
| 5559 | int i; |
| 5560 | |
Mika Kuoppala | 5c1a887 | 2015-05-15 13:09:21 +0300 | [diff] [blame] | 5561 | if (connector->status != connector_status_connected) |
| 5562 | return -ENODEV; |
| 5563 | |
Jani Nikula | aa7471d | 2015-04-01 11:15:21 +0300 | [diff] [blame] | 5564 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
| 5565 | const struct dpcd_block *b = &i915_dpcd_debug[i]; |
| 5566 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); |
| 5567 | |
| 5568 | if (b->edp && |
| 5569 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) |
| 5570 | continue; |
| 5571 | |
| 5572 | /* low tech for now */ |
| 5573 | if (WARN_ON(size > sizeof(buf))) |
| 5574 | continue; |
| 5575 | |
| 5576 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); |
| 5577 | if (err <= 0) { |
| 5578 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", |
| 5579 | size, b->offset, err); |
| 5580 | continue; |
| 5581 | } |
| 5582 | |
| 5583 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); |
kbuild test robot | b3f9d7d | 2015-04-16 18:34:06 +0800 | [diff] [blame] | 5584 | } |
Jani Nikula | aa7471d | 2015-04-01 11:15:21 +0300 | [diff] [blame] | 5585 | |
| 5586 | return 0; |
| 5587 | } |
| 5588 | |
| 5589 | static int i915_dpcd_open(struct inode *inode, struct file *file) |
| 5590 | { |
| 5591 | return single_open(file, i915_dpcd_show, inode->i_private); |
| 5592 | } |
| 5593 | |
| 5594 | static const struct file_operations i915_dpcd_fops = { |
| 5595 | .owner = THIS_MODULE, |
| 5596 | .open = i915_dpcd_open, |
| 5597 | .read = seq_read, |
| 5598 | .llseek = seq_lseek, |
| 5599 | .release = single_release, |
| 5600 | }; |
| 5601 | |
| 5602 | /** |
| 5603 | * i915_debugfs_connector_add - add i915 specific connector debugfs files |
| 5604 | * @connector: pointer to a registered drm_connector |
| 5605 | * |
| 5606 | * Cleanup will be done by drm_connector_unregister() through a call to |
| 5607 | * drm_debugfs_connector_remove(). |
| 5608 | * |
| 5609 | * Returns 0 on success, negative error codes on error. |
| 5610 | */ |
| 5611 | int i915_debugfs_connector_add(struct drm_connector *connector) |
| 5612 | { |
| 5613 | struct dentry *root = connector->debugfs_entry; |
| 5614 | |
| 5615 | /* The connector must have been registered beforehands. */ |
| 5616 | if (!root) |
| 5617 | return -ENODEV; |
| 5618 | |
| 5619 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || |
| 5620 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
| 5621 | debugfs_create_file("i915_dpcd", S_IRUGO, root, connector, |
| 5622 | &i915_dpcd_fops); |
| 5623 | |
| 5624 | return 0; |
| 5625 | } |