blob: b2dca46989e0d979280cc388e68fc53f94d631a7 [file] [log] [blame]
Ben Gamari20172632009-02-17 20:08:50 -05001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
Damien Lespiaub2c88f52013-10-15 18:55:29 +010030#include <linux/circ_buf.h>
Daniel Vetter926321d2013-10-16 13:30:34 +020031#include <linux/ctype.h>
Chris Wilsonf3cd4742009-10-13 22:20:20 +010032#include <linux/debugfs.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090033#include <linux/slab.h>
Paul Gortmaker2d1a8a42011-08-30 18:16:33 -040034#include <linux/export.h>
Chris Wilson6d2b8882013-08-07 18:30:54 +010035#include <linux/list_sort.h>
Jesse Barnesec013e72013-08-20 10:29:23 +010036#include <asm/msr-index.h>
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/drmP.h>
Simon Farnsworth4e5359c2010-09-01 17:47:52 +010038#include "intel_drv.h"
Chris Wilsone5c65262010-11-01 11:35:28 +000039#include "intel_ringbuffer.h"
David Howells760285e2012-10-02 18:01:07 +010040#include <drm/i915_drm.h>
Ben Gamari20172632009-02-17 20:08:50 -050041#include "i915_drv.h"
42
Chris Wilsonf13d3f72010-09-20 17:36:15 +010043enum {
Chris Wilson69dc4982010-10-19 10:36:51 +010044 ACTIVE_LIST,
Chris Wilsonf13d3f72010-09-20 17:36:15 +010045 INACTIVE_LIST,
Chris Wilsond21d5972010-09-26 11:19:33 +010046 PINNED_LIST,
Chris Wilsonf13d3f72010-09-20 17:36:15 +010047};
Ben Gamari433e12f2009-02-17 20:08:51 -050048
Chris Wilson70d39fe2010-08-25 16:03:34 +010049static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
Damien Lespiau497666d2013-10-15 18:55:39 +010054/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
Chris Wilson70d39fe2010-08-25 16:03:34 +010080static int i915_capabilities(struct seq_file *m, void *data)
81{
Damien Lespiau9f25d002014-05-13 15:30:28 +010082 struct drm_info_node *node = m->private;
Chris Wilson70d39fe2010-08-25 16:03:34 +010083 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
Paulo Zanoni03d00ac2011-10-14 18:17:41 -030087 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
Damien Lespiau79fc46d2013-04-23 16:37:17 +010088#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
Chris Wilson70d39fe2010-08-25 16:03:34 +010093
94 return 0;
95}
Ben Gamari433e12f2009-02-17 20:08:51 -050096
Chris Wilson05394f32010-11-08 19:18:58 +000097static const char *get_pin_flag(struct drm_i915_gem_object *obj)
Chris Wilsona6172a82009-02-11 14:26:38 +000098{
Daniel Vetter4feb7652014-11-24 11:21:52 +010099 if (i915_gem_obj_is_pinned(obj))
Chris Wilsona6172a82009-02-11 14:26:38 +0000100 return "p";
101 else
102 return " ";
103}
104
Chris Wilson05394f32010-11-08 19:18:58 +0000105static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
Chris Wilsona6172a82009-02-11 14:26:38 +0000106{
Akshay Joshi0206e352011-08-16 15:34:10 -0400107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
Chris Wilsona6172a82009-02-11 14:26:38 +0000113}
114
Ben Widawsky1d693bc2013-07-31 17:00:00 -0700115static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116{
Tvrtko Ursulinaff43762014-10-24 12:42:33 +0100117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
Ben Widawsky1d693bc2013-07-31 17:00:00 -0700118}
119
Chris Wilson37811fc2010-08-25 22:45:57 +0100120static void
121describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
122{
Ben Widawsky1d693bc2013-07-31 17:00:00 -0700123 struct i915_vma *vma;
Ben Widawskyd7f46fc2013-12-06 14:10:55 -0800124 int pin_count = 0;
125
Ville Syrjäläfb1ae912013-08-22 19:21:30 +0300126 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
Chris Wilson37811fc2010-08-25 22:45:57 +0100127 &obj->base,
128 get_pin_flag(obj),
129 get_tiling_flag(obj),
Ben Widawsky1d693bc2013-07-31 17:00:00 -0700130 get_global_flag(obj),
Eric Anholta05a5862011-12-20 08:54:15 -0800131 obj->base.size / 1024,
Chris Wilson37811fc2010-08-25 22:45:57 +0100132 obj->base.read_domains,
133 obj->base.write_domain,
John Harrison97b2a6a2014-11-24 18:49:26 +0000134 i915_gem_request_get_seqno(obj->last_read_req),
135 i915_gem_request_get_seqno(obj->last_write_req),
136 i915_gem_request_get_seqno(obj->last_fenced_req),
Chris Wilson0a4cd7c2014-08-22 14:41:39 +0100137 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
Chris Wilson37811fc2010-08-25 22:45:57 +0100138 obj->dirty ? " dirty" : "",
139 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
140 if (obj->base.name)
141 seq_printf(m, " (name: %d)", obj->base.name);
Ben Widawskyd7f46fc2013-12-06 14:10:55 -0800142 list_for_each_entry(vma, &obj->vma_list, vma_link)
143 if (vma->pin_count > 0)
144 pin_count++;
145 seq_printf(m, " (pinned x %d)", pin_count);
Chris Wilsoncc98b412013-08-09 12:25:09 +0100146 if (obj->pin_display)
147 seq_printf(m, " (display)");
Chris Wilson37811fc2010-08-25 22:45:57 +0100148 if (obj->fence_reg != I915_FENCE_REG_NONE)
149 seq_printf(m, " (fence: %d)", obj->fence_reg);
Ben Widawsky1d693bc2013-07-31 17:00:00 -0700150 list_for_each_entry(vma, &obj->vma_list, vma_link) {
151 if (!i915_is_ggtt(vma->vm))
152 seq_puts(m, " (pp");
153 else
154 seq_puts(m, " (g");
155 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
156 vma->node.start, vma->node.size);
157 }
Chris Wilsonc1ad11f2012-11-15 11:32:21 +0000158 if (obj->stolen)
159 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
Chris Wilson6299f992010-11-24 12:23:44 +0000160 if (obj->pin_mappable || obj->fault_mappable) {
161 char s[3], *t = s;
162 if (obj->pin_mappable)
163 *t++ = 'p';
164 if (obj->fault_mappable)
165 *t++ = 'f';
166 *t = '\0';
167 seq_printf(m, " (%s mappable)", s);
168 }
John Harrison41c52412014-11-24 18:49:43 +0000169 if (obj->last_read_req != NULL)
170 seq_printf(m, " (%s)",
171 i915_gem_request_get_ring(obj->last_read_req)->name);
Daniel Vetterd5a81ef2014-06-18 14:46:49 +0200172 if (obj->frontbuffer_bits)
173 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
Chris Wilson37811fc2010-08-25 22:45:57 +0100174}
175
Oscar Mateo273497e2014-05-22 14:13:37 +0100176static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
Ben Widawsky3ccfd192013-09-18 19:03:18 -0700177{
Oscar Mateoea0c76f2014-07-03 16:27:59 +0100178 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
Ben Widawsky3ccfd192013-09-18 19:03:18 -0700179 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
180 seq_putc(m, ' ');
181}
182
Ben Gamari433e12f2009-02-17 20:08:51 -0500183static int i915_gem_object_list_info(struct seq_file *m, void *data)
Ben Gamari20172632009-02-17 20:08:50 -0500184{
Damien Lespiau9f25d002014-05-13 15:30:28 +0100185 struct drm_info_node *node = m->private;
Ben Gamari433e12f2009-02-17 20:08:51 -0500186 uintptr_t list = (uintptr_t) node->info_ent->data;
187 struct list_head *head;
Ben Gamari20172632009-02-17 20:08:50 -0500188 struct drm_device *dev = node->minor->dev;
Ben Widawsky5cef07e2013-07-16 16:50:08 -0700189 struct drm_i915_private *dev_priv = dev->dev_private;
190 struct i915_address_space *vm = &dev_priv->gtt.base;
Ben Widawskyca191b12013-07-31 17:00:14 -0700191 struct i915_vma *vma;
Chris Wilson8f2480f2010-09-26 11:44:19 +0100192 size_t total_obj_size, total_gtt_size;
193 int count, ret;
Chris Wilsonde227ef2010-07-03 07:58:38 +0100194
195 ret = mutex_lock_interruptible(&dev->struct_mutex);
196 if (ret)
197 return ret;
Ben Gamari20172632009-02-17 20:08:50 -0500198
Ben Widawskyca191b12013-07-31 17:00:14 -0700199 /* FIXME: the user of this interface might want more than just GGTT */
Ben Gamari433e12f2009-02-17 20:08:51 -0500200 switch (list) {
201 case ACTIVE_LIST:
Damien Lespiau267f0c92013-06-24 22:59:48 +0100202 seq_puts(m, "Active:\n");
Ben Widawsky5cef07e2013-07-16 16:50:08 -0700203 head = &vm->active_list;
Ben Gamari433e12f2009-02-17 20:08:51 -0500204 break;
205 case INACTIVE_LIST:
Damien Lespiau267f0c92013-06-24 22:59:48 +0100206 seq_puts(m, "Inactive:\n");
Ben Widawsky5cef07e2013-07-16 16:50:08 -0700207 head = &vm->inactive_list;
Ben Gamari433e12f2009-02-17 20:08:51 -0500208 break;
Ben Gamari433e12f2009-02-17 20:08:51 -0500209 default:
Chris Wilsonde227ef2010-07-03 07:58:38 +0100210 mutex_unlock(&dev->struct_mutex);
211 return -EINVAL;
Ben Gamari433e12f2009-02-17 20:08:51 -0500212 }
213
Chris Wilson8f2480f2010-09-26 11:44:19 +0100214 total_obj_size = total_gtt_size = count = 0;
Ben Widawskyca191b12013-07-31 17:00:14 -0700215 list_for_each_entry(vma, head, mm_list) {
216 seq_printf(m, " ");
217 describe_obj(m, vma->obj);
218 seq_printf(m, "\n");
219 total_obj_size += vma->obj->base.size;
220 total_gtt_size += vma->node.size;
Chris Wilson8f2480f2010-09-26 11:44:19 +0100221 count++;
Ben Gamari20172632009-02-17 20:08:50 -0500222 }
Chris Wilsonde227ef2010-07-03 07:58:38 +0100223 mutex_unlock(&dev->struct_mutex);
Carl Worth5e118f42009-03-20 11:54:25 -0700224
Chris Wilson8f2480f2010-09-26 11:44:19 +0100225 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
226 count, total_obj_size, total_gtt_size);
Ben Gamari20172632009-02-17 20:08:50 -0500227 return 0;
228}
229
Chris Wilson6d2b8882013-08-07 18:30:54 +0100230static int obj_rank_by_stolen(void *priv,
231 struct list_head *A, struct list_head *B)
232{
233 struct drm_i915_gem_object *a =
Ben Widawskyb25cb2f2013-08-14 11:38:33 +0200234 container_of(A, struct drm_i915_gem_object, obj_exec_link);
Chris Wilson6d2b8882013-08-07 18:30:54 +0100235 struct drm_i915_gem_object *b =
Ben Widawskyb25cb2f2013-08-14 11:38:33 +0200236 container_of(B, struct drm_i915_gem_object, obj_exec_link);
Chris Wilson6d2b8882013-08-07 18:30:54 +0100237
238 return a->stolen->start - b->stolen->start;
239}
240
241static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
242{
Damien Lespiau9f25d002014-05-13 15:30:28 +0100243 struct drm_info_node *node = m->private;
Chris Wilson6d2b8882013-08-07 18:30:54 +0100244 struct drm_device *dev = node->minor->dev;
245 struct drm_i915_private *dev_priv = dev->dev_private;
246 struct drm_i915_gem_object *obj;
247 size_t total_obj_size, total_gtt_size;
248 LIST_HEAD(stolen);
249 int count, ret;
250
251 ret = mutex_lock_interruptible(&dev->struct_mutex);
252 if (ret)
253 return ret;
254
255 total_obj_size = total_gtt_size = count = 0;
256 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
257 if (obj->stolen == NULL)
258 continue;
259
Ben Widawskyb25cb2f2013-08-14 11:38:33 +0200260 list_add(&obj->obj_exec_link, &stolen);
Chris Wilson6d2b8882013-08-07 18:30:54 +0100261
262 total_obj_size += obj->base.size;
263 total_gtt_size += i915_gem_obj_ggtt_size(obj);
264 count++;
265 }
266 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
267 if (obj->stolen == NULL)
268 continue;
269
Ben Widawskyb25cb2f2013-08-14 11:38:33 +0200270 list_add(&obj->obj_exec_link, &stolen);
Chris Wilson6d2b8882013-08-07 18:30:54 +0100271
272 total_obj_size += obj->base.size;
273 count++;
274 }
275 list_sort(NULL, &stolen, obj_rank_by_stolen);
276 seq_puts(m, "Stolen:\n");
277 while (!list_empty(&stolen)) {
Ben Widawskyb25cb2f2013-08-14 11:38:33 +0200278 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
Chris Wilson6d2b8882013-08-07 18:30:54 +0100279 seq_puts(m, " ");
280 describe_obj(m, obj);
281 seq_putc(m, '\n');
Ben Widawskyb25cb2f2013-08-14 11:38:33 +0200282 list_del_init(&obj->obj_exec_link);
Chris Wilson6d2b8882013-08-07 18:30:54 +0100283 }
284 mutex_unlock(&dev->struct_mutex);
285
286 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
287 count, total_obj_size, total_gtt_size);
288 return 0;
289}
290
Chris Wilson6299f992010-11-24 12:23:44 +0000291#define count_objects(list, member) do { \
292 list_for_each_entry(obj, list, member) { \
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700293 size += i915_gem_obj_ggtt_size(obj); \
Chris Wilson6299f992010-11-24 12:23:44 +0000294 ++count; \
295 if (obj->map_and_fenceable) { \
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700296 mappable_size += i915_gem_obj_ggtt_size(obj); \
Chris Wilson6299f992010-11-24 12:23:44 +0000297 ++mappable_count; \
298 } \
299 } \
Akshay Joshi0206e352011-08-16 15:34:10 -0400300} while (0)
Chris Wilson6299f992010-11-24 12:23:44 +0000301
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100302struct file_stats {
Chris Wilson6313c202014-03-19 13:45:45 +0000303 struct drm_i915_file_private *file_priv;
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100304 int count;
Chris Wilsonc67a17e2014-03-19 13:45:46 +0000305 size_t total, unbound;
306 size_t global, shared;
307 size_t active, inactive;
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100308};
309
310static int per_file_stats(int id, void *ptr, void *data)
311{
312 struct drm_i915_gem_object *obj = ptr;
313 struct file_stats *stats = data;
Chris Wilson6313c202014-03-19 13:45:45 +0000314 struct i915_vma *vma;
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100315
316 stats->count++;
317 stats->total += obj->base.size;
318
Chris Wilsonc67a17e2014-03-19 13:45:46 +0000319 if (obj->base.name || obj->base.dma_buf)
320 stats->shared += obj->base.size;
321
Chris Wilson6313c202014-03-19 13:45:45 +0000322 if (USES_FULL_PPGTT(obj->base.dev)) {
323 list_for_each_entry(vma, &obj->vma_list, vma_link) {
324 struct i915_hw_ppgtt *ppgtt;
325
326 if (!drm_mm_node_allocated(&vma->node))
327 continue;
328
329 if (i915_is_ggtt(vma->vm)) {
330 stats->global += obj->base.size;
331 continue;
332 }
333
334 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
Daniel Vetter4d884702014-08-06 15:04:47 +0200335 if (ppgtt->file_priv != stats->file_priv)
Chris Wilson6313c202014-03-19 13:45:45 +0000336 continue;
337
John Harrison41c52412014-11-24 18:49:43 +0000338 if (obj->active) /* XXX per-vma statistic */
Chris Wilson6313c202014-03-19 13:45:45 +0000339 stats->active += obj->base.size;
340 else
341 stats->inactive += obj->base.size;
342
343 return 0;
344 }
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100345 } else {
Chris Wilson6313c202014-03-19 13:45:45 +0000346 if (i915_gem_obj_ggtt_bound(obj)) {
347 stats->global += obj->base.size;
John Harrison41c52412014-11-24 18:49:43 +0000348 if (obj->active)
Chris Wilson6313c202014-03-19 13:45:45 +0000349 stats->active += obj->base.size;
350 else
351 stats->inactive += obj->base.size;
352 return 0;
353 }
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100354 }
355
Chris Wilson6313c202014-03-19 13:45:45 +0000356 if (!list_empty(&obj->global_list))
357 stats->unbound += obj->base.size;
358
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100359 return 0;
360}
361
Ben Widawskyca191b12013-07-31 17:00:14 -0700362#define count_vmas(list, member) do { \
363 list_for_each_entry(vma, list, member) { \
364 size += i915_gem_obj_ggtt_size(vma->obj); \
365 ++count; \
366 if (vma->obj->map_and_fenceable) { \
367 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
368 ++mappable_count; \
369 } \
370 } \
371} while (0)
372
373static int i915_gem_object_info(struct seq_file *m, void* data)
Chris Wilson73aa8082010-09-30 11:46:12 +0100374{
Damien Lespiau9f25d002014-05-13 15:30:28 +0100375 struct drm_info_node *node = m->private;
Chris Wilson73aa8082010-09-30 11:46:12 +0100376 struct drm_device *dev = node->minor->dev;
377 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonb7abb712012-08-20 11:33:30 +0200378 u32 count, mappable_count, purgeable_count;
379 size_t size, mappable_size, purgeable_size;
Chris Wilson6299f992010-11-24 12:23:44 +0000380 struct drm_i915_gem_object *obj;
Ben Widawsky5cef07e2013-07-16 16:50:08 -0700381 struct i915_address_space *vm = &dev_priv->gtt.base;
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100382 struct drm_file *file;
Ben Widawskyca191b12013-07-31 17:00:14 -0700383 struct i915_vma *vma;
Chris Wilson73aa8082010-09-30 11:46:12 +0100384 int ret;
385
386 ret = mutex_lock_interruptible(&dev->struct_mutex);
387 if (ret)
388 return ret;
389
Chris Wilson6299f992010-11-24 12:23:44 +0000390 seq_printf(m, "%u objects, %zu bytes\n",
391 dev_priv->mm.object_count,
392 dev_priv->mm.object_memory);
393
394 size = count = mappable_size = mappable_count = 0;
Ben Widawsky35c20a62013-05-31 11:28:48 -0700395 count_objects(&dev_priv->mm.bound_list, global_list);
Chris Wilson6299f992010-11-24 12:23:44 +0000396 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
397 count, mappable_count, size, mappable_size);
398
399 size = count = mappable_size = mappable_count = 0;
Ben Widawskyca191b12013-07-31 17:00:14 -0700400 count_vmas(&vm->active_list, mm_list);
Chris Wilson6299f992010-11-24 12:23:44 +0000401 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
402 count, mappable_count, size, mappable_size);
403
404 size = count = mappable_size = mappable_count = 0;
Ben Widawskyca191b12013-07-31 17:00:14 -0700405 count_vmas(&vm->inactive_list, mm_list);
Chris Wilson6299f992010-11-24 12:23:44 +0000406 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
407 count, mappable_count, size, mappable_size);
408
Chris Wilsonb7abb712012-08-20 11:33:30 +0200409 size = count = purgeable_size = purgeable_count = 0;
Ben Widawsky35c20a62013-05-31 11:28:48 -0700410 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
Chris Wilson6c085a72012-08-20 11:40:46 +0200411 size += obj->base.size, ++count;
Chris Wilsonb7abb712012-08-20 11:33:30 +0200412 if (obj->madv == I915_MADV_DONTNEED)
413 purgeable_size += obj->base.size, ++purgeable_count;
414 }
Chris Wilson6c085a72012-08-20 11:40:46 +0200415 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
416
Chris Wilson6299f992010-11-24 12:23:44 +0000417 size = count = mappable_size = mappable_count = 0;
Ben Widawsky35c20a62013-05-31 11:28:48 -0700418 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
Chris Wilson6299f992010-11-24 12:23:44 +0000419 if (obj->fault_mappable) {
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700420 size += i915_gem_obj_ggtt_size(obj);
Chris Wilson6299f992010-11-24 12:23:44 +0000421 ++count;
422 }
423 if (obj->pin_mappable) {
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700424 mappable_size += i915_gem_obj_ggtt_size(obj);
Chris Wilson6299f992010-11-24 12:23:44 +0000425 ++mappable_count;
426 }
Chris Wilsonb7abb712012-08-20 11:33:30 +0200427 if (obj->madv == I915_MADV_DONTNEED) {
428 purgeable_size += obj->base.size;
429 ++purgeable_count;
430 }
Chris Wilson6299f992010-11-24 12:23:44 +0000431 }
Chris Wilsonb7abb712012-08-20 11:33:30 +0200432 seq_printf(m, "%u purgeable objects, %zu bytes\n",
433 purgeable_count, purgeable_size);
Chris Wilson6299f992010-11-24 12:23:44 +0000434 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
435 mappable_count, mappable_size);
436 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
437 count, size);
438
Ben Widawsky93d18792013-01-17 12:45:17 -0800439 seq_printf(m, "%zu [%lu] gtt total\n",
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700440 dev_priv->gtt.base.total,
441 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
Chris Wilson73aa8082010-09-30 11:46:12 +0100442
Damien Lespiau267f0c92013-06-24 22:59:48 +0100443 seq_putc(m, '\n');
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100444 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
445 struct file_stats stats;
Tetsuo Handa3ec2f422014-01-03 20:42:18 +0900446 struct task_struct *task;
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100447
448 memset(&stats, 0, sizeof(stats));
Chris Wilson6313c202014-03-19 13:45:45 +0000449 stats.file_priv = file->driver_priv;
Chris Wilson5b5ffff2014-06-17 09:56:24 +0100450 spin_lock(&file->table_lock);
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100451 idr_for_each(&file->object_idr, per_file_stats, &stats);
Chris Wilson5b5ffff2014-06-17 09:56:24 +0100452 spin_unlock(&file->table_lock);
Tetsuo Handa3ec2f422014-01-03 20:42:18 +0900453 /*
454 * Although we have a valid reference on file->pid, that does
455 * not guarantee that the task_struct who called get_pid() is
456 * still alive (e.g. get_pid(current) => fork() => exit()).
457 * Therefore, we need to protect this ->comm access using RCU.
458 */
459 rcu_read_lock();
460 task = pid_task(file->pid, PIDTYPE_PID);
Chris Wilsonc67a17e2014-03-19 13:45:46 +0000461 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
Tetsuo Handa3ec2f422014-01-03 20:42:18 +0900462 task ? task->comm : "<unknown>",
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100463 stats.count,
464 stats.total,
465 stats.active,
466 stats.inactive,
Chris Wilson6313c202014-03-19 13:45:45 +0000467 stats.global,
Chris Wilsonc67a17e2014-03-19 13:45:46 +0000468 stats.shared,
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100469 stats.unbound);
Tetsuo Handa3ec2f422014-01-03 20:42:18 +0900470 rcu_read_unlock();
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100471 }
472
Chris Wilson73aa8082010-09-30 11:46:12 +0100473 mutex_unlock(&dev->struct_mutex);
474
475 return 0;
476}
477
Damien Lespiauaee56cf2013-06-24 22:59:49 +0100478static int i915_gem_gtt_info(struct seq_file *m, void *data)
Chris Wilson08c18322011-01-10 00:00:24 +0000479{
Damien Lespiau9f25d002014-05-13 15:30:28 +0100480 struct drm_info_node *node = m->private;
Chris Wilson08c18322011-01-10 00:00:24 +0000481 struct drm_device *dev = node->minor->dev;
Chris Wilson1b502472012-04-24 15:47:30 +0100482 uintptr_t list = (uintptr_t) node->info_ent->data;
Chris Wilson08c18322011-01-10 00:00:24 +0000483 struct drm_i915_private *dev_priv = dev->dev_private;
484 struct drm_i915_gem_object *obj;
485 size_t total_obj_size, total_gtt_size;
486 int count, ret;
487
488 ret = mutex_lock_interruptible(&dev->struct_mutex);
489 if (ret)
490 return ret;
491
492 total_obj_size = total_gtt_size = count = 0;
Ben Widawsky35c20a62013-05-31 11:28:48 -0700493 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
Ben Widawskyd7f46fc2013-12-06 14:10:55 -0800494 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
Chris Wilson1b502472012-04-24 15:47:30 +0100495 continue;
496
Damien Lespiau267f0c92013-06-24 22:59:48 +0100497 seq_puts(m, " ");
Chris Wilson08c18322011-01-10 00:00:24 +0000498 describe_obj(m, obj);
Damien Lespiau267f0c92013-06-24 22:59:48 +0100499 seq_putc(m, '\n');
Chris Wilson08c18322011-01-10 00:00:24 +0000500 total_obj_size += obj->base.size;
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700501 total_gtt_size += i915_gem_obj_ggtt_size(obj);
Chris Wilson08c18322011-01-10 00:00:24 +0000502 count++;
503 }
504
505 mutex_unlock(&dev->struct_mutex);
506
507 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
508 count, total_obj_size, total_gtt_size);
509
510 return 0;
511}
512
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100513static int i915_gem_pageflip_info(struct seq_file *m, void *data)
514{
Damien Lespiau9f25d002014-05-13 15:30:28 +0100515 struct drm_info_node *node = m->private;
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100516 struct drm_device *dev = node->minor->dev;
Chris Wilsond6bbafa2014-09-05 07:13:24 +0100517 struct drm_i915_private *dev_priv = dev->dev_private;
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100518 struct intel_crtc *crtc;
Daniel Vetter8a270eb2014-06-17 22:34:37 +0200519 int ret;
520
521 ret = mutex_lock_interruptible(&dev->struct_mutex);
522 if (ret)
523 return ret;
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100524
Damien Lespiaud3fcc802014-05-13 23:32:22 +0100525 for_each_intel_crtc(dev, crtc) {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800526 const char pipe = pipe_name(crtc->pipe);
527 const char plane = plane_name(crtc->plane);
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100528 struct intel_unpin_work *work;
529
Daniel Vetter5e2d7af2014-09-15 14:55:22 +0200530 spin_lock_irq(&dev->event_lock);
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100531 work = crtc->unpin_work;
532 if (work == NULL) {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800533 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100534 pipe, plane);
535 } else {
Chris Wilsond6bbafa2014-09-05 07:13:24 +0100536 u32 addr;
537
Chris Wilsone7d841c2012-12-03 11:36:30 +0000538 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800539 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100540 pipe, plane);
541 } else {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800542 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100543 pipe, plane);
544 }
Chris Wilsond6bbafa2014-09-05 07:13:24 +0100545 if (work->flip_queued_ring) {
546 seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n",
547 work->flip_queued_ring->name,
John Harrisonf06cc1b2014-11-24 18:49:37 +0000548 i915_gem_request_get_seqno(work->flip_queued_req),
Chris Wilsond6bbafa2014-09-05 07:13:24 +0100549 dev_priv->next_seqno,
550 work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
John Harrison1b5a4332014-11-24 18:49:42 +0000551 i915_gem_request_completed(work->flip_queued_req, true));
Chris Wilsond6bbafa2014-09-05 07:13:24 +0100552 } else
553 seq_printf(m, "Flip not associated with any ring\n");
554 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
555 work->flip_queued_vblank,
556 work->flip_ready_vblank,
557 drm_vblank_count(dev, crtc->pipe));
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100558 if (work->enable_stall_check)
Damien Lespiau267f0c92013-06-24 22:59:48 +0100559 seq_puts(m, "Stall check enabled, ");
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100560 else
Damien Lespiau267f0c92013-06-24 22:59:48 +0100561 seq_puts(m, "Stall check waiting for page flip ioctl, ");
Chris Wilsone7d841c2012-12-03 11:36:30 +0000562 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100563
Chris Wilsond6bbafa2014-09-05 07:13:24 +0100564 if (INTEL_INFO(dev)->gen >= 4)
565 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
566 else
567 addr = I915_READ(DSPADDR(crtc->plane));
568 seq_printf(m, "Current scanout address 0x%08x\n", addr);
569
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100570 if (work->pending_flip_obj) {
Chris Wilsond6bbafa2014-09-05 07:13:24 +0100571 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
572 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100573 }
574 }
Daniel Vetter5e2d7af2014-09-15 14:55:22 +0200575 spin_unlock_irq(&dev->event_lock);
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100576 }
577
Daniel Vetter8a270eb2014-06-17 22:34:37 +0200578 mutex_unlock(&dev->struct_mutex);
579
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100580 return 0;
581}
582
Ben Gamari20172632009-02-17 20:08:50 -0500583static int i915_gem_request_info(struct seq_file *m, void *data)
584{
Damien Lespiau9f25d002014-05-13 15:30:28 +0100585 struct drm_info_node *node = m->private;
Ben Gamari20172632009-02-17 20:08:50 -0500586 struct drm_device *dev = node->minor->dev;
Jani Nikulae277a1f2014-03-31 14:27:14 +0300587 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +0100588 struct intel_engine_cs *ring;
Ben Gamari20172632009-02-17 20:08:50 -0500589 struct drm_i915_gem_request *gem_request;
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100590 int ret, count, i;
Chris Wilsonde227ef2010-07-03 07:58:38 +0100591
592 ret = mutex_lock_interruptible(&dev->struct_mutex);
593 if (ret)
594 return ret;
Ben Gamari20172632009-02-17 20:08:50 -0500595
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100596 count = 0;
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100597 for_each_ring(ring, dev_priv, i) {
598 if (list_empty(&ring->request_list))
599 continue;
600
601 seq_printf(m, "%s requests:\n", ring->name);
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100602 list_for_each_entry(gem_request,
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100603 &ring->request_list,
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100604 list) {
605 seq_printf(m, " %d @ %d\n",
606 gem_request->seqno,
607 (int) (jiffies - gem_request->emitted_jiffies));
608 }
609 count++;
Ben Gamari20172632009-02-17 20:08:50 -0500610 }
Chris Wilsonde227ef2010-07-03 07:58:38 +0100611 mutex_unlock(&dev->struct_mutex);
612
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100613 if (count == 0)
Damien Lespiau267f0c92013-06-24 22:59:48 +0100614 seq_puts(m, "No requests\n");
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100615
Ben Gamari20172632009-02-17 20:08:50 -0500616 return 0;
617}
618
Chris Wilsonb2223492010-10-27 15:27:33 +0100619static void i915_ring_seqno_info(struct seq_file *m,
Oscar Mateoa4872ba2014-05-22 14:13:33 +0100620 struct intel_engine_cs *ring)
Chris Wilsonb2223492010-10-27 15:27:33 +0100621{
622 if (ring->get_seqno) {
Mika Kuoppala43a7b922012-12-04 15:12:01 +0200623 seq_printf(m, "Current sequence (%s): %u\n",
Chris Wilsonb2eadbc2012-08-09 10:58:30 +0100624 ring->name, ring->get_seqno(ring, false));
Chris Wilsonb2223492010-10-27 15:27:33 +0100625 }
626}
627
Ben Gamari20172632009-02-17 20:08:50 -0500628static int i915_gem_seqno_info(struct seq_file *m, void *data)
629{
Damien Lespiau9f25d002014-05-13 15:30:28 +0100630 struct drm_info_node *node = m->private;
Ben Gamari20172632009-02-17 20:08:50 -0500631 struct drm_device *dev = node->minor->dev;
Jani Nikulae277a1f2014-03-31 14:27:14 +0300632 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +0100633 struct intel_engine_cs *ring;
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000634 int ret, i;
Chris Wilsonde227ef2010-07-03 07:58:38 +0100635
636 ret = mutex_lock_interruptible(&dev->struct_mutex);
637 if (ret)
638 return ret;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -0200639 intel_runtime_pm_get(dev_priv);
Ben Gamari20172632009-02-17 20:08:50 -0500640
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100641 for_each_ring(ring, dev_priv, i)
642 i915_ring_seqno_info(m, ring);
Chris Wilsonde227ef2010-07-03 07:58:38 +0100643
Paulo Zanonic8c8fb32013-11-27 18:21:54 -0200644 intel_runtime_pm_put(dev_priv);
Chris Wilsonde227ef2010-07-03 07:58:38 +0100645 mutex_unlock(&dev->struct_mutex);
646
Ben Gamari20172632009-02-17 20:08:50 -0500647 return 0;
648}
649
650
651static int i915_interrupt_info(struct seq_file *m, void *data)
652{
Damien Lespiau9f25d002014-05-13 15:30:28 +0100653 struct drm_info_node *node = m->private;
Ben Gamari20172632009-02-17 20:08:50 -0500654 struct drm_device *dev = node->minor->dev;
Jani Nikulae277a1f2014-03-31 14:27:14 +0300655 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +0100656 struct intel_engine_cs *ring;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800657 int ret, i, pipe;
Chris Wilsonde227ef2010-07-03 07:58:38 +0100658
659 ret = mutex_lock_interruptible(&dev->struct_mutex);
660 if (ret)
661 return ret;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -0200662 intel_runtime_pm_get(dev_priv);
Ben Gamari20172632009-02-17 20:08:50 -0500663
Ville Syrjälä74e1ca82014-04-09 13:28:09 +0300664 if (IS_CHERRYVIEW(dev)) {
Ville Syrjälä74e1ca82014-04-09 13:28:09 +0300665 seq_printf(m, "Master Interrupt Control:\t%08x\n",
666 I915_READ(GEN8_MASTER_IRQ));
667
668 seq_printf(m, "Display IER:\t%08x\n",
669 I915_READ(VLV_IER));
670 seq_printf(m, "Display IIR:\t%08x\n",
671 I915_READ(VLV_IIR));
672 seq_printf(m, "Display IIR_RW:\t%08x\n",
673 I915_READ(VLV_IIR_RW));
674 seq_printf(m, "Display IMR:\t%08x\n",
675 I915_READ(VLV_IMR));
Damien Lespiau055e3932014-08-18 13:49:10 +0100676 for_each_pipe(dev_priv, pipe)
Ville Syrjälä74e1ca82014-04-09 13:28:09 +0300677 seq_printf(m, "Pipe %c stat:\t%08x\n",
678 pipe_name(pipe),
679 I915_READ(PIPESTAT(pipe)));
680
681 seq_printf(m, "Port hotplug:\t%08x\n",
682 I915_READ(PORT_HOTPLUG_EN));
683 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
684 I915_READ(VLV_DPFLIPSTAT));
685 seq_printf(m, "DPINVGTT:\t%08x\n",
686 I915_READ(DPINVGTT));
687
688 for (i = 0; i < 4; i++) {
689 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
690 i, I915_READ(GEN8_GT_IMR(i)));
691 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
692 i, I915_READ(GEN8_GT_IIR(i)));
693 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
694 i, I915_READ(GEN8_GT_IER(i)));
695 }
696
697 seq_printf(m, "PCU interrupt mask:\t%08x\n",
698 I915_READ(GEN8_PCU_IMR));
699 seq_printf(m, "PCU interrupt identity:\t%08x\n",
700 I915_READ(GEN8_PCU_IIR));
701 seq_printf(m, "PCU interrupt enable:\t%08x\n",
702 I915_READ(GEN8_PCU_IER));
703 } else if (INTEL_INFO(dev)->gen >= 8) {
Ben Widawskya123f152013-11-02 21:07:10 -0700704 seq_printf(m, "Master Interrupt Control:\t%08x\n",
705 I915_READ(GEN8_MASTER_IRQ));
706
707 for (i = 0; i < 4; i++) {
708 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
709 i, I915_READ(GEN8_GT_IMR(i)));
710 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
711 i, I915_READ(GEN8_GT_IIR(i)));
712 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
713 i, I915_READ(GEN8_GT_IER(i)));
714 }
715
Damien Lespiau055e3932014-08-18 13:49:10 +0100716 for_each_pipe(dev_priv, pipe) {
Daniel Vetterf458ebb2014-09-30 10:56:39 +0200717 if (!intel_display_power_is_enabled(dev_priv,
Paulo Zanoni22c59962014-08-08 17:45:32 -0300718 POWER_DOMAIN_PIPE(pipe))) {
719 seq_printf(m, "Pipe %c power disabled\n",
720 pipe_name(pipe));
721 continue;
722 }
Ben Widawskya123f152013-11-02 21:07:10 -0700723 seq_printf(m, "Pipe %c IMR:\t%08x\n",
Damien Lespiau07d27e22014-03-03 17:31:46 +0000724 pipe_name(pipe),
725 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
Ben Widawskya123f152013-11-02 21:07:10 -0700726 seq_printf(m, "Pipe %c IIR:\t%08x\n",
Damien Lespiau07d27e22014-03-03 17:31:46 +0000727 pipe_name(pipe),
728 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
Ben Widawskya123f152013-11-02 21:07:10 -0700729 seq_printf(m, "Pipe %c IER:\t%08x\n",
Damien Lespiau07d27e22014-03-03 17:31:46 +0000730 pipe_name(pipe),
731 I915_READ(GEN8_DE_PIPE_IER(pipe)));
Ben Widawskya123f152013-11-02 21:07:10 -0700732 }
733
734 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
735 I915_READ(GEN8_DE_PORT_IMR));
736 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
737 I915_READ(GEN8_DE_PORT_IIR));
738 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
739 I915_READ(GEN8_DE_PORT_IER));
740
741 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
742 I915_READ(GEN8_DE_MISC_IMR));
743 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
744 I915_READ(GEN8_DE_MISC_IIR));
745 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
746 I915_READ(GEN8_DE_MISC_IER));
747
748 seq_printf(m, "PCU interrupt mask:\t%08x\n",
749 I915_READ(GEN8_PCU_IMR));
750 seq_printf(m, "PCU interrupt identity:\t%08x\n",
751 I915_READ(GEN8_PCU_IIR));
752 seq_printf(m, "PCU interrupt enable:\t%08x\n",
753 I915_READ(GEN8_PCU_IER));
754 } else if (IS_VALLEYVIEW(dev)) {
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700755 seq_printf(m, "Display IER:\t%08x\n",
756 I915_READ(VLV_IER));
757 seq_printf(m, "Display IIR:\t%08x\n",
758 I915_READ(VLV_IIR));
759 seq_printf(m, "Display IIR_RW:\t%08x\n",
760 I915_READ(VLV_IIR_RW));
761 seq_printf(m, "Display IMR:\t%08x\n",
762 I915_READ(VLV_IMR));
Damien Lespiau055e3932014-08-18 13:49:10 +0100763 for_each_pipe(dev_priv, pipe)
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700764 seq_printf(m, "Pipe %c stat:\t%08x\n",
765 pipe_name(pipe),
766 I915_READ(PIPESTAT(pipe)));
767
768 seq_printf(m, "Master IER:\t%08x\n",
769 I915_READ(VLV_MASTER_IER));
770
771 seq_printf(m, "Render IER:\t%08x\n",
772 I915_READ(GTIER));
773 seq_printf(m, "Render IIR:\t%08x\n",
774 I915_READ(GTIIR));
775 seq_printf(m, "Render IMR:\t%08x\n",
776 I915_READ(GTIMR));
777
778 seq_printf(m, "PM IER:\t\t%08x\n",
779 I915_READ(GEN6_PMIER));
780 seq_printf(m, "PM IIR:\t\t%08x\n",
781 I915_READ(GEN6_PMIIR));
782 seq_printf(m, "PM IMR:\t\t%08x\n",
783 I915_READ(GEN6_PMIMR));
784
785 seq_printf(m, "Port hotplug:\t%08x\n",
786 I915_READ(PORT_HOTPLUG_EN));
787 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
788 I915_READ(VLV_DPFLIPSTAT));
789 seq_printf(m, "DPINVGTT:\t%08x\n",
790 I915_READ(DPINVGTT));
791
792 } else if (!HAS_PCH_SPLIT(dev)) {
Zhenyu Wang5f6a1692009-08-10 21:37:24 +0800793 seq_printf(m, "Interrupt enable: %08x\n",
794 I915_READ(IER));
795 seq_printf(m, "Interrupt identity: %08x\n",
796 I915_READ(IIR));
797 seq_printf(m, "Interrupt mask: %08x\n",
798 I915_READ(IMR));
Damien Lespiau055e3932014-08-18 13:49:10 +0100799 for_each_pipe(dev_priv, pipe)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800800 seq_printf(m, "Pipe %c stat: %08x\n",
801 pipe_name(pipe),
802 I915_READ(PIPESTAT(pipe)));
Zhenyu Wang5f6a1692009-08-10 21:37:24 +0800803 } else {
804 seq_printf(m, "North Display Interrupt enable: %08x\n",
805 I915_READ(DEIER));
806 seq_printf(m, "North Display Interrupt identity: %08x\n",
807 I915_READ(DEIIR));
808 seq_printf(m, "North Display Interrupt mask: %08x\n",
809 I915_READ(DEIMR));
810 seq_printf(m, "South Display Interrupt enable: %08x\n",
811 I915_READ(SDEIER));
812 seq_printf(m, "South Display Interrupt identity: %08x\n",
813 I915_READ(SDEIIR));
814 seq_printf(m, "South Display Interrupt mask: %08x\n",
815 I915_READ(SDEIMR));
816 seq_printf(m, "Graphics Interrupt enable: %08x\n",
817 I915_READ(GTIER));
818 seq_printf(m, "Graphics Interrupt identity: %08x\n",
819 I915_READ(GTIIR));
820 seq_printf(m, "Graphics Interrupt mask: %08x\n",
821 I915_READ(GTIMR));
822 }
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100823 for_each_ring(ring, dev_priv, i) {
Ben Widawskya123f152013-11-02 21:07:10 -0700824 if (INTEL_INFO(dev)->gen >= 6) {
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100825 seq_printf(m,
826 "Graphics Interrupt mask (%s): %08x\n",
827 ring->name, I915_READ_IMR(ring));
Chris Wilson9862e602011-01-04 22:22:17 +0000828 }
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100829 i915_ring_seqno_info(m, ring);
Chris Wilson9862e602011-01-04 22:22:17 +0000830 }
Paulo Zanonic8c8fb32013-11-27 18:21:54 -0200831 intel_runtime_pm_put(dev_priv);
Chris Wilsonde227ef2010-07-03 07:58:38 +0100832 mutex_unlock(&dev->struct_mutex);
833
Ben Gamari20172632009-02-17 20:08:50 -0500834 return 0;
835}
836
Chris Wilsona6172a82009-02-11 14:26:38 +0000837static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
838{
Damien Lespiau9f25d002014-05-13 15:30:28 +0100839 struct drm_info_node *node = m->private;
Chris Wilsona6172a82009-02-11 14:26:38 +0000840 struct drm_device *dev = node->minor->dev;
Jani Nikulae277a1f2014-03-31 14:27:14 +0300841 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonde227ef2010-07-03 07:58:38 +0100842 int i, ret;
843
844 ret = mutex_lock_interruptible(&dev->struct_mutex);
845 if (ret)
846 return ret;
Chris Wilsona6172a82009-02-11 14:26:38 +0000847
848 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
849 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
850 for (i = 0; i < dev_priv->num_fence_regs; i++) {
Chris Wilson05394f32010-11-08 19:18:58 +0000851 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
Chris Wilsona6172a82009-02-11 14:26:38 +0000852
Chris Wilson6c085a72012-08-20 11:40:46 +0200853 seq_printf(m, "Fence %d, pin count = %d, object = ",
854 i, dev_priv->fence_regs[i].pin_count);
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100855 if (obj == NULL)
Damien Lespiau267f0c92013-06-24 22:59:48 +0100856 seq_puts(m, "unused");
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100857 else
Chris Wilson05394f32010-11-08 19:18:58 +0000858 describe_obj(m, obj);
Damien Lespiau267f0c92013-06-24 22:59:48 +0100859 seq_putc(m, '\n');
Chris Wilsona6172a82009-02-11 14:26:38 +0000860 }
861
Chris Wilson05394f32010-11-08 19:18:58 +0000862 mutex_unlock(&dev->struct_mutex);
Chris Wilsona6172a82009-02-11 14:26:38 +0000863 return 0;
864}
865
Ben Gamari20172632009-02-17 20:08:50 -0500866static int i915_hws_info(struct seq_file *m, void *data)
867{
Damien Lespiau9f25d002014-05-13 15:30:28 +0100868 struct drm_info_node *node = m->private;
Ben Gamari20172632009-02-17 20:08:50 -0500869 struct drm_device *dev = node->minor->dev;
Jani Nikulae277a1f2014-03-31 14:27:14 +0300870 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +0100871 struct intel_engine_cs *ring;
Daniel Vetter1a240d42012-11-29 22:18:51 +0100872 const u32 *hws;
Chris Wilson4066c0a2010-10-29 21:00:54 +0100873 int i;
Ben Gamari20172632009-02-17 20:08:50 -0500874
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000875 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
Daniel Vetter1a240d42012-11-29 22:18:51 +0100876 hws = ring->status_page.page_addr;
Ben Gamari20172632009-02-17 20:08:50 -0500877 if (hws == NULL)
878 return 0;
879
880 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
881 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
882 i * 4,
883 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
884 }
885 return 0;
886}
887
Daniel Vetterd5442302012-04-27 15:17:40 +0200888static ssize_t
889i915_error_state_write(struct file *filp,
890 const char __user *ubuf,
891 size_t cnt,
892 loff_t *ppos)
893{
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300894 struct i915_error_state_file_priv *error_priv = filp->private_data;
Daniel Vetterd5442302012-04-27 15:17:40 +0200895 struct drm_device *dev = error_priv->dev;
Daniel Vetter22bcfc62012-08-09 15:07:02 +0200896 int ret;
Daniel Vetterd5442302012-04-27 15:17:40 +0200897
898 DRM_DEBUG_DRIVER("Resetting error state\n");
899
Daniel Vetter22bcfc62012-08-09 15:07:02 +0200900 ret = mutex_lock_interruptible(&dev->struct_mutex);
901 if (ret)
902 return ret;
903
Daniel Vetterd5442302012-04-27 15:17:40 +0200904 i915_destroy_error_state(dev);
905 mutex_unlock(&dev->struct_mutex);
906
907 return cnt;
908}
909
910static int i915_error_state_open(struct inode *inode, struct file *file)
911{
912 struct drm_device *dev = inode->i_private;
Daniel Vetterd5442302012-04-27 15:17:40 +0200913 struct i915_error_state_file_priv *error_priv;
Daniel Vetterd5442302012-04-27 15:17:40 +0200914
915 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
916 if (!error_priv)
917 return -ENOMEM;
918
919 error_priv->dev = dev;
920
Mika Kuoppala95d5bfb2013-06-06 15:18:40 +0300921 i915_error_state_get(dev, error_priv);
Daniel Vetterd5442302012-04-27 15:17:40 +0200922
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300923 file->private_data = error_priv;
924
925 return 0;
Daniel Vetterd5442302012-04-27 15:17:40 +0200926}
927
928static int i915_error_state_release(struct inode *inode, struct file *file)
929{
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300930 struct i915_error_state_file_priv *error_priv = file->private_data;
Daniel Vetterd5442302012-04-27 15:17:40 +0200931
Mika Kuoppala95d5bfb2013-06-06 15:18:40 +0300932 i915_error_state_put(error_priv);
Daniel Vetterd5442302012-04-27 15:17:40 +0200933 kfree(error_priv);
934
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300935 return 0;
936}
937
938static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
939 size_t count, loff_t *pos)
940{
941 struct i915_error_state_file_priv *error_priv = file->private_data;
942 struct drm_i915_error_state_buf error_str;
943 loff_t tmp_pos = 0;
944 ssize_t ret_count = 0;
Mika Kuoppala4dc955f2013-06-06 15:18:41 +0300945 int ret;
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300946
Chris Wilson0a4cd7c2014-08-22 14:41:39 +0100947 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
Mika Kuoppala4dc955f2013-06-06 15:18:41 +0300948 if (ret)
949 return ret;
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300950
Mika Kuoppalafc16b482013-06-06 15:18:39 +0300951 ret = i915_error_state_to_str(&error_str, error_priv);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300952 if (ret)
953 goto out;
954
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300955 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
956 error_str.buf,
957 error_str.bytes);
958
959 if (ret_count < 0)
960 ret = ret_count;
961 else
962 *pos = error_str.start + ret_count;
963out:
Mika Kuoppala4dc955f2013-06-06 15:18:41 +0300964 i915_error_state_buf_release(&error_str);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300965 return ret ?: ret_count;
Daniel Vetterd5442302012-04-27 15:17:40 +0200966}
967
968static const struct file_operations i915_error_state_fops = {
969 .owner = THIS_MODULE,
970 .open = i915_error_state_open,
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300971 .read = i915_error_state_read,
Daniel Vetterd5442302012-04-27 15:17:40 +0200972 .write = i915_error_state_write,
973 .llseek = default_llseek,
974 .release = i915_error_state_release,
975};
976
Kees Cook647416f2013-03-10 14:10:06 -0700977static int
978i915_next_seqno_get(void *data, u64 *val)
Mika Kuoppala40633212012-12-04 15:12:00 +0200979{
Kees Cook647416f2013-03-10 14:10:06 -0700980 struct drm_device *dev = data;
Jani Nikulae277a1f2014-03-31 14:27:14 +0300981 struct drm_i915_private *dev_priv = dev->dev_private;
Mika Kuoppala40633212012-12-04 15:12:00 +0200982 int ret;
983
984 ret = mutex_lock_interruptible(&dev->struct_mutex);
985 if (ret)
986 return ret;
987
Kees Cook647416f2013-03-10 14:10:06 -0700988 *val = dev_priv->next_seqno;
Mika Kuoppala40633212012-12-04 15:12:00 +0200989 mutex_unlock(&dev->struct_mutex);
990
Kees Cook647416f2013-03-10 14:10:06 -0700991 return 0;
Mika Kuoppala40633212012-12-04 15:12:00 +0200992}
993
Kees Cook647416f2013-03-10 14:10:06 -0700994static int
995i915_next_seqno_set(void *data, u64 val)
Mika Kuoppala40633212012-12-04 15:12:00 +0200996{
Kees Cook647416f2013-03-10 14:10:06 -0700997 struct drm_device *dev = data;
Mika Kuoppala40633212012-12-04 15:12:00 +0200998 int ret;
999
Mika Kuoppala40633212012-12-04 15:12:00 +02001000 ret = mutex_lock_interruptible(&dev->struct_mutex);
1001 if (ret)
1002 return ret;
1003
Mika Kuoppalae94fbaa2012-12-19 11:13:09 +02001004 ret = i915_gem_set_seqno(dev, val);
Mika Kuoppala40633212012-12-04 15:12:00 +02001005 mutex_unlock(&dev->struct_mutex);
1006
Kees Cook647416f2013-03-10 14:10:06 -07001007 return ret;
Mika Kuoppala40633212012-12-04 15:12:00 +02001008}
1009
Kees Cook647416f2013-03-10 14:10:06 -07001010DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1011 i915_next_seqno_get, i915_next_seqno_set,
Mika Kuoppala3a3b4f92013-04-12 12:10:05 +03001012 "0x%llx\n");
Mika Kuoppala40633212012-12-04 15:12:00 +02001013
Deepak Sadb4bd12014-03-31 11:30:02 +05301014static int i915_frequency_info(struct seq_file *m, void *unused)
Jesse Barnesf97108d2010-01-29 11:27:07 -08001015{
Damien Lespiau9f25d002014-05-13 15:30:28 +01001016 struct drm_info_node *node = m->private;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001017 struct drm_device *dev = node->minor->dev;
Jani Nikulae277a1f2014-03-31 14:27:14 +03001018 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001019 int ret = 0;
1020
1021 intel_runtime_pm_get(dev_priv);
Jesse Barnesf97108d2010-01-29 11:27:07 -08001022
Tom O'Rourke5c9669c2013-09-16 14:56:43 -07001023 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1024
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001025 if (IS_GEN5(dev)) {
1026 u16 rgvswctl = I915_READ16(MEMSWCTL);
1027 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1028
1029 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1030 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1031 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1032 MEMSTAT_VID_SHIFT);
1033 seq_printf(m, "Current P-state: %d\n",
1034 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
Tom O'Rourkedaa3afb2014-05-30 16:22:10 -07001035 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1036 IS_BROADWELL(dev)) {
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001037 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1038 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1039 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
Chris Wilson0d8f9492014-03-27 09:06:14 +00001040 u32 rpmodectl, rpinclimit, rpdeclimit;
Chris Wilson8e8c06c2013-08-26 19:51:01 -03001041 u32 rpstat, cagf, reqf;
Jesse Barnesccab5c82011-01-18 15:49:25 -08001042 u32 rpupei, rpcurup, rpprevup;
1043 u32 rpdownei, rpcurdown, rpprevdown;
Paulo Zanoni9dd3c602014-08-01 18:14:48 -03001044 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001045 int max_freq;
1046
1047 /* RPSTAT1 is in the GT power well */
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01001048 ret = mutex_lock_interruptible(&dev->struct_mutex);
1049 if (ret)
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001050 goto out;
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01001051
Deepak Sc8d9a592013-11-23 14:55:42 +05301052 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001053
Chris Wilson8e8c06c2013-08-26 19:51:01 -03001054 reqf = I915_READ(GEN6_RPNSWREQ);
1055 reqf &= ~GEN6_TURBO_DISABLE;
Tom O'Rourkedaa3afb2014-05-30 16:22:10 -07001056 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Chris Wilson8e8c06c2013-08-26 19:51:01 -03001057 reqf >>= 24;
1058 else
1059 reqf >>= 25;
1060 reqf *= GT_FREQUENCY_MULTIPLIER;
1061
Chris Wilson0d8f9492014-03-27 09:06:14 +00001062 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1063 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1064 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1065
Jesse Barnesccab5c82011-01-18 15:49:25 -08001066 rpstat = I915_READ(GEN6_RPSTAT1);
1067 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1068 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1069 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1070 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1071 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1072 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
Tom O'Rourkedaa3afb2014-05-30 16:22:10 -07001073 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Ben Widawskyf82855d2013-01-29 12:00:15 -08001074 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1075 else
1076 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1077 cagf *= GT_FREQUENCY_MULTIPLIER;
Jesse Barnesccab5c82011-01-18 15:49:25 -08001078
Deepak Sc8d9a592013-11-23 14:55:42 +05301079 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01001080 mutex_unlock(&dev->struct_mutex);
1081
Paulo Zanoni9dd3c602014-08-01 18:14:48 -03001082 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1083 pm_ier = I915_READ(GEN6_PMIER);
1084 pm_imr = I915_READ(GEN6_PMIMR);
1085 pm_isr = I915_READ(GEN6_PMISR);
1086 pm_iir = I915_READ(GEN6_PMIIR);
1087 pm_mask = I915_READ(GEN6_PMINTRMSK);
1088 } else {
1089 pm_ier = I915_READ(GEN8_GT_IER(2));
1090 pm_imr = I915_READ(GEN8_GT_IMR(2));
1091 pm_isr = I915_READ(GEN8_GT_ISR(2));
1092 pm_iir = I915_READ(GEN8_GT_IIR(2));
1093 pm_mask = I915_READ(GEN6_PMINTRMSK);
1094 }
Chris Wilson0d8f9492014-03-27 09:06:14 +00001095 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
Paulo Zanoni9dd3c602014-08-01 18:14:48 -03001096 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001097 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001098 seq_printf(m, "Render p-state ratio: %d\n",
1099 (gt_perf_status & 0xff00) >> 8);
1100 seq_printf(m, "Render p-state VID: %d\n",
1101 gt_perf_status & 0xff);
1102 seq_printf(m, "Render p-state limit: %d\n",
1103 rp_state_limits & 0xff);
Chris Wilson0d8f9492014-03-27 09:06:14 +00001104 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1105 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1106 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1107 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
Chris Wilson8e8c06c2013-08-26 19:51:01 -03001108 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
Ben Widawskyf82855d2013-01-29 12:00:15 -08001109 seq_printf(m, "CAGF: %dMHz\n", cagf);
Jesse Barnesccab5c82011-01-18 15:49:25 -08001110 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1111 GEN6_CURICONT_MASK);
1112 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1113 GEN6_CURBSYTAVG_MASK);
1114 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1115 GEN6_CURBSYTAVG_MASK);
1116 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1117 GEN6_CURIAVG_MASK);
1118 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1119 GEN6_CURBSYTAVG_MASK);
1120 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1121 GEN6_CURBSYTAVG_MASK);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001122
1123 max_freq = (rp_state_cap & 0xff0000) >> 16;
1124 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
Ben Widawskyc8735b02012-09-07 19:43:39 -07001125 max_freq * GT_FREQUENCY_MULTIPLIER);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001126
1127 max_freq = (rp_state_cap & 0xff00) >> 8;
1128 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
Ben Widawskyc8735b02012-09-07 19:43:39 -07001129 max_freq * GT_FREQUENCY_MULTIPLIER);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001130
1131 max_freq = rp_state_cap & 0xff;
1132 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
Ben Widawskyc8735b02012-09-07 19:43:39 -07001133 max_freq * GT_FREQUENCY_MULTIPLIER);
Ben Widawsky31c77382013-04-05 14:29:22 -07001134
1135 seq_printf(m, "Max overclocked frequency: %dMHz\n",
Ben Widawskyb39fb292014-03-19 18:31:11 -07001136 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
Jesse Barnes0a073b82013-04-17 15:54:58 -07001137 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjälä03af2042014-06-28 02:03:53 +03001138 u32 freq_sts;
Jesse Barnes0a073b82013-04-17 15:54:58 -07001139
Jesse Barnes259bd5d2013-04-22 15:59:30 -07001140 mutex_lock(&dev_priv->rps.hw_lock);
Jani Nikula64936252013-05-22 15:36:20 +03001141 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
Jesse Barnes0a073b82013-04-17 15:54:58 -07001142 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1143 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1144
Jesse Barnes0a073b82013-04-17 15:54:58 -07001145 seq_printf(m, "max GPU freq: %d MHz\n",
Deepak Sb2435c92014-07-17 14:21:14 +05301146 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq));
Jesse Barnes0a073b82013-04-17 15:54:58 -07001147
Jesse Barnes0a073b82013-04-17 15:54:58 -07001148 seq_printf(m, "min GPU freq: %d MHz\n",
Deepak Sb2435c92014-07-17 14:21:14 +05301149 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq));
Ville Syrjälä03af2042014-06-28 02:03:53 +03001150
1151 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
Deepak Sb2435c92014-07-17 14:21:14 +05301152 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
Jesse Barnes0a073b82013-04-17 15:54:58 -07001153
1154 seq_printf(m, "current GPU freq: %d MHz\n",
Ville Syrjälä2ec38152013-11-05 22:42:29 +02001155 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
Jesse Barnes259bd5d2013-04-22 15:59:30 -07001156 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001157 } else {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001158 seq_puts(m, "no P-state info available\n");
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001159 }
Jesse Barnesf97108d2010-01-29 11:27:07 -08001160
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001161out:
1162 intel_runtime_pm_put(dev_priv);
1163 return ret;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001164}
1165
Ben Widawsky4d855292011-12-12 19:34:16 -08001166static int ironlake_drpc_info(struct seq_file *m)
Jesse Barnesf97108d2010-01-29 11:27:07 -08001167{
Damien Lespiau9f25d002014-05-13 15:30:28 +01001168 struct drm_info_node *node = m->private;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001169 struct drm_device *dev = node->minor->dev;
Jani Nikulae277a1f2014-03-31 14:27:14 +03001170 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky616fdb52011-10-05 11:44:54 -07001171 u32 rgvmodectl, rstdbyctl;
1172 u16 crstandvid;
1173 int ret;
1174
1175 ret = mutex_lock_interruptible(&dev->struct_mutex);
1176 if (ret)
1177 return ret;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001178 intel_runtime_pm_get(dev_priv);
Ben Widawsky616fdb52011-10-05 11:44:54 -07001179
1180 rgvmodectl = I915_READ(MEMMODECTL);
1181 rstdbyctl = I915_READ(RSTDBYCTL);
1182 crstandvid = I915_READ16(CRSTANDVID);
1183
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001184 intel_runtime_pm_put(dev_priv);
Ben Widawsky616fdb52011-10-05 11:44:54 -07001185 mutex_unlock(&dev->struct_mutex);
Jesse Barnesf97108d2010-01-29 11:27:07 -08001186
1187 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1188 "yes" : "no");
1189 seq_printf(m, "Boost freq: %d\n",
1190 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1191 MEMMODE_BOOST_FREQ_SHIFT);
1192 seq_printf(m, "HW control enabled: %s\n",
1193 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1194 seq_printf(m, "SW control enabled: %s\n",
1195 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1196 seq_printf(m, "Gated voltage change: %s\n",
1197 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1198 seq_printf(m, "Starting frequency: P%d\n",
1199 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001200 seq_printf(m, "Max P-state: P%d\n",
Jesse Barnesf97108d2010-01-29 11:27:07 -08001201 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001202 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1203 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1204 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1205 seq_printf(m, "Render standby enabled: %s\n",
1206 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
Damien Lespiau267f0c92013-06-24 22:59:48 +01001207 seq_puts(m, "Current RS state: ");
Jesse Barnes88271da2011-01-05 12:01:24 -08001208 switch (rstdbyctl & RSX_STATUS_MASK) {
1209 case RSX_STATUS_ON:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001210 seq_puts(m, "on\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001211 break;
1212 case RSX_STATUS_RC1:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001213 seq_puts(m, "RC1\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001214 break;
1215 case RSX_STATUS_RC1E:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001216 seq_puts(m, "RC1E\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001217 break;
1218 case RSX_STATUS_RS1:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001219 seq_puts(m, "RS1\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001220 break;
1221 case RSX_STATUS_RS2:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001222 seq_puts(m, "RS2 (RC6)\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001223 break;
1224 case RSX_STATUS_RS3:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001225 seq_puts(m, "RC3 (RC6+)\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001226 break;
1227 default:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001228 seq_puts(m, "unknown\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001229 break;
1230 }
Jesse Barnesf97108d2010-01-29 11:27:07 -08001231
1232 return 0;
1233}
1234
Deepak S669ab5a2014-01-10 15:18:26 +05301235static int vlv_drpc_info(struct seq_file *m)
1236{
1237
Damien Lespiau9f25d002014-05-13 15:30:28 +01001238 struct drm_info_node *node = m->private;
Deepak S669ab5a2014-01-10 15:18:26 +05301239 struct drm_device *dev = node->minor->dev;
1240 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä6b312cd2014-11-19 20:07:42 +02001241 u32 rpmodectl1, rcctl1, pw_status;
Deepak S669ab5a2014-01-10 15:18:26 +05301242 unsigned fw_rendercount = 0, fw_mediacount = 0;
1243
Imre Deakd46c0512014-04-14 20:24:27 +03001244 intel_runtime_pm_get(dev_priv);
1245
Ville Syrjälä6b312cd2014-11-19 20:07:42 +02001246 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
Deepak S669ab5a2014-01-10 15:18:26 +05301247 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1248 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1249
Imre Deakd46c0512014-04-14 20:24:27 +03001250 intel_runtime_pm_put(dev_priv);
1251
Deepak S669ab5a2014-01-10 15:18:26 +05301252 seq_printf(m, "Video Turbo Mode: %s\n",
1253 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1254 seq_printf(m, "Turbo enabled: %s\n",
1255 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1256 seq_printf(m, "HW control enabled: %s\n",
1257 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1258 seq_printf(m, "SW control enabled: %s\n",
1259 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1260 GEN6_RP_MEDIA_SW_MODE));
1261 seq_printf(m, "RC6 Enabled: %s\n",
1262 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1263 GEN6_RC_CTL_EI_MODE(1))));
1264 seq_printf(m, "Render Power Well: %s\n",
Ville Syrjälä6b312cd2014-11-19 20:07:42 +02001265 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
Deepak S669ab5a2014-01-10 15:18:26 +05301266 seq_printf(m, "Media Power Well: %s\n",
Ville Syrjälä6b312cd2014-11-19 20:07:42 +02001267 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
Deepak S669ab5a2014-01-10 15:18:26 +05301268
Imre Deak9cc19be2014-04-14 20:24:24 +03001269 seq_printf(m, "Render RC6 residency since boot: %u\n",
1270 I915_READ(VLV_GT_RENDER_RC6));
1271 seq_printf(m, "Media RC6 residency since boot: %u\n",
1272 I915_READ(VLV_GT_MEDIA_RC6));
1273
Deepak S669ab5a2014-01-10 15:18:26 +05301274 spin_lock_irq(&dev_priv->uncore.lock);
1275 fw_rendercount = dev_priv->uncore.fw_rendercount;
1276 fw_mediacount = dev_priv->uncore.fw_mediacount;
1277 spin_unlock_irq(&dev_priv->uncore.lock);
1278
1279 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1280 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1281
1282
1283 return 0;
1284}
1285
1286
Ben Widawsky4d855292011-12-12 19:34:16 -08001287static int gen6_drpc_info(struct seq_file *m)
1288{
1289
Damien Lespiau9f25d002014-05-13 15:30:28 +01001290 struct drm_info_node *node = m->private;
Ben Widawsky4d855292011-12-12 19:34:16 -08001291 struct drm_device *dev = node->minor->dev;
1292 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskyecd8fae2012-09-26 10:34:02 -07001293 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
Daniel Vetter93b525d2012-01-25 13:52:43 +01001294 unsigned forcewake_count;
Damien Lespiauaee56cf2013-06-24 22:59:49 +01001295 int count = 0, ret;
Ben Widawsky4d855292011-12-12 19:34:16 -08001296
1297 ret = mutex_lock_interruptible(&dev->struct_mutex);
1298 if (ret)
1299 return ret;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001300 intel_runtime_pm_get(dev_priv);
Ben Widawsky4d855292011-12-12 19:34:16 -08001301
Chris Wilson907b28c2013-07-19 20:36:52 +01001302 spin_lock_irq(&dev_priv->uncore.lock);
1303 forcewake_count = dev_priv->uncore.forcewake_count;
1304 spin_unlock_irq(&dev_priv->uncore.lock);
Daniel Vetter93b525d2012-01-25 13:52:43 +01001305
1306 if (forcewake_count) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001307 seq_puts(m, "RC information inaccurate because somebody "
1308 "holds a forcewake reference \n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001309 } else {
1310 /* NB: we cannot use forcewake, else we read the wrong values */
1311 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1312 udelay(10);
1313 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1314 }
1315
1316 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
Chris Wilsoned71f1b2013-07-19 20:36:56 +01001317 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
Ben Widawsky4d855292011-12-12 19:34:16 -08001318
1319 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1320 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1321 mutex_unlock(&dev->struct_mutex);
Ben Widawsky44cbd332012-11-06 14:36:36 +00001322 mutex_lock(&dev_priv->rps.hw_lock);
1323 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1324 mutex_unlock(&dev_priv->rps.hw_lock);
Ben Widawsky4d855292011-12-12 19:34:16 -08001325
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001326 intel_runtime_pm_put(dev_priv);
1327
Ben Widawsky4d855292011-12-12 19:34:16 -08001328 seq_printf(m, "Video Turbo Mode: %s\n",
1329 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1330 seq_printf(m, "HW control enabled: %s\n",
1331 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1332 seq_printf(m, "SW control enabled: %s\n",
1333 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1334 GEN6_RP_MEDIA_SW_MODE));
Eric Anholtfff24e22012-01-23 16:14:05 -08001335 seq_printf(m, "RC1e Enabled: %s\n",
Ben Widawsky4d855292011-12-12 19:34:16 -08001336 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1337 seq_printf(m, "RC6 Enabled: %s\n",
1338 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1339 seq_printf(m, "Deep RC6 Enabled: %s\n",
1340 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1341 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1342 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
Damien Lespiau267f0c92013-06-24 22:59:48 +01001343 seq_puts(m, "Current RC state: ");
Ben Widawsky4d855292011-12-12 19:34:16 -08001344 switch (gt_core_status & GEN6_RCn_MASK) {
1345 case GEN6_RC0:
1346 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
Damien Lespiau267f0c92013-06-24 22:59:48 +01001347 seq_puts(m, "Core Power Down\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001348 else
Damien Lespiau267f0c92013-06-24 22:59:48 +01001349 seq_puts(m, "on\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001350 break;
1351 case GEN6_RC3:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001352 seq_puts(m, "RC3\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001353 break;
1354 case GEN6_RC6:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001355 seq_puts(m, "RC6\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001356 break;
1357 case GEN6_RC7:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001358 seq_puts(m, "RC7\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001359 break;
1360 default:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001361 seq_puts(m, "Unknown\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001362 break;
1363 }
1364
1365 seq_printf(m, "Core Power Down: %s\n",
1366 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
Ben Widawskycce66a22012-03-27 18:59:38 -07001367
1368 /* Not exactly sure what this is */
1369 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1370 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1371 seq_printf(m, "RC6 residency since boot: %u\n",
1372 I915_READ(GEN6_GT_GFX_RC6));
1373 seq_printf(m, "RC6+ residency since boot: %u\n",
1374 I915_READ(GEN6_GT_GFX_RC6p));
1375 seq_printf(m, "RC6++ residency since boot: %u\n",
1376 I915_READ(GEN6_GT_GFX_RC6pp));
1377
Ben Widawskyecd8fae2012-09-26 10:34:02 -07001378 seq_printf(m, "RC6 voltage: %dmV\n",
1379 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1380 seq_printf(m, "RC6+ voltage: %dmV\n",
1381 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1382 seq_printf(m, "RC6++ voltage: %dmV\n",
1383 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
Ben Widawsky4d855292011-12-12 19:34:16 -08001384 return 0;
1385}
1386
1387static int i915_drpc_info(struct seq_file *m, void *unused)
1388{
Damien Lespiau9f25d002014-05-13 15:30:28 +01001389 struct drm_info_node *node = m->private;
Ben Widawsky4d855292011-12-12 19:34:16 -08001390 struct drm_device *dev = node->minor->dev;
1391
Deepak S669ab5a2014-01-10 15:18:26 +05301392 if (IS_VALLEYVIEW(dev))
1393 return vlv_drpc_info(m);
Vedang Patelac66cf42014-08-26 10:42:51 -07001394 else if (INTEL_INFO(dev)->gen >= 6)
Ben Widawsky4d855292011-12-12 19:34:16 -08001395 return gen6_drpc_info(m);
1396 else
1397 return ironlake_drpc_info(m);
1398}
1399
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001400static int i915_fbc_status(struct seq_file *m, void *unused)
1401{
Damien Lespiau9f25d002014-05-13 15:30:28 +01001402 struct drm_info_node *node = m->private;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001403 struct drm_device *dev = node->minor->dev;
Jani Nikulae277a1f2014-03-31 14:27:14 +03001404 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001405
Daniel Vetter3a77c4c2014-01-10 08:50:12 +01001406 if (!HAS_FBC(dev)) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001407 seq_puts(m, "FBC unsupported on this chipset\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001408 return 0;
1409 }
1410
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001411 intel_runtime_pm_get(dev_priv);
1412
Adam Jacksonee5382a2010-04-23 11:17:39 -04001413 if (intel_fbc_enabled(dev)) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001414 seq_puts(m, "FBC enabled\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001415 } else {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001416 seq_puts(m, "FBC disabled: ");
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -07001417 switch (dev_priv->fbc.no_fbc_reason) {
Chris Wilson29ebf902013-07-27 17:23:55 +01001418 case FBC_OK:
1419 seq_puts(m, "FBC actived, but currently disabled in hardware");
1420 break;
1421 case FBC_UNSUPPORTED:
1422 seq_puts(m, "unsupported by this chipset");
1423 break;
Chris Wilsonbed4a672010-09-11 10:47:47 +01001424 case FBC_NO_OUTPUT:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001425 seq_puts(m, "no outputs");
Chris Wilsonbed4a672010-09-11 10:47:47 +01001426 break;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001427 case FBC_STOLEN_TOO_SMALL:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001428 seq_puts(m, "not enough stolen memory");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001429 break;
1430 case FBC_UNSUPPORTED_MODE:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001431 seq_puts(m, "mode not supported");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001432 break;
1433 case FBC_MODE_TOO_LARGE:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001434 seq_puts(m, "mode too large");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001435 break;
1436 case FBC_BAD_PLANE:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001437 seq_puts(m, "FBC unsupported on plane");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001438 break;
1439 case FBC_NOT_TILED:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001440 seq_puts(m, "scanout buffer not tiled");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001441 break;
Jesse Barnes9c928d12010-07-23 15:20:00 -07001442 case FBC_MULTIPLE_PIPES:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001443 seq_puts(m, "multiple pipes are enabled");
Jesse Barnes9c928d12010-07-23 15:20:00 -07001444 break;
Jesse Barnesc1a9f042011-05-05 15:24:21 -07001445 case FBC_MODULE_PARAM:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001446 seq_puts(m, "disabled per module param (default off)");
Jesse Barnesc1a9f042011-05-05 15:24:21 -07001447 break;
Damien Lespiau8a5729a2013-06-24 16:22:02 +01001448 case FBC_CHIP_DEFAULT:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001449 seq_puts(m, "disabled per chip default");
Damien Lespiau8a5729a2013-06-24 16:22:02 +01001450 break;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001451 default:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001452 seq_puts(m, "unknown reason");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001453 }
Damien Lespiau267f0c92013-06-24 22:59:48 +01001454 seq_putc(m, '\n');
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001455 }
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001456
1457 intel_runtime_pm_put(dev_priv);
1458
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001459 return 0;
1460}
1461
Rodrigo Vivida46f932014-08-01 02:04:45 -07001462static int i915_fbc_fc_get(void *data, u64 *val)
1463{
1464 struct drm_device *dev = data;
1465 struct drm_i915_private *dev_priv = dev->dev_private;
1466
1467 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1468 return -ENODEV;
1469
1470 drm_modeset_lock_all(dev);
1471 *val = dev_priv->fbc.false_color;
1472 drm_modeset_unlock_all(dev);
1473
1474 return 0;
1475}
1476
1477static int i915_fbc_fc_set(void *data, u64 val)
1478{
1479 struct drm_device *dev = data;
1480 struct drm_i915_private *dev_priv = dev->dev_private;
1481 u32 reg;
1482
1483 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1484 return -ENODEV;
1485
1486 drm_modeset_lock_all(dev);
1487
1488 reg = I915_READ(ILK_DPFC_CONTROL);
1489 dev_priv->fbc.false_color = val;
1490
1491 I915_WRITE(ILK_DPFC_CONTROL, val ?
1492 (reg | FBC_CTL_FALSE_COLOR) :
1493 (reg & ~FBC_CTL_FALSE_COLOR));
1494
1495 drm_modeset_unlock_all(dev);
1496 return 0;
1497}
1498
1499DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1500 i915_fbc_fc_get, i915_fbc_fc_set,
1501 "%llu\n");
1502
Paulo Zanoni92d44622013-05-31 16:33:24 -03001503static int i915_ips_status(struct seq_file *m, void *unused)
1504{
Damien Lespiau9f25d002014-05-13 15:30:28 +01001505 struct drm_info_node *node = m->private;
Paulo Zanoni92d44622013-05-31 16:33:24 -03001506 struct drm_device *dev = node->minor->dev;
1507 struct drm_i915_private *dev_priv = dev->dev_private;
1508
Damien Lespiauf5adf942013-06-24 18:29:34 +01001509 if (!HAS_IPS(dev)) {
Paulo Zanoni92d44622013-05-31 16:33:24 -03001510 seq_puts(m, "not supported\n");
1511 return 0;
1512 }
1513
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001514 intel_runtime_pm_get(dev_priv);
1515
Rodrigo Vivi0eaa53f2014-06-30 04:45:01 -07001516 seq_printf(m, "Enabled by kernel parameter: %s\n",
1517 yesno(i915.enable_ips));
1518
1519 if (INTEL_INFO(dev)->gen >= 8) {
1520 seq_puts(m, "Currently: unknown\n");
1521 } else {
1522 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1523 seq_puts(m, "Currently: enabled\n");
1524 else
1525 seq_puts(m, "Currently: disabled\n");
1526 }
Paulo Zanoni92d44622013-05-31 16:33:24 -03001527
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001528 intel_runtime_pm_put(dev_priv);
1529
Paulo Zanoni92d44622013-05-31 16:33:24 -03001530 return 0;
1531}
1532
Jesse Barnes4a9bef32010-02-05 12:47:35 -08001533static int i915_sr_status(struct seq_file *m, void *unused)
1534{
Damien Lespiau9f25d002014-05-13 15:30:28 +01001535 struct drm_info_node *node = m->private;
Jesse Barnes4a9bef32010-02-05 12:47:35 -08001536 struct drm_device *dev = node->minor->dev;
Jani Nikulae277a1f2014-03-31 14:27:14 +03001537 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes4a9bef32010-02-05 12:47:35 -08001538 bool sr_enabled = false;
1539
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001540 intel_runtime_pm_get(dev_priv);
1541
Yuanhan Liu13982612010-12-15 15:42:31 +08001542 if (HAS_PCH_SPLIT(dev))
Chris Wilson5ba2aaa2010-08-19 18:04:08 +01001543 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001544 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
Jesse Barnes4a9bef32010-02-05 12:47:35 -08001545 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1546 else if (IS_I915GM(dev))
1547 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1548 else if (IS_PINEVIEW(dev))
1549 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1550
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001551 intel_runtime_pm_put(dev_priv);
1552
Chris Wilson5ba2aaa2010-08-19 18:04:08 +01001553 seq_printf(m, "self-refresh: %s\n",
1554 sr_enabled ? "enabled" : "disabled");
Jesse Barnes4a9bef32010-02-05 12:47:35 -08001555
1556 return 0;
1557}
1558
Jesse Barnes7648fa92010-05-20 14:28:11 -07001559static int i915_emon_status(struct seq_file *m, void *unused)
1560{
Damien Lespiau9f25d002014-05-13 15:30:28 +01001561 struct drm_info_node *node = m->private;
Jesse Barnes7648fa92010-05-20 14:28:11 -07001562 struct drm_device *dev = node->minor->dev;
Jani Nikulae277a1f2014-03-31 14:27:14 +03001563 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7648fa92010-05-20 14:28:11 -07001564 unsigned long temp, chipset, gfx;
Chris Wilsonde227ef2010-07-03 07:58:38 +01001565 int ret;
1566
Chris Wilson582be6b2012-04-30 19:35:02 +01001567 if (!IS_GEN5(dev))
1568 return -ENODEV;
1569
Chris Wilsonde227ef2010-07-03 07:58:38 +01001570 ret = mutex_lock_interruptible(&dev->struct_mutex);
1571 if (ret)
1572 return ret;
Jesse Barnes7648fa92010-05-20 14:28:11 -07001573
1574 temp = i915_mch_val(dev_priv);
1575 chipset = i915_chipset_val(dev_priv);
1576 gfx = i915_gfx_val(dev_priv);
Chris Wilsonde227ef2010-07-03 07:58:38 +01001577 mutex_unlock(&dev->struct_mutex);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001578
1579 seq_printf(m, "GMCH temp: %ld\n", temp);
1580 seq_printf(m, "Chipset power: %ld\n", chipset);
1581 seq_printf(m, "GFX power: %ld\n", gfx);
1582 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1583
1584 return 0;
1585}
1586
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001587static int i915_ring_freq_table(struct seq_file *m, void *unused)
1588{
Damien Lespiau9f25d002014-05-13 15:30:28 +01001589 struct drm_info_node *node = m->private;
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001590 struct drm_device *dev = node->minor->dev;
Jani Nikulae277a1f2014-03-31 14:27:14 +03001591 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni5bfa0192013-12-19 11:54:52 -02001592 int ret = 0;
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001593 int gpu_freq, ia_freq;
1594
Jesse Barnes1c70c0c2011-06-29 13:34:36 -07001595 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001596 seq_puts(m, "unsupported on this chipset\n");
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001597 return 0;
1598 }
1599
Paulo Zanoni5bfa0192013-12-19 11:54:52 -02001600 intel_runtime_pm_get(dev_priv);
1601
Tom O'Rourke5c9669c2013-09-16 14:56:43 -07001602 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1603
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001604 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001605 if (ret)
Paulo Zanoni5bfa0192013-12-19 11:54:52 -02001606 goto out;
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001607
Damien Lespiau267f0c92013-06-24 22:59:48 +01001608 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001609
Ben Widawskyb39fb292014-03-19 18:31:11 -07001610 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1611 gpu_freq <= dev_priv->rps.max_freq_softlimit;
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001612 gpu_freq++) {
Ben Widawsky42c05262012-09-26 10:34:00 -07001613 ia_freq = gpu_freq;
1614 sandybridge_pcode_read(dev_priv,
1615 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1616 &ia_freq);
Chris Wilson3ebecd02013-04-12 19:10:13 +01001617 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1618 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1619 ((ia_freq >> 0) & 0xff) * 100,
1620 ((ia_freq >> 8) & 0xff) * 100);
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001621 }
1622
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001623 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001624
Paulo Zanoni5bfa0192013-12-19 11:54:52 -02001625out:
1626 intel_runtime_pm_put(dev_priv);
1627 return ret;
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001628}
1629
Chris Wilson44834a62010-08-19 16:09:23 +01001630static int i915_opregion(struct seq_file *m, void *unused)
1631{
Damien Lespiau9f25d002014-05-13 15:30:28 +01001632 struct drm_info_node *node = m->private;
Chris Wilson44834a62010-08-19 16:09:23 +01001633 struct drm_device *dev = node->minor->dev;
Jani Nikulae277a1f2014-03-31 14:27:14 +03001634 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson44834a62010-08-19 16:09:23 +01001635 struct intel_opregion *opregion = &dev_priv->opregion;
Daniel Vetter0d38f002012-04-21 22:49:10 +02001636 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
Chris Wilson44834a62010-08-19 16:09:23 +01001637 int ret;
1638
Daniel Vetter0d38f002012-04-21 22:49:10 +02001639 if (data == NULL)
1640 return -ENOMEM;
1641
Chris Wilson44834a62010-08-19 16:09:23 +01001642 ret = mutex_lock_interruptible(&dev->struct_mutex);
1643 if (ret)
Daniel Vetter0d38f002012-04-21 22:49:10 +02001644 goto out;
Chris Wilson44834a62010-08-19 16:09:23 +01001645
Daniel Vetter0d38f002012-04-21 22:49:10 +02001646 if (opregion->header) {
1647 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1648 seq_write(m, data, OPREGION_SIZE);
1649 }
Chris Wilson44834a62010-08-19 16:09:23 +01001650
1651 mutex_unlock(&dev->struct_mutex);
1652
Daniel Vetter0d38f002012-04-21 22:49:10 +02001653out:
1654 kfree(data);
Chris Wilson44834a62010-08-19 16:09:23 +01001655 return 0;
1656}
1657
Chris Wilson37811fc2010-08-25 22:45:57 +01001658static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1659{
Damien Lespiau9f25d002014-05-13 15:30:28 +01001660 struct drm_info_node *node = m->private;
Chris Wilson37811fc2010-08-25 22:45:57 +01001661 struct drm_device *dev = node->minor->dev;
Daniel Vetter4520f532013-10-09 09:18:51 +02001662 struct intel_fbdev *ifbdev = NULL;
Chris Wilson37811fc2010-08-25 22:45:57 +01001663 struct intel_framebuffer *fb;
Chris Wilson37811fc2010-08-25 22:45:57 +01001664
Daniel Vetter4520f532013-10-09 09:18:51 +02001665#ifdef CONFIG_DRM_I915_FBDEV
1666 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson37811fc2010-08-25 22:45:57 +01001667
1668 ifbdev = dev_priv->fbdev;
1669 fb = to_intel_framebuffer(ifbdev->helper.fb);
1670
Daniel Vetter623f9782012-12-11 16:21:38 +01001671 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
Chris Wilson37811fc2010-08-25 22:45:57 +01001672 fb->base.width,
1673 fb->base.height,
1674 fb->base.depth,
Daniel Vetter623f9782012-12-11 16:21:38 +01001675 fb->base.bits_per_pixel,
1676 atomic_read(&fb->base.refcount.refcount));
Chris Wilson05394f32010-11-08 19:18:58 +00001677 describe_obj(m, fb->obj);
Damien Lespiau267f0c92013-06-24 22:59:48 +01001678 seq_putc(m, '\n');
Daniel Vetter4520f532013-10-09 09:18:51 +02001679#endif
Chris Wilson37811fc2010-08-25 22:45:57 +01001680
Daniel Vetter4b096ac2012-12-10 21:19:18 +01001681 mutex_lock(&dev->mode_config.fb_lock);
Chris Wilson37811fc2010-08-25 22:45:57 +01001682 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
Daniel Vetter131a56d2013-10-17 14:35:31 +02001683 if (ifbdev && &fb->base == ifbdev->helper.fb)
Chris Wilson37811fc2010-08-25 22:45:57 +01001684 continue;
1685
Daniel Vetter623f9782012-12-11 16:21:38 +01001686 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
Chris Wilson37811fc2010-08-25 22:45:57 +01001687 fb->base.width,
1688 fb->base.height,
1689 fb->base.depth,
Daniel Vetter623f9782012-12-11 16:21:38 +01001690 fb->base.bits_per_pixel,
1691 atomic_read(&fb->base.refcount.refcount));
Chris Wilson05394f32010-11-08 19:18:58 +00001692 describe_obj(m, fb->obj);
Damien Lespiau267f0c92013-06-24 22:59:48 +01001693 seq_putc(m, '\n');
Chris Wilson37811fc2010-08-25 22:45:57 +01001694 }
Daniel Vetter4b096ac2012-12-10 21:19:18 +01001695 mutex_unlock(&dev->mode_config.fb_lock);
Chris Wilson37811fc2010-08-25 22:45:57 +01001696
1697 return 0;
1698}
1699
Oscar Mateoc9fe99b2014-07-24 17:04:46 +01001700static void describe_ctx_ringbuf(struct seq_file *m,
1701 struct intel_ringbuffer *ringbuf)
1702{
1703 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1704 ringbuf->space, ringbuf->head, ringbuf->tail,
1705 ringbuf->last_retired_head);
1706}
1707
Ben Widawskye76d3632011-03-19 18:14:29 -07001708static int i915_context_status(struct seq_file *m, void *unused)
1709{
Damien Lespiau9f25d002014-05-13 15:30:28 +01001710 struct drm_info_node *node = m->private;
Ben Widawskye76d3632011-03-19 18:14:29 -07001711 struct drm_device *dev = node->minor->dev;
Jani Nikulae277a1f2014-03-31 14:27:14 +03001712 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01001713 struct intel_engine_cs *ring;
Oscar Mateo273497e2014-05-22 14:13:37 +01001714 struct intel_context *ctx;
Ben Widawskya168c292013-02-14 15:05:12 -08001715 int ret, i;
Ben Widawskye76d3632011-03-19 18:14:29 -07001716
Daniel Vetterf3d28872014-05-29 23:23:08 +02001717 ret = mutex_lock_interruptible(&dev->struct_mutex);
Ben Widawskye76d3632011-03-19 18:14:29 -07001718 if (ret)
1719 return ret;
1720
Daniel Vetter3e373942012-11-02 19:55:04 +01001721 if (dev_priv->ips.pwrctx) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001722 seq_puts(m, "power context ");
Daniel Vetter3e373942012-11-02 19:55:04 +01001723 describe_obj(m, dev_priv->ips.pwrctx);
Damien Lespiau267f0c92013-06-24 22:59:48 +01001724 seq_putc(m, '\n');
Ben Widawskydc501fb2011-06-29 11:41:51 -07001725 }
Ben Widawskye76d3632011-03-19 18:14:29 -07001726
Daniel Vetter3e373942012-11-02 19:55:04 +01001727 if (dev_priv->ips.renderctx) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001728 seq_puts(m, "render context ");
Daniel Vetter3e373942012-11-02 19:55:04 +01001729 describe_obj(m, dev_priv->ips.renderctx);
Damien Lespiau267f0c92013-06-24 22:59:48 +01001730 seq_putc(m, '\n');
Ben Widawskydc501fb2011-06-29 11:41:51 -07001731 }
Ben Widawskye76d3632011-03-19 18:14:29 -07001732
Ben Widawskya33afea2013-09-17 21:12:45 -07001733 list_for_each_entry(ctx, &dev_priv->context_list, link) {
Oscar Mateoc9fe99b2014-07-24 17:04:46 +01001734 if (!i915.enable_execlists &&
1735 ctx->legacy_hw_ctx.rcs_state == NULL)
Chris Wilsonb77f6992014-04-30 08:30:00 +01001736 continue;
1737
Ben Widawskya33afea2013-09-17 21:12:45 -07001738 seq_puts(m, "HW context ");
Ben Widawsky3ccfd192013-09-18 19:03:18 -07001739 describe_ctx(m, ctx);
Oscar Mateoc9fe99b2014-07-24 17:04:46 +01001740 for_each_ring(ring, dev_priv, i) {
Ben Widawskya33afea2013-09-17 21:12:45 -07001741 if (ring->default_context == ctx)
Oscar Mateoc9fe99b2014-07-24 17:04:46 +01001742 seq_printf(m, "(default context %s) ",
1743 ring->name);
1744 }
Ben Widawskya33afea2013-09-17 21:12:45 -07001745
Oscar Mateoc9fe99b2014-07-24 17:04:46 +01001746 if (i915.enable_execlists) {
1747 seq_putc(m, '\n');
1748 for_each_ring(ring, dev_priv, i) {
1749 struct drm_i915_gem_object *ctx_obj =
1750 ctx->engine[i].state;
1751 struct intel_ringbuffer *ringbuf =
1752 ctx->engine[i].ringbuf;
1753
1754 seq_printf(m, "%s: ", ring->name);
1755 if (ctx_obj)
1756 describe_obj(m, ctx_obj);
1757 if (ringbuf)
1758 describe_ctx_ringbuf(m, ringbuf);
1759 seq_putc(m, '\n');
1760 }
1761 } else {
1762 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1763 }
1764
Ben Widawskya33afea2013-09-17 21:12:45 -07001765 seq_putc(m, '\n');
Ben Widawskya168c292013-02-14 15:05:12 -08001766 }
1767
Daniel Vetterf3d28872014-05-29 23:23:08 +02001768 mutex_unlock(&dev->struct_mutex);
Ben Widawskye76d3632011-03-19 18:14:29 -07001769
1770 return 0;
1771}
1772
Thomas Daniel064ca1d2014-12-02 13:21:18 +00001773static void i915_dump_lrc_obj(struct seq_file *m,
1774 struct intel_engine_cs *ring,
1775 struct drm_i915_gem_object *ctx_obj)
1776{
1777 struct page *page;
1778 uint32_t *reg_state;
1779 int j;
1780 unsigned long ggtt_offset = 0;
1781
1782 if (ctx_obj == NULL) {
1783 seq_printf(m, "Context on %s with no gem object\n",
1784 ring->name);
1785 return;
1786 }
1787
1788 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1789 intel_execlists_ctx_id(ctx_obj));
1790
1791 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1792 seq_puts(m, "\tNot bound in GGTT\n");
1793 else
1794 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1795
1796 if (i915_gem_object_get_pages(ctx_obj)) {
1797 seq_puts(m, "\tFailed to get pages for context object\n");
1798 return;
1799 }
1800
1801 page = i915_gem_object_get_page(ctx_obj, 1);
1802 if (!WARN_ON(page == NULL)) {
1803 reg_state = kmap_atomic(page);
1804
1805 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1806 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1807 ggtt_offset + 4096 + (j * 4),
1808 reg_state[j], reg_state[j + 1],
1809 reg_state[j + 2], reg_state[j + 3]);
1810 }
1811 kunmap_atomic(reg_state);
1812 }
1813
1814 seq_putc(m, '\n');
1815}
1816
Ben Widawskyc0ab1ae2014-08-07 13:24:26 +01001817static int i915_dump_lrc(struct seq_file *m, void *unused)
1818{
1819 struct drm_info_node *node = (struct drm_info_node *) m->private;
1820 struct drm_device *dev = node->minor->dev;
1821 struct drm_i915_private *dev_priv = dev->dev_private;
1822 struct intel_engine_cs *ring;
1823 struct intel_context *ctx;
1824 int ret, i;
1825
1826 if (!i915.enable_execlists) {
1827 seq_printf(m, "Logical Ring Contexts are disabled\n");
1828 return 0;
1829 }
1830
1831 ret = mutex_lock_interruptible(&dev->struct_mutex);
1832 if (ret)
1833 return ret;
1834
1835 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1836 for_each_ring(ring, dev_priv, i) {
Thomas Daniel064ca1d2014-12-02 13:21:18 +00001837 if (ring->default_context != ctx)
1838 i915_dump_lrc_obj(m, ring,
1839 ctx->engine[i].state);
Ben Widawskyc0ab1ae2014-08-07 13:24:26 +01001840 }
1841 }
1842
1843 mutex_unlock(&dev->struct_mutex);
1844
1845 return 0;
1846}
1847
Oscar Mateo4ba70e42014-08-07 13:23:20 +01001848static int i915_execlists(struct seq_file *m, void *data)
1849{
1850 struct drm_info_node *node = (struct drm_info_node *)m->private;
1851 struct drm_device *dev = node->minor->dev;
1852 struct drm_i915_private *dev_priv = dev->dev_private;
1853 struct intel_engine_cs *ring;
1854 u32 status_pointer;
1855 u8 read_pointer;
1856 u8 write_pointer;
1857 u32 status;
1858 u32 ctx_id;
1859 struct list_head *cursor;
1860 int ring_id, i;
1861 int ret;
1862
1863 if (!i915.enable_execlists) {
1864 seq_puts(m, "Logical Ring Contexts are disabled\n");
1865 return 0;
1866 }
1867
1868 ret = mutex_lock_interruptible(&dev->struct_mutex);
1869 if (ret)
1870 return ret;
1871
Michel Thierryfc0412e2014-10-16 16:13:38 +01001872 intel_runtime_pm_get(dev_priv);
1873
Oscar Mateo4ba70e42014-08-07 13:23:20 +01001874 for_each_ring(ring, dev_priv, ring_id) {
1875 struct intel_ctx_submit_request *head_req = NULL;
1876 int count = 0;
1877 unsigned long flags;
1878
1879 seq_printf(m, "%s\n", ring->name);
1880
1881 status = I915_READ(RING_EXECLIST_STATUS(ring));
1882 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1883 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1884 status, ctx_id);
1885
1886 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1887 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1888
1889 read_pointer = ring->next_context_status_buffer;
1890 write_pointer = status_pointer & 0x07;
1891 if (read_pointer > write_pointer)
1892 write_pointer += 6;
1893 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1894 read_pointer, write_pointer);
1895
1896 for (i = 0; i < 6; i++) {
1897 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
1898 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
1899
1900 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
1901 i, status, ctx_id);
1902 }
1903
1904 spin_lock_irqsave(&ring->execlist_lock, flags);
1905 list_for_each(cursor, &ring->execlist_queue)
1906 count++;
1907 head_req = list_first_entry_or_null(&ring->execlist_queue,
1908 struct intel_ctx_submit_request, execlist_link);
1909 spin_unlock_irqrestore(&ring->execlist_lock, flags);
1910
1911 seq_printf(m, "\t%d requests in queue\n", count);
1912 if (head_req) {
1913 struct drm_i915_gem_object *ctx_obj;
1914
1915 ctx_obj = head_req->ctx->engine[ring_id].state;
1916 seq_printf(m, "\tHead request id: %u\n",
1917 intel_execlists_ctx_id(ctx_obj));
1918 seq_printf(m, "\tHead request tail: %u\n",
1919 head_req->tail);
1920 }
1921
1922 seq_putc(m, '\n');
1923 }
1924
Michel Thierryfc0412e2014-10-16 16:13:38 +01001925 intel_runtime_pm_put(dev_priv);
Oscar Mateo4ba70e42014-08-07 13:23:20 +01001926 mutex_unlock(&dev->struct_mutex);
1927
1928 return 0;
1929}
1930
Ben Widawsky6d794d42011-04-25 11:25:56 -07001931static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1932{
Damien Lespiau9f25d002014-05-13 15:30:28 +01001933 struct drm_info_node *node = m->private;
Ben Widawsky6d794d42011-04-25 11:25:56 -07001934 struct drm_device *dev = node->minor->dev;
1935 struct drm_i915_private *dev_priv = dev->dev_private;
Deepak S43709ba2013-11-23 14:55:44 +05301936 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
Ben Widawsky6d794d42011-04-25 11:25:56 -07001937
Chris Wilson907b28c2013-07-19 20:36:52 +01001938 spin_lock_irq(&dev_priv->uncore.lock);
Deepak S43709ba2013-11-23 14:55:44 +05301939 if (IS_VALLEYVIEW(dev)) {
1940 fw_rendercount = dev_priv->uncore.fw_rendercount;
1941 fw_mediacount = dev_priv->uncore.fw_mediacount;
1942 } else
1943 forcewake_count = dev_priv->uncore.forcewake_count;
Chris Wilson907b28c2013-07-19 20:36:52 +01001944 spin_unlock_irq(&dev_priv->uncore.lock);
Daniel Vetter9f1f46a2011-12-14 13:57:03 +01001945
Deepak S43709ba2013-11-23 14:55:44 +05301946 if (IS_VALLEYVIEW(dev)) {
1947 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1948 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1949 } else
1950 seq_printf(m, "forcewake count = %u\n", forcewake_count);
Ben Widawsky6d794d42011-04-25 11:25:56 -07001951
1952 return 0;
1953}
1954
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001955static const char *swizzle_string(unsigned swizzle)
1956{
Damien Lespiauaee56cf2013-06-24 22:59:49 +01001957 switch (swizzle) {
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001958 case I915_BIT_6_SWIZZLE_NONE:
1959 return "none";
1960 case I915_BIT_6_SWIZZLE_9:
1961 return "bit9";
1962 case I915_BIT_6_SWIZZLE_9_10:
1963 return "bit9/bit10";
1964 case I915_BIT_6_SWIZZLE_9_11:
1965 return "bit9/bit11";
1966 case I915_BIT_6_SWIZZLE_9_10_11:
1967 return "bit9/bit10/bit11";
1968 case I915_BIT_6_SWIZZLE_9_17:
1969 return "bit9/bit17";
1970 case I915_BIT_6_SWIZZLE_9_10_17:
1971 return "bit9/bit10/bit17";
1972 case I915_BIT_6_SWIZZLE_UNKNOWN:
Masanari Iida8a168ca2012-12-29 02:00:09 +09001973 return "unknown";
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001974 }
1975
1976 return "bug";
1977}
1978
1979static int i915_swizzle_info(struct seq_file *m, void *data)
1980{
Damien Lespiau9f25d002014-05-13 15:30:28 +01001981 struct drm_info_node *node = m->private;
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001982 struct drm_device *dev = node->minor->dev;
1983 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter22bcfc62012-08-09 15:07:02 +02001984 int ret;
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001985
Daniel Vetter22bcfc62012-08-09 15:07:02 +02001986 ret = mutex_lock_interruptible(&dev->struct_mutex);
1987 if (ret)
1988 return ret;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001989 intel_runtime_pm_get(dev_priv);
Daniel Vetter22bcfc62012-08-09 15:07:02 +02001990
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001991 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1992 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1993 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1994 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1995
1996 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1997 seq_printf(m, "DDC = 0x%08x\n",
1998 I915_READ(DCC));
Daniel Vetter656bfa32014-11-20 09:26:30 +01001999 seq_printf(m, "DDC2 = 0x%08x\n",
2000 I915_READ(DCC2));
Daniel Vetterea16a3c2011-12-14 13:57:16 +01002001 seq_printf(m, "C0DRB3 = 0x%04x\n",
2002 I915_READ16(C0DRB3));
2003 seq_printf(m, "C1DRB3 = 0x%04x\n",
2004 I915_READ16(C1DRB3));
Ben Widawsky9d3203e2013-11-02 21:07:14 -07002005 } else if (INTEL_INFO(dev)->gen >= 6) {
Daniel Vetter3fa7d232012-01-31 16:47:56 +01002006 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2007 I915_READ(MAD_DIMM_C0));
2008 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2009 I915_READ(MAD_DIMM_C1));
2010 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2011 I915_READ(MAD_DIMM_C2));
2012 seq_printf(m, "TILECTL = 0x%08x\n",
2013 I915_READ(TILECTL));
Robert Beckett5907f5f2014-01-23 14:23:14 +00002014 if (INTEL_INFO(dev)->gen >= 8)
Ben Widawsky9d3203e2013-11-02 21:07:14 -07002015 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2016 I915_READ(GAMTARBMODE));
2017 else
2018 seq_printf(m, "ARB_MODE = 0x%08x\n",
2019 I915_READ(ARB_MODE));
Daniel Vetter3fa7d232012-01-31 16:47:56 +01002020 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2021 I915_READ(DISP_ARB_CTL));
Daniel Vetterea16a3c2011-12-14 13:57:16 +01002022 }
Daniel Vetter656bfa32014-11-20 09:26:30 +01002023
2024 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2025 seq_puts(m, "L-shaped memory detected\n");
2026
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02002027 intel_runtime_pm_put(dev_priv);
Daniel Vetterea16a3c2011-12-14 13:57:16 +01002028 mutex_unlock(&dev->struct_mutex);
2029
2030 return 0;
2031}
2032
Ben Widawsky1c60fef2013-12-06 14:11:30 -08002033static int per_file_ctx(int id, void *ptr, void *data)
2034{
Oscar Mateo273497e2014-05-22 14:13:37 +01002035 struct intel_context *ctx = ptr;
Ben Widawsky1c60fef2013-12-06 14:11:30 -08002036 struct seq_file *m = data;
Daniel Vetterae6c4802014-08-06 15:04:53 +02002037 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2038
2039 if (!ppgtt) {
2040 seq_printf(m, " no ppgtt for context %d\n",
2041 ctx->user_handle);
2042 return 0;
2043 }
Ben Widawsky1c60fef2013-12-06 14:11:30 -08002044
Oscar Mateof83d6512014-05-22 14:13:38 +01002045 if (i915_gem_context_is_default(ctx))
2046 seq_puts(m, " default context:\n");
2047 else
Oscar Mateo821d66d2014-07-03 16:28:00 +01002048 seq_printf(m, " context %d:\n", ctx->user_handle);
Ben Widawsky1c60fef2013-12-06 14:11:30 -08002049 ppgtt->debug_dump(ppgtt, m);
2050
2051 return 0;
2052}
2053
Ben Widawsky77df6772013-11-02 21:07:30 -07002054static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01002055{
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01002056 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002057 struct intel_engine_cs *ring;
Ben Widawsky77df6772013-11-02 21:07:30 -07002058 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2059 int unused, i;
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01002060
Ben Widawsky77df6772013-11-02 21:07:30 -07002061 if (!ppgtt)
2062 return;
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01002063
Ben Widawsky77df6772013-11-02 21:07:30 -07002064 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
Ben Widawsky5abbcca2014-02-21 13:06:34 -08002065 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
Ben Widawsky77df6772013-11-02 21:07:30 -07002066 for_each_ring(ring, dev_priv, unused) {
2067 seq_printf(m, "%s\n", ring->name);
2068 for (i = 0; i < 4; i++) {
2069 u32 offset = 0x270 + i * 8;
2070 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2071 pdp <<= 32;
2072 pdp |= I915_READ(ring->mmio_base + offset);
Ville Syrjäläa2a5b152014-03-31 18:17:16 +03002073 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
Ben Widawsky77df6772013-11-02 21:07:30 -07002074 }
2075 }
2076}
2077
2078static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2079{
2080 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002081 struct intel_engine_cs *ring;
Ben Widawsky1c60fef2013-12-06 14:11:30 -08002082 struct drm_file *file;
Ben Widawsky77df6772013-11-02 21:07:30 -07002083 int i;
2084
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01002085 if (INTEL_INFO(dev)->gen == 6)
2086 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2087
Chris Wilsona2c7f6f2012-09-01 20:51:22 +01002088 for_each_ring(ring, dev_priv, i) {
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01002089 seq_printf(m, "%s\n", ring->name);
2090 if (INTEL_INFO(dev)->gen == 7)
2091 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2092 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2093 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2094 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2095 }
2096 if (dev_priv->mm.aliasing_ppgtt) {
2097 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2098
Damien Lespiau267f0c92013-06-24 22:59:48 +01002099 seq_puts(m, "aliasing PPGTT:\n");
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01002100 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
Ben Widawsky1c60fef2013-12-06 14:11:30 -08002101
Ben Widawsky87d60b62013-12-06 14:11:29 -08002102 ppgtt->debug_dump(ppgtt, m);
Daniel Vetterae6c4802014-08-06 15:04:53 +02002103 }
Ben Widawsky1c60fef2013-12-06 14:11:30 -08002104
2105 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2106 struct drm_i915_file_private *file_priv = file->driver_priv;
Ben Widawsky1c60fef2013-12-06 14:11:30 -08002107
Ben Widawsky1c60fef2013-12-06 14:11:30 -08002108 seq_printf(m, "proc: %s\n",
2109 get_pid_task(file->pid, PIDTYPE_PID)->comm);
Ben Widawsky1c60fef2013-12-06 14:11:30 -08002110 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01002111 }
2112 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
Ben Widawsky77df6772013-11-02 21:07:30 -07002113}
2114
2115static int i915_ppgtt_info(struct seq_file *m, void *data)
2116{
Damien Lespiau9f25d002014-05-13 15:30:28 +01002117 struct drm_info_node *node = m->private;
Ben Widawsky77df6772013-11-02 21:07:30 -07002118 struct drm_device *dev = node->minor->dev;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02002119 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky77df6772013-11-02 21:07:30 -07002120
2121 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2122 if (ret)
2123 return ret;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02002124 intel_runtime_pm_get(dev_priv);
Ben Widawsky77df6772013-11-02 21:07:30 -07002125
2126 if (INTEL_INFO(dev)->gen >= 8)
2127 gen8_ppgtt_info(m, dev);
2128 else if (INTEL_INFO(dev)->gen >= 6)
2129 gen6_ppgtt_info(m, dev);
2130
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02002131 intel_runtime_pm_put(dev_priv);
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01002132 mutex_unlock(&dev->struct_mutex);
2133
2134 return 0;
2135}
2136
Ben Widawsky63573eb2013-07-04 11:02:07 -07002137static int i915_llc(struct seq_file *m, void *data)
2138{
Damien Lespiau9f25d002014-05-13 15:30:28 +01002139 struct drm_info_node *node = m->private;
Ben Widawsky63573eb2013-07-04 11:02:07 -07002140 struct drm_device *dev = node->minor->dev;
2141 struct drm_i915_private *dev_priv = dev->dev_private;
2142
2143 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2144 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2145 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2146
2147 return 0;
2148}
2149
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002150static int i915_edp_psr_status(struct seq_file *m, void *data)
2151{
2152 struct drm_info_node *node = m->private;
2153 struct drm_device *dev = node->minor->dev;
2154 struct drm_i915_private *dev_priv = dev->dev_private;
Rodrigo Vivia031d702013-10-03 16:15:06 -03002155 u32 psrperf = 0;
Rodrigo Vivia6cbdb82014-11-14 08:52:40 -08002156 u32 stat[3];
2157 enum pipe pipe;
Rodrigo Vivia031d702013-10-03 16:15:06 -03002158 bool enabled = false;
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002159
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02002160 intel_runtime_pm_get(dev_priv);
2161
Daniel Vetterfa128fa2014-07-11 10:30:17 -07002162 mutex_lock(&dev_priv->psr.lock);
Rodrigo Vivia031d702013-10-03 16:15:06 -03002163 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2164 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
Daniel Vetter2807cf62014-07-11 10:30:11 -07002165 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
Rodrigo Vivi5755c782014-06-12 10:16:45 -07002166 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
Daniel Vetterfa128fa2014-07-11 10:30:17 -07002167 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2168 dev_priv->psr.busy_frontbuffer_bits);
2169 seq_printf(m, "Re-enable work scheduled: %s\n",
2170 yesno(work_busy(&dev_priv->psr.work.work)));
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002171
Rodrigo Vivia6cbdb82014-11-14 08:52:40 -08002172 if (HAS_PSR(dev)) {
2173 if (HAS_DDI(dev))
2174 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2175 else {
2176 for_each_pipe(dev_priv, pipe) {
2177 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2178 VLV_EDP_PSR_CURR_STATE_MASK;
2179 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2180 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2181 enabled = true;
2182 }
2183 }
2184 }
2185 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002186
Rodrigo Vivia6cbdb82014-11-14 08:52:40 -08002187 if (!HAS_DDI(dev))
2188 for_each_pipe(dev_priv, pipe) {
2189 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2190 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2191 seq_printf(m, " pipe %c", pipe_name(pipe));
2192 }
2193 seq_puts(m, "\n");
2194
2195 /* CHV PSR has no kind of performance counter */
2196 if (HAS_PSR(dev) && HAS_DDI(dev)) {
Rodrigo Vivia031d702013-10-03 16:15:06 -03002197 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2198 EDP_PSR_PERF_CNT_MASK;
Rodrigo Vivia6cbdb82014-11-14 08:52:40 -08002199
2200 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2201 }
Daniel Vetterfa128fa2014-07-11 10:30:17 -07002202 mutex_unlock(&dev_priv->psr.lock);
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002203
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02002204 intel_runtime_pm_put(dev_priv);
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002205 return 0;
2206}
2207
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02002208static int i915_sink_crc(struct seq_file *m, void *data)
2209{
2210 struct drm_info_node *node = m->private;
2211 struct drm_device *dev = node->minor->dev;
2212 struct intel_encoder *encoder;
2213 struct intel_connector *connector;
2214 struct intel_dp *intel_dp = NULL;
2215 int ret;
2216 u8 crc[6];
2217
2218 drm_modeset_lock_all(dev);
2219 list_for_each_entry(connector, &dev->mode_config.connector_list,
2220 base.head) {
2221
2222 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2223 continue;
2224
Paulo Zanonib6ae3c72014-02-13 17:51:33 -02002225 if (!connector->base.encoder)
2226 continue;
2227
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02002228 encoder = to_intel_encoder(connector->base.encoder);
2229 if (encoder->type != INTEL_OUTPUT_EDP)
2230 continue;
2231
2232 intel_dp = enc_to_intel_dp(&encoder->base);
2233
2234 ret = intel_dp_sink_crc(intel_dp, crc);
2235 if (ret)
2236 goto out;
2237
2238 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2239 crc[0], crc[1], crc[2],
2240 crc[3], crc[4], crc[5]);
2241 goto out;
2242 }
2243 ret = -ENODEV;
2244out:
2245 drm_modeset_unlock_all(dev);
2246 return ret;
2247}
2248
Jesse Barnesec013e72013-08-20 10:29:23 +01002249static int i915_energy_uJ(struct seq_file *m, void *data)
2250{
2251 struct drm_info_node *node = m->private;
2252 struct drm_device *dev = node->minor->dev;
2253 struct drm_i915_private *dev_priv = dev->dev_private;
2254 u64 power;
2255 u32 units;
2256
2257 if (INTEL_INFO(dev)->gen < 6)
2258 return -ENODEV;
2259
Paulo Zanoni36623ef2014-02-21 13:52:23 -03002260 intel_runtime_pm_get(dev_priv);
2261
Jesse Barnesec013e72013-08-20 10:29:23 +01002262 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2263 power = (power & 0x1f00) >> 8;
2264 units = 1000000 / (1 << power); /* convert to uJ */
2265 power = I915_READ(MCH_SECP_NRG_STTS);
2266 power *= units;
2267
Paulo Zanoni36623ef2014-02-21 13:52:23 -03002268 intel_runtime_pm_put(dev_priv);
2269
Jesse Barnesec013e72013-08-20 10:29:23 +01002270 seq_printf(m, "%llu", (long long unsigned)power);
Paulo Zanoni371db662013-08-19 13:18:10 -03002271
2272 return 0;
2273}
2274
2275static int i915_pc8_status(struct seq_file *m, void *unused)
2276{
Damien Lespiau9f25d002014-05-13 15:30:28 +01002277 struct drm_info_node *node = m->private;
Paulo Zanoni371db662013-08-19 13:18:10 -03002278 struct drm_device *dev = node->minor->dev;
2279 struct drm_i915_private *dev_priv = dev->dev_private;
2280
Zhenyu Wang85b8d5c2014-04-01 19:39:48 -03002281 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
Paulo Zanoni371db662013-08-19 13:18:10 -03002282 seq_puts(m, "not supported\n");
2283 return 0;
2284 }
2285
Paulo Zanoni86c4ec02014-02-21 13:52:24 -03002286 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
Paulo Zanoni371db662013-08-19 13:18:10 -03002287 seq_printf(m, "IRQs disabled: %s\n",
Jesse Barnes9df7575f2014-06-20 09:29:20 -07002288 yesno(!intel_irqs_enabled(dev_priv)));
Paulo Zanoni371db662013-08-19 13:18:10 -03002289
Jesse Barnesec013e72013-08-20 10:29:23 +01002290 return 0;
2291}
2292
Imre Deak1da51582013-11-25 17:15:35 +02002293static const char *power_domain_str(enum intel_display_power_domain domain)
2294{
2295 switch (domain) {
2296 case POWER_DOMAIN_PIPE_A:
2297 return "PIPE_A";
2298 case POWER_DOMAIN_PIPE_B:
2299 return "PIPE_B";
2300 case POWER_DOMAIN_PIPE_C:
2301 return "PIPE_C";
2302 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2303 return "PIPE_A_PANEL_FITTER";
2304 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2305 return "PIPE_B_PANEL_FITTER";
2306 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2307 return "PIPE_C_PANEL_FITTER";
2308 case POWER_DOMAIN_TRANSCODER_A:
2309 return "TRANSCODER_A";
2310 case POWER_DOMAIN_TRANSCODER_B:
2311 return "TRANSCODER_B";
2312 case POWER_DOMAIN_TRANSCODER_C:
2313 return "TRANSCODER_C";
2314 case POWER_DOMAIN_TRANSCODER_EDP:
2315 return "TRANSCODER_EDP";
Imre Deak319be8a2014-03-04 19:22:57 +02002316 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2317 return "PORT_DDI_A_2_LANES";
2318 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2319 return "PORT_DDI_A_4_LANES";
2320 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2321 return "PORT_DDI_B_2_LANES";
2322 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2323 return "PORT_DDI_B_4_LANES";
2324 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2325 return "PORT_DDI_C_2_LANES";
2326 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2327 return "PORT_DDI_C_4_LANES";
2328 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2329 return "PORT_DDI_D_2_LANES";
2330 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2331 return "PORT_DDI_D_4_LANES";
2332 case POWER_DOMAIN_PORT_DSI:
2333 return "PORT_DSI";
2334 case POWER_DOMAIN_PORT_CRT:
2335 return "PORT_CRT";
2336 case POWER_DOMAIN_PORT_OTHER:
2337 return "PORT_OTHER";
Imre Deak1da51582013-11-25 17:15:35 +02002338 case POWER_DOMAIN_VGA:
2339 return "VGA";
2340 case POWER_DOMAIN_AUDIO:
2341 return "AUDIO";
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -03002342 case POWER_DOMAIN_PLLS:
2343 return "PLLS";
Imre Deak1da51582013-11-25 17:15:35 +02002344 case POWER_DOMAIN_INIT:
2345 return "INIT";
2346 default:
2347 WARN_ON(1);
2348 return "?";
2349 }
2350}
2351
2352static int i915_power_domain_info(struct seq_file *m, void *unused)
2353{
Damien Lespiau9f25d002014-05-13 15:30:28 +01002354 struct drm_info_node *node = m->private;
Imre Deak1da51582013-11-25 17:15:35 +02002355 struct drm_device *dev = node->minor->dev;
2356 struct drm_i915_private *dev_priv = dev->dev_private;
2357 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2358 int i;
2359
2360 mutex_lock(&power_domains->lock);
2361
2362 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2363 for (i = 0; i < power_domains->power_well_count; i++) {
2364 struct i915_power_well *power_well;
2365 enum intel_display_power_domain power_domain;
2366
2367 power_well = &power_domains->power_wells[i];
2368 seq_printf(m, "%-25s %d\n", power_well->name,
2369 power_well->count);
2370
2371 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2372 power_domain++) {
2373 if (!(BIT(power_domain) & power_well->domains))
2374 continue;
2375
2376 seq_printf(m, " %-23s %d\n",
2377 power_domain_str(power_domain),
2378 power_domains->domain_use_count[power_domain]);
2379 }
2380 }
2381
2382 mutex_unlock(&power_domains->lock);
2383
2384 return 0;
2385}
2386
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002387static void intel_seq_print_mode(struct seq_file *m, int tabs,
2388 struct drm_display_mode *mode)
2389{
2390 int i;
2391
2392 for (i = 0; i < tabs; i++)
2393 seq_putc(m, '\t');
2394
2395 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2396 mode->base.id, mode->name,
2397 mode->vrefresh, mode->clock,
2398 mode->hdisplay, mode->hsync_start,
2399 mode->hsync_end, mode->htotal,
2400 mode->vdisplay, mode->vsync_start,
2401 mode->vsync_end, mode->vtotal,
2402 mode->type, mode->flags);
2403}
2404
2405static void intel_encoder_info(struct seq_file *m,
2406 struct intel_crtc *intel_crtc,
2407 struct intel_encoder *intel_encoder)
2408{
Damien Lespiau9f25d002014-05-13 15:30:28 +01002409 struct drm_info_node *node = m->private;
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002410 struct drm_device *dev = node->minor->dev;
2411 struct drm_crtc *crtc = &intel_crtc->base;
2412 struct intel_connector *intel_connector;
2413 struct drm_encoder *encoder;
2414
2415 encoder = &intel_encoder->base;
2416 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
Jani Nikula8e329a02014-06-03 14:56:21 +03002417 encoder->base.id, encoder->name);
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002418 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2419 struct drm_connector *connector = &intel_connector->base;
2420 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2421 connector->base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03002422 connector->name,
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002423 drm_get_connector_status_name(connector->status));
2424 if (connector->status == connector_status_connected) {
2425 struct drm_display_mode *mode = &crtc->mode;
2426 seq_printf(m, ", mode:\n");
2427 intel_seq_print_mode(m, 2, mode);
2428 } else {
2429 seq_putc(m, '\n');
2430 }
2431 }
2432}
2433
2434static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2435{
Damien Lespiau9f25d002014-05-13 15:30:28 +01002436 struct drm_info_node *node = m->private;
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002437 struct drm_device *dev = node->minor->dev;
2438 struct drm_crtc *crtc = &intel_crtc->base;
2439 struct intel_encoder *intel_encoder;
2440
Matt Roper5aa8a932014-06-16 10:12:55 -07002441 if (crtc->primary->fb)
2442 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2443 crtc->primary->fb->base.id, crtc->x, crtc->y,
2444 crtc->primary->fb->width, crtc->primary->fb->height);
2445 else
2446 seq_puts(m, "\tprimary plane disabled\n");
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002447 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2448 intel_encoder_info(m, intel_crtc, intel_encoder);
2449}
2450
2451static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2452{
2453 struct drm_display_mode *mode = panel->fixed_mode;
2454
2455 seq_printf(m, "\tfixed mode:\n");
2456 intel_seq_print_mode(m, 2, mode);
2457}
2458
2459static void intel_dp_info(struct seq_file *m,
2460 struct intel_connector *intel_connector)
2461{
2462 struct intel_encoder *intel_encoder = intel_connector->encoder;
2463 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2464
2465 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2466 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2467 "no");
2468 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2469 intel_panel_info(m, &intel_connector->panel);
2470}
2471
2472static void intel_hdmi_info(struct seq_file *m,
2473 struct intel_connector *intel_connector)
2474{
2475 struct intel_encoder *intel_encoder = intel_connector->encoder;
2476 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2477
2478 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2479 "no");
2480}
2481
2482static void intel_lvds_info(struct seq_file *m,
2483 struct intel_connector *intel_connector)
2484{
2485 intel_panel_info(m, &intel_connector->panel);
2486}
2487
2488static void intel_connector_info(struct seq_file *m,
2489 struct drm_connector *connector)
2490{
2491 struct intel_connector *intel_connector = to_intel_connector(connector);
2492 struct intel_encoder *intel_encoder = intel_connector->encoder;
Jesse Barnesf103fc72014-02-20 12:39:57 -08002493 struct drm_display_mode *mode;
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002494
2495 seq_printf(m, "connector %d: type %s, status: %s\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03002496 connector->base.id, connector->name,
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002497 drm_get_connector_status_name(connector->status));
2498 if (connector->status == connector_status_connected) {
2499 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2500 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2501 connector->display_info.width_mm,
2502 connector->display_info.height_mm);
2503 seq_printf(m, "\tsubpixel order: %s\n",
2504 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2505 seq_printf(m, "\tCEA rev: %d\n",
2506 connector->display_info.cea_rev);
2507 }
Dave Airlie36cd7442014-05-02 13:44:18 +10002508 if (intel_encoder) {
2509 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2510 intel_encoder->type == INTEL_OUTPUT_EDP)
2511 intel_dp_info(m, intel_connector);
2512 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2513 intel_hdmi_info(m, intel_connector);
2514 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2515 intel_lvds_info(m, intel_connector);
2516 }
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002517
Jesse Barnesf103fc72014-02-20 12:39:57 -08002518 seq_printf(m, "\tmodes:\n");
2519 list_for_each_entry(mode, &connector->modes, head)
2520 intel_seq_print_mode(m, 2, mode);
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002521}
2522
Chris Wilson065f2ec2014-03-12 09:13:13 +00002523static bool cursor_active(struct drm_device *dev, int pipe)
2524{
2525 struct drm_i915_private *dev_priv = dev->dev_private;
2526 u32 state;
2527
2528 if (IS_845G(dev) || IS_I865G(dev))
2529 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
Chris Wilson065f2ec2014-03-12 09:13:13 +00002530 else
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03002531 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
Chris Wilson065f2ec2014-03-12 09:13:13 +00002532
2533 return state;
2534}
2535
2536static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2537{
2538 struct drm_i915_private *dev_priv = dev->dev_private;
2539 u32 pos;
2540
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03002541 pos = I915_READ(CURPOS(pipe));
Chris Wilson065f2ec2014-03-12 09:13:13 +00002542
2543 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2544 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2545 *x = -*x;
2546
2547 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2548 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2549 *y = -*y;
2550
2551 return cursor_active(dev, pipe);
2552}
2553
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002554static int i915_display_info(struct seq_file *m, void *unused)
2555{
Damien Lespiau9f25d002014-05-13 15:30:28 +01002556 struct drm_info_node *node = m->private;
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002557 struct drm_device *dev = node->minor->dev;
Paulo Zanonib0e5ddf2014-04-01 14:55:10 -03002558 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson065f2ec2014-03-12 09:13:13 +00002559 struct intel_crtc *crtc;
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002560 struct drm_connector *connector;
2561
Paulo Zanonib0e5ddf2014-04-01 14:55:10 -03002562 intel_runtime_pm_get(dev_priv);
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002563 drm_modeset_lock_all(dev);
2564 seq_printf(m, "CRTC info\n");
2565 seq_printf(m, "---------\n");
Damien Lespiaud3fcc802014-05-13 23:32:22 +01002566 for_each_intel_crtc(dev, crtc) {
Chris Wilson065f2ec2014-03-12 09:13:13 +00002567 bool active;
2568 int x, y;
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002569
Chris Wilson57127ef2014-07-04 08:20:11 +01002570 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
Chris Wilson065f2ec2014-03-12 09:13:13 +00002571 crtc->base.base.id, pipe_name(crtc->pipe),
Chris Wilson57127ef2014-07-04 08:20:11 +01002572 yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
Paulo Zanonia23dc652014-04-01 14:55:11 -03002573 if (crtc->active) {
Chris Wilson065f2ec2014-03-12 09:13:13 +00002574 intel_crtc_info(m, crtc);
2575
Paulo Zanonia23dc652014-04-01 14:55:11 -03002576 active = cursor_position(dev, crtc->pipe, &x, &y);
Chris Wilson57127ef2014-07-04 08:20:11 +01002577 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
Chris Wilson4b0e3332014-05-30 16:35:26 +03002578 yesno(crtc->cursor_base),
Chris Wilson57127ef2014-07-04 08:20:11 +01002579 x, y, crtc->cursor_width, crtc->cursor_height,
2580 crtc->cursor_addr, yesno(active));
Paulo Zanonia23dc652014-04-01 14:55:11 -03002581 }
Daniel Vettercace8412014-05-22 17:56:31 +02002582
2583 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2584 yesno(!crtc->cpu_fifo_underrun_disabled),
2585 yesno(!crtc->pch_fifo_underrun_disabled));
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002586 }
2587
2588 seq_printf(m, "\n");
2589 seq_printf(m, "Connector info\n");
2590 seq_printf(m, "--------------\n");
2591 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2592 intel_connector_info(m, connector);
2593 }
2594 drm_modeset_unlock_all(dev);
Paulo Zanonib0e5ddf2014-04-01 14:55:10 -03002595 intel_runtime_pm_put(dev_priv);
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002596
2597 return 0;
2598}
2599
Ben Widawskye04934c2014-06-30 09:53:42 -07002600static int i915_semaphore_status(struct seq_file *m, void *unused)
2601{
2602 struct drm_info_node *node = (struct drm_info_node *) m->private;
2603 struct drm_device *dev = node->minor->dev;
2604 struct drm_i915_private *dev_priv = dev->dev_private;
2605 struct intel_engine_cs *ring;
2606 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2607 int i, j, ret;
2608
2609 if (!i915_semaphore_is_enabled(dev)) {
2610 seq_puts(m, "Semaphores are disabled\n");
2611 return 0;
2612 }
2613
2614 ret = mutex_lock_interruptible(&dev->struct_mutex);
2615 if (ret)
2616 return ret;
Paulo Zanoni03872062014-07-09 14:31:57 -03002617 intel_runtime_pm_get(dev_priv);
Ben Widawskye04934c2014-06-30 09:53:42 -07002618
2619 if (IS_BROADWELL(dev)) {
2620 struct page *page;
2621 uint64_t *seqno;
2622
2623 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2624
2625 seqno = (uint64_t *)kmap_atomic(page);
2626 for_each_ring(ring, dev_priv, i) {
2627 uint64_t offset;
2628
2629 seq_printf(m, "%s\n", ring->name);
2630
2631 seq_puts(m, " Last signal:");
2632 for (j = 0; j < num_rings; j++) {
2633 offset = i * I915_NUM_RINGS + j;
2634 seq_printf(m, "0x%08llx (0x%02llx) ",
2635 seqno[offset], offset * 8);
2636 }
2637 seq_putc(m, '\n');
2638
2639 seq_puts(m, " Last wait: ");
2640 for (j = 0; j < num_rings; j++) {
2641 offset = i + (j * I915_NUM_RINGS);
2642 seq_printf(m, "0x%08llx (0x%02llx) ",
2643 seqno[offset], offset * 8);
2644 }
2645 seq_putc(m, '\n');
2646
2647 }
2648 kunmap_atomic(seqno);
2649 } else {
2650 seq_puts(m, " Last signal:");
2651 for_each_ring(ring, dev_priv, i)
2652 for (j = 0; j < num_rings; j++)
2653 seq_printf(m, "0x%08x\n",
2654 I915_READ(ring->semaphore.mbox.signal[j]));
2655 seq_putc(m, '\n');
2656 }
2657
2658 seq_puts(m, "\nSync seqno:\n");
2659 for_each_ring(ring, dev_priv, i) {
2660 for (j = 0; j < num_rings; j++) {
2661 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2662 }
2663 seq_putc(m, '\n');
2664 }
2665 seq_putc(m, '\n');
2666
Paulo Zanoni03872062014-07-09 14:31:57 -03002667 intel_runtime_pm_put(dev_priv);
Ben Widawskye04934c2014-06-30 09:53:42 -07002668 mutex_unlock(&dev->struct_mutex);
2669 return 0;
2670}
2671
Daniel Vetter728e29d2014-06-25 22:01:53 +03002672static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2673{
2674 struct drm_info_node *node = (struct drm_info_node *) m->private;
2675 struct drm_device *dev = node->minor->dev;
2676 struct drm_i915_private *dev_priv = dev->dev_private;
2677 int i;
2678
2679 drm_modeset_lock_all(dev);
2680 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2681 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2682
2683 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +02002684 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02002685 pll->config.crtc_mask, pll->active, yesno(pll->on));
Daniel Vetter728e29d2014-06-25 22:01:53 +03002686 seq_printf(m, " tracked hardware state:\n");
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02002687 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2688 seq_printf(m, " dpll_md: 0x%08x\n",
2689 pll->config.hw_state.dpll_md);
2690 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2691 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2692 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
Daniel Vetter728e29d2014-06-25 22:01:53 +03002693 }
2694 drm_modeset_unlock_all(dev);
2695
2696 return 0;
2697}
2698
Damien Lespiau1ed1ef92014-08-30 16:50:59 +01002699static int i915_wa_registers(struct seq_file *m, void *unused)
Arun Siluvery888b5992014-08-26 14:44:51 +01002700{
2701 int i;
2702 int ret;
2703 struct drm_info_node *node = (struct drm_info_node *) m->private;
2704 struct drm_device *dev = node->minor->dev;
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706
Arun Siluvery888b5992014-08-26 14:44:51 +01002707 ret = mutex_lock_interruptible(&dev->struct_mutex);
2708 if (ret)
2709 return ret;
2710
2711 intel_runtime_pm_get(dev_priv);
2712
Mika Kuoppala72253422014-10-07 17:21:26 +03002713 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2714 for (i = 0; i < dev_priv->workarounds.count; ++i) {
Mika Kuoppala2fa60f62014-10-07 17:21:27 +03002715 u32 addr, mask, value, read;
2716 bool ok;
Arun Siluvery888b5992014-08-26 14:44:51 +01002717
Mika Kuoppala72253422014-10-07 17:21:26 +03002718 addr = dev_priv->workarounds.reg[i].addr;
2719 mask = dev_priv->workarounds.reg[i].mask;
Mika Kuoppala2fa60f62014-10-07 17:21:27 +03002720 value = dev_priv->workarounds.reg[i].value;
2721 read = I915_READ(addr);
2722 ok = (value & mask) == (read & mask);
2723 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2724 addr, value, mask, read, ok ? "OK" : "FAIL");
Arun Siluvery888b5992014-08-26 14:44:51 +01002725 }
2726
2727 intel_runtime_pm_put(dev_priv);
2728 mutex_unlock(&dev->struct_mutex);
2729
2730 return 0;
2731}
2732
Damien Lespiauc5511e42014-11-04 17:06:51 +00002733static int i915_ddb_info(struct seq_file *m, void *unused)
2734{
2735 struct drm_info_node *node = m->private;
2736 struct drm_device *dev = node->minor->dev;
2737 struct drm_i915_private *dev_priv = dev->dev_private;
2738 struct skl_ddb_allocation *ddb;
2739 struct skl_ddb_entry *entry;
2740 enum pipe pipe;
2741 int plane;
2742
2743 drm_modeset_lock_all(dev);
2744
2745 ddb = &dev_priv->wm.skl_hw.ddb;
2746
2747 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2748
2749 for_each_pipe(dev_priv, pipe) {
2750 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2751
2752 for_each_plane(pipe, plane) {
2753 entry = &ddb->plane[pipe][plane];
2754 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2755 entry->start, entry->end,
2756 skl_ddb_entry_size(entry));
2757 }
2758
2759 entry = &ddb->cursor[pipe];
2760 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2761 entry->end, skl_ddb_entry_size(entry));
2762 }
2763
2764 drm_modeset_unlock_all(dev);
2765
2766 return 0;
2767}
2768
Damien Lespiau07144422013-10-15 18:55:40 +01002769struct pipe_crc_info {
2770 const char *name;
2771 struct drm_device *dev;
2772 enum pipe pipe;
2773};
2774
Dave Airlie11bed9582014-05-12 15:22:27 +10002775static int i915_dp_mst_info(struct seq_file *m, void *unused)
2776{
2777 struct drm_info_node *node = (struct drm_info_node *) m->private;
2778 struct drm_device *dev = node->minor->dev;
2779 struct drm_encoder *encoder;
2780 struct intel_encoder *intel_encoder;
2781 struct intel_digital_port *intel_dig_port;
2782 drm_modeset_lock_all(dev);
2783 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2784 intel_encoder = to_intel_encoder(encoder);
2785 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2786 continue;
2787 intel_dig_port = enc_to_dig_port(encoder);
2788 if (!intel_dig_port->dp.can_mst)
2789 continue;
2790
2791 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2792 }
2793 drm_modeset_unlock_all(dev);
2794 return 0;
2795}
2796
Damien Lespiau07144422013-10-15 18:55:40 +01002797static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002798{
Damien Lespiaube5c7a92013-10-15 18:55:41 +01002799 struct pipe_crc_info *info = inode->i_private;
2800 struct drm_i915_private *dev_priv = info->dev->dev_private;
2801 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2802
Daniel Vetter7eb1c492013-11-14 11:30:43 +01002803 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2804 return -ENODEV;
2805
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002806 spin_lock_irq(&pipe_crc->lock);
2807
2808 if (pipe_crc->opened) {
2809 spin_unlock_irq(&pipe_crc->lock);
Damien Lespiaube5c7a92013-10-15 18:55:41 +01002810 return -EBUSY; /* already open */
2811 }
2812
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002813 pipe_crc->opened = true;
Damien Lespiau07144422013-10-15 18:55:40 +01002814 filep->private_data = inode->i_private;
2815
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002816 spin_unlock_irq(&pipe_crc->lock);
2817
Damien Lespiau07144422013-10-15 18:55:40 +01002818 return 0;
2819}
2820
2821static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2822{
Damien Lespiaube5c7a92013-10-15 18:55:41 +01002823 struct pipe_crc_info *info = inode->i_private;
2824 struct drm_i915_private *dev_priv = info->dev->dev_private;
2825 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2826
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002827 spin_lock_irq(&pipe_crc->lock);
2828 pipe_crc->opened = false;
2829 spin_unlock_irq(&pipe_crc->lock);
Damien Lespiaube5c7a92013-10-15 18:55:41 +01002830
Damien Lespiau07144422013-10-15 18:55:40 +01002831 return 0;
2832}
2833
2834/* (6 fields, 8 chars each, space separated (5) + '\n') */
2835#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2836/* account for \'0' */
2837#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2838
2839static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2840{
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002841 assert_spin_locked(&pipe_crc->lock);
2842 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2843 INTEL_PIPE_CRC_ENTRIES_NR);
Damien Lespiau07144422013-10-15 18:55:40 +01002844}
Shuang He8bf1e9f2013-10-15 18:55:27 +01002845
Damien Lespiau07144422013-10-15 18:55:40 +01002846static ssize_t
2847i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2848 loff_t *pos)
2849{
2850 struct pipe_crc_info *info = filep->private_data;
2851 struct drm_device *dev = info->dev;
2852 struct drm_i915_private *dev_priv = dev->dev_private;
2853 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2854 char buf[PIPE_CRC_BUFFER_LEN];
2855 int head, tail, n_entries, n;
2856 ssize_t bytes_read;
2857
2858 /*
2859 * Don't allow user space to provide buffers not big enough to hold
2860 * a line of data.
2861 */
2862 if (count < PIPE_CRC_LINE_LEN)
2863 return -EINVAL;
2864
2865 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2866 return 0;
2867
2868 /* nothing to read */
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002869 spin_lock_irq(&pipe_crc->lock);
Damien Lespiau07144422013-10-15 18:55:40 +01002870 while (pipe_crc_data_count(pipe_crc) == 0) {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002871 int ret;
Damien Lespiau07144422013-10-15 18:55:40 +01002872
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002873 if (filep->f_flags & O_NONBLOCK) {
2874 spin_unlock_irq(&pipe_crc->lock);
2875 return -EAGAIN;
2876 }
2877
2878 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2879 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2880 if (ret) {
2881 spin_unlock_irq(&pipe_crc->lock);
2882 return ret;
2883 }
Damien Lespiau07144422013-10-15 18:55:40 +01002884 }
2885
2886 /* We now have one or more entries to read */
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002887 head = pipe_crc->head;
2888 tail = pipe_crc->tail;
Damien Lespiau07144422013-10-15 18:55:40 +01002889 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2890 count / PIPE_CRC_LINE_LEN);
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002891 spin_unlock_irq(&pipe_crc->lock);
2892
Damien Lespiau07144422013-10-15 18:55:40 +01002893 bytes_read = 0;
2894 n = 0;
2895 do {
2896 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
2897 int ret;
2898
2899 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2900 "%8u %8x %8x %8x %8x %8x\n",
2901 entry->frame, entry->crc[0],
2902 entry->crc[1], entry->crc[2],
2903 entry->crc[3], entry->crc[4]);
2904
2905 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2906 buf, PIPE_CRC_LINE_LEN);
2907 if (ret == PIPE_CRC_LINE_LEN)
2908 return -EFAULT;
Damien Lespiaub2c88f52013-10-15 18:55:29 +01002909
2910 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2911 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
Damien Lespiau07144422013-10-15 18:55:40 +01002912 n++;
2913 } while (--n_entries);
Shuang He8bf1e9f2013-10-15 18:55:27 +01002914
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002915 spin_lock_irq(&pipe_crc->lock);
2916 pipe_crc->tail = tail;
2917 spin_unlock_irq(&pipe_crc->lock);
2918
Damien Lespiau07144422013-10-15 18:55:40 +01002919 return bytes_read;
2920}
2921
2922static const struct file_operations i915_pipe_crc_fops = {
2923 .owner = THIS_MODULE,
2924 .open = i915_pipe_crc_open,
2925 .read = i915_pipe_crc_read,
2926 .release = i915_pipe_crc_release,
2927};
2928
2929static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2930 {
2931 .name = "i915_pipe_A_crc",
2932 .pipe = PIPE_A,
2933 },
2934 {
2935 .name = "i915_pipe_B_crc",
2936 .pipe = PIPE_B,
2937 },
2938 {
2939 .name = "i915_pipe_C_crc",
2940 .pipe = PIPE_C,
2941 },
2942};
2943
2944static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2945 enum pipe pipe)
2946{
2947 struct drm_device *dev = minor->dev;
2948 struct dentry *ent;
2949 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2950
2951 info->dev = dev;
2952 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2953 &i915_pipe_crc_fops);
Wei Yongjunf3c5fe92013-12-16 14:13:25 +08002954 if (!ent)
2955 return -ENOMEM;
Damien Lespiau07144422013-10-15 18:55:40 +01002956
2957 return drm_add_fake_info_node(minor, ent, info);
Shuang He8bf1e9f2013-10-15 18:55:27 +01002958}
2959
Daniel Vettere8dfcf72013-10-16 11:51:54 +02002960static const char * const pipe_crc_sources[] = {
Daniel Vetter926321d2013-10-16 13:30:34 +02002961 "none",
2962 "plane1",
2963 "plane2",
2964 "pf",
Daniel Vetter5b3a8562013-10-16 22:55:48 +02002965 "pipe",
Daniel Vetter3d099a02013-10-16 22:55:58 +02002966 "TV",
2967 "DP-B",
2968 "DP-C",
2969 "DP-D",
Daniel Vetter46a19182013-11-01 10:50:20 +01002970 "auto",
Daniel Vetter926321d2013-10-16 13:30:34 +02002971};
2972
2973static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2974{
2975 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2976 return pipe_crc_sources[source];
2977}
2978
Damien Lespiaubd9db022013-10-15 18:55:36 +01002979static int display_crc_ctl_show(struct seq_file *m, void *data)
Daniel Vetter926321d2013-10-16 13:30:34 +02002980{
2981 struct drm_device *dev = m->private;
2982 struct drm_i915_private *dev_priv = dev->dev_private;
2983 int i;
2984
2985 for (i = 0; i < I915_MAX_PIPES; i++)
2986 seq_printf(m, "%c %s\n", pipe_name(i),
2987 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2988
2989 return 0;
2990}
2991
Damien Lespiaubd9db022013-10-15 18:55:36 +01002992static int display_crc_ctl_open(struct inode *inode, struct file *file)
Daniel Vetter926321d2013-10-16 13:30:34 +02002993{
2994 struct drm_device *dev = inode->i_private;
2995
Damien Lespiaubd9db022013-10-15 18:55:36 +01002996 return single_open(file, display_crc_ctl_show, dev);
Daniel Vetter926321d2013-10-16 13:30:34 +02002997}
2998
Daniel Vetter46a19182013-11-01 10:50:20 +01002999static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
Daniel Vetter52f843f2013-10-21 17:26:38 +02003000 uint32_t *val)
3001{
Daniel Vetter46a19182013-11-01 10:50:20 +01003002 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3003 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3004
3005 switch (*source) {
Daniel Vetter52f843f2013-10-21 17:26:38 +02003006 case INTEL_PIPE_CRC_SOURCE_PIPE:
3007 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3008 break;
3009 case INTEL_PIPE_CRC_SOURCE_NONE:
3010 *val = 0;
3011 break;
3012 default:
3013 return -EINVAL;
3014 }
3015
3016 return 0;
3017}
3018
Daniel Vetter46a19182013-11-01 10:50:20 +01003019static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3020 enum intel_pipe_crc_source *source)
3021{
3022 struct intel_encoder *encoder;
3023 struct intel_crtc *crtc;
Daniel Vetter26756802013-11-01 10:50:23 +01003024 struct intel_digital_port *dig_port;
Daniel Vetter46a19182013-11-01 10:50:20 +01003025 int ret = 0;
3026
3027 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3028
Daniel Vetter6e9f7982014-05-29 23:54:47 +02003029 drm_modeset_lock_all(dev);
Damien Lespiaub2784e12014-08-05 11:29:37 +01003030 for_each_intel_encoder(dev, encoder) {
Daniel Vetter46a19182013-11-01 10:50:20 +01003031 if (!encoder->base.crtc)
3032 continue;
3033
3034 crtc = to_intel_crtc(encoder->base.crtc);
3035
3036 if (crtc->pipe != pipe)
3037 continue;
3038
3039 switch (encoder->type) {
3040 case INTEL_OUTPUT_TVOUT:
3041 *source = INTEL_PIPE_CRC_SOURCE_TV;
3042 break;
3043 case INTEL_OUTPUT_DISPLAYPORT:
3044 case INTEL_OUTPUT_EDP:
Daniel Vetter26756802013-11-01 10:50:23 +01003045 dig_port = enc_to_dig_port(&encoder->base);
3046 switch (dig_port->port) {
3047 case PORT_B:
3048 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3049 break;
3050 case PORT_C:
3051 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3052 break;
3053 case PORT_D:
3054 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3055 break;
3056 default:
3057 WARN(1, "nonexisting DP port %c\n",
3058 port_name(dig_port->port));
3059 break;
3060 }
Daniel Vetter46a19182013-11-01 10:50:20 +01003061 break;
Paulo Zanoni6847d712014-10-27 17:47:52 -02003062 default:
3063 break;
Daniel Vetter46a19182013-11-01 10:50:20 +01003064 }
3065 }
Daniel Vetter6e9f7982014-05-29 23:54:47 +02003066 drm_modeset_unlock_all(dev);
Daniel Vetter46a19182013-11-01 10:50:20 +01003067
3068 return ret;
3069}
3070
3071static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3072 enum pipe pipe,
3073 enum intel_pipe_crc_source *source,
Daniel Vetter7ac01292013-10-18 16:37:06 +02003074 uint32_t *val)
3075{
Daniel Vetter8d2f24c2013-11-01 10:50:22 +01003076 struct drm_i915_private *dev_priv = dev->dev_private;
3077 bool need_stable_symbols = false;
3078
Daniel Vetter46a19182013-11-01 10:50:20 +01003079 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3080 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3081 if (ret)
3082 return ret;
3083 }
3084
3085 switch (*source) {
Daniel Vetter7ac01292013-10-18 16:37:06 +02003086 case INTEL_PIPE_CRC_SOURCE_PIPE:
3087 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3088 break;
3089 case INTEL_PIPE_CRC_SOURCE_DP_B:
3090 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
Daniel Vetter8d2f24c2013-11-01 10:50:22 +01003091 need_stable_symbols = true;
Daniel Vetter7ac01292013-10-18 16:37:06 +02003092 break;
3093 case INTEL_PIPE_CRC_SOURCE_DP_C:
3094 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
Daniel Vetter8d2f24c2013-11-01 10:50:22 +01003095 need_stable_symbols = true;
Daniel Vetter7ac01292013-10-18 16:37:06 +02003096 break;
3097 case INTEL_PIPE_CRC_SOURCE_NONE:
3098 *val = 0;
3099 break;
3100 default:
3101 return -EINVAL;
3102 }
3103
Daniel Vetter8d2f24c2013-11-01 10:50:22 +01003104 /*
3105 * When the pipe CRC tap point is after the transcoders we need
3106 * to tweak symbol-level features to produce a deterministic series of
3107 * symbols for a given frame. We need to reset those features only once
3108 * a frame (instead of every nth symbol):
3109 * - DC-balance: used to ensure a better clock recovery from the data
3110 * link (SDVO)
3111 * - DisplayPort scrambling: used for EMI reduction
3112 */
3113 if (need_stable_symbols) {
3114 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3115
Daniel Vetter8d2f24c2013-11-01 10:50:22 +01003116 tmp |= DC_BALANCE_RESET_VLV;
3117 if (pipe == PIPE_A)
3118 tmp |= PIPE_A_SCRAMBLE_RESET;
3119 else
3120 tmp |= PIPE_B_SCRAMBLE_RESET;
3121
3122 I915_WRITE(PORT_DFT2_G4X, tmp);
3123 }
3124
Daniel Vetter7ac01292013-10-18 16:37:06 +02003125 return 0;
3126}
3127
Daniel Vetter4b79ebf2013-10-16 22:55:59 +02003128static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
Daniel Vetter46a19182013-11-01 10:50:20 +01003129 enum pipe pipe,
3130 enum intel_pipe_crc_source *source,
Daniel Vetter4b79ebf2013-10-16 22:55:59 +02003131 uint32_t *val)
3132{
Daniel Vetter84093602013-11-01 10:50:21 +01003133 struct drm_i915_private *dev_priv = dev->dev_private;
3134 bool need_stable_symbols = false;
3135
Daniel Vetter46a19182013-11-01 10:50:20 +01003136 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3137 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3138 if (ret)
3139 return ret;
3140 }
3141
3142 switch (*source) {
Daniel Vetter4b79ebf2013-10-16 22:55:59 +02003143 case INTEL_PIPE_CRC_SOURCE_PIPE:
3144 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3145 break;
3146 case INTEL_PIPE_CRC_SOURCE_TV:
3147 if (!SUPPORTS_TV(dev))
3148 return -EINVAL;
3149 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3150 break;
3151 case INTEL_PIPE_CRC_SOURCE_DP_B:
3152 if (!IS_G4X(dev))
3153 return -EINVAL;
3154 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
Daniel Vetter84093602013-11-01 10:50:21 +01003155 need_stable_symbols = true;
Daniel Vetter4b79ebf2013-10-16 22:55:59 +02003156 break;
3157 case INTEL_PIPE_CRC_SOURCE_DP_C:
3158 if (!IS_G4X(dev))
3159 return -EINVAL;
3160 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
Daniel Vetter84093602013-11-01 10:50:21 +01003161 need_stable_symbols = true;
Daniel Vetter4b79ebf2013-10-16 22:55:59 +02003162 break;
3163 case INTEL_PIPE_CRC_SOURCE_DP_D:
3164 if (!IS_G4X(dev))
3165 return -EINVAL;
3166 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
Daniel Vetter84093602013-11-01 10:50:21 +01003167 need_stable_symbols = true;
Daniel Vetter4b79ebf2013-10-16 22:55:59 +02003168 break;
3169 case INTEL_PIPE_CRC_SOURCE_NONE:
3170 *val = 0;
3171 break;
3172 default:
3173 return -EINVAL;
3174 }
3175
Daniel Vetter84093602013-11-01 10:50:21 +01003176 /*
3177 * When the pipe CRC tap point is after the transcoders we need
3178 * to tweak symbol-level features to produce a deterministic series of
3179 * symbols for a given frame. We need to reset those features only once
3180 * a frame (instead of every nth symbol):
3181 * - DC-balance: used to ensure a better clock recovery from the data
3182 * link (SDVO)
3183 * - DisplayPort scrambling: used for EMI reduction
3184 */
3185 if (need_stable_symbols) {
3186 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3187
3188 WARN_ON(!IS_G4X(dev));
3189
3190 I915_WRITE(PORT_DFT_I9XX,
3191 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3192
3193 if (pipe == PIPE_A)
3194 tmp |= PIPE_A_SCRAMBLE_RESET;
3195 else
3196 tmp |= PIPE_B_SCRAMBLE_RESET;
3197
3198 I915_WRITE(PORT_DFT2_G4X, tmp);
3199 }
3200
Daniel Vetter4b79ebf2013-10-16 22:55:59 +02003201 return 0;
3202}
3203
Daniel Vetter8d2f24c2013-11-01 10:50:22 +01003204static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3205 enum pipe pipe)
3206{
3207 struct drm_i915_private *dev_priv = dev->dev_private;
3208 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3209
3210 if (pipe == PIPE_A)
3211 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3212 else
3213 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3214 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3215 tmp &= ~DC_BALANCE_RESET_VLV;
3216 I915_WRITE(PORT_DFT2_G4X, tmp);
3217
3218}
3219
Daniel Vetter84093602013-11-01 10:50:21 +01003220static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3221 enum pipe pipe)
3222{
3223 struct drm_i915_private *dev_priv = dev->dev_private;
3224 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3225
3226 if (pipe == PIPE_A)
3227 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3228 else
3229 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3230 I915_WRITE(PORT_DFT2_G4X, tmp);
3231
3232 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3233 I915_WRITE(PORT_DFT_I9XX,
3234 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3235 }
3236}
3237
Daniel Vetter46a19182013-11-01 10:50:20 +01003238static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003239 uint32_t *val)
3240{
Daniel Vetter46a19182013-11-01 10:50:20 +01003241 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3242 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3243
3244 switch (*source) {
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003245 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3246 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3247 break;
3248 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3249 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3250 break;
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003251 case INTEL_PIPE_CRC_SOURCE_PIPE:
3252 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3253 break;
Daniel Vetter3d099a02013-10-16 22:55:58 +02003254 case INTEL_PIPE_CRC_SOURCE_NONE:
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003255 *val = 0;
3256 break;
Daniel Vetter3d099a02013-10-16 22:55:58 +02003257 default:
3258 return -EINVAL;
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003259 }
3260
3261 return 0;
3262}
3263
Daniel Vetterfabf6e52014-05-29 14:10:22 +02003264static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3265{
3266 struct drm_i915_private *dev_priv = dev->dev_private;
3267 struct intel_crtc *crtc =
3268 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3269
3270 drm_modeset_lock_all(dev);
3271 /*
3272 * If we use the eDP transcoder we need to make sure that we don't
3273 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3274 * relevant on hsw with pipe A when using the always-on power well
3275 * routing.
3276 */
3277 if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&
3278 !crtc->config.pch_pfit.enabled) {
3279 crtc->config.pch_pfit.force_thru = true;
3280
3281 intel_display_power_get(dev_priv,
3282 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3283
3284 dev_priv->display.crtc_disable(&crtc->base);
3285 dev_priv->display.crtc_enable(&crtc->base);
3286 }
3287 drm_modeset_unlock_all(dev);
3288}
3289
3290static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3291{
3292 struct drm_i915_private *dev_priv = dev->dev_private;
3293 struct intel_crtc *crtc =
3294 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3295
3296 drm_modeset_lock_all(dev);
3297 /*
3298 * If we use the eDP transcoder we need to make sure that we don't
3299 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3300 * relevant on hsw with pipe A when using the always-on power well
3301 * routing.
3302 */
3303 if (crtc->config.pch_pfit.force_thru) {
3304 crtc->config.pch_pfit.force_thru = false;
3305
3306 dev_priv->display.crtc_disable(&crtc->base);
3307 dev_priv->display.crtc_enable(&crtc->base);
3308
3309 intel_display_power_put(dev_priv,
3310 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3311 }
3312 drm_modeset_unlock_all(dev);
3313}
3314
3315static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3316 enum pipe pipe,
3317 enum intel_pipe_crc_source *source,
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003318 uint32_t *val)
3319{
Daniel Vetter46a19182013-11-01 10:50:20 +01003320 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3321 *source = INTEL_PIPE_CRC_SOURCE_PF;
3322
3323 switch (*source) {
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003324 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3325 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3326 break;
3327 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3328 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3329 break;
3330 case INTEL_PIPE_CRC_SOURCE_PF:
Daniel Vetterfabf6e52014-05-29 14:10:22 +02003331 if (IS_HASWELL(dev) && pipe == PIPE_A)
3332 hsw_trans_edp_pipe_A_crc_wa(dev);
3333
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003334 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3335 break;
Daniel Vetter3d099a02013-10-16 22:55:58 +02003336 case INTEL_PIPE_CRC_SOURCE_NONE:
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003337 *val = 0;
3338 break;
Daniel Vetter3d099a02013-10-16 22:55:58 +02003339 default:
3340 return -EINVAL;
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003341 }
3342
3343 return 0;
3344}
3345
Daniel Vetter926321d2013-10-16 13:30:34 +02003346static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3347 enum intel_pipe_crc_source source)
3348{
3349 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiaucc3da172013-10-15 18:55:31 +01003350 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
Paulo Zanoni8c740dc2014-10-17 18:42:03 -03003351 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3352 pipe));
Borislav Petkov432f3342013-11-21 16:49:46 +01003353 u32 val = 0; /* shut up gcc */
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003354 int ret;
Daniel Vetter926321d2013-10-16 13:30:34 +02003355
Damien Lespiaucc3da172013-10-15 18:55:31 +01003356 if (pipe_crc->source == source)
3357 return 0;
3358
Damien Lespiauae676fc2013-10-15 18:55:32 +01003359 /* forbid changing the source without going back to 'none' */
3360 if (pipe_crc->source && source)
3361 return -EINVAL;
3362
Daniel Vetter9d8b0582014-11-25 14:00:40 +01003363 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3364 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3365 return -EIO;
3366 }
3367
Daniel Vetter52f843f2013-10-21 17:26:38 +02003368 if (IS_GEN2(dev))
Daniel Vetter46a19182013-11-01 10:50:20 +01003369 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
Daniel Vetter52f843f2013-10-21 17:26:38 +02003370 else if (INTEL_INFO(dev)->gen < 5)
Daniel Vetter46a19182013-11-01 10:50:20 +01003371 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
Daniel Vetter7ac01292013-10-18 16:37:06 +02003372 else if (IS_VALLEYVIEW(dev))
Daniel Vetterfabf6e52014-05-29 14:10:22 +02003373 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
Daniel Vetter4b79ebf2013-10-16 22:55:59 +02003374 else if (IS_GEN5(dev) || IS_GEN6(dev))
Daniel Vetter46a19182013-11-01 10:50:20 +01003375 ret = ilk_pipe_crc_ctl_reg(&source, &val);
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003376 else
Daniel Vetterfabf6e52014-05-29 14:10:22 +02003377 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003378
3379 if (ret != 0)
3380 return ret;
3381
Damien Lespiau4b584362013-10-15 18:55:33 +01003382 /* none -> real source transition */
3383 if (source) {
Damien Lespiau7cd6ccf2013-10-15 18:55:38 +01003384 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3385 pipe_name(pipe), pipe_crc_source_name(source));
3386
Damien Lespiaue5f75ac2013-10-15 18:55:34 +01003387 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
3388 INTEL_PIPE_CRC_ENTRIES_NR,
3389 GFP_KERNEL);
3390 if (!pipe_crc->entries)
3391 return -ENOMEM;
3392
Paulo Zanoni8c740dc2014-10-17 18:42:03 -03003393 /*
3394 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3395 * enabled and disabled dynamically based on package C states,
3396 * user space can't make reliable use of the CRCs, so let's just
3397 * completely disable it.
3398 */
3399 hsw_disable_ips(crtc);
3400
Damien Lespiaud538bbd2013-10-21 14:29:30 +01003401 spin_lock_irq(&pipe_crc->lock);
3402 pipe_crc->head = 0;
3403 pipe_crc->tail = 0;
3404 spin_unlock_irq(&pipe_crc->lock);
Damien Lespiau4b584362013-10-15 18:55:33 +01003405 }
3406
Damien Lespiaucc3da172013-10-15 18:55:31 +01003407 pipe_crc->source = source;
Daniel Vetter926321d2013-10-16 13:30:34 +02003408
Daniel Vetter926321d2013-10-16 13:30:34 +02003409 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3410 POSTING_READ(PIPE_CRC_CTL(pipe));
3411
Damien Lespiaue5f75ac2013-10-15 18:55:34 +01003412 /* real source -> none transition */
3413 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01003414 struct intel_pipe_crc_entry *entries;
Daniel Vettera33d7102014-06-06 08:22:08 +02003415 struct intel_crtc *crtc =
3416 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
Damien Lespiaud538bbd2013-10-21 14:29:30 +01003417
Damien Lespiau7cd6ccf2013-10-15 18:55:38 +01003418 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3419 pipe_name(pipe));
3420
Daniel Vettera33d7102014-06-06 08:22:08 +02003421 drm_modeset_lock(&crtc->base.mutex, NULL);
3422 if (crtc->active)
3423 intel_wait_for_vblank(dev, pipe);
3424 drm_modeset_unlock(&crtc->base.mutex);
Daniel Vetterbcf17ab2013-10-16 22:55:50 +02003425
Damien Lespiaud538bbd2013-10-21 14:29:30 +01003426 spin_lock_irq(&pipe_crc->lock);
3427 entries = pipe_crc->entries;
Damien Lespiaue5f75ac2013-10-15 18:55:34 +01003428 pipe_crc->entries = NULL;
Damien Lespiaud538bbd2013-10-21 14:29:30 +01003429 spin_unlock_irq(&pipe_crc->lock);
3430
3431 kfree(entries);
Daniel Vetter84093602013-11-01 10:50:21 +01003432
3433 if (IS_G4X(dev))
3434 g4x_undo_pipe_scramble_reset(dev, pipe);
Daniel Vetter8d2f24c2013-11-01 10:50:22 +01003435 else if (IS_VALLEYVIEW(dev))
3436 vlv_undo_pipe_scramble_reset(dev, pipe);
Daniel Vetterfabf6e52014-05-29 14:10:22 +02003437 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3438 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
Paulo Zanoni8c740dc2014-10-17 18:42:03 -03003439
3440 hsw_enable_ips(crtc);
Damien Lespiaue5f75ac2013-10-15 18:55:34 +01003441 }
3442
Daniel Vetter926321d2013-10-16 13:30:34 +02003443 return 0;
3444}
3445
3446/*
3447 * Parse pipe CRC command strings:
Damien Lespiaub94dec82013-10-15 18:55:35 +01003448 * command: wsp* object wsp+ name wsp+ source wsp*
3449 * object: 'pipe'
3450 * name: (A | B | C)
Daniel Vetter926321d2013-10-16 13:30:34 +02003451 * source: (none | plane1 | plane2 | pf)
3452 * wsp: (#0x20 | #0x9 | #0xA)+
3453 *
3454 * eg.:
Damien Lespiaub94dec82013-10-15 18:55:35 +01003455 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3456 * "pipe A none" -> Stop CRC
Daniel Vetter926321d2013-10-16 13:30:34 +02003457 */
Damien Lespiaubd9db022013-10-15 18:55:36 +01003458static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
Daniel Vetter926321d2013-10-16 13:30:34 +02003459{
3460 int n_words = 0;
3461
3462 while (*buf) {
3463 char *end;
3464
3465 /* skip leading white space */
3466 buf = skip_spaces(buf);
3467 if (!*buf)
3468 break; /* end of buffer */
3469
3470 /* find end of word */
3471 for (end = buf; *end && !isspace(*end); end++)
3472 ;
3473
3474 if (n_words == max_words) {
3475 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3476 max_words);
3477 return -EINVAL; /* ran out of words[] before bytes */
3478 }
3479
3480 if (*end)
3481 *end++ = '\0';
3482 words[n_words++] = buf;
3483 buf = end;
3484 }
3485
3486 return n_words;
3487}
3488
Damien Lespiaub94dec82013-10-15 18:55:35 +01003489enum intel_pipe_crc_object {
3490 PIPE_CRC_OBJECT_PIPE,
3491};
3492
Daniel Vettere8dfcf72013-10-16 11:51:54 +02003493static const char * const pipe_crc_objects[] = {
Damien Lespiaub94dec82013-10-15 18:55:35 +01003494 "pipe",
3495};
3496
3497static int
Damien Lespiaubd9db022013-10-15 18:55:36 +01003498display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
Damien Lespiaub94dec82013-10-15 18:55:35 +01003499{
3500 int i;
3501
3502 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3503 if (!strcmp(buf, pipe_crc_objects[i])) {
Damien Lespiaubd9db022013-10-15 18:55:36 +01003504 *o = i;
Damien Lespiaub94dec82013-10-15 18:55:35 +01003505 return 0;
3506 }
3507
3508 return -EINVAL;
3509}
3510
Damien Lespiaubd9db022013-10-15 18:55:36 +01003511static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
Daniel Vetter926321d2013-10-16 13:30:34 +02003512{
3513 const char name = buf[0];
3514
3515 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3516 return -EINVAL;
3517
3518 *pipe = name - 'A';
3519
3520 return 0;
3521}
3522
3523static int
Damien Lespiaubd9db022013-10-15 18:55:36 +01003524display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
Daniel Vetter926321d2013-10-16 13:30:34 +02003525{
3526 int i;
3527
3528 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3529 if (!strcmp(buf, pipe_crc_sources[i])) {
Damien Lespiaubd9db022013-10-15 18:55:36 +01003530 *s = i;
Daniel Vetter926321d2013-10-16 13:30:34 +02003531 return 0;
3532 }
3533
3534 return -EINVAL;
3535}
3536
Damien Lespiaubd9db022013-10-15 18:55:36 +01003537static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
Daniel Vetter926321d2013-10-16 13:30:34 +02003538{
Damien Lespiaub94dec82013-10-15 18:55:35 +01003539#define N_WORDS 3
Daniel Vetter926321d2013-10-16 13:30:34 +02003540 int n_words;
Damien Lespiaub94dec82013-10-15 18:55:35 +01003541 char *words[N_WORDS];
Daniel Vetter926321d2013-10-16 13:30:34 +02003542 enum pipe pipe;
Damien Lespiaub94dec82013-10-15 18:55:35 +01003543 enum intel_pipe_crc_object object;
Daniel Vetter926321d2013-10-16 13:30:34 +02003544 enum intel_pipe_crc_source source;
3545
Damien Lespiaubd9db022013-10-15 18:55:36 +01003546 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
Damien Lespiaub94dec82013-10-15 18:55:35 +01003547 if (n_words != N_WORDS) {
3548 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3549 N_WORDS);
Daniel Vetter926321d2013-10-16 13:30:34 +02003550 return -EINVAL;
3551 }
3552
Damien Lespiaubd9db022013-10-15 18:55:36 +01003553 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
Damien Lespiaub94dec82013-10-15 18:55:35 +01003554 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
Daniel Vetter926321d2013-10-16 13:30:34 +02003555 return -EINVAL;
3556 }
3557
Damien Lespiaubd9db022013-10-15 18:55:36 +01003558 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
Damien Lespiaub94dec82013-10-15 18:55:35 +01003559 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3560 return -EINVAL;
3561 }
3562
Damien Lespiaubd9db022013-10-15 18:55:36 +01003563 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
Damien Lespiaub94dec82013-10-15 18:55:35 +01003564 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
Daniel Vetter926321d2013-10-16 13:30:34 +02003565 return -EINVAL;
3566 }
3567
3568 return pipe_crc_set_source(dev, pipe, source);
3569}
3570
Damien Lespiaubd9db022013-10-15 18:55:36 +01003571static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3572 size_t len, loff_t *offp)
Daniel Vetter926321d2013-10-16 13:30:34 +02003573{
3574 struct seq_file *m = file->private_data;
3575 struct drm_device *dev = m->private;
3576 char *tmpbuf;
3577 int ret;
3578
3579 if (len == 0)
3580 return 0;
3581
3582 if (len > PAGE_SIZE - 1) {
3583 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3584 PAGE_SIZE);
3585 return -E2BIG;
3586 }
3587
3588 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3589 if (!tmpbuf)
3590 return -ENOMEM;
3591
3592 if (copy_from_user(tmpbuf, ubuf, len)) {
3593 ret = -EFAULT;
3594 goto out;
3595 }
3596 tmpbuf[len] = '\0';
3597
Damien Lespiaubd9db022013-10-15 18:55:36 +01003598 ret = display_crc_ctl_parse(dev, tmpbuf, len);
Daniel Vetter926321d2013-10-16 13:30:34 +02003599
3600out:
3601 kfree(tmpbuf);
3602 if (ret < 0)
3603 return ret;
3604
3605 *offp += len;
3606 return len;
3607}
3608
Damien Lespiaubd9db022013-10-15 18:55:36 +01003609static const struct file_operations i915_display_crc_ctl_fops = {
Daniel Vetter926321d2013-10-16 13:30:34 +02003610 .owner = THIS_MODULE,
Damien Lespiaubd9db022013-10-15 18:55:36 +01003611 .open = display_crc_ctl_open,
Daniel Vetter926321d2013-10-16 13:30:34 +02003612 .read = seq_read,
3613 .llseek = seq_lseek,
3614 .release = single_release,
Damien Lespiaubd9db022013-10-15 18:55:36 +01003615 .write = display_crc_ctl_write
Daniel Vetter926321d2013-10-16 13:30:34 +02003616};
3617
Damien Lespiau97e94b22014-11-04 17:06:50 +00003618static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
Ville Syrjälä369a1342014-01-22 14:36:08 +02003619{
3620 struct drm_device *dev = m->private;
Damien Lespiau546c81f2014-05-13 15:30:26 +01003621 int num_levels = ilk_wm_max_level(dev) + 1;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003622 int level;
3623
3624 drm_modeset_lock_all(dev);
3625
3626 for (level = 0; level < num_levels; level++) {
3627 unsigned int latency = wm[level];
3628
Damien Lespiau97e94b22014-11-04 17:06:50 +00003629 /*
3630 * - WM1+ latency values in 0.5us units
3631 * - latencies are in us on gen9
3632 */
3633 if (INTEL_INFO(dev)->gen >= 9)
3634 latency *= 10;
3635 else if (level > 0)
Ville Syrjälä369a1342014-01-22 14:36:08 +02003636 latency *= 5;
3637
3638 seq_printf(m, "WM%d %u (%u.%u usec)\n",
Damien Lespiau97e94b22014-11-04 17:06:50 +00003639 level, wm[level], latency / 10, latency % 10);
Ville Syrjälä369a1342014-01-22 14:36:08 +02003640 }
3641
3642 drm_modeset_unlock_all(dev);
3643}
3644
3645static int pri_wm_latency_show(struct seq_file *m, void *data)
3646{
3647 struct drm_device *dev = m->private;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003648 struct drm_i915_private *dev_priv = dev->dev_private;
3649 const uint16_t *latencies;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003650
Damien Lespiau97e94b22014-11-04 17:06:50 +00003651 if (INTEL_INFO(dev)->gen >= 9)
3652 latencies = dev_priv->wm.skl_latency;
3653 else
3654 latencies = to_i915(dev)->wm.pri_latency;
3655
3656 wm_latency_show(m, latencies);
Ville Syrjälä369a1342014-01-22 14:36:08 +02003657
3658 return 0;
3659}
3660
3661static int spr_wm_latency_show(struct seq_file *m, void *data)
3662{
3663 struct drm_device *dev = m->private;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003664 struct drm_i915_private *dev_priv = dev->dev_private;
3665 const uint16_t *latencies;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003666
Damien Lespiau97e94b22014-11-04 17:06:50 +00003667 if (INTEL_INFO(dev)->gen >= 9)
3668 latencies = dev_priv->wm.skl_latency;
3669 else
3670 latencies = to_i915(dev)->wm.spr_latency;
3671
3672 wm_latency_show(m, latencies);
Ville Syrjälä369a1342014-01-22 14:36:08 +02003673
3674 return 0;
3675}
3676
3677static int cur_wm_latency_show(struct seq_file *m, void *data)
3678{
3679 struct drm_device *dev = m->private;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003680 struct drm_i915_private *dev_priv = dev->dev_private;
3681 const uint16_t *latencies;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003682
Damien Lespiau97e94b22014-11-04 17:06:50 +00003683 if (INTEL_INFO(dev)->gen >= 9)
3684 latencies = dev_priv->wm.skl_latency;
3685 else
3686 latencies = to_i915(dev)->wm.cur_latency;
3687
3688 wm_latency_show(m, latencies);
Ville Syrjälä369a1342014-01-22 14:36:08 +02003689
3690 return 0;
3691}
3692
3693static int pri_wm_latency_open(struct inode *inode, struct file *file)
3694{
3695 struct drm_device *dev = inode->i_private;
3696
Sonika Jindal9ad02572014-07-21 15:23:39 +05303697 if (HAS_GMCH_DISPLAY(dev))
Ville Syrjälä369a1342014-01-22 14:36:08 +02003698 return -ENODEV;
3699
3700 return single_open(file, pri_wm_latency_show, dev);
3701}
3702
3703static int spr_wm_latency_open(struct inode *inode, struct file *file)
3704{
3705 struct drm_device *dev = inode->i_private;
3706
Sonika Jindal9ad02572014-07-21 15:23:39 +05303707 if (HAS_GMCH_DISPLAY(dev))
Ville Syrjälä369a1342014-01-22 14:36:08 +02003708 return -ENODEV;
3709
3710 return single_open(file, spr_wm_latency_show, dev);
3711}
3712
3713static int cur_wm_latency_open(struct inode *inode, struct file *file)
3714{
3715 struct drm_device *dev = inode->i_private;
3716
Sonika Jindal9ad02572014-07-21 15:23:39 +05303717 if (HAS_GMCH_DISPLAY(dev))
Ville Syrjälä369a1342014-01-22 14:36:08 +02003718 return -ENODEV;
3719
3720 return single_open(file, cur_wm_latency_show, dev);
3721}
3722
3723static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
Damien Lespiau97e94b22014-11-04 17:06:50 +00003724 size_t len, loff_t *offp, uint16_t wm[8])
Ville Syrjälä369a1342014-01-22 14:36:08 +02003725{
3726 struct seq_file *m = file->private_data;
3727 struct drm_device *dev = m->private;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003728 uint16_t new[8] = { 0 };
Damien Lespiau546c81f2014-05-13 15:30:26 +01003729 int num_levels = ilk_wm_max_level(dev) + 1;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003730 int level;
3731 int ret;
3732 char tmp[32];
3733
3734 if (len >= sizeof(tmp))
3735 return -EINVAL;
3736
3737 if (copy_from_user(tmp, ubuf, len))
3738 return -EFAULT;
3739
3740 tmp[len] = '\0';
3741
Damien Lespiau97e94b22014-11-04 17:06:50 +00003742 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3743 &new[0], &new[1], &new[2], &new[3],
3744 &new[4], &new[5], &new[6], &new[7]);
Ville Syrjälä369a1342014-01-22 14:36:08 +02003745 if (ret != num_levels)
3746 return -EINVAL;
3747
3748 drm_modeset_lock_all(dev);
3749
3750 for (level = 0; level < num_levels; level++)
3751 wm[level] = new[level];
3752
3753 drm_modeset_unlock_all(dev);
3754
3755 return len;
3756}
3757
3758
3759static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3760 size_t len, loff_t *offp)
3761{
3762 struct seq_file *m = file->private_data;
3763 struct drm_device *dev = m->private;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003764 struct drm_i915_private *dev_priv = dev->dev_private;
3765 uint16_t *latencies;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003766
Damien Lespiau97e94b22014-11-04 17:06:50 +00003767 if (INTEL_INFO(dev)->gen >= 9)
3768 latencies = dev_priv->wm.skl_latency;
3769 else
3770 latencies = to_i915(dev)->wm.pri_latency;
3771
3772 return wm_latency_write(file, ubuf, len, offp, latencies);
Ville Syrjälä369a1342014-01-22 14:36:08 +02003773}
3774
3775static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3776 size_t len, loff_t *offp)
3777{
3778 struct seq_file *m = file->private_data;
3779 struct drm_device *dev = m->private;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003780 struct drm_i915_private *dev_priv = dev->dev_private;
3781 uint16_t *latencies;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003782
Damien Lespiau97e94b22014-11-04 17:06:50 +00003783 if (INTEL_INFO(dev)->gen >= 9)
3784 latencies = dev_priv->wm.skl_latency;
3785 else
3786 latencies = to_i915(dev)->wm.spr_latency;
3787
3788 return wm_latency_write(file, ubuf, len, offp, latencies);
Ville Syrjälä369a1342014-01-22 14:36:08 +02003789}
3790
3791static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3792 size_t len, loff_t *offp)
3793{
3794 struct seq_file *m = file->private_data;
3795 struct drm_device *dev = m->private;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003796 struct drm_i915_private *dev_priv = dev->dev_private;
3797 uint16_t *latencies;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003798
Damien Lespiau97e94b22014-11-04 17:06:50 +00003799 if (INTEL_INFO(dev)->gen >= 9)
3800 latencies = dev_priv->wm.skl_latency;
3801 else
3802 latencies = to_i915(dev)->wm.cur_latency;
3803
3804 return wm_latency_write(file, ubuf, len, offp, latencies);
Ville Syrjälä369a1342014-01-22 14:36:08 +02003805}
3806
3807static const struct file_operations i915_pri_wm_latency_fops = {
3808 .owner = THIS_MODULE,
3809 .open = pri_wm_latency_open,
3810 .read = seq_read,
3811 .llseek = seq_lseek,
3812 .release = single_release,
3813 .write = pri_wm_latency_write
3814};
3815
3816static const struct file_operations i915_spr_wm_latency_fops = {
3817 .owner = THIS_MODULE,
3818 .open = spr_wm_latency_open,
3819 .read = seq_read,
3820 .llseek = seq_lseek,
3821 .release = single_release,
3822 .write = spr_wm_latency_write
3823};
3824
3825static const struct file_operations i915_cur_wm_latency_fops = {
3826 .owner = THIS_MODULE,
3827 .open = cur_wm_latency_open,
3828 .read = seq_read,
3829 .llseek = seq_lseek,
3830 .release = single_release,
3831 .write = cur_wm_latency_write
3832};
3833
Kees Cook647416f2013-03-10 14:10:06 -07003834static int
3835i915_wedged_get(void *data, u64 *val)
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003836{
Kees Cook647416f2013-03-10 14:10:06 -07003837 struct drm_device *dev = data;
Jani Nikulae277a1f2014-03-31 14:27:14 +03003838 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003839
Kees Cook647416f2013-03-10 14:10:06 -07003840 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003841
Kees Cook647416f2013-03-10 14:10:06 -07003842 return 0;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003843}
3844
Kees Cook647416f2013-03-10 14:10:06 -07003845static int
3846i915_wedged_set(void *data, u64 val)
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003847{
Kees Cook647416f2013-03-10 14:10:06 -07003848 struct drm_device *dev = data;
Imre Deakd46c0512014-04-14 20:24:27 +03003849 struct drm_i915_private *dev_priv = dev->dev_private;
3850
3851 intel_runtime_pm_get(dev_priv);
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003852
Mika Kuoppala58174462014-02-25 17:11:26 +02003853 i915_handle_error(dev, val,
3854 "Manually setting wedged to %llu", val);
Imre Deakd46c0512014-04-14 20:24:27 +03003855
3856 intel_runtime_pm_put(dev_priv);
3857
Kees Cook647416f2013-03-10 14:10:06 -07003858 return 0;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003859}
3860
Kees Cook647416f2013-03-10 14:10:06 -07003861DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3862 i915_wedged_get, i915_wedged_set,
Mika Kuoppala3a3b4f92013-04-12 12:10:05 +03003863 "%llu\n");
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003864
Kees Cook647416f2013-03-10 14:10:06 -07003865static int
3866i915_ring_stop_get(void *data, u64 *val)
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003867{
Kees Cook647416f2013-03-10 14:10:06 -07003868 struct drm_device *dev = data;
Jani Nikulae277a1f2014-03-31 14:27:14 +03003869 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003870
Kees Cook647416f2013-03-10 14:10:06 -07003871 *val = dev_priv->gpu_error.stop_rings;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003872
Kees Cook647416f2013-03-10 14:10:06 -07003873 return 0;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003874}
3875
Kees Cook647416f2013-03-10 14:10:06 -07003876static int
3877i915_ring_stop_set(void *data, u64 val)
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003878{
Kees Cook647416f2013-03-10 14:10:06 -07003879 struct drm_device *dev = data;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003880 struct drm_i915_private *dev_priv = dev->dev_private;
Kees Cook647416f2013-03-10 14:10:06 -07003881 int ret;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003882
Kees Cook647416f2013-03-10 14:10:06 -07003883 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003884
Daniel Vetter22bcfc62012-08-09 15:07:02 +02003885 ret = mutex_lock_interruptible(&dev->struct_mutex);
3886 if (ret)
3887 return ret;
3888
Daniel Vetter99584db2012-11-14 17:14:04 +01003889 dev_priv->gpu_error.stop_rings = val;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003890 mutex_unlock(&dev->struct_mutex);
3891
Kees Cook647416f2013-03-10 14:10:06 -07003892 return 0;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003893}
3894
Kees Cook647416f2013-03-10 14:10:06 -07003895DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3896 i915_ring_stop_get, i915_ring_stop_set,
3897 "0x%08llx\n");
Daniel Vetterd5442302012-04-27 15:17:40 +02003898
Chris Wilson094f9a52013-09-25 17:34:55 +01003899static int
3900i915_ring_missed_irq_get(void *data, u64 *val)
3901{
3902 struct drm_device *dev = data;
3903 struct drm_i915_private *dev_priv = dev->dev_private;
3904
3905 *val = dev_priv->gpu_error.missed_irq_rings;
3906 return 0;
3907}
3908
3909static int
3910i915_ring_missed_irq_set(void *data, u64 val)
3911{
3912 struct drm_device *dev = data;
3913 struct drm_i915_private *dev_priv = dev->dev_private;
3914 int ret;
3915
3916 /* Lock against concurrent debugfs callers */
3917 ret = mutex_lock_interruptible(&dev->struct_mutex);
3918 if (ret)
3919 return ret;
3920 dev_priv->gpu_error.missed_irq_rings = val;
3921 mutex_unlock(&dev->struct_mutex);
3922
3923 return 0;
3924}
3925
3926DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3927 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3928 "0x%08llx\n");
3929
3930static int
3931i915_ring_test_irq_get(void *data, u64 *val)
3932{
3933 struct drm_device *dev = data;
3934 struct drm_i915_private *dev_priv = dev->dev_private;
3935
3936 *val = dev_priv->gpu_error.test_irq_rings;
3937
3938 return 0;
3939}
3940
3941static int
3942i915_ring_test_irq_set(void *data, u64 val)
3943{
3944 struct drm_device *dev = data;
3945 struct drm_i915_private *dev_priv = dev->dev_private;
3946 int ret;
3947
3948 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3949
3950 /* Lock against concurrent debugfs callers */
3951 ret = mutex_lock_interruptible(&dev->struct_mutex);
3952 if (ret)
3953 return ret;
3954
3955 dev_priv->gpu_error.test_irq_rings = val;
3956 mutex_unlock(&dev->struct_mutex);
3957
3958 return 0;
3959}
3960
3961DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3962 i915_ring_test_irq_get, i915_ring_test_irq_set,
3963 "0x%08llx\n");
3964
Chris Wilsondd624af2013-01-15 12:39:35 +00003965#define DROP_UNBOUND 0x1
3966#define DROP_BOUND 0x2
3967#define DROP_RETIRE 0x4
3968#define DROP_ACTIVE 0x8
3969#define DROP_ALL (DROP_UNBOUND | \
3970 DROP_BOUND | \
3971 DROP_RETIRE | \
3972 DROP_ACTIVE)
Kees Cook647416f2013-03-10 14:10:06 -07003973static int
3974i915_drop_caches_get(void *data, u64 *val)
Chris Wilsondd624af2013-01-15 12:39:35 +00003975{
Kees Cook647416f2013-03-10 14:10:06 -07003976 *val = DROP_ALL;
Chris Wilsondd624af2013-01-15 12:39:35 +00003977
Kees Cook647416f2013-03-10 14:10:06 -07003978 return 0;
Chris Wilsondd624af2013-01-15 12:39:35 +00003979}
3980
Kees Cook647416f2013-03-10 14:10:06 -07003981static int
3982i915_drop_caches_set(void *data, u64 val)
Chris Wilsondd624af2013-01-15 12:39:35 +00003983{
Kees Cook647416f2013-03-10 14:10:06 -07003984 struct drm_device *dev = data;
Chris Wilsondd624af2013-01-15 12:39:35 +00003985 struct drm_i915_private *dev_priv = dev->dev_private;
Kees Cook647416f2013-03-10 14:10:06 -07003986 int ret;
Chris Wilsondd624af2013-01-15 12:39:35 +00003987
Ben Widawsky2f9fe5f2013-11-25 09:54:37 -08003988 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
Chris Wilsondd624af2013-01-15 12:39:35 +00003989
3990 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3991 * on ioctls on -EAGAIN. */
3992 ret = mutex_lock_interruptible(&dev->struct_mutex);
3993 if (ret)
3994 return ret;
3995
3996 if (val & DROP_ACTIVE) {
3997 ret = i915_gpu_idle(dev);
3998 if (ret)
3999 goto unlock;
4000 }
4001
4002 if (val & (DROP_RETIRE | DROP_ACTIVE))
4003 i915_gem_retire_requests(dev);
4004
Chris Wilson21ab4e72014-09-09 11:16:08 +01004005 if (val & DROP_BOUND)
4006 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
Chris Wilson4ad72b72014-09-03 19:23:37 +01004007
Chris Wilson21ab4e72014-09-09 11:16:08 +01004008 if (val & DROP_UNBOUND)
4009 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
Chris Wilsondd624af2013-01-15 12:39:35 +00004010
4011unlock:
4012 mutex_unlock(&dev->struct_mutex);
4013
Kees Cook647416f2013-03-10 14:10:06 -07004014 return ret;
Chris Wilsondd624af2013-01-15 12:39:35 +00004015}
4016
Kees Cook647416f2013-03-10 14:10:06 -07004017DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4018 i915_drop_caches_get, i915_drop_caches_set,
4019 "0x%08llx\n");
Chris Wilsondd624af2013-01-15 12:39:35 +00004020
Kees Cook647416f2013-03-10 14:10:06 -07004021static int
4022i915_max_freq_get(void *data, u64 *val)
Jesse Barnes358733e2011-07-27 11:53:01 -07004023{
Kees Cook647416f2013-03-10 14:10:06 -07004024 struct drm_device *dev = data;
Jani Nikulae277a1f2014-03-31 14:27:14 +03004025 struct drm_i915_private *dev_priv = dev->dev_private;
Kees Cook647416f2013-03-10 14:10:06 -07004026 int ret;
Daniel Vetter004777c2012-08-09 15:07:01 +02004027
Tom O'Rourkedaa3afb2014-05-30 16:22:10 -07004028 if (INTEL_INFO(dev)->gen < 6)
Daniel Vetter004777c2012-08-09 15:07:01 +02004029 return -ENODEV;
4030
Tom O'Rourke5c9669c2013-09-16 14:56:43 -07004031 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4032
Jesse Barnes4fc688c2012-11-02 11:14:01 -07004033 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
Daniel Vetter004777c2012-08-09 15:07:01 +02004034 if (ret)
4035 return ret;
Jesse Barnes358733e2011-07-27 11:53:01 -07004036
Jesse Barnes0a073b82013-04-17 15:54:58 -07004037 if (IS_VALLEYVIEW(dev))
Ben Widawskyb39fb292014-03-19 18:31:11 -07004038 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
Jesse Barnes0a073b82013-04-17 15:54:58 -07004039 else
Ben Widawskyb39fb292014-03-19 18:31:11 -07004040 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
Jesse Barnes4fc688c2012-11-02 11:14:01 -07004041 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes358733e2011-07-27 11:53:01 -07004042
Kees Cook647416f2013-03-10 14:10:06 -07004043 return 0;
Jesse Barnes358733e2011-07-27 11:53:01 -07004044}
4045
Kees Cook647416f2013-03-10 14:10:06 -07004046static int
4047i915_max_freq_set(void *data, u64 val)
Jesse Barnes358733e2011-07-27 11:53:01 -07004048{
Kees Cook647416f2013-03-10 14:10:06 -07004049 struct drm_device *dev = data;
Jesse Barnes358733e2011-07-27 11:53:01 -07004050 struct drm_i915_private *dev_priv = dev->dev_private;
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004051 u32 rp_state_cap, hw_max, hw_min;
Kees Cook647416f2013-03-10 14:10:06 -07004052 int ret;
Daniel Vetter004777c2012-08-09 15:07:01 +02004053
Tom O'Rourkedaa3afb2014-05-30 16:22:10 -07004054 if (INTEL_INFO(dev)->gen < 6)
Daniel Vetter004777c2012-08-09 15:07:01 +02004055 return -ENODEV;
Jesse Barnes358733e2011-07-27 11:53:01 -07004056
Tom O'Rourke5c9669c2013-09-16 14:56:43 -07004057 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4058
Kees Cook647416f2013-03-10 14:10:06 -07004059 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
Jesse Barnes358733e2011-07-27 11:53:01 -07004060
Jesse Barnes4fc688c2012-11-02 11:14:01 -07004061 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
Daniel Vetter004777c2012-08-09 15:07:01 +02004062 if (ret)
4063 return ret;
4064
Jesse Barnes358733e2011-07-27 11:53:01 -07004065 /*
4066 * Turbo will still be enabled, but won't go above the set value.
4067 */
Jesse Barnes0a073b82013-04-17 15:54:58 -07004068 if (IS_VALLEYVIEW(dev)) {
Ville Syrjälä2ec38152013-11-05 22:42:29 +02004069 val = vlv_freq_opcode(dev_priv, val);
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004070
Ville Syrjälä03af2042014-06-28 02:03:53 +03004071 hw_max = dev_priv->rps.max_freq;
4072 hw_min = dev_priv->rps.min_freq;
Jesse Barnes0a073b82013-04-17 15:54:58 -07004073 } else {
4074 do_div(val, GT_FREQUENCY_MULTIPLIER);
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004075
4076 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
Ben Widawskyb39fb292014-03-19 18:31:11 -07004077 hw_max = dev_priv->rps.max_freq;
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004078 hw_min = (rp_state_cap >> 16) & 0xff;
Jesse Barnes0a073b82013-04-17 15:54:58 -07004079 }
4080
Ben Widawskyb39fb292014-03-19 18:31:11 -07004081 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004082 mutex_unlock(&dev_priv->rps.hw_lock);
4083 return -EINVAL;
4084 }
4085
Ben Widawskyb39fb292014-03-19 18:31:11 -07004086 dev_priv->rps.max_freq_softlimit = val;
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004087
4088 if (IS_VALLEYVIEW(dev))
4089 valleyview_set_rps(dev, val);
4090 else
4091 gen6_set_rps(dev, val);
4092
Jesse Barnes4fc688c2012-11-02 11:14:01 -07004093 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes358733e2011-07-27 11:53:01 -07004094
Kees Cook647416f2013-03-10 14:10:06 -07004095 return 0;
Jesse Barnes358733e2011-07-27 11:53:01 -07004096}
4097
Kees Cook647416f2013-03-10 14:10:06 -07004098DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4099 i915_max_freq_get, i915_max_freq_set,
Mika Kuoppala3a3b4f92013-04-12 12:10:05 +03004100 "%llu\n");
Jesse Barnes358733e2011-07-27 11:53:01 -07004101
Kees Cook647416f2013-03-10 14:10:06 -07004102static int
4103i915_min_freq_get(void *data, u64 *val)
Jesse Barnes1523c312012-05-25 12:34:54 -07004104{
Kees Cook647416f2013-03-10 14:10:06 -07004105 struct drm_device *dev = data;
Jani Nikulae277a1f2014-03-31 14:27:14 +03004106 struct drm_i915_private *dev_priv = dev->dev_private;
Kees Cook647416f2013-03-10 14:10:06 -07004107 int ret;
Daniel Vetter004777c2012-08-09 15:07:01 +02004108
Tom O'Rourkedaa3afb2014-05-30 16:22:10 -07004109 if (INTEL_INFO(dev)->gen < 6)
Daniel Vetter004777c2012-08-09 15:07:01 +02004110 return -ENODEV;
4111
Tom O'Rourke5c9669c2013-09-16 14:56:43 -07004112 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4113
Jesse Barnes4fc688c2012-11-02 11:14:01 -07004114 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
Daniel Vetter004777c2012-08-09 15:07:01 +02004115 if (ret)
4116 return ret;
Jesse Barnes1523c312012-05-25 12:34:54 -07004117
Jesse Barnes0a073b82013-04-17 15:54:58 -07004118 if (IS_VALLEYVIEW(dev))
Ben Widawskyb39fb292014-03-19 18:31:11 -07004119 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
Jesse Barnes0a073b82013-04-17 15:54:58 -07004120 else
Ben Widawskyb39fb292014-03-19 18:31:11 -07004121 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
Jesse Barnes4fc688c2012-11-02 11:14:01 -07004122 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes1523c312012-05-25 12:34:54 -07004123
Kees Cook647416f2013-03-10 14:10:06 -07004124 return 0;
Jesse Barnes1523c312012-05-25 12:34:54 -07004125}
4126
Kees Cook647416f2013-03-10 14:10:06 -07004127static int
4128i915_min_freq_set(void *data, u64 val)
Jesse Barnes1523c312012-05-25 12:34:54 -07004129{
Kees Cook647416f2013-03-10 14:10:06 -07004130 struct drm_device *dev = data;
Jesse Barnes1523c312012-05-25 12:34:54 -07004131 struct drm_i915_private *dev_priv = dev->dev_private;
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004132 u32 rp_state_cap, hw_max, hw_min;
Kees Cook647416f2013-03-10 14:10:06 -07004133 int ret;
Daniel Vetter004777c2012-08-09 15:07:01 +02004134
Tom O'Rourkedaa3afb2014-05-30 16:22:10 -07004135 if (INTEL_INFO(dev)->gen < 6)
Daniel Vetter004777c2012-08-09 15:07:01 +02004136 return -ENODEV;
Jesse Barnes1523c312012-05-25 12:34:54 -07004137
Tom O'Rourke5c9669c2013-09-16 14:56:43 -07004138 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4139
Kees Cook647416f2013-03-10 14:10:06 -07004140 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
Jesse Barnes1523c312012-05-25 12:34:54 -07004141
Jesse Barnes4fc688c2012-11-02 11:14:01 -07004142 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
Daniel Vetter004777c2012-08-09 15:07:01 +02004143 if (ret)
4144 return ret;
4145
Jesse Barnes1523c312012-05-25 12:34:54 -07004146 /*
4147 * Turbo will still be enabled, but won't go below the set value.
4148 */
Jesse Barnes0a073b82013-04-17 15:54:58 -07004149 if (IS_VALLEYVIEW(dev)) {
Ville Syrjälä2ec38152013-11-05 22:42:29 +02004150 val = vlv_freq_opcode(dev_priv, val);
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004151
Ville Syrjälä03af2042014-06-28 02:03:53 +03004152 hw_max = dev_priv->rps.max_freq;
4153 hw_min = dev_priv->rps.min_freq;
Jesse Barnes0a073b82013-04-17 15:54:58 -07004154 } else {
4155 do_div(val, GT_FREQUENCY_MULTIPLIER);
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004156
4157 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
Ben Widawskyb39fb292014-03-19 18:31:11 -07004158 hw_max = dev_priv->rps.max_freq;
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004159 hw_min = (rp_state_cap >> 16) & 0xff;
Jesse Barnes0a073b82013-04-17 15:54:58 -07004160 }
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004161
Ben Widawskyb39fb292014-03-19 18:31:11 -07004162 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004163 mutex_unlock(&dev_priv->rps.hw_lock);
4164 return -EINVAL;
4165 }
4166
Ben Widawskyb39fb292014-03-19 18:31:11 -07004167 dev_priv->rps.min_freq_softlimit = val;
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004168
4169 if (IS_VALLEYVIEW(dev))
4170 valleyview_set_rps(dev, val);
4171 else
4172 gen6_set_rps(dev, val);
4173
Jesse Barnes4fc688c2012-11-02 11:14:01 -07004174 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes1523c312012-05-25 12:34:54 -07004175
Kees Cook647416f2013-03-10 14:10:06 -07004176 return 0;
Jesse Barnes1523c312012-05-25 12:34:54 -07004177}
4178
Kees Cook647416f2013-03-10 14:10:06 -07004179DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4180 i915_min_freq_get, i915_min_freq_set,
Mika Kuoppala3a3b4f92013-04-12 12:10:05 +03004181 "%llu\n");
Jesse Barnes1523c312012-05-25 12:34:54 -07004182
Kees Cook647416f2013-03-10 14:10:06 -07004183static int
4184i915_cache_sharing_get(void *data, u64 *val)
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004185{
Kees Cook647416f2013-03-10 14:10:06 -07004186 struct drm_device *dev = data;
Jani Nikulae277a1f2014-03-31 14:27:14 +03004187 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004188 u32 snpcr;
Kees Cook647416f2013-03-10 14:10:06 -07004189 int ret;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004190
Daniel Vetter004777c2012-08-09 15:07:01 +02004191 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4192 return -ENODEV;
4193
Daniel Vetter22bcfc62012-08-09 15:07:02 +02004194 ret = mutex_lock_interruptible(&dev->struct_mutex);
4195 if (ret)
4196 return ret;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02004197 intel_runtime_pm_get(dev_priv);
Daniel Vetter22bcfc62012-08-09 15:07:02 +02004198
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004199 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02004200
4201 intel_runtime_pm_put(dev_priv);
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004202 mutex_unlock(&dev_priv->dev->struct_mutex);
4203
Kees Cook647416f2013-03-10 14:10:06 -07004204 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004205
Kees Cook647416f2013-03-10 14:10:06 -07004206 return 0;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004207}
4208
Kees Cook647416f2013-03-10 14:10:06 -07004209static int
4210i915_cache_sharing_set(void *data, u64 val)
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004211{
Kees Cook647416f2013-03-10 14:10:06 -07004212 struct drm_device *dev = data;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004213 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004214 u32 snpcr;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004215
Daniel Vetter004777c2012-08-09 15:07:01 +02004216 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4217 return -ENODEV;
4218
Kees Cook647416f2013-03-10 14:10:06 -07004219 if (val > 3)
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004220 return -EINVAL;
4221
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02004222 intel_runtime_pm_get(dev_priv);
Kees Cook647416f2013-03-10 14:10:06 -07004223 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004224
4225 /* Update the cache sharing policy here as well */
4226 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4227 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4228 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4229 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4230
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02004231 intel_runtime_pm_put(dev_priv);
Kees Cook647416f2013-03-10 14:10:06 -07004232 return 0;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004233}
4234
Kees Cook647416f2013-03-10 14:10:06 -07004235DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4236 i915_cache_sharing_get, i915_cache_sharing_set,
4237 "%llu\n");
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004238
Ben Widawsky6d794d42011-04-25 11:25:56 -07004239static int i915_forcewake_open(struct inode *inode, struct file *file)
4240{
4241 struct drm_device *dev = inode->i_private;
4242 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky6d794d42011-04-25 11:25:56 -07004243
Daniel Vetter075edca2012-01-24 09:44:28 +01004244 if (INTEL_INFO(dev)->gen < 6)
Ben Widawsky6d794d42011-04-25 11:25:56 -07004245 return 0;
4246
Deepak Sc8d9a592013-11-23 14:55:42 +05304247 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
Ben Widawsky6d794d42011-04-25 11:25:56 -07004248
4249 return 0;
4250}
4251
Ben Widawskyc43b5632012-04-16 14:07:40 -07004252static int i915_forcewake_release(struct inode *inode, struct file *file)
Ben Widawsky6d794d42011-04-25 11:25:56 -07004253{
4254 struct drm_device *dev = inode->i_private;
4255 struct drm_i915_private *dev_priv = dev->dev_private;
4256
Daniel Vetter075edca2012-01-24 09:44:28 +01004257 if (INTEL_INFO(dev)->gen < 6)
Ben Widawsky6d794d42011-04-25 11:25:56 -07004258 return 0;
4259
Deepak Sc8d9a592013-11-23 14:55:42 +05304260 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
Ben Widawsky6d794d42011-04-25 11:25:56 -07004261
4262 return 0;
4263}
4264
4265static const struct file_operations i915_forcewake_fops = {
4266 .owner = THIS_MODULE,
4267 .open = i915_forcewake_open,
4268 .release = i915_forcewake_release,
4269};
4270
4271static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4272{
4273 struct drm_device *dev = minor->dev;
4274 struct dentry *ent;
4275
4276 ent = debugfs_create_file("i915_forcewake_user",
Ben Widawsky8eb57292011-05-11 15:10:58 -07004277 S_IRUSR,
Ben Widawsky6d794d42011-04-25 11:25:56 -07004278 root, dev,
4279 &i915_forcewake_fops);
Wei Yongjunf3c5fe92013-12-16 14:13:25 +08004280 if (!ent)
4281 return -ENOMEM;
Ben Widawsky6d794d42011-04-25 11:25:56 -07004282
Ben Widawsky8eb57292011-05-11 15:10:58 -07004283 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
Ben Widawsky6d794d42011-04-25 11:25:56 -07004284}
4285
Daniel Vetter6a9c3082011-12-14 13:57:11 +01004286static int i915_debugfs_create(struct dentry *root,
4287 struct drm_minor *minor,
4288 const char *name,
4289 const struct file_operations *fops)
Jesse Barnes358733e2011-07-27 11:53:01 -07004290{
4291 struct drm_device *dev = minor->dev;
4292 struct dentry *ent;
4293
Daniel Vetter6a9c3082011-12-14 13:57:11 +01004294 ent = debugfs_create_file(name,
Jesse Barnes358733e2011-07-27 11:53:01 -07004295 S_IRUGO | S_IWUSR,
4296 root, dev,
Daniel Vetter6a9c3082011-12-14 13:57:11 +01004297 fops);
Wei Yongjunf3c5fe92013-12-16 14:13:25 +08004298 if (!ent)
4299 return -ENOMEM;
Jesse Barnes358733e2011-07-27 11:53:01 -07004300
Daniel Vetter6a9c3082011-12-14 13:57:11 +01004301 return drm_add_fake_info_node(minor, ent, fops);
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004302}
4303
Lespiau, Damien06c5bf82013-10-17 19:09:56 +01004304static const struct drm_info_list i915_debugfs_list[] = {
Chris Wilson311bd682011-01-13 19:06:50 +00004305 {"i915_capabilities", i915_capabilities, 0},
Chris Wilson73aa8082010-09-30 11:46:12 +01004306 {"i915_gem_objects", i915_gem_object_info, 0},
Chris Wilson08c18322011-01-10 00:00:24 +00004307 {"i915_gem_gtt", i915_gem_gtt_info, 0},
Chris Wilson1b502472012-04-24 15:47:30 +01004308 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
Ben Gamari433e12f2009-02-17 20:08:51 -05004309 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
Ben Gamari433e12f2009-02-17 20:08:51 -05004310 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
Chris Wilson6d2b8882013-08-07 18:30:54 +01004311 {"i915_gem_stolen", i915_gem_stolen_list_info },
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01004312 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
Ben Gamari20172632009-02-17 20:08:50 -05004313 {"i915_gem_request", i915_gem_request_info, 0},
4314 {"i915_gem_seqno", i915_gem_seqno_info, 0},
Chris Wilsona6172a82009-02-11 14:26:38 +00004315 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
Ben Gamari20172632009-02-17 20:08:50 -05004316 {"i915_gem_interrupt", i915_interrupt_info, 0},
Chris Wilson1ec14ad2010-12-04 11:30:53 +00004317 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4318 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4319 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
Xiang, Haihao9010ebf2013-05-29 09:22:36 -07004320 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
Deepak Sadb4bd12014-03-31 11:30:02 +05304321 {"i915_frequency_info", i915_frequency_info, 0},
Jesse Barnesf97108d2010-01-29 11:27:07 -08004322 {"i915_drpc_info", i915_drpc_info, 0},
Jesse Barnes7648fa92010-05-20 14:28:11 -07004323 {"i915_emon_status", i915_emon_status, 0},
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07004324 {"i915_ring_freq_table", i915_ring_freq_table, 0},
Jesse Barnesb5e50c32010-02-05 12:42:41 -08004325 {"i915_fbc_status", i915_fbc_status, 0},
Paulo Zanoni92d44622013-05-31 16:33:24 -03004326 {"i915_ips_status", i915_ips_status, 0},
Jesse Barnes4a9bef32010-02-05 12:47:35 -08004327 {"i915_sr_status", i915_sr_status, 0},
Chris Wilson44834a62010-08-19 16:09:23 +01004328 {"i915_opregion", i915_opregion, 0},
Chris Wilson37811fc2010-08-25 22:45:57 +01004329 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
Ben Widawskye76d3632011-03-19 18:14:29 -07004330 {"i915_context_status", i915_context_status, 0},
Ben Widawskyc0ab1ae2014-08-07 13:24:26 +01004331 {"i915_dump_lrc", i915_dump_lrc, 0},
Oscar Mateo4ba70e42014-08-07 13:23:20 +01004332 {"i915_execlists", i915_execlists, 0},
Ben Widawsky6d794d42011-04-25 11:25:56 -07004333 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
Daniel Vetterea16a3c2011-12-14 13:57:16 +01004334 {"i915_swizzle_info", i915_swizzle_info, 0},
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01004335 {"i915_ppgtt_info", i915_ppgtt_info, 0},
Ben Widawsky63573eb2013-07-04 11:02:07 -07004336 {"i915_llc", i915_llc, 0},
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03004337 {"i915_edp_psr_status", i915_edp_psr_status, 0},
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02004338 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
Jesse Barnesec013e72013-08-20 10:29:23 +01004339 {"i915_energy_uJ", i915_energy_uJ, 0},
Paulo Zanoni371db662013-08-19 13:18:10 -03004340 {"i915_pc8_status", i915_pc8_status, 0},
Imre Deak1da51582013-11-25 17:15:35 +02004341 {"i915_power_domain_info", i915_power_domain_info, 0},
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08004342 {"i915_display_info", i915_display_info, 0},
Ben Widawskye04934c2014-06-30 09:53:42 -07004343 {"i915_semaphore_status", i915_semaphore_status, 0},
Daniel Vetter728e29d2014-06-25 22:01:53 +03004344 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
Dave Airlie11bed9582014-05-12 15:22:27 +10004345 {"i915_dp_mst_info", i915_dp_mst_info, 0},
Damien Lespiau1ed1ef92014-08-30 16:50:59 +01004346 {"i915_wa_registers", i915_wa_registers, 0},
Damien Lespiauc5511e42014-11-04 17:06:51 +00004347 {"i915_ddb_info", i915_ddb_info, 0},
Ben Gamari20172632009-02-17 20:08:50 -05004348};
Ben Gamari27c202a2009-07-01 22:26:52 -04004349#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
Ben Gamari20172632009-02-17 20:08:50 -05004350
Lespiau, Damien06c5bf82013-10-17 19:09:56 +01004351static const struct i915_debugfs_files {
Daniel Vetter34b96742013-07-04 20:49:44 +02004352 const char *name;
4353 const struct file_operations *fops;
4354} i915_debugfs_files[] = {
4355 {"i915_wedged", &i915_wedged_fops},
4356 {"i915_max_freq", &i915_max_freq_fops},
4357 {"i915_min_freq", &i915_min_freq_fops},
4358 {"i915_cache_sharing", &i915_cache_sharing_fops},
4359 {"i915_ring_stop", &i915_ring_stop_fops},
Chris Wilson094f9a52013-09-25 17:34:55 +01004360 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4361 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
Daniel Vetter34b96742013-07-04 20:49:44 +02004362 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4363 {"i915_error_state", &i915_error_state_fops},
4364 {"i915_next_seqno", &i915_next_seqno_fops},
Damien Lespiaubd9db022013-10-15 18:55:36 +01004365 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
Ville Syrjälä369a1342014-01-22 14:36:08 +02004366 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4367 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4368 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
Rodrigo Vivida46f932014-08-01 02:04:45 -07004369 {"i915_fbc_false_color", &i915_fbc_fc_fops},
Daniel Vetter34b96742013-07-04 20:49:44 +02004370};
4371
Damien Lespiau07144422013-10-15 18:55:40 +01004372void intel_display_crc_init(struct drm_device *dev)
4373{
4374 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterb3783602013-11-14 11:30:42 +01004375 enum pipe pipe;
Damien Lespiau07144422013-10-15 18:55:40 +01004376
Damien Lespiau055e3932014-08-18 13:49:10 +01004377 for_each_pipe(dev_priv, pipe) {
Daniel Vetterb3783602013-11-14 11:30:42 +01004378 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
Damien Lespiau07144422013-10-15 18:55:40 +01004379
Damien Lespiaud538bbd2013-10-21 14:29:30 +01004380 pipe_crc->opened = false;
4381 spin_lock_init(&pipe_crc->lock);
Damien Lespiau07144422013-10-15 18:55:40 +01004382 init_waitqueue_head(&pipe_crc->wq);
4383 }
4384}
4385
Ben Gamari27c202a2009-07-01 22:26:52 -04004386int i915_debugfs_init(struct drm_minor *minor)
Ben Gamari20172632009-02-17 20:08:50 -05004387{
Daniel Vetter34b96742013-07-04 20:49:44 +02004388 int ret, i;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01004389
Ben Widawsky6d794d42011-04-25 11:25:56 -07004390 ret = i915_forcewake_create(minor->debugfs_root, minor);
4391 if (ret)
4392 return ret;
Daniel Vetter6a9c3082011-12-14 13:57:11 +01004393
Damien Lespiau07144422013-10-15 18:55:40 +01004394 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4395 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4396 if (ret)
4397 return ret;
4398 }
4399
Daniel Vetter34b96742013-07-04 20:49:44 +02004400 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4401 ret = i915_debugfs_create(minor->debugfs_root, minor,
4402 i915_debugfs_files[i].name,
4403 i915_debugfs_files[i].fops);
4404 if (ret)
4405 return ret;
4406 }
Mika Kuoppala40633212012-12-04 15:12:00 +02004407
Ben Gamari27c202a2009-07-01 22:26:52 -04004408 return drm_debugfs_create_files(i915_debugfs_list,
4409 I915_DEBUGFS_ENTRIES,
Ben Gamari20172632009-02-17 20:08:50 -05004410 minor->debugfs_root, minor);
4411}
4412
Ben Gamari27c202a2009-07-01 22:26:52 -04004413void i915_debugfs_cleanup(struct drm_minor *minor)
Ben Gamari20172632009-02-17 20:08:50 -05004414{
Daniel Vetter34b96742013-07-04 20:49:44 +02004415 int i;
4416
Ben Gamari27c202a2009-07-01 22:26:52 -04004417 drm_debugfs_remove_files(i915_debugfs_list,
4418 I915_DEBUGFS_ENTRIES, minor);
Damien Lespiau07144422013-10-15 18:55:40 +01004419
Ben Widawsky6d794d42011-04-25 11:25:56 -07004420 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4421 1, minor);
Damien Lespiau07144422013-10-15 18:55:40 +01004422
Daniel Vettere309a992013-10-16 22:55:51 +02004423 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
Damien Lespiau07144422013-10-15 18:55:40 +01004424 struct drm_info_list *info_list =
4425 (struct drm_info_list *)&i915_pipe_crc_data[i];
4426
4427 drm_debugfs_remove_files(info_list, 1, minor);
4428 }
4429
Daniel Vetter34b96742013-07-04 20:49:44 +02004430 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4431 struct drm_info_list *info_list =
4432 (struct drm_info_list *) i915_debugfs_files[i].fops;
4433
4434 drm_debugfs_remove_files(info_list, 1, minor);
4435 }
Ben Gamari20172632009-02-17 20:08:50 -05004436}