Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Keith Packard <keithp@keithp.com> |
| 26 | * |
| 27 | */ |
| 28 | |
| 29 | #include <linux/seq_file.h> |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 30 | #include <linux/circ_buf.h> |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 31 | #include <linux/ctype.h> |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 32 | #include <linux/debugfs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 33 | #include <linux/slab.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 34 | #include <linux/export.h> |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 35 | #include <linux/list_sort.h> |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 36 | #include <asm/msr-index.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 37 | #include <drm/drmP.h> |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 38 | #include "intel_drv.h" |
Chris Wilson | e5c6526 | 2010-11-01 11:35:28 +0000 | [diff] [blame] | 39 | #include "intel_ringbuffer.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 40 | #include <drm/i915_drm.h> |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 41 | #include "i915_drv.h" |
| 42 | |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 43 | enum { |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 44 | ACTIVE_LIST, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 45 | INACTIVE_LIST, |
Chris Wilson | d21d597 | 2010-09-26 11:19:33 +0100 | [diff] [blame] | 46 | PINNED_LIST, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 47 | }; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 48 | |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 49 | static const char *yesno(int v) |
| 50 | { |
| 51 | return v ? "yes" : "no"; |
| 52 | } |
| 53 | |
Damien Lespiau | 497666d | 2013-10-15 18:55:39 +0100 | [diff] [blame] | 54 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
| 55 | * allocated we need to hook into the minor for release. */ |
| 56 | static int |
| 57 | drm_add_fake_info_node(struct drm_minor *minor, |
| 58 | struct dentry *ent, |
| 59 | const void *key) |
| 60 | { |
| 61 | struct drm_info_node *node; |
| 62 | |
| 63 | node = kmalloc(sizeof(*node), GFP_KERNEL); |
| 64 | if (node == NULL) { |
| 65 | debugfs_remove(ent); |
| 66 | return -ENOMEM; |
| 67 | } |
| 68 | |
| 69 | node->minor = minor; |
| 70 | node->dent = ent; |
| 71 | node->info_ent = (void *) key; |
| 72 | |
| 73 | mutex_lock(&minor->debugfs_lock); |
| 74 | list_add(&node->list, &minor->debugfs_list); |
| 75 | mutex_unlock(&minor->debugfs_lock); |
| 76 | |
| 77 | return 0; |
| 78 | } |
| 79 | |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 80 | static int i915_capabilities(struct seq_file *m, void *data) |
| 81 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 82 | struct drm_info_node *node = m->private; |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 83 | struct drm_device *dev = node->minor->dev; |
| 84 | const struct intel_device_info *info = INTEL_INFO(dev); |
| 85 | |
| 86 | seq_printf(m, "gen: %d\n", info->gen); |
Paulo Zanoni | 03d00ac | 2011-10-14 18:17:41 -0300 | [diff] [blame] | 87 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 88 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
| 89 | #define SEP_SEMICOLON ; |
| 90 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); |
| 91 | #undef PRINT_FLAG |
| 92 | #undef SEP_SEMICOLON |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 93 | |
| 94 | return 0; |
| 95 | } |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 96 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 97 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 98 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 99 | if (obj->user_pin_count > 0) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 100 | return "P"; |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 101 | else if (i915_gem_obj_is_pinned(obj)) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 102 | return "p"; |
| 103 | else |
| 104 | return " "; |
| 105 | } |
| 106 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 107 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 108 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 109 | switch (obj->tiling_mode) { |
| 110 | default: |
| 111 | case I915_TILING_NONE: return " "; |
| 112 | case I915_TILING_X: return "X"; |
| 113 | case I915_TILING_Y: return "Y"; |
| 114 | } |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 115 | } |
| 116 | |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 117 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
| 118 | { |
| 119 | return obj->has_global_gtt_mapping ? "g" : " "; |
| 120 | } |
| 121 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 122 | static void |
| 123 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) |
| 124 | { |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 125 | struct i915_vma *vma; |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 126 | int pin_count = 0; |
| 127 | |
Ville Syrjälä | fb1ae91 | 2013-08-22 19:21:30 +0300 | [diff] [blame] | 128 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 129 | &obj->base, |
| 130 | get_pin_flag(obj), |
| 131 | get_tiling_flag(obj), |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 132 | get_global_flag(obj), |
Eric Anholt | a05a586 | 2011-12-20 08:54:15 -0800 | [diff] [blame] | 133 | obj->base.size / 1024, |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 134 | obj->base.read_domains, |
| 135 | obj->base.write_domain, |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 136 | obj->last_read_seqno, |
| 137 | obj->last_write_seqno, |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 138 | obj->last_fenced_seqno, |
Chris Wilson | 0a4cd7c | 2014-08-22 14:41:39 +0100 | [diff] [blame] | 139 | i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level), |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 140 | obj->dirty ? " dirty" : "", |
| 141 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); |
| 142 | if (obj->base.name) |
| 143 | seq_printf(m, " (name: %d)", obj->base.name); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 144 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 145 | if (vma->pin_count > 0) |
| 146 | pin_count++; |
| 147 | seq_printf(m, " (pinned x %d)", pin_count); |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 148 | if (obj->pin_display) |
| 149 | seq_printf(m, " (display)"); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 150 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
| 151 | seq_printf(m, " (fence: %d)", obj->fence_reg); |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 152 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
| 153 | if (!i915_is_ggtt(vma->vm)) |
| 154 | seq_puts(m, " (pp"); |
| 155 | else |
| 156 | seq_puts(m, " (g"); |
| 157 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", |
| 158 | vma->node.start, vma->node.size); |
| 159 | } |
Chris Wilson | c1ad11f | 2012-11-15 11:32:21 +0000 | [diff] [blame] | 160 | if (obj->stolen) |
| 161 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 162 | if (obj->pin_mappable || obj->fault_mappable) { |
| 163 | char s[3], *t = s; |
| 164 | if (obj->pin_mappable) |
| 165 | *t++ = 'p'; |
| 166 | if (obj->fault_mappable) |
| 167 | *t++ = 'f'; |
| 168 | *t = '\0'; |
| 169 | seq_printf(m, " (%s mappable)", s); |
| 170 | } |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 171 | if (obj->ring != NULL) |
| 172 | seq_printf(m, " (%s)", obj->ring->name); |
Daniel Vetter | d5a81ef | 2014-06-18 14:46:49 +0200 | [diff] [blame] | 173 | if (obj->frontbuffer_bits) |
| 174 | seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 175 | } |
| 176 | |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 177 | static void describe_ctx(struct seq_file *m, struct intel_context *ctx) |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 178 | { |
Oscar Mateo | ea0c76f | 2014-07-03 16:27:59 +0100 | [diff] [blame] | 179 | seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i'); |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 180 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
| 181 | seq_putc(m, ' '); |
| 182 | } |
| 183 | |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 184 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 185 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 186 | struct drm_info_node *node = m->private; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 187 | uintptr_t list = (uintptr_t) node->info_ent->data; |
| 188 | struct list_head *head; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 189 | struct drm_device *dev = node->minor->dev; |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 190 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 191 | struct i915_address_space *vm = &dev_priv->gtt.base; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 192 | struct i915_vma *vma; |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 193 | size_t total_obj_size, total_gtt_size; |
| 194 | int count, ret; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 195 | |
| 196 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 197 | if (ret) |
| 198 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 199 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 200 | /* FIXME: the user of this interface might want more than just GGTT */ |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 201 | switch (list) { |
| 202 | case ACTIVE_LIST: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 203 | seq_puts(m, "Active:\n"); |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 204 | head = &vm->active_list; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 205 | break; |
| 206 | case INACTIVE_LIST: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 207 | seq_puts(m, "Inactive:\n"); |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 208 | head = &vm->inactive_list; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 209 | break; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 210 | default: |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 211 | mutex_unlock(&dev->struct_mutex); |
| 212 | return -EINVAL; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 213 | } |
| 214 | |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 215 | total_obj_size = total_gtt_size = count = 0; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 216 | list_for_each_entry(vma, head, mm_list) { |
| 217 | seq_printf(m, " "); |
| 218 | describe_obj(m, vma->obj); |
| 219 | seq_printf(m, "\n"); |
| 220 | total_obj_size += vma->obj->base.size; |
| 221 | total_gtt_size += vma->node.size; |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 222 | count++; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 223 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 224 | mutex_unlock(&dev->struct_mutex); |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 225 | |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 226 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 227 | count, total_obj_size, total_gtt_size); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 228 | return 0; |
| 229 | } |
| 230 | |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 231 | static int obj_rank_by_stolen(void *priv, |
| 232 | struct list_head *A, struct list_head *B) |
| 233 | { |
| 234 | struct drm_i915_gem_object *a = |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 235 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 236 | struct drm_i915_gem_object *b = |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 237 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 238 | |
| 239 | return a->stolen->start - b->stolen->start; |
| 240 | } |
| 241 | |
| 242 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) |
| 243 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 244 | struct drm_info_node *node = m->private; |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 245 | struct drm_device *dev = node->minor->dev; |
| 246 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 247 | struct drm_i915_gem_object *obj; |
| 248 | size_t total_obj_size, total_gtt_size; |
| 249 | LIST_HEAD(stolen); |
| 250 | int count, ret; |
| 251 | |
| 252 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 253 | if (ret) |
| 254 | return ret; |
| 255 | |
| 256 | total_obj_size = total_gtt_size = count = 0; |
| 257 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
| 258 | if (obj->stolen == NULL) |
| 259 | continue; |
| 260 | |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 261 | list_add(&obj->obj_exec_link, &stolen); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 262 | |
| 263 | total_obj_size += obj->base.size; |
| 264 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
| 265 | count++; |
| 266 | } |
| 267 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
| 268 | if (obj->stolen == NULL) |
| 269 | continue; |
| 270 | |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 271 | list_add(&obj->obj_exec_link, &stolen); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 272 | |
| 273 | total_obj_size += obj->base.size; |
| 274 | count++; |
| 275 | } |
| 276 | list_sort(NULL, &stolen, obj_rank_by_stolen); |
| 277 | seq_puts(m, "Stolen:\n"); |
| 278 | while (!list_empty(&stolen)) { |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 279 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 280 | seq_puts(m, " "); |
| 281 | describe_obj(m, obj); |
| 282 | seq_putc(m, '\n'); |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 283 | list_del_init(&obj->obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 284 | } |
| 285 | mutex_unlock(&dev->struct_mutex); |
| 286 | |
| 287 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 288 | count, total_obj_size, total_gtt_size); |
| 289 | return 0; |
| 290 | } |
| 291 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 292 | #define count_objects(list, member) do { \ |
| 293 | list_for_each_entry(obj, list, member) { \ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 294 | size += i915_gem_obj_ggtt_size(obj); \ |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 295 | ++count; \ |
| 296 | if (obj->map_and_fenceable) { \ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 297 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 298 | ++mappable_count; \ |
| 299 | } \ |
| 300 | } \ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 301 | } while (0) |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 302 | |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 303 | struct file_stats { |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 304 | struct drm_i915_file_private *file_priv; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 305 | int count; |
Chris Wilson | c67a17e | 2014-03-19 13:45:46 +0000 | [diff] [blame] | 306 | size_t total, unbound; |
| 307 | size_t global, shared; |
| 308 | size_t active, inactive; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 309 | }; |
| 310 | |
| 311 | static int per_file_stats(int id, void *ptr, void *data) |
| 312 | { |
| 313 | struct drm_i915_gem_object *obj = ptr; |
| 314 | struct file_stats *stats = data; |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 315 | struct i915_vma *vma; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 316 | |
| 317 | stats->count++; |
| 318 | stats->total += obj->base.size; |
| 319 | |
Chris Wilson | c67a17e | 2014-03-19 13:45:46 +0000 | [diff] [blame] | 320 | if (obj->base.name || obj->base.dma_buf) |
| 321 | stats->shared += obj->base.size; |
| 322 | |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 323 | if (USES_FULL_PPGTT(obj->base.dev)) { |
| 324 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
| 325 | struct i915_hw_ppgtt *ppgtt; |
| 326 | |
| 327 | if (!drm_mm_node_allocated(&vma->node)) |
| 328 | continue; |
| 329 | |
| 330 | if (i915_is_ggtt(vma->vm)) { |
| 331 | stats->global += obj->base.size; |
| 332 | continue; |
| 333 | } |
| 334 | |
| 335 | ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base); |
Daniel Vetter | 4d88470 | 2014-08-06 15:04:47 +0200 | [diff] [blame] | 336 | if (ppgtt->file_priv != stats->file_priv) |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 337 | continue; |
| 338 | |
| 339 | if (obj->ring) /* XXX per-vma statistic */ |
| 340 | stats->active += obj->base.size; |
| 341 | else |
| 342 | stats->inactive += obj->base.size; |
| 343 | |
| 344 | return 0; |
| 345 | } |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 346 | } else { |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 347 | if (i915_gem_obj_ggtt_bound(obj)) { |
| 348 | stats->global += obj->base.size; |
| 349 | if (obj->ring) |
| 350 | stats->active += obj->base.size; |
| 351 | else |
| 352 | stats->inactive += obj->base.size; |
| 353 | return 0; |
| 354 | } |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 355 | } |
| 356 | |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 357 | if (!list_empty(&obj->global_list)) |
| 358 | stats->unbound += obj->base.size; |
| 359 | |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 360 | return 0; |
| 361 | } |
| 362 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 363 | #define count_vmas(list, member) do { \ |
| 364 | list_for_each_entry(vma, list, member) { \ |
| 365 | size += i915_gem_obj_ggtt_size(vma->obj); \ |
| 366 | ++count; \ |
| 367 | if (vma->obj->map_and_fenceable) { \ |
| 368 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ |
| 369 | ++mappable_count; \ |
| 370 | } \ |
| 371 | } \ |
| 372 | } while (0) |
| 373 | |
| 374 | static int i915_gem_object_info(struct seq_file *m, void* data) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 375 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 376 | struct drm_info_node *node = m->private; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 377 | struct drm_device *dev = node->minor->dev; |
| 378 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 379 | u32 count, mappable_count, purgeable_count; |
| 380 | size_t size, mappable_size, purgeable_size; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 381 | struct drm_i915_gem_object *obj; |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 382 | struct i915_address_space *vm = &dev_priv->gtt.base; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 383 | struct drm_file *file; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 384 | struct i915_vma *vma; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 385 | int ret; |
| 386 | |
| 387 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 388 | if (ret) |
| 389 | return ret; |
| 390 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 391 | seq_printf(m, "%u objects, %zu bytes\n", |
| 392 | dev_priv->mm.object_count, |
| 393 | dev_priv->mm.object_memory); |
| 394 | |
| 395 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 396 | count_objects(&dev_priv->mm.bound_list, global_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 397 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
| 398 | count, mappable_count, size, mappable_size); |
| 399 | |
| 400 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 401 | count_vmas(&vm->active_list, mm_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 402 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
| 403 | count, mappable_count, size, mappable_size); |
| 404 | |
| 405 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 406 | count_vmas(&vm->inactive_list, mm_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 407 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
| 408 | count, mappable_count, size, mappable_size); |
| 409 | |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 410 | size = count = purgeable_size = purgeable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 411 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 412 | size += obj->base.size, ++count; |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 413 | if (obj->madv == I915_MADV_DONTNEED) |
| 414 | purgeable_size += obj->base.size, ++purgeable_count; |
| 415 | } |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 416 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
| 417 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 418 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 419 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 420 | if (obj->fault_mappable) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 421 | size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 422 | ++count; |
| 423 | } |
| 424 | if (obj->pin_mappable) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 425 | mappable_size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 426 | ++mappable_count; |
| 427 | } |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 428 | if (obj->madv == I915_MADV_DONTNEED) { |
| 429 | purgeable_size += obj->base.size; |
| 430 | ++purgeable_count; |
| 431 | } |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 432 | } |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 433 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
| 434 | purgeable_count, purgeable_size); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 435 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
| 436 | mappable_count, mappable_size); |
| 437 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", |
| 438 | count, size); |
| 439 | |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 440 | seq_printf(m, "%zu [%lu] gtt total\n", |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 441 | dev_priv->gtt.base.total, |
| 442 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 443 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 444 | seq_putc(m, '\n'); |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 445 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
| 446 | struct file_stats stats; |
Tetsuo Handa | 3ec2f42 | 2014-01-03 20:42:18 +0900 | [diff] [blame] | 447 | struct task_struct *task; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 448 | |
| 449 | memset(&stats, 0, sizeof(stats)); |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 450 | stats.file_priv = file->driver_priv; |
Chris Wilson | 5b5ffff | 2014-06-17 09:56:24 +0100 | [diff] [blame] | 451 | spin_lock(&file->table_lock); |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 452 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
Chris Wilson | 5b5ffff | 2014-06-17 09:56:24 +0100 | [diff] [blame] | 453 | spin_unlock(&file->table_lock); |
Tetsuo Handa | 3ec2f42 | 2014-01-03 20:42:18 +0900 | [diff] [blame] | 454 | /* |
| 455 | * Although we have a valid reference on file->pid, that does |
| 456 | * not guarantee that the task_struct who called get_pid() is |
| 457 | * still alive (e.g. get_pid(current) => fork() => exit()). |
| 458 | * Therefore, we need to protect this ->comm access using RCU. |
| 459 | */ |
| 460 | rcu_read_lock(); |
| 461 | task = pid_task(file->pid, PIDTYPE_PID); |
Chris Wilson | c67a17e | 2014-03-19 13:45:46 +0000 | [diff] [blame] | 462 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", |
Tetsuo Handa | 3ec2f42 | 2014-01-03 20:42:18 +0900 | [diff] [blame] | 463 | task ? task->comm : "<unknown>", |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 464 | stats.count, |
| 465 | stats.total, |
| 466 | stats.active, |
| 467 | stats.inactive, |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 468 | stats.global, |
Chris Wilson | c67a17e | 2014-03-19 13:45:46 +0000 | [diff] [blame] | 469 | stats.shared, |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 470 | stats.unbound); |
Tetsuo Handa | 3ec2f42 | 2014-01-03 20:42:18 +0900 | [diff] [blame] | 471 | rcu_read_unlock(); |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 472 | } |
| 473 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 474 | mutex_unlock(&dev->struct_mutex); |
| 475 | |
| 476 | return 0; |
| 477 | } |
| 478 | |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 479 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 480 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 481 | struct drm_info_node *node = m->private; |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 482 | struct drm_device *dev = node->minor->dev; |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 483 | uintptr_t list = (uintptr_t) node->info_ent->data; |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 484 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 485 | struct drm_i915_gem_object *obj; |
| 486 | size_t total_obj_size, total_gtt_size; |
| 487 | int count, ret; |
| 488 | |
| 489 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 490 | if (ret) |
| 491 | return ret; |
| 492 | |
| 493 | total_obj_size = total_gtt_size = count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 494 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 495 | if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 496 | continue; |
| 497 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 498 | seq_puts(m, " "); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 499 | describe_obj(m, obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 500 | seq_putc(m, '\n'); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 501 | total_obj_size += obj->base.size; |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 502 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 503 | count++; |
| 504 | } |
| 505 | |
| 506 | mutex_unlock(&dev->struct_mutex); |
| 507 | |
| 508 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 509 | count, total_obj_size, total_gtt_size); |
| 510 | |
| 511 | return 0; |
| 512 | } |
| 513 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 514 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
| 515 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 516 | struct drm_info_node *node = m->private; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 517 | struct drm_device *dev = node->minor->dev; |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 518 | struct drm_i915_private *dev_priv = dev->dev_private; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 519 | struct intel_crtc *crtc; |
Daniel Vetter | 8a270eb | 2014-06-17 22:34:37 +0200 | [diff] [blame] | 520 | int ret; |
| 521 | |
| 522 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 523 | if (ret) |
| 524 | return ret; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 525 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 526 | for_each_intel_crtc(dev, crtc) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 527 | const char pipe = pipe_name(crtc->pipe); |
| 528 | const char plane = plane_name(crtc->plane); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 529 | struct intel_unpin_work *work; |
| 530 | |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 531 | spin_lock_irq(&dev->event_lock); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 532 | work = crtc->unpin_work; |
| 533 | if (work == NULL) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 534 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 535 | pipe, plane); |
| 536 | } else { |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 537 | u32 addr; |
| 538 | |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 539 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 540 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 541 | pipe, plane); |
| 542 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 543 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 544 | pipe, plane); |
| 545 | } |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 546 | if (work->flip_queued_ring) { |
| 547 | seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n", |
| 548 | work->flip_queued_ring->name, |
| 549 | work->flip_queued_seqno, |
| 550 | dev_priv->next_seqno, |
| 551 | work->flip_queued_ring->get_seqno(work->flip_queued_ring, true), |
| 552 | i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true), |
| 553 | work->flip_queued_seqno)); |
| 554 | } else |
| 555 | seq_printf(m, "Flip not associated with any ring\n"); |
| 556 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", |
| 557 | work->flip_queued_vblank, |
| 558 | work->flip_ready_vblank, |
| 559 | drm_vblank_count(dev, crtc->pipe)); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 560 | if (work->enable_stall_check) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 561 | seq_puts(m, "Stall check enabled, "); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 562 | else |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 563 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 564 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 565 | |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 566 | if (INTEL_INFO(dev)->gen >= 4) |
| 567 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); |
| 568 | else |
| 569 | addr = I915_READ(DSPADDR(crtc->plane)); |
| 570 | seq_printf(m, "Current scanout address 0x%08x\n", addr); |
| 571 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 572 | if (work->pending_flip_obj) { |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 573 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); |
| 574 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 575 | } |
| 576 | } |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 577 | spin_unlock_irq(&dev->event_lock); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 578 | } |
| 579 | |
Daniel Vetter | 8a270eb | 2014-06-17 22:34:37 +0200 | [diff] [blame] | 580 | mutex_unlock(&dev->struct_mutex); |
| 581 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 582 | return 0; |
| 583 | } |
| 584 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 585 | static int i915_gem_request_info(struct seq_file *m, void *data) |
| 586 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 587 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 588 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 589 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 590 | struct intel_engine_cs *ring; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 591 | struct drm_i915_gem_request *gem_request; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 592 | int ret, count, i; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 593 | |
| 594 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 595 | if (ret) |
| 596 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 597 | |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 598 | count = 0; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 599 | for_each_ring(ring, dev_priv, i) { |
| 600 | if (list_empty(&ring->request_list)) |
| 601 | continue; |
| 602 | |
| 603 | seq_printf(m, "%s requests:\n", ring->name); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 604 | list_for_each_entry(gem_request, |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 605 | &ring->request_list, |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 606 | list) { |
| 607 | seq_printf(m, " %d @ %d\n", |
| 608 | gem_request->seqno, |
| 609 | (int) (jiffies - gem_request->emitted_jiffies)); |
| 610 | } |
| 611 | count++; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 612 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 613 | mutex_unlock(&dev->struct_mutex); |
| 614 | |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 615 | if (count == 0) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 616 | seq_puts(m, "No requests\n"); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 617 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 618 | return 0; |
| 619 | } |
| 620 | |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 621 | static void i915_ring_seqno_info(struct seq_file *m, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 622 | struct intel_engine_cs *ring) |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 623 | { |
| 624 | if (ring->get_seqno) { |
Mika Kuoppala | 43a7b92 | 2012-12-04 15:12:01 +0200 | [diff] [blame] | 625 | seq_printf(m, "Current sequence (%s): %u\n", |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 626 | ring->name, ring->get_seqno(ring, false)); |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 627 | } |
| 628 | } |
| 629 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 630 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
| 631 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 632 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 633 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 634 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 635 | struct intel_engine_cs *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 636 | int ret, i; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 637 | |
| 638 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 639 | if (ret) |
| 640 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 641 | intel_runtime_pm_get(dev_priv); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 642 | |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 643 | for_each_ring(ring, dev_priv, i) |
| 644 | i915_ring_seqno_info(m, ring); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 645 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 646 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 647 | mutex_unlock(&dev->struct_mutex); |
| 648 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 649 | return 0; |
| 650 | } |
| 651 | |
| 652 | |
| 653 | static int i915_interrupt_info(struct seq_file *m, void *data) |
| 654 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 655 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 656 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 657 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 658 | struct intel_engine_cs *ring; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 659 | int ret, i, pipe; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 660 | |
| 661 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 662 | if (ret) |
| 663 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 664 | intel_runtime_pm_get(dev_priv); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 665 | |
Ville Syrjälä | 74e1ca8 | 2014-04-09 13:28:09 +0300 | [diff] [blame] | 666 | if (IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | 74e1ca8 | 2014-04-09 13:28:09 +0300 | [diff] [blame] | 667 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
| 668 | I915_READ(GEN8_MASTER_IRQ)); |
| 669 | |
| 670 | seq_printf(m, "Display IER:\t%08x\n", |
| 671 | I915_READ(VLV_IER)); |
| 672 | seq_printf(m, "Display IIR:\t%08x\n", |
| 673 | I915_READ(VLV_IIR)); |
| 674 | seq_printf(m, "Display IIR_RW:\t%08x\n", |
| 675 | I915_READ(VLV_IIR_RW)); |
| 676 | seq_printf(m, "Display IMR:\t%08x\n", |
| 677 | I915_READ(VLV_IMR)); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 678 | for_each_pipe(dev_priv, pipe) |
Ville Syrjälä | 74e1ca8 | 2014-04-09 13:28:09 +0300 | [diff] [blame] | 679 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
| 680 | pipe_name(pipe), |
| 681 | I915_READ(PIPESTAT(pipe))); |
| 682 | |
| 683 | seq_printf(m, "Port hotplug:\t%08x\n", |
| 684 | I915_READ(PORT_HOTPLUG_EN)); |
| 685 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", |
| 686 | I915_READ(VLV_DPFLIPSTAT)); |
| 687 | seq_printf(m, "DPINVGTT:\t%08x\n", |
| 688 | I915_READ(DPINVGTT)); |
| 689 | |
| 690 | for (i = 0; i < 4; i++) { |
| 691 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", |
| 692 | i, I915_READ(GEN8_GT_IMR(i))); |
| 693 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", |
| 694 | i, I915_READ(GEN8_GT_IIR(i))); |
| 695 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", |
| 696 | i, I915_READ(GEN8_GT_IER(i))); |
| 697 | } |
| 698 | |
| 699 | seq_printf(m, "PCU interrupt mask:\t%08x\n", |
| 700 | I915_READ(GEN8_PCU_IMR)); |
| 701 | seq_printf(m, "PCU interrupt identity:\t%08x\n", |
| 702 | I915_READ(GEN8_PCU_IIR)); |
| 703 | seq_printf(m, "PCU interrupt enable:\t%08x\n", |
| 704 | I915_READ(GEN8_PCU_IER)); |
| 705 | } else if (INTEL_INFO(dev)->gen >= 8) { |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 706 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
| 707 | I915_READ(GEN8_MASTER_IRQ)); |
| 708 | |
| 709 | for (i = 0; i < 4; i++) { |
| 710 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", |
| 711 | i, I915_READ(GEN8_GT_IMR(i))); |
| 712 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", |
| 713 | i, I915_READ(GEN8_GT_IIR(i))); |
| 714 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", |
| 715 | i, I915_READ(GEN8_GT_IER(i))); |
| 716 | } |
| 717 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 718 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 719 | if (!intel_display_power_is_enabled(dev_priv, |
Paulo Zanoni | 22c5996 | 2014-08-08 17:45:32 -0300 | [diff] [blame] | 720 | POWER_DOMAIN_PIPE(pipe))) { |
| 721 | seq_printf(m, "Pipe %c power disabled\n", |
| 722 | pipe_name(pipe)); |
| 723 | continue; |
| 724 | } |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 725 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 726 | pipe_name(pipe), |
| 727 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 728 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 729 | pipe_name(pipe), |
| 730 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 731 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 732 | pipe_name(pipe), |
| 733 | I915_READ(GEN8_DE_PIPE_IER(pipe))); |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 734 | } |
| 735 | |
| 736 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", |
| 737 | I915_READ(GEN8_DE_PORT_IMR)); |
| 738 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", |
| 739 | I915_READ(GEN8_DE_PORT_IIR)); |
| 740 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", |
| 741 | I915_READ(GEN8_DE_PORT_IER)); |
| 742 | |
| 743 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", |
| 744 | I915_READ(GEN8_DE_MISC_IMR)); |
| 745 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", |
| 746 | I915_READ(GEN8_DE_MISC_IIR)); |
| 747 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", |
| 748 | I915_READ(GEN8_DE_MISC_IER)); |
| 749 | |
| 750 | seq_printf(m, "PCU interrupt mask:\t%08x\n", |
| 751 | I915_READ(GEN8_PCU_IMR)); |
| 752 | seq_printf(m, "PCU interrupt identity:\t%08x\n", |
| 753 | I915_READ(GEN8_PCU_IIR)); |
| 754 | seq_printf(m, "PCU interrupt enable:\t%08x\n", |
| 755 | I915_READ(GEN8_PCU_IER)); |
| 756 | } else if (IS_VALLEYVIEW(dev)) { |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 757 | seq_printf(m, "Display IER:\t%08x\n", |
| 758 | I915_READ(VLV_IER)); |
| 759 | seq_printf(m, "Display IIR:\t%08x\n", |
| 760 | I915_READ(VLV_IIR)); |
| 761 | seq_printf(m, "Display IIR_RW:\t%08x\n", |
| 762 | I915_READ(VLV_IIR_RW)); |
| 763 | seq_printf(m, "Display IMR:\t%08x\n", |
| 764 | I915_READ(VLV_IMR)); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 765 | for_each_pipe(dev_priv, pipe) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 766 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
| 767 | pipe_name(pipe), |
| 768 | I915_READ(PIPESTAT(pipe))); |
| 769 | |
| 770 | seq_printf(m, "Master IER:\t%08x\n", |
| 771 | I915_READ(VLV_MASTER_IER)); |
| 772 | |
| 773 | seq_printf(m, "Render IER:\t%08x\n", |
| 774 | I915_READ(GTIER)); |
| 775 | seq_printf(m, "Render IIR:\t%08x\n", |
| 776 | I915_READ(GTIIR)); |
| 777 | seq_printf(m, "Render IMR:\t%08x\n", |
| 778 | I915_READ(GTIMR)); |
| 779 | |
| 780 | seq_printf(m, "PM IER:\t\t%08x\n", |
| 781 | I915_READ(GEN6_PMIER)); |
| 782 | seq_printf(m, "PM IIR:\t\t%08x\n", |
| 783 | I915_READ(GEN6_PMIIR)); |
| 784 | seq_printf(m, "PM IMR:\t\t%08x\n", |
| 785 | I915_READ(GEN6_PMIMR)); |
| 786 | |
| 787 | seq_printf(m, "Port hotplug:\t%08x\n", |
| 788 | I915_READ(PORT_HOTPLUG_EN)); |
| 789 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", |
| 790 | I915_READ(VLV_DPFLIPSTAT)); |
| 791 | seq_printf(m, "DPINVGTT:\t%08x\n", |
| 792 | I915_READ(DPINVGTT)); |
| 793 | |
| 794 | } else if (!HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 5f6a169 | 2009-08-10 21:37:24 +0800 | [diff] [blame] | 795 | seq_printf(m, "Interrupt enable: %08x\n", |
| 796 | I915_READ(IER)); |
| 797 | seq_printf(m, "Interrupt identity: %08x\n", |
| 798 | I915_READ(IIR)); |
| 799 | seq_printf(m, "Interrupt mask: %08x\n", |
| 800 | I915_READ(IMR)); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 801 | for_each_pipe(dev_priv, pipe) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 802 | seq_printf(m, "Pipe %c stat: %08x\n", |
| 803 | pipe_name(pipe), |
| 804 | I915_READ(PIPESTAT(pipe))); |
Zhenyu Wang | 5f6a169 | 2009-08-10 21:37:24 +0800 | [diff] [blame] | 805 | } else { |
| 806 | seq_printf(m, "North Display Interrupt enable: %08x\n", |
| 807 | I915_READ(DEIER)); |
| 808 | seq_printf(m, "North Display Interrupt identity: %08x\n", |
| 809 | I915_READ(DEIIR)); |
| 810 | seq_printf(m, "North Display Interrupt mask: %08x\n", |
| 811 | I915_READ(DEIMR)); |
| 812 | seq_printf(m, "South Display Interrupt enable: %08x\n", |
| 813 | I915_READ(SDEIER)); |
| 814 | seq_printf(m, "South Display Interrupt identity: %08x\n", |
| 815 | I915_READ(SDEIIR)); |
| 816 | seq_printf(m, "South Display Interrupt mask: %08x\n", |
| 817 | I915_READ(SDEIMR)); |
| 818 | seq_printf(m, "Graphics Interrupt enable: %08x\n", |
| 819 | I915_READ(GTIER)); |
| 820 | seq_printf(m, "Graphics Interrupt identity: %08x\n", |
| 821 | I915_READ(GTIIR)); |
| 822 | seq_printf(m, "Graphics Interrupt mask: %08x\n", |
| 823 | I915_READ(GTIMR)); |
| 824 | } |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 825 | for_each_ring(ring, dev_priv, i) { |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 826 | if (INTEL_INFO(dev)->gen >= 6) { |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 827 | seq_printf(m, |
| 828 | "Graphics Interrupt mask (%s): %08x\n", |
| 829 | ring->name, I915_READ_IMR(ring)); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 830 | } |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 831 | i915_ring_seqno_info(m, ring); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 832 | } |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 833 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 834 | mutex_unlock(&dev->struct_mutex); |
| 835 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 836 | return 0; |
| 837 | } |
| 838 | |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 839 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
| 840 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 841 | struct drm_info_node *node = m->private; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 842 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 843 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 844 | int i, ret; |
| 845 | |
| 846 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 847 | if (ret) |
| 848 | return ret; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 849 | |
| 850 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); |
| 851 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
| 852 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 853 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 854 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 855 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
| 856 | i, dev_priv->fence_regs[i].pin_count); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 857 | if (obj == NULL) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 858 | seq_puts(m, "unused"); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 859 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 860 | describe_obj(m, obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 861 | seq_putc(m, '\n'); |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 862 | } |
| 863 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 864 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 865 | return 0; |
| 866 | } |
| 867 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 868 | static int i915_hws_info(struct seq_file *m, void *data) |
| 869 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 870 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 871 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 872 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 873 | struct intel_engine_cs *ring; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 874 | const u32 *hws; |
Chris Wilson | 4066c0a | 2010-10-29 21:00:54 +0100 | [diff] [blame] | 875 | int i; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 876 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 877 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 878 | hws = ring->status_page.page_addr; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 879 | if (hws == NULL) |
| 880 | return 0; |
| 881 | |
| 882 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { |
| 883 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 884 | i * 4, |
| 885 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); |
| 886 | } |
| 887 | return 0; |
| 888 | } |
| 889 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 890 | static ssize_t |
| 891 | i915_error_state_write(struct file *filp, |
| 892 | const char __user *ubuf, |
| 893 | size_t cnt, |
| 894 | loff_t *ppos) |
| 895 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 896 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 897 | struct drm_device *dev = error_priv->dev; |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 898 | int ret; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 899 | |
| 900 | DRM_DEBUG_DRIVER("Resetting error state\n"); |
| 901 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 902 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 903 | if (ret) |
| 904 | return ret; |
| 905 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 906 | i915_destroy_error_state(dev); |
| 907 | mutex_unlock(&dev->struct_mutex); |
| 908 | |
| 909 | return cnt; |
| 910 | } |
| 911 | |
| 912 | static int i915_error_state_open(struct inode *inode, struct file *file) |
| 913 | { |
| 914 | struct drm_device *dev = inode->i_private; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 915 | struct i915_error_state_file_priv *error_priv; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 916 | |
| 917 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); |
| 918 | if (!error_priv) |
| 919 | return -ENOMEM; |
| 920 | |
| 921 | error_priv->dev = dev; |
| 922 | |
Mika Kuoppala | 95d5bfb | 2013-06-06 15:18:40 +0300 | [diff] [blame] | 923 | i915_error_state_get(dev, error_priv); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 924 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 925 | file->private_data = error_priv; |
| 926 | |
| 927 | return 0; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 928 | } |
| 929 | |
| 930 | static int i915_error_state_release(struct inode *inode, struct file *file) |
| 931 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 932 | struct i915_error_state_file_priv *error_priv = file->private_data; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 933 | |
Mika Kuoppala | 95d5bfb | 2013-06-06 15:18:40 +0300 | [diff] [blame] | 934 | i915_error_state_put(error_priv); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 935 | kfree(error_priv); |
| 936 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 937 | return 0; |
| 938 | } |
| 939 | |
| 940 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
| 941 | size_t count, loff_t *pos) |
| 942 | { |
| 943 | struct i915_error_state_file_priv *error_priv = file->private_data; |
| 944 | struct drm_i915_error_state_buf error_str; |
| 945 | loff_t tmp_pos = 0; |
| 946 | ssize_t ret_count = 0; |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 947 | int ret; |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 948 | |
Chris Wilson | 0a4cd7c | 2014-08-22 14:41:39 +0100 | [diff] [blame] | 949 | ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos); |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 950 | if (ret) |
| 951 | return ret; |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 952 | |
Mika Kuoppala | fc16b48 | 2013-06-06 15:18:39 +0300 | [diff] [blame] | 953 | ret = i915_error_state_to_str(&error_str, error_priv); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 954 | if (ret) |
| 955 | goto out; |
| 956 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 957 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
| 958 | error_str.buf, |
| 959 | error_str.bytes); |
| 960 | |
| 961 | if (ret_count < 0) |
| 962 | ret = ret_count; |
| 963 | else |
| 964 | *pos = error_str.start + ret_count; |
| 965 | out: |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 966 | i915_error_state_buf_release(&error_str); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 967 | return ret ?: ret_count; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 968 | } |
| 969 | |
| 970 | static const struct file_operations i915_error_state_fops = { |
| 971 | .owner = THIS_MODULE, |
| 972 | .open = i915_error_state_open, |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 973 | .read = i915_error_state_read, |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 974 | .write = i915_error_state_write, |
| 975 | .llseek = default_llseek, |
| 976 | .release = i915_error_state_release, |
| 977 | }; |
| 978 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 979 | static int |
| 980 | i915_next_seqno_get(void *data, u64 *val) |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 981 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 982 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 983 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 984 | int ret; |
| 985 | |
| 986 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 987 | if (ret) |
| 988 | return ret; |
| 989 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 990 | *val = dev_priv->next_seqno; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 991 | mutex_unlock(&dev->struct_mutex); |
| 992 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 993 | return 0; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 994 | } |
| 995 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 996 | static int |
| 997 | i915_next_seqno_set(void *data, u64 val) |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 998 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 999 | struct drm_device *dev = data; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1000 | int ret; |
| 1001 | |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1002 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1003 | if (ret) |
| 1004 | return ret; |
| 1005 | |
Mika Kuoppala | e94fbaa | 2012-12-19 11:13:09 +0200 | [diff] [blame] | 1006 | ret = i915_gem_set_seqno(dev, val); |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1007 | mutex_unlock(&dev->struct_mutex); |
| 1008 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1009 | return ret; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1010 | } |
| 1011 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1012 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
| 1013 | i915_next_seqno_get, i915_next_seqno_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 1014 | "0x%llx\n"); |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1015 | |
Deepak S | adb4bd1 | 2014-03-31 11:30:02 +0530 | [diff] [blame] | 1016 | static int i915_frequency_info(struct seq_file *m, void *unused) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1017 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1018 | struct drm_info_node *node = m->private; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1019 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1020 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1021 | int ret = 0; |
| 1022 | |
| 1023 | intel_runtime_pm_get(dev_priv); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1024 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 1025 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 1026 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1027 | if (IS_GEN5(dev)) { |
| 1028 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
| 1029 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); |
| 1030 | |
| 1031 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); |
| 1032 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); |
| 1033 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> |
| 1034 | MEMSTAT_VID_SHIFT); |
| 1035 | seq_printf(m, "Current P-state: %d\n", |
| 1036 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 1037 | } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) || |
| 1038 | IS_BROADWELL(dev)) { |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1039 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
| 1040 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
| 1041 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1042 | u32 rpmodectl, rpinclimit, rpdeclimit; |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1043 | u32 rpstat, cagf, reqf; |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1044 | u32 rpupei, rpcurup, rpprevup; |
| 1045 | u32 rpdownei, rpcurdown, rpprevdown; |
Paulo Zanoni | 9dd3c60 | 2014-08-01 18:14:48 -0300 | [diff] [blame] | 1046 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1047 | int max_freq; |
| 1048 | |
| 1049 | /* RPSTAT1 is in the GT power well */ |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 1050 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1051 | if (ret) |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1052 | goto out; |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 1053 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 1054 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1055 | |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1056 | reqf = I915_READ(GEN6_RPNSWREQ); |
| 1057 | reqf &= ~GEN6_TURBO_DISABLE; |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 1058 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1059 | reqf >>= 24; |
| 1060 | else |
| 1061 | reqf >>= 25; |
| 1062 | reqf *= GT_FREQUENCY_MULTIPLIER; |
| 1063 | |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1064 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
| 1065 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); |
| 1066 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); |
| 1067 | |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1068 | rpstat = I915_READ(GEN6_RPSTAT1); |
| 1069 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); |
| 1070 | rpcurup = I915_READ(GEN6_RP_CUR_UP); |
| 1071 | rpprevup = I915_READ(GEN6_RP_PREV_UP); |
| 1072 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); |
| 1073 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); |
| 1074 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 1075 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 1076 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
| 1077 | else |
| 1078 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; |
| 1079 | cagf *= GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1080 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 1081 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 1082 | mutex_unlock(&dev->struct_mutex); |
| 1083 | |
Paulo Zanoni | 9dd3c60 | 2014-08-01 18:14:48 -0300 | [diff] [blame] | 1084 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
| 1085 | pm_ier = I915_READ(GEN6_PMIER); |
| 1086 | pm_imr = I915_READ(GEN6_PMIMR); |
| 1087 | pm_isr = I915_READ(GEN6_PMISR); |
| 1088 | pm_iir = I915_READ(GEN6_PMIIR); |
| 1089 | pm_mask = I915_READ(GEN6_PMINTRMSK); |
| 1090 | } else { |
| 1091 | pm_ier = I915_READ(GEN8_GT_IER(2)); |
| 1092 | pm_imr = I915_READ(GEN8_GT_IMR(2)); |
| 1093 | pm_isr = I915_READ(GEN8_GT_ISR(2)); |
| 1094 | pm_iir = I915_READ(GEN8_GT_IIR(2)); |
| 1095 | pm_mask = I915_READ(GEN6_PMINTRMSK); |
| 1096 | } |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1097 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
Paulo Zanoni | 9dd3c60 | 2014-08-01 18:14:48 -0300 | [diff] [blame] | 1098 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1099 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1100 | seq_printf(m, "Render p-state ratio: %d\n", |
| 1101 | (gt_perf_status & 0xff00) >> 8); |
| 1102 | seq_printf(m, "Render p-state VID: %d\n", |
| 1103 | gt_perf_status & 0xff); |
| 1104 | seq_printf(m, "Render p-state limit: %d\n", |
| 1105 | rp_state_limits & 0xff); |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1106 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
| 1107 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); |
| 1108 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); |
| 1109 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1110 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 1111 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1112 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
| 1113 | GEN6_CURICONT_MASK); |
| 1114 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & |
| 1115 | GEN6_CURBSYTAVG_MASK); |
| 1116 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & |
| 1117 | GEN6_CURBSYTAVG_MASK); |
| 1118 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & |
| 1119 | GEN6_CURIAVG_MASK); |
| 1120 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & |
| 1121 | GEN6_CURBSYTAVG_MASK); |
| 1122 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & |
| 1123 | GEN6_CURBSYTAVG_MASK); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1124 | |
| 1125 | max_freq = (rp_state_cap & 0xff0000) >> 16; |
| 1126 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1127 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1128 | |
| 1129 | max_freq = (rp_state_cap & 0xff00) >> 8; |
| 1130 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1131 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1132 | |
| 1133 | max_freq = rp_state_cap & 0xff; |
| 1134 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1135 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Ben Widawsky | 31c7738 | 2013-04-05 14:29:22 -0700 | [diff] [blame] | 1136 | |
| 1137 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1138 | dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1139 | } else if (IS_VALLEYVIEW(dev)) { |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 1140 | u32 freq_sts; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1141 | |
Jesse Barnes | 259bd5d | 2013-04-22 15:59:30 -0700 | [diff] [blame] | 1142 | mutex_lock(&dev_priv->rps.hw_lock); |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 1143 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1144 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
| 1145 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); |
| 1146 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1147 | seq_printf(m, "max GPU freq: %d MHz\n", |
Deepak S | b2435c9 | 2014-07-17 14:21:14 +0530 | [diff] [blame] | 1148 | vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1149 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1150 | seq_printf(m, "min GPU freq: %d MHz\n", |
Deepak S | b2435c9 | 2014-07-17 14:21:14 +0530 | [diff] [blame] | 1151 | vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq)); |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 1152 | |
| 1153 | seq_printf(m, "efficient (RPe) frequency: %d MHz\n", |
Deepak S | b2435c9 | 2014-07-17 14:21:14 +0530 | [diff] [blame] | 1154 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1155 | |
| 1156 | seq_printf(m, "current GPU freq: %d MHz\n", |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 1157 | vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); |
Jesse Barnes | 259bd5d | 2013-04-22 15:59:30 -0700 | [diff] [blame] | 1158 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1159 | } else { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1160 | seq_puts(m, "no P-state info available\n"); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1161 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1162 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1163 | out: |
| 1164 | intel_runtime_pm_put(dev_priv); |
| 1165 | return ret; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1166 | } |
| 1167 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1168 | static int ironlake_drpc_info(struct seq_file *m) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1169 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1170 | struct drm_info_node *node = m->private; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1171 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1172 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1173 | u32 rgvmodectl, rstdbyctl; |
| 1174 | u16 crstandvid; |
| 1175 | int ret; |
| 1176 | |
| 1177 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1178 | if (ret) |
| 1179 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1180 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1181 | |
| 1182 | rgvmodectl = I915_READ(MEMMODECTL); |
| 1183 | rstdbyctl = I915_READ(RSTDBYCTL); |
| 1184 | crstandvid = I915_READ16(CRSTANDVID); |
| 1185 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1186 | intel_runtime_pm_put(dev_priv); |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1187 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1188 | |
| 1189 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? |
| 1190 | "yes" : "no"); |
| 1191 | seq_printf(m, "Boost freq: %d\n", |
| 1192 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> |
| 1193 | MEMMODE_BOOST_FREQ_SHIFT); |
| 1194 | seq_printf(m, "HW control enabled: %s\n", |
| 1195 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); |
| 1196 | seq_printf(m, "SW control enabled: %s\n", |
| 1197 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); |
| 1198 | seq_printf(m, "Gated voltage change: %s\n", |
| 1199 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); |
| 1200 | seq_printf(m, "Starting frequency: P%d\n", |
| 1201 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1202 | seq_printf(m, "Max P-state: P%d\n", |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1203 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1204 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
| 1205 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); |
| 1206 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); |
| 1207 | seq_printf(m, "Render standby enabled: %s\n", |
| 1208 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1209 | seq_puts(m, "Current RS state: "); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1210 | switch (rstdbyctl & RSX_STATUS_MASK) { |
| 1211 | case RSX_STATUS_ON: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1212 | seq_puts(m, "on\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1213 | break; |
| 1214 | case RSX_STATUS_RC1: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1215 | seq_puts(m, "RC1\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1216 | break; |
| 1217 | case RSX_STATUS_RC1E: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1218 | seq_puts(m, "RC1E\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1219 | break; |
| 1220 | case RSX_STATUS_RS1: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1221 | seq_puts(m, "RS1\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1222 | break; |
| 1223 | case RSX_STATUS_RS2: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1224 | seq_puts(m, "RS2 (RC6)\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1225 | break; |
| 1226 | case RSX_STATUS_RS3: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1227 | seq_puts(m, "RC3 (RC6+)\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1228 | break; |
| 1229 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1230 | seq_puts(m, "unknown\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1231 | break; |
| 1232 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1233 | |
| 1234 | return 0; |
| 1235 | } |
| 1236 | |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1237 | static int vlv_drpc_info(struct seq_file *m) |
| 1238 | { |
| 1239 | |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1240 | struct drm_info_node *node = m->private; |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1241 | struct drm_device *dev = node->minor->dev; |
| 1242 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1243 | u32 rpmodectl1, rcctl1; |
| 1244 | unsigned fw_rendercount = 0, fw_mediacount = 0; |
| 1245 | |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 1246 | intel_runtime_pm_get(dev_priv); |
| 1247 | |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1248 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
| 1249 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
| 1250 | |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 1251 | intel_runtime_pm_put(dev_priv); |
| 1252 | |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1253 | seq_printf(m, "Video Turbo Mode: %s\n", |
| 1254 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); |
| 1255 | seq_printf(m, "Turbo enabled: %s\n", |
| 1256 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); |
| 1257 | seq_printf(m, "HW control enabled: %s\n", |
| 1258 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); |
| 1259 | seq_printf(m, "SW control enabled: %s\n", |
| 1260 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == |
| 1261 | GEN6_RP_MEDIA_SW_MODE)); |
| 1262 | seq_printf(m, "RC6 Enabled: %s\n", |
| 1263 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | |
| 1264 | GEN6_RC_CTL_EI_MODE(1)))); |
| 1265 | seq_printf(m, "Render Power Well: %s\n", |
| 1266 | (I915_READ(VLV_GTLC_PW_STATUS) & |
| 1267 | VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
| 1268 | seq_printf(m, "Media Power Well: %s\n", |
| 1269 | (I915_READ(VLV_GTLC_PW_STATUS) & |
| 1270 | VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
| 1271 | |
Imre Deak | 9cc19be | 2014-04-14 20:24:24 +0300 | [diff] [blame] | 1272 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
| 1273 | I915_READ(VLV_GT_RENDER_RC6)); |
| 1274 | seq_printf(m, "Media RC6 residency since boot: %u\n", |
| 1275 | I915_READ(VLV_GT_MEDIA_RC6)); |
| 1276 | |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1277 | spin_lock_irq(&dev_priv->uncore.lock); |
| 1278 | fw_rendercount = dev_priv->uncore.fw_rendercount; |
| 1279 | fw_mediacount = dev_priv->uncore.fw_mediacount; |
| 1280 | spin_unlock_irq(&dev_priv->uncore.lock); |
| 1281 | |
| 1282 | seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount); |
| 1283 | seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount); |
| 1284 | |
| 1285 | |
| 1286 | return 0; |
| 1287 | } |
| 1288 | |
| 1289 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1290 | static int gen6_drpc_info(struct seq_file *m) |
| 1291 | { |
| 1292 | |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1293 | struct drm_info_node *node = m->private; |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1294 | struct drm_device *dev = node->minor->dev; |
| 1295 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | ecd8fae | 2012-09-26 10:34:02 -0700 | [diff] [blame] | 1296 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
Daniel Vetter | 93b525d | 2012-01-25 13:52:43 +0100 | [diff] [blame] | 1297 | unsigned forcewake_count; |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 1298 | int count = 0, ret; |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1299 | |
| 1300 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1301 | if (ret) |
| 1302 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1303 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1304 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1305 | spin_lock_irq(&dev_priv->uncore.lock); |
| 1306 | forcewake_count = dev_priv->uncore.forcewake_count; |
| 1307 | spin_unlock_irq(&dev_priv->uncore.lock); |
Daniel Vetter | 93b525d | 2012-01-25 13:52:43 +0100 | [diff] [blame] | 1308 | |
| 1309 | if (forcewake_count) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1310 | seq_puts(m, "RC information inaccurate because somebody " |
| 1311 | "holds a forcewake reference \n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1312 | } else { |
| 1313 | /* NB: we cannot use forcewake, else we read the wrong values */ |
| 1314 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) |
| 1315 | udelay(10); |
| 1316 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); |
| 1317 | } |
| 1318 | |
| 1319 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); |
Chris Wilson | ed71f1b | 2013-07-19 20:36:56 +0100 | [diff] [blame] | 1320 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1321 | |
| 1322 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
| 1323 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
| 1324 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | 44cbd33 | 2012-11-06 14:36:36 +0000 | [diff] [blame] | 1325 | mutex_lock(&dev_priv->rps.hw_lock); |
| 1326 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
| 1327 | mutex_unlock(&dev_priv->rps.hw_lock); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1328 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1329 | intel_runtime_pm_put(dev_priv); |
| 1330 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1331 | seq_printf(m, "Video Turbo Mode: %s\n", |
| 1332 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); |
| 1333 | seq_printf(m, "HW control enabled: %s\n", |
| 1334 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); |
| 1335 | seq_printf(m, "SW control enabled: %s\n", |
| 1336 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == |
| 1337 | GEN6_RP_MEDIA_SW_MODE)); |
Eric Anholt | fff24e2 | 2012-01-23 16:14:05 -0800 | [diff] [blame] | 1338 | seq_printf(m, "RC1e Enabled: %s\n", |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1339 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
| 1340 | seq_printf(m, "RC6 Enabled: %s\n", |
| 1341 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); |
| 1342 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
| 1343 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); |
| 1344 | seq_printf(m, "Deepest RC6 Enabled: %s\n", |
| 1345 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1346 | seq_puts(m, "Current RC state: "); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1347 | switch (gt_core_status & GEN6_RCn_MASK) { |
| 1348 | case GEN6_RC0: |
| 1349 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1350 | seq_puts(m, "Core Power Down\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1351 | else |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1352 | seq_puts(m, "on\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1353 | break; |
| 1354 | case GEN6_RC3: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1355 | seq_puts(m, "RC3\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1356 | break; |
| 1357 | case GEN6_RC6: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1358 | seq_puts(m, "RC6\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1359 | break; |
| 1360 | case GEN6_RC7: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1361 | seq_puts(m, "RC7\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1362 | break; |
| 1363 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1364 | seq_puts(m, "Unknown\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1365 | break; |
| 1366 | } |
| 1367 | |
| 1368 | seq_printf(m, "Core Power Down: %s\n", |
| 1369 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); |
Ben Widawsky | cce66a2 | 2012-03-27 18:59:38 -0700 | [diff] [blame] | 1370 | |
| 1371 | /* Not exactly sure what this is */ |
| 1372 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", |
| 1373 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); |
| 1374 | seq_printf(m, "RC6 residency since boot: %u\n", |
| 1375 | I915_READ(GEN6_GT_GFX_RC6)); |
| 1376 | seq_printf(m, "RC6+ residency since boot: %u\n", |
| 1377 | I915_READ(GEN6_GT_GFX_RC6p)); |
| 1378 | seq_printf(m, "RC6++ residency since boot: %u\n", |
| 1379 | I915_READ(GEN6_GT_GFX_RC6pp)); |
| 1380 | |
Ben Widawsky | ecd8fae | 2012-09-26 10:34:02 -0700 | [diff] [blame] | 1381 | seq_printf(m, "RC6 voltage: %dmV\n", |
| 1382 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); |
| 1383 | seq_printf(m, "RC6+ voltage: %dmV\n", |
| 1384 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); |
| 1385 | seq_printf(m, "RC6++ voltage: %dmV\n", |
| 1386 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1387 | return 0; |
| 1388 | } |
| 1389 | |
| 1390 | static int i915_drpc_info(struct seq_file *m, void *unused) |
| 1391 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1392 | struct drm_info_node *node = m->private; |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1393 | struct drm_device *dev = node->minor->dev; |
| 1394 | |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1395 | if (IS_VALLEYVIEW(dev)) |
| 1396 | return vlv_drpc_info(m); |
Vedang Patel | ac66cf4 | 2014-08-26 10:42:51 -0700 | [diff] [blame] | 1397 | else if (INTEL_INFO(dev)->gen >= 6) |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1398 | return gen6_drpc_info(m); |
| 1399 | else |
| 1400 | return ironlake_drpc_info(m); |
| 1401 | } |
| 1402 | |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1403 | static int i915_fbc_status(struct seq_file *m, void *unused) |
| 1404 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1405 | struct drm_info_node *node = m->private; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1406 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1407 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1408 | |
Daniel Vetter | 3a77c4c | 2014-01-10 08:50:12 +0100 | [diff] [blame] | 1409 | if (!HAS_FBC(dev)) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1410 | seq_puts(m, "FBC unsupported on this chipset\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1411 | return 0; |
| 1412 | } |
| 1413 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1414 | intel_runtime_pm_get(dev_priv); |
| 1415 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1416 | if (intel_fbc_enabled(dev)) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1417 | seq_puts(m, "FBC enabled\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1418 | } else { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1419 | seq_puts(m, "FBC disabled: "); |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 1420 | switch (dev_priv->fbc.no_fbc_reason) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 1421 | case FBC_OK: |
| 1422 | seq_puts(m, "FBC actived, but currently disabled in hardware"); |
| 1423 | break; |
| 1424 | case FBC_UNSUPPORTED: |
| 1425 | seq_puts(m, "unsupported by this chipset"); |
| 1426 | break; |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1427 | case FBC_NO_OUTPUT: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1428 | seq_puts(m, "no outputs"); |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1429 | break; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1430 | case FBC_STOLEN_TOO_SMALL: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1431 | seq_puts(m, "not enough stolen memory"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1432 | break; |
| 1433 | case FBC_UNSUPPORTED_MODE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1434 | seq_puts(m, "mode not supported"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1435 | break; |
| 1436 | case FBC_MODE_TOO_LARGE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1437 | seq_puts(m, "mode too large"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1438 | break; |
| 1439 | case FBC_BAD_PLANE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1440 | seq_puts(m, "FBC unsupported on plane"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1441 | break; |
| 1442 | case FBC_NOT_TILED: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1443 | seq_puts(m, "scanout buffer not tiled"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1444 | break; |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1445 | case FBC_MULTIPLE_PIPES: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1446 | seq_puts(m, "multiple pipes are enabled"); |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1447 | break; |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 1448 | case FBC_MODULE_PARAM: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1449 | seq_puts(m, "disabled per module param (default off)"); |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 1450 | break; |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 1451 | case FBC_CHIP_DEFAULT: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1452 | seq_puts(m, "disabled per chip default"); |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 1453 | break; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1454 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1455 | seq_puts(m, "unknown reason"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1456 | } |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1457 | seq_putc(m, '\n'); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1458 | } |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1459 | |
| 1460 | intel_runtime_pm_put(dev_priv); |
| 1461 | |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1462 | return 0; |
| 1463 | } |
| 1464 | |
Rodrigo Vivi | da46f93 | 2014-08-01 02:04:45 -0700 | [diff] [blame] | 1465 | static int i915_fbc_fc_get(void *data, u64 *val) |
| 1466 | { |
| 1467 | struct drm_device *dev = data; |
| 1468 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1469 | |
| 1470 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) |
| 1471 | return -ENODEV; |
| 1472 | |
| 1473 | drm_modeset_lock_all(dev); |
| 1474 | *val = dev_priv->fbc.false_color; |
| 1475 | drm_modeset_unlock_all(dev); |
| 1476 | |
| 1477 | return 0; |
| 1478 | } |
| 1479 | |
| 1480 | static int i915_fbc_fc_set(void *data, u64 val) |
| 1481 | { |
| 1482 | struct drm_device *dev = data; |
| 1483 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1484 | u32 reg; |
| 1485 | |
| 1486 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) |
| 1487 | return -ENODEV; |
| 1488 | |
| 1489 | drm_modeset_lock_all(dev); |
| 1490 | |
| 1491 | reg = I915_READ(ILK_DPFC_CONTROL); |
| 1492 | dev_priv->fbc.false_color = val; |
| 1493 | |
| 1494 | I915_WRITE(ILK_DPFC_CONTROL, val ? |
| 1495 | (reg | FBC_CTL_FALSE_COLOR) : |
| 1496 | (reg & ~FBC_CTL_FALSE_COLOR)); |
| 1497 | |
| 1498 | drm_modeset_unlock_all(dev); |
| 1499 | return 0; |
| 1500 | } |
| 1501 | |
| 1502 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, |
| 1503 | i915_fbc_fc_get, i915_fbc_fc_set, |
| 1504 | "%llu\n"); |
| 1505 | |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1506 | static int i915_ips_status(struct seq_file *m, void *unused) |
| 1507 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1508 | struct drm_info_node *node = m->private; |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1509 | struct drm_device *dev = node->minor->dev; |
| 1510 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1511 | |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 1512 | if (!HAS_IPS(dev)) { |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1513 | seq_puts(m, "not supported\n"); |
| 1514 | return 0; |
| 1515 | } |
| 1516 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1517 | intel_runtime_pm_get(dev_priv); |
| 1518 | |
Rodrigo Vivi | 0eaa53f | 2014-06-30 04:45:01 -0700 | [diff] [blame] | 1519 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
| 1520 | yesno(i915.enable_ips)); |
| 1521 | |
| 1522 | if (INTEL_INFO(dev)->gen >= 8) { |
| 1523 | seq_puts(m, "Currently: unknown\n"); |
| 1524 | } else { |
| 1525 | if (I915_READ(IPS_CTL) & IPS_ENABLE) |
| 1526 | seq_puts(m, "Currently: enabled\n"); |
| 1527 | else |
| 1528 | seq_puts(m, "Currently: disabled\n"); |
| 1529 | } |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1530 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1531 | intel_runtime_pm_put(dev_priv); |
| 1532 | |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1533 | return 0; |
| 1534 | } |
| 1535 | |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1536 | static int i915_sr_status(struct seq_file *m, void *unused) |
| 1537 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1538 | struct drm_info_node *node = m->private; |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1539 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1540 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1541 | bool sr_enabled = false; |
| 1542 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1543 | intel_runtime_pm_get(dev_priv); |
| 1544 | |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 1545 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 5ba2aaa | 2010-08-19 18:04:08 +0100 | [diff] [blame] | 1546 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1547 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1548 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
| 1549 | else if (IS_I915GM(dev)) |
| 1550 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
| 1551 | else if (IS_PINEVIEW(dev)) |
| 1552 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
| 1553 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1554 | intel_runtime_pm_put(dev_priv); |
| 1555 | |
Chris Wilson | 5ba2aaa | 2010-08-19 18:04:08 +0100 | [diff] [blame] | 1556 | seq_printf(m, "self-refresh: %s\n", |
| 1557 | sr_enabled ? "enabled" : "disabled"); |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1558 | |
| 1559 | return 0; |
| 1560 | } |
| 1561 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1562 | static int i915_emon_status(struct seq_file *m, void *unused) |
| 1563 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1564 | struct drm_info_node *node = m->private; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1565 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1566 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1567 | unsigned long temp, chipset, gfx; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1568 | int ret; |
| 1569 | |
Chris Wilson | 582be6b | 2012-04-30 19:35:02 +0100 | [diff] [blame] | 1570 | if (!IS_GEN5(dev)) |
| 1571 | return -ENODEV; |
| 1572 | |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1573 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1574 | if (ret) |
| 1575 | return ret; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1576 | |
| 1577 | temp = i915_mch_val(dev_priv); |
| 1578 | chipset = i915_chipset_val(dev_priv); |
| 1579 | gfx = i915_gfx_val(dev_priv); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1580 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1581 | |
| 1582 | seq_printf(m, "GMCH temp: %ld\n", temp); |
| 1583 | seq_printf(m, "Chipset power: %ld\n", chipset); |
| 1584 | seq_printf(m, "GFX power: %ld\n", gfx); |
| 1585 | seq_printf(m, "Total power: %ld\n", chipset + gfx); |
| 1586 | |
| 1587 | return 0; |
| 1588 | } |
| 1589 | |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1590 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
| 1591 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1592 | struct drm_info_node *node = m->private; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1593 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1594 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1595 | int ret = 0; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1596 | int gpu_freq, ia_freq; |
| 1597 | |
Jesse Barnes | 1c70c0c | 2011-06-29 13:34:36 -0700 | [diff] [blame] | 1598 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1599 | seq_puts(m, "unsupported on this chipset\n"); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1600 | return 0; |
| 1601 | } |
| 1602 | |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1603 | intel_runtime_pm_get(dev_priv); |
| 1604 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 1605 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 1606 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1607 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1608 | if (ret) |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1609 | goto out; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1610 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1611 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1612 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1613 | for (gpu_freq = dev_priv->rps.min_freq_softlimit; |
| 1614 | gpu_freq <= dev_priv->rps.max_freq_softlimit; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1615 | gpu_freq++) { |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 1616 | ia_freq = gpu_freq; |
| 1617 | sandybridge_pcode_read(dev_priv, |
| 1618 | GEN6_PCODE_READ_MIN_FREQ_TABLE, |
| 1619 | &ia_freq); |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 1620 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
| 1621 | gpu_freq * GT_FREQUENCY_MULTIPLIER, |
| 1622 | ((ia_freq >> 0) & 0xff) * 100, |
| 1623 | ((ia_freq >> 8) & 0xff) * 100); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1624 | } |
| 1625 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1626 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1627 | |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1628 | out: |
| 1629 | intel_runtime_pm_put(dev_priv); |
| 1630 | return ret; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1631 | } |
| 1632 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1633 | static int i915_opregion(struct seq_file *m, void *unused) |
| 1634 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1635 | struct drm_info_node *node = m->private; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1636 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1637 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1638 | struct intel_opregion *opregion = &dev_priv->opregion; |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1639 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1640 | int ret; |
| 1641 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1642 | if (data == NULL) |
| 1643 | return -ENOMEM; |
| 1644 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1645 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1646 | if (ret) |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1647 | goto out; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1648 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1649 | if (opregion->header) { |
| 1650 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); |
| 1651 | seq_write(m, data, OPREGION_SIZE); |
| 1652 | } |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1653 | |
| 1654 | mutex_unlock(&dev->struct_mutex); |
| 1655 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1656 | out: |
| 1657 | kfree(data); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1658 | return 0; |
| 1659 | } |
| 1660 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1661 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
| 1662 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1663 | struct drm_info_node *node = m->private; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1664 | struct drm_device *dev = node->minor->dev; |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1665 | struct intel_fbdev *ifbdev = NULL; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1666 | struct intel_framebuffer *fb; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1667 | |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1668 | #ifdef CONFIG_DRM_I915_FBDEV |
| 1669 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1670 | |
| 1671 | ifbdev = dev_priv->fbdev; |
| 1672 | fb = to_intel_framebuffer(ifbdev->helper.fb); |
| 1673 | |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1674 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1675 | fb->base.width, |
| 1676 | fb->base.height, |
| 1677 | fb->base.depth, |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1678 | fb->base.bits_per_pixel, |
| 1679 | atomic_read(&fb->base.refcount.refcount)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1680 | describe_obj(m, fb->obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1681 | seq_putc(m, '\n'); |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1682 | #endif |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1683 | |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1684 | mutex_lock(&dev->mode_config.fb_lock); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1685 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
Daniel Vetter | 131a56d | 2013-10-17 14:35:31 +0200 | [diff] [blame] | 1686 | if (ifbdev && &fb->base == ifbdev->helper.fb) |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1687 | continue; |
| 1688 | |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1689 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1690 | fb->base.width, |
| 1691 | fb->base.height, |
| 1692 | fb->base.depth, |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1693 | fb->base.bits_per_pixel, |
| 1694 | atomic_read(&fb->base.refcount.refcount)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1695 | describe_obj(m, fb->obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1696 | seq_putc(m, '\n'); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1697 | } |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1698 | mutex_unlock(&dev->mode_config.fb_lock); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1699 | |
| 1700 | return 0; |
| 1701 | } |
| 1702 | |
Oscar Mateo | c9fe99b | 2014-07-24 17:04:46 +0100 | [diff] [blame] | 1703 | static void describe_ctx_ringbuf(struct seq_file *m, |
| 1704 | struct intel_ringbuffer *ringbuf) |
| 1705 | { |
| 1706 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", |
| 1707 | ringbuf->space, ringbuf->head, ringbuf->tail, |
| 1708 | ringbuf->last_retired_head); |
| 1709 | } |
| 1710 | |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1711 | static int i915_context_status(struct seq_file *m, void *unused) |
| 1712 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1713 | struct drm_info_node *node = m->private; |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1714 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1715 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1716 | struct intel_engine_cs *ring; |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 1717 | struct intel_context *ctx; |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 1718 | int ret, i; |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1719 | |
Daniel Vetter | f3d2887 | 2014-05-29 23:23:08 +0200 | [diff] [blame] | 1720 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1721 | if (ret) |
| 1722 | return ret; |
| 1723 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1724 | if (dev_priv->ips.pwrctx) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1725 | seq_puts(m, "power context "); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1726 | describe_obj(m, dev_priv->ips.pwrctx); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1727 | seq_putc(m, '\n'); |
Ben Widawsky | dc501fb | 2011-06-29 11:41:51 -0700 | [diff] [blame] | 1728 | } |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1729 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1730 | if (dev_priv->ips.renderctx) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1731 | seq_puts(m, "render context "); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1732 | describe_obj(m, dev_priv->ips.renderctx); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1733 | seq_putc(m, '\n'); |
Ben Widawsky | dc501fb | 2011-06-29 11:41:51 -0700 | [diff] [blame] | 1734 | } |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1735 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1736 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
Oscar Mateo | c9fe99b | 2014-07-24 17:04:46 +0100 | [diff] [blame] | 1737 | if (!i915.enable_execlists && |
| 1738 | ctx->legacy_hw_ctx.rcs_state == NULL) |
Chris Wilson | b77f699 | 2014-04-30 08:30:00 +0100 | [diff] [blame] | 1739 | continue; |
| 1740 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1741 | seq_puts(m, "HW context "); |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 1742 | describe_ctx(m, ctx); |
Oscar Mateo | c9fe99b | 2014-07-24 17:04:46 +0100 | [diff] [blame] | 1743 | for_each_ring(ring, dev_priv, i) { |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1744 | if (ring->default_context == ctx) |
Oscar Mateo | c9fe99b | 2014-07-24 17:04:46 +0100 | [diff] [blame] | 1745 | seq_printf(m, "(default context %s) ", |
| 1746 | ring->name); |
| 1747 | } |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1748 | |
Oscar Mateo | c9fe99b | 2014-07-24 17:04:46 +0100 | [diff] [blame] | 1749 | if (i915.enable_execlists) { |
| 1750 | seq_putc(m, '\n'); |
| 1751 | for_each_ring(ring, dev_priv, i) { |
| 1752 | struct drm_i915_gem_object *ctx_obj = |
| 1753 | ctx->engine[i].state; |
| 1754 | struct intel_ringbuffer *ringbuf = |
| 1755 | ctx->engine[i].ringbuf; |
| 1756 | |
| 1757 | seq_printf(m, "%s: ", ring->name); |
| 1758 | if (ctx_obj) |
| 1759 | describe_obj(m, ctx_obj); |
| 1760 | if (ringbuf) |
| 1761 | describe_ctx_ringbuf(m, ringbuf); |
| 1762 | seq_putc(m, '\n'); |
| 1763 | } |
| 1764 | } else { |
| 1765 | describe_obj(m, ctx->legacy_hw_ctx.rcs_state); |
| 1766 | } |
| 1767 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1768 | seq_putc(m, '\n'); |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 1769 | } |
| 1770 | |
Daniel Vetter | f3d2887 | 2014-05-29 23:23:08 +0200 | [diff] [blame] | 1771 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1772 | |
| 1773 | return 0; |
| 1774 | } |
| 1775 | |
Ben Widawsky | c0ab1ae | 2014-08-07 13:24:26 +0100 | [diff] [blame] | 1776 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
| 1777 | { |
| 1778 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1779 | struct drm_device *dev = node->minor->dev; |
| 1780 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1781 | struct intel_engine_cs *ring; |
| 1782 | struct intel_context *ctx; |
| 1783 | int ret, i; |
| 1784 | |
| 1785 | if (!i915.enable_execlists) { |
| 1786 | seq_printf(m, "Logical Ring Contexts are disabled\n"); |
| 1787 | return 0; |
| 1788 | } |
| 1789 | |
| 1790 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1791 | if (ret) |
| 1792 | return ret; |
| 1793 | |
| 1794 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
| 1795 | for_each_ring(ring, dev_priv, i) { |
| 1796 | struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; |
| 1797 | |
| 1798 | if (ring->default_context == ctx) |
| 1799 | continue; |
| 1800 | |
| 1801 | if (ctx_obj) { |
| 1802 | struct page *page = i915_gem_object_get_page(ctx_obj, 1); |
| 1803 | uint32_t *reg_state = kmap_atomic(page); |
| 1804 | int j; |
| 1805 | |
| 1806 | seq_printf(m, "CONTEXT: %s %u\n", ring->name, |
| 1807 | intel_execlists_ctx_id(ctx_obj)); |
| 1808 | |
| 1809 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { |
| 1810 | seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 1811 | i915_gem_obj_ggtt_offset(ctx_obj) + 4096 + (j * 4), |
| 1812 | reg_state[j], reg_state[j + 1], |
| 1813 | reg_state[j + 2], reg_state[j + 3]); |
| 1814 | } |
| 1815 | kunmap_atomic(reg_state); |
| 1816 | |
| 1817 | seq_putc(m, '\n'); |
| 1818 | } |
| 1819 | } |
| 1820 | } |
| 1821 | |
| 1822 | mutex_unlock(&dev->struct_mutex); |
| 1823 | |
| 1824 | return 0; |
| 1825 | } |
| 1826 | |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 1827 | static int i915_execlists(struct seq_file *m, void *data) |
| 1828 | { |
| 1829 | struct drm_info_node *node = (struct drm_info_node *)m->private; |
| 1830 | struct drm_device *dev = node->minor->dev; |
| 1831 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1832 | struct intel_engine_cs *ring; |
| 1833 | u32 status_pointer; |
| 1834 | u8 read_pointer; |
| 1835 | u8 write_pointer; |
| 1836 | u32 status; |
| 1837 | u32 ctx_id; |
| 1838 | struct list_head *cursor; |
| 1839 | int ring_id, i; |
| 1840 | int ret; |
| 1841 | |
| 1842 | if (!i915.enable_execlists) { |
| 1843 | seq_puts(m, "Logical Ring Contexts are disabled\n"); |
| 1844 | return 0; |
| 1845 | } |
| 1846 | |
| 1847 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1848 | if (ret) |
| 1849 | return ret; |
| 1850 | |
| 1851 | for_each_ring(ring, dev_priv, ring_id) { |
| 1852 | struct intel_ctx_submit_request *head_req = NULL; |
| 1853 | int count = 0; |
| 1854 | unsigned long flags; |
| 1855 | |
| 1856 | seq_printf(m, "%s\n", ring->name); |
| 1857 | |
| 1858 | status = I915_READ(RING_EXECLIST_STATUS(ring)); |
| 1859 | ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4); |
| 1860 | seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n", |
| 1861 | status, ctx_id); |
| 1862 | |
| 1863 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); |
| 1864 | seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer); |
| 1865 | |
| 1866 | read_pointer = ring->next_context_status_buffer; |
| 1867 | write_pointer = status_pointer & 0x07; |
| 1868 | if (read_pointer > write_pointer) |
| 1869 | write_pointer += 6; |
| 1870 | seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n", |
| 1871 | read_pointer, write_pointer); |
| 1872 | |
| 1873 | for (i = 0; i < 6; i++) { |
| 1874 | status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i); |
| 1875 | ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4); |
| 1876 | |
| 1877 | seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n", |
| 1878 | i, status, ctx_id); |
| 1879 | } |
| 1880 | |
| 1881 | spin_lock_irqsave(&ring->execlist_lock, flags); |
| 1882 | list_for_each(cursor, &ring->execlist_queue) |
| 1883 | count++; |
| 1884 | head_req = list_first_entry_or_null(&ring->execlist_queue, |
| 1885 | struct intel_ctx_submit_request, execlist_link); |
| 1886 | spin_unlock_irqrestore(&ring->execlist_lock, flags); |
| 1887 | |
| 1888 | seq_printf(m, "\t%d requests in queue\n", count); |
| 1889 | if (head_req) { |
| 1890 | struct drm_i915_gem_object *ctx_obj; |
| 1891 | |
| 1892 | ctx_obj = head_req->ctx->engine[ring_id].state; |
| 1893 | seq_printf(m, "\tHead request id: %u\n", |
| 1894 | intel_execlists_ctx_id(ctx_obj)); |
| 1895 | seq_printf(m, "\tHead request tail: %u\n", |
| 1896 | head_req->tail); |
| 1897 | } |
| 1898 | |
| 1899 | seq_putc(m, '\n'); |
| 1900 | } |
| 1901 | |
| 1902 | mutex_unlock(&dev->struct_mutex); |
| 1903 | |
| 1904 | return 0; |
| 1905 | } |
| 1906 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1907 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
| 1908 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1909 | struct drm_info_node *node = m->private; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1910 | struct drm_device *dev = node->minor->dev; |
| 1911 | struct drm_i915_private *dev_priv = dev->dev_private; |
Deepak S | 43709ba | 2013-11-23 14:55:44 +0530 | [diff] [blame] | 1912 | unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1913 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1914 | spin_lock_irq(&dev_priv->uncore.lock); |
Deepak S | 43709ba | 2013-11-23 14:55:44 +0530 | [diff] [blame] | 1915 | if (IS_VALLEYVIEW(dev)) { |
| 1916 | fw_rendercount = dev_priv->uncore.fw_rendercount; |
| 1917 | fw_mediacount = dev_priv->uncore.fw_mediacount; |
| 1918 | } else |
| 1919 | forcewake_count = dev_priv->uncore.forcewake_count; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1920 | spin_unlock_irq(&dev_priv->uncore.lock); |
Daniel Vetter | 9f1f46a | 2011-12-14 13:57:03 +0100 | [diff] [blame] | 1921 | |
Deepak S | 43709ba | 2013-11-23 14:55:44 +0530 | [diff] [blame] | 1922 | if (IS_VALLEYVIEW(dev)) { |
| 1923 | seq_printf(m, "fw_rendercount = %u\n", fw_rendercount); |
| 1924 | seq_printf(m, "fw_mediacount = %u\n", fw_mediacount); |
| 1925 | } else |
| 1926 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1927 | |
| 1928 | return 0; |
| 1929 | } |
| 1930 | |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1931 | static const char *swizzle_string(unsigned swizzle) |
| 1932 | { |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 1933 | switch (swizzle) { |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1934 | case I915_BIT_6_SWIZZLE_NONE: |
| 1935 | return "none"; |
| 1936 | case I915_BIT_6_SWIZZLE_9: |
| 1937 | return "bit9"; |
| 1938 | case I915_BIT_6_SWIZZLE_9_10: |
| 1939 | return "bit9/bit10"; |
| 1940 | case I915_BIT_6_SWIZZLE_9_11: |
| 1941 | return "bit9/bit11"; |
| 1942 | case I915_BIT_6_SWIZZLE_9_10_11: |
| 1943 | return "bit9/bit10/bit11"; |
| 1944 | case I915_BIT_6_SWIZZLE_9_17: |
| 1945 | return "bit9/bit17"; |
| 1946 | case I915_BIT_6_SWIZZLE_9_10_17: |
| 1947 | return "bit9/bit10/bit17"; |
| 1948 | case I915_BIT_6_SWIZZLE_UNKNOWN: |
Masanari Iida | 8a168ca | 2012-12-29 02:00:09 +0900 | [diff] [blame] | 1949 | return "unknown"; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1950 | } |
| 1951 | |
| 1952 | return "bug"; |
| 1953 | } |
| 1954 | |
| 1955 | static int i915_swizzle_info(struct seq_file *m, void *data) |
| 1956 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1957 | struct drm_info_node *node = m->private; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1958 | struct drm_device *dev = node->minor->dev; |
| 1959 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1960 | int ret; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1961 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1962 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1963 | if (ret) |
| 1964 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1965 | intel_runtime_pm_get(dev_priv); |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1966 | |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1967 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
| 1968 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); |
| 1969 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", |
| 1970 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); |
| 1971 | |
| 1972 | if (IS_GEN3(dev) || IS_GEN4(dev)) { |
| 1973 | seq_printf(m, "DDC = 0x%08x\n", |
| 1974 | I915_READ(DCC)); |
| 1975 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
| 1976 | I915_READ16(C0DRB3)); |
| 1977 | seq_printf(m, "C1DRB3 = 0x%04x\n", |
| 1978 | I915_READ16(C1DRB3)); |
Ben Widawsky | 9d3203e | 2013-11-02 21:07:14 -0700 | [diff] [blame] | 1979 | } else if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | 3fa7d23 | 2012-01-31 16:47:56 +0100 | [diff] [blame] | 1980 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
| 1981 | I915_READ(MAD_DIMM_C0)); |
| 1982 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", |
| 1983 | I915_READ(MAD_DIMM_C1)); |
| 1984 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", |
| 1985 | I915_READ(MAD_DIMM_C2)); |
| 1986 | seq_printf(m, "TILECTL = 0x%08x\n", |
| 1987 | I915_READ(TILECTL)); |
Robert Beckett | 5907f5f | 2014-01-23 14:23:14 +0000 | [diff] [blame] | 1988 | if (INTEL_INFO(dev)->gen >= 8) |
Ben Widawsky | 9d3203e | 2013-11-02 21:07:14 -0700 | [diff] [blame] | 1989 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
| 1990 | I915_READ(GAMTARBMODE)); |
| 1991 | else |
| 1992 | seq_printf(m, "ARB_MODE = 0x%08x\n", |
| 1993 | I915_READ(ARB_MODE)); |
Daniel Vetter | 3fa7d23 | 2012-01-31 16:47:56 +0100 | [diff] [blame] | 1994 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
| 1995 | I915_READ(DISP_ARB_CTL)); |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1996 | } |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1997 | intel_runtime_pm_put(dev_priv); |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1998 | mutex_unlock(&dev->struct_mutex); |
| 1999 | |
| 2000 | return 0; |
| 2001 | } |
| 2002 | |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2003 | static int per_file_ctx(int id, void *ptr, void *data) |
| 2004 | { |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 2005 | struct intel_context *ctx = ptr; |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2006 | struct seq_file *m = data; |
Daniel Vetter | ae6c480 | 2014-08-06 15:04:53 +0200 | [diff] [blame] | 2007 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
| 2008 | |
| 2009 | if (!ppgtt) { |
| 2010 | seq_printf(m, " no ppgtt for context %d\n", |
| 2011 | ctx->user_handle); |
| 2012 | return 0; |
| 2013 | } |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2014 | |
Oscar Mateo | f83d651 | 2014-05-22 14:13:38 +0100 | [diff] [blame] | 2015 | if (i915_gem_context_is_default(ctx)) |
| 2016 | seq_puts(m, " default context:\n"); |
| 2017 | else |
Oscar Mateo | 821d66d | 2014-07-03 16:28:00 +0100 | [diff] [blame] | 2018 | seq_printf(m, " context %d:\n", ctx->user_handle); |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2019 | ppgtt->debug_dump(ppgtt, m); |
| 2020 | |
| 2021 | return 0; |
| 2022 | } |
| 2023 | |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2024 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2025 | { |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2026 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2027 | struct intel_engine_cs *ring; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2028 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 2029 | int unused, i; |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2030 | |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2031 | if (!ppgtt) |
| 2032 | return; |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2033 | |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2034 | seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages); |
Ben Widawsky | 5abbcca | 2014-02-21 13:06:34 -0800 | [diff] [blame] | 2035 | seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2036 | for_each_ring(ring, dev_priv, unused) { |
| 2037 | seq_printf(m, "%s\n", ring->name); |
| 2038 | for (i = 0; i < 4; i++) { |
| 2039 | u32 offset = 0x270 + i * 8; |
| 2040 | u64 pdp = I915_READ(ring->mmio_base + offset + 4); |
| 2041 | pdp <<= 32; |
| 2042 | pdp |= I915_READ(ring->mmio_base + offset); |
Ville Syrjälä | a2a5b15 | 2014-03-31 18:17:16 +0300 | [diff] [blame] | 2043 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2044 | } |
| 2045 | } |
| 2046 | } |
| 2047 | |
| 2048 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
| 2049 | { |
| 2050 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2051 | struct intel_engine_cs *ring; |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2052 | struct drm_file *file; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2053 | int i; |
| 2054 | |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2055 | if (INTEL_INFO(dev)->gen == 6) |
| 2056 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
| 2057 | |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 2058 | for_each_ring(ring, dev_priv, i) { |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2059 | seq_printf(m, "%s\n", ring->name); |
| 2060 | if (INTEL_INFO(dev)->gen == 7) |
| 2061 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); |
| 2062 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); |
| 2063 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); |
| 2064 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); |
| 2065 | } |
| 2066 | if (dev_priv->mm.aliasing_ppgtt) { |
| 2067 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 2068 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 2069 | seq_puts(m, "aliasing PPGTT:\n"); |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2070 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2071 | |
Ben Widawsky | 87d60b6 | 2013-12-06 14:11:29 -0800 | [diff] [blame] | 2072 | ppgtt->debug_dump(ppgtt, m); |
Daniel Vetter | ae6c480 | 2014-08-06 15:04:53 +0200 | [diff] [blame] | 2073 | } |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2074 | |
| 2075 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
| 2076 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2077 | |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2078 | seq_printf(m, "proc: %s\n", |
| 2079 | get_pid_task(file->pid, PIDTYPE_PID)->comm); |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2080 | idr_for_each(&file_priv->context_idr, per_file_ctx, m); |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2081 | } |
| 2082 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2083 | } |
| 2084 | |
| 2085 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
| 2086 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2087 | struct drm_info_node *node = m->private; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2088 | struct drm_device *dev = node->minor->dev; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2089 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2090 | |
| 2091 | int ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2092 | if (ret) |
| 2093 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2094 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2095 | |
| 2096 | if (INTEL_INFO(dev)->gen >= 8) |
| 2097 | gen8_ppgtt_info(m, dev); |
| 2098 | else if (INTEL_INFO(dev)->gen >= 6) |
| 2099 | gen6_ppgtt_info(m, dev); |
| 2100 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2101 | intel_runtime_pm_put(dev_priv); |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2102 | mutex_unlock(&dev->struct_mutex); |
| 2103 | |
| 2104 | return 0; |
| 2105 | } |
| 2106 | |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 2107 | static int i915_llc(struct seq_file *m, void *data) |
| 2108 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2109 | struct drm_info_node *node = m->private; |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 2110 | struct drm_device *dev = node->minor->dev; |
| 2111 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2112 | |
| 2113 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ |
| 2114 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); |
| 2115 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); |
| 2116 | |
| 2117 | return 0; |
| 2118 | } |
| 2119 | |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2120 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
| 2121 | { |
| 2122 | struct drm_info_node *node = m->private; |
| 2123 | struct drm_device *dev = node->minor->dev; |
| 2124 | struct drm_i915_private *dev_priv = dev->dev_private; |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 2125 | u32 psrperf = 0; |
| 2126 | bool enabled = false; |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2127 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2128 | intel_runtime_pm_get(dev_priv); |
| 2129 | |
Daniel Vetter | fa128fa | 2014-07-11 10:30:17 -0700 | [diff] [blame] | 2130 | mutex_lock(&dev_priv->psr.lock); |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 2131 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
| 2132 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); |
Daniel Vetter | 2807cf6 | 2014-07-11 10:30:11 -0700 | [diff] [blame] | 2133 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
Rodrigo Vivi | 5755c78 | 2014-06-12 10:16:45 -0700 | [diff] [blame] | 2134 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
Daniel Vetter | fa128fa | 2014-07-11 10:30:17 -0700 | [diff] [blame] | 2135 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
| 2136 | dev_priv->psr.busy_frontbuffer_bits); |
| 2137 | seq_printf(m, "Re-enable work scheduled: %s\n", |
| 2138 | yesno(work_busy(&dev_priv->psr.work.work))); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2139 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 2140 | enabled = HAS_PSR(dev) && |
| 2141 | I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; |
Rodrigo Vivi | 5755c78 | 2014-06-12 10:16:45 -0700 | [diff] [blame] | 2142 | seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled)); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2143 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 2144 | if (HAS_PSR(dev)) |
| 2145 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & |
| 2146 | EDP_PSR_PERF_CNT_MASK; |
| 2147 | seq_printf(m, "Performance_Counter: %u\n", psrperf); |
Daniel Vetter | fa128fa | 2014-07-11 10:30:17 -0700 | [diff] [blame] | 2148 | mutex_unlock(&dev_priv->psr.lock); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2149 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2150 | intel_runtime_pm_put(dev_priv); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2151 | return 0; |
| 2152 | } |
| 2153 | |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 2154 | static int i915_sink_crc(struct seq_file *m, void *data) |
| 2155 | { |
| 2156 | struct drm_info_node *node = m->private; |
| 2157 | struct drm_device *dev = node->minor->dev; |
| 2158 | struct intel_encoder *encoder; |
| 2159 | struct intel_connector *connector; |
| 2160 | struct intel_dp *intel_dp = NULL; |
| 2161 | int ret; |
| 2162 | u8 crc[6]; |
| 2163 | |
| 2164 | drm_modeset_lock_all(dev); |
| 2165 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 2166 | base.head) { |
| 2167 | |
| 2168 | if (connector->base.dpms != DRM_MODE_DPMS_ON) |
| 2169 | continue; |
| 2170 | |
Paulo Zanoni | b6ae3c7 | 2014-02-13 17:51:33 -0200 | [diff] [blame] | 2171 | if (!connector->base.encoder) |
| 2172 | continue; |
| 2173 | |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 2174 | encoder = to_intel_encoder(connector->base.encoder); |
| 2175 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 2176 | continue; |
| 2177 | |
| 2178 | intel_dp = enc_to_intel_dp(&encoder->base); |
| 2179 | |
| 2180 | ret = intel_dp_sink_crc(intel_dp, crc); |
| 2181 | if (ret) |
| 2182 | goto out; |
| 2183 | |
| 2184 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", |
| 2185 | crc[0], crc[1], crc[2], |
| 2186 | crc[3], crc[4], crc[5]); |
| 2187 | goto out; |
| 2188 | } |
| 2189 | ret = -ENODEV; |
| 2190 | out: |
| 2191 | drm_modeset_unlock_all(dev); |
| 2192 | return ret; |
| 2193 | } |
| 2194 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 2195 | static int i915_energy_uJ(struct seq_file *m, void *data) |
| 2196 | { |
| 2197 | struct drm_info_node *node = m->private; |
| 2198 | struct drm_device *dev = node->minor->dev; |
| 2199 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2200 | u64 power; |
| 2201 | u32 units; |
| 2202 | |
| 2203 | if (INTEL_INFO(dev)->gen < 6) |
| 2204 | return -ENODEV; |
| 2205 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 2206 | intel_runtime_pm_get(dev_priv); |
| 2207 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 2208 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
| 2209 | power = (power & 0x1f00) >> 8; |
| 2210 | units = 1000000 / (1 << power); /* convert to uJ */ |
| 2211 | power = I915_READ(MCH_SECP_NRG_STTS); |
| 2212 | power *= units; |
| 2213 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 2214 | intel_runtime_pm_put(dev_priv); |
| 2215 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 2216 | seq_printf(m, "%llu", (long long unsigned)power); |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2217 | |
| 2218 | return 0; |
| 2219 | } |
| 2220 | |
| 2221 | static int i915_pc8_status(struct seq_file *m, void *unused) |
| 2222 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2223 | struct drm_info_node *node = m->private; |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2224 | struct drm_device *dev = node->minor->dev; |
| 2225 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2226 | |
Zhenyu Wang | 85b8d5c | 2014-04-01 19:39:48 -0300 | [diff] [blame] | 2227 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2228 | seq_puts(m, "not supported\n"); |
| 2229 | return 0; |
| 2230 | } |
| 2231 | |
Paulo Zanoni | 86c4ec0 | 2014-02-21 13:52:24 -0300 | [diff] [blame] | 2232 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2233 | seq_printf(m, "IRQs disabled: %s\n", |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 2234 | yesno(!intel_irqs_enabled(dev_priv))); |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2235 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 2236 | return 0; |
| 2237 | } |
| 2238 | |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 2239 | static const char *power_domain_str(enum intel_display_power_domain domain) |
| 2240 | { |
| 2241 | switch (domain) { |
| 2242 | case POWER_DOMAIN_PIPE_A: |
| 2243 | return "PIPE_A"; |
| 2244 | case POWER_DOMAIN_PIPE_B: |
| 2245 | return "PIPE_B"; |
| 2246 | case POWER_DOMAIN_PIPE_C: |
| 2247 | return "PIPE_C"; |
| 2248 | case POWER_DOMAIN_PIPE_A_PANEL_FITTER: |
| 2249 | return "PIPE_A_PANEL_FITTER"; |
| 2250 | case POWER_DOMAIN_PIPE_B_PANEL_FITTER: |
| 2251 | return "PIPE_B_PANEL_FITTER"; |
| 2252 | case POWER_DOMAIN_PIPE_C_PANEL_FITTER: |
| 2253 | return "PIPE_C_PANEL_FITTER"; |
| 2254 | case POWER_DOMAIN_TRANSCODER_A: |
| 2255 | return "TRANSCODER_A"; |
| 2256 | case POWER_DOMAIN_TRANSCODER_B: |
| 2257 | return "TRANSCODER_B"; |
| 2258 | case POWER_DOMAIN_TRANSCODER_C: |
| 2259 | return "TRANSCODER_C"; |
| 2260 | case POWER_DOMAIN_TRANSCODER_EDP: |
| 2261 | return "TRANSCODER_EDP"; |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 2262 | case POWER_DOMAIN_PORT_DDI_A_2_LANES: |
| 2263 | return "PORT_DDI_A_2_LANES"; |
| 2264 | case POWER_DOMAIN_PORT_DDI_A_4_LANES: |
| 2265 | return "PORT_DDI_A_4_LANES"; |
| 2266 | case POWER_DOMAIN_PORT_DDI_B_2_LANES: |
| 2267 | return "PORT_DDI_B_2_LANES"; |
| 2268 | case POWER_DOMAIN_PORT_DDI_B_4_LANES: |
| 2269 | return "PORT_DDI_B_4_LANES"; |
| 2270 | case POWER_DOMAIN_PORT_DDI_C_2_LANES: |
| 2271 | return "PORT_DDI_C_2_LANES"; |
| 2272 | case POWER_DOMAIN_PORT_DDI_C_4_LANES: |
| 2273 | return "PORT_DDI_C_4_LANES"; |
| 2274 | case POWER_DOMAIN_PORT_DDI_D_2_LANES: |
| 2275 | return "PORT_DDI_D_2_LANES"; |
| 2276 | case POWER_DOMAIN_PORT_DDI_D_4_LANES: |
| 2277 | return "PORT_DDI_D_4_LANES"; |
| 2278 | case POWER_DOMAIN_PORT_DSI: |
| 2279 | return "PORT_DSI"; |
| 2280 | case POWER_DOMAIN_PORT_CRT: |
| 2281 | return "PORT_CRT"; |
| 2282 | case POWER_DOMAIN_PORT_OTHER: |
| 2283 | return "PORT_OTHER"; |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 2284 | case POWER_DOMAIN_VGA: |
| 2285 | return "VGA"; |
| 2286 | case POWER_DOMAIN_AUDIO: |
| 2287 | return "AUDIO"; |
Paulo Zanoni | bd2bb1b | 2014-07-04 11:27:38 -0300 | [diff] [blame] | 2288 | case POWER_DOMAIN_PLLS: |
| 2289 | return "PLLS"; |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 2290 | case POWER_DOMAIN_INIT: |
| 2291 | return "INIT"; |
| 2292 | default: |
| 2293 | WARN_ON(1); |
| 2294 | return "?"; |
| 2295 | } |
| 2296 | } |
| 2297 | |
| 2298 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
| 2299 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2300 | struct drm_info_node *node = m->private; |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 2301 | struct drm_device *dev = node->minor->dev; |
| 2302 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2303 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 2304 | int i; |
| 2305 | |
| 2306 | mutex_lock(&power_domains->lock); |
| 2307 | |
| 2308 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); |
| 2309 | for (i = 0; i < power_domains->power_well_count; i++) { |
| 2310 | struct i915_power_well *power_well; |
| 2311 | enum intel_display_power_domain power_domain; |
| 2312 | |
| 2313 | power_well = &power_domains->power_wells[i]; |
| 2314 | seq_printf(m, "%-25s %d\n", power_well->name, |
| 2315 | power_well->count); |
| 2316 | |
| 2317 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; |
| 2318 | power_domain++) { |
| 2319 | if (!(BIT(power_domain) & power_well->domains)) |
| 2320 | continue; |
| 2321 | |
| 2322 | seq_printf(m, " %-23s %d\n", |
| 2323 | power_domain_str(power_domain), |
| 2324 | power_domains->domain_use_count[power_domain]); |
| 2325 | } |
| 2326 | } |
| 2327 | |
| 2328 | mutex_unlock(&power_domains->lock); |
| 2329 | |
| 2330 | return 0; |
| 2331 | } |
| 2332 | |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2333 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
| 2334 | struct drm_display_mode *mode) |
| 2335 | { |
| 2336 | int i; |
| 2337 | |
| 2338 | for (i = 0; i < tabs; i++) |
| 2339 | seq_putc(m, '\t'); |
| 2340 | |
| 2341 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", |
| 2342 | mode->base.id, mode->name, |
| 2343 | mode->vrefresh, mode->clock, |
| 2344 | mode->hdisplay, mode->hsync_start, |
| 2345 | mode->hsync_end, mode->htotal, |
| 2346 | mode->vdisplay, mode->vsync_start, |
| 2347 | mode->vsync_end, mode->vtotal, |
| 2348 | mode->type, mode->flags); |
| 2349 | } |
| 2350 | |
| 2351 | static void intel_encoder_info(struct seq_file *m, |
| 2352 | struct intel_crtc *intel_crtc, |
| 2353 | struct intel_encoder *intel_encoder) |
| 2354 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2355 | struct drm_info_node *node = m->private; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2356 | struct drm_device *dev = node->minor->dev; |
| 2357 | struct drm_crtc *crtc = &intel_crtc->base; |
| 2358 | struct intel_connector *intel_connector; |
| 2359 | struct drm_encoder *encoder; |
| 2360 | |
| 2361 | encoder = &intel_encoder->base; |
| 2362 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", |
Jani Nikula | 8e329a0 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 2363 | encoder->base.id, encoder->name); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2364 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
| 2365 | struct drm_connector *connector = &intel_connector->base; |
| 2366 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", |
| 2367 | connector->base.id, |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 2368 | connector->name, |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2369 | drm_get_connector_status_name(connector->status)); |
| 2370 | if (connector->status == connector_status_connected) { |
| 2371 | struct drm_display_mode *mode = &crtc->mode; |
| 2372 | seq_printf(m, ", mode:\n"); |
| 2373 | intel_seq_print_mode(m, 2, mode); |
| 2374 | } else { |
| 2375 | seq_putc(m, '\n'); |
| 2376 | } |
| 2377 | } |
| 2378 | } |
| 2379 | |
| 2380 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) |
| 2381 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2382 | struct drm_info_node *node = m->private; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2383 | struct drm_device *dev = node->minor->dev; |
| 2384 | struct drm_crtc *crtc = &intel_crtc->base; |
| 2385 | struct intel_encoder *intel_encoder; |
| 2386 | |
Matt Roper | 5aa8a93 | 2014-06-16 10:12:55 -0700 | [diff] [blame] | 2387 | if (crtc->primary->fb) |
| 2388 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
| 2389 | crtc->primary->fb->base.id, crtc->x, crtc->y, |
| 2390 | crtc->primary->fb->width, crtc->primary->fb->height); |
| 2391 | else |
| 2392 | seq_puts(m, "\tprimary plane disabled\n"); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2393 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
| 2394 | intel_encoder_info(m, intel_crtc, intel_encoder); |
| 2395 | } |
| 2396 | |
| 2397 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) |
| 2398 | { |
| 2399 | struct drm_display_mode *mode = panel->fixed_mode; |
| 2400 | |
| 2401 | seq_printf(m, "\tfixed mode:\n"); |
| 2402 | intel_seq_print_mode(m, 2, mode); |
| 2403 | } |
| 2404 | |
| 2405 | static void intel_dp_info(struct seq_file *m, |
| 2406 | struct intel_connector *intel_connector) |
| 2407 | { |
| 2408 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
| 2409 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
| 2410 | |
| 2411 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); |
| 2412 | seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" : |
| 2413 | "no"); |
| 2414 | if (intel_encoder->type == INTEL_OUTPUT_EDP) |
| 2415 | intel_panel_info(m, &intel_connector->panel); |
| 2416 | } |
| 2417 | |
| 2418 | static void intel_hdmi_info(struct seq_file *m, |
| 2419 | struct intel_connector *intel_connector) |
| 2420 | { |
| 2421 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
| 2422 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); |
| 2423 | |
| 2424 | seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" : |
| 2425 | "no"); |
| 2426 | } |
| 2427 | |
| 2428 | static void intel_lvds_info(struct seq_file *m, |
| 2429 | struct intel_connector *intel_connector) |
| 2430 | { |
| 2431 | intel_panel_info(m, &intel_connector->panel); |
| 2432 | } |
| 2433 | |
| 2434 | static void intel_connector_info(struct seq_file *m, |
| 2435 | struct drm_connector *connector) |
| 2436 | { |
| 2437 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 2438 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
Jesse Barnes | f103fc7 | 2014-02-20 12:39:57 -0800 | [diff] [blame] | 2439 | struct drm_display_mode *mode; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2440 | |
| 2441 | seq_printf(m, "connector %d: type %s, status: %s\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 2442 | connector->base.id, connector->name, |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2443 | drm_get_connector_status_name(connector->status)); |
| 2444 | if (connector->status == connector_status_connected) { |
| 2445 | seq_printf(m, "\tname: %s\n", connector->display_info.name); |
| 2446 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", |
| 2447 | connector->display_info.width_mm, |
| 2448 | connector->display_info.height_mm); |
| 2449 | seq_printf(m, "\tsubpixel order: %s\n", |
| 2450 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); |
| 2451 | seq_printf(m, "\tCEA rev: %d\n", |
| 2452 | connector->display_info.cea_rev); |
| 2453 | } |
Dave Airlie | 36cd744 | 2014-05-02 13:44:18 +1000 | [diff] [blame] | 2454 | if (intel_encoder) { |
| 2455 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
| 2456 | intel_encoder->type == INTEL_OUTPUT_EDP) |
| 2457 | intel_dp_info(m, intel_connector); |
| 2458 | else if (intel_encoder->type == INTEL_OUTPUT_HDMI) |
| 2459 | intel_hdmi_info(m, intel_connector); |
| 2460 | else if (intel_encoder->type == INTEL_OUTPUT_LVDS) |
| 2461 | intel_lvds_info(m, intel_connector); |
| 2462 | } |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2463 | |
Jesse Barnes | f103fc7 | 2014-02-20 12:39:57 -0800 | [diff] [blame] | 2464 | seq_printf(m, "\tmodes:\n"); |
| 2465 | list_for_each_entry(mode, &connector->modes, head) |
| 2466 | intel_seq_print_mode(m, 2, mode); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2467 | } |
| 2468 | |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2469 | static bool cursor_active(struct drm_device *dev, int pipe) |
| 2470 | { |
| 2471 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2472 | u32 state; |
| 2473 | |
| 2474 | if (IS_845G(dev) || IS_I865G(dev)) |
| 2475 | state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2476 | else |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 2477 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2478 | |
| 2479 | return state; |
| 2480 | } |
| 2481 | |
| 2482 | static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) |
| 2483 | { |
| 2484 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2485 | u32 pos; |
| 2486 | |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 2487 | pos = I915_READ(CURPOS(pipe)); |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2488 | |
| 2489 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; |
| 2490 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) |
| 2491 | *x = -*x; |
| 2492 | |
| 2493 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; |
| 2494 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) |
| 2495 | *y = -*y; |
| 2496 | |
| 2497 | return cursor_active(dev, pipe); |
| 2498 | } |
| 2499 | |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2500 | static int i915_display_info(struct seq_file *m, void *unused) |
| 2501 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2502 | struct drm_info_node *node = m->private; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2503 | struct drm_device *dev = node->minor->dev; |
Paulo Zanoni | b0e5ddf | 2014-04-01 14:55:10 -0300 | [diff] [blame] | 2504 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2505 | struct intel_crtc *crtc; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2506 | struct drm_connector *connector; |
| 2507 | |
Paulo Zanoni | b0e5ddf | 2014-04-01 14:55:10 -0300 | [diff] [blame] | 2508 | intel_runtime_pm_get(dev_priv); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2509 | drm_modeset_lock_all(dev); |
| 2510 | seq_printf(m, "CRTC info\n"); |
| 2511 | seq_printf(m, "---------\n"); |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 2512 | for_each_intel_crtc(dev, crtc) { |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2513 | bool active; |
| 2514 | int x, y; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2515 | |
Chris Wilson | 57127ef | 2014-07-04 08:20:11 +0100 | [diff] [blame] | 2516 | seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n", |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2517 | crtc->base.base.id, pipe_name(crtc->pipe), |
Chris Wilson | 57127ef | 2014-07-04 08:20:11 +0100 | [diff] [blame] | 2518 | yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h); |
Paulo Zanoni | a23dc65 | 2014-04-01 14:55:11 -0300 | [diff] [blame] | 2519 | if (crtc->active) { |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2520 | intel_crtc_info(m, crtc); |
| 2521 | |
Paulo Zanoni | a23dc65 | 2014-04-01 14:55:11 -0300 | [diff] [blame] | 2522 | active = cursor_position(dev, crtc->pipe, &x, &y); |
Chris Wilson | 57127ef | 2014-07-04 08:20:11 +0100 | [diff] [blame] | 2523 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 2524 | yesno(crtc->cursor_base), |
Chris Wilson | 57127ef | 2014-07-04 08:20:11 +0100 | [diff] [blame] | 2525 | x, y, crtc->cursor_width, crtc->cursor_height, |
| 2526 | crtc->cursor_addr, yesno(active)); |
Paulo Zanoni | a23dc65 | 2014-04-01 14:55:11 -0300 | [diff] [blame] | 2527 | } |
Daniel Vetter | cace841 | 2014-05-22 17:56:31 +0200 | [diff] [blame] | 2528 | |
| 2529 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", |
| 2530 | yesno(!crtc->cpu_fifo_underrun_disabled), |
| 2531 | yesno(!crtc->pch_fifo_underrun_disabled)); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2532 | } |
| 2533 | |
| 2534 | seq_printf(m, "\n"); |
| 2535 | seq_printf(m, "Connector info\n"); |
| 2536 | seq_printf(m, "--------------\n"); |
| 2537 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 2538 | intel_connector_info(m, connector); |
| 2539 | } |
| 2540 | drm_modeset_unlock_all(dev); |
Paulo Zanoni | b0e5ddf | 2014-04-01 14:55:10 -0300 | [diff] [blame] | 2541 | intel_runtime_pm_put(dev_priv); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2542 | |
| 2543 | return 0; |
| 2544 | } |
| 2545 | |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 2546 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
| 2547 | { |
| 2548 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2549 | struct drm_device *dev = node->minor->dev; |
| 2550 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2551 | struct intel_engine_cs *ring; |
| 2552 | int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
| 2553 | int i, j, ret; |
| 2554 | |
| 2555 | if (!i915_semaphore_is_enabled(dev)) { |
| 2556 | seq_puts(m, "Semaphores are disabled\n"); |
| 2557 | return 0; |
| 2558 | } |
| 2559 | |
| 2560 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2561 | if (ret) |
| 2562 | return ret; |
Paulo Zanoni | 0387206 | 2014-07-09 14:31:57 -0300 | [diff] [blame] | 2563 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 2564 | |
| 2565 | if (IS_BROADWELL(dev)) { |
| 2566 | struct page *page; |
| 2567 | uint64_t *seqno; |
| 2568 | |
| 2569 | page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0); |
| 2570 | |
| 2571 | seqno = (uint64_t *)kmap_atomic(page); |
| 2572 | for_each_ring(ring, dev_priv, i) { |
| 2573 | uint64_t offset; |
| 2574 | |
| 2575 | seq_printf(m, "%s\n", ring->name); |
| 2576 | |
| 2577 | seq_puts(m, " Last signal:"); |
| 2578 | for (j = 0; j < num_rings; j++) { |
| 2579 | offset = i * I915_NUM_RINGS + j; |
| 2580 | seq_printf(m, "0x%08llx (0x%02llx) ", |
| 2581 | seqno[offset], offset * 8); |
| 2582 | } |
| 2583 | seq_putc(m, '\n'); |
| 2584 | |
| 2585 | seq_puts(m, " Last wait: "); |
| 2586 | for (j = 0; j < num_rings; j++) { |
| 2587 | offset = i + (j * I915_NUM_RINGS); |
| 2588 | seq_printf(m, "0x%08llx (0x%02llx) ", |
| 2589 | seqno[offset], offset * 8); |
| 2590 | } |
| 2591 | seq_putc(m, '\n'); |
| 2592 | |
| 2593 | } |
| 2594 | kunmap_atomic(seqno); |
| 2595 | } else { |
| 2596 | seq_puts(m, " Last signal:"); |
| 2597 | for_each_ring(ring, dev_priv, i) |
| 2598 | for (j = 0; j < num_rings; j++) |
| 2599 | seq_printf(m, "0x%08x\n", |
| 2600 | I915_READ(ring->semaphore.mbox.signal[j])); |
| 2601 | seq_putc(m, '\n'); |
| 2602 | } |
| 2603 | |
| 2604 | seq_puts(m, "\nSync seqno:\n"); |
| 2605 | for_each_ring(ring, dev_priv, i) { |
| 2606 | for (j = 0; j < num_rings; j++) { |
| 2607 | seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]); |
| 2608 | } |
| 2609 | seq_putc(m, '\n'); |
| 2610 | } |
| 2611 | seq_putc(m, '\n'); |
| 2612 | |
Paulo Zanoni | 0387206 | 2014-07-09 14:31:57 -0300 | [diff] [blame] | 2613 | intel_runtime_pm_put(dev_priv); |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 2614 | mutex_unlock(&dev->struct_mutex); |
| 2615 | return 0; |
| 2616 | } |
| 2617 | |
Daniel Vetter | 728e29d | 2014-06-25 22:01:53 +0300 | [diff] [blame] | 2618 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
| 2619 | { |
| 2620 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2621 | struct drm_device *dev = node->minor->dev; |
| 2622 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2623 | int i; |
| 2624 | |
| 2625 | drm_modeset_lock_all(dev); |
| 2626 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 2627 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
| 2628 | |
| 2629 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); |
| 2630 | seq_printf(m, " refcount: %i, active: %i, on: %s\n", pll->refcount, |
| 2631 | pll->active, yesno(pll->on)); |
| 2632 | seq_printf(m, " tracked hardware state:\n"); |
| 2633 | seq_printf(m, " dpll: 0x%08x\n", pll->hw_state.dpll); |
| 2634 | seq_printf(m, " dpll_md: 0x%08x\n", pll->hw_state.dpll_md); |
| 2635 | seq_printf(m, " fp0: 0x%08x\n", pll->hw_state.fp0); |
| 2636 | seq_printf(m, " fp1: 0x%08x\n", pll->hw_state.fp1); |
Daniel Vetter | d452c5b | 2014-07-04 11:27:39 -0300 | [diff] [blame] | 2637 | seq_printf(m, " wrpll: 0x%08x\n", pll->hw_state.wrpll); |
Daniel Vetter | 728e29d | 2014-06-25 22:01:53 +0300 | [diff] [blame] | 2638 | } |
| 2639 | drm_modeset_unlock_all(dev); |
| 2640 | |
| 2641 | return 0; |
| 2642 | } |
| 2643 | |
Damien Lespiau | 1ed1ef9 | 2014-08-30 16:50:59 +0100 | [diff] [blame] | 2644 | static int i915_wa_registers(struct seq_file *m, void *unused) |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 2645 | { |
| 2646 | int i; |
| 2647 | int ret; |
| 2648 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2649 | struct drm_device *dev = node->minor->dev; |
| 2650 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2651 | |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 2652 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2653 | if (ret) |
| 2654 | return ret; |
| 2655 | |
| 2656 | intel_runtime_pm_get(dev_priv); |
| 2657 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 2658 | seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count); |
| 2659 | for (i = 0; i < dev_priv->workarounds.count; ++i) { |
Mika Kuoppala | 2fa60f6 | 2014-10-07 17:21:27 +0300 | [diff] [blame^] | 2660 | u32 addr, mask, value, read; |
| 2661 | bool ok; |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 2662 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 2663 | addr = dev_priv->workarounds.reg[i].addr; |
| 2664 | mask = dev_priv->workarounds.reg[i].mask; |
Mika Kuoppala | 2fa60f6 | 2014-10-07 17:21:27 +0300 | [diff] [blame^] | 2665 | value = dev_priv->workarounds.reg[i].value; |
| 2666 | read = I915_READ(addr); |
| 2667 | ok = (value & mask) == (read & mask); |
| 2668 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", |
| 2669 | addr, value, mask, read, ok ? "OK" : "FAIL"); |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 2670 | } |
| 2671 | |
| 2672 | intel_runtime_pm_put(dev_priv); |
| 2673 | mutex_unlock(&dev->struct_mutex); |
| 2674 | |
| 2675 | return 0; |
| 2676 | } |
| 2677 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2678 | struct pipe_crc_info { |
| 2679 | const char *name; |
| 2680 | struct drm_device *dev; |
| 2681 | enum pipe pipe; |
| 2682 | }; |
| 2683 | |
Dave Airlie | 11bed958 | 2014-05-12 15:22:27 +1000 | [diff] [blame] | 2684 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
| 2685 | { |
| 2686 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2687 | struct drm_device *dev = node->minor->dev; |
| 2688 | struct drm_encoder *encoder; |
| 2689 | struct intel_encoder *intel_encoder; |
| 2690 | struct intel_digital_port *intel_dig_port; |
| 2691 | drm_modeset_lock_all(dev); |
| 2692 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 2693 | intel_encoder = to_intel_encoder(encoder); |
| 2694 | if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT) |
| 2695 | continue; |
| 2696 | intel_dig_port = enc_to_dig_port(encoder); |
| 2697 | if (!intel_dig_port->dp.can_mst) |
| 2698 | continue; |
| 2699 | |
| 2700 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
| 2701 | } |
| 2702 | drm_modeset_unlock_all(dev); |
| 2703 | return 0; |
| 2704 | } |
| 2705 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2706 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 2707 | { |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 2708 | struct pipe_crc_info *info = inode->i_private; |
| 2709 | struct drm_i915_private *dev_priv = info->dev->dev_private; |
| 2710 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
| 2711 | |
Daniel Vetter | 7eb1c49 | 2013-11-14 11:30:43 +0100 | [diff] [blame] | 2712 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
| 2713 | return -ENODEV; |
| 2714 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2715 | spin_lock_irq(&pipe_crc->lock); |
| 2716 | |
| 2717 | if (pipe_crc->opened) { |
| 2718 | spin_unlock_irq(&pipe_crc->lock); |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 2719 | return -EBUSY; /* already open */ |
| 2720 | } |
| 2721 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2722 | pipe_crc->opened = true; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2723 | filep->private_data = inode->i_private; |
| 2724 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2725 | spin_unlock_irq(&pipe_crc->lock); |
| 2726 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2727 | return 0; |
| 2728 | } |
| 2729 | |
| 2730 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) |
| 2731 | { |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 2732 | struct pipe_crc_info *info = inode->i_private; |
| 2733 | struct drm_i915_private *dev_priv = info->dev->dev_private; |
| 2734 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
| 2735 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2736 | spin_lock_irq(&pipe_crc->lock); |
| 2737 | pipe_crc->opened = false; |
| 2738 | spin_unlock_irq(&pipe_crc->lock); |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 2739 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2740 | return 0; |
| 2741 | } |
| 2742 | |
| 2743 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ |
| 2744 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) |
| 2745 | /* account for \'0' */ |
| 2746 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) |
| 2747 | |
| 2748 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) |
| 2749 | { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2750 | assert_spin_locked(&pipe_crc->lock); |
| 2751 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
| 2752 | INTEL_PIPE_CRC_ENTRIES_NR); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2753 | } |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 2754 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2755 | static ssize_t |
| 2756 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, |
| 2757 | loff_t *pos) |
| 2758 | { |
| 2759 | struct pipe_crc_info *info = filep->private_data; |
| 2760 | struct drm_device *dev = info->dev; |
| 2761 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2762 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
| 2763 | char buf[PIPE_CRC_BUFFER_LEN]; |
| 2764 | int head, tail, n_entries, n; |
| 2765 | ssize_t bytes_read; |
| 2766 | |
| 2767 | /* |
| 2768 | * Don't allow user space to provide buffers not big enough to hold |
| 2769 | * a line of data. |
| 2770 | */ |
| 2771 | if (count < PIPE_CRC_LINE_LEN) |
| 2772 | return -EINVAL; |
| 2773 | |
| 2774 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) |
| 2775 | return 0; |
| 2776 | |
| 2777 | /* nothing to read */ |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2778 | spin_lock_irq(&pipe_crc->lock); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2779 | while (pipe_crc_data_count(pipe_crc) == 0) { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2780 | int ret; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2781 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2782 | if (filep->f_flags & O_NONBLOCK) { |
| 2783 | spin_unlock_irq(&pipe_crc->lock); |
| 2784 | return -EAGAIN; |
| 2785 | } |
| 2786 | |
| 2787 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
| 2788 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); |
| 2789 | if (ret) { |
| 2790 | spin_unlock_irq(&pipe_crc->lock); |
| 2791 | return ret; |
| 2792 | } |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2793 | } |
| 2794 | |
| 2795 | /* We now have one or more entries to read */ |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2796 | head = pipe_crc->head; |
| 2797 | tail = pipe_crc->tail; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2798 | n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR), |
| 2799 | count / PIPE_CRC_LINE_LEN); |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2800 | spin_unlock_irq(&pipe_crc->lock); |
| 2801 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2802 | bytes_read = 0; |
| 2803 | n = 0; |
| 2804 | do { |
| 2805 | struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail]; |
| 2806 | int ret; |
| 2807 | |
| 2808 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
| 2809 | "%8u %8x %8x %8x %8x %8x\n", |
| 2810 | entry->frame, entry->crc[0], |
| 2811 | entry->crc[1], entry->crc[2], |
| 2812 | entry->crc[3], entry->crc[4]); |
| 2813 | |
| 2814 | ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN, |
| 2815 | buf, PIPE_CRC_LINE_LEN); |
| 2816 | if (ret == PIPE_CRC_LINE_LEN) |
| 2817 | return -EFAULT; |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 2818 | |
| 2819 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); |
| 2820 | tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2821 | n++; |
| 2822 | } while (--n_entries); |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 2823 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2824 | spin_lock_irq(&pipe_crc->lock); |
| 2825 | pipe_crc->tail = tail; |
| 2826 | spin_unlock_irq(&pipe_crc->lock); |
| 2827 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2828 | return bytes_read; |
| 2829 | } |
| 2830 | |
| 2831 | static const struct file_operations i915_pipe_crc_fops = { |
| 2832 | .owner = THIS_MODULE, |
| 2833 | .open = i915_pipe_crc_open, |
| 2834 | .read = i915_pipe_crc_read, |
| 2835 | .release = i915_pipe_crc_release, |
| 2836 | }; |
| 2837 | |
| 2838 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { |
| 2839 | { |
| 2840 | .name = "i915_pipe_A_crc", |
| 2841 | .pipe = PIPE_A, |
| 2842 | }, |
| 2843 | { |
| 2844 | .name = "i915_pipe_B_crc", |
| 2845 | .pipe = PIPE_B, |
| 2846 | }, |
| 2847 | { |
| 2848 | .name = "i915_pipe_C_crc", |
| 2849 | .pipe = PIPE_C, |
| 2850 | }, |
| 2851 | }; |
| 2852 | |
| 2853 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, |
| 2854 | enum pipe pipe) |
| 2855 | { |
| 2856 | struct drm_device *dev = minor->dev; |
| 2857 | struct dentry *ent; |
| 2858 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; |
| 2859 | |
| 2860 | info->dev = dev; |
| 2861 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, |
| 2862 | &i915_pipe_crc_fops); |
Wei Yongjun | f3c5fe9 | 2013-12-16 14:13:25 +0800 | [diff] [blame] | 2863 | if (!ent) |
| 2864 | return -ENOMEM; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2865 | |
| 2866 | return drm_add_fake_info_node(minor, ent, info); |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 2867 | } |
| 2868 | |
Daniel Vetter | e8dfcf7 | 2013-10-16 11:51:54 +0200 | [diff] [blame] | 2869 | static const char * const pipe_crc_sources[] = { |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2870 | "none", |
| 2871 | "plane1", |
| 2872 | "plane2", |
| 2873 | "pf", |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2874 | "pipe", |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 2875 | "TV", |
| 2876 | "DP-B", |
| 2877 | "DP-C", |
| 2878 | "DP-D", |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2879 | "auto", |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2880 | }; |
| 2881 | |
| 2882 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) |
| 2883 | { |
| 2884 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); |
| 2885 | return pipe_crc_sources[source]; |
| 2886 | } |
| 2887 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2888 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2889 | { |
| 2890 | struct drm_device *dev = m->private; |
| 2891 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2892 | int i; |
| 2893 | |
| 2894 | for (i = 0; i < I915_MAX_PIPES; i++) |
| 2895 | seq_printf(m, "%c %s\n", pipe_name(i), |
| 2896 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); |
| 2897 | |
| 2898 | return 0; |
| 2899 | } |
| 2900 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2901 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2902 | { |
| 2903 | struct drm_device *dev = inode->i_private; |
| 2904 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2905 | return single_open(file, display_crc_ctl_show, dev); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2906 | } |
| 2907 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2908 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 2909 | uint32_t *val) |
| 2910 | { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2911 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
| 2912 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; |
| 2913 | |
| 2914 | switch (*source) { |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 2915 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 2916 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; |
| 2917 | break; |
| 2918 | case INTEL_PIPE_CRC_SOURCE_NONE: |
| 2919 | *val = 0; |
| 2920 | break; |
| 2921 | default: |
| 2922 | return -EINVAL; |
| 2923 | } |
| 2924 | |
| 2925 | return 0; |
| 2926 | } |
| 2927 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2928 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
| 2929 | enum intel_pipe_crc_source *source) |
| 2930 | { |
| 2931 | struct intel_encoder *encoder; |
| 2932 | struct intel_crtc *crtc; |
Daniel Vetter | 2675680 | 2013-11-01 10:50:23 +0100 | [diff] [blame] | 2933 | struct intel_digital_port *dig_port; |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2934 | int ret = 0; |
| 2935 | |
| 2936 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; |
| 2937 | |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 2938 | drm_modeset_lock_all(dev); |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 2939 | for_each_intel_encoder(dev, encoder) { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2940 | if (!encoder->base.crtc) |
| 2941 | continue; |
| 2942 | |
| 2943 | crtc = to_intel_crtc(encoder->base.crtc); |
| 2944 | |
| 2945 | if (crtc->pipe != pipe) |
| 2946 | continue; |
| 2947 | |
| 2948 | switch (encoder->type) { |
| 2949 | case INTEL_OUTPUT_TVOUT: |
| 2950 | *source = INTEL_PIPE_CRC_SOURCE_TV; |
| 2951 | break; |
| 2952 | case INTEL_OUTPUT_DISPLAYPORT: |
| 2953 | case INTEL_OUTPUT_EDP: |
Daniel Vetter | 2675680 | 2013-11-01 10:50:23 +0100 | [diff] [blame] | 2954 | dig_port = enc_to_dig_port(&encoder->base); |
| 2955 | switch (dig_port->port) { |
| 2956 | case PORT_B: |
| 2957 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; |
| 2958 | break; |
| 2959 | case PORT_C: |
| 2960 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; |
| 2961 | break; |
| 2962 | case PORT_D: |
| 2963 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; |
| 2964 | break; |
| 2965 | default: |
| 2966 | WARN(1, "nonexisting DP port %c\n", |
| 2967 | port_name(dig_port->port)); |
| 2968 | break; |
| 2969 | } |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2970 | break; |
| 2971 | } |
| 2972 | } |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 2973 | drm_modeset_unlock_all(dev); |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2974 | |
| 2975 | return ret; |
| 2976 | } |
| 2977 | |
| 2978 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, |
| 2979 | enum pipe pipe, |
| 2980 | enum intel_pipe_crc_source *source, |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 2981 | uint32_t *val) |
| 2982 | { |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 2983 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2984 | bool need_stable_symbols = false; |
| 2985 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2986 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
| 2987 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); |
| 2988 | if (ret) |
| 2989 | return ret; |
| 2990 | } |
| 2991 | |
| 2992 | switch (*source) { |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 2993 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 2994 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; |
| 2995 | break; |
| 2996 | case INTEL_PIPE_CRC_SOURCE_DP_B: |
| 2997 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 2998 | need_stable_symbols = true; |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 2999 | break; |
| 3000 | case INTEL_PIPE_CRC_SOURCE_DP_C: |
| 3001 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3002 | need_stable_symbols = true; |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3003 | break; |
| 3004 | case INTEL_PIPE_CRC_SOURCE_NONE: |
| 3005 | *val = 0; |
| 3006 | break; |
| 3007 | default: |
| 3008 | return -EINVAL; |
| 3009 | } |
| 3010 | |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3011 | /* |
| 3012 | * When the pipe CRC tap point is after the transcoders we need |
| 3013 | * to tweak symbol-level features to produce a deterministic series of |
| 3014 | * symbols for a given frame. We need to reset those features only once |
| 3015 | * a frame (instead of every nth symbol): |
| 3016 | * - DC-balance: used to ensure a better clock recovery from the data |
| 3017 | * link (SDVO) |
| 3018 | * - DisplayPort scrambling: used for EMI reduction |
| 3019 | */ |
| 3020 | if (need_stable_symbols) { |
| 3021 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 3022 | |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3023 | tmp |= DC_BALANCE_RESET_VLV; |
| 3024 | if (pipe == PIPE_A) |
| 3025 | tmp |= PIPE_A_SCRAMBLE_RESET; |
| 3026 | else |
| 3027 | tmp |= PIPE_B_SCRAMBLE_RESET; |
| 3028 | |
| 3029 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 3030 | } |
| 3031 | |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3032 | return 0; |
| 3033 | } |
| 3034 | |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3035 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3036 | enum pipe pipe, |
| 3037 | enum intel_pipe_crc_source *source, |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3038 | uint32_t *val) |
| 3039 | { |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3040 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3041 | bool need_stable_symbols = false; |
| 3042 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3043 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
| 3044 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); |
| 3045 | if (ret) |
| 3046 | return ret; |
| 3047 | } |
| 3048 | |
| 3049 | switch (*source) { |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3050 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 3051 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; |
| 3052 | break; |
| 3053 | case INTEL_PIPE_CRC_SOURCE_TV: |
| 3054 | if (!SUPPORTS_TV(dev)) |
| 3055 | return -EINVAL; |
| 3056 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; |
| 3057 | break; |
| 3058 | case INTEL_PIPE_CRC_SOURCE_DP_B: |
| 3059 | if (!IS_G4X(dev)) |
| 3060 | return -EINVAL; |
| 3061 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3062 | need_stable_symbols = true; |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3063 | break; |
| 3064 | case INTEL_PIPE_CRC_SOURCE_DP_C: |
| 3065 | if (!IS_G4X(dev)) |
| 3066 | return -EINVAL; |
| 3067 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3068 | need_stable_symbols = true; |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3069 | break; |
| 3070 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
| 3071 | if (!IS_G4X(dev)) |
| 3072 | return -EINVAL; |
| 3073 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3074 | need_stable_symbols = true; |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3075 | break; |
| 3076 | case INTEL_PIPE_CRC_SOURCE_NONE: |
| 3077 | *val = 0; |
| 3078 | break; |
| 3079 | default: |
| 3080 | return -EINVAL; |
| 3081 | } |
| 3082 | |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3083 | /* |
| 3084 | * When the pipe CRC tap point is after the transcoders we need |
| 3085 | * to tweak symbol-level features to produce a deterministic series of |
| 3086 | * symbols for a given frame. We need to reset those features only once |
| 3087 | * a frame (instead of every nth symbol): |
| 3088 | * - DC-balance: used to ensure a better clock recovery from the data |
| 3089 | * link (SDVO) |
| 3090 | * - DisplayPort scrambling: used for EMI reduction |
| 3091 | */ |
| 3092 | if (need_stable_symbols) { |
| 3093 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 3094 | |
| 3095 | WARN_ON(!IS_G4X(dev)); |
| 3096 | |
| 3097 | I915_WRITE(PORT_DFT_I9XX, |
| 3098 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); |
| 3099 | |
| 3100 | if (pipe == PIPE_A) |
| 3101 | tmp |= PIPE_A_SCRAMBLE_RESET; |
| 3102 | else |
| 3103 | tmp |= PIPE_B_SCRAMBLE_RESET; |
| 3104 | |
| 3105 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 3106 | } |
| 3107 | |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3108 | return 0; |
| 3109 | } |
| 3110 | |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3111 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
| 3112 | enum pipe pipe) |
| 3113 | { |
| 3114 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3115 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 3116 | |
| 3117 | if (pipe == PIPE_A) |
| 3118 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
| 3119 | else |
| 3120 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
| 3121 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
| 3122 | tmp &= ~DC_BALANCE_RESET_VLV; |
| 3123 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 3124 | |
| 3125 | } |
| 3126 | |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3127 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
| 3128 | enum pipe pipe) |
| 3129 | { |
| 3130 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3131 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 3132 | |
| 3133 | if (pipe == PIPE_A) |
| 3134 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
| 3135 | else |
| 3136 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
| 3137 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 3138 | |
| 3139 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { |
| 3140 | I915_WRITE(PORT_DFT_I9XX, |
| 3141 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); |
| 3142 | } |
| 3143 | } |
| 3144 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3145 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3146 | uint32_t *val) |
| 3147 | { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3148 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
| 3149 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; |
| 3150 | |
| 3151 | switch (*source) { |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3152 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
| 3153 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; |
| 3154 | break; |
| 3155 | case INTEL_PIPE_CRC_SOURCE_PLANE2: |
| 3156 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; |
| 3157 | break; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3158 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 3159 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; |
| 3160 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 3161 | case INTEL_PIPE_CRC_SOURCE_NONE: |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3162 | *val = 0; |
| 3163 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 3164 | default: |
| 3165 | return -EINVAL; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3166 | } |
| 3167 | |
| 3168 | return 0; |
| 3169 | } |
| 3170 | |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3171 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev) |
| 3172 | { |
| 3173 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3174 | struct intel_crtc *crtc = |
| 3175 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); |
| 3176 | |
| 3177 | drm_modeset_lock_all(dev); |
| 3178 | /* |
| 3179 | * If we use the eDP transcoder we need to make sure that we don't |
| 3180 | * bypass the pfit, since otherwise the pipe CRC source won't work. Only |
| 3181 | * relevant on hsw with pipe A when using the always-on power well |
| 3182 | * routing. |
| 3183 | */ |
| 3184 | if (crtc->config.cpu_transcoder == TRANSCODER_EDP && |
| 3185 | !crtc->config.pch_pfit.enabled) { |
| 3186 | crtc->config.pch_pfit.force_thru = true; |
| 3187 | |
| 3188 | intel_display_power_get(dev_priv, |
| 3189 | POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); |
| 3190 | |
| 3191 | dev_priv->display.crtc_disable(&crtc->base); |
| 3192 | dev_priv->display.crtc_enable(&crtc->base); |
| 3193 | } |
| 3194 | drm_modeset_unlock_all(dev); |
| 3195 | } |
| 3196 | |
| 3197 | static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev) |
| 3198 | { |
| 3199 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3200 | struct intel_crtc *crtc = |
| 3201 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); |
| 3202 | |
| 3203 | drm_modeset_lock_all(dev); |
| 3204 | /* |
| 3205 | * If we use the eDP transcoder we need to make sure that we don't |
| 3206 | * bypass the pfit, since otherwise the pipe CRC source won't work. Only |
| 3207 | * relevant on hsw with pipe A when using the always-on power well |
| 3208 | * routing. |
| 3209 | */ |
| 3210 | if (crtc->config.pch_pfit.force_thru) { |
| 3211 | crtc->config.pch_pfit.force_thru = false; |
| 3212 | |
| 3213 | dev_priv->display.crtc_disable(&crtc->base); |
| 3214 | dev_priv->display.crtc_enable(&crtc->base); |
| 3215 | |
| 3216 | intel_display_power_put(dev_priv, |
| 3217 | POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); |
| 3218 | } |
| 3219 | drm_modeset_unlock_all(dev); |
| 3220 | } |
| 3221 | |
| 3222 | static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, |
| 3223 | enum pipe pipe, |
| 3224 | enum intel_pipe_crc_source *source, |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3225 | uint32_t *val) |
| 3226 | { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3227 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
| 3228 | *source = INTEL_PIPE_CRC_SOURCE_PF; |
| 3229 | |
| 3230 | switch (*source) { |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3231 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
| 3232 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; |
| 3233 | break; |
| 3234 | case INTEL_PIPE_CRC_SOURCE_PLANE2: |
| 3235 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; |
| 3236 | break; |
| 3237 | case INTEL_PIPE_CRC_SOURCE_PF: |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3238 | if (IS_HASWELL(dev) && pipe == PIPE_A) |
| 3239 | hsw_trans_edp_pipe_A_crc_wa(dev); |
| 3240 | |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3241 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
| 3242 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 3243 | case INTEL_PIPE_CRC_SOURCE_NONE: |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3244 | *val = 0; |
| 3245 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 3246 | default: |
| 3247 | return -EINVAL; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3248 | } |
| 3249 | |
| 3250 | return 0; |
| 3251 | } |
| 3252 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3253 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
| 3254 | enum intel_pipe_crc_source source) |
| 3255 | { |
| 3256 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | cc3da17 | 2013-10-15 18:55:31 +0100 | [diff] [blame] | 3257 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
Borislav Petkov | 432f334 | 2013-11-21 16:49:46 +0100 | [diff] [blame] | 3258 | u32 val = 0; /* shut up gcc */ |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3259 | int ret; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3260 | |
Damien Lespiau | cc3da17 | 2013-10-15 18:55:31 +0100 | [diff] [blame] | 3261 | if (pipe_crc->source == source) |
| 3262 | return 0; |
| 3263 | |
Damien Lespiau | ae676fc | 2013-10-15 18:55:32 +0100 | [diff] [blame] | 3264 | /* forbid changing the source without going back to 'none' */ |
| 3265 | if (pipe_crc->source && source) |
| 3266 | return -EINVAL; |
| 3267 | |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 3268 | if (IS_GEN2(dev)) |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3269 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 3270 | else if (INTEL_INFO(dev)->gen < 5) |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3271 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3272 | else if (IS_VALLEYVIEW(dev)) |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3273 | ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3274 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3275 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3276 | else |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3277 | ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3278 | |
| 3279 | if (ret != 0) |
| 3280 | return ret; |
| 3281 | |
Damien Lespiau | 4b58436 | 2013-10-15 18:55:33 +0100 | [diff] [blame] | 3282 | /* none -> real source transition */ |
| 3283 | if (source) { |
Damien Lespiau | 7cd6ccf | 2013-10-15 18:55:38 +0100 | [diff] [blame] | 3284 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
| 3285 | pipe_name(pipe), pipe_crc_source_name(source)); |
| 3286 | |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 3287 | pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) * |
| 3288 | INTEL_PIPE_CRC_ENTRIES_NR, |
| 3289 | GFP_KERNEL); |
| 3290 | if (!pipe_crc->entries) |
| 3291 | return -ENOMEM; |
| 3292 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3293 | spin_lock_irq(&pipe_crc->lock); |
| 3294 | pipe_crc->head = 0; |
| 3295 | pipe_crc->tail = 0; |
| 3296 | spin_unlock_irq(&pipe_crc->lock); |
Damien Lespiau | 4b58436 | 2013-10-15 18:55:33 +0100 | [diff] [blame] | 3297 | } |
| 3298 | |
Damien Lespiau | cc3da17 | 2013-10-15 18:55:31 +0100 | [diff] [blame] | 3299 | pipe_crc->source = source; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3300 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3301 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
| 3302 | POSTING_READ(PIPE_CRC_CTL(pipe)); |
| 3303 | |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 3304 | /* real source -> none transition */ |
| 3305 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3306 | struct intel_pipe_crc_entry *entries; |
Daniel Vetter | a33d710 | 2014-06-06 08:22:08 +0200 | [diff] [blame] | 3307 | struct intel_crtc *crtc = |
| 3308 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3309 | |
Damien Lespiau | 7cd6ccf | 2013-10-15 18:55:38 +0100 | [diff] [blame] | 3310 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
| 3311 | pipe_name(pipe)); |
| 3312 | |
Daniel Vetter | a33d710 | 2014-06-06 08:22:08 +0200 | [diff] [blame] | 3313 | drm_modeset_lock(&crtc->base.mutex, NULL); |
| 3314 | if (crtc->active) |
| 3315 | intel_wait_for_vblank(dev, pipe); |
| 3316 | drm_modeset_unlock(&crtc->base.mutex); |
Daniel Vetter | bcf17ab | 2013-10-16 22:55:50 +0200 | [diff] [blame] | 3317 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3318 | spin_lock_irq(&pipe_crc->lock); |
| 3319 | entries = pipe_crc->entries; |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 3320 | pipe_crc->entries = NULL; |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3321 | spin_unlock_irq(&pipe_crc->lock); |
| 3322 | |
| 3323 | kfree(entries); |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3324 | |
| 3325 | if (IS_G4X(dev)) |
| 3326 | g4x_undo_pipe_scramble_reset(dev, pipe); |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3327 | else if (IS_VALLEYVIEW(dev)) |
| 3328 | vlv_undo_pipe_scramble_reset(dev, pipe); |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3329 | else if (IS_HASWELL(dev) && pipe == PIPE_A) |
| 3330 | hsw_undo_trans_edp_pipe_A_crc_wa(dev); |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 3331 | } |
| 3332 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3333 | return 0; |
| 3334 | } |
| 3335 | |
| 3336 | /* |
| 3337 | * Parse pipe CRC command strings: |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3338 | * command: wsp* object wsp+ name wsp+ source wsp* |
| 3339 | * object: 'pipe' |
| 3340 | * name: (A | B | C) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3341 | * source: (none | plane1 | plane2 | pf) |
| 3342 | * wsp: (#0x20 | #0x9 | #0xA)+ |
| 3343 | * |
| 3344 | * eg.: |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3345 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
| 3346 | * "pipe A none" -> Stop CRC |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3347 | */ |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3348 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3349 | { |
| 3350 | int n_words = 0; |
| 3351 | |
| 3352 | while (*buf) { |
| 3353 | char *end; |
| 3354 | |
| 3355 | /* skip leading white space */ |
| 3356 | buf = skip_spaces(buf); |
| 3357 | if (!*buf) |
| 3358 | break; /* end of buffer */ |
| 3359 | |
| 3360 | /* find end of word */ |
| 3361 | for (end = buf; *end && !isspace(*end); end++) |
| 3362 | ; |
| 3363 | |
| 3364 | if (n_words == max_words) { |
| 3365 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", |
| 3366 | max_words); |
| 3367 | return -EINVAL; /* ran out of words[] before bytes */ |
| 3368 | } |
| 3369 | |
| 3370 | if (*end) |
| 3371 | *end++ = '\0'; |
| 3372 | words[n_words++] = buf; |
| 3373 | buf = end; |
| 3374 | } |
| 3375 | |
| 3376 | return n_words; |
| 3377 | } |
| 3378 | |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3379 | enum intel_pipe_crc_object { |
| 3380 | PIPE_CRC_OBJECT_PIPE, |
| 3381 | }; |
| 3382 | |
Daniel Vetter | e8dfcf7 | 2013-10-16 11:51:54 +0200 | [diff] [blame] | 3383 | static const char * const pipe_crc_objects[] = { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3384 | "pipe", |
| 3385 | }; |
| 3386 | |
| 3387 | static int |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3388 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3389 | { |
| 3390 | int i; |
| 3391 | |
| 3392 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) |
| 3393 | if (!strcmp(buf, pipe_crc_objects[i])) { |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3394 | *o = i; |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3395 | return 0; |
| 3396 | } |
| 3397 | |
| 3398 | return -EINVAL; |
| 3399 | } |
| 3400 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3401 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3402 | { |
| 3403 | const char name = buf[0]; |
| 3404 | |
| 3405 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) |
| 3406 | return -EINVAL; |
| 3407 | |
| 3408 | *pipe = name - 'A'; |
| 3409 | |
| 3410 | return 0; |
| 3411 | } |
| 3412 | |
| 3413 | static int |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3414 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3415 | { |
| 3416 | int i; |
| 3417 | |
| 3418 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) |
| 3419 | if (!strcmp(buf, pipe_crc_sources[i])) { |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3420 | *s = i; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3421 | return 0; |
| 3422 | } |
| 3423 | |
| 3424 | return -EINVAL; |
| 3425 | } |
| 3426 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3427 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3428 | { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3429 | #define N_WORDS 3 |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3430 | int n_words; |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3431 | char *words[N_WORDS]; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3432 | enum pipe pipe; |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3433 | enum intel_pipe_crc_object object; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3434 | enum intel_pipe_crc_source source; |
| 3435 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3436 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3437 | if (n_words != N_WORDS) { |
| 3438 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", |
| 3439 | N_WORDS); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3440 | return -EINVAL; |
| 3441 | } |
| 3442 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3443 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3444 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3445 | return -EINVAL; |
| 3446 | } |
| 3447 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3448 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3449 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
| 3450 | return -EINVAL; |
| 3451 | } |
| 3452 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3453 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3454 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3455 | return -EINVAL; |
| 3456 | } |
| 3457 | |
| 3458 | return pipe_crc_set_source(dev, pipe, source); |
| 3459 | } |
| 3460 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3461 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
| 3462 | size_t len, loff_t *offp) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3463 | { |
| 3464 | struct seq_file *m = file->private_data; |
| 3465 | struct drm_device *dev = m->private; |
| 3466 | char *tmpbuf; |
| 3467 | int ret; |
| 3468 | |
| 3469 | if (len == 0) |
| 3470 | return 0; |
| 3471 | |
| 3472 | if (len > PAGE_SIZE - 1) { |
| 3473 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", |
| 3474 | PAGE_SIZE); |
| 3475 | return -E2BIG; |
| 3476 | } |
| 3477 | |
| 3478 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); |
| 3479 | if (!tmpbuf) |
| 3480 | return -ENOMEM; |
| 3481 | |
| 3482 | if (copy_from_user(tmpbuf, ubuf, len)) { |
| 3483 | ret = -EFAULT; |
| 3484 | goto out; |
| 3485 | } |
| 3486 | tmpbuf[len] = '\0'; |
| 3487 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3488 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3489 | |
| 3490 | out: |
| 3491 | kfree(tmpbuf); |
| 3492 | if (ret < 0) |
| 3493 | return ret; |
| 3494 | |
| 3495 | *offp += len; |
| 3496 | return len; |
| 3497 | } |
| 3498 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3499 | static const struct file_operations i915_display_crc_ctl_fops = { |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3500 | .owner = THIS_MODULE, |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3501 | .open = display_crc_ctl_open, |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3502 | .read = seq_read, |
| 3503 | .llseek = seq_lseek, |
| 3504 | .release = single_release, |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3505 | .write = display_crc_ctl_write |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3506 | }; |
| 3507 | |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3508 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[5]) |
| 3509 | { |
| 3510 | struct drm_device *dev = m->private; |
Damien Lespiau | 546c81f | 2014-05-13 15:30:26 +0100 | [diff] [blame] | 3511 | int num_levels = ilk_wm_max_level(dev) + 1; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3512 | int level; |
| 3513 | |
| 3514 | drm_modeset_lock_all(dev); |
| 3515 | |
| 3516 | for (level = 0; level < num_levels; level++) { |
| 3517 | unsigned int latency = wm[level]; |
| 3518 | |
| 3519 | /* WM1+ latency values in 0.5us units */ |
| 3520 | if (level > 0) |
| 3521 | latency *= 5; |
| 3522 | |
| 3523 | seq_printf(m, "WM%d %u (%u.%u usec)\n", |
| 3524 | level, wm[level], |
| 3525 | latency / 10, latency % 10); |
| 3526 | } |
| 3527 | |
| 3528 | drm_modeset_unlock_all(dev); |
| 3529 | } |
| 3530 | |
| 3531 | static int pri_wm_latency_show(struct seq_file *m, void *data) |
| 3532 | { |
| 3533 | struct drm_device *dev = m->private; |
| 3534 | |
| 3535 | wm_latency_show(m, to_i915(dev)->wm.pri_latency); |
| 3536 | |
| 3537 | return 0; |
| 3538 | } |
| 3539 | |
| 3540 | static int spr_wm_latency_show(struct seq_file *m, void *data) |
| 3541 | { |
| 3542 | struct drm_device *dev = m->private; |
| 3543 | |
| 3544 | wm_latency_show(m, to_i915(dev)->wm.spr_latency); |
| 3545 | |
| 3546 | return 0; |
| 3547 | } |
| 3548 | |
| 3549 | static int cur_wm_latency_show(struct seq_file *m, void *data) |
| 3550 | { |
| 3551 | struct drm_device *dev = m->private; |
| 3552 | |
| 3553 | wm_latency_show(m, to_i915(dev)->wm.cur_latency); |
| 3554 | |
| 3555 | return 0; |
| 3556 | } |
| 3557 | |
| 3558 | static int pri_wm_latency_open(struct inode *inode, struct file *file) |
| 3559 | { |
| 3560 | struct drm_device *dev = inode->i_private; |
| 3561 | |
Sonika Jindal | 9ad0257 | 2014-07-21 15:23:39 +0530 | [diff] [blame] | 3562 | if (HAS_GMCH_DISPLAY(dev)) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3563 | return -ENODEV; |
| 3564 | |
| 3565 | return single_open(file, pri_wm_latency_show, dev); |
| 3566 | } |
| 3567 | |
| 3568 | static int spr_wm_latency_open(struct inode *inode, struct file *file) |
| 3569 | { |
| 3570 | struct drm_device *dev = inode->i_private; |
| 3571 | |
Sonika Jindal | 9ad0257 | 2014-07-21 15:23:39 +0530 | [diff] [blame] | 3572 | if (HAS_GMCH_DISPLAY(dev)) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3573 | return -ENODEV; |
| 3574 | |
| 3575 | return single_open(file, spr_wm_latency_show, dev); |
| 3576 | } |
| 3577 | |
| 3578 | static int cur_wm_latency_open(struct inode *inode, struct file *file) |
| 3579 | { |
| 3580 | struct drm_device *dev = inode->i_private; |
| 3581 | |
Sonika Jindal | 9ad0257 | 2014-07-21 15:23:39 +0530 | [diff] [blame] | 3582 | if (HAS_GMCH_DISPLAY(dev)) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3583 | return -ENODEV; |
| 3584 | |
| 3585 | return single_open(file, cur_wm_latency_show, dev); |
| 3586 | } |
| 3587 | |
| 3588 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, |
| 3589 | size_t len, loff_t *offp, uint16_t wm[5]) |
| 3590 | { |
| 3591 | struct seq_file *m = file->private_data; |
| 3592 | struct drm_device *dev = m->private; |
| 3593 | uint16_t new[5] = { 0 }; |
Damien Lespiau | 546c81f | 2014-05-13 15:30:26 +0100 | [diff] [blame] | 3594 | int num_levels = ilk_wm_max_level(dev) + 1; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3595 | int level; |
| 3596 | int ret; |
| 3597 | char tmp[32]; |
| 3598 | |
| 3599 | if (len >= sizeof(tmp)) |
| 3600 | return -EINVAL; |
| 3601 | |
| 3602 | if (copy_from_user(tmp, ubuf, len)) |
| 3603 | return -EFAULT; |
| 3604 | |
| 3605 | tmp[len] = '\0'; |
| 3606 | |
| 3607 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]); |
| 3608 | if (ret != num_levels) |
| 3609 | return -EINVAL; |
| 3610 | |
| 3611 | drm_modeset_lock_all(dev); |
| 3612 | |
| 3613 | for (level = 0; level < num_levels; level++) |
| 3614 | wm[level] = new[level]; |
| 3615 | |
| 3616 | drm_modeset_unlock_all(dev); |
| 3617 | |
| 3618 | return len; |
| 3619 | } |
| 3620 | |
| 3621 | |
| 3622 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, |
| 3623 | size_t len, loff_t *offp) |
| 3624 | { |
| 3625 | struct seq_file *m = file->private_data; |
| 3626 | struct drm_device *dev = m->private; |
| 3627 | |
| 3628 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency); |
| 3629 | } |
| 3630 | |
| 3631 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, |
| 3632 | size_t len, loff_t *offp) |
| 3633 | { |
| 3634 | struct seq_file *m = file->private_data; |
| 3635 | struct drm_device *dev = m->private; |
| 3636 | |
| 3637 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency); |
| 3638 | } |
| 3639 | |
| 3640 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, |
| 3641 | size_t len, loff_t *offp) |
| 3642 | { |
| 3643 | struct seq_file *m = file->private_data; |
| 3644 | struct drm_device *dev = m->private; |
| 3645 | |
| 3646 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency); |
| 3647 | } |
| 3648 | |
| 3649 | static const struct file_operations i915_pri_wm_latency_fops = { |
| 3650 | .owner = THIS_MODULE, |
| 3651 | .open = pri_wm_latency_open, |
| 3652 | .read = seq_read, |
| 3653 | .llseek = seq_lseek, |
| 3654 | .release = single_release, |
| 3655 | .write = pri_wm_latency_write |
| 3656 | }; |
| 3657 | |
| 3658 | static const struct file_operations i915_spr_wm_latency_fops = { |
| 3659 | .owner = THIS_MODULE, |
| 3660 | .open = spr_wm_latency_open, |
| 3661 | .read = seq_read, |
| 3662 | .llseek = seq_lseek, |
| 3663 | .release = single_release, |
| 3664 | .write = spr_wm_latency_write |
| 3665 | }; |
| 3666 | |
| 3667 | static const struct file_operations i915_cur_wm_latency_fops = { |
| 3668 | .owner = THIS_MODULE, |
| 3669 | .open = cur_wm_latency_open, |
| 3670 | .read = seq_read, |
| 3671 | .llseek = seq_lseek, |
| 3672 | .release = single_release, |
| 3673 | .write = cur_wm_latency_write |
| 3674 | }; |
| 3675 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3676 | static int |
| 3677 | i915_wedged_get(void *data, u64 *val) |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3678 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3679 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 3680 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3681 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3682 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3683 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3684 | return 0; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3685 | } |
| 3686 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3687 | static int |
| 3688 | i915_wedged_set(void *data, u64 val) |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3689 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3690 | struct drm_device *dev = data; |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 3691 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3692 | |
| 3693 | intel_runtime_pm_get(dev_priv); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3694 | |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 3695 | i915_handle_error(dev, val, |
| 3696 | "Manually setting wedged to %llu", val); |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 3697 | |
| 3698 | intel_runtime_pm_put(dev_priv); |
| 3699 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3700 | return 0; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3701 | } |
| 3702 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3703 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
| 3704 | i915_wedged_get, i915_wedged_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 3705 | "%llu\n"); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3706 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3707 | static int |
| 3708 | i915_ring_stop_get(void *data, u64 *val) |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3709 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3710 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 3711 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3712 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3713 | *val = dev_priv->gpu_error.stop_rings; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3714 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3715 | return 0; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3716 | } |
| 3717 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3718 | static int |
| 3719 | i915_ring_stop_set(void *data, u64 val) |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3720 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3721 | struct drm_device *dev = data; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3722 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3723 | int ret; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3724 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3725 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3726 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 3727 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 3728 | if (ret) |
| 3729 | return ret; |
| 3730 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 3731 | dev_priv->gpu_error.stop_rings = val; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3732 | mutex_unlock(&dev->struct_mutex); |
| 3733 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3734 | return 0; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3735 | } |
| 3736 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3737 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
| 3738 | i915_ring_stop_get, i915_ring_stop_set, |
| 3739 | "0x%08llx\n"); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 3740 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 3741 | static int |
| 3742 | i915_ring_missed_irq_get(void *data, u64 *val) |
| 3743 | { |
| 3744 | struct drm_device *dev = data; |
| 3745 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3746 | |
| 3747 | *val = dev_priv->gpu_error.missed_irq_rings; |
| 3748 | return 0; |
| 3749 | } |
| 3750 | |
| 3751 | static int |
| 3752 | i915_ring_missed_irq_set(void *data, u64 val) |
| 3753 | { |
| 3754 | struct drm_device *dev = data; |
| 3755 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3756 | int ret; |
| 3757 | |
| 3758 | /* Lock against concurrent debugfs callers */ |
| 3759 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 3760 | if (ret) |
| 3761 | return ret; |
| 3762 | dev_priv->gpu_error.missed_irq_rings = val; |
| 3763 | mutex_unlock(&dev->struct_mutex); |
| 3764 | |
| 3765 | return 0; |
| 3766 | } |
| 3767 | |
| 3768 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, |
| 3769 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, |
| 3770 | "0x%08llx\n"); |
| 3771 | |
| 3772 | static int |
| 3773 | i915_ring_test_irq_get(void *data, u64 *val) |
| 3774 | { |
| 3775 | struct drm_device *dev = data; |
| 3776 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3777 | |
| 3778 | *val = dev_priv->gpu_error.test_irq_rings; |
| 3779 | |
| 3780 | return 0; |
| 3781 | } |
| 3782 | |
| 3783 | static int |
| 3784 | i915_ring_test_irq_set(void *data, u64 val) |
| 3785 | { |
| 3786 | struct drm_device *dev = data; |
| 3787 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3788 | int ret; |
| 3789 | |
| 3790 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
| 3791 | |
| 3792 | /* Lock against concurrent debugfs callers */ |
| 3793 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 3794 | if (ret) |
| 3795 | return ret; |
| 3796 | |
| 3797 | dev_priv->gpu_error.test_irq_rings = val; |
| 3798 | mutex_unlock(&dev->struct_mutex); |
| 3799 | |
| 3800 | return 0; |
| 3801 | } |
| 3802 | |
| 3803 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, |
| 3804 | i915_ring_test_irq_get, i915_ring_test_irq_set, |
| 3805 | "0x%08llx\n"); |
| 3806 | |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3807 | #define DROP_UNBOUND 0x1 |
| 3808 | #define DROP_BOUND 0x2 |
| 3809 | #define DROP_RETIRE 0x4 |
| 3810 | #define DROP_ACTIVE 0x8 |
| 3811 | #define DROP_ALL (DROP_UNBOUND | \ |
| 3812 | DROP_BOUND | \ |
| 3813 | DROP_RETIRE | \ |
| 3814 | DROP_ACTIVE) |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3815 | static int |
| 3816 | i915_drop_caches_get(void *data, u64 *val) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3817 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3818 | *val = DROP_ALL; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3819 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3820 | return 0; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3821 | } |
| 3822 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3823 | static int |
| 3824 | i915_drop_caches_set(void *data, u64 val) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3825 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3826 | struct drm_device *dev = data; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3827 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3828 | int ret; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3829 | |
Ben Widawsky | 2f9fe5f | 2013-11-25 09:54:37 -0800 | [diff] [blame] | 3830 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3831 | |
| 3832 | /* No need to check and wait for gpu resets, only libdrm auto-restarts |
| 3833 | * on ioctls on -EAGAIN. */ |
| 3834 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 3835 | if (ret) |
| 3836 | return ret; |
| 3837 | |
| 3838 | if (val & DROP_ACTIVE) { |
| 3839 | ret = i915_gpu_idle(dev); |
| 3840 | if (ret) |
| 3841 | goto unlock; |
| 3842 | } |
| 3843 | |
| 3844 | if (val & (DROP_RETIRE | DROP_ACTIVE)) |
| 3845 | i915_gem_retire_requests(dev); |
| 3846 | |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 3847 | if (val & DROP_BOUND) |
| 3848 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); |
Chris Wilson | 4ad72b7 | 2014-09-03 19:23:37 +0100 | [diff] [blame] | 3849 | |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 3850 | if (val & DROP_UNBOUND) |
| 3851 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3852 | |
| 3853 | unlock: |
| 3854 | mutex_unlock(&dev->struct_mutex); |
| 3855 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3856 | return ret; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3857 | } |
| 3858 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3859 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
| 3860 | i915_drop_caches_get, i915_drop_caches_set, |
| 3861 | "0x%08llx\n"); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3862 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3863 | static int |
| 3864 | i915_max_freq_get(void *data, u64 *val) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3865 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3866 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 3867 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3868 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3869 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 3870 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3871 | return -ENODEV; |
| 3872 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 3873 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 3874 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3875 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3876 | if (ret) |
| 3877 | return ret; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3878 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3879 | if (IS_VALLEYVIEW(dev)) |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3880 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3881 | else |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3882 | *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3883 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3884 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3885 | return 0; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3886 | } |
| 3887 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3888 | static int |
| 3889 | i915_max_freq_set(void *data, u64 val) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3890 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3891 | struct drm_device *dev = data; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3892 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3893 | u32 rp_state_cap, hw_max, hw_min; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3894 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3895 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 3896 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3897 | return -ENODEV; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3898 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 3899 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 3900 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3901 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3902 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3903 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3904 | if (ret) |
| 3905 | return ret; |
| 3906 | |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3907 | /* |
| 3908 | * Turbo will still be enabled, but won't go above the set value. |
| 3909 | */ |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3910 | if (IS_VALLEYVIEW(dev)) { |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 3911 | val = vlv_freq_opcode(dev_priv, val); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3912 | |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 3913 | hw_max = dev_priv->rps.max_freq; |
| 3914 | hw_min = dev_priv->rps.min_freq; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3915 | } else { |
| 3916 | do_div(val, GT_FREQUENCY_MULTIPLIER); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3917 | |
| 3918 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3919 | hw_max = dev_priv->rps.max_freq; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3920 | hw_min = (rp_state_cap >> 16) & 0xff; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3921 | } |
| 3922 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3923 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3924 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 3925 | return -EINVAL; |
| 3926 | } |
| 3927 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3928 | dev_priv->rps.max_freq_softlimit = val; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3929 | |
| 3930 | if (IS_VALLEYVIEW(dev)) |
| 3931 | valleyview_set_rps(dev, val); |
| 3932 | else |
| 3933 | gen6_set_rps(dev, val); |
| 3934 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3935 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3936 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3937 | return 0; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3938 | } |
| 3939 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3940 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
| 3941 | i915_max_freq_get, i915_max_freq_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 3942 | "%llu\n"); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 3943 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3944 | static int |
| 3945 | i915_min_freq_get(void *data, u64 *val) |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3946 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3947 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 3948 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3949 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3950 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 3951 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3952 | return -ENODEV; |
| 3953 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 3954 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 3955 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3956 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3957 | if (ret) |
| 3958 | return ret; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3959 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3960 | if (IS_VALLEYVIEW(dev)) |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3961 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3962 | else |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3963 | *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3964 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3965 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3966 | return 0; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3967 | } |
| 3968 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3969 | static int |
| 3970 | i915_min_freq_set(void *data, u64 val) |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3971 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3972 | struct drm_device *dev = data; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3973 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3974 | u32 rp_state_cap, hw_max, hw_min; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3975 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3976 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 3977 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3978 | return -ENODEV; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3979 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 3980 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 3981 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3982 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3983 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3984 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3985 | if (ret) |
| 3986 | return ret; |
| 3987 | |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 3988 | /* |
| 3989 | * Turbo will still be enabled, but won't go below the set value. |
| 3990 | */ |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3991 | if (IS_VALLEYVIEW(dev)) { |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 3992 | val = vlv_freq_opcode(dev_priv, val); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3993 | |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 3994 | hw_max = dev_priv->rps.max_freq; |
| 3995 | hw_min = dev_priv->rps.min_freq; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3996 | } else { |
| 3997 | do_div(val, GT_FREQUENCY_MULTIPLIER); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3998 | |
| 3999 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4000 | hw_max = dev_priv->rps.max_freq; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4001 | hw_min = (rp_state_cap >> 16) & 0xff; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4002 | } |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4003 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4004 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4005 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 4006 | return -EINVAL; |
| 4007 | } |
| 4008 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4009 | dev_priv->rps.min_freq_softlimit = val; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4010 | |
| 4011 | if (IS_VALLEYVIEW(dev)) |
| 4012 | valleyview_set_rps(dev, val); |
| 4013 | else |
| 4014 | gen6_set_rps(dev, val); |
| 4015 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4016 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4017 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4018 | return 0; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4019 | } |
| 4020 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4021 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
| 4022 | i915_min_freq_get, i915_min_freq_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 4023 | "%llu\n"); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4024 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4025 | static int |
| 4026 | i915_cache_sharing_get(void *data, u64 *val) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4027 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4028 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 4029 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4030 | u32 snpcr; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4031 | int ret; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4032 | |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4033 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 4034 | return -ENODEV; |
| 4035 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 4036 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 4037 | if (ret) |
| 4038 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4039 | intel_runtime_pm_get(dev_priv); |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 4040 | |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4041 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4042 | |
| 4043 | intel_runtime_pm_put(dev_priv); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4044 | mutex_unlock(&dev_priv->dev->struct_mutex); |
| 4045 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4046 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4047 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4048 | return 0; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4049 | } |
| 4050 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4051 | static int |
| 4052 | i915_cache_sharing_set(void *data, u64 val) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4053 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4054 | struct drm_device *dev = data; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4055 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4056 | u32 snpcr; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4057 | |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4058 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 4059 | return -ENODEV; |
| 4060 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4061 | if (val > 3) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4062 | return -EINVAL; |
| 4063 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4064 | intel_runtime_pm_get(dev_priv); |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4065 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4066 | |
| 4067 | /* Update the cache sharing policy here as well */ |
| 4068 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
| 4069 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
| 4070 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); |
| 4071 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
| 4072 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4073 | intel_runtime_pm_put(dev_priv); |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4074 | return 0; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4075 | } |
| 4076 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4077 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
| 4078 | i915_cache_sharing_get, i915_cache_sharing_set, |
| 4079 | "%llu\n"); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4080 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4081 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
| 4082 | { |
| 4083 | struct drm_device *dev = inode->i_private; |
| 4084 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4085 | |
Daniel Vetter | 075edca | 2012-01-24 09:44:28 +0100 | [diff] [blame] | 4086 | if (INTEL_INFO(dev)->gen < 6) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4087 | return 0; |
| 4088 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 4089 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4090 | |
| 4091 | return 0; |
| 4092 | } |
| 4093 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 4094 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4095 | { |
| 4096 | struct drm_device *dev = inode->i_private; |
| 4097 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4098 | |
Daniel Vetter | 075edca | 2012-01-24 09:44:28 +0100 | [diff] [blame] | 4099 | if (INTEL_INFO(dev)->gen < 6) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4100 | return 0; |
| 4101 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 4102 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4103 | |
| 4104 | return 0; |
| 4105 | } |
| 4106 | |
| 4107 | static const struct file_operations i915_forcewake_fops = { |
| 4108 | .owner = THIS_MODULE, |
| 4109 | .open = i915_forcewake_open, |
| 4110 | .release = i915_forcewake_release, |
| 4111 | }; |
| 4112 | |
| 4113 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) |
| 4114 | { |
| 4115 | struct drm_device *dev = minor->dev; |
| 4116 | struct dentry *ent; |
| 4117 | |
| 4118 | ent = debugfs_create_file("i915_forcewake_user", |
Ben Widawsky | 8eb5729 | 2011-05-11 15:10:58 -0700 | [diff] [blame] | 4119 | S_IRUSR, |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4120 | root, dev, |
| 4121 | &i915_forcewake_fops); |
Wei Yongjun | f3c5fe9 | 2013-12-16 14:13:25 +0800 | [diff] [blame] | 4122 | if (!ent) |
| 4123 | return -ENOMEM; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4124 | |
Ben Widawsky | 8eb5729 | 2011-05-11 15:10:58 -0700 | [diff] [blame] | 4125 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4126 | } |
| 4127 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 4128 | static int i915_debugfs_create(struct dentry *root, |
| 4129 | struct drm_minor *minor, |
| 4130 | const char *name, |
| 4131 | const struct file_operations *fops) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4132 | { |
| 4133 | struct drm_device *dev = minor->dev; |
| 4134 | struct dentry *ent; |
| 4135 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 4136 | ent = debugfs_create_file(name, |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4137 | S_IRUGO | S_IWUSR, |
| 4138 | root, dev, |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 4139 | fops); |
Wei Yongjun | f3c5fe9 | 2013-12-16 14:13:25 +0800 | [diff] [blame] | 4140 | if (!ent) |
| 4141 | return -ENOMEM; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4142 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 4143 | return drm_add_fake_info_node(minor, ent, fops); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4144 | } |
| 4145 | |
Lespiau, Damien | 06c5bf8 | 2013-10-17 19:09:56 +0100 | [diff] [blame] | 4146 | static const struct drm_info_list i915_debugfs_list[] = { |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 4147 | {"i915_capabilities", i915_capabilities, 0}, |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4148 | {"i915_gem_objects", i915_gem_object_info, 0}, |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 4149 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 4150 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 4151 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 4152 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 4153 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 4154 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4155 | {"i915_gem_request", i915_gem_request_info, 0}, |
| 4156 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 4157 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4158 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 4159 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
| 4160 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, |
| 4161 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, |
Xiang, Haihao | 9010ebf | 2013-05-29 09:22:36 -0700 | [diff] [blame] | 4162 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
Deepak S | adb4bd1 | 2014-03-31 11:30:02 +0530 | [diff] [blame] | 4163 | {"i915_frequency_info", i915_frequency_info, 0}, |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 4164 | {"i915_drpc_info", i915_drpc_info, 0}, |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 4165 | {"i915_emon_status", i915_emon_status, 0}, |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 4166 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 4167 | {"i915_fbc_status", i915_fbc_status, 0}, |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 4168 | {"i915_ips_status", i915_ips_status, 0}, |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 4169 | {"i915_sr_status", i915_sr_status, 0}, |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 4170 | {"i915_opregion", i915_opregion, 0}, |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 4171 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 4172 | {"i915_context_status", i915_context_status, 0}, |
Ben Widawsky | c0ab1ae | 2014-08-07 13:24:26 +0100 | [diff] [blame] | 4173 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 4174 | {"i915_execlists", i915_execlists, 0}, |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4175 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 4176 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 4177 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 4178 | {"i915_llc", i915_llc, 0}, |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 4179 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 4180 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 4181 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 4182 | {"i915_pc8_status", i915_pc8_status, 0}, |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 4183 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 4184 | {"i915_display_info", i915_display_info, 0}, |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 4185 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
Daniel Vetter | 728e29d | 2014-06-25 22:01:53 +0300 | [diff] [blame] | 4186 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
Dave Airlie | 11bed958 | 2014-05-12 15:22:27 +1000 | [diff] [blame] | 4187 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
Damien Lespiau | 1ed1ef9 | 2014-08-30 16:50:59 +0100 | [diff] [blame] | 4188 | {"i915_wa_registers", i915_wa_registers, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4189 | }; |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 4190 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4191 | |
Lespiau, Damien | 06c5bf8 | 2013-10-17 19:09:56 +0100 | [diff] [blame] | 4192 | static const struct i915_debugfs_files { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4193 | const char *name; |
| 4194 | const struct file_operations *fops; |
| 4195 | } i915_debugfs_files[] = { |
| 4196 | {"i915_wedged", &i915_wedged_fops}, |
| 4197 | {"i915_max_freq", &i915_max_freq_fops}, |
| 4198 | {"i915_min_freq", &i915_min_freq_fops}, |
| 4199 | {"i915_cache_sharing", &i915_cache_sharing_fops}, |
| 4200 | {"i915_ring_stop", &i915_ring_stop_fops}, |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 4201 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
| 4202 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4203 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
| 4204 | {"i915_error_state", &i915_error_state_fops}, |
| 4205 | {"i915_next_seqno", &i915_next_seqno_fops}, |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 4206 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4207 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
| 4208 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, |
| 4209 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, |
Rodrigo Vivi | da46f93 | 2014-08-01 02:04:45 -0700 | [diff] [blame] | 4210 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4211 | }; |
| 4212 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4213 | void intel_display_crc_init(struct drm_device *dev) |
| 4214 | { |
| 4215 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | b378360 | 2013-11-14 11:30:42 +0100 | [diff] [blame] | 4216 | enum pipe pipe; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4217 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4218 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | b378360 | 2013-11-14 11:30:42 +0100 | [diff] [blame] | 4219 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4220 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 4221 | pipe_crc->opened = false; |
| 4222 | spin_lock_init(&pipe_crc->lock); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4223 | init_waitqueue_head(&pipe_crc->wq); |
| 4224 | } |
| 4225 | } |
| 4226 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 4227 | int i915_debugfs_init(struct drm_minor *minor) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4228 | { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4229 | int ret, i; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 4230 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4231 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
| 4232 | if (ret) |
| 4233 | return ret; |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 4234 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4235 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
| 4236 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); |
| 4237 | if (ret) |
| 4238 | return ret; |
| 4239 | } |
| 4240 | |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4241 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
| 4242 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
| 4243 | i915_debugfs_files[i].name, |
| 4244 | i915_debugfs_files[i].fops); |
| 4245 | if (ret) |
| 4246 | return ret; |
| 4247 | } |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 4248 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 4249 | return drm_debugfs_create_files(i915_debugfs_list, |
| 4250 | I915_DEBUGFS_ENTRIES, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4251 | minor->debugfs_root, minor); |
| 4252 | } |
| 4253 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 4254 | void i915_debugfs_cleanup(struct drm_minor *minor) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4255 | { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4256 | int i; |
| 4257 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 4258 | drm_debugfs_remove_files(i915_debugfs_list, |
| 4259 | I915_DEBUGFS_ENTRIES, minor); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4260 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4261 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
| 4262 | 1, minor); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4263 | |
Daniel Vetter | e309a99 | 2013-10-16 22:55:51 +0200 | [diff] [blame] | 4264 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4265 | struct drm_info_list *info_list = |
| 4266 | (struct drm_info_list *)&i915_pipe_crc_data[i]; |
| 4267 | |
| 4268 | drm_debugfs_remove_files(info_list, 1, minor); |
| 4269 | } |
| 4270 | |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4271 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
| 4272 | struct drm_info_list *info_list = |
| 4273 | (struct drm_info_list *) i915_debugfs_files[i].fops; |
| 4274 | |
| 4275 | drm_debugfs_remove_files(info_list, 1, minor); |
| 4276 | } |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4277 | } |