blob: 096507d2ca9a7323c8d8e674ff4da7d921e677e4 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 *
Takashi Iwaid01ce992007-07-27 16:52:19 +02003 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
Linus Torvalds1da177e2005-04-16 15:20:36 -070037#include <linux/delay.h>
38#include <linux/interrupt.h>
Randy Dunlap362775e2005-11-07 14:43:23 +010039#include <linux/kernel.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040#include <linux/module.h>
Andrew Morton24982c52008-03-04 10:08:58 +010041#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070042#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
Ingo Molnar62932df2006-01-16 16:34:20 +010046#include <linux/mutex.h>
Takashi Iwai0cbf0092008-10-29 16:18:25 +010047#include <linux/reboot.h>
Takashi Iwai27fe48d92011-09-28 17:16:09 +020048#include <linux/io.h>
49#ifdef CONFIG_X86
50/* for snoop control */
51#include <asm/pgtable.h>
52#include <asm/cacheflush.h>
53#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070054#include <sound/core.h>
55#include <sound/initval.h>
56#include "hda_codec.h"
57
58
Takashi Iwai5aba4f82008-01-07 15:16:37 +010059static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
60static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
61static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
62static char *model[SNDRV_CARDS];
63static int position_fix[SNDRV_CARDS];
Takashi Iwai5c0d7bc2008-06-10 17:53:35 +020064static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
Takashi Iwai5aba4f82008-01-07 15:16:37 +010065static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
Takashi Iwaid4d9cd032008-12-19 15:19:11 +010066static int probe_only[SNDRV_CARDS];
Takashi Iwai27346162006-01-12 18:28:44 +010067static int single_cmd;
Takashi Iwai716238552009-09-28 13:14:04 +020068static int enable_msi = -1;
Takashi Iwai4ea6fbc2009-06-17 09:52:54 +020069#ifdef CONFIG_SND_HDA_PATCH_LOADER
70static char *patch[SNDRV_CARDS];
71#endif
Jaroslav Kysela2dca0bb2009-11-13 18:41:52 +010072#ifdef CONFIG_SND_HDA_INPUT_BEEP
73static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
74 CONFIG_SND_HDA_INPUT_BEEP_MODE};
75#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070076
Takashi Iwai5aba4f82008-01-07 15:16:37 +010077module_param_array(index, int, NULL, 0444);
Linus Torvalds1da177e2005-04-16 15:20:36 -070078MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
Takashi Iwai5aba4f82008-01-07 15:16:37 +010079module_param_array(id, charp, NULL, 0444);
Linus Torvalds1da177e2005-04-16 15:20:36 -070080MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
Takashi Iwai5aba4f82008-01-07 15:16:37 +010081module_param_array(enable, bool, NULL, 0444);
82MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
83module_param_array(model, charp, NULL, 0444);
Linus Torvalds1da177e2005-04-16 15:20:36 -070084MODULE_PARM_DESC(model, "Use the given board model.");
Takashi Iwai5aba4f82008-01-07 15:16:37 +010085module_param_array(position_fix, int, NULL, 0444);
David Henningsson4cb36312010-09-30 10:12:50 +020086MODULE_PARM_DESC(position_fix, "DMA pointer read method."
87 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
Takashi Iwai555e2192008-06-10 17:53:34 +020088module_param_array(bdl_pos_adj, int, NULL, 0644);
89MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
Takashi Iwai5aba4f82008-01-07 15:16:37 +010090module_param_array(probe_mask, int, NULL, 0444);
Takashi Iwai606ad752005-11-24 16:03:40 +010091MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
Jaroslav Kysela079e6832010-03-26 11:16:59 +010092module_param_array(probe_only, int, NULL, 0444);
Takashi Iwaid4d9cd032008-12-19 15:19:11 +010093MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
Takashi Iwai27346162006-01-12 18:28:44 +010094module_param(single_cmd, bool, 0444);
Takashi Iwaid01ce992007-07-27 16:52:19 +020095MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
96 "(for debugging only).");
Takashi Iwai5aba4f82008-01-07 15:16:37 +010097module_param(enable_msi, int, 0444);
Takashi Iwai134a11f2006-11-10 12:08:37 +010098MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
Takashi Iwai4ea6fbc2009-06-17 09:52:54 +020099#ifdef CONFIG_SND_HDA_PATCH_LOADER
100module_param_array(patch, charp, NULL, 0444);
101MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
102#endif
Jaroslav Kysela2dca0bb2009-11-13 18:41:52 +0100103#ifdef CONFIG_SND_HDA_INPUT_BEEP
104module_param_array(beep_mode, int, NULL, 0444);
105MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
106 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
107#endif
Takashi Iwai606ad752005-11-24 16:03:40 +0100108
Takashi Iwaidee1b662007-08-13 16:10:30 +0200109#ifdef CONFIG_SND_HDA_POWER_SAVE
Takashi Iwaifee2fba2008-11-27 12:43:28 +0100110static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
111module_param(power_save, int, 0644);
112MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
113 "(in second, 0 = disable).");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114
Takashi Iwaidee1b662007-08-13 16:10:30 +0200115/* reset the HD-audio controller in power save mode.
116 * this may give more power-saving, but will take longer time to
117 * wake up.
118 */
119static int power_save_controller = 1;
120module_param(power_save_controller, bool, 0644);
121MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
122#endif
123
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -0500124static int align_buffer_size = 1;
125module_param(align_buffer_size, bool, 0644);
126MODULE_PARM_DESC(align_buffer_size,
127 "Force buffer and period sizes to be multiple of 128 bytes.");
128
Takashi Iwai27fe48d92011-09-28 17:16:09 +0200129#ifdef CONFIG_X86
130static bool hda_snoop = true;
131module_param_named(snoop, hda_snoop, bool, 0444);
132MODULE_PARM_DESC(snoop, "Enable/disable snooping");
133#define azx_snoop(chip) (chip)->snoop
134#else
135#define hda_snoop true
136#define azx_snoop(chip) true
137#endif
138
139
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140MODULE_LICENSE("GPL");
141MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
142 "{Intel, ICH6M},"
Jason Gaston2f1b3812005-05-01 08:58:50 -0700143 "{Intel, ICH7},"
Frederick Lif5d40b32005-05-12 14:55:20 +0200144 "{Intel, ESB2},"
Jason Gastond2981392006-01-10 11:07:37 +0100145 "{Intel, ICH8},"
Jason Gastonf9cc8a82006-11-22 11:53:52 +0100146 "{Intel, ICH9},"
Jason Gastonc34f5a02008-01-29 12:38:49 +0100147 "{Intel, ICH10},"
Seth Heasleyb29c2362008-08-08 15:56:39 -0700148 "{Intel, PCH},"
Seth Heasleyd2f2fcd2010-01-12 17:03:35 -0800149 "{Intel, CPT},"
Seth Heasleyd2edeb72011-04-20 10:59:57 -0700150 "{Intel, PPT},"
Seth Heasleycea310e2010-09-10 16:29:56 -0700151 "{Intel, PBG},"
Tobin Davis4979bca2008-01-30 08:13:55 +0100152 "{Intel, SCH},"
Takashi Iwaifc20a562005-05-12 15:00:41 +0200153 "{ATI, SB450},"
Felix Kuehling89be83f2006-03-31 12:33:59 +0200154 "{ATI, SB600},"
Felix Kuehling778b6e12006-05-17 11:22:21 +0200155 "{ATI, RS600},"
Felix Kuehling5b15c952006-10-16 12:49:47 +0200156 "{ATI, RS690},"
Wolke Liue6db1112007-04-27 12:20:57 +0200157 "{ATI, RS780},"
158 "{ATI, R600},"
Herton Ronaldo Krzesinski2797f722007-11-05 18:21:56 +0100159 "{ATI, RV630},"
160 "{ATI, RV610},"
Wolke Liu27da1832007-11-16 11:06:30 +0100161 "{ATI, RV670},"
162 "{ATI, RV635},"
163 "{ATI, RV620},"
164 "{ATI, RV770},"
Takashi Iwaifc20a562005-05-12 15:00:41 +0200165 "{VIA, VT8251},"
Takashi Iwai47672312005-08-12 16:44:04 +0200166 "{VIA, VT8237A},"
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200167 "{SiS, SIS966},"
168 "{ULI, M5461}}");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700169MODULE_DESCRIPTION("Intel HDA driver");
170
Takashi Iwai4abc1cc2009-05-19 12:16:46 +0200171#ifdef CONFIG_SND_VERBOSE_PRINTK
172#define SFX /* nop */
173#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174#define SFX "hda-intel: "
Takashi Iwai4abc1cc2009-05-19 12:16:46 +0200175#endif
Takashi Iwaicb53c622007-08-10 17:21:45 +0200176
177/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178 * registers
179 */
180#define ICH6_REG_GCAP 0x00
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200181#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
182#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
183#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
184#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
185#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186#define ICH6_REG_VMIN 0x02
187#define ICH6_REG_VMAJ 0x03
188#define ICH6_REG_OUTPAY 0x04
189#define ICH6_REG_INPAY 0x06
190#define ICH6_REG_GCTL 0x08
Takashi Iwai8a933ec2009-05-31 09:28:12 +0200191#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200192#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
193#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194#define ICH6_REG_WAKEEN 0x0c
195#define ICH6_REG_STATESTS 0x0e
196#define ICH6_REG_GSTS 0x10
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200197#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198#define ICH6_REG_INTCTL 0x20
199#define ICH6_REG_INTSTS 0x24
Jaroslav Kyselae5463722010-05-11 10:21:46 +0200200#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
Takashi Iwai8b0bd222011-06-10 14:56:26 +0200201#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
202#define ICH6_REG_SSYNC 0x38
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203#define ICH6_REG_CORBLBASE 0x40
204#define ICH6_REG_CORBUBASE 0x44
205#define ICH6_REG_CORBWP 0x48
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200206#define ICH6_REG_CORBRP 0x4a
207#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700208#define ICH6_REG_CORBCTL 0x4c
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200209#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
210#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700211#define ICH6_REG_CORBSTS 0x4d
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200212#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213#define ICH6_REG_CORBSIZE 0x4e
214
215#define ICH6_REG_RIRBLBASE 0x50
216#define ICH6_REG_RIRBUBASE 0x54
217#define ICH6_REG_RIRBWP 0x58
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200218#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219#define ICH6_REG_RINTCNT 0x5a
220#define ICH6_REG_RIRBCTL 0x5c
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200221#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
222#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
223#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224#define ICH6_REG_RIRBSTS 0x5d
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200225#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
226#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227#define ICH6_REG_RIRBSIZE 0x5e
228
229#define ICH6_REG_IC 0x60
230#define ICH6_REG_IR 0x64
231#define ICH6_REG_IRS 0x68
232#define ICH6_IRS_VALID (1<<1)
233#define ICH6_IRS_BUSY (1<<0)
234
235#define ICH6_REG_DPLBASE 0x70
236#define ICH6_REG_DPUBASE 0x74
237#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
238
239/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
240enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
241
242/* stream register offsets from stream base */
243#define ICH6_REG_SD_CTL 0x00
244#define ICH6_REG_SD_STS 0x03
245#define ICH6_REG_SD_LPIB 0x04
246#define ICH6_REG_SD_CBL 0x08
247#define ICH6_REG_SD_LVI 0x0c
248#define ICH6_REG_SD_FIFOW 0x0e
249#define ICH6_REG_SD_FIFOSIZE 0x10
250#define ICH6_REG_SD_FORMAT 0x12
251#define ICH6_REG_SD_BDLPL 0x18
252#define ICH6_REG_SD_BDLPU 0x1c
253
254/* PCI space */
255#define ICH6_PCIREG_TCSEL 0x44
256
257/*
258 * other constants
259 */
260
261/* max number of SDs */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200262/* ICH, ATI and VIA have 4 playback and 4 capture */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200263#define ICH6_NUM_CAPTURE 4
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200264#define ICH6_NUM_PLAYBACK 4
265
266/* ULI has 6 playback and 5 capture */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200267#define ULI_NUM_CAPTURE 5
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200268#define ULI_NUM_PLAYBACK 6
269
Felix Kuehling778b6e12006-05-17 11:22:21 +0200270/* ATI HDMI has 1 playback and 0 capture */
Felix Kuehling778b6e12006-05-17 11:22:21 +0200271#define ATIHDMI_NUM_CAPTURE 0
Felix Kuehling778b6e12006-05-17 11:22:21 +0200272#define ATIHDMI_NUM_PLAYBACK 1
273
Kailang Yangf2690022008-05-27 11:44:55 +0200274/* TERA has 4 playback and 3 capture */
275#define TERA_NUM_CAPTURE 3
276#define TERA_NUM_PLAYBACK 4
277
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200278/* this number is statically defined for simplicity */
279#define MAX_AZX_DEV 16
280
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281/* max number of fragments - we may use more if allocating more pages for BDL */
Takashi Iwai4ce107b2008-02-06 14:50:19 +0100282#define BDL_SIZE 4096
283#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
284#define AZX_MAX_FRAG 32
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285/* max buffer size - no h/w limit, you can increase as you like */
286#define AZX_MAX_BUF_SIZE (1024*1024*1024)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700287
288/* RIRB int mask: overrun[2], response[0] */
289#define RIRB_INT_RESPONSE 0x01
290#define RIRB_INT_OVERRUN 0x04
291#define RIRB_INT_MASK 0x05
292
Takashi Iwai2f5983f2008-09-03 16:00:44 +0200293/* STATESTS int mask: S3,SD2,SD1,SD0 */
Wei Ni7445dfc2010-03-03 15:05:53 +0800294#define AZX_MAX_CODECS 8
295#define AZX_DEFAULT_CODECS 4
Wu Fengguangdeadff12009-08-01 18:45:16 +0800296#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297
298/* SD_CTL bits */
299#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
300#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
Takashi Iwai850f0e52008-03-18 17:11:05 +0100301#define SD_CTL_STRIPE (3 << 16) /* stripe control */
302#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
303#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
305#define SD_CTL_STREAM_TAG_SHIFT 20
306
307/* SD_CTL and SD_STS */
308#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
309#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
310#define SD_INT_COMPLETE 0x04 /* completion interrupt */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200311#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
312 SD_INT_COMPLETE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700313
314/* SD_STS */
315#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
316
317/* INTCTL and INTSTS */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200318#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
319#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
320#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321
Linus Torvalds1da177e2005-04-16 15:20:36 -0700322/* below are so far hardcoded - should read registers in future */
323#define ICH6_MAX_CORB_ENTRIES 256
324#define ICH6_MAX_RIRB_ENTRIES 256
325
Takashi Iwaic74db862005-05-12 14:26:27 +0200326/* position fix mode */
327enum {
Takashi Iwai0be3b5d2005-09-05 17:11:40 +0200328 POS_FIX_AUTO,
Takashi Iwaid2e1c972008-06-10 17:53:34 +0200329 POS_FIX_LPIB,
Takashi Iwai0be3b5d2005-09-05 17:11:40 +0200330 POS_FIX_POSBUF,
David Henningsson4cb36312010-09-30 10:12:50 +0200331 POS_FIX_VIACOMBO,
Takashi Iwaic74db862005-05-12 14:26:27 +0200332};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333
Frederick Lif5d40b32005-05-12 14:55:20 +0200334/* Defines for ATI HD Audio support in SB450 south bridge */
Frederick Lif5d40b32005-05-12 14:55:20 +0200335#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
336#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
337
Vinod Gda3fca22005-09-13 18:49:12 +0200338/* Defines for Nvidia HDA support */
339#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
340#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
Peer Chen320dcc32008-08-20 16:43:24 -0700341#define NVIDIA_HDA_ISTRM_COH 0x4d
342#define NVIDIA_HDA_OSTRM_COH 0x4c
343#define NVIDIA_HDA_ENABLE_COHBIT 0x01
Frederick Lif5d40b32005-05-12 14:55:20 +0200344
Takashi Iwai90a5ad52008-02-22 18:36:22 +0100345/* Defines for Intel SCH HDA snoop control */
346#define INTEL_SCH_HDA_DEVC 0x78
347#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
348
Joseph Chan0e153472008-08-26 14:38:03 +0200349/* Define IN stream 0 FIFO size offset in VIA controller */
350#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
351/* Define VIA HD Audio Device ID*/
352#define VIA_HDAC_DEVICE_ID 0x3288
353
Yang, Libinc4da29c2008-11-13 11:07:07 +0100354/* HD Audio class code */
355#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
Takashi Iwai90a5ad52008-02-22 18:36:22 +0100356
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358 */
359
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100360struct azx_dev {
Takashi Iwai4ce107b2008-02-06 14:50:19 +0100361 struct snd_dma_buffer bdl; /* BDL buffer */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200362 u32 *posbuf; /* position buffer pointer */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700363
Takashi Iwaid01ce992007-07-27 16:52:19 +0200364 unsigned int bufsize; /* size of the play buffer in bytes */
Takashi Iwai9ad593f2008-05-16 12:34:47 +0200365 unsigned int period_bytes; /* size of the period in bytes */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200366 unsigned int frags; /* number for period in the play buffer */
367 unsigned int fifo_size; /* FIFO size */
Jaroslav Kyselae5463722010-05-11 10:21:46 +0200368 unsigned long start_wallclk; /* start + minimum wallclk */
369 unsigned long period_wallclk; /* wallclk for period */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370
Takashi Iwaid01ce992007-07-27 16:52:19 +0200371 void __iomem *sd_addr; /* stream descriptor pointer */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372
Takashi Iwaid01ce992007-07-27 16:52:19 +0200373 u32 sd_int_sta_mask; /* stream int status mask */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374
375 /* pcm support */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200376 struct snd_pcm_substream *substream; /* assigned substream,
377 * set in PCM open
378 */
379 unsigned int format_val; /* format value to be set in the
380 * controller and the codec
381 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382 unsigned char stream_tag; /* assigned stream */
383 unsigned char index; /* stream index */
Takashi Iwaid5cf9912011-10-06 10:07:58 +0200384 int assigned_key; /* last device# key assigned to */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700385
Pavel Machek927fc862006-08-31 17:03:43 +0200386 unsigned int opened :1;
387 unsigned int running :1;
Takashi Iwai675f25d2008-06-10 17:53:20 +0200388 unsigned int irq_pending :1;
Joseph Chan0e153472008-08-26 14:38:03 +0200389 /*
390 * For VIA:
391 * A flag to ensure DMA position is 0
392 * when link position is not greater than FIFO size
393 */
394 unsigned int insufficient :1;
Takashi Iwai27fe48d92011-09-28 17:16:09 +0200395 unsigned int wc_marked:1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396};
397
398/* CORB/RIRB */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100399struct azx_rb {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400 u32 *buf; /* CORB/RIRB buffer
401 * Each CORB entry is 4byte, RIRB is 8byte
402 */
403 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
404 /* for RIRB */
405 unsigned short rp, wp; /* read/write pointers */
Wu Fengguangdeadff12009-08-01 18:45:16 +0800406 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
407 u32 res[AZX_MAX_CODECS]; /* last read value */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408};
409
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100410struct azx {
411 struct snd_card *card;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412 struct pci_dev *pci;
Takashi Iwai555e2192008-06-10 17:53:34 +0200413 int dev_index;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200415 /* chip type specific */
416 int driver_type;
Takashi Iwai9477c582011-05-25 09:11:37 +0200417 unsigned int driver_caps;
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200418 int playback_streams;
419 int playback_index_offset;
420 int capture_streams;
421 int capture_index_offset;
422 int num_streams;
423
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424 /* pci resources */
425 unsigned long addr;
426 void __iomem *remap_addr;
427 int irq;
428
429 /* locks */
430 spinlock_t reg_lock;
Ingo Molnar62932df2006-01-16 16:34:20 +0100431 struct mutex open_mutex;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200433 /* streams (x num_streams) */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100434 struct azx_dev *azx_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435
436 /* PCM */
Takashi Iwaic8936222010-01-28 17:08:53 +0100437 struct snd_pcm *pcm[HDA_MAX_PCMS];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438
439 /* HD codec */
440 unsigned short codec_mask;
Takashi Iwaif1eaaee2009-02-13 08:16:55 +0100441 int codec_probe_mask; /* copied from probe_mask option */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442 struct hda_bus *bus;
Jaroslav Kysela2dca0bb2009-11-13 18:41:52 +0100443 unsigned int beep_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444
445 /* CORB/RIRB */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100446 struct azx_rb corb;
447 struct azx_rb rirb;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448
Takashi Iwai4ce107b2008-02-06 14:50:19 +0100449 /* CORB/RIRB and position buffers */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450 struct snd_dma_buffer rb;
451 struct snd_dma_buffer posbuf;
Takashi Iwaic74db862005-05-12 14:26:27 +0200452
453 /* flags */
Shahin Ghazinouribeaffc32010-05-11 08:19:55 +0200454 int position_fix[2]; /* for both playback/capture streams */
Maxim Levitsky1eb6dc72010-02-04 22:21:47 +0200455 int poll_count;
Takashi Iwaicb53c622007-08-10 17:21:45 +0200456 unsigned int running :1;
Pavel Machek927fc862006-08-31 17:03:43 +0200457 unsigned int initialized :1;
458 unsigned int single_cmd :1;
459 unsigned int polling_mode :1;
Takashi Iwai68e7fff2006-10-23 13:40:59 +0200460 unsigned int msi :1;
Takashi Iwaia6a950a2008-06-10 17:53:35 +0200461 unsigned int irq_pending_warned :1;
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +0100462 unsigned int probing :1; /* codec probing phase */
Takashi Iwai27fe48d92011-09-28 17:16:09 +0200463 unsigned int snoop:1;
Takashi Iwai43bbb6c2007-07-06 20:22:05 +0200464
465 /* for debugging */
Wu Fengguangfeb27342009-08-01 19:17:14 +0800466 unsigned int last_cmd[AZX_MAX_CODECS];
Takashi Iwai9ad593f2008-05-16 12:34:47 +0200467
468 /* for pending irqs */
469 struct work_struct irq_pending_work;
Takashi Iwai0cbf0092008-10-29 16:18:25 +0100470
471 /* reboot notifier (for mysterious hangup problem at power-down) */
472 struct notifier_block reboot_notifier;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473};
474
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200475/* driver types */
476enum {
477 AZX_DRIVER_ICH,
Seth Heasley32679f92010-02-22 17:31:09 -0800478 AZX_DRIVER_PCH,
Tobin Davis4979bca2008-01-30 08:13:55 +0100479 AZX_DRIVER_SCH,
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200480 AZX_DRIVER_ATI,
Felix Kuehling778b6e12006-05-17 11:22:21 +0200481 AZX_DRIVER_ATIHDMI,
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200482 AZX_DRIVER_VIA,
483 AZX_DRIVER_SIS,
484 AZX_DRIVER_ULI,
Vinod Gda3fca22005-09-13 18:49:12 +0200485 AZX_DRIVER_NVIDIA,
Kailang Yangf2690022008-05-27 11:44:55 +0200486 AZX_DRIVER_TERA,
Takashi Iwai14d34f12010-10-21 09:03:25 +0200487 AZX_DRIVER_CTX,
Yang, Libinc4da29c2008-11-13 11:07:07 +0100488 AZX_DRIVER_GENERIC,
Takashi Iwai2f5983f2008-09-03 16:00:44 +0200489 AZX_NUM_DRIVERS, /* keep this as last entry */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200490};
491
Takashi Iwai9477c582011-05-25 09:11:37 +0200492/* driver quirks (capabilities) */
493/* bits 0-7 are used for indicating driver type */
494#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
495#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
496#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
497#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
498#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
499#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
500#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
501#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
502#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
503#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
504#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
505#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
Takashi Iwai8b0bd222011-06-10 14:56:26 +0200506#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -0500507#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
Takashi Iwai9477c582011-05-25 09:11:37 +0200508
509/* quirks for ATI SB / AMD Hudson */
510#define AZX_DCAPS_PRESET_ATI_SB \
511 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
512 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
513
514/* quirks for ATI/AMD HDMI */
515#define AZX_DCAPS_PRESET_ATI_HDMI \
516 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
517
518/* quirks for Nvidia */
519#define AZX_DCAPS_PRESET_NVIDIA \
520 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI)
521
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200522static char *driver_short_names[] __devinitdata = {
523 [AZX_DRIVER_ICH] = "HDA Intel",
Seth Heasley32679f92010-02-22 17:31:09 -0800524 [AZX_DRIVER_PCH] = "HDA Intel PCH",
Tobin Davis4979bca2008-01-30 08:13:55 +0100525 [AZX_DRIVER_SCH] = "HDA Intel MID",
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200526 [AZX_DRIVER_ATI] = "HDA ATI SB",
Felix Kuehling778b6e12006-05-17 11:22:21 +0200527 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200528 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
529 [AZX_DRIVER_SIS] = "HDA SIS966",
Vinod Gda3fca22005-09-13 18:49:12 +0200530 [AZX_DRIVER_ULI] = "HDA ULI M5461",
531 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
Kailang Yangf2690022008-05-27 11:44:55 +0200532 [AZX_DRIVER_TERA] = "HDA Teradici",
Takashi Iwai14d34f12010-10-21 09:03:25 +0200533 [AZX_DRIVER_CTX] = "HDA Creative",
Yang, Libinc4da29c2008-11-13 11:07:07 +0100534 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200535};
536
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537/*
538 * macros for easy use
539 */
540#define azx_writel(chip,reg,value) \
541 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
542#define azx_readl(chip,reg) \
543 readl((chip)->remap_addr + ICH6_REG_##reg)
544#define azx_writew(chip,reg,value) \
545 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
546#define azx_readw(chip,reg) \
547 readw((chip)->remap_addr + ICH6_REG_##reg)
548#define azx_writeb(chip,reg,value) \
549 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
550#define azx_readb(chip,reg) \
551 readb((chip)->remap_addr + ICH6_REG_##reg)
552
553#define azx_sd_writel(dev,reg,value) \
554 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
555#define azx_sd_readl(dev,reg) \
556 readl((dev)->sd_addr + ICH6_REG_##reg)
557#define azx_sd_writew(dev,reg,value) \
558 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
559#define azx_sd_readw(dev,reg) \
560 readw((dev)->sd_addr + ICH6_REG_##reg)
561#define azx_sd_writeb(dev,reg,value) \
562 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
563#define azx_sd_readb(dev,reg) \
564 readb((dev)->sd_addr + ICH6_REG_##reg)
565
566/* for pcm support */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100567#define get_azx_dev(substream) (substream->runtime->private_data)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700568
Takashi Iwai27fe48d92011-09-28 17:16:09 +0200569#ifdef CONFIG_X86
570static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
571{
572 if (azx_snoop(chip))
573 return;
574 if (addr && size) {
575 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
576 if (on)
577 set_memory_wc((unsigned long)addr, pages);
578 else
579 set_memory_wb((unsigned long)addr, pages);
580 }
581}
582
583static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
584 bool on)
585{
586 __mark_pages_wc(chip, buf->area, buf->bytes, on);
587}
588static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
589 struct snd_pcm_runtime *runtime, bool on)
590{
591 if (azx_dev->wc_marked != on) {
592 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
593 azx_dev->wc_marked = on;
594 }
595}
596#else
597/* NOP for other archs */
598static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
599 bool on)
600{
601}
602static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
603 struct snd_pcm_runtime *runtime, bool on)
604{
605}
606#endif
607
Takashi Iwai68e7fff2006-10-23 13:40:59 +0200608static int azx_acquire_irq(struct azx *chip, int do_disconnect);
Maxim Levitsky1eb6dc72010-02-04 22:21:47 +0200609static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610/*
611 * Interface for HD codec
612 */
613
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614/*
615 * CORB / RIRB interface
616 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100617static int azx_alloc_cmd_io(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700618{
619 int err;
620
621 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200622 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
623 snd_dma_pci_data(chip->pci),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700624 PAGE_SIZE, &chip->rb);
625 if (err < 0) {
626 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
627 return err;
628 }
Takashi Iwai27fe48d92011-09-28 17:16:09 +0200629 mark_pages_wc(chip, &chip->rb, true);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700630 return 0;
631}
632
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100633static void azx_init_cmd_io(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634{
Wu Fengguangcdb1fbf2009-08-01 18:47:41 +0800635 spin_lock_irq(&chip->reg_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700636 /* CORB set up */
637 chip->corb.addr = chip->rb.addr;
638 chip->corb.buf = (u32 *)chip->rb.area;
639 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
Takashi Iwai766979e2008-06-13 20:53:56 +0200640 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200642 /* set the corb size to 256 entries (ULI requires explicitly) */
643 azx_writeb(chip, CORBSIZE, 0x02);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700644 /* set the corb write pointer to 0 */
645 azx_writew(chip, CORBWP, 0);
646 /* reset the corb hw read pointer */
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200647 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648 /* enable corb dma */
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200649 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700650
651 /* RIRB set up */
652 chip->rirb.addr = chip->rb.addr + 2048;
653 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
Wu Fengguangdeadff12009-08-01 18:45:16 +0800654 chip->rirb.wp = chip->rirb.rp = 0;
655 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700656 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
Takashi Iwai766979e2008-06-13 20:53:56 +0200657 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700658
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200659 /* set the rirb size to 256 entries (ULI requires explicitly) */
660 azx_writeb(chip, RIRBSIZE, 0x02);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661 /* reset the rirb hw write pointer */
Takashi Iwaib21fadb2009-05-28 12:26:15 +0200662 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663 /* set N=1, get RIRB response interrupt for new entry */
Takashi Iwai9477c582011-05-25 09:11:37 +0200664 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
Takashi Iwai14d34f12010-10-21 09:03:25 +0200665 azx_writew(chip, RINTCNT, 0xc0);
666 else
667 azx_writew(chip, RINTCNT, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700668 /* enable rirb dma and response irq */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700669 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
Wu Fengguangcdb1fbf2009-08-01 18:47:41 +0800670 spin_unlock_irq(&chip->reg_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671}
672
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100673static void azx_free_cmd_io(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700674{
Wu Fengguangcdb1fbf2009-08-01 18:47:41 +0800675 spin_lock_irq(&chip->reg_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700676 /* disable ringbuffer DMAs */
677 azx_writeb(chip, RIRBCTL, 0);
678 azx_writeb(chip, CORBCTL, 0);
Wu Fengguangcdb1fbf2009-08-01 18:47:41 +0800679 spin_unlock_irq(&chip->reg_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680}
681
Wu Fengguangdeadff12009-08-01 18:45:16 +0800682static unsigned int azx_command_addr(u32 cmd)
683{
684 unsigned int addr = cmd >> 28;
685
686 if (addr >= AZX_MAX_CODECS) {
687 snd_BUG();
688 addr = 0;
689 }
690
691 return addr;
692}
693
694static unsigned int azx_response_addr(u32 res)
695{
696 unsigned int addr = res & 0xf;
697
698 if (addr >= AZX_MAX_CODECS) {
699 snd_BUG();
700 addr = 0;
701 }
702
703 return addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704}
705
706/* send a command */
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100707static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700708{
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100709 struct azx *chip = bus->private_data;
Wu Fengguangdeadff12009-08-01 18:45:16 +0800710 unsigned int addr = azx_command_addr(val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700711 unsigned int wp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700712
Wu Fengguangc32649f2009-08-01 18:48:12 +0800713 spin_lock_irq(&chip->reg_lock);
714
Linus Torvalds1da177e2005-04-16 15:20:36 -0700715 /* add command to corb */
716 wp = azx_readb(chip, CORBWP);
717 wp++;
718 wp %= ICH6_MAX_CORB_ENTRIES;
719
Wu Fengguangdeadff12009-08-01 18:45:16 +0800720 chip->rirb.cmds[addr]++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700721 chip->corb.buf[wp] = cpu_to_le32(val);
722 azx_writel(chip, CORBWP, wp);
Wu Fengguangc32649f2009-08-01 18:48:12 +0800723
Linus Torvalds1da177e2005-04-16 15:20:36 -0700724 spin_unlock_irq(&chip->reg_lock);
725
726 return 0;
727}
728
729#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
730
731/* retrieve RIRB entry - called from interrupt handler */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100732static void azx_update_rirb(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700733{
734 unsigned int rp, wp;
Wu Fengguangdeadff12009-08-01 18:45:16 +0800735 unsigned int addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700736 u32 res, res_ex;
737
738 wp = azx_readb(chip, RIRBWP);
739 if (wp == chip->rirb.wp)
740 return;
741 chip->rirb.wp = wp;
Wu Fengguangdeadff12009-08-01 18:45:16 +0800742
Linus Torvalds1da177e2005-04-16 15:20:36 -0700743 while (chip->rirb.rp != wp) {
744 chip->rirb.rp++;
745 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
746
747 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
748 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
749 res = le32_to_cpu(chip->rirb.buf[rp]);
Wu Fengguangdeadff12009-08-01 18:45:16 +0800750 addr = azx_response_addr(res_ex);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
752 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
Wu Fengguangdeadff12009-08-01 18:45:16 +0800753 else if (chip->rirb.cmds[addr]) {
754 chip->rirb.res[addr] = res;
Takashi Iwai2add9b92008-03-18 09:47:06 +0100755 smp_wmb();
Wu Fengguangdeadff12009-08-01 18:45:16 +0800756 chip->rirb.cmds[addr]--;
Wu Fengguange310bb02009-08-01 19:18:45 +0800757 } else
758 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
759 "last cmd=%#08x\n",
760 res, res_ex,
761 chip->last_cmd[addr]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700762 }
763}
764
765/* receive a response */
Wu Fengguangdeadff12009-08-01 18:45:16 +0800766static unsigned int azx_rirb_get_response(struct hda_bus *bus,
767 unsigned int addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700768{
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100769 struct azx *chip = bus->private_data;
Takashi Iwai5c79b1f2006-09-21 13:34:13 +0200770 unsigned long timeout;
Maxim Levitsky1eb6dc72010-02-04 22:21:47 +0200771 int do_poll = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772
Takashi Iwai5c79b1f2006-09-21 13:34:13 +0200773 again:
774 timeout = jiffies + msecs_to_jiffies(1000);
Takashi Iwai28a0d9d2008-01-18 15:32:32 +0100775 for (;;) {
Maxim Levitsky1eb6dc72010-02-04 22:21:47 +0200776 if (chip->polling_mode || do_poll) {
Takashi Iwaie96224a2006-08-21 17:57:44 +0200777 spin_lock_irq(&chip->reg_lock);
778 azx_update_rirb(chip);
779 spin_unlock_irq(&chip->reg_lock);
780 }
Wu Fengguangdeadff12009-08-01 18:45:16 +0800781 if (!chip->rirb.cmds[addr]) {
Takashi Iwai2add9b92008-03-18 09:47:06 +0100782 smp_rmb();
Takashi Iwaib6132912009-03-24 07:36:09 +0100783 bus->rirb_error = 0;
Maxim Levitsky1eb6dc72010-02-04 22:21:47 +0200784
785 if (!do_poll)
786 chip->poll_count = 0;
Wu Fengguangdeadff12009-08-01 18:45:16 +0800787 return chip->rirb.res[addr]; /* the last value */
Takashi Iwai2add9b92008-03-18 09:47:06 +0100788 }
Takashi Iwai28a0d9d2008-01-18 15:32:32 +0100789 if (time_after(jiffies, timeout))
790 break;
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100791 if (bus->needs_damn_long_delay)
Takashi Iwai52987652008-01-16 16:09:47 +0100792 msleep(2); /* temporary workaround */
793 else {
794 udelay(10);
795 cond_resched();
796 }
Takashi Iwai28a0d9d2008-01-18 15:32:32 +0100797 }
Takashi Iwai5c79b1f2006-09-21 13:34:13 +0200798
Maxim Levitsky1eb6dc72010-02-04 22:21:47 +0200799 if (!chip->polling_mode && chip->poll_count < 2) {
800 snd_printdd(SFX "azx_get_response timeout, "
801 "polling the codec once: last cmd=0x%08x\n",
802 chip->last_cmd[addr]);
803 do_poll = 1;
804 chip->poll_count++;
805 goto again;
806 }
807
808
Takashi Iwai23c4a882009-10-30 13:21:49 +0100809 if (!chip->polling_mode) {
810 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
811 "switching to polling mode: last cmd=0x%08x\n",
812 chip->last_cmd[addr]);
813 chip->polling_mode = 1;
814 goto again;
815 }
816
Takashi Iwai68e7fff2006-10-23 13:40:59 +0200817 if (chip->msi) {
Takashi Iwai4abc1cc2009-05-19 12:16:46 +0200818 snd_printk(KERN_WARNING SFX "No response from codec, "
Wu Fengguangfeb27342009-08-01 19:17:14 +0800819 "disabling MSI: last cmd=0x%08x\n",
820 chip->last_cmd[addr]);
Takashi Iwai68e7fff2006-10-23 13:40:59 +0200821 free_irq(chip->irq, chip);
822 chip->irq = -1;
823 pci_disable_msi(chip->pci);
824 chip->msi = 0;
Takashi Iwaib6132912009-03-24 07:36:09 +0100825 if (azx_acquire_irq(chip, 1) < 0) {
826 bus->rirb_error = 1;
Takashi Iwai68e7fff2006-10-23 13:40:59 +0200827 return -1;
Takashi Iwaib6132912009-03-24 07:36:09 +0100828 }
Takashi Iwai68e7fff2006-10-23 13:40:59 +0200829 goto again;
830 }
831
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +0100832 if (chip->probing) {
833 /* If this critical timeout happens during the codec probing
834 * phase, this is likely an access to a non-existing codec
835 * slot. Better to return an error and reset the system.
836 */
837 return -1;
838 }
839
Takashi Iwai8dd78332009-06-02 01:16:07 +0200840 /* a fatal communication error; need either to reset or to fallback
841 * to the single_cmd mode
842 */
Takashi Iwaib6132912009-03-24 07:36:09 +0100843 bus->rirb_error = 1;
Takashi Iwaib20f3b82009-06-02 01:20:22 +0200844 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
Takashi Iwai8dd78332009-06-02 01:16:07 +0200845 bus->response_reset = 1;
846 return -1; /* give a chance to retry */
847 }
848
849 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
850 "switching to single_cmd mode: last cmd=0x%08x\n",
Wu Fengguangfeb27342009-08-01 19:17:14 +0800851 chip->last_cmd[addr]);
Takashi Iwai8dd78332009-06-02 01:16:07 +0200852 chip->single_cmd = 1;
853 bus->response_reset = 0;
Takashi Iwai1a696972009-11-07 09:49:04 +0100854 /* release CORB/RIRB */
Takashi Iwai4fcd3922009-05-25 18:34:52 +0200855 azx_free_cmd_io(chip);
Takashi Iwai1a696972009-11-07 09:49:04 +0100856 /* disable unsolicited responses */
857 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
Takashi Iwai5c79b1f2006-09-21 13:34:13 +0200858 return -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859}
860
Linus Torvalds1da177e2005-04-16 15:20:36 -0700861/*
862 * Use the single immediate command instead of CORB/RIRB for simplicity
863 *
864 * Note: according to Intel, this is not preferred use. The command was
865 * intended for the BIOS only, and may get confused with unsolicited
866 * responses. So, we shouldn't use it for normal operation from the
867 * driver.
868 * I left the codes, however, for debugging/testing purposes.
869 */
870
Takashi Iwaib05a7d42009-05-28 11:59:12 +0200871/* receive a response */
Wu Fengguangdeadff12009-08-01 18:45:16 +0800872static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
Takashi Iwaib05a7d42009-05-28 11:59:12 +0200873{
874 int timeout = 50;
875
876 while (timeout--) {
877 /* check IRV busy bit */
878 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
879 /* reuse rirb.res as the response return value */
Wu Fengguangdeadff12009-08-01 18:45:16 +0800880 chip->rirb.res[addr] = azx_readl(chip, IR);
Takashi Iwaib05a7d42009-05-28 11:59:12 +0200881 return 0;
882 }
883 udelay(1);
884 }
885 if (printk_ratelimit())
886 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
887 azx_readw(chip, IRS));
Wu Fengguangdeadff12009-08-01 18:45:16 +0800888 chip->rirb.res[addr] = -1;
Takashi Iwaib05a7d42009-05-28 11:59:12 +0200889 return -EIO;
890}
891
Linus Torvalds1da177e2005-04-16 15:20:36 -0700892/* send a command */
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100893static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700894{
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100895 struct azx *chip = bus->private_data;
Wu Fengguangdeadff12009-08-01 18:45:16 +0800896 unsigned int addr = azx_command_addr(val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700897 int timeout = 50;
898
Takashi Iwai8dd78332009-06-02 01:16:07 +0200899 bus->rirb_error = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700900 while (timeout--) {
901 /* check ICB busy bit */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200902 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700903 /* Clear IRV valid bit */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200904 azx_writew(chip, IRS, azx_readw(chip, IRS) |
905 ICH6_IRS_VALID);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700906 azx_writel(chip, IC, val);
Takashi Iwaid01ce992007-07-27 16:52:19 +0200907 azx_writew(chip, IRS, azx_readw(chip, IRS) |
908 ICH6_IRS_BUSY);
Wu Fengguangdeadff12009-08-01 18:45:16 +0800909 return azx_single_wait_for_response(chip, addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700910 }
911 udelay(1);
912 }
Marc Boucher1cfd52b2008-01-22 15:29:26 +0100913 if (printk_ratelimit())
914 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
915 azx_readw(chip, IRS), val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700916 return -EIO;
917}
918
919/* receive a response */
Wu Fengguangdeadff12009-08-01 18:45:16 +0800920static unsigned int azx_single_get_response(struct hda_bus *bus,
921 unsigned int addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700922{
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100923 struct azx *chip = bus->private_data;
Wu Fengguangdeadff12009-08-01 18:45:16 +0800924 return chip->rirb.res[addr];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700925}
926
Takashi Iwai111d3af2006-02-16 18:17:58 +0100927/*
928 * The below are the main callbacks from hda_codec.
929 *
930 * They are just the skeleton to call sub-callbacks according to the
931 * current setting of chip->single_cmd.
932 */
933
934/* send a command */
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100935static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
Takashi Iwai111d3af2006-02-16 18:17:58 +0100936{
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100937 struct azx *chip = bus->private_data;
Takashi Iwai43bbb6c2007-07-06 20:22:05 +0200938
Wu Fengguangfeb27342009-08-01 19:17:14 +0800939 chip->last_cmd[azx_command_addr(val)] = val;
Takashi Iwai111d3af2006-02-16 18:17:58 +0100940 if (chip->single_cmd)
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100941 return azx_single_send_cmd(bus, val);
Takashi Iwai111d3af2006-02-16 18:17:58 +0100942 else
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100943 return azx_corb_send_cmd(bus, val);
Takashi Iwai111d3af2006-02-16 18:17:58 +0100944}
945
946/* get a response */
Wu Fengguangdeadff12009-08-01 18:45:16 +0800947static unsigned int azx_get_response(struct hda_bus *bus,
948 unsigned int addr)
Takashi Iwai111d3af2006-02-16 18:17:58 +0100949{
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100950 struct azx *chip = bus->private_data;
Takashi Iwai111d3af2006-02-16 18:17:58 +0100951 if (chip->single_cmd)
Wu Fengguangdeadff12009-08-01 18:45:16 +0800952 return azx_single_get_response(bus, addr);
Takashi Iwai111d3af2006-02-16 18:17:58 +0100953 else
Wu Fengguangdeadff12009-08-01 18:45:16 +0800954 return azx_rirb_get_response(bus, addr);
Takashi Iwai111d3af2006-02-16 18:17:58 +0100955}
956
Takashi Iwaicb53c622007-08-10 17:21:45 +0200957#ifdef CONFIG_SND_HDA_POWER_SAVE
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100958static void azx_power_notify(struct hda_bus *bus);
Takashi Iwaicb53c622007-08-10 17:21:45 +0200959#endif
Takashi Iwai111d3af2006-02-16 18:17:58 +0100960
Linus Torvalds1da177e2005-04-16 15:20:36 -0700961/* reset codec link */
Jaroslav Kyselacd508fe2010-03-26 10:28:46 +0100962static int azx_reset(struct azx *chip, int full_reset)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700963{
964 int count;
965
Jaroslav Kyselacd508fe2010-03-26 10:28:46 +0100966 if (!full_reset)
967 goto __skip;
968
Danny Tholene8a7f132007-09-11 21:41:56 +0200969 /* clear STATESTS */
970 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
971
Linus Torvalds1da177e2005-04-16 15:20:36 -0700972 /* reset controller */
973 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
974
975 count = 50;
976 while (azx_readb(chip, GCTL) && --count)
977 msleep(1);
978
979 /* delay for >= 100us for codec PLL to settle per spec
980 * Rev 0.9 section 5.5.1
981 */
982 msleep(1);
983
984 /* Bring controller out of reset */
985 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
986
987 count = 50;
Pavel Machek927fc862006-08-31 17:03:43 +0200988 while (!azx_readb(chip, GCTL) && --count)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700989 msleep(1);
990
Pavel Machek927fc862006-08-31 17:03:43 +0200991 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700992 msleep(1);
993
Jaroslav Kyselacd508fe2010-03-26 10:28:46 +0100994 __skip:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700995 /* check to see if controller is ready */
Pavel Machek927fc862006-08-31 17:03:43 +0200996 if (!azx_readb(chip, GCTL)) {
Takashi Iwai4abc1cc2009-05-19 12:16:46 +0200997 snd_printd(SFX "azx_reset: controller not ready!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700998 return -EBUSY;
999 }
1000
Matt41e2fce2005-07-04 17:49:55 +02001001 /* Accept unsolicited responses */
Takashi Iwai1a696972009-11-07 09:49:04 +01001002 if (!chip->single_cmd)
1003 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1004 ICH6_GCTL_UNSOL);
Matt41e2fce2005-07-04 17:49:55 +02001005
Linus Torvalds1da177e2005-04-16 15:20:36 -07001006 /* detect codecs */
Pavel Machek927fc862006-08-31 17:03:43 +02001007 if (!chip->codec_mask) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001008 chip->codec_mask = azx_readw(chip, STATESTS);
Takashi Iwai4abc1cc2009-05-19 12:16:46 +02001009 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001010 }
1011
1012 return 0;
1013}
1014
1015
1016/*
1017 * Lowlevel interface
1018 */
1019
1020/* enable interrupts */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001021static void azx_int_enable(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001022{
1023 /* enable controller CIE and GIE */
1024 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1025 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1026}
1027
1028/* disable interrupts */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001029static void azx_int_disable(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001030{
1031 int i;
1032
1033 /* disable interrupts in stream descriptor */
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001034 for (i = 0; i < chip->num_streams; i++) {
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001035 struct azx_dev *azx_dev = &chip->azx_dev[i];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001036 azx_sd_writeb(azx_dev, SD_CTL,
1037 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1038 }
1039
1040 /* disable SIE for all streams */
1041 azx_writeb(chip, INTCTL, 0);
1042
1043 /* disable controller CIE and GIE */
1044 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1045 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1046}
1047
1048/* clear interrupts */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001049static void azx_int_clear(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001050{
1051 int i;
1052
1053 /* clear stream status */
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001054 for (i = 0; i < chip->num_streams; i++) {
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001055 struct azx_dev *azx_dev = &chip->azx_dev[i];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001056 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1057 }
1058
1059 /* clear STATESTS */
1060 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1061
1062 /* clear rirb status */
1063 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1064
1065 /* clear int status */
1066 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1067}
1068
1069/* start a stream */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001070static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001071{
Joseph Chan0e153472008-08-26 14:38:03 +02001072 /*
1073 * Before stream start, initialize parameter
1074 */
1075 azx_dev->insufficient = 1;
1076
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077 /* enable SIE */
Wei Niccc5df02010-01-26 15:59:33 +08001078 azx_writel(chip, INTCTL,
1079 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001080 /* set DMA start and interrupt mask */
1081 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1082 SD_CTL_DMA_START | SD_INT_MASK);
1083}
1084
Takashi Iwai1dddab42009-03-18 15:15:37 +01001085/* stop DMA */
1086static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001087{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001088 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1089 ~(SD_CTL_DMA_START | SD_INT_MASK));
1090 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
Takashi Iwai1dddab42009-03-18 15:15:37 +01001091}
1092
1093/* stop a stream */
1094static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1095{
1096 azx_stream_clear(chip, azx_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001097 /* disable SIE */
Wei Niccc5df02010-01-26 15:59:33 +08001098 azx_writel(chip, INTCTL,
1099 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001100}
1101
1102
1103/*
Takashi Iwaicb53c622007-08-10 17:21:45 +02001104 * reset and start the controller registers
Linus Torvalds1da177e2005-04-16 15:20:36 -07001105 */
Jaroslav Kyselacd508fe2010-03-26 10:28:46 +01001106static void azx_init_chip(struct azx *chip, int full_reset)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001107{
Takashi Iwaicb53c622007-08-10 17:21:45 +02001108 if (chip->initialized)
1109 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001110
1111 /* reset controller */
Jaroslav Kyselacd508fe2010-03-26 10:28:46 +01001112 azx_reset(chip, full_reset);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113
1114 /* initialize interrupts */
1115 azx_int_clear(chip);
1116 azx_int_enable(chip);
1117
1118 /* initialize the codec command I/O */
Takashi Iwai1a696972009-11-07 09:49:04 +01001119 if (!chip->single_cmd)
1120 azx_init_cmd_io(chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001121
Takashi Iwai0be3b5d2005-09-05 17:11:40 +02001122 /* program the position buffer */
1123 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
Takashi Iwai766979e2008-06-13 20:53:56 +02001124 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
Frederick Lif5d40b32005-05-12 14:55:20 +02001125
Takashi Iwaicb53c622007-08-10 17:21:45 +02001126 chip->initialized = 1;
1127}
1128
1129/*
1130 * initialize the PCI registers
1131 */
1132/* update bits in a PCI register byte */
1133static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1134 unsigned char mask, unsigned char val)
1135{
1136 unsigned char data;
1137
1138 pci_read_config_byte(pci, reg, &data);
1139 data &= ~mask;
1140 data |= (val & mask);
1141 pci_write_config_byte(pci, reg, data);
1142}
1143
1144static void azx_init_pci(struct azx *chip)
1145{
Takashi Iwai27fe48d92011-09-28 17:16:09 +02001146 /* force to non-snoop mode for a new VIA controller when BIOS is set */
1147 if (chip->snoop && chip->driver_type == AZX_DRIVER_VIA) {
1148 u8 snoop;
1149 pci_read_config_byte(chip->pci, 0x42, &snoop);
1150 if (!(snoop & 0x80) && chip->pci->revision == 0x30) {
1151 chip->snoop = 0;
1152 snd_printdd(SFX "Force to non-snoop mode\n");
1153 }
1154 }
Takashi Iwai90a5ad52008-02-22 18:36:22 +01001155
Takashi Iwaicb53c622007-08-10 17:21:45 +02001156 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1157 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1158 * Ensuring these bits are 0 clears playback static on some HD Audio
Adam Lackorzynskia09e89f2011-03-10 17:41:56 +01001159 * codecs.
1160 * The PCI register TCSEL is defined in the Intel manuals.
Takashi Iwaicb53c622007-08-10 17:21:45 +02001161 */
Linus Torvalds46f2cc82011-05-27 19:45:28 -07001162 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
Takashi Iwai9477c582011-05-25 09:11:37 +02001163 snd_printdd(SFX "Clearing TCSEL\n");
Adam Lackorzynskia09e89f2011-03-10 17:41:56 +01001164 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
Takashi Iwai9477c582011-05-25 09:11:37 +02001165 }
Takashi Iwaicb53c622007-08-10 17:21:45 +02001166
Takashi Iwai9477c582011-05-25 09:11:37 +02001167 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1168 * we need to enable snoop.
1169 */
1170 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
Takashi Iwai27fe48d92011-09-28 17:16:09 +02001171 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
Takashi Iwaicb53c622007-08-10 17:21:45 +02001172 update_pci_byte(chip->pci,
Takashi Iwai27fe48d92011-09-28 17:16:09 +02001173 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1174 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
Takashi Iwai9477c582011-05-25 09:11:37 +02001175 }
1176
1177 /* For NVIDIA HDA, enable snoop */
1178 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
Takashi Iwai27fe48d92011-09-28 17:16:09 +02001179 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
Takashi Iwaicb53c622007-08-10 17:21:45 +02001180 update_pci_byte(chip->pci,
1181 NVIDIA_HDA_TRANSREG_ADDR,
1182 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
Peer Chen320dcc32008-08-20 16:43:24 -07001183 update_pci_byte(chip->pci,
1184 NVIDIA_HDA_ISTRM_COH,
1185 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1186 update_pci_byte(chip->pci,
1187 NVIDIA_HDA_OSTRM_COH,
1188 0x01, NVIDIA_HDA_ENABLE_COHBIT);
Takashi Iwai9477c582011-05-25 09:11:37 +02001189 }
1190
1191 /* Enable SCH/PCH snoop if needed */
1192 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
Takashi Iwai27fe48d92011-09-28 17:16:09 +02001193 unsigned short snoop;
Takashi Iwai90a5ad52008-02-22 18:36:22 +01001194 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
Takashi Iwai27fe48d92011-09-28 17:16:09 +02001195 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1196 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1197 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1198 if (!azx_snoop(chip))
1199 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1200 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
Takashi Iwai90a5ad52008-02-22 18:36:22 +01001201 pci_read_config_word(chip->pci,
1202 INTEL_SCH_HDA_DEVC, &snoop);
Takashi Iwai90a5ad52008-02-22 18:36:22 +01001203 }
Takashi Iwai27fe48d92011-09-28 17:16:09 +02001204 snd_printdd(SFX "SCH snoop: %s\n",
1205 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1206 ? "Disabled" : "Enabled");
Vinod Gda3fca22005-09-13 18:49:12 +02001207 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001208}
1209
1210
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001211static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1212
Linus Torvalds1da177e2005-04-16 15:20:36 -07001213/*
1214 * interrupt handler
1215 */
David Howells7d12e782006-10-05 14:55:46 +01001216static irqreturn_t azx_interrupt(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001217{
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001218 struct azx *chip = dev_id;
1219 struct azx_dev *azx_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001220 u32 status;
Clemens Ladisch9ef04062010-05-25 09:03:40 +02001221 u8 sd_status;
Jaroslav Kyselafa00e042009-04-10 12:20:45 +02001222 int i, ok;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001223
1224 spin_lock(&chip->reg_lock);
1225
1226 status = azx_readl(chip, INTSTS);
1227 if (status == 0) {
1228 spin_unlock(&chip->reg_lock);
1229 return IRQ_NONE;
1230 }
1231
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001232 for (i = 0; i < chip->num_streams; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001233 azx_dev = &chip->azx_dev[i];
1234 if (status & azx_dev->sd_int_sta_mask) {
Clemens Ladisch9ef04062010-05-25 09:03:40 +02001235 sd_status = azx_sd_readb(azx_dev, SD_STS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001236 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
Clemens Ladisch9ef04062010-05-25 09:03:40 +02001237 if (!azx_dev->substream || !azx_dev->running ||
1238 !(sd_status & SD_INT_COMPLETE))
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001239 continue;
1240 /* check whether this IRQ is really acceptable */
Jaroslav Kyselafa00e042009-04-10 12:20:45 +02001241 ok = azx_position_ok(chip, azx_dev);
1242 if (ok == 1) {
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001243 azx_dev->irq_pending = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001244 spin_unlock(&chip->reg_lock);
1245 snd_pcm_period_elapsed(azx_dev->substream);
1246 spin_lock(&chip->reg_lock);
Jaroslav Kyselafa00e042009-04-10 12:20:45 +02001247 } else if (ok == 0 && chip->bus && chip->bus->workq) {
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001248 /* bogus IRQ, process it later */
1249 azx_dev->irq_pending = 1;
Takashi Iwai6acaed32009-01-12 10:09:24 +01001250 queue_work(chip->bus->workq,
1251 &chip->irq_pending_work);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001252 }
1253 }
1254 }
1255
1256 /* clear rirb int */
1257 status = azx_readb(chip, RIRBSTS);
1258 if (status & RIRB_INT_MASK) {
Takashi Iwai14d34f12010-10-21 09:03:25 +02001259 if (status & RIRB_INT_RESPONSE) {
Takashi Iwai9477c582011-05-25 09:11:37 +02001260 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
Takashi Iwai14d34f12010-10-21 09:03:25 +02001261 udelay(80);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001262 azx_update_rirb(chip);
Takashi Iwai14d34f12010-10-21 09:03:25 +02001263 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001264 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1265 }
1266
1267#if 0
1268 /* clear state status int */
1269 if (azx_readb(chip, STATESTS) & 0x04)
1270 azx_writeb(chip, STATESTS, 0x04);
1271#endif
1272 spin_unlock(&chip->reg_lock);
1273
1274 return IRQ_HANDLED;
1275}
1276
1277
1278/*
Takashi Iwai675f25d2008-06-10 17:53:20 +02001279 * set up a BDL entry
1280 */
1281static int setup_bdle(struct snd_pcm_substream *substream,
1282 struct azx_dev *azx_dev, u32 **bdlp,
1283 int ofs, int size, int with_ioc)
1284{
Takashi Iwai675f25d2008-06-10 17:53:20 +02001285 u32 *bdl = *bdlp;
1286
1287 while (size > 0) {
1288 dma_addr_t addr;
1289 int chunk;
1290
1291 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1292 return -EINVAL;
1293
Takashi Iwai77a23f22008-08-21 13:00:13 +02001294 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
Takashi Iwai675f25d2008-06-10 17:53:20 +02001295 /* program the address field of the BDL entry */
1296 bdl[0] = cpu_to_le32((u32)addr);
Takashi Iwai766979e2008-06-13 20:53:56 +02001297 bdl[1] = cpu_to_le32(upper_32_bits(addr));
Takashi Iwai675f25d2008-06-10 17:53:20 +02001298 /* program the size field of the BDL entry */
Takashi Iwaifc4abee2008-07-30 15:13:34 +02001299 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
Takashi Iwai675f25d2008-06-10 17:53:20 +02001300 bdl[2] = cpu_to_le32(chunk);
1301 /* program the IOC to enable interrupt
1302 * only when the whole fragment is processed
1303 */
1304 size -= chunk;
1305 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1306 bdl += 4;
1307 azx_dev->frags++;
1308 ofs += chunk;
1309 }
1310 *bdlp = bdl;
1311 return ofs;
1312}
1313
1314/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001315 * set up BDL entries
1316 */
Takashi Iwai555e2192008-06-10 17:53:34 +02001317static int azx_setup_periods(struct azx *chip,
1318 struct snd_pcm_substream *substream,
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001319 struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001320{
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001321 u32 *bdl;
1322 int i, ofs, periods, period_bytes;
Takashi Iwai555e2192008-06-10 17:53:34 +02001323 int pos_adj;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001324
1325 /* reset BDL address */
1326 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1327 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1328
Takashi Iwai97b71c92009-03-18 15:09:13 +01001329 period_bytes = azx_dev->period_bytes;
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001330 periods = azx_dev->bufsize / period_bytes;
1331
Linus Torvalds1da177e2005-04-16 15:20:36 -07001332 /* program the initial BDL entries */
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001333 bdl = (u32 *)azx_dev->bdl.area;
1334 ofs = 0;
1335 azx_dev->frags = 0;
Takashi Iwai555e2192008-06-10 17:53:34 +02001336 pos_adj = bdl_pos_adj[chip->dev_index];
1337 if (pos_adj > 0) {
Takashi Iwai675f25d2008-06-10 17:53:20 +02001338 struct snd_pcm_runtime *runtime = substream->runtime;
Takashi Iwaie785d3d2008-07-15 16:28:43 +02001339 int pos_align = pos_adj;
Takashi Iwai555e2192008-06-10 17:53:34 +02001340 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
Takashi Iwai675f25d2008-06-10 17:53:20 +02001341 if (!pos_adj)
Takashi Iwaie785d3d2008-07-15 16:28:43 +02001342 pos_adj = pos_align;
1343 else
1344 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1345 pos_align;
Takashi Iwai675f25d2008-06-10 17:53:20 +02001346 pos_adj = frames_to_bytes(runtime, pos_adj);
1347 if (pos_adj >= period_bytes) {
Takashi Iwai4abc1cc2009-05-19 12:16:46 +02001348 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
Takashi Iwai555e2192008-06-10 17:53:34 +02001349 bdl_pos_adj[chip->dev_index]);
Takashi Iwai675f25d2008-06-10 17:53:20 +02001350 pos_adj = 0;
1351 } else {
1352 ofs = setup_bdle(substream, azx_dev,
Clemens Ladisch7bb8fb72010-11-15 10:49:47 +01001353 &bdl, ofs, pos_adj,
1354 !substream->runtime->no_period_wakeup);
Takashi Iwai675f25d2008-06-10 17:53:20 +02001355 if (ofs < 0)
1356 goto error;
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001357 }
Takashi Iwai555e2192008-06-10 17:53:34 +02001358 } else
1359 pos_adj = 0;
Takashi Iwai675f25d2008-06-10 17:53:20 +02001360 for (i = 0; i < periods; i++) {
1361 if (i == periods - 1 && pos_adj)
1362 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1363 period_bytes - pos_adj, 0);
1364 else
1365 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
Clemens Ladisch7bb8fb72010-11-15 10:49:47 +01001366 period_bytes,
1367 !substream->runtime->no_period_wakeup);
Takashi Iwai675f25d2008-06-10 17:53:20 +02001368 if (ofs < 0)
1369 goto error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001370 }
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001371 return 0;
Takashi Iwai675f25d2008-06-10 17:53:20 +02001372
1373 error:
Takashi Iwai4abc1cc2009-05-19 12:16:46 +02001374 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
Takashi Iwai675f25d2008-06-10 17:53:20 +02001375 azx_dev->bufsize, period_bytes);
Takashi Iwai675f25d2008-06-10 17:53:20 +02001376 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001377}
1378
Takashi Iwai1dddab42009-03-18 15:15:37 +01001379/* reset stream */
1380static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001381{
1382 unsigned char val;
1383 int timeout;
1384
Takashi Iwai1dddab42009-03-18 15:15:37 +01001385 azx_stream_clear(chip, azx_dev);
1386
Takashi Iwaid01ce992007-07-27 16:52:19 +02001387 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1388 SD_CTL_STREAM_RESET);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001389 udelay(3);
1390 timeout = 300;
1391 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1392 --timeout)
1393 ;
1394 val &= ~SD_CTL_STREAM_RESET;
1395 azx_sd_writeb(azx_dev, SD_CTL, val);
1396 udelay(3);
1397
1398 timeout = 300;
1399 /* waiting for hardware to report that the stream is out of reset */
1400 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1401 --timeout)
1402 ;
Jaroslav Kyselafa00e042009-04-10 12:20:45 +02001403
1404 /* reset first position - may not be synced with hw at this time */
1405 *azx_dev->posbuf = 0;
Takashi Iwai1dddab42009-03-18 15:15:37 +01001406}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001407
Takashi Iwai1dddab42009-03-18 15:15:37 +01001408/*
1409 * set up the SD for streaming
1410 */
1411static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1412{
Takashi Iwai27fe48d92011-09-28 17:16:09 +02001413 unsigned int val;
Takashi Iwai1dddab42009-03-18 15:15:37 +01001414 /* make sure the run bit is zero for SD */
1415 azx_stream_clear(chip, azx_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001416 /* program the stream_tag */
Takashi Iwai27fe48d92011-09-28 17:16:09 +02001417 val = azx_sd_readl(azx_dev, SD_CTL);
1418 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1419 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1420 if (!azx_snoop(chip))
1421 val |= SD_CTL_TRAFFIC_PRIO;
1422 azx_sd_writel(azx_dev, SD_CTL, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001423
1424 /* program the length of samples in cyclic buffer */
1425 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1426
1427 /* program the stream format */
1428 /* this value needs to be the same as the one programmed */
1429 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1430
1431 /* program the stream LVI (last valid index) of the BDL */
1432 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1433
1434 /* program the BDL address */
1435 /* lower BDL address */
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001436 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001437 /* upper BDL address */
Takashi Iwai766979e2008-06-13 20:53:56 +02001438 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001439
Takashi Iwai0be3b5d2005-09-05 17:11:40 +02001440 /* enable the position buffer */
David Henningsson4cb36312010-09-30 10:12:50 +02001441 if (chip->position_fix[0] != POS_FIX_LPIB ||
1442 chip->position_fix[1] != POS_FIX_LPIB) {
Takashi Iwaiee9d6b92008-03-14 15:52:20 +01001443 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1444 azx_writel(chip, DPLBASE,
1445 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1446 }
Takashi Iwaic74db862005-05-12 14:26:27 +02001447
Linus Torvalds1da177e2005-04-16 15:20:36 -07001448 /* set the interrupt enable bits in the descriptor control register */
Takashi Iwaid01ce992007-07-27 16:52:19 +02001449 azx_sd_writel(azx_dev, SD_CTL,
1450 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001451
1452 return 0;
1453}
1454
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001455/*
1456 * Probe the given codec address
1457 */
1458static int probe_codec(struct azx *chip, int addr)
1459{
1460 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1461 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1462 unsigned int res;
1463
Wu Fengguanga678cde2009-08-01 18:46:46 +08001464 mutex_lock(&chip->bus->cmd_mutex);
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001465 chip->probing = 1;
1466 azx_send_cmd(chip->bus, cmd);
Wu Fengguangdeadff12009-08-01 18:45:16 +08001467 res = azx_get_response(chip->bus, addr);
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001468 chip->probing = 0;
Wu Fengguanga678cde2009-08-01 18:46:46 +08001469 mutex_unlock(&chip->bus->cmd_mutex);
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001470 if (res == -1)
1471 return -EIO;
Takashi Iwai4abc1cc2009-05-19 12:16:46 +02001472 snd_printdd(SFX "codec #%d probed OK\n", addr);
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001473 return 0;
1474}
1475
Takashi Iwai33fa35e2008-11-06 16:50:40 +01001476static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1477 struct hda_pcm *cpcm);
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001478static void azx_stop_chip(struct azx *chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001479
Takashi Iwai8dd78332009-06-02 01:16:07 +02001480static void azx_bus_reset(struct hda_bus *bus)
1481{
1482 struct azx *chip = bus->private_data;
Takashi Iwai8dd78332009-06-02 01:16:07 +02001483
1484 bus->in_reset = 1;
1485 azx_stop_chip(chip);
Jaroslav Kyselacd508fe2010-03-26 10:28:46 +01001486 azx_init_chip(chip, 1);
Alexander Beregalov65f75982009-06-04 13:46:16 +04001487#ifdef CONFIG_PM
Takashi Iwai8dd78332009-06-02 01:16:07 +02001488 if (chip->initialized) {
Alexander Beregalov65f75982009-06-04 13:46:16 +04001489 int i;
1490
Takashi Iwaic8936222010-01-28 17:08:53 +01001491 for (i = 0; i < HDA_MAX_PCMS; i++)
Takashi Iwai8dd78332009-06-02 01:16:07 +02001492 snd_pcm_suspend_all(chip->pcm[i]);
1493 snd_hda_suspend(chip->bus);
1494 snd_hda_resume(chip->bus);
1495 }
Alexander Beregalov65f75982009-06-04 13:46:16 +04001496#endif
Takashi Iwai8dd78332009-06-02 01:16:07 +02001497 bus->in_reset = 0;
1498}
1499
Linus Torvalds1da177e2005-04-16 15:20:36 -07001500/*
1501 * Codec initialization
1502 */
1503
Takashi Iwai2f5983f2008-09-03 16:00:44 +02001504/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1505static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
Wei Ni7445dfc2010-03-03 15:05:53 +08001506 [AZX_DRIVER_NVIDIA] = 8,
Kailang Yangf2690022008-05-27 11:44:55 +02001507 [AZX_DRIVER_TERA] = 1,
Takashi Iwaia9995a32007-03-12 21:30:46 +01001508};
1509
Takashi Iwaia1e21c92009-06-17 09:33:52 +02001510static int __devinit azx_codec_create(struct azx *chip, const char *model)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001511{
1512 struct hda_bus_template bus_temp;
Takashi Iwai34c25352008-10-28 11:38:58 +01001513 int c, codecs, err;
1514 int max_slots;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001515
1516 memset(&bus_temp, 0, sizeof(bus_temp));
1517 bus_temp.private_data = chip;
1518 bus_temp.modelname = model;
1519 bus_temp.pci = chip->pci;
Takashi Iwai111d3af2006-02-16 18:17:58 +01001520 bus_temp.ops.command = azx_send_cmd;
1521 bus_temp.ops.get_response = azx_get_response;
Takashi Iwai176d5332008-07-30 15:01:44 +02001522 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
Takashi Iwai8dd78332009-06-02 01:16:07 +02001523 bus_temp.ops.bus_reset = azx_bus_reset;
Takashi Iwaicb53c622007-08-10 17:21:45 +02001524#ifdef CONFIG_SND_HDA_POWER_SAVE
Takashi Iwai11cd41b2008-11-28 07:22:18 +01001525 bus_temp.power_save = &power_save;
Takashi Iwaicb53c622007-08-10 17:21:45 +02001526 bus_temp.ops.pm_notify = azx_power_notify;
1527#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001528
Takashi Iwaid01ce992007-07-27 16:52:19 +02001529 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1530 if (err < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001531 return err;
1532
Takashi Iwai9477c582011-05-25 09:11:37 +02001533 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1534 snd_printd(SFX "Enable delay in RIRB handling\n");
Wei Nidc9c8e22008-09-26 13:55:56 +08001535 chip->bus->needs_damn_long_delay = 1;
Takashi Iwai9477c582011-05-25 09:11:37 +02001536 }
Wei Nidc9c8e22008-09-26 13:55:56 +08001537
Takashi Iwai34c25352008-10-28 11:38:58 +01001538 codecs = 0;
Takashi Iwai2f5983f2008-09-03 16:00:44 +02001539 max_slots = azx_max_codecs[chip->driver_type];
1540 if (!max_slots)
Wei Ni7445dfc2010-03-03 15:05:53 +08001541 max_slots = AZX_DEFAULT_CODECS;
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001542
1543 /* First try to probe all given codec slots */
1544 for (c = 0; c < max_slots; c++) {
Takashi Iwaif1eaaee2009-02-13 08:16:55 +01001545 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001546 if (probe_codec(chip, c) < 0) {
1547 /* Some BIOSen give you wrong codec addresses
1548 * that don't exist
1549 */
Takashi Iwai4abc1cc2009-05-19 12:16:46 +02001550 snd_printk(KERN_WARNING SFX
1551 "Codec #%d probe error; "
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001552 "disabling it...\n", c);
1553 chip->codec_mask &= ~(1 << c);
1554 /* More badly, accessing to a non-existing
1555 * codec often screws up the controller chip,
Paul Menzel24481582010-02-08 20:37:26 +01001556 * and disturbs the further communications.
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001557 * Thus if an error occurs during probing,
1558 * better to reset the controller chip to
1559 * get back to the sanity state.
1560 */
1561 azx_stop_chip(chip);
Jaroslav Kyselacd508fe2010-03-26 10:28:46 +01001562 azx_init_chip(chip, 1);
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001563 }
1564 }
1565 }
1566
Takashi Iwaid507cd62011-04-26 15:25:02 +02001567 /* AMD chipsets often cause the communication stalls upon certain
1568 * sequence like the pin-detection. It seems that forcing the synced
1569 * access works around the stall. Grrr...
1570 */
Takashi Iwai9477c582011-05-25 09:11:37 +02001571 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1572 snd_printd(SFX "Enable sync_write for stable communication\n");
Takashi Iwaid507cd62011-04-26 15:25:02 +02001573 chip->bus->sync_write = 1;
1574 chip->bus->allow_bus_reset = 1;
1575 }
1576
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001577 /* Then create codec instances */
Takashi Iwai34c25352008-10-28 11:38:58 +01001578 for (c = 0; c < max_slots; c++) {
Takashi Iwaif1eaaee2009-02-13 08:16:55 +01001579 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
Takashi Iwaibccad142007-04-24 12:23:53 +02001580 struct hda_codec *codec;
Takashi Iwaia1e21c92009-06-17 09:33:52 +02001581 err = snd_hda_codec_new(chip->bus, c, &codec);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001582 if (err < 0)
1583 continue;
Jaroslav Kysela2dca0bb2009-11-13 18:41:52 +01001584 codec->beep_mode = chip->beep_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001585 codecs++;
Takashi Iwai19a982b2007-03-21 15:14:35 +01001586 }
1587 }
1588 if (!codecs) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001589 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1590 return -ENXIO;
1591 }
Takashi Iwaia1e21c92009-06-17 09:33:52 +02001592 return 0;
1593}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001594
Takashi Iwaia1e21c92009-06-17 09:33:52 +02001595/* configure each codec instance */
1596static int __devinit azx_codec_configure(struct azx *chip)
1597{
1598 struct hda_codec *codec;
1599 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1600 snd_hda_codec_configure(codec);
1601 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001602 return 0;
1603}
1604
1605
1606/*
1607 * PCM support
1608 */
1609
1610/* assign a stream for the PCM */
Wu Fengguangef18bed2009-12-25 13:14:27 +08001611static inline struct azx_dev *
1612azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001613{
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001614 int dev, i, nums;
Wu Fengguangef18bed2009-12-25 13:14:27 +08001615 struct azx_dev *res = NULL;
Takashi Iwaid5cf9912011-10-06 10:07:58 +02001616 /* make a non-zero unique key for the substream */
1617 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1618 (substream->stream + 1);
Wu Fengguangef18bed2009-12-25 13:14:27 +08001619
1620 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001621 dev = chip->playback_index_offset;
1622 nums = chip->playback_streams;
1623 } else {
1624 dev = chip->capture_index_offset;
1625 nums = chip->capture_streams;
1626 }
1627 for (i = 0; i < nums; i++, dev++)
Takashi Iwaid01ce992007-07-27 16:52:19 +02001628 if (!chip->azx_dev[dev].opened) {
Wu Fengguangef18bed2009-12-25 13:14:27 +08001629 res = &chip->azx_dev[dev];
Takashi Iwaid5cf9912011-10-06 10:07:58 +02001630 if (res->assigned_key == key)
Wu Fengguangef18bed2009-12-25 13:14:27 +08001631 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001632 }
Wu Fengguangef18bed2009-12-25 13:14:27 +08001633 if (res) {
1634 res->opened = 1;
Takashi Iwaid5cf9912011-10-06 10:07:58 +02001635 res->assigned_key = key;
Wu Fengguangef18bed2009-12-25 13:14:27 +08001636 }
1637 return res;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001638}
1639
1640/* release the assigned stream */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001641static inline void azx_release_device(struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001642{
1643 azx_dev->opened = 0;
1644}
1645
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001646static struct snd_pcm_hardware azx_pcm_hw = {
Takashi Iwaid01ce992007-07-27 16:52:19 +02001647 .info = (SNDRV_PCM_INFO_MMAP |
1648 SNDRV_PCM_INFO_INTERLEAVED |
Linus Torvalds1da177e2005-04-16 15:20:36 -07001649 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1650 SNDRV_PCM_INFO_MMAP_VALID |
Pavel Machek927fc862006-08-31 17:03:43 +02001651 /* No full-resume yet implemented */
1652 /* SNDRV_PCM_INFO_RESUME |*/
Takashi Iwai850f0e52008-03-18 17:11:05 +01001653 SNDRV_PCM_INFO_PAUSE |
Clemens Ladisch7bb8fb72010-11-15 10:49:47 +01001654 SNDRV_PCM_INFO_SYNC_START |
1655 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
Linus Torvalds1da177e2005-04-16 15:20:36 -07001656 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1657 .rates = SNDRV_PCM_RATE_48000,
1658 .rate_min = 48000,
1659 .rate_max = 48000,
1660 .channels_min = 2,
1661 .channels_max = 2,
1662 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1663 .period_bytes_min = 128,
1664 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1665 .periods_min = 2,
1666 .periods_max = AZX_MAX_FRAG,
1667 .fifo_size = 0,
1668};
1669
1670struct azx_pcm {
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001671 struct azx *chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001672 struct hda_codec *codec;
1673 struct hda_pcm_stream *hinfo[2];
1674};
1675
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001676static int azx_pcm_open(struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001677{
1678 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1679 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001680 struct azx *chip = apcm->chip;
1681 struct azx_dev *azx_dev;
1682 struct snd_pcm_runtime *runtime = substream->runtime;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001683 unsigned long flags;
1684 int err;
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -05001685 int buff_step;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001686
Ingo Molnar62932df2006-01-16 16:34:20 +01001687 mutex_lock(&chip->open_mutex);
Wu Fengguangef18bed2009-12-25 13:14:27 +08001688 azx_dev = azx_assign_device(chip, substream);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001689 if (azx_dev == NULL) {
Ingo Molnar62932df2006-01-16 16:34:20 +01001690 mutex_unlock(&chip->open_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001691 return -EBUSY;
1692 }
1693 runtime->hw = azx_pcm_hw;
1694 runtime->hw.channels_min = hinfo->channels_min;
1695 runtime->hw.channels_max = hinfo->channels_max;
1696 runtime->hw.formats = hinfo->formats;
1697 runtime->hw.rates = hinfo->rates;
1698 snd_pcm_limit_hw_rates(runtime);
1699 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -05001700 if (align_buffer_size)
1701 /* constrain buffer sizes to be multiple of 128
1702 bytes. This is more efficient in terms of memory
1703 access but isn't required by the HDA spec and
1704 prevents users from specifying exact period/buffer
1705 sizes. For example for 44.1kHz, a period size set
1706 to 20ms will be rounded to 19.59ms. */
1707 buff_step = 128;
1708 else
1709 /* Don't enforce steps on buffer sizes, still need to
1710 be multiple of 4 bytes (HDA spec). Tested on Intel
1711 HDA controllers, may not work on all devices where
1712 option needs to be disabled */
1713 buff_step = 4;
1714
Joachim Deguara5f1545b2007-03-16 15:01:36 +01001715 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -05001716 buff_step);
Joachim Deguara5f1545b2007-03-16 15:01:36 +01001717 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -05001718 buff_step);
Takashi Iwaicb53c622007-08-10 17:21:45 +02001719 snd_hda_power_up(apcm->codec);
Takashi Iwaid01ce992007-07-27 16:52:19 +02001720 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1721 if (err < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001722 azx_release_device(azx_dev);
Takashi Iwaicb53c622007-08-10 17:21:45 +02001723 snd_hda_power_down(apcm->codec);
Ingo Molnar62932df2006-01-16 16:34:20 +01001724 mutex_unlock(&chip->open_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001725 return err;
1726 }
Takashi Iwai70d321e2009-07-03 23:06:45 +02001727 snd_pcm_limit_hw_rates(runtime);
Takashi Iwaiaba66532009-07-05 11:44:46 +02001728 /* sanity check */
1729 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1730 snd_BUG_ON(!runtime->hw.channels_max) ||
1731 snd_BUG_ON(!runtime->hw.formats) ||
1732 snd_BUG_ON(!runtime->hw.rates)) {
1733 azx_release_device(azx_dev);
1734 hinfo->ops.close(hinfo, apcm->codec, substream);
1735 snd_hda_power_down(apcm->codec);
1736 mutex_unlock(&chip->open_mutex);
1737 return -EINVAL;
1738 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001739 spin_lock_irqsave(&chip->reg_lock, flags);
1740 azx_dev->substream = substream;
1741 azx_dev->running = 0;
1742 spin_unlock_irqrestore(&chip->reg_lock, flags);
1743
1744 runtime->private_data = azx_dev;
Takashi Iwai850f0e52008-03-18 17:11:05 +01001745 snd_pcm_set_sync(substream);
Ingo Molnar62932df2006-01-16 16:34:20 +01001746 mutex_unlock(&chip->open_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001747 return 0;
1748}
1749
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001750static int azx_pcm_close(struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001751{
1752 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1753 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001754 struct azx *chip = apcm->chip;
1755 struct azx_dev *azx_dev = get_azx_dev(substream);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001756 unsigned long flags;
1757
Ingo Molnar62932df2006-01-16 16:34:20 +01001758 mutex_lock(&chip->open_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001759 spin_lock_irqsave(&chip->reg_lock, flags);
1760 azx_dev->substream = NULL;
1761 azx_dev->running = 0;
1762 spin_unlock_irqrestore(&chip->reg_lock, flags);
1763 azx_release_device(azx_dev);
1764 hinfo->ops.close(hinfo, apcm->codec, substream);
Takashi Iwaicb53c622007-08-10 17:21:45 +02001765 snd_hda_power_down(apcm->codec);
Ingo Molnar62932df2006-01-16 16:34:20 +01001766 mutex_unlock(&chip->open_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001767 return 0;
1768}
1769
Takashi Iwaid01ce992007-07-27 16:52:19 +02001770static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1771 struct snd_pcm_hw_params *hw_params)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001772{
Takashi Iwai27fe48d92011-09-28 17:16:09 +02001773 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1774 struct azx *chip = apcm->chip;
1775 struct snd_pcm_runtime *runtime = substream->runtime;
Takashi Iwai97b71c92009-03-18 15:09:13 +01001776 struct azx_dev *azx_dev = get_azx_dev(substream);
Takashi Iwai27fe48d92011-09-28 17:16:09 +02001777 int ret;
Takashi Iwai97b71c92009-03-18 15:09:13 +01001778
Takashi Iwai27fe48d92011-09-28 17:16:09 +02001779 mark_runtime_wc(chip, azx_dev, runtime, false);
Takashi Iwai97b71c92009-03-18 15:09:13 +01001780 azx_dev->bufsize = 0;
1781 azx_dev->period_bytes = 0;
1782 azx_dev->format_val = 0;
Takashi Iwai27fe48d92011-09-28 17:16:09 +02001783 ret = snd_pcm_lib_malloc_pages(substream,
Takashi Iwaid01ce992007-07-27 16:52:19 +02001784 params_buffer_bytes(hw_params));
Takashi Iwai27fe48d92011-09-28 17:16:09 +02001785 if (ret < 0)
1786 return ret;
1787 mark_runtime_wc(chip, azx_dev, runtime, true);
1788 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001789}
1790
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001791static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001792{
1793 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001794 struct azx_dev *azx_dev = get_azx_dev(substream);
Takashi Iwai27fe48d92011-09-28 17:16:09 +02001795 struct azx *chip = apcm->chip;
1796 struct snd_pcm_runtime *runtime = substream->runtime;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001797 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1798
1799 /* reset BDL address */
1800 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1801 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1802 azx_sd_writel(azx_dev, SD_CTL, 0);
Takashi Iwai97b71c92009-03-18 15:09:13 +01001803 azx_dev->bufsize = 0;
1804 azx_dev->period_bytes = 0;
1805 azx_dev->format_val = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001806
Takashi Iwaieb541332010-08-06 13:48:11 +02001807 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001808
Takashi Iwai27fe48d92011-09-28 17:16:09 +02001809 mark_runtime_wc(chip, azx_dev, runtime, false);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001810 return snd_pcm_lib_free_pages(substream);
1811}
1812
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001813static int azx_pcm_prepare(struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001814{
1815 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001816 struct azx *chip = apcm->chip;
1817 struct azx_dev *azx_dev = get_azx_dev(substream);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001818 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001819 struct snd_pcm_runtime *runtime = substream->runtime;
Takashi Iwai62b7e5e2010-10-22 17:15:47 +02001820 unsigned int bufsize, period_bytes, format_val, stream_tag;
Takashi Iwai97b71c92009-03-18 15:09:13 +01001821 int err;
Stephen Warren7c9359762011-06-01 11:14:17 -06001822 struct hda_spdif_out *spdif =
1823 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1824 unsigned short ctls = spdif ? spdif->ctls : 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001825
Jaroslav Kyselafa00e042009-04-10 12:20:45 +02001826 azx_stream_reset(chip, azx_dev);
Takashi Iwai97b71c92009-03-18 15:09:13 +01001827 format_val = snd_hda_calc_stream_format(runtime->rate,
1828 runtime->channels,
1829 runtime->format,
Anssi Hannula32c168c2010-08-03 13:28:57 +03001830 hinfo->maxbps,
Stephen Warren7c9359762011-06-01 11:14:17 -06001831 ctls);
Takashi Iwai97b71c92009-03-18 15:09:13 +01001832 if (!format_val) {
Takashi Iwaid01ce992007-07-27 16:52:19 +02001833 snd_printk(KERN_ERR SFX
1834 "invalid format_val, rate=%d, ch=%d, format=%d\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001835 runtime->rate, runtime->channels, runtime->format);
1836 return -EINVAL;
1837 }
1838
Takashi Iwai97b71c92009-03-18 15:09:13 +01001839 bufsize = snd_pcm_lib_buffer_bytes(substream);
1840 period_bytes = snd_pcm_lib_period_bytes(substream);
1841
Takashi Iwai4abc1cc2009-05-19 12:16:46 +02001842 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
Takashi Iwai97b71c92009-03-18 15:09:13 +01001843 bufsize, format_val);
1844
1845 if (bufsize != azx_dev->bufsize ||
1846 period_bytes != azx_dev->period_bytes ||
1847 format_val != azx_dev->format_val) {
1848 azx_dev->bufsize = bufsize;
1849 azx_dev->period_bytes = period_bytes;
1850 azx_dev->format_val = format_val;
1851 err = azx_setup_periods(chip, substream, azx_dev);
1852 if (err < 0)
1853 return err;
1854 }
1855
Jaroslav Kyselae5463722010-05-11 10:21:46 +02001856 /* wallclk has 24Mhz clock source */
1857 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1858 runtime->rate) * 1000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001859 azx_setup_controller(chip, azx_dev);
1860 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1861 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1862 else
1863 azx_dev->fifo_size = 0;
1864
Takashi Iwai62b7e5e2010-10-22 17:15:47 +02001865 stream_tag = azx_dev->stream_tag;
1866 /* CA-IBG chips need the playback stream starting from 1 */
Takashi Iwai9477c582011-05-25 09:11:37 +02001867 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
Takashi Iwai62b7e5e2010-10-22 17:15:47 +02001868 stream_tag > chip->capture_streams)
1869 stream_tag -= chip->capture_streams;
1870 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
Takashi Iwaieb541332010-08-06 13:48:11 +02001871 azx_dev->format_val, substream);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001872}
1873
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001874static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001875{
1876 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001877 struct azx *chip = apcm->chip;
Takashi Iwai850f0e52008-03-18 17:11:05 +01001878 struct azx_dev *azx_dev;
1879 struct snd_pcm_substream *s;
Jaroslav Kyselafa00e042009-04-10 12:20:45 +02001880 int rstart = 0, start, nsync = 0, sbits = 0;
Takashi Iwai850f0e52008-03-18 17:11:05 +01001881 int nwait, timeout;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001882
Linus Torvalds1da177e2005-04-16 15:20:36 -07001883 switch (cmd) {
Jaroslav Kyselafa00e042009-04-10 12:20:45 +02001884 case SNDRV_PCM_TRIGGER_START:
1885 rstart = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001886 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1887 case SNDRV_PCM_TRIGGER_RESUME:
Takashi Iwai850f0e52008-03-18 17:11:05 +01001888 start = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001889 break;
1890 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
Jaroslav Kysela47123192005-08-15 20:53:07 +02001891 case SNDRV_PCM_TRIGGER_SUSPEND:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001892 case SNDRV_PCM_TRIGGER_STOP:
Takashi Iwai850f0e52008-03-18 17:11:05 +01001893 start = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001894 break;
1895 default:
Takashi Iwai850f0e52008-03-18 17:11:05 +01001896 return -EINVAL;
1897 }
1898
1899 snd_pcm_group_for_each_entry(s, substream) {
1900 if (s->pcm->card != substream->pcm->card)
1901 continue;
1902 azx_dev = get_azx_dev(s);
1903 sbits |= 1 << azx_dev->index;
1904 nsync++;
1905 snd_pcm_trigger_done(s, substream);
1906 }
1907
1908 spin_lock(&chip->reg_lock);
1909 if (nsync > 1) {
1910 /* first, set SYNC bits of corresponding streams */
Takashi Iwai8b0bd222011-06-10 14:56:26 +02001911 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1912 azx_writel(chip, OLD_SSYNC,
1913 azx_readl(chip, OLD_SSYNC) | sbits);
1914 else
1915 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
Takashi Iwai850f0e52008-03-18 17:11:05 +01001916 }
1917 snd_pcm_group_for_each_entry(s, substream) {
1918 if (s->pcm->card != substream->pcm->card)
1919 continue;
1920 azx_dev = get_azx_dev(s);
Jaroslav Kyselae5463722010-05-11 10:21:46 +02001921 if (start) {
1922 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1923 if (!rstart)
1924 azx_dev->start_wallclk -=
1925 azx_dev->period_wallclk;
Takashi Iwai850f0e52008-03-18 17:11:05 +01001926 azx_stream_start(chip, azx_dev);
Jaroslav Kyselae5463722010-05-11 10:21:46 +02001927 } else {
Takashi Iwai850f0e52008-03-18 17:11:05 +01001928 azx_stream_stop(chip, azx_dev);
Jaroslav Kyselae5463722010-05-11 10:21:46 +02001929 }
Takashi Iwai850f0e52008-03-18 17:11:05 +01001930 azx_dev->running = start;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001931 }
1932 spin_unlock(&chip->reg_lock);
Takashi Iwai850f0e52008-03-18 17:11:05 +01001933 if (start) {
1934 if (nsync == 1)
1935 return 0;
1936 /* wait until all FIFOs get ready */
1937 for (timeout = 5000; timeout; timeout--) {
1938 nwait = 0;
1939 snd_pcm_group_for_each_entry(s, substream) {
1940 if (s->pcm->card != substream->pcm->card)
1941 continue;
1942 azx_dev = get_azx_dev(s);
1943 if (!(azx_sd_readb(azx_dev, SD_STS) &
1944 SD_STS_FIFO_READY))
1945 nwait++;
1946 }
1947 if (!nwait)
1948 break;
1949 cpu_relax();
1950 }
1951 } else {
1952 /* wait until all RUN bits are cleared */
1953 for (timeout = 5000; timeout; timeout--) {
1954 nwait = 0;
1955 snd_pcm_group_for_each_entry(s, substream) {
1956 if (s->pcm->card != substream->pcm->card)
1957 continue;
1958 azx_dev = get_azx_dev(s);
1959 if (azx_sd_readb(azx_dev, SD_CTL) &
1960 SD_CTL_DMA_START)
1961 nwait++;
1962 }
1963 if (!nwait)
1964 break;
1965 cpu_relax();
1966 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001967 }
Takashi Iwai850f0e52008-03-18 17:11:05 +01001968 if (nsync > 1) {
1969 spin_lock(&chip->reg_lock);
1970 /* reset SYNC bits */
Takashi Iwai8b0bd222011-06-10 14:56:26 +02001971 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1972 azx_writel(chip, OLD_SSYNC,
1973 azx_readl(chip, OLD_SSYNC) & ~sbits);
1974 else
1975 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
Takashi Iwai850f0e52008-03-18 17:11:05 +01001976 spin_unlock(&chip->reg_lock);
1977 }
1978 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001979}
1980
Joseph Chan0e153472008-08-26 14:38:03 +02001981/* get the current DMA position with correction on VIA chips */
1982static unsigned int azx_via_get_position(struct azx *chip,
1983 struct azx_dev *azx_dev)
1984{
1985 unsigned int link_pos, mini_pos, bound_pos;
1986 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1987 unsigned int fifo_size;
1988
1989 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
Takashi Iwaib4a655e2011-06-07 12:26:56 +02001990 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
Joseph Chan0e153472008-08-26 14:38:03 +02001991 /* Playback, no problem using link position */
1992 return link_pos;
1993 }
1994
1995 /* Capture */
1996 /* For new chipset,
1997 * use mod to get the DMA position just like old chipset
1998 */
1999 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2000 mod_dma_pos %= azx_dev->period_bytes;
2001
2002 /* azx_dev->fifo_size can't get FIFO size of in stream.
2003 * Get from base address + offset.
2004 */
2005 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2006
2007 if (azx_dev->insufficient) {
2008 /* Link position never gather than FIFO size */
2009 if (link_pos <= fifo_size)
2010 return 0;
2011
2012 azx_dev->insufficient = 0;
2013 }
2014
2015 if (link_pos <= fifo_size)
2016 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2017 else
2018 mini_pos = link_pos - fifo_size;
2019
2020 /* Find nearest previous boudary */
2021 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2022 mod_link_pos = link_pos % azx_dev->period_bytes;
2023 if (mod_link_pos >= fifo_size)
2024 bound_pos = link_pos - mod_link_pos;
2025 else if (mod_dma_pos >= mod_mini_pos)
2026 bound_pos = mini_pos - mod_mini_pos;
2027 else {
2028 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2029 if (bound_pos >= azx_dev->bufsize)
2030 bound_pos = 0;
2031 }
2032
2033 /* Calculate real DMA position we want */
2034 return bound_pos + mod_dma_pos;
2035}
2036
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002037static unsigned int azx_get_position(struct azx *chip,
Takashi Iwai798cb7e2011-09-30 08:52:26 +02002038 struct azx_dev *azx_dev,
2039 bool with_check)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002040{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002041 unsigned int pos;
David Henningsson4cb36312010-09-30 10:12:50 +02002042 int stream = azx_dev->substream->stream;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002043
David Henningsson4cb36312010-09-30 10:12:50 +02002044 switch (chip->position_fix[stream]) {
2045 case POS_FIX_LPIB:
2046 /* read LPIB */
2047 pos = azx_sd_readl(azx_dev, SD_LPIB);
2048 break;
2049 case POS_FIX_VIACOMBO:
Joseph Chan0e153472008-08-26 14:38:03 +02002050 pos = azx_via_get_position(chip, azx_dev);
David Henningsson4cb36312010-09-30 10:12:50 +02002051 break;
2052 default:
2053 /* use the position buffer */
2054 pos = le32_to_cpu(*azx_dev->posbuf);
Takashi Iwai798cb7e2011-09-30 08:52:26 +02002055 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
Takashi Iwaia8103642011-06-07 12:23:23 +02002056 if (!pos || pos == (u32)-1) {
2057 printk(KERN_WARNING
2058 "hda-intel: Invalid position buffer, "
2059 "using LPIB read method instead.\n");
2060 chip->position_fix[stream] = POS_FIX_LPIB;
2061 pos = azx_sd_readl(azx_dev, SD_LPIB);
2062 } else
2063 chip->position_fix[stream] = POS_FIX_POSBUF;
2064 }
2065 break;
Takashi Iwaic74db862005-05-12 14:26:27 +02002066 }
David Henningsson4cb36312010-09-30 10:12:50 +02002067
Linus Torvalds1da177e2005-04-16 15:20:36 -07002068 if (pos >= azx_dev->bufsize)
2069 pos = 0;
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002070 return pos;
2071}
2072
2073static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2074{
2075 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2076 struct azx *chip = apcm->chip;
2077 struct azx_dev *azx_dev = get_azx_dev(substream);
2078 return bytes_to_frames(substream->runtime,
Takashi Iwai798cb7e2011-09-30 08:52:26 +02002079 azx_get_position(chip, azx_dev, false));
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002080}
2081
2082/*
2083 * Check whether the current DMA position is acceptable for updating
2084 * periods. Returns non-zero if it's OK.
2085 *
2086 * Many HD-audio controllers appear pretty inaccurate about
2087 * the update-IRQ timing. The IRQ is issued before actually the
2088 * data is processed. So, we need to process it afterwords in a
2089 * workqueue.
2090 */
2091static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2092{
Jaroslav Kyselae5463722010-05-11 10:21:46 +02002093 u32 wallclk;
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002094 unsigned int pos;
Shahin Ghazinouribeaffc32010-05-11 08:19:55 +02002095 int stream;
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002096
Jaroslav Kyselaf48f6062010-05-11 12:10:47 +02002097 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2098 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
Jaroslav Kyselafa00e042009-04-10 12:20:45 +02002099 return -1; /* bogus (too early) interrupt */
Jaroslav Kyselafa00e042009-04-10 12:20:45 +02002100
Shahin Ghazinouribeaffc32010-05-11 08:19:55 +02002101 stream = azx_dev->substream->stream;
Takashi Iwai798cb7e2011-09-30 08:52:26 +02002102 pos = azx_get_position(chip, azx_dev, true);
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002103
Takashi Iwaid6d8bf52010-02-12 18:17:06 +01002104 if (WARN_ONCE(!azx_dev->period_bytes,
2105 "hda-intel: zero azx_dev->period_bytes"))
Jaroslav Kyselaf48f6062010-05-11 12:10:47 +02002106 return -1; /* this shouldn't happen! */
Jaroslav Kyselaedb39932010-06-02 13:29:17 +02002107 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
Jaroslav Kyselaf48f6062010-05-11 12:10:47 +02002108 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2109 /* NG - it's below the first next period boundary */
2110 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
Jaroslav Kyselaedb39932010-06-02 13:29:17 +02002111 azx_dev->start_wallclk += wallclk;
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002112 return 1; /* OK, it's fine */
2113}
2114
2115/*
2116 * The work for pending PCM period updates.
2117 */
2118static void azx_irq_pending_work(struct work_struct *work)
2119{
2120 struct azx *chip = container_of(work, struct azx, irq_pending_work);
Jaroslav Kyselae5463722010-05-11 10:21:46 +02002121 int i, pending, ok;
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002122
Takashi Iwaia6a950a2008-06-10 17:53:35 +02002123 if (!chip->irq_pending_warned) {
2124 printk(KERN_WARNING
2125 "hda-intel: IRQ timing workaround is activated "
2126 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2127 chip->card->number);
2128 chip->irq_pending_warned = 1;
2129 }
2130
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002131 for (;;) {
2132 pending = 0;
2133 spin_lock_irq(&chip->reg_lock);
2134 for (i = 0; i < chip->num_streams; i++) {
2135 struct azx_dev *azx_dev = &chip->azx_dev[i];
2136 if (!azx_dev->irq_pending ||
2137 !azx_dev->substream ||
2138 !azx_dev->running)
2139 continue;
Jaroslav Kyselae5463722010-05-11 10:21:46 +02002140 ok = azx_position_ok(chip, azx_dev);
2141 if (ok > 0) {
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002142 azx_dev->irq_pending = 0;
2143 spin_unlock(&chip->reg_lock);
2144 snd_pcm_period_elapsed(azx_dev->substream);
2145 spin_lock(&chip->reg_lock);
Jaroslav Kyselae5463722010-05-11 10:21:46 +02002146 } else if (ok < 0) {
2147 pending = 0; /* too early */
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002148 } else
2149 pending++;
2150 }
2151 spin_unlock_irq(&chip->reg_lock);
2152 if (!pending)
2153 return;
Takashi Iwai08af4952010-08-03 14:39:04 +02002154 msleep(1);
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002155 }
2156}
2157
2158/* clear irq_pending flags and assure no on-going workq */
2159static void azx_clear_irq_pending(struct azx *chip)
2160{
2161 int i;
2162
2163 spin_lock_irq(&chip->reg_lock);
2164 for (i = 0; i < chip->num_streams; i++)
2165 chip->azx_dev[i].irq_pending = 0;
2166 spin_unlock_irq(&chip->reg_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002167}
2168
Takashi Iwai27fe48d92011-09-28 17:16:09 +02002169#ifdef CONFIG_X86
2170static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2171 struct vm_area_struct *area)
2172{
2173 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2174 struct azx *chip = apcm->chip;
2175 if (!azx_snoop(chip))
2176 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2177 return snd_pcm_lib_default_mmap(substream, area);
2178}
2179#else
2180#define azx_pcm_mmap NULL
2181#endif
2182
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002183static struct snd_pcm_ops azx_pcm_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002184 .open = azx_pcm_open,
2185 .close = azx_pcm_close,
2186 .ioctl = snd_pcm_lib_ioctl,
2187 .hw_params = azx_pcm_hw_params,
2188 .hw_free = azx_pcm_hw_free,
2189 .prepare = azx_pcm_prepare,
2190 .trigger = azx_pcm_trigger,
2191 .pointer = azx_pcm_pointer,
Takashi Iwai27fe48d92011-09-28 17:16:09 +02002192 .mmap = azx_pcm_mmap,
Takashi Iwai4ce107b2008-02-06 14:50:19 +01002193 .page = snd_pcm_sgbuf_ops_page,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002194};
2195
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002196static void azx_pcm_free(struct snd_pcm *pcm)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002197{
Takashi Iwai176d5332008-07-30 15:01:44 +02002198 struct azx_pcm *apcm = pcm->private_data;
2199 if (apcm) {
2200 apcm->chip->pcm[pcm->device] = NULL;
2201 kfree(apcm);
2202 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002203}
2204
Takashi Iwaiacfa6342011-07-12 17:27:46 +02002205#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2206
Takashi Iwai176d5332008-07-30 15:01:44 +02002207static int
Takashi Iwai33fa35e2008-11-06 16:50:40 +01002208azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2209 struct hda_pcm *cpcm)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002210{
Takashi Iwai33fa35e2008-11-06 16:50:40 +01002211 struct azx *chip = bus->private_data;
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002212 struct snd_pcm *pcm;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002213 struct azx_pcm *apcm;
Takashi Iwai176d5332008-07-30 15:01:44 +02002214 int pcm_dev = cpcm->device;
Takashi Iwaiacfa6342011-07-12 17:27:46 +02002215 unsigned int size;
Takashi Iwai176d5332008-07-30 15:01:44 +02002216 int s, err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002217
Takashi Iwaic8936222010-01-28 17:08:53 +01002218 if (pcm_dev >= HDA_MAX_PCMS) {
Takashi Iwai176d5332008-07-30 15:01:44 +02002219 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2220 pcm_dev);
Takashi Iwaida3cec32008-08-08 17:12:14 +02002221 return -EINVAL;
Takashi Iwai176d5332008-07-30 15:01:44 +02002222 }
2223 if (chip->pcm[pcm_dev]) {
2224 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2225 return -EBUSY;
2226 }
2227 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2228 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2229 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002230 &pcm);
2231 if (err < 0)
2232 return err;
Takashi Iwai18cb7102009-04-16 10:22:24 +02002233 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
Takashi Iwai176d5332008-07-30 15:01:44 +02002234 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002235 if (apcm == NULL)
2236 return -ENOMEM;
2237 apcm->chip = chip;
2238 apcm->codec = codec;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002239 pcm->private_data = apcm;
2240 pcm->private_free = azx_pcm_free;
Takashi Iwai176d5332008-07-30 15:01:44 +02002241 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2242 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2243 chip->pcm[pcm_dev] = pcm;
2244 cpcm->pcm = pcm;
2245 for (s = 0; s < 2; s++) {
2246 apcm->hinfo[s] = &cpcm->stream[s];
2247 if (cpcm->stream[s].substreams)
2248 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2249 }
2250 /* buffer pre-allocation */
Takashi Iwaiacfa6342011-07-12 17:27:46 +02002251 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2252 if (size > MAX_PREALLOC_SIZE)
2253 size = MAX_PREALLOC_SIZE;
Takashi Iwai4ce107b2008-02-06 14:50:19 +01002254 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002255 snd_dma_pci_data(chip->pci),
Takashi Iwaiacfa6342011-07-12 17:27:46 +02002256 size, MAX_PREALLOC_SIZE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002257 return 0;
2258}
2259
2260/*
2261 * mixer creation - all stuff is implemented in hda module
2262 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002263static int __devinit azx_mixer_create(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002264{
2265 return snd_hda_build_controls(chip->bus);
2266}
2267
2268
2269/*
2270 * initialize SD streams
2271 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002272static int __devinit azx_init_stream(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002273{
2274 int i;
2275
2276 /* initialize each stream (aka device)
Takashi Iwaid01ce992007-07-27 16:52:19 +02002277 * assign the starting bdl address to each stream (device)
2278 * and initialize
Linus Torvalds1da177e2005-04-16 15:20:36 -07002279 */
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002280 for (i = 0; i < chip->num_streams; i++) {
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002281 struct azx_dev *azx_dev = &chip->azx_dev[i];
Takashi Iwai929861c2006-08-31 16:55:40 +02002282 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002283 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2284 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2285 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2286 azx_dev->sd_int_sta_mask = 1 << i;
2287 /* stream tag: must be non-zero and unique */
2288 azx_dev->index = i;
2289 azx_dev->stream_tag = i + 1;
2290 }
2291
2292 return 0;
2293}
2294
Takashi Iwai68e7fff2006-10-23 13:40:59 +02002295static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2296{
Takashi Iwai437a5a42006-11-21 12:14:23 +01002297 if (request_irq(chip->pci->irq, azx_interrupt,
2298 chip->msi ? 0 : IRQF_SHARED,
Takashi Iwai934c2b62011-06-10 16:36:37 +02002299 KBUILD_MODNAME, chip)) {
Takashi Iwai68e7fff2006-10-23 13:40:59 +02002300 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2301 "disabling device\n", chip->pci->irq);
2302 if (do_disconnect)
2303 snd_card_disconnect(chip->card);
2304 return -1;
2305 }
2306 chip->irq = chip->pci->irq;
Takashi Iwai69e13412006-11-21 12:10:55 +01002307 pci_intx(chip->pci, !chip->msi);
Takashi Iwai68e7fff2006-10-23 13:40:59 +02002308 return 0;
2309}
2310
Linus Torvalds1da177e2005-04-16 15:20:36 -07002311
Takashi Iwaicb53c622007-08-10 17:21:45 +02002312static void azx_stop_chip(struct azx *chip)
2313{
Takashi Iwai95e99fd2007-08-13 15:29:04 +02002314 if (!chip->initialized)
Takashi Iwaicb53c622007-08-10 17:21:45 +02002315 return;
2316
2317 /* disable interrupts */
2318 azx_int_disable(chip);
2319 azx_int_clear(chip);
2320
2321 /* disable CORB/RIRB */
2322 azx_free_cmd_io(chip);
2323
2324 /* disable position buffer */
2325 azx_writel(chip, DPLBASE, 0);
2326 azx_writel(chip, DPUBASE, 0);
2327
2328 chip->initialized = 0;
2329}
2330
2331#ifdef CONFIG_SND_HDA_POWER_SAVE
2332/* power-up/down the controller */
Takashi Iwai33fa35e2008-11-06 16:50:40 +01002333static void azx_power_notify(struct hda_bus *bus)
Takashi Iwaicb53c622007-08-10 17:21:45 +02002334{
Takashi Iwai33fa35e2008-11-06 16:50:40 +01002335 struct azx *chip = bus->private_data;
Takashi Iwaicb53c622007-08-10 17:21:45 +02002336 struct hda_codec *c;
2337 int power_on = 0;
2338
Takashi Iwai33fa35e2008-11-06 16:50:40 +01002339 list_for_each_entry(c, &bus->codec_list, list) {
Takashi Iwaicb53c622007-08-10 17:21:45 +02002340 if (c->power_on) {
2341 power_on = 1;
2342 break;
2343 }
2344 }
2345 if (power_on)
Jaroslav Kyselacd508fe2010-03-26 10:28:46 +01002346 azx_init_chip(chip, 1);
Wu Fengguang0287d972009-12-11 20:15:11 +08002347 else if (chip->running && power_save_controller &&
2348 !bus->power_keep_link_on)
Takashi Iwaicb53c622007-08-10 17:21:45 +02002349 azx_stop_chip(chip);
Takashi Iwaicb53c622007-08-10 17:21:45 +02002350}
Takashi Iwai5c0b9be2008-12-11 11:47:17 +01002351#endif /* CONFIG_SND_HDA_POWER_SAVE */
2352
2353#ifdef CONFIG_PM
2354/*
2355 * power management
2356 */
Takashi Iwai986862bd2008-11-27 12:40:13 +01002357
2358static int snd_hda_codecs_inuse(struct hda_bus *bus)
2359{
2360 struct hda_codec *codec;
2361
2362 list_for_each_entry(codec, &bus->codec_list, list) {
2363 if (snd_hda_codec_needs_resume(codec))
2364 return 1;
2365 }
2366 return 0;
2367}
Takashi Iwaicb53c622007-08-10 17:21:45 +02002368
Takashi Iwai421a1252005-11-17 16:11:09 +01002369static int azx_suspend(struct pci_dev *pci, pm_message_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002370{
Takashi Iwai421a1252005-11-17 16:11:09 +01002371 struct snd_card *card = pci_get_drvdata(pci);
2372 struct azx *chip = card->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002373 int i;
2374
Takashi Iwai421a1252005-11-17 16:11:09 +01002375 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002376 azx_clear_irq_pending(chip);
Takashi Iwaic8936222010-01-28 17:08:53 +01002377 for (i = 0; i < HDA_MAX_PCMS; i++)
Takashi Iwai421a1252005-11-17 16:11:09 +01002378 snd_pcm_suspend_all(chip->pcm[i]);
Takashi Iwai0b7a2e92007-08-14 15:18:26 +02002379 if (chip->initialized)
Takashi Iwai8dd78332009-06-02 01:16:07 +02002380 snd_hda_suspend(chip->bus);
Takashi Iwaicb53c622007-08-10 17:21:45 +02002381 azx_stop_chip(chip);
Takashi Iwai30b35392006-10-11 18:52:53 +02002382 if (chip->irq >= 0) {
Takashi Iwai43001c92006-09-08 12:30:03 +02002383 free_irq(chip->irq, chip);
Takashi Iwai30b35392006-10-11 18:52:53 +02002384 chip->irq = -1;
2385 }
Takashi Iwai68e7fff2006-10-23 13:40:59 +02002386 if (chip->msi)
Takashi Iwai43001c92006-09-08 12:30:03 +02002387 pci_disable_msi(chip->pci);
Takashi Iwai421a1252005-11-17 16:11:09 +01002388 pci_disable_device(pci);
2389 pci_save_state(pci);
Takashi Iwai30b35392006-10-11 18:52:53 +02002390 pci_set_power_state(pci, pci_choose_state(pci, state));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002391 return 0;
2392}
2393
Takashi Iwai421a1252005-11-17 16:11:09 +01002394static int azx_resume(struct pci_dev *pci)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002395{
Takashi Iwai421a1252005-11-17 16:11:09 +01002396 struct snd_card *card = pci_get_drvdata(pci);
2397 struct azx *chip = card->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002398
Takashi Iwaid14a7e02009-02-16 10:13:03 +01002399 pci_set_power_state(pci, PCI_D0);
2400 pci_restore_state(pci);
Takashi Iwai30b35392006-10-11 18:52:53 +02002401 if (pci_enable_device(pci) < 0) {
2402 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2403 "disabling device\n");
2404 snd_card_disconnect(card);
2405 return -EIO;
2406 }
2407 pci_set_master(pci);
Takashi Iwai68e7fff2006-10-23 13:40:59 +02002408 if (chip->msi)
2409 if (pci_enable_msi(pci) < 0)
2410 chip->msi = 0;
2411 if (azx_acquire_irq(chip, 1) < 0)
Takashi Iwai30b35392006-10-11 18:52:53 +02002412 return -EIO;
Takashi Iwaicb53c622007-08-10 17:21:45 +02002413 azx_init_pci(chip);
Maxim Levitskyd804ad92007-09-03 15:28:04 +02002414
2415 if (snd_hda_codecs_inuse(chip->bus))
Jaroslav Kyselacd508fe2010-03-26 10:28:46 +01002416 azx_init_chip(chip, 1);
Maxim Levitskyd804ad92007-09-03 15:28:04 +02002417
Linus Torvalds1da177e2005-04-16 15:20:36 -07002418 snd_hda_resume(chip->bus);
Takashi Iwai421a1252005-11-17 16:11:09 +01002419 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002420 return 0;
2421}
2422#endif /* CONFIG_PM */
2423
2424
2425/*
Takashi Iwai0cbf0092008-10-29 16:18:25 +01002426 * reboot notifier for hang-up problem at power-down
2427 */
2428static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2429{
2430 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
Takashi Iwaifb8d1a32009-11-10 16:02:29 +01002431 snd_hda_bus_reboot_notify(chip->bus);
Takashi Iwai0cbf0092008-10-29 16:18:25 +01002432 azx_stop_chip(chip);
2433 return NOTIFY_OK;
2434}
2435
2436static void azx_notifier_register(struct azx *chip)
2437{
2438 chip->reboot_notifier.notifier_call = azx_halt;
2439 register_reboot_notifier(&chip->reboot_notifier);
2440}
2441
2442static void azx_notifier_unregister(struct azx *chip)
2443{
2444 if (chip->reboot_notifier.notifier_call)
2445 unregister_reboot_notifier(&chip->reboot_notifier);
2446}
2447
2448/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002449 * destructor
2450 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002451static int azx_free(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002452{
Takashi Iwai4ce107b2008-02-06 14:50:19 +01002453 int i;
2454
Takashi Iwai0cbf0092008-10-29 16:18:25 +01002455 azx_notifier_unregister(chip);
2456
Takashi Iwaice43fba2005-05-30 20:33:44 +02002457 if (chip->initialized) {
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002458 azx_clear_irq_pending(chip);
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002459 for (i = 0; i < chip->num_streams; i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002460 azx_stream_stop(chip, &chip->azx_dev[i]);
Takashi Iwaicb53c622007-08-10 17:21:45 +02002461 azx_stop_chip(chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002462 }
2463
Jeff Garzikf000fd82008-04-22 13:50:34 +02002464 if (chip->irq >= 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002465 free_irq(chip->irq, (void*)chip);
Takashi Iwai68e7fff2006-10-23 13:40:59 +02002466 if (chip->msi)
Takashi Iwai30b35392006-10-11 18:52:53 +02002467 pci_disable_msi(chip->pci);
Takashi Iwaif079c252006-06-01 11:42:14 +02002468 if (chip->remap_addr)
2469 iounmap(chip->remap_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002470
Takashi Iwai4ce107b2008-02-06 14:50:19 +01002471 if (chip->azx_dev) {
2472 for (i = 0; i < chip->num_streams; i++)
Takashi Iwai27fe48d92011-09-28 17:16:09 +02002473 if (chip->azx_dev[i].bdl.area) {
2474 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
Takashi Iwai4ce107b2008-02-06 14:50:19 +01002475 snd_dma_free_pages(&chip->azx_dev[i].bdl);
Takashi Iwai27fe48d92011-09-28 17:16:09 +02002476 }
Takashi Iwai4ce107b2008-02-06 14:50:19 +01002477 }
Takashi Iwai27fe48d92011-09-28 17:16:09 +02002478 if (chip->rb.area) {
2479 mark_pages_wc(chip, &chip->rb, false);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002480 snd_dma_free_pages(&chip->rb);
Takashi Iwai27fe48d92011-09-28 17:16:09 +02002481 }
2482 if (chip->posbuf.area) {
2483 mark_pages_wc(chip, &chip->posbuf, false);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002484 snd_dma_free_pages(&chip->posbuf);
Takashi Iwai27fe48d92011-09-28 17:16:09 +02002485 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002486 pci_release_regions(chip->pci);
2487 pci_disable_device(chip->pci);
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002488 kfree(chip->azx_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002489 kfree(chip);
2490
2491 return 0;
2492}
2493
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002494static int azx_dev_free(struct snd_device *device)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002495{
2496 return azx_free(device->device_data);
2497}
2498
2499/*
Takashi Iwai3372a152007-02-01 15:46:50 +01002500 * white/black-listing for position_fix
2501 */
Ralf Baechle623ec042007-03-13 15:29:47 +01002502static struct snd_pci_quirk position_fix_list[] __devinitdata = {
Takashi Iwaid2e1c972008-06-10 17:53:34 +02002503 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2504 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
Takashi Iwai051a8cb2011-10-18 10:44:05 +02002505 SND_PCI_QUIRK(0x1028, 0x02c6, "Dell Inspiron 1010", POS_FIX_LPIB),
Takashi Iwai2f703e72009-12-01 14:17:37 +01002506 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
Takashi Iwaid2e1c972008-06-10 17:53:34 +02002507 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
Daniel T Chendd37f8e2010-05-30 01:17:03 -04002508 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
Daniel T Chen9f75c1b2010-05-30 13:08:41 -04002509 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
Daniel T Chene96d3122010-05-27 18:32:18 -04002510 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
Daniel T Chen4e0938d2010-05-22 13:12:22 -04002511 SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
Daniel T Chen61bb42c2010-05-29 11:04:11 -04002512 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
Daniel T Chen9ec8dda2010-03-28 02:34:40 -04002513 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
Takashi Iwai45d4ebf2009-11-30 11:58:30 +01002514 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
Takashi Iwai8815cd02010-04-15 09:02:41 +02002515 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
Daniel T Chenb90c0762010-05-30 19:31:41 -04002516 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
Daniel T Chen0e0280d2010-04-21 19:55:43 -04002517 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
Takashi Iwai3372a152007-02-01 15:46:50 +01002518 {}
2519};
2520
2521static int __devinit check_position_fix(struct azx *chip, int fix)
2522{
2523 const struct snd_pci_quirk *q;
2524
Takashi Iwaic673ba12009-03-17 07:49:14 +01002525 switch (fix) {
2526 case POS_FIX_LPIB:
2527 case POS_FIX_POSBUF:
David Henningsson4cb36312010-09-30 10:12:50 +02002528 case POS_FIX_VIACOMBO:
Takashi Iwaic673ba12009-03-17 07:49:14 +01002529 return fix;
2530 }
2531
Takashi Iwaic673ba12009-03-17 07:49:14 +01002532 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2533 if (q) {
2534 printk(KERN_INFO
2535 "hda_intel: position_fix set to %d "
2536 "for device %04x:%04x\n",
2537 q->value, q->subvendor, q->subdevice);
2538 return q->value;
Takashi Iwai3372a152007-02-01 15:46:50 +01002539 }
David Henningssonbdd9ef22010-10-04 12:02:14 +02002540
2541 /* Check VIA/ATI HD Audio Controller exist */
Takashi Iwai9477c582011-05-25 09:11:37 +02002542 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2543 snd_printd(SFX "Using VIACOMBO position fix\n");
David Henningssonbdd9ef22010-10-04 12:02:14 +02002544 return POS_FIX_VIACOMBO;
2545 }
Takashi Iwai9477c582011-05-25 09:11:37 +02002546 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2547 snd_printd(SFX "Using LPIB position fix\n");
2548 return POS_FIX_LPIB;
2549 }
Takashi Iwaic673ba12009-03-17 07:49:14 +01002550 return POS_FIX_AUTO;
Takashi Iwai3372a152007-02-01 15:46:50 +01002551}
2552
2553/*
Takashi Iwai669ba272007-08-17 09:17:36 +02002554 * black-lists for probe_mask
2555 */
2556static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2557 /* Thinkpad often breaks the controller communication when accessing
2558 * to the non-working (or non-existing) modem codec slot.
2559 */
2560 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2561 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2562 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
Takashi Iwai0edb9452008-11-07 14:53:09 +01002563 /* broken BIOS */
2564 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
Takashi Iwaief1681d2008-11-24 17:29:28 +01002565 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2566 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
Takashi Iwai20db7cb2009-02-13 08:18:48 +01002567 /* forced codec slots */
Ozan Çağlayan93574842009-05-23 15:00:04 +03002568 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
Takashi Iwai20db7cb2009-02-13 08:18:48 +01002569 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
Takashi Iwai669ba272007-08-17 09:17:36 +02002570 {}
2571};
2572
Takashi Iwaif1eaaee2009-02-13 08:16:55 +01002573#define AZX_FORCE_CODEC_MASK 0x100
2574
Takashi Iwai5aba4f82008-01-07 15:16:37 +01002575static void __devinit check_probe_mask(struct azx *chip, int dev)
Takashi Iwai669ba272007-08-17 09:17:36 +02002576{
2577 const struct snd_pci_quirk *q;
2578
Takashi Iwaif1eaaee2009-02-13 08:16:55 +01002579 chip->codec_probe_mask = probe_mask[dev];
2580 if (chip->codec_probe_mask == -1) {
Takashi Iwai669ba272007-08-17 09:17:36 +02002581 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2582 if (q) {
2583 printk(KERN_INFO
2584 "hda_intel: probe_mask set to 0x%x "
2585 "for device %04x:%04x\n",
2586 q->value, q->subvendor, q->subdevice);
Takashi Iwaif1eaaee2009-02-13 08:16:55 +01002587 chip->codec_probe_mask = q->value;
Takashi Iwai669ba272007-08-17 09:17:36 +02002588 }
2589 }
Takashi Iwaif1eaaee2009-02-13 08:16:55 +01002590
2591 /* check forced option */
2592 if (chip->codec_probe_mask != -1 &&
2593 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2594 chip->codec_mask = chip->codec_probe_mask & 0xff;
2595 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2596 chip->codec_mask);
2597 }
Takashi Iwai669ba272007-08-17 09:17:36 +02002598}
2599
Takashi Iwai4d8e22e2009-08-11 14:21:26 +02002600/*
Takashi Iwai716238552009-09-28 13:14:04 +02002601 * white/black-list for enable_msi
Takashi Iwai4d8e22e2009-08-11 14:21:26 +02002602 */
Takashi Iwai716238552009-09-28 13:14:04 +02002603static struct snd_pci_quirk msi_black_list[] __devinitdata = {
Takashi Iwai9dc83982009-12-22 08:15:01 +01002604 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
Takashi Iwai0a27fcf2010-02-15 17:05:28 +01002605 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
Ralf Gerbigecd21622010-03-09 18:25:47 +01002606 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
Michele Ballabio4193d132010-03-06 21:06:46 +01002607 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
Takashi Iwai38155952010-04-04 12:14:03 +02002608 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
Takashi Iwai4d8e22e2009-08-11 14:21:26 +02002609 {}
2610};
2611
2612static void __devinit check_msi(struct azx *chip)
2613{
2614 const struct snd_pci_quirk *q;
2615
Takashi Iwai716238552009-09-28 13:14:04 +02002616 if (enable_msi >= 0) {
2617 chip->msi = !!enable_msi;
Takashi Iwai4d8e22e2009-08-11 14:21:26 +02002618 return;
Takashi Iwai716238552009-09-28 13:14:04 +02002619 }
2620 chip->msi = 1; /* enable MSI as default */
2621 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
Takashi Iwai4d8e22e2009-08-11 14:21:26 +02002622 if (q) {
2623 printk(KERN_INFO
2624 "hda_intel: msi for device %04x:%04x set to %d\n",
2625 q->subvendor, q->subdevice, q->value);
2626 chip->msi = q->value;
Takashi Iwai80c43ed2010-03-15 15:51:53 +01002627 return;
2628 }
2629
2630 /* NVidia chipsets seem to cause troubles with MSI */
Takashi Iwai9477c582011-05-25 09:11:37 +02002631 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2632 printk(KERN_INFO "hda_intel: Disabling MSI\n");
Takashi Iwai80c43ed2010-03-15 15:51:53 +01002633 chip->msi = 0;
Takashi Iwai4d8e22e2009-08-11 14:21:26 +02002634 }
2635}
2636
Takashi Iwai669ba272007-08-17 09:17:36 +02002637
2638/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002639 * constructor
2640 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002641static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
Takashi Iwai9477c582011-05-25 09:11:37 +02002642 int dev, unsigned int driver_caps,
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002643 struct azx **rchip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002644{
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002645 struct azx *chip;
Takashi Iwai4ce107b2008-02-06 14:50:19 +01002646 int i, err;
Tobin Davisbcd72002008-01-15 11:23:55 +01002647 unsigned short gcap;
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002648 static struct snd_device_ops ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002649 .dev_free = azx_dev_free,
2650 };
2651
2652 *rchip = NULL;
Tobin Davisbcd72002008-01-15 11:23:55 +01002653
Pavel Machek927fc862006-08-31 17:03:43 +02002654 err = pci_enable_device(pci);
2655 if (err < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002656 return err;
2657
Takashi Iwaie560d8d2005-09-09 14:21:46 +02002658 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
Pavel Machek927fc862006-08-31 17:03:43 +02002659 if (!chip) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002660 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2661 pci_disable_device(pci);
2662 return -ENOMEM;
2663 }
2664
2665 spin_lock_init(&chip->reg_lock);
Ingo Molnar62932df2006-01-16 16:34:20 +01002666 mutex_init(&chip->open_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002667 chip->card = card;
2668 chip->pci = pci;
2669 chip->irq = -1;
Takashi Iwai9477c582011-05-25 09:11:37 +02002670 chip->driver_caps = driver_caps;
2671 chip->driver_type = driver_caps & 0xff;
Takashi Iwai4d8e22e2009-08-11 14:21:26 +02002672 check_msi(chip);
Takashi Iwai555e2192008-06-10 17:53:34 +02002673 chip->dev_index = dev;
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002674 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002675
Shahin Ghazinouribeaffc32010-05-11 08:19:55 +02002676 chip->position_fix[0] = chip->position_fix[1] =
2677 check_position_fix(chip, position_fix[dev]);
Takashi Iwai5aba4f82008-01-07 15:16:37 +01002678 check_probe_mask(chip, dev);
Takashi Iwai3372a152007-02-01 15:46:50 +01002679
Takashi Iwai27346162006-01-12 18:28:44 +01002680 chip->single_cmd = single_cmd;
Takashi Iwai27fe48d92011-09-28 17:16:09 +02002681 chip->snoop = hda_snoop;
Takashi Iwaic74db862005-05-12 14:26:27 +02002682
Takashi Iwai5c0d7bc2008-06-10 17:53:35 +02002683 if (bdl_pos_adj[dev] < 0) {
2684 switch (chip->driver_type) {
Takashi Iwai0c6341a2008-06-13 20:50:27 +02002685 case AZX_DRIVER_ICH:
Seth Heasley32679f92010-02-22 17:31:09 -08002686 case AZX_DRIVER_PCH:
Takashi Iwai0c6341a2008-06-13 20:50:27 +02002687 bdl_pos_adj[dev] = 1;
Takashi Iwai5c0d7bc2008-06-10 17:53:35 +02002688 break;
2689 default:
Takashi Iwai0c6341a2008-06-13 20:50:27 +02002690 bdl_pos_adj[dev] = 32;
Takashi Iwai5c0d7bc2008-06-10 17:53:35 +02002691 break;
2692 }
2693 }
2694
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002695#if BITS_PER_LONG != 64
2696 /* Fix up base address on ULI M5461 */
2697 if (chip->driver_type == AZX_DRIVER_ULI) {
2698 u16 tmp3;
2699 pci_read_config_word(pci, 0x40, &tmp3);
2700 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2701 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2702 }
2703#endif
2704
Pavel Machek927fc862006-08-31 17:03:43 +02002705 err = pci_request_regions(pci, "ICH HD audio");
2706 if (err < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002707 kfree(chip);
2708 pci_disable_device(pci);
2709 return err;
2710 }
2711
Pavel Machek927fc862006-08-31 17:03:43 +02002712 chip->addr = pci_resource_start(pci, 0);
Arjan van de Ven2f5ad542008-09-28 16:20:09 -07002713 chip->remap_addr = pci_ioremap_bar(pci, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002714 if (chip->remap_addr == NULL) {
2715 snd_printk(KERN_ERR SFX "ioremap error\n");
2716 err = -ENXIO;
2717 goto errout;
2718 }
2719
Takashi Iwai68e7fff2006-10-23 13:40:59 +02002720 if (chip->msi)
2721 if (pci_enable_msi(pci) < 0)
2722 chip->msi = 0;
Stephen Hemminger7376d012006-08-21 19:17:46 +02002723
Takashi Iwai68e7fff2006-10-23 13:40:59 +02002724 if (azx_acquire_irq(chip, 0) < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002725 err = -EBUSY;
2726 goto errout;
2727 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002728
2729 pci_set_master(pci);
2730 synchronize_irq(chip->irq);
2731
Tobin Davisbcd72002008-01-15 11:23:55 +01002732 gcap = azx_readw(chip, GCAP);
Takashi Iwai4abc1cc2009-05-19 12:16:46 +02002733 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
Tobin Davisbcd72002008-01-15 11:23:55 +01002734
Andiry Brienzadc4c2e62009-07-08 13:55:31 +08002735 /* disable SB600 64bit support for safety */
Takashi Iwai9477c582011-05-25 09:11:37 +02002736 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
Andiry Brienzadc4c2e62009-07-08 13:55:31 +08002737 struct pci_dev *p_smbus;
2738 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2739 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2740 NULL);
2741 if (p_smbus) {
2742 if (p_smbus->revision < 0x30)
2743 gcap &= ~ICH6_GCAP_64OK;
2744 pci_dev_put(p_smbus);
2745 }
2746 }
Takashi Iwai09240cf2009-03-17 07:47:18 +01002747
Takashi Iwai9477c582011-05-25 09:11:37 +02002748 /* disable 64bit DMA address on some devices */
2749 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2750 snd_printd(SFX "Disabling 64bit DMA\n");
Jaroslav Kysela396087e2009-12-09 10:44:47 +01002751 gcap &= ~ICH6_GCAP_64OK;
Takashi Iwai9477c582011-05-25 09:11:37 +02002752 }
Jaroslav Kysela396087e2009-12-09 10:44:47 +01002753
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -05002754 /* disable buffer size rounding to 128-byte multiples if supported */
2755 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
2756 align_buffer_size = 0;
2757
Takashi Iwaicf7aaca2008-02-06 15:05:57 +01002758 /* allow 64bit DMA address if supported by H/W */
Takashi Iwaib21fadb2009-05-28 12:26:15 +02002759 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
Yang Hongyange9304382009-04-13 14:40:14 -07002760 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
Takashi Iwai09240cf2009-03-17 07:47:18 +01002761 else {
Yang Hongyange9304382009-04-13 14:40:14 -07002762 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2763 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
Takashi Iwai09240cf2009-03-17 07:47:18 +01002764 }
Takashi Iwaicf7aaca2008-02-06 15:05:57 +01002765
Takashi Iwai8b6ed8e2008-02-19 11:36:35 +01002766 /* read number of streams from GCAP register instead of using
2767 * hardcoded value
2768 */
2769 chip->capture_streams = (gcap >> 8) & 0x0f;
2770 chip->playback_streams = (gcap >> 12) & 0x0f;
2771 if (!chip->playback_streams && !chip->capture_streams) {
Tobin Davisbcd72002008-01-15 11:23:55 +01002772 /* gcap didn't give any info, switching to old method */
2773
2774 switch (chip->driver_type) {
2775 case AZX_DRIVER_ULI:
2776 chip->playback_streams = ULI_NUM_PLAYBACK;
2777 chip->capture_streams = ULI_NUM_CAPTURE;
Tobin Davisbcd72002008-01-15 11:23:55 +01002778 break;
2779 case AZX_DRIVER_ATIHDMI:
2780 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2781 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
Tobin Davisbcd72002008-01-15 11:23:55 +01002782 break;
Yang, Libinc4da29c2008-11-13 11:07:07 +01002783 case AZX_DRIVER_GENERIC:
Tobin Davisbcd72002008-01-15 11:23:55 +01002784 default:
2785 chip->playback_streams = ICH6_NUM_PLAYBACK;
2786 chip->capture_streams = ICH6_NUM_CAPTURE;
Tobin Davisbcd72002008-01-15 11:23:55 +01002787 break;
2788 }
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002789 }
Takashi Iwai8b6ed8e2008-02-19 11:36:35 +01002790 chip->capture_index_offset = 0;
2791 chip->playback_index_offset = chip->capture_streams;
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002792 chip->num_streams = chip->playback_streams + chip->capture_streams;
Takashi Iwaid01ce992007-07-27 16:52:19 +02002793 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2794 GFP_KERNEL);
Pavel Machek927fc862006-08-31 17:03:43 +02002795 if (!chip->azx_dev) {
Takashi Iwai4abc1cc2009-05-19 12:16:46 +02002796 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002797 goto errout;
2798 }
2799
Takashi Iwai4ce107b2008-02-06 14:50:19 +01002800 for (i = 0; i < chip->num_streams; i++) {
2801 /* allocate memory for the BDL for each stream */
2802 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2803 snd_dma_pci_data(chip->pci),
2804 BDL_SIZE, &chip->azx_dev[i].bdl);
2805 if (err < 0) {
2806 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2807 goto errout;
2808 }
Takashi Iwai27fe48d92011-09-28 17:16:09 +02002809 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002810 }
Takashi Iwai0be3b5d2005-09-05 17:11:40 +02002811 /* allocate memory for the position buffer */
Takashi Iwaid01ce992007-07-27 16:52:19 +02002812 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2813 snd_dma_pci_data(chip->pci),
2814 chip->num_streams * 8, &chip->posbuf);
2815 if (err < 0) {
Takashi Iwai0be3b5d2005-09-05 17:11:40 +02002816 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2817 goto errout;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002818 }
Takashi Iwai27fe48d92011-09-28 17:16:09 +02002819 mark_pages_wc(chip, &chip->posbuf, true);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002820 /* allocate CORB/RIRB */
Takashi Iwai81740862009-05-26 15:22:00 +02002821 err = azx_alloc_cmd_io(chip);
2822 if (err < 0)
2823 goto errout;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002824
2825 /* initialize streams */
2826 azx_init_stream(chip);
2827
2828 /* initialize chip */
Takashi Iwaicb53c622007-08-10 17:21:45 +02002829 azx_init_pci(chip);
Jaroslav Kysela10e77dd2010-03-26 11:04:38 +01002830 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002831
2832 /* codec detection */
Pavel Machek927fc862006-08-31 17:03:43 +02002833 if (!chip->codec_mask) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002834 snd_printk(KERN_ERR SFX "no codecs found!\n");
2835 err = -ENODEV;
2836 goto errout;
2837 }
2838
Takashi Iwaid01ce992007-07-27 16:52:19 +02002839 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2840 if (err <0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002841 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2842 goto errout;
2843 }
2844
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002845 strcpy(card->driver, "HDA-Intel");
Takashi Iwai18cb7102009-04-16 10:22:24 +02002846 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2847 sizeof(card->shortname));
2848 snprintf(card->longname, sizeof(card->longname),
2849 "%s at 0x%lx irq %i",
2850 card->shortname, chip->addr, chip->irq);
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002851
Linus Torvalds1da177e2005-04-16 15:20:36 -07002852 *rchip = chip;
2853 return 0;
2854
2855 errout:
2856 azx_free(chip);
2857 return err;
2858}
2859
Takashi Iwaicb53c622007-08-10 17:21:45 +02002860static void power_down_all_codecs(struct azx *chip)
2861{
2862#ifdef CONFIG_SND_HDA_POWER_SAVE
2863 /* The codecs were powered up in snd_hda_codec_new().
2864 * Now all initialization done, so turn them down if possible
2865 */
2866 struct hda_codec *codec;
2867 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2868 snd_hda_power_down(codec);
2869 }
2870#endif
2871}
2872
Takashi Iwaid01ce992007-07-27 16:52:19 +02002873static int __devinit azx_probe(struct pci_dev *pci,
2874 const struct pci_device_id *pci_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002875{
Takashi Iwai5aba4f82008-01-07 15:16:37 +01002876 static int dev;
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002877 struct snd_card *card;
2878 struct azx *chip;
Pavel Machek927fc862006-08-31 17:03:43 +02002879 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002880
Takashi Iwai5aba4f82008-01-07 15:16:37 +01002881 if (dev >= SNDRV_CARDS)
2882 return -ENODEV;
2883 if (!enable[dev]) {
2884 dev++;
2885 return -ENOENT;
2886 }
2887
Takashi Iwaie58de7b2008-12-28 16:44:30 +01002888 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2889 if (err < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002890 snd_printk(KERN_ERR SFX "Error creating card!\n");
Takashi Iwaie58de7b2008-12-28 16:44:30 +01002891 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002892 }
2893
Takashi Iwai4ea6fbc2009-06-17 09:52:54 +02002894 /* set this here since it's referred in snd_hda_load_patch() */
2895 snd_card_set_dev(card, &pci->dev);
2896
Takashi Iwai5aba4f82008-01-07 15:16:37 +01002897 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
Wu Fengguang41dda0f2008-11-20 09:24:52 +08002898 if (err < 0)
2899 goto out_free;
Takashi Iwai421a1252005-11-17 16:11:09 +01002900 card->private_data = chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002901
Jaroslav Kysela2dca0bb2009-11-13 18:41:52 +01002902#ifdef CONFIG_SND_HDA_INPUT_BEEP
2903 chip->beep_mode = beep_mode[dev];
2904#endif
2905
Linus Torvalds1da177e2005-04-16 15:20:36 -07002906 /* create codec instances */
Takashi Iwaia1e21c92009-06-17 09:33:52 +02002907 err = azx_codec_create(chip, model[dev]);
Wu Fengguang41dda0f2008-11-20 09:24:52 +08002908 if (err < 0)
2909 goto out_free;
Takashi Iwai4ea6fbc2009-06-17 09:52:54 +02002910#ifdef CONFIG_SND_HDA_PATCH_LOADER
Takashi Iwai41a63f12011-02-10 17:39:20 +01002911 if (patch[dev] && *patch[dev]) {
Takashi Iwai4ea6fbc2009-06-17 09:52:54 +02002912 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2913 patch[dev]);
2914 err = snd_hda_load_patch(chip->bus, patch[dev]);
2915 if (err < 0)
2916 goto out_free;
2917 }
2918#endif
Jaroslav Kysela10e77dd2010-03-26 11:04:38 +01002919 if ((probe_only[dev] & 1) == 0) {
Takashi Iwaia1e21c92009-06-17 09:33:52 +02002920 err = azx_codec_configure(chip);
2921 if (err < 0)
2922 goto out_free;
2923 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002924
2925 /* create PCM streams */
Takashi Iwai176d5332008-07-30 15:01:44 +02002926 err = snd_hda_build_pcms(chip->bus);
Wu Fengguang41dda0f2008-11-20 09:24:52 +08002927 if (err < 0)
2928 goto out_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002929
2930 /* create mixer controls */
Takashi Iwaid01ce992007-07-27 16:52:19 +02002931 err = azx_mixer_create(chip);
Wu Fengguang41dda0f2008-11-20 09:24:52 +08002932 if (err < 0)
2933 goto out_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002934
Takashi Iwaid01ce992007-07-27 16:52:19 +02002935 err = snd_card_register(card);
Wu Fengguang41dda0f2008-11-20 09:24:52 +08002936 if (err < 0)
2937 goto out_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002938
2939 pci_set_drvdata(pci, card);
Takashi Iwaicb53c622007-08-10 17:21:45 +02002940 chip->running = 1;
2941 power_down_all_codecs(chip);
Takashi Iwai0cbf0092008-10-29 16:18:25 +01002942 azx_notifier_register(chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002943
Andrew Paprockie25bcdb2008-01-13 11:57:17 +01002944 dev++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002945 return err;
Wu Fengguang41dda0f2008-11-20 09:24:52 +08002946out_free:
2947 snd_card_free(card);
2948 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002949}
2950
2951static void __devexit azx_remove(struct pci_dev *pci)
2952{
2953 snd_card_free(pci_get_drvdata(pci));
2954 pci_set_drvdata(pci, NULL);
2955}
2956
2957/* PCI IDs */
Alexey Dobriyancebe41d2010-02-06 00:21:03 +02002958static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
Seth Heasleyd2f2fcd2010-01-12 17:03:35 -08002959 /* CPT */
Takashi Iwai9477c582011-05-25 09:11:37 +02002960 { PCI_DEVICE(0x8086, 0x1c20),
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -05002961 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2962 AZX_DCAPS_BUFSIZE },
Seth Heasleycea310e2010-09-10 16:29:56 -07002963 /* PBG */
Takashi Iwai9477c582011-05-25 09:11:37 +02002964 { PCI_DEVICE(0x8086, 0x1d20),
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -05002965 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2966 AZX_DCAPS_BUFSIZE},
Seth Heasleyd2edeb72011-04-20 10:59:57 -07002967 /* Panther Point */
Takashi Iwai9477c582011-05-25 09:11:37 +02002968 { PCI_DEVICE(0x8086, 0x1e20),
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -05002969 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2970 AZX_DCAPS_BUFSIZE},
Takashi Iwai87218e92008-02-21 08:13:11 +01002971 /* SCH */
Takashi Iwai9477c582011-05-25 09:11:37 +02002972 { PCI_DEVICE(0x8086, 0x811b),
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -05002973 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
2974 AZX_DCAPS_BUFSIZE},
Takashi Iwai8b0bd222011-06-10 14:56:26 +02002975 { PCI_DEVICE(0x8086, 0x2668),
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -05002976 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2977 AZX_DCAPS_BUFSIZE }, /* ICH6 */
Takashi Iwai8b0bd222011-06-10 14:56:26 +02002978 { PCI_DEVICE(0x8086, 0x27d8),
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -05002979 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2980 AZX_DCAPS_BUFSIZE }, /* ICH7 */
Takashi Iwai8b0bd222011-06-10 14:56:26 +02002981 { PCI_DEVICE(0x8086, 0x269a),
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -05002982 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2983 AZX_DCAPS_BUFSIZE }, /* ESB2 */
Takashi Iwai8b0bd222011-06-10 14:56:26 +02002984 { PCI_DEVICE(0x8086, 0x284b),
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -05002985 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2986 AZX_DCAPS_BUFSIZE }, /* ICH8 */
Takashi Iwai8b0bd222011-06-10 14:56:26 +02002987 { PCI_DEVICE(0x8086, 0x293e),
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -05002988 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2989 AZX_DCAPS_BUFSIZE }, /* ICH9 */
Takashi Iwai8b0bd222011-06-10 14:56:26 +02002990 { PCI_DEVICE(0x8086, 0x293f),
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -05002991 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2992 AZX_DCAPS_BUFSIZE }, /* ICH9 */
Takashi Iwai8b0bd222011-06-10 14:56:26 +02002993 { PCI_DEVICE(0x8086, 0x3a3e),
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -05002994 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2995 AZX_DCAPS_BUFSIZE }, /* ICH10 */
Takashi Iwai8b0bd222011-06-10 14:56:26 +02002996 { PCI_DEVICE(0x8086, 0x3a6e),
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -05002997 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2998 AZX_DCAPS_BUFSIZE }, /* ICH10 */
Takashi Iwaib6864532010-09-15 10:17:26 +02002999 /* Generic Intel */
3000 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3001 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3002 .class_mask = 0xffffff,
Pierre-Louis Bossart2ae66c22011-08-04 10:12:56 -05003003 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
Takashi Iwai9477c582011-05-25 09:11:37 +02003004 /* ATI SB 450/600/700/800/900 */
3005 { PCI_DEVICE(0x1002, 0x437b),
3006 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3007 { PCI_DEVICE(0x1002, 0x4383),
3008 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3009 /* AMD Hudson */
3010 { PCI_DEVICE(0x1022, 0x780d),
3011 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
Takashi Iwai87218e92008-02-21 08:13:11 +01003012 /* ATI HDMI */
Takashi Iwai9477c582011-05-25 09:11:37 +02003013 { PCI_DEVICE(0x1002, 0x793b),
3014 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3015 { PCI_DEVICE(0x1002, 0x7919),
3016 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3017 { PCI_DEVICE(0x1002, 0x960f),
3018 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3019 { PCI_DEVICE(0x1002, 0x970f),
3020 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3021 { PCI_DEVICE(0x1002, 0xaa00),
3022 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3023 { PCI_DEVICE(0x1002, 0xaa08),
3024 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3025 { PCI_DEVICE(0x1002, 0xaa10),
3026 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3027 { PCI_DEVICE(0x1002, 0xaa18),
3028 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3029 { PCI_DEVICE(0x1002, 0xaa20),
3030 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3031 { PCI_DEVICE(0x1002, 0xaa28),
3032 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3033 { PCI_DEVICE(0x1002, 0xaa30),
3034 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3035 { PCI_DEVICE(0x1002, 0xaa38),
3036 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3037 { PCI_DEVICE(0x1002, 0xaa40),
3038 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3039 { PCI_DEVICE(0x1002, 0xaa48),
3040 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
Takashi Iwai87218e92008-02-21 08:13:11 +01003041 /* VIA VT8251/VT8237A */
Takashi Iwai9477c582011-05-25 09:11:37 +02003042 { PCI_DEVICE(0x1106, 0x3288),
3043 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
Takashi Iwai87218e92008-02-21 08:13:11 +01003044 /* SIS966 */
3045 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3046 /* ULI M5461 */
3047 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3048 /* NVIDIA MCP */
Takashi Iwai0c2fd1bf42009-12-18 16:41:39 +01003049 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3050 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3051 .class_mask = 0xffffff,
Takashi Iwai9477c582011-05-25 09:11:37 +02003052 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
Kailang Yangf2690022008-05-27 11:44:55 +02003053 /* Teradici */
Takashi Iwai9477c582011-05-25 09:11:37 +02003054 { PCI_DEVICE(0x6549, 0x1200),
3055 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
Takashi Iwai4e01f542009-04-16 08:53:34 +02003056 /* Creative X-Fi (CA0110-IBG) */
Takashi Iwai313f6e22009-05-18 12:40:52 +02003057#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3058 /* the following entry conflicts with snd-ctxfi driver,
3059 * as ctxfi driver mutates from HD-audio to native mode with
3060 * a special command sequence.
3061 */
Takashi Iwai4e01f542009-04-16 08:53:34 +02003062 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3063 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3064 .class_mask = 0xffffff,
Takashi Iwai9477c582011-05-25 09:11:37 +02003065 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
Takashi Iwai69f9ba92011-11-06 13:49:13 +01003066 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
Takashi Iwai313f6e22009-05-18 12:40:52 +02003067#else
3068 /* this entry seems still valid -- i.e. without emu20kx chip */
Takashi Iwai9477c582011-05-25 09:11:37 +02003069 { PCI_DEVICE(0x1102, 0x0009),
3070 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
Takashi Iwai69f9ba92011-11-06 13:49:13 +01003071 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
Takashi Iwai313f6e22009-05-18 12:40:52 +02003072#endif
Otavio Salvadore35d4b12010-09-26 23:35:06 -03003073 /* Vortex86MX */
3074 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
Bankim Bhavsar0f0714c52011-01-17 15:23:21 +01003075 /* VMware HDAudio */
3076 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
Andiry Brienza9176b672009-07-17 11:32:32 +08003077 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
Yang, Libinc4da29c2008-11-13 11:07:07 +01003078 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3079 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3080 .class_mask = 0xffffff,
Takashi Iwai9477c582011-05-25 09:11:37 +02003081 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
Andiry Brienza9176b672009-07-17 11:32:32 +08003082 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3083 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3084 .class_mask = 0xffffff,
Takashi Iwai9477c582011-05-25 09:11:37 +02003085 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
Linus Torvalds1da177e2005-04-16 15:20:36 -07003086 { 0, }
3087};
3088MODULE_DEVICE_TABLE(pci, azx_ids);
3089
3090/* pci_driver definition */
3091static struct pci_driver driver = {
Takashi Iwai3733e422011-06-10 16:20:20 +02003092 .name = KBUILD_MODNAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -07003093 .id_table = azx_ids,
3094 .probe = azx_probe,
3095 .remove = __devexit_p(azx_remove),
Takashi Iwai421a1252005-11-17 16:11:09 +01003096#ifdef CONFIG_PM
3097 .suspend = azx_suspend,
3098 .resume = azx_resume,
3099#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003100};
3101
3102static int __init alsa_card_azx_init(void)
3103{
Takashi Iwai01d25d42005-04-11 16:58:24 +02003104 return pci_register_driver(&driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003105}
3106
3107static void __exit alsa_card_azx_exit(void)
3108{
3109 pci_unregister_driver(&driver);
3110}
3111
3112module_init(alsa_card_azx_init)
3113module_exit(alsa_card_azx_exit)