Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 34 | #include <linux/shmem_fs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 35 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 36 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 37 | #include <linux/pci.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 38 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 39 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
| 41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 42 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
| 43 | unsigned alignment, |
| 44 | bool map_and_fenceable); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 45 | static void i915_gem_clear_fence_reg(struct drm_device *dev, |
| 46 | struct drm_i915_fence_reg *reg); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 47 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
| 48 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 49 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 50 | struct drm_file *file); |
| 51 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 52 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 53 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 54 | struct shrink_control *sc); |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 55 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 56 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 57 | /* some bookkeeping */ |
| 58 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 59 | size_t size) |
| 60 | { |
| 61 | dev_priv->mm.object_count++; |
| 62 | dev_priv->mm.object_memory += size; |
| 63 | } |
| 64 | |
| 65 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 66 | size_t size) |
| 67 | { |
| 68 | dev_priv->mm.object_count--; |
| 69 | dev_priv->mm.object_memory -= size; |
| 70 | } |
| 71 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 72 | static int |
| 73 | i915_gem_wait_for_error(struct drm_device *dev) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 74 | { |
| 75 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 76 | struct completion *x = &dev_priv->error_completion; |
| 77 | unsigned long flags; |
| 78 | int ret; |
| 79 | |
| 80 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 81 | return 0; |
| 82 | |
| 83 | ret = wait_for_completion_interruptible(x); |
| 84 | if (ret) |
| 85 | return ret; |
| 86 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 87 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 88 | /* GPU is hung, bump the completion count to account for |
| 89 | * the token we just consumed so that we never hit zero and |
| 90 | * end up waiting upon a subsequent completion event that |
| 91 | * will never happen. |
| 92 | */ |
| 93 | spin_lock_irqsave(&x->wait.lock, flags); |
| 94 | x->done++; |
| 95 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 96 | } |
| 97 | return 0; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 98 | } |
| 99 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 100 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 101 | { |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 102 | int ret; |
| 103 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 104 | ret = i915_gem_wait_for_error(dev); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 105 | if (ret) |
| 106 | return ret; |
| 107 | |
| 108 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 109 | if (ret) |
| 110 | return ret; |
| 111 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 112 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 113 | return 0; |
| 114 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 115 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 116 | static inline bool |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 117 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 118 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 119 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 120 | } |
| 121 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 122 | int |
| 123 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 124 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 125 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 126 | struct drm_i915_gem_init *args = data; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 127 | |
| 128 | if (args->gtt_start >= args->gtt_end || |
| 129 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) |
| 130 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 131 | |
| 132 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 133 | i915_gem_init_global_gtt(dev, args->gtt_start, |
| 134 | args->gtt_end, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 135 | mutex_unlock(&dev->struct_mutex); |
| 136 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 137 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 138 | } |
| 139 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 140 | int |
| 141 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 142 | struct drm_file *file) |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 143 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 144 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 145 | struct drm_i915_gem_get_aperture *args = data; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 146 | struct drm_i915_gem_object *obj; |
| 147 | size_t pinned; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 148 | |
| 149 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 150 | return -ENODEV; |
| 151 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 152 | pinned = 0; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 153 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 154 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
| 155 | pinned += obj->gtt_space->size; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 156 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 157 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 158 | args->aper_size = dev_priv->mm.gtt_total; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 159 | args->aper_available_size = args->aper_size - pinned; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 160 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 161 | return 0; |
| 162 | } |
| 163 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 164 | static int |
| 165 | i915_gem_create(struct drm_file *file, |
| 166 | struct drm_device *dev, |
| 167 | uint64_t size, |
| 168 | uint32_t *handle_p) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 169 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 170 | struct drm_i915_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 171 | int ret; |
| 172 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 173 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 174 | size = roundup(size, PAGE_SIZE); |
Chris Wilson | 8ffc024 | 2011-09-14 14:14:28 +0200 | [diff] [blame] | 175 | if (size == 0) |
| 176 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 177 | |
| 178 | /* Allocate the new object */ |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 179 | obj = i915_gem_alloc_object(dev, size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 180 | if (obj == NULL) |
| 181 | return -ENOMEM; |
| 182 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 183 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 184 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 185 | drm_gem_object_release(&obj->base); |
| 186 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 187 | kfree(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 188 | return ret; |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 189 | } |
| 190 | |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 191 | /* drop reference from allocate - handle holds it now */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 192 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 193 | trace_i915_gem_object_create(obj); |
| 194 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 195 | *handle_p = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 196 | return 0; |
| 197 | } |
| 198 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 199 | int |
| 200 | i915_gem_dumb_create(struct drm_file *file, |
| 201 | struct drm_device *dev, |
| 202 | struct drm_mode_create_dumb *args) |
| 203 | { |
| 204 | /* have to work out size/pitch and return them */ |
Chris Wilson | ed0291f | 2011-03-19 08:21:45 +0000 | [diff] [blame] | 205 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 206 | args->size = args->pitch * args->height; |
| 207 | return i915_gem_create(file, dev, |
| 208 | args->size, &args->handle); |
| 209 | } |
| 210 | |
| 211 | int i915_gem_dumb_destroy(struct drm_file *file, |
| 212 | struct drm_device *dev, |
| 213 | uint32_t handle) |
| 214 | { |
| 215 | return drm_gem_handle_delete(file, handle); |
| 216 | } |
| 217 | |
| 218 | /** |
| 219 | * Creates a new mm object and returns a handle to it. |
| 220 | */ |
| 221 | int |
| 222 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 223 | struct drm_file *file) |
| 224 | { |
| 225 | struct drm_i915_gem_create *args = data; |
| 226 | return i915_gem_create(file, dev, |
| 227 | args->size, &args->handle); |
| 228 | } |
| 229 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 230 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 231 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 232 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 233 | |
| 234 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 235 | obj->tiling_mode != I915_TILING_NONE; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 236 | } |
| 237 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 238 | static inline int |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 239 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
| 240 | const char *gpu_vaddr, int gpu_offset, |
| 241 | int length) |
| 242 | { |
| 243 | int ret, cpu_offset = 0; |
| 244 | |
| 245 | while (length > 0) { |
| 246 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 247 | int this_length = min(cacheline_end - gpu_offset, length); |
| 248 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 249 | |
| 250 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
| 251 | gpu_vaddr + swizzled_gpu_offset, |
| 252 | this_length); |
| 253 | if (ret) |
| 254 | return ret + length; |
| 255 | |
| 256 | cpu_offset += this_length; |
| 257 | gpu_offset += this_length; |
| 258 | length -= this_length; |
| 259 | } |
| 260 | |
| 261 | return 0; |
| 262 | } |
| 263 | |
| 264 | static inline int |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 265 | __copy_from_user_swizzled(char __user *gpu_vaddr, int gpu_offset, |
| 266 | const char *cpu_vaddr, |
| 267 | int length) |
| 268 | { |
| 269 | int ret, cpu_offset = 0; |
| 270 | |
| 271 | while (length > 0) { |
| 272 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 273 | int this_length = min(cacheline_end - gpu_offset, length); |
| 274 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 275 | |
| 276 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
| 277 | cpu_vaddr + cpu_offset, |
| 278 | this_length); |
| 279 | if (ret) |
| 280 | return ret + length; |
| 281 | |
| 282 | cpu_offset += this_length; |
| 283 | gpu_offset += this_length; |
| 284 | length -= this_length; |
| 285 | } |
| 286 | |
| 287 | return 0; |
| 288 | } |
| 289 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 290 | /* Per-page copy function for the shmem pread fastpath. |
| 291 | * Flushes invalid cachelines before reading the target if |
| 292 | * needs_clflush is set. */ |
| 293 | static int |
| 294 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
| 295 | char __user *user_data, |
| 296 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 297 | { |
| 298 | char *vaddr; |
| 299 | int ret; |
| 300 | |
| 301 | if (page_do_bit17_swizzling) |
| 302 | return -EINVAL; |
| 303 | |
| 304 | vaddr = kmap_atomic(page); |
| 305 | if (needs_clflush) |
| 306 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 307 | page_length); |
| 308 | ret = __copy_to_user_inatomic(user_data, |
| 309 | vaddr + shmem_page_offset, |
| 310 | page_length); |
| 311 | kunmap_atomic(vaddr); |
| 312 | |
| 313 | return ret; |
| 314 | } |
| 315 | |
| 316 | /* Only difference to the fast-path function is that this can handle bit17 |
| 317 | * and uses non-atomic copy and kmap functions. */ |
| 318 | static int |
| 319 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
| 320 | char __user *user_data, |
| 321 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 322 | { |
| 323 | char *vaddr; |
| 324 | int ret; |
| 325 | |
| 326 | vaddr = kmap(page); |
| 327 | if (needs_clflush) |
| 328 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 329 | page_length); |
| 330 | |
| 331 | if (page_do_bit17_swizzling) |
| 332 | ret = __copy_to_user_swizzled(user_data, |
| 333 | vaddr, shmem_page_offset, |
| 334 | page_length); |
| 335 | else |
| 336 | ret = __copy_to_user(user_data, |
| 337 | vaddr + shmem_page_offset, |
| 338 | page_length); |
| 339 | kunmap(page); |
| 340 | |
| 341 | return ret; |
| 342 | } |
| 343 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 344 | static int |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 345 | i915_gem_shmem_pread(struct drm_device *dev, |
| 346 | struct drm_i915_gem_object *obj, |
| 347 | struct drm_i915_gem_pread *args, |
| 348 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 349 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 350 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 351 | char __user *user_data; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 352 | ssize_t remain; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 353 | loff_t offset; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 354 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 355 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 356 | int hit_slowpath = 0; |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 357 | int prefaulted = 0; |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 358 | int needs_clflush = 0; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 359 | int release_page; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 360 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 361 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 362 | remain = args->size; |
| 363 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 364 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 365 | |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 366 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
| 367 | /* If we're not in the cpu read domain, set ourself into the gtt |
| 368 | * read domain and manually flush cachelines (if required). This |
| 369 | * optimizes for the case when the gpu will dirty the data |
| 370 | * anyway again before the next pread happens. */ |
| 371 | if (obj->cache_level == I915_CACHE_NONE) |
| 372 | needs_clflush = 1; |
| 373 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
| 374 | if (ret) |
| 375 | return ret; |
| 376 | } |
| 377 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 378 | offset = args->offset; |
| 379 | |
| 380 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 381 | struct page *page; |
| 382 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 383 | /* Operation in this page |
| 384 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 385 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 386 | * page_length = bytes to copy for this page |
| 387 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 388 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 389 | page_length = remain; |
| 390 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 391 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 392 | |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 393 | if (obj->pages) { |
| 394 | page = obj->pages[offset >> PAGE_SHIFT]; |
| 395 | release_page = 0; |
| 396 | } else { |
| 397 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
| 398 | if (IS_ERR(page)) { |
| 399 | ret = PTR_ERR(page); |
| 400 | goto out; |
| 401 | } |
| 402 | release_page = 1; |
Jesper Juhl | b65552f | 2011-06-12 20:53:44 +0000 | [diff] [blame] | 403 | } |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 404 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 405 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 406 | (page_to_phys(page) & (1 << 17)) != 0; |
| 407 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 408 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
| 409 | user_data, page_do_bit17_swizzling, |
| 410 | needs_clflush); |
| 411 | if (ret == 0) |
| 412 | goto next_page; |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 413 | |
| 414 | hit_slowpath = 1; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 415 | page_cache_get(page); |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 416 | mutex_unlock(&dev->struct_mutex); |
| 417 | |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 418 | if (!prefaulted) { |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame^] | 419 | ret = fault_in_multipages_writeable(user_data, remain); |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 420 | /* Userspace is tricking us, but we've already clobbered |
| 421 | * its pages with the prefault and promised to write the |
| 422 | * data up to the first fault. Hence ignore any errors |
| 423 | * and just continue. */ |
| 424 | (void)ret; |
| 425 | prefaulted = 1; |
| 426 | } |
| 427 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 428 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
| 429 | user_data, page_do_bit17_swizzling, |
| 430 | needs_clflush); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 431 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 432 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 433 | page_cache_release(page); |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 434 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 435 | mark_page_accessed(page); |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 436 | if (release_page) |
| 437 | page_cache_release(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 438 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 439 | if (ret) { |
| 440 | ret = -EFAULT; |
| 441 | goto out; |
| 442 | } |
| 443 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 444 | remain -= page_length; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 445 | user_data += page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 446 | offset += page_length; |
| 447 | } |
| 448 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 449 | out: |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 450 | if (hit_slowpath) { |
| 451 | /* Fixup: Kill any reinstated backing storage pages */ |
| 452 | if (obj->madv == __I915_MADV_PURGED) |
| 453 | i915_gem_object_truncate(obj); |
| 454 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 455 | |
| 456 | return ret; |
| 457 | } |
| 458 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 459 | /** |
| 460 | * Reads data from the object referenced by handle. |
| 461 | * |
| 462 | * On error, the contents of *data are undefined. |
| 463 | */ |
| 464 | int |
| 465 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 466 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 467 | { |
| 468 | struct drm_i915_gem_pread *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 469 | struct drm_i915_gem_object *obj; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 470 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 471 | |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 472 | if (args->size == 0) |
| 473 | return 0; |
| 474 | |
| 475 | if (!access_ok(VERIFY_WRITE, |
| 476 | (char __user *)(uintptr_t)args->data_ptr, |
| 477 | args->size)) |
| 478 | return -EFAULT; |
| 479 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 480 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 481 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 482 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 483 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 484 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 485 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 486 | ret = -ENOENT; |
| 487 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 488 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 489 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 490 | /* Bounds check source. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 491 | if (args->offset > obj->base.size || |
| 492 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 493 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 494 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 495 | } |
| 496 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 497 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
| 498 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 499 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 500 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 501 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 502 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 503 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 504 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 505 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 506 | } |
| 507 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 508 | /* This is the fast write path which cannot handle |
| 509 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 510 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 511 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 512 | static inline int |
| 513 | fast_user_write(struct io_mapping *mapping, |
| 514 | loff_t page_base, int page_offset, |
| 515 | char __user *user_data, |
| 516 | int length) |
| 517 | { |
| 518 | char *vaddr_atomic; |
| 519 | unsigned long unwritten; |
| 520 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 521 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 522 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
| 523 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 524 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 525 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 526 | } |
| 527 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 528 | /** |
| 529 | * This is the fast pwrite path, where we copy the data directly from the |
| 530 | * user into the GTT, uncached. |
| 531 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 532 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 533 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 534 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 535 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 536 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 537 | { |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 538 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 539 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 540 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 541 | char __user *user_data; |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 542 | int page_offset, page_length, ret; |
| 543 | |
| 544 | ret = i915_gem_object_pin(obj, 0, true); |
| 545 | if (ret) |
| 546 | goto out; |
| 547 | |
| 548 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 549 | if (ret) |
| 550 | goto out_unpin; |
| 551 | |
| 552 | ret = i915_gem_object_put_fence(obj); |
| 553 | if (ret) |
| 554 | goto out_unpin; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 555 | |
| 556 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 557 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 558 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 559 | offset = obj->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 560 | |
| 561 | while (remain > 0) { |
| 562 | /* Operation in this page |
| 563 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 564 | * page_base = page offset within aperture |
| 565 | * page_offset = offset within page |
| 566 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 567 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 568 | page_base = offset & PAGE_MASK; |
| 569 | page_offset = offset_in_page(offset); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 570 | page_length = remain; |
| 571 | if ((page_offset + remain) > PAGE_SIZE) |
| 572 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 573 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 574 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 575 | * source page isn't available. Return the error and we'll |
| 576 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 577 | */ |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 578 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 579 | page_offset, user_data, page_length)) { |
| 580 | ret = -EFAULT; |
| 581 | goto out_unpin; |
| 582 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 583 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 584 | remain -= page_length; |
| 585 | user_data += page_length; |
| 586 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 587 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 588 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 589 | out_unpin: |
| 590 | i915_gem_object_unpin(obj); |
| 591 | out: |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 592 | return ret; |
| 593 | } |
| 594 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 595 | /* Per-page copy function for the shmem pwrite fastpath. |
| 596 | * Flushes invalid cachelines before writing to the target if |
| 597 | * needs_clflush_before is set and flushes out any written cachelines after |
| 598 | * writing if needs_clflush is set. */ |
| 599 | static int |
| 600 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
| 601 | char __user *user_data, |
| 602 | bool page_do_bit17_swizzling, |
| 603 | bool needs_clflush_before, |
| 604 | bool needs_clflush_after) |
| 605 | { |
| 606 | char *vaddr; |
| 607 | int ret; |
| 608 | |
| 609 | if (page_do_bit17_swizzling) |
| 610 | return -EINVAL; |
| 611 | |
| 612 | vaddr = kmap_atomic(page); |
| 613 | if (needs_clflush_before) |
| 614 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 615 | page_length); |
| 616 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, |
| 617 | user_data, |
| 618 | page_length); |
| 619 | if (needs_clflush_after) |
| 620 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 621 | page_length); |
| 622 | kunmap_atomic(vaddr); |
| 623 | |
| 624 | return ret; |
| 625 | } |
| 626 | |
| 627 | /* Only difference to the fast-path function is that this can handle bit17 |
| 628 | * and uses non-atomic copy and kmap functions. */ |
| 629 | static int |
| 630 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
| 631 | char __user *user_data, |
| 632 | bool page_do_bit17_swizzling, |
| 633 | bool needs_clflush_before, |
| 634 | bool needs_clflush_after) |
| 635 | { |
| 636 | char *vaddr; |
| 637 | int ret; |
| 638 | |
| 639 | vaddr = kmap(page); |
| 640 | if (needs_clflush_before) |
| 641 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 642 | page_length); |
| 643 | if (page_do_bit17_swizzling) |
| 644 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
| 645 | user_data, |
| 646 | page_length); |
| 647 | else |
| 648 | ret = __copy_from_user(vaddr + shmem_page_offset, |
| 649 | user_data, |
| 650 | page_length); |
| 651 | if (needs_clflush_after) |
| 652 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 653 | page_length); |
| 654 | kunmap(page); |
| 655 | |
| 656 | return ret; |
| 657 | } |
| 658 | |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 659 | static int |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 660 | i915_gem_shmem_pwrite(struct drm_device *dev, |
| 661 | struct drm_i915_gem_object *obj, |
| 662 | struct drm_i915_gem_pwrite *args, |
| 663 | struct drm_file *file) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 664 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 665 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 666 | ssize_t remain; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 667 | loff_t offset; |
| 668 | char __user *user_data; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 669 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 670 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 671 | int hit_slowpath = 0; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 672 | int needs_clflush_after = 0; |
| 673 | int needs_clflush_before = 0; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 674 | int release_page; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 675 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 676 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 677 | remain = args->size; |
| 678 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 679 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 680 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 681 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 682 | /* If we're not in the cpu write domain, set ourself into the gtt |
| 683 | * write domain and manually flush cachelines (if required). This |
| 684 | * optimizes for the case when the gpu will use the data |
| 685 | * right away and we therefore have to clflush anyway. */ |
| 686 | if (obj->cache_level == I915_CACHE_NONE) |
| 687 | needs_clflush_after = 1; |
| 688 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 689 | if (ret) |
| 690 | return ret; |
| 691 | } |
| 692 | /* Same trick applies for invalidate partially written cachelines before |
| 693 | * writing. */ |
| 694 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) |
| 695 | && obj->cache_level == I915_CACHE_NONE) |
| 696 | needs_clflush_before = 1; |
| 697 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 698 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 699 | obj->dirty = 1; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 700 | |
| 701 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 702 | struct page *page; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 703 | int partial_cacheline_write; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 704 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 705 | /* Operation in this page |
| 706 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 707 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 708 | * page_length = bytes to copy for this page |
| 709 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 710 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 711 | |
| 712 | page_length = remain; |
| 713 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 714 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 715 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 716 | /* If we don't overwrite a cacheline completely we need to be |
| 717 | * careful to have up-to-date data by first clflushing. Don't |
| 718 | * overcomplicate things and flush the entire patch. */ |
| 719 | partial_cacheline_write = needs_clflush_before && |
| 720 | ((shmem_page_offset | page_length) |
| 721 | & (boot_cpu_data.x86_clflush_size - 1)); |
| 722 | |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 723 | if (obj->pages) { |
| 724 | page = obj->pages[offset >> PAGE_SHIFT]; |
| 725 | release_page = 0; |
| 726 | } else { |
| 727 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
| 728 | if (IS_ERR(page)) { |
| 729 | ret = PTR_ERR(page); |
| 730 | goto out; |
| 731 | } |
| 732 | release_page = 1; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 733 | } |
| 734 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 735 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 736 | (page_to_phys(page) & (1 << 17)) != 0; |
| 737 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 738 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
| 739 | user_data, page_do_bit17_swizzling, |
| 740 | partial_cacheline_write, |
| 741 | needs_clflush_after); |
| 742 | if (ret == 0) |
| 743 | goto next_page; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 744 | |
| 745 | hit_slowpath = 1; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 746 | page_cache_get(page); |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 747 | mutex_unlock(&dev->struct_mutex); |
| 748 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 749 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
| 750 | user_data, page_do_bit17_swizzling, |
| 751 | partial_cacheline_write, |
| 752 | needs_clflush_after); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 753 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 754 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 755 | page_cache_release(page); |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 756 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 757 | set_page_dirty(page); |
| 758 | mark_page_accessed(page); |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 759 | if (release_page) |
| 760 | page_cache_release(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 761 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 762 | if (ret) { |
| 763 | ret = -EFAULT; |
| 764 | goto out; |
| 765 | } |
| 766 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 767 | remain -= page_length; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 768 | user_data += page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 769 | offset += page_length; |
| 770 | } |
| 771 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 772 | out: |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 773 | if (hit_slowpath) { |
| 774 | /* Fixup: Kill any reinstated backing storage pages */ |
| 775 | if (obj->madv == __I915_MADV_PURGED) |
| 776 | i915_gem_object_truncate(obj); |
| 777 | /* and flush dirty cachelines in case the object isn't in the cpu write |
| 778 | * domain anymore. */ |
| 779 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 780 | i915_gem_clflush_object(obj); |
| 781 | intel_gtt_chipset_flush(); |
| 782 | } |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 783 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 784 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 785 | if (needs_clflush_after) |
| 786 | intel_gtt_chipset_flush(); |
| 787 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 788 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 789 | } |
| 790 | |
| 791 | /** |
| 792 | * Writes data to the object referenced by handle. |
| 793 | * |
| 794 | * On error, the contents of the buffer that were to be modified are undefined. |
| 795 | */ |
| 796 | int |
| 797 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 798 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 799 | { |
| 800 | struct drm_i915_gem_pwrite *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 801 | struct drm_i915_gem_object *obj; |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 802 | int ret; |
| 803 | |
| 804 | if (args->size == 0) |
| 805 | return 0; |
| 806 | |
| 807 | if (!access_ok(VERIFY_READ, |
| 808 | (char __user *)(uintptr_t)args->data_ptr, |
| 809 | args->size)) |
| 810 | return -EFAULT; |
| 811 | |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame^] | 812 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
| 813 | args->size); |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 814 | if (ret) |
| 815 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 816 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 817 | ret = i915_mutex_lock_interruptible(dev); |
| 818 | if (ret) |
| 819 | return ret; |
| 820 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 821 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 822 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 823 | ret = -ENOENT; |
| 824 | goto unlock; |
| 825 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 826 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 827 | /* Bounds check destination. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 828 | if (args->offset > obj->base.size || |
| 829 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 830 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 831 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 832 | } |
| 833 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 834 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
| 835 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 836 | ret = -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 837 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 838 | * it would end up going through the fenced access, and we'll get |
| 839 | * different detiling behavior between reading and writing. |
| 840 | * pread/pwrite currently are reading and writing from the CPU |
| 841 | * perspective, requiring manual detiling by the client. |
| 842 | */ |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 843 | if (obj->phys_obj) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 844 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 845 | goto out; |
| 846 | } |
| 847 | |
| 848 | if (obj->gtt_space && |
Daniel Vetter | 3ae5378 | 2012-03-25 19:47:33 +0200 | [diff] [blame] | 849 | obj->cache_level == I915_CACHE_NONE && |
Daniel Vetter | ffc6297 | 2012-03-25 19:47:38 +0200 | [diff] [blame] | 850 | obj->map_and_fenceable && |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 851 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 852 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 853 | /* Note that the gtt paths might fail with non-page-backed user |
| 854 | * pointers (e.g. gtt mappings when moving data between |
| 855 | * textures). Fallback to the shmem path in that case. */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 856 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 857 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 858 | if (ret == -EFAULT) |
| 859 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 860 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 861 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 862 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 863 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 864 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 865 | return ret; |
| 866 | } |
| 867 | |
| 868 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 869 | * Called when user space prepares to use an object with the CPU, either |
| 870 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 871 | */ |
| 872 | int |
| 873 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 874 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 875 | { |
| 876 | struct drm_i915_gem_set_domain *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 877 | struct drm_i915_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 878 | uint32_t read_domains = args->read_domains; |
| 879 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 880 | int ret; |
| 881 | |
| 882 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 883 | return -ENODEV; |
| 884 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 885 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 886 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 887 | return -EINVAL; |
| 888 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 889 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 890 | return -EINVAL; |
| 891 | |
| 892 | /* Having something in the write domain implies it's in the read |
| 893 | * domain, and only that read domain. Enforce that in the request. |
| 894 | */ |
| 895 | if (write_domain != 0 && read_domains != write_domain) |
| 896 | return -EINVAL; |
| 897 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 898 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 899 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 900 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 901 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 902 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 903 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 904 | ret = -ENOENT; |
| 905 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 906 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 907 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 908 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 909 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 910 | |
| 911 | /* Silently promote "you're not bound, there was nothing to do" |
| 912 | * to success, since the client was just asking us to |
| 913 | * make sure everything was done. |
| 914 | */ |
| 915 | if (ret == -EINVAL) |
| 916 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 917 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 918 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 919 | } |
| 920 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 921 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 922 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 923 | mutex_unlock(&dev->struct_mutex); |
| 924 | return ret; |
| 925 | } |
| 926 | |
| 927 | /** |
| 928 | * Called when user space has done writes to this buffer |
| 929 | */ |
| 930 | int |
| 931 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 932 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 933 | { |
| 934 | struct drm_i915_gem_sw_finish *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 935 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 936 | int ret = 0; |
| 937 | |
| 938 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 939 | return -ENODEV; |
| 940 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 941 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 942 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 943 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 944 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 945 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 946 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 947 | ret = -ENOENT; |
| 948 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 949 | } |
| 950 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 951 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 952 | if (obj->pin_count) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 953 | i915_gem_object_flush_cpu_write_domain(obj); |
| 954 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 955 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 956 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 957 | mutex_unlock(&dev->struct_mutex); |
| 958 | return ret; |
| 959 | } |
| 960 | |
| 961 | /** |
| 962 | * Maps the contents of an object, returning the address it is mapped |
| 963 | * into. |
| 964 | * |
| 965 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 966 | * imply a ref on the object itself. |
| 967 | */ |
| 968 | int |
| 969 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 970 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 971 | { |
| 972 | struct drm_i915_gem_mmap *args = data; |
| 973 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 974 | unsigned long addr; |
| 975 | |
| 976 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 977 | return -ENODEV; |
| 978 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 979 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 980 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 981 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 982 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 983 | down_write(¤t->mm->mmap_sem); |
| 984 | addr = do_mmap(obj->filp, 0, args->size, |
| 985 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 986 | args->offset); |
| 987 | up_write(¤t->mm->mmap_sem); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 988 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 989 | if (IS_ERR((void *)addr)) |
| 990 | return addr; |
| 991 | |
| 992 | args->addr_ptr = (uint64_t) addr; |
| 993 | |
| 994 | return 0; |
| 995 | } |
| 996 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 997 | /** |
| 998 | * i915_gem_fault - fault a page into the GTT |
| 999 | * vma: VMA in question |
| 1000 | * vmf: fault info |
| 1001 | * |
| 1002 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1003 | * from userspace. The fault handler takes care of binding the object to |
| 1004 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1005 | * only if needed based on whether the old reg is still valid or the object |
| 1006 | * is tiled) and inserting a new PTE into the faulting process. |
| 1007 | * |
| 1008 | * Note that the faulting process may involve evicting existing objects |
| 1009 | * from the GTT and/or fence registers to make room. So performance may |
| 1010 | * suffer if the GTT working set is large or there are few fence registers |
| 1011 | * left. |
| 1012 | */ |
| 1013 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1014 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1015 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1016 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1017 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1018 | pgoff_t page_offset; |
| 1019 | unsigned long pfn; |
| 1020 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1021 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1022 | |
| 1023 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1024 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1025 | PAGE_SHIFT; |
| 1026 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1027 | ret = i915_mutex_lock_interruptible(dev); |
| 1028 | if (ret) |
| 1029 | goto out; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1030 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1031 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
| 1032 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1033 | /* Now bind it into the GTT if needed */ |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 1034 | if (!obj->map_and_fenceable) { |
| 1035 | ret = i915_gem_object_unbind(obj); |
| 1036 | if (ret) |
| 1037 | goto unlock; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1038 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1039 | if (!obj->gtt_space) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1040 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1041 | if (ret) |
| 1042 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1043 | |
Eric Anholt | e92d03b | 2011-06-14 16:43:09 -0700 | [diff] [blame] | 1044 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1045 | if (ret) |
| 1046 | goto unlock; |
| 1047 | } |
Chris Wilson | 4a684a4 | 2010-10-28 14:44:08 +0100 | [diff] [blame] | 1048 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 1049 | if (!obj->has_global_gtt_mapping) |
| 1050 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
| 1051 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1052 | if (obj->tiling_mode == I915_TILING_NONE) |
| 1053 | ret = i915_gem_object_put_fence(obj); |
| 1054 | else |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1055 | ret = i915_gem_object_get_fence(obj, NULL); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1056 | if (ret) |
| 1057 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1058 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1059 | if (i915_gem_object_is_inactive(obj)) |
| 1060 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1061 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1062 | obj->fault_mappable = true; |
| 1063 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1064 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1065 | page_offset; |
| 1066 | |
| 1067 | /* Finally, remap it using the new GTT offset */ |
| 1068 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1069 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1070 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1071 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1072 | switch (ret) { |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1073 | case -EIO: |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1074 | case -EAGAIN: |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1075 | /* Give the error handler a chance to run and move the |
| 1076 | * objects off the GPU active list. Next time we service the |
| 1077 | * fault, we should be able to transition the page into the |
| 1078 | * GTT without touching the GPU (and so avoid further |
| 1079 | * EIO/EGAIN). If the GPU is wedged, then there is no issue |
| 1080 | * with coherency, just lost writes. |
| 1081 | */ |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1082 | set_need_resched(); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1083 | case 0: |
| 1084 | case -ERESTARTSYS: |
Chris Wilson | bed636a | 2011-02-11 20:31:19 +0000 | [diff] [blame] | 1085 | case -EINTR: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1086 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1087 | case -ENOMEM: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1088 | return VM_FAULT_OOM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1089 | default: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1090 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1091 | } |
| 1092 | } |
| 1093 | |
| 1094 | /** |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1095 | * i915_gem_release_mmap - remove physical page mappings |
| 1096 | * @obj: obj in question |
| 1097 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1098 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1099 | * relinquish ownership of the pages back to the system. |
| 1100 | * |
| 1101 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1102 | * object through the GTT and then lose the fence register due to |
| 1103 | * resource pressure. Similarly if the object has been moved out of the |
| 1104 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1105 | * mapping will then trigger a page fault on the next user access, allowing |
| 1106 | * fixup by i915_gem_fault(). |
| 1107 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1108 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1109 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1110 | { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1111 | if (!obj->fault_mappable) |
| 1112 | return; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1113 | |
Chris Wilson | f6e4788 | 2011-03-20 21:09:12 +0000 | [diff] [blame] | 1114 | if (obj->base.dev->dev_mapping) |
| 1115 | unmap_mapping_range(obj->base.dev->dev_mapping, |
| 1116 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, |
| 1117 | obj->base.size, 1); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1118 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1119 | obj->fault_mappable = false; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1120 | } |
| 1121 | |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1122 | static uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1123 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1124 | { |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1125 | uint32_t gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1126 | |
| 1127 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1128 | tiling_mode == I915_TILING_NONE) |
| 1129 | return size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1130 | |
| 1131 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1132 | if (INTEL_INFO(dev)->gen == 3) |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1133 | gtt_size = 1024*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1134 | else |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1135 | gtt_size = 512*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1136 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1137 | while (gtt_size < size) |
| 1138 | gtt_size <<= 1; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1139 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1140 | return gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1141 | } |
| 1142 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1143 | /** |
| 1144 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1145 | * @obj: object to check |
| 1146 | * |
| 1147 | * Return the required GTT alignment for an object, taking into account |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1148 | * potential fence register mapping. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1149 | */ |
| 1150 | static uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1151 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
| 1152 | uint32_t size, |
| 1153 | int tiling_mode) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1154 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1155 | /* |
| 1156 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1157 | * if a fence register is needed for the object. |
| 1158 | */ |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1159 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1160 | tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1161 | return 4096; |
| 1162 | |
| 1163 | /* |
| 1164 | * Previous chips need to be aligned to the size of the smallest |
| 1165 | * fence register that can contain the object. |
| 1166 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1167 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1168 | } |
| 1169 | |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1170 | /** |
| 1171 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an |
| 1172 | * unfenced object |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1173 | * @dev: the device |
| 1174 | * @size: size of the object |
| 1175 | * @tiling_mode: tiling mode of the object |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1176 | * |
| 1177 | * Return the required GTT alignment for an object, only taking into account |
| 1178 | * unfenced tiled surface requirements. |
| 1179 | */ |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 1180 | uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1181 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
| 1182 | uint32_t size, |
| 1183 | int tiling_mode) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1184 | { |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1185 | /* |
| 1186 | * Minimum alignment is 4k (GTT page size) for sane hw. |
| 1187 | */ |
| 1188 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1189 | tiling_mode == I915_TILING_NONE) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1190 | return 4096; |
| 1191 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1192 | /* Previous hardware however needs to be aligned to a power-of-two |
| 1193 | * tile height. The simplest method for determining this is to reuse |
| 1194 | * the power-of-tile object size. |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1195 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1196 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1197 | } |
| 1198 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1199 | int |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1200 | i915_gem_mmap_gtt(struct drm_file *file, |
| 1201 | struct drm_device *dev, |
| 1202 | uint32_t handle, |
| 1203 | uint64_t *offset) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1204 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1205 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1206 | struct drm_i915_gem_object *obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1207 | int ret; |
| 1208 | |
| 1209 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1210 | return -ENODEV; |
| 1211 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1212 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1213 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1214 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1215 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1216 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1217 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1218 | ret = -ENOENT; |
| 1219 | goto unlock; |
| 1220 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1221 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1222 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1223 | ret = -E2BIG; |
Eric Anholt | ff56b0b | 2011-10-31 23:16:21 -0700 | [diff] [blame] | 1224 | goto out; |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1225 | } |
| 1226 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1227 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1228 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1229 | ret = -EINVAL; |
| 1230 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1231 | } |
| 1232 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1233 | if (!obj->base.map_list.map) { |
Rob Clark | b464e9a | 2011-08-10 08:09:08 -0500 | [diff] [blame] | 1234 | ret = drm_gem_create_mmap_offset(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1235 | if (ret) |
| 1236 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1237 | } |
| 1238 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1239 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1240 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1241 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1242 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1243 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1244 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1245 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1246 | } |
| 1247 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1248 | /** |
| 1249 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1250 | * @dev: DRM device |
| 1251 | * @data: GTT mapping ioctl data |
| 1252 | * @file: GEM object info |
| 1253 | * |
| 1254 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1255 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1256 | * up so we can get faults in the handler above. |
| 1257 | * |
| 1258 | * The fault handler will take care of binding the object into the GTT |
| 1259 | * (since it may have been evicted to make room for something), allocating |
| 1260 | * a fence register, and mapping the appropriate aperture address into |
| 1261 | * userspace. |
| 1262 | */ |
| 1263 | int |
| 1264 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1265 | struct drm_file *file) |
| 1266 | { |
| 1267 | struct drm_i915_gem_mmap_gtt *args = data; |
| 1268 | |
| 1269 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1270 | return -ENODEV; |
| 1271 | |
| 1272 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
| 1273 | } |
| 1274 | |
| 1275 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1276 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1277 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1278 | gfp_t gfpmask) |
| 1279 | { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1280 | int page_count, i; |
| 1281 | struct address_space *mapping; |
| 1282 | struct inode *inode; |
| 1283 | struct page *page; |
| 1284 | |
| 1285 | /* Get the list of pages out of our struct file. They'll be pinned |
| 1286 | * at this point until we release them. |
| 1287 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1288 | page_count = obj->base.size / PAGE_SIZE; |
| 1289 | BUG_ON(obj->pages != NULL); |
| 1290 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); |
| 1291 | if (obj->pages == NULL) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1292 | return -ENOMEM; |
| 1293 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1294 | inode = obj->base.filp->f_path.dentry->d_inode; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1295 | mapping = inode->i_mapping; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 1296 | gfpmask |= mapping_gfp_mask(mapping); |
| 1297 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1298 | for (i = 0; i < page_count; i++) { |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 1299 | page = shmem_read_mapping_page_gfp(mapping, i, gfpmask); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1300 | if (IS_ERR(page)) |
| 1301 | goto err_pages; |
| 1302 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1303 | obj->pages[i] = page; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1304 | } |
| 1305 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 1306 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1307 | i915_gem_object_do_bit_17_swizzle(obj); |
| 1308 | |
| 1309 | return 0; |
| 1310 | |
| 1311 | err_pages: |
| 1312 | while (i--) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1313 | page_cache_release(obj->pages[i]); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1314 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1315 | drm_free_large(obj->pages); |
| 1316 | obj->pages = NULL; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1317 | return PTR_ERR(page); |
| 1318 | } |
| 1319 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1320 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1321 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1322 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1323 | int page_count = obj->base.size / PAGE_SIZE; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1324 | int i; |
| 1325 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1326 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1327 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 1328 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1329 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1330 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1331 | if (obj->madv == I915_MADV_DONTNEED) |
| 1332 | obj->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1333 | |
| 1334 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1335 | if (obj->dirty) |
| 1336 | set_page_dirty(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1337 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1338 | if (obj->madv == I915_MADV_WILLNEED) |
| 1339 | mark_page_accessed(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1340 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1341 | page_cache_release(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1342 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1343 | obj->dirty = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1344 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1345 | drm_free_large(obj->pages); |
| 1346 | obj->pages = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1347 | } |
| 1348 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1349 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1350 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1351 | struct intel_ring_buffer *ring, |
| 1352 | u32 seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1353 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1354 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1355 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1356 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1357 | BUG_ON(ring == NULL); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1358 | obj->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1359 | |
| 1360 | /* Add a reference if we're newly entering the active list. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1361 | if (!obj->active) { |
| 1362 | drm_gem_object_reference(&obj->base); |
| 1363 | obj->active = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1364 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1365 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1366 | /* Move from whatever list we were on to the tail of execution. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1367 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
| 1368 | list_move_tail(&obj->ring_list, &ring->active_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1369 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1370 | obj->last_rendering_seqno = seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1371 | if (obj->fenced_gpu_access) { |
| 1372 | struct drm_i915_fence_reg *reg; |
| 1373 | |
| 1374 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); |
| 1375 | |
| 1376 | obj->last_fenced_seqno = seqno; |
| 1377 | obj->last_fenced_ring = ring; |
| 1378 | |
| 1379 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
| 1380 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
| 1381 | } |
| 1382 | } |
| 1383 | |
| 1384 | static void |
| 1385 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) |
| 1386 | { |
| 1387 | list_del_init(&obj->ring_list); |
| 1388 | obj->last_rendering_seqno = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1389 | } |
| 1390 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1391 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1392 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1393 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1394 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1395 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1396 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1397 | BUG_ON(!obj->active); |
| 1398 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1399 | |
| 1400 | i915_gem_object_move_off_active(obj); |
| 1401 | } |
| 1402 | |
| 1403 | static void |
| 1404 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
| 1405 | { |
| 1406 | struct drm_device *dev = obj->base.dev; |
| 1407 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1408 | |
| 1409 | if (obj->pin_count != 0) |
| 1410 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); |
| 1411 | else |
| 1412 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
| 1413 | |
| 1414 | BUG_ON(!list_empty(&obj->gpu_write_list)); |
| 1415 | BUG_ON(!obj->active); |
| 1416 | obj->ring = NULL; |
| 1417 | |
| 1418 | i915_gem_object_move_off_active(obj); |
| 1419 | obj->fenced_gpu_access = false; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1420 | |
| 1421 | obj->active = 0; |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 1422 | obj->pending_gpu_write = false; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1423 | drm_gem_object_unreference(&obj->base); |
| 1424 | |
| 1425 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1426 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1427 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1428 | /* Immediately discard the backing storage */ |
| 1429 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1430 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1431 | { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1432 | struct inode *inode; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1433 | |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1434 | /* Our goal here is to return as much of the memory as |
| 1435 | * is possible back to the system as we are called from OOM. |
| 1436 | * To do this we must instruct the shmfs to drop all of its |
Hugh Dickins | e2377fe | 2011-06-27 16:18:19 -0700 | [diff] [blame] | 1437 | * backing pages, *now*. |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1438 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1439 | inode = obj->base.filp->f_path.dentry->d_inode; |
Hugh Dickins | e2377fe | 2011-06-27 16:18:19 -0700 | [diff] [blame] | 1440 | shmem_truncate_range(inode, 0, (loff_t)-1); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1441 | |
Chris Wilson | a14917e | 2012-02-24 21:13:38 +0000 | [diff] [blame] | 1442 | if (obj->base.map_list.map) |
| 1443 | drm_gem_free_mmap_offset(&obj->base); |
| 1444 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1445 | obj->madv = __I915_MADV_PURGED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1446 | } |
| 1447 | |
| 1448 | static inline int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1449 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1450 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1451 | return obj->madv == I915_MADV_DONTNEED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1452 | } |
| 1453 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1454 | static void |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1455 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
| 1456 | uint32_t flush_domains) |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1457 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1458 | struct drm_i915_gem_object *obj, *next; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1459 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1460 | list_for_each_entry_safe(obj, next, |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 1461 | &ring->gpu_write_list, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1462 | gpu_write_list) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1463 | if (obj->base.write_domain & flush_domains) { |
| 1464 | uint32_t old_write_domain = obj->base.write_domain; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1465 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1466 | obj->base.write_domain = 0; |
| 1467 | list_del_init(&obj->gpu_write_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1468 | i915_gem_object_move_to_active(obj, ring, |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1469 | i915_gem_next_request_seqno(ring)); |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1470 | |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1471 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1472 | obj->base.read_domains, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1473 | old_write_domain); |
| 1474 | } |
| 1475 | } |
| 1476 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1477 | |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1478 | static u32 |
| 1479 | i915_gem_get_seqno(struct drm_device *dev) |
| 1480 | { |
| 1481 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1482 | u32 seqno = dev_priv->next_seqno; |
| 1483 | |
| 1484 | /* reserve 0 for non-seqno */ |
| 1485 | if (++dev_priv->next_seqno == 0) |
| 1486 | dev_priv->next_seqno = 1; |
| 1487 | |
| 1488 | return seqno; |
| 1489 | } |
| 1490 | |
| 1491 | u32 |
| 1492 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) |
| 1493 | { |
| 1494 | if (ring->outstanding_lazy_request == 0) |
| 1495 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); |
| 1496 | |
| 1497 | return ring->outstanding_lazy_request; |
| 1498 | } |
| 1499 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1500 | int |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1501 | i915_add_request(struct intel_ring_buffer *ring, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1502 | struct drm_file *file, |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1503 | struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1504 | { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1505 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1506 | uint32_t seqno; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1507 | u32 request_ring_position; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1508 | int was_empty; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1509 | int ret; |
| 1510 | |
| 1511 | BUG_ON(request == NULL); |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1512 | seqno = i915_gem_next_request_seqno(ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1513 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1514 | /* Record the position of the start of the request so that |
| 1515 | * should we detect the updated seqno part-way through the |
| 1516 | * GPU processing the request, we never over-estimate the |
| 1517 | * position of the head. |
| 1518 | */ |
| 1519 | request_ring_position = intel_ring_get_tail(ring); |
| 1520 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1521 | ret = ring->add_request(ring, &seqno); |
| 1522 | if (ret) |
| 1523 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1524 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1525 | trace_i915_gem_request_add(ring, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1526 | |
| 1527 | request->seqno = seqno; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1528 | request->ring = ring; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1529 | request->tail = request_ring_position; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1530 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1531 | was_empty = list_empty(&ring->request_list); |
| 1532 | list_add_tail(&request->list, &ring->request_list); |
| 1533 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1534 | if (file) { |
| 1535 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 1536 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1537 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1538 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1539 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1540 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1541 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1542 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1543 | |
Daniel Vetter | 5391d0c | 2012-01-25 14:03:57 +0100 | [diff] [blame] | 1544 | ring->outstanding_lazy_request = 0; |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1545 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1546 | if (!dev_priv->mm.suspended) { |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 1547 | if (i915_enable_hangcheck) { |
| 1548 | mod_timer(&dev_priv->hangcheck_timer, |
| 1549 | jiffies + |
| 1550 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
| 1551 | } |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1552 | if (was_empty) |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1553 | queue_delayed_work(dev_priv->wq, |
| 1554 | &dev_priv->mm.retire_work, HZ); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1555 | } |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1556 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1557 | } |
| 1558 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1559 | static inline void |
| 1560 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1561 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1562 | struct drm_i915_file_private *file_priv = request->file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1563 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1564 | if (!file_priv) |
| 1565 | return; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1566 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1567 | spin_lock(&file_priv->mm.lock); |
Herton Ronaldo Krzesinski | 09bfa51 | 2011-03-17 13:45:12 +0000 | [diff] [blame] | 1568 | if (request->file_priv) { |
| 1569 | list_del(&request->client_list); |
| 1570 | request->file_priv = NULL; |
| 1571 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1572 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1573 | } |
| 1574 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1575 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
| 1576 | struct intel_ring_buffer *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1577 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1578 | while (!list_empty(&ring->request_list)) { |
| 1579 | struct drm_i915_gem_request *request; |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1580 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1581 | request = list_first_entry(&ring->request_list, |
| 1582 | struct drm_i915_gem_request, |
| 1583 | list); |
| 1584 | |
| 1585 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1586 | i915_gem_request_remove_from_client(request); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1587 | kfree(request); |
| 1588 | } |
| 1589 | |
| 1590 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1591 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1592 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1593 | obj = list_first_entry(&ring->active_list, |
| 1594 | struct drm_i915_gem_object, |
| 1595 | ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1596 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1597 | obj->base.write_domain = 0; |
| 1598 | list_del_init(&obj->gpu_write_list); |
| 1599 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1600 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1601 | } |
| 1602 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1603 | static void i915_gem_reset_fences(struct drm_device *dev) |
| 1604 | { |
| 1605 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1606 | int i; |
| 1607 | |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 1608 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1609 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 1610 | struct drm_i915_gem_object *obj = reg->obj; |
| 1611 | |
| 1612 | if (!obj) |
| 1613 | continue; |
| 1614 | |
| 1615 | if (obj->tiling_mode) |
| 1616 | i915_gem_release_mmap(obj); |
| 1617 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1618 | reg->obj->fence_reg = I915_FENCE_REG_NONE; |
| 1619 | reg->obj->fenced_gpu_access = false; |
| 1620 | reg->obj->last_fenced_seqno = 0; |
| 1621 | reg->obj->last_fenced_ring = NULL; |
| 1622 | i915_gem_clear_fence_reg(dev, reg); |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1623 | } |
| 1624 | } |
| 1625 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1626 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1627 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1628 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1629 | struct drm_i915_gem_object *obj; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1630 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1631 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1632 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 1633 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1634 | |
| 1635 | /* Remove anything from the flushing lists. The GPU cache is likely |
| 1636 | * to be lost on reset along with the data, so simply move the |
| 1637 | * lost bo to the inactive list. |
| 1638 | */ |
| 1639 | while (!list_empty(&dev_priv->mm.flushing_list)) { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1640 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1641 | struct drm_i915_gem_object, |
| 1642 | mm_list); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1643 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1644 | obj->base.write_domain = 0; |
| 1645 | list_del_init(&obj->gpu_write_list); |
| 1646 | i915_gem_object_move_to_inactive(obj); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1647 | } |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1648 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1649 | /* Move everything out of the GPU domains to ensure we do any |
| 1650 | * necessary invalidation upon reuse. |
| 1651 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1652 | list_for_each_entry(obj, |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1653 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1654 | mm_list) |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1655 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1656 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1657 | } |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1658 | |
| 1659 | /* The fence registers are invalidated so clear them out */ |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1660 | i915_gem_reset_fences(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1661 | } |
| 1662 | |
| 1663 | /** |
| 1664 | * This function clears the request list as sequence numbers are passed. |
| 1665 | */ |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1666 | void |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1667 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1668 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1669 | uint32_t seqno; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1670 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1671 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1672 | if (list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 1673 | return; |
| 1674 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1675 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1676 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1677 | seqno = ring->get_seqno(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1678 | |
Chris Wilson | 076e2c0 | 2011-01-21 10:07:18 +0000 | [diff] [blame] | 1679 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1680 | if (seqno >= ring->sync_seqno[i]) |
| 1681 | ring->sync_seqno[i] = 0; |
| 1682 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1683 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1684 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1685 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1686 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1687 | struct drm_i915_gem_request, |
| 1688 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1689 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1690 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1691 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1692 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1693 | trace_i915_gem_request_retire(ring, request->seqno); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1694 | /* We know the GPU must have read the request to have |
| 1695 | * sent us the seqno + interrupt, so use the position |
| 1696 | * of tail of the request to update the last known position |
| 1697 | * of the GPU head. |
| 1698 | */ |
| 1699 | ring->last_retired_head = request->tail; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1700 | |
| 1701 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1702 | i915_gem_request_remove_from_client(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1703 | kfree(request); |
| 1704 | } |
| 1705 | |
| 1706 | /* Move any buffers on the active list that are no longer referenced |
| 1707 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 1708 | */ |
| 1709 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1710 | struct drm_i915_gem_object *obj; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1711 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1712 | obj = list_first_entry(&ring->active_list, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1713 | struct drm_i915_gem_object, |
| 1714 | ring_list); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1715 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1716 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1717 | break; |
| 1718 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1719 | if (obj->base.write_domain != 0) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1720 | i915_gem_object_move_to_flushing(obj); |
| 1721 | else |
| 1722 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1723 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1724 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1725 | if (unlikely(ring->trace_irq_seqno && |
| 1726 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1727 | ring->irq_put(ring); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1728 | ring->trace_irq_seqno = 0; |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1729 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1730 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1731 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1732 | } |
| 1733 | |
| 1734 | void |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1735 | i915_gem_retire_requests(struct drm_device *dev) |
| 1736 | { |
| 1737 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1738 | int i; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1739 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1740 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1741 | struct drm_i915_gem_object *obj, *next; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1742 | |
| 1743 | /* We must be careful that during unbind() we do not |
| 1744 | * accidentally infinitely recurse into retire requests. |
| 1745 | * Currently: |
| 1746 | * retire -> free -> unbind -> wait -> retire_ring |
| 1747 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1748 | list_for_each_entry_safe(obj, next, |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1749 | &dev_priv->mm.deferred_free_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1750 | mm_list) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1751 | i915_gem_free_object_tail(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1752 | } |
| 1753 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1754 | for (i = 0; i < I915_NUM_RINGS; i++) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1755 | i915_gem_retire_requests_ring(&dev_priv->ring[i]); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1756 | } |
| 1757 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 1758 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1759 | i915_gem_retire_work_handler(struct work_struct *work) |
| 1760 | { |
| 1761 | drm_i915_private_t *dev_priv; |
| 1762 | struct drm_device *dev; |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1763 | bool idle; |
| 1764 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1765 | |
| 1766 | dev_priv = container_of(work, drm_i915_private_t, |
| 1767 | mm.retire_work.work); |
| 1768 | dev = dev_priv->dev; |
| 1769 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 1770 | /* Come back later if the device is busy... */ |
| 1771 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 1772 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 1773 | return; |
| 1774 | } |
| 1775 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1776 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1777 | |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1778 | /* Send a periodic flush down the ring so we don't hold onto GEM |
| 1779 | * objects indefinitely. |
| 1780 | */ |
| 1781 | idle = true; |
| 1782 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 1783 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; |
| 1784 | |
| 1785 | if (!list_empty(&ring->gpu_write_list)) { |
| 1786 | struct drm_i915_gem_request *request; |
| 1787 | int ret; |
| 1788 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1789 | ret = i915_gem_flush_ring(ring, |
| 1790 | 0, I915_GEM_GPU_DOMAINS); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1791 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 1792 | if (ret || request == NULL || |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1793 | i915_add_request(ring, NULL, request)) |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1794 | kfree(request); |
| 1795 | } |
| 1796 | |
| 1797 | idle &= list_empty(&ring->request_list); |
| 1798 | } |
| 1799 | |
| 1800 | if (!dev_priv->mm.suspended && !idle) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1801 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1802 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1803 | mutex_unlock(&dev->struct_mutex); |
| 1804 | } |
| 1805 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1806 | /** |
| 1807 | * Waits for a sequence number to be signaled, and cleans up the |
| 1808 | * request and object lists appropriately for that event. |
| 1809 | */ |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 1810 | int |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1811 | i915_wait_request(struct intel_ring_buffer *ring, |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 1812 | uint32_t seqno, |
| 1813 | bool do_retire) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1814 | { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1815 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1816 | u32 ier; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1817 | int ret = 0; |
| 1818 | |
| 1819 | BUG_ON(seqno == 0); |
| 1820 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1821 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 1822 | struct completion *x = &dev_priv->error_completion; |
| 1823 | bool recovery_complete; |
| 1824 | unsigned long flags; |
| 1825 | |
| 1826 | /* Give the error handler a chance to run. */ |
| 1827 | spin_lock_irqsave(&x->wait.lock, flags); |
| 1828 | recovery_complete = x->done > 0; |
| 1829 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 1830 | |
| 1831 | return recovery_complete ? -EIO : -EAGAIN; |
| 1832 | } |
Ben Gamari | ffed1d0 | 2009-09-14 17:48:41 -0400 | [diff] [blame] | 1833 | |
Chris Wilson | 5d97eb6 | 2010-11-10 20:40:02 +0000 | [diff] [blame] | 1834 | if (seqno == ring->outstanding_lazy_request) { |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1835 | struct drm_i915_gem_request *request; |
| 1836 | |
| 1837 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 1838 | if (request == NULL) |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1839 | return -ENOMEM; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1840 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1841 | ret = i915_add_request(ring, NULL, request); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1842 | if (ret) { |
| 1843 | kfree(request); |
| 1844 | return ret; |
| 1845 | } |
| 1846 | |
| 1847 | seqno = request->seqno; |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1848 | } |
| 1849 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1850 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1851 | if (HAS_PCH_SPLIT(ring->dev)) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1852 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
| 1853 | else |
| 1854 | ier = I915_READ(IER); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1855 | if (!ier) { |
| 1856 | DRM_ERROR("something (likely vbetool) disabled " |
| 1857 | "interrupts, re-enabling\n"); |
Chris Wilson | f01c22f | 2011-06-28 11:48:51 +0100 | [diff] [blame] | 1858 | ring->dev->driver->irq_preinstall(ring->dev); |
| 1859 | ring->dev->driver->irq_postinstall(ring->dev); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1860 | } |
| 1861 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1862 | trace_i915_gem_request_wait_begin(ring, seqno); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1863 | |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 1864 | ring->waiting_seqno = seqno; |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1865 | if (ring->irq_get(ring)) { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1866 | if (dev_priv->mm.interruptible) |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1867 | ret = wait_event_interruptible(ring->irq_queue, |
| 1868 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
| 1869 | || atomic_read(&dev_priv->mm.wedged)); |
| 1870 | else |
| 1871 | wait_event(ring->irq_queue, |
| 1872 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
| 1873 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1874 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1875 | ring->irq_put(ring); |
Eric Anholt | e959b5d | 2011-12-22 14:55:01 -0800 | [diff] [blame] | 1876 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
| 1877 | seqno) || |
| 1878 | atomic_read(&dev_priv->mm.wedged), 3000)) |
Chris Wilson | b5ba177 | 2010-12-14 12:17:15 +0000 | [diff] [blame] | 1879 | ret = -EBUSY; |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 1880 | ring->waiting_seqno = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1881 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1882 | trace_i915_gem_request_wait_end(ring, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1883 | } |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1884 | if (atomic_read(&dev_priv->mm.wedged)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 1885 | ret = -EAGAIN; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1886 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1887 | /* Directly dispatch request retiring. While we have the work queue |
| 1888 | * to handle this, the waiter on a request often wants an associated |
| 1889 | * buffer to have made it to the inactive list, and we would need |
| 1890 | * a separate wait queue to handle that. |
| 1891 | */ |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 1892 | if (ret == 0 && do_retire) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1893 | i915_gem_retire_requests_ring(ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1894 | |
| 1895 | return ret; |
| 1896 | } |
| 1897 | |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1898 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1899 | * Ensures that all rendering to the object has completed and the object is |
| 1900 | * safe to unbind from the GTT or access from the CPU. |
| 1901 | */ |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1902 | int |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1903 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1904 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1905 | int ret; |
| 1906 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1907 | /* This function only exists to support waiting for existing rendering, |
| 1908 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1909 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1910 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1911 | |
| 1912 | /* If there is rendering queued on the buffer being evicted, wait for |
| 1913 | * it. |
| 1914 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1915 | if (obj->active) { |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 1916 | ret = i915_wait_request(obj->ring, obj->last_rendering_seqno, |
| 1917 | true); |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 1918 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1919 | return ret; |
| 1920 | } |
| 1921 | |
| 1922 | return 0; |
| 1923 | } |
| 1924 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 1925 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
| 1926 | { |
| 1927 | u32 old_write_domain, old_read_domains; |
| 1928 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 1929 | /* Act a barrier for all accesses through the GTT */ |
| 1930 | mb(); |
| 1931 | |
| 1932 | /* Force a pagefault for domain tracking on next user access */ |
| 1933 | i915_gem_release_mmap(obj); |
| 1934 | |
Keith Packard | b97c3d9 | 2011-06-24 21:02:59 -0700 | [diff] [blame] | 1935 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 1936 | return; |
| 1937 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 1938 | old_read_domains = obj->base.read_domains; |
| 1939 | old_write_domain = obj->base.write_domain; |
| 1940 | |
| 1941 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
| 1942 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
| 1943 | |
| 1944 | trace_i915_gem_object_change_domain(obj, |
| 1945 | old_read_domains, |
| 1946 | old_write_domain); |
| 1947 | } |
| 1948 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1949 | /** |
| 1950 | * Unbinds an object from the GTT aperture. |
| 1951 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1952 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1953 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1954 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 1955 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1956 | int ret = 0; |
| 1957 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1958 | if (obj->gtt_space == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1959 | return 0; |
| 1960 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1961 | if (obj->pin_count != 0) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1962 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
| 1963 | return -EINVAL; |
| 1964 | } |
| 1965 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 1966 | ret = i915_gem_object_finish_gpu(obj); |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 1967 | if (ret == -ERESTARTSYS) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1968 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 1969 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 1970 | * should be safe and we need to cleanup or else we might |
| 1971 | * cause memory corruption through use-after-free. |
| 1972 | */ |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 1973 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 1974 | i915_gem_object_finish_gtt(obj); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 1975 | |
| 1976 | /* Move the object to the CPU domain to ensure that |
| 1977 | * any possible CPU writes while it's not in the GTT |
| 1978 | * are flushed when we go to remap it. |
| 1979 | */ |
| 1980 | if (ret == 0) |
| 1981 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 1982 | if (ret == -ERESTARTSYS) |
| 1983 | return ret; |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 1984 | if (ret) { |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 1985 | /* In the event of a disaster, abandon all caches and |
| 1986 | * hope for the best. |
| 1987 | */ |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 1988 | i915_gem_clflush_object(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1989 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 1990 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1991 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 1992 | /* release the fence reg _after_ flushing */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1993 | ret = i915_gem_object_put_fence(obj); |
| 1994 | if (ret == -ERESTARTSYS) |
| 1995 | return ret; |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 1996 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1997 | trace_i915_gem_object_unbind(obj); |
| 1998 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 1999 | if (obj->has_global_gtt_mapping) |
| 2000 | i915_gem_gtt_unbind_object(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2001 | if (obj->has_aliasing_ppgtt_mapping) { |
| 2002 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); |
| 2003 | obj->has_aliasing_ppgtt_mapping = 0; |
| 2004 | } |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2005 | i915_gem_gtt_finish_object(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2006 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2007 | i915_gem_object_put_pages_gtt(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2008 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2009 | list_del_init(&obj->gtt_list); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2010 | list_del_init(&obj->mm_list); |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2011 | /* Avoid an unnecessary call to unbind on rebind. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2012 | obj->map_and_fenceable = true; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2013 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2014 | drm_mm_put_block(obj->gtt_space); |
| 2015 | obj->gtt_space = NULL; |
| 2016 | obj->gtt_offset = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2017 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2018 | if (i915_gem_object_is_purgeable(obj)) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2019 | i915_gem_object_truncate(obj); |
| 2020 | |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2021 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2022 | } |
| 2023 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2024 | int |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2025 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2026 | uint32_t invalidate_domains, |
| 2027 | uint32_t flush_domains) |
| 2028 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2029 | int ret; |
| 2030 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 2031 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
| 2032 | return 0; |
| 2033 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2034 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
| 2035 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2036 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
| 2037 | if (ret) |
| 2038 | return ret; |
| 2039 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 2040 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
| 2041 | i915_gem_process_flushing_list(ring, flush_domains); |
| 2042 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2043 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2044 | } |
| 2045 | |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 2046 | static int i915_ring_idle(struct intel_ring_buffer *ring, bool do_retire) |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2047 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2048 | int ret; |
| 2049 | |
Chris Wilson | 395b70b | 2010-10-28 21:28:46 +0100 | [diff] [blame] | 2050 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 2051 | return 0; |
| 2052 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2053 | if (!list_empty(&ring->gpu_write_list)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2054 | ret = i915_gem_flush_ring(ring, |
Chris Wilson | 0ac74c6 | 2010-12-06 14:36:02 +0000 | [diff] [blame] | 2055 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2056 | if (ret) |
| 2057 | return ret; |
| 2058 | } |
| 2059 | |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 2060 | return i915_wait_request(ring, i915_gem_next_request_seqno(ring), |
| 2061 | do_retire); |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2062 | } |
| 2063 | |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 2064 | int i915_gpu_idle(struct drm_device *dev, bool do_retire) |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2065 | { |
| 2066 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2067 | int ret, i; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2068 | |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2069 | /* Flush everything onto the inactive list. */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2070 | for (i = 0; i < I915_NUM_RINGS; i++) { |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 2071 | ret = i915_ring_idle(&dev_priv->ring[i], do_retire); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2072 | if (ret) |
| 2073 | return ret; |
| 2074 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2075 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2076 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2077 | } |
| 2078 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2079 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2080 | struct intel_ring_buffer *pipelined) |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2081 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2082 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2083 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2084 | u32 size = obj->gtt_space->size; |
| 2085 | int regnum = obj->fence_reg; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2086 | uint64_t val; |
| 2087 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2088 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2089 | 0xfffff000) << 32; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2090 | val |= obj->gtt_offset & 0xfffff000; |
| 2091 | val |= (uint64_t)((obj->stride / 128) - 1) << |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2092 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 2093 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2094 | if (obj->tiling_mode == I915_TILING_Y) |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2095 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2096 | val |= I965_FENCE_REG_VALID; |
| 2097 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2098 | if (pipelined) { |
| 2099 | int ret = intel_ring_begin(pipelined, 6); |
| 2100 | if (ret) |
| 2101 | return ret; |
| 2102 | |
| 2103 | intel_ring_emit(pipelined, MI_NOOP); |
| 2104 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); |
| 2105 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); |
| 2106 | intel_ring_emit(pipelined, (u32)val); |
| 2107 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); |
| 2108 | intel_ring_emit(pipelined, (u32)(val >> 32)); |
| 2109 | intel_ring_advance(pipelined); |
| 2110 | } else |
| 2111 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); |
| 2112 | |
| 2113 | return 0; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2114 | } |
| 2115 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2116 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2117 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2118 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2119 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2120 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2121 | u32 size = obj->gtt_space->size; |
| 2122 | int regnum = obj->fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2123 | uint64_t val; |
| 2124 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2125 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2126 | 0xfffff000) << 32; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2127 | val |= obj->gtt_offset & 0xfffff000; |
| 2128 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2129 | if (obj->tiling_mode == I915_TILING_Y) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2130 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2131 | val |= I965_FENCE_REG_VALID; |
| 2132 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2133 | if (pipelined) { |
| 2134 | int ret = intel_ring_begin(pipelined, 6); |
| 2135 | if (ret) |
| 2136 | return ret; |
| 2137 | |
| 2138 | intel_ring_emit(pipelined, MI_NOOP); |
| 2139 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); |
| 2140 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); |
| 2141 | intel_ring_emit(pipelined, (u32)val); |
| 2142 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); |
| 2143 | intel_ring_emit(pipelined, (u32)(val >> 32)); |
| 2144 | intel_ring_advance(pipelined); |
| 2145 | } else |
| 2146 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); |
| 2147 | |
| 2148 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2149 | } |
| 2150 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2151 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2152 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2153 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2154 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2155 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2156 | u32 size = obj->gtt_space->size; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2157 | u32 fence_reg, val, pitch_val; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2158 | int tile_width; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2159 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2160 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2161 | (size & -size) != size || |
| 2162 | (obj->gtt_offset & (size - 1)), |
| 2163 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
| 2164 | obj->gtt_offset, obj->map_and_fenceable, size)) |
| 2165 | return -EINVAL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2166 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2167 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2168 | tile_width = 128; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2169 | else |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2170 | tile_width = 512; |
| 2171 | |
| 2172 | /* Note: pitch better be a power of two tile widths */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2173 | pitch_val = obj->stride / tile_width; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2174 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2175 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2176 | val = obj->gtt_offset; |
| 2177 | if (obj->tiling_mode == I915_TILING_Y) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2178 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2179 | val |= I915_FENCE_SIZE_BITS(size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2180 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2181 | val |= I830_FENCE_REG_VALID; |
| 2182 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2183 | fence_reg = obj->fence_reg; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2184 | if (fence_reg < 8) |
| 2185 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2186 | else |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2187 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2188 | |
| 2189 | if (pipelined) { |
| 2190 | int ret = intel_ring_begin(pipelined, 4); |
| 2191 | if (ret) |
| 2192 | return ret; |
| 2193 | |
| 2194 | intel_ring_emit(pipelined, MI_NOOP); |
| 2195 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); |
| 2196 | intel_ring_emit(pipelined, fence_reg); |
| 2197 | intel_ring_emit(pipelined, val); |
| 2198 | intel_ring_advance(pipelined); |
| 2199 | } else |
| 2200 | I915_WRITE(fence_reg, val); |
| 2201 | |
| 2202 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2203 | } |
| 2204 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2205 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2206 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2207 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2208 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2209 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2210 | u32 size = obj->gtt_space->size; |
| 2211 | int regnum = obj->fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2212 | uint32_t val; |
| 2213 | uint32_t pitch_val; |
| 2214 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2215 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
| 2216 | (size & -size) != size || |
| 2217 | (obj->gtt_offset & (size - 1)), |
| 2218 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", |
| 2219 | obj->gtt_offset, size)) |
| 2220 | return -EINVAL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2221 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2222 | pitch_val = obj->stride / 128; |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2223 | pitch_val = ffs(pitch_val) - 1; |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2224 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2225 | val = obj->gtt_offset; |
| 2226 | if (obj->tiling_mode == I915_TILING_Y) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2227 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2228 | val |= I830_FENCE_SIZE_BITS(size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2229 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2230 | val |= I830_FENCE_REG_VALID; |
| 2231 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2232 | if (pipelined) { |
| 2233 | int ret = intel_ring_begin(pipelined, 4); |
| 2234 | if (ret) |
| 2235 | return ret; |
| 2236 | |
| 2237 | intel_ring_emit(pipelined, MI_NOOP); |
| 2238 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); |
| 2239 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); |
| 2240 | intel_ring_emit(pipelined, val); |
| 2241 | intel_ring_advance(pipelined); |
| 2242 | } else |
| 2243 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); |
| 2244 | |
| 2245 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2246 | } |
| 2247 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2248 | static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 2249 | { |
| 2250 | return i915_seqno_passed(ring->get_seqno(ring), seqno); |
| 2251 | } |
| 2252 | |
| 2253 | static int |
| 2254 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj, |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2255 | struct intel_ring_buffer *pipelined) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2256 | { |
| 2257 | int ret; |
| 2258 | |
| 2259 | if (obj->fenced_gpu_access) { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2260 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2261 | ret = i915_gem_flush_ring(obj->last_fenced_ring, |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2262 | 0, obj->base.write_domain); |
| 2263 | if (ret) |
| 2264 | return ret; |
| 2265 | } |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2266 | |
| 2267 | obj->fenced_gpu_access = false; |
| 2268 | } |
| 2269 | |
| 2270 | if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) { |
| 2271 | if (!ring_passed_seqno(obj->last_fenced_ring, |
| 2272 | obj->last_fenced_seqno)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2273 | ret = i915_wait_request(obj->last_fenced_ring, |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 2274 | obj->last_fenced_seqno, |
| 2275 | true); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2276 | if (ret) |
| 2277 | return ret; |
| 2278 | } |
| 2279 | |
| 2280 | obj->last_fenced_seqno = 0; |
| 2281 | obj->last_fenced_ring = NULL; |
| 2282 | } |
| 2283 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2284 | /* Ensure that all CPU reads are completed before installing a fence |
| 2285 | * and all writes before removing the fence. |
| 2286 | */ |
| 2287 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) |
| 2288 | mb(); |
| 2289 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2290 | return 0; |
| 2291 | } |
| 2292 | |
| 2293 | int |
| 2294 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
| 2295 | { |
| 2296 | int ret; |
| 2297 | |
| 2298 | if (obj->tiling_mode) |
| 2299 | i915_gem_release_mmap(obj); |
| 2300 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2301 | ret = i915_gem_object_flush_fence(obj, NULL); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2302 | if (ret) |
| 2303 | return ret; |
| 2304 | |
| 2305 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2306 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2307 | |
| 2308 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2309 | i915_gem_clear_fence_reg(obj->base.dev, |
| 2310 | &dev_priv->fence_regs[obj->fence_reg]); |
| 2311 | |
| 2312 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 2313 | } |
| 2314 | |
| 2315 | return 0; |
| 2316 | } |
| 2317 | |
| 2318 | static struct drm_i915_fence_reg * |
| 2319 | i915_find_fence_reg(struct drm_device *dev, |
| 2320 | struct intel_ring_buffer *pipelined) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2321 | { |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2322 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2323 | struct drm_i915_fence_reg *reg, *first, *avail; |
| 2324 | int i; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2325 | |
| 2326 | /* First try to find a free reg */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2327 | avail = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2328 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2329 | reg = &dev_priv->fence_regs[i]; |
| 2330 | if (!reg->obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2331 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2332 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2333 | if (!reg->pin_count) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2334 | avail = reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2335 | } |
| 2336 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2337 | if (avail == NULL) |
| 2338 | return NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2339 | |
| 2340 | /* None available, try to steal one or wait for a user to finish */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2341 | avail = first = NULL; |
| 2342 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2343 | if (reg->pin_count) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2344 | continue; |
| 2345 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2346 | if (first == NULL) |
| 2347 | first = reg; |
| 2348 | |
| 2349 | if (!pipelined || |
| 2350 | !reg->obj->last_fenced_ring || |
| 2351 | reg->obj->last_fenced_ring == pipelined) { |
| 2352 | avail = reg; |
| 2353 | break; |
| 2354 | } |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2355 | } |
| 2356 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2357 | if (avail == NULL) |
| 2358 | avail = first; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2359 | |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2360 | return avail; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2361 | } |
| 2362 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2363 | /** |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2364 | * i915_gem_object_get_fence - set up a fence reg for an object |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2365 | * @obj: object to map through a fence reg |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2366 | * @pipelined: ring on which to queue the change, or NULL for CPU access |
| 2367 | * @interruptible: must we wait uninterruptibly for the register to retire? |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2368 | * |
| 2369 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2370 | * to them without having to worry about swizzling if the object is tiled. |
| 2371 | * |
| 2372 | * This function walks the fence regs looking for a free one for @obj, |
| 2373 | * stealing one if it can't find any. |
| 2374 | * |
| 2375 | * It then sets up the reg based on the object's properties: address, pitch |
| 2376 | * and tiling format. |
| 2377 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2378 | int |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2379 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2380 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2381 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2382 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2383 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2384 | struct drm_i915_fence_reg *reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2385 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2386 | |
Chris Wilson | 6bda10d | 2010-12-05 21:04:18 +0000 | [diff] [blame] | 2387 | /* XXX disable pipelining. There are bugs. Shocking. */ |
| 2388 | pipelined = NULL; |
| 2389 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2390 | /* Just update our place in the LRU if our fence is getting reused. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2391 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2392 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2393 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2394 | |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 2395 | if (obj->tiling_changed) { |
| 2396 | ret = i915_gem_object_flush_fence(obj, pipelined); |
| 2397 | if (ret) |
| 2398 | return ret; |
| 2399 | |
| 2400 | if (!obj->fenced_gpu_access && !obj->last_fenced_seqno) |
| 2401 | pipelined = NULL; |
| 2402 | |
| 2403 | if (pipelined) { |
| 2404 | reg->setup_seqno = |
| 2405 | i915_gem_next_request_seqno(pipelined); |
| 2406 | obj->last_fenced_seqno = reg->setup_seqno; |
| 2407 | obj->last_fenced_ring = pipelined; |
| 2408 | } |
| 2409 | |
| 2410 | goto update; |
| 2411 | } |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2412 | |
| 2413 | if (!pipelined) { |
| 2414 | if (reg->setup_seqno) { |
| 2415 | if (!ring_passed_seqno(obj->last_fenced_ring, |
| 2416 | reg->setup_seqno)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2417 | ret = i915_wait_request(obj->last_fenced_ring, |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 2418 | reg->setup_seqno, |
| 2419 | true); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2420 | if (ret) |
| 2421 | return ret; |
| 2422 | } |
| 2423 | |
| 2424 | reg->setup_seqno = 0; |
| 2425 | } |
| 2426 | } else if (obj->last_fenced_ring && |
| 2427 | obj->last_fenced_ring != pipelined) { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2428 | ret = i915_gem_object_flush_fence(obj, pipelined); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2429 | if (ret) |
| 2430 | return ret; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2431 | } |
| 2432 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2433 | return 0; |
| 2434 | } |
| 2435 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2436 | reg = i915_find_fence_reg(dev, pipelined); |
| 2437 | if (reg == NULL) |
Daniel Vetter | 39965b3 | 2011-12-14 13:57:09 +0100 | [diff] [blame] | 2438 | return -EDEADLK; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2439 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2440 | ret = i915_gem_object_flush_fence(obj, pipelined); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2441 | if (ret) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2442 | return ret; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2443 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2444 | if (reg->obj) { |
| 2445 | struct drm_i915_gem_object *old = reg->obj; |
| 2446 | |
| 2447 | drm_gem_object_reference(&old->base); |
| 2448 | |
| 2449 | if (old->tiling_mode) |
| 2450 | i915_gem_release_mmap(old); |
| 2451 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2452 | ret = i915_gem_object_flush_fence(old, pipelined); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2453 | if (ret) { |
| 2454 | drm_gem_object_unreference(&old->base); |
| 2455 | return ret; |
| 2456 | } |
| 2457 | |
| 2458 | if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0) |
| 2459 | pipelined = NULL; |
| 2460 | |
| 2461 | old->fence_reg = I915_FENCE_REG_NONE; |
| 2462 | old->last_fenced_ring = pipelined; |
| 2463 | old->last_fenced_seqno = |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2464 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2465 | |
| 2466 | drm_gem_object_unreference(&old->base); |
| 2467 | } else if (obj->last_fenced_seqno == 0) |
| 2468 | pipelined = NULL; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2469 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2470 | reg->obj = obj; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2471 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
| 2472 | obj->fence_reg = reg - dev_priv->fence_regs; |
| 2473 | obj->last_fenced_ring = pipelined; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2474 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2475 | reg->setup_seqno = |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2476 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2477 | obj->last_fenced_seqno = reg->setup_seqno; |
| 2478 | |
| 2479 | update: |
| 2480 | obj->tiling_changed = false; |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2481 | switch (INTEL_INFO(dev)->gen) { |
Eric Anholt | 25aebfc3 | 2011-05-06 13:55:53 -0700 | [diff] [blame] | 2482 | case 7: |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2483 | case 6: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2484 | ret = sandybridge_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2485 | break; |
| 2486 | case 5: |
| 2487 | case 4: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2488 | ret = i965_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2489 | break; |
| 2490 | case 3: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2491 | ret = i915_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2492 | break; |
| 2493 | case 2: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2494 | ret = i830_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2495 | break; |
| 2496 | } |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2497 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2498 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2499 | } |
| 2500 | |
| 2501 | /** |
| 2502 | * i915_gem_clear_fence_reg - clear out fence register info |
| 2503 | * @obj: object to clear |
| 2504 | * |
| 2505 | * Zeroes out the fence register itself and clears out the associated |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2506 | * data structures in dev_priv and obj. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2507 | */ |
| 2508 | static void |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2509 | i915_gem_clear_fence_reg(struct drm_device *dev, |
| 2510 | struct drm_i915_fence_reg *reg) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2511 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2512 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2513 | uint32_t fence_reg = reg - dev_priv->fence_regs; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2514 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2515 | switch (INTEL_INFO(dev)->gen) { |
Eric Anholt | 25aebfc3 | 2011-05-06 13:55:53 -0700 | [diff] [blame] | 2516 | case 7: |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2517 | case 6: |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2518 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2519 | break; |
| 2520 | case 5: |
| 2521 | case 4: |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2522 | I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2523 | break; |
| 2524 | case 3: |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2525 | if (fence_reg >= 8) |
| 2526 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2527 | else |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2528 | case 2: |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2529 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2530 | |
| 2531 | I915_WRITE(fence_reg, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2532 | break; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2533 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2534 | |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2535 | list_del_init(®->lru_list); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2536 | reg->obj = NULL; |
| 2537 | reg->setup_seqno = 0; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2538 | reg->pin_count = 0; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2539 | } |
| 2540 | |
| 2541 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2542 | * Finds free space in the GTT aperture and binds the object there. |
| 2543 | */ |
| 2544 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2545 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2546 | unsigned alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2547 | bool map_and_fenceable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2548 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2549 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2550 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2551 | struct drm_mm_node *free_space; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2552 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2553 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2554 | bool mappable, fenceable; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2555 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2556 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2557 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2558 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2559 | return -EINVAL; |
| 2560 | } |
| 2561 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2562 | fence_size = i915_gem_get_gtt_size(dev, |
| 2563 | obj->base.size, |
| 2564 | obj->tiling_mode); |
| 2565 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 2566 | obj->base.size, |
| 2567 | obj->tiling_mode); |
| 2568 | unfenced_alignment = |
| 2569 | i915_gem_get_unfenced_gtt_alignment(dev, |
| 2570 | obj->base.size, |
| 2571 | obj->tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2572 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2573 | if (alignment == 0) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2574 | alignment = map_and_fenceable ? fence_alignment : |
| 2575 | unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2576 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2577 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2578 | return -EINVAL; |
| 2579 | } |
| 2580 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2581 | size = map_and_fenceable ? fence_size : obj->base.size; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2582 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2583 | /* If the object is bigger than the entire aperture, reject it early |
| 2584 | * before evicting everything in a vain attempt to find space. |
| 2585 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2586 | if (obj->base.size > |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2587 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2588 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
| 2589 | return -E2BIG; |
| 2590 | } |
| 2591 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2592 | search_free: |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2593 | if (map_and_fenceable) |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2594 | free_space = |
| 2595 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2596 | size, alignment, 0, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2597 | dev_priv->mm.gtt_mappable_end, |
| 2598 | 0); |
| 2599 | else |
| 2600 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2601 | size, alignment, 0); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2602 | |
| 2603 | if (free_space != NULL) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2604 | if (map_and_fenceable) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2605 | obj->gtt_space = |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2606 | drm_mm_get_block_range_generic(free_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2607 | size, alignment, 0, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2608 | dev_priv->mm.gtt_mappable_end, |
| 2609 | 0); |
| 2610 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2611 | obj->gtt_space = |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2612 | drm_mm_get_block(free_space, size, alignment); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2613 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2614 | if (obj->gtt_space == NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2615 | /* If the gtt is empty and we're still having trouble |
| 2616 | * fitting our object in, we're out of memory. |
| 2617 | */ |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2618 | ret = i915_gem_evict_something(dev, size, alignment, |
| 2619 | map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2620 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2621 | return ret; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2622 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2623 | goto search_free; |
| 2624 | } |
| 2625 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2626 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2627 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2628 | drm_mm_put_block(obj->gtt_space); |
| 2629 | obj->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2630 | |
| 2631 | if (ret == -ENOMEM) { |
Chris Wilson | 809b633 | 2011-01-10 17:33:15 +0000 | [diff] [blame] | 2632 | /* first try to reclaim some memory by clearing the GTT */ |
| 2633 | ret = i915_gem_evict_everything(dev, false); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2634 | if (ret) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2635 | /* now try to shrink everyone else */ |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2636 | if (gfpmask) { |
| 2637 | gfpmask = 0; |
| 2638 | goto search_free; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2639 | } |
| 2640 | |
Chris Wilson | 809b633 | 2011-01-10 17:33:15 +0000 | [diff] [blame] | 2641 | return -ENOMEM; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2642 | } |
| 2643 | |
| 2644 | goto search_free; |
| 2645 | } |
| 2646 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2647 | return ret; |
| 2648 | } |
| 2649 | |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2650 | ret = i915_gem_gtt_prepare_object(obj); |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 2651 | if (ret) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2652 | i915_gem_object_put_pages_gtt(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2653 | drm_mm_put_block(obj->gtt_space); |
| 2654 | obj->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2655 | |
Chris Wilson | 809b633 | 2011-01-10 17:33:15 +0000 | [diff] [blame] | 2656 | if (i915_gem_evict_everything(dev, false)) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2657 | return ret; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2658 | |
| 2659 | goto search_free; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2660 | } |
Daniel Vetter | 0ebb982 | 2012-02-15 23:50:24 +0100 | [diff] [blame] | 2661 | |
| 2662 | if (!dev_priv->mm.aliasing_ppgtt) |
| 2663 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2664 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2665 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2666 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2667 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2668 | /* Assert that the object is not currently in any GPU domain. As it |
| 2669 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2670 | * a GPU cache |
| 2671 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2672 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 2673 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2674 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2675 | obj->gtt_offset = obj->gtt_space->start; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2676 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2677 | fenceable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2678 | obj->gtt_space->size == fence_size && |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2679 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2680 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2681 | mappable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2682 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2683 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2684 | obj->map_and_fenceable = mappable && fenceable; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2685 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2686 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2687 | return 0; |
| 2688 | } |
| 2689 | |
| 2690 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2691 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2692 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2693 | /* If we don't have a page list set up, then we're not pinned |
| 2694 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2695 | * again at bind time. |
| 2696 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2697 | if (obj->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2698 | return; |
| 2699 | |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 2700 | /* If the GPU is snooping the contents of the CPU cache, |
| 2701 | * we do not need to manually clear the CPU cache lines. However, |
| 2702 | * the caches are only snooped when the render cache is |
| 2703 | * flushed/invalidated. As we always have to emit invalidations |
| 2704 | * and flushes when moving into and out of the RENDER domain, correct |
| 2705 | * snooping behaviour occurs naturally as the result of our domain |
| 2706 | * tracking. |
| 2707 | */ |
| 2708 | if (obj->cache_level != I915_CACHE_NONE) |
| 2709 | return; |
| 2710 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2711 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 2712 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2713 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2714 | } |
| 2715 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2716 | /** Flushes any GPU write domain for the object if it's dirty. */ |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2717 | static int |
Chris Wilson | 3619df0 | 2010-11-28 15:37:17 +0000 | [diff] [blame] | 2718 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2719 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2720 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2721 | return 0; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2722 | |
| 2723 | /* Queue the GPU write cache flushing we need. */ |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2724 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2725 | } |
| 2726 | |
| 2727 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 2728 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2729 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2730 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2731 | uint32_t old_write_domain; |
| 2732 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2733 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2734 | return; |
| 2735 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2736 | /* No actual flushing is required for the GTT write domain. Writes |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2737 | * to it immediately go to main memory as far as we know, so there's |
| 2738 | * no chipset flush. It also doesn't land in render cache. |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2739 | * |
| 2740 | * However, we do have to enforce the order so that all writes through |
| 2741 | * the GTT land before any writes to the device, such as updates to |
| 2742 | * the GATT itself. |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2743 | */ |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2744 | wmb(); |
| 2745 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2746 | old_write_domain = obj->base.write_domain; |
| 2747 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2748 | |
| 2749 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2750 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2751 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2752 | } |
| 2753 | |
| 2754 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 2755 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2756 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2757 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2758 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2759 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2760 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2761 | return; |
| 2762 | |
| 2763 | i915_gem_clflush_object(obj); |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 2764 | intel_gtt_chipset_flush(); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2765 | old_write_domain = obj->base.write_domain; |
| 2766 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2767 | |
| 2768 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2769 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2770 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2771 | } |
| 2772 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2773 | /** |
| 2774 | * Moves a single object to the GTT read, and possibly write domain. |
| 2775 | * |
| 2776 | * This function returns when the move is complete, including waiting on |
| 2777 | * flushes to occur. |
| 2778 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2779 | int |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2780 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2781 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2782 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2783 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2784 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2785 | /* Not valid to be called on unbound objects. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2786 | if (obj->gtt_space == NULL) |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2787 | return -EINVAL; |
| 2788 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 2789 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
| 2790 | return 0; |
| 2791 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2792 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 2793 | if (ret) |
| 2794 | return ret; |
| 2795 | |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 2796 | if (obj->pending_gpu_write || write) { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2797 | ret = i915_gem_object_wait_rendering(obj); |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 2798 | if (ret) |
| 2799 | return ret; |
| 2800 | } |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2801 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2802 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2803 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2804 | old_write_domain = obj->base.write_domain; |
| 2805 | old_read_domains = obj->base.read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2806 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2807 | /* It should now be out of any other write domains, and we can update |
| 2808 | * the domain values for our changes. |
| 2809 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2810 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2811 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2812 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2813 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 2814 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 2815 | obj->dirty = 1; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2816 | } |
| 2817 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2818 | trace_i915_gem_object_change_domain(obj, |
| 2819 | old_read_domains, |
| 2820 | old_write_domain); |
| 2821 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2822 | return 0; |
| 2823 | } |
| 2824 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2825 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 2826 | enum i915_cache_level cache_level) |
| 2827 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2828 | struct drm_device *dev = obj->base.dev; |
| 2829 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2830 | int ret; |
| 2831 | |
| 2832 | if (obj->cache_level == cache_level) |
| 2833 | return 0; |
| 2834 | |
| 2835 | if (obj->pin_count) { |
| 2836 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
| 2837 | return -EBUSY; |
| 2838 | } |
| 2839 | |
| 2840 | if (obj->gtt_space) { |
| 2841 | ret = i915_gem_object_finish_gpu(obj); |
| 2842 | if (ret) |
| 2843 | return ret; |
| 2844 | |
| 2845 | i915_gem_object_finish_gtt(obj); |
| 2846 | |
| 2847 | /* Before SandyBridge, you could not use tiling or fence |
| 2848 | * registers with snooped memory, so relinquish any fences |
| 2849 | * currently pointing to our region in the aperture. |
| 2850 | */ |
| 2851 | if (INTEL_INFO(obj->base.dev)->gen < 6) { |
| 2852 | ret = i915_gem_object_put_fence(obj); |
| 2853 | if (ret) |
| 2854 | return ret; |
| 2855 | } |
| 2856 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 2857 | if (obj->has_global_gtt_mapping) |
| 2858 | i915_gem_gtt_bind_object(obj, cache_level); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2859 | if (obj->has_aliasing_ppgtt_mapping) |
| 2860 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, |
| 2861 | obj, cache_level); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2862 | } |
| 2863 | |
| 2864 | if (cache_level == I915_CACHE_NONE) { |
| 2865 | u32 old_read_domains, old_write_domain; |
| 2866 | |
| 2867 | /* If we're coming from LLC cached, then we haven't |
| 2868 | * actually been tracking whether the data is in the |
| 2869 | * CPU cache or not, since we only allow one bit set |
| 2870 | * in obj->write_domain and have been skipping the clflushes. |
| 2871 | * Just set it to the CPU cache for now. |
| 2872 | */ |
| 2873 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
| 2874 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); |
| 2875 | |
| 2876 | old_read_domains = obj->base.read_domains; |
| 2877 | old_write_domain = obj->base.write_domain; |
| 2878 | |
| 2879 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 2880 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 2881 | |
| 2882 | trace_i915_gem_object_change_domain(obj, |
| 2883 | old_read_domains, |
| 2884 | old_write_domain); |
| 2885 | } |
| 2886 | |
| 2887 | obj->cache_level = cache_level; |
| 2888 | return 0; |
| 2889 | } |
| 2890 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2891 | /* |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2892 | * Prepare buffer for display plane (scanout, cursors, etc). |
| 2893 | * Can be called from an uninterruptible phase (modesetting) and allows |
| 2894 | * any flushes to be pipelined (for pageflips). |
| 2895 | * |
| 2896 | * For the display plane, we want to be in the GTT but out of any write |
| 2897 | * domains. So in many ways this looks like set_to_gtt_domain() apart from the |
| 2898 | * ability to pipeline the waits, pinning and any additional subtleties |
| 2899 | * that may differentiate the display plane from ordinary buffers. |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2900 | */ |
| 2901 | int |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2902 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 2903 | u32 alignment, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2904 | struct intel_ring_buffer *pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2905 | { |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2906 | u32 old_read_domains, old_write_domain; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2907 | int ret; |
| 2908 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2909 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 2910 | if (ret) |
| 2911 | return ret; |
| 2912 | |
Chris Wilson | 0be7328 | 2010-12-06 14:36:27 +0000 | [diff] [blame] | 2913 | if (pipelined != obj->ring) { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2914 | ret = i915_gem_object_wait_rendering(obj); |
Keith Packard | f0b69ef | 2011-07-19 16:21:40 -0700 | [diff] [blame] | 2915 | if (ret == -ERESTARTSYS) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2916 | return ret; |
| 2917 | } |
| 2918 | |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 2919 | /* The display engine is not coherent with the LLC cache on gen6. As |
| 2920 | * a result, we make sure that the pinning that is about to occur is |
| 2921 | * done with uncached PTEs. This is lowest common denominator for all |
| 2922 | * chipsets. |
| 2923 | * |
| 2924 | * However for gen6+, we could do better by using the GFDT bit instead |
| 2925 | * of uncaching, which would allow us to flush all the LLC-cached data |
| 2926 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
| 2927 | */ |
| 2928 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); |
| 2929 | if (ret) |
| 2930 | return ret; |
| 2931 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2932 | /* As the user may map the buffer once pinned in the display plane |
| 2933 | * (e.g. libkms for the bootup splash), we have to ensure that we |
| 2934 | * always use map_and_fenceable for all scanout buffers. |
| 2935 | */ |
| 2936 | ret = i915_gem_object_pin(obj, alignment, true); |
| 2937 | if (ret) |
| 2938 | return ret; |
| 2939 | |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 2940 | i915_gem_object_flush_cpu_write_domain(obj); |
| 2941 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2942 | old_write_domain = obj->base.write_domain; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2943 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2944 | |
| 2945 | /* It should now be out of any other write domains, and we can update |
| 2946 | * the domain values for our changes. |
| 2947 | */ |
| 2948 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2949 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2950 | |
| 2951 | trace_i915_gem_object_change_domain(obj, |
| 2952 | old_read_domains, |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2953 | old_write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2954 | |
| 2955 | return 0; |
| 2956 | } |
| 2957 | |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 2958 | int |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2959 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 2960 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2961 | int ret; |
| 2962 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2963 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 2964 | return 0; |
| 2965 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2966 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2967 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2968 | if (ret) |
| 2969 | return ret; |
| 2970 | } |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 2971 | |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 2972 | ret = i915_gem_object_wait_rendering(obj); |
| 2973 | if (ret) |
| 2974 | return ret; |
| 2975 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2976 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
| 2977 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 2978 | return 0; |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 2979 | } |
| 2980 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2981 | /** |
| 2982 | * Moves a single object to the CPU read, and possibly write domain. |
| 2983 | * |
| 2984 | * This function returns when the move is complete, including waiting on |
| 2985 | * flushes to occur. |
| 2986 | */ |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 2987 | int |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2988 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2989 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2990 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2991 | int ret; |
| 2992 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 2993 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
| 2994 | return 0; |
| 2995 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2996 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 2997 | if (ret) |
| 2998 | return ret; |
| 2999 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 3000 | ret = i915_gem_object_wait_rendering(obj); |
Daniel Vetter | de18a29 | 2010-11-27 22:30:41 +0100 | [diff] [blame] | 3001 | if (ret) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3002 | return ret; |
| 3003 | |
| 3004 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3005 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3006 | old_write_domain = obj->base.write_domain; |
| 3007 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3008 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3009 | /* Flush the CPU cache if it's still invalid. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3010 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3011 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3012 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3013 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3014 | } |
| 3015 | |
| 3016 | /* It should now be out of any other write domains, and we can update |
| 3017 | * the domain values for our changes. |
| 3018 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3019 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3020 | |
| 3021 | /* If we're writing through the CPU, then the GPU read domains will |
| 3022 | * need to be invalidated at next use. |
| 3023 | */ |
| 3024 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3025 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3026 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3027 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3028 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3029 | trace_i915_gem_object_change_domain(obj, |
| 3030 | old_read_domains, |
| 3031 | old_write_domain); |
| 3032 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3033 | return 0; |
| 3034 | } |
| 3035 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3036 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3037 | * emitted over 20 msec ago. |
| 3038 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3039 | * Note that if we were to use the current jiffies each time around the loop, |
| 3040 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3041 | * render a frame was over 20ms. |
| 3042 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3043 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3044 | * relatively low latency when blocking on a particular request to finish. |
| 3045 | */ |
| 3046 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3047 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3048 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3049 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3050 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3051 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3052 | struct drm_i915_gem_request *request; |
| 3053 | struct intel_ring_buffer *ring = NULL; |
| 3054 | u32 seqno = 0; |
| 3055 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3056 | |
Chris Wilson | e110e8d | 2011-01-26 15:39:14 +0000 | [diff] [blame] | 3057 | if (atomic_read(&dev_priv->mm.wedged)) |
| 3058 | return -EIO; |
| 3059 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3060 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3061 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3062 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3063 | break; |
| 3064 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3065 | ring = request->ring; |
| 3066 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3067 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3068 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3069 | |
| 3070 | if (seqno == 0) |
| 3071 | return 0; |
| 3072 | |
| 3073 | ret = 0; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3074 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3075 | /* And wait for the seqno passing without holding any locks and |
| 3076 | * causing extra latency for others. This is safe as the irq |
| 3077 | * generation is designed to be run atomically and so is |
| 3078 | * lockless. |
| 3079 | */ |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 3080 | if (ring->irq_get(ring)) { |
| 3081 | ret = wait_event_interruptible(ring->irq_queue, |
| 3082 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
| 3083 | || atomic_read(&dev_priv->mm.wedged)); |
| 3084 | ring->irq_put(ring); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3085 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 3086 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
| 3087 | ret = -EIO; |
Eric Anholt | e959b5d | 2011-12-22 14:55:01 -0800 | [diff] [blame] | 3088 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
| 3089 | seqno) || |
Eric Anholt | 7ea29b1 | 2011-12-22 14:54:59 -0800 | [diff] [blame] | 3090 | atomic_read(&dev_priv->mm.wedged), 3000)) { |
| 3091 | ret = -EBUSY; |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 3092 | } |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3093 | } |
| 3094 | |
| 3095 | if (ret == 0) |
| 3096 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3097 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3098 | return ret; |
| 3099 | } |
| 3100 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3101 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3102 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 3103 | uint32_t alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3104 | bool map_and_fenceable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3105 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3106 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 3107 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3108 | int ret; |
| 3109 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3110 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3111 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3112 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3113 | if (obj->gtt_space != NULL) { |
| 3114 | if ((alignment && obj->gtt_offset & (alignment - 1)) || |
| 3115 | (map_and_fenceable && !obj->map_and_fenceable)) { |
| 3116 | WARN(obj->pin_count, |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 3117 | "bo is already pinned with incorrect alignment:" |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3118 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
| 3119 | " obj->map_and_fenceable=%d\n", |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3120 | obj->gtt_offset, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3121 | map_and_fenceable, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3122 | obj->map_and_fenceable); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3123 | ret = i915_gem_object_unbind(obj); |
| 3124 | if (ret) |
| 3125 | return ret; |
| 3126 | } |
| 3127 | } |
| 3128 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3129 | if (obj->gtt_space == NULL) { |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3130 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3131 | map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3132 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3133 | return ret; |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 3134 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3135 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 3136 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
| 3137 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
| 3138 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3139 | if (obj->pin_count++ == 0) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3140 | if (!obj->active) |
| 3141 | list_move_tail(&obj->mm_list, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 3142 | &dev_priv->mm.pinned_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3143 | } |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3144 | obj->pin_mappable |= map_and_fenceable; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3145 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3146 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3147 | return 0; |
| 3148 | } |
| 3149 | |
| 3150 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3151 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3152 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3153 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3154 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3155 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3156 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3157 | BUG_ON(obj->pin_count == 0); |
| 3158 | BUG_ON(obj->gtt_space == NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3159 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3160 | if (--obj->pin_count == 0) { |
| 3161 | if (!obj->active) |
| 3162 | list_move_tail(&obj->mm_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3163 | &dev_priv->mm.inactive_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3164 | obj->pin_mappable = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3165 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3166 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3167 | } |
| 3168 | |
| 3169 | int |
| 3170 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3171 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3172 | { |
| 3173 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3174 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3175 | int ret; |
| 3176 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3177 | ret = i915_mutex_lock_interruptible(dev); |
| 3178 | if (ret) |
| 3179 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3180 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3181 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3182 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3183 | ret = -ENOENT; |
| 3184 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3185 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3186 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3187 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3188 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3189 | ret = -EINVAL; |
| 3190 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3191 | } |
| 3192 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3193 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3194 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 3195 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3196 | ret = -EINVAL; |
| 3197 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3198 | } |
| 3199 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3200 | obj->user_pin_count++; |
| 3201 | obj->pin_filp = file; |
| 3202 | if (obj->user_pin_count == 1) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3203 | ret = i915_gem_object_pin(obj, args->alignment, true); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3204 | if (ret) |
| 3205 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3206 | } |
| 3207 | |
| 3208 | /* XXX - flush the CPU caches for pinned objects |
| 3209 | * as the X server doesn't manage domains yet |
| 3210 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3211 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3212 | args->offset = obj->gtt_offset; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3213 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3214 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3215 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3216 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3217 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3218 | } |
| 3219 | |
| 3220 | int |
| 3221 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3222 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3223 | { |
| 3224 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3225 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3226 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3227 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3228 | ret = i915_mutex_lock_interruptible(dev); |
| 3229 | if (ret) |
| 3230 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3231 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3232 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3233 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3234 | ret = -ENOENT; |
| 3235 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3236 | } |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3237 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3238 | if (obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3239 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 3240 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3241 | ret = -EINVAL; |
| 3242 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3243 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3244 | obj->user_pin_count--; |
| 3245 | if (obj->user_pin_count == 0) { |
| 3246 | obj->pin_filp = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3247 | i915_gem_object_unpin(obj); |
| 3248 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3249 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3250 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3251 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3252 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3253 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3254 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3255 | } |
| 3256 | |
| 3257 | int |
| 3258 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3259 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3260 | { |
| 3261 | struct drm_i915_gem_busy *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3262 | struct drm_i915_gem_object *obj; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3263 | int ret; |
| 3264 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3265 | ret = i915_mutex_lock_interruptible(dev); |
| 3266 | if (ret) |
| 3267 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3268 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3269 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3270 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3271 | ret = -ENOENT; |
| 3272 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3273 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3274 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3275 | /* Count all active objects as busy, even if they are currently not used |
| 3276 | * by the gpu. Users of this interface expect objects to eventually |
| 3277 | * become non-busy without any further actions, therefore emit any |
| 3278 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 3279 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3280 | args->busy = obj->active; |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3281 | if (args->busy) { |
| 3282 | /* Unconditionally flush objects, even when the gpu still uses this |
| 3283 | * object. Userspace calling this function indicates that it wants to |
| 3284 | * use this buffer rather sooner than later, so issuing the required |
| 3285 | * flush earlier is beneficial. |
| 3286 | */ |
Chris Wilson | 1a1c697 | 2010-12-07 23:00:20 +0000 | [diff] [blame] | 3287 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3288 | ret = i915_gem_flush_ring(obj->ring, |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3289 | 0, obj->base.write_domain); |
Chris Wilson | 1a1c697 | 2010-12-07 23:00:20 +0000 | [diff] [blame] | 3290 | } else if (obj->ring->outstanding_lazy_request == |
| 3291 | obj->last_rendering_seqno) { |
| 3292 | struct drm_i915_gem_request *request; |
| 3293 | |
Chris Wilson | 7a19487 | 2010-12-07 10:38:40 +0000 | [diff] [blame] | 3294 | /* This ring is not being cleared by active usage, |
| 3295 | * so emit a request to do so. |
| 3296 | */ |
Chris Wilson | 1a1c697 | 2010-12-07 23:00:20 +0000 | [diff] [blame] | 3297 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
Rakib Mullick | 457eafc | 2011-11-16 00:49:28 +0600 | [diff] [blame] | 3298 | if (request) { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3299 | ret = i915_add_request(obj->ring, NULL, request); |
Rakib Mullick | 457eafc | 2011-11-16 00:49:28 +0600 | [diff] [blame] | 3300 | if (ret) |
| 3301 | kfree(request); |
| 3302 | } else |
Chris Wilson | 7a19487 | 2010-12-07 10:38:40 +0000 | [diff] [blame] | 3303 | ret = -ENOMEM; |
| 3304 | } |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3305 | |
| 3306 | /* Update the active list for the hardware's current position. |
| 3307 | * Otherwise this only updates on a delayed timer or when irqs |
| 3308 | * are actually unmasked, and our working set ends up being |
| 3309 | * larger than required. |
| 3310 | */ |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3311 | i915_gem_retire_requests_ring(obj->ring); |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3312 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3313 | args->busy = obj->active; |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3314 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3315 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3316 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3317 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3318 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3319 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3320 | } |
| 3321 | |
| 3322 | int |
| 3323 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 3324 | struct drm_file *file_priv) |
| 3325 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3326 | return i915_gem_ring_throttle(dev, file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3327 | } |
| 3328 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3329 | int |
| 3330 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 3331 | struct drm_file *file_priv) |
| 3332 | { |
| 3333 | struct drm_i915_gem_madvise *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3334 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3335 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3336 | |
| 3337 | switch (args->madv) { |
| 3338 | case I915_MADV_DONTNEED: |
| 3339 | case I915_MADV_WILLNEED: |
| 3340 | break; |
| 3341 | default: |
| 3342 | return -EINVAL; |
| 3343 | } |
| 3344 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3345 | ret = i915_mutex_lock_interruptible(dev); |
| 3346 | if (ret) |
| 3347 | return ret; |
| 3348 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3349 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3350 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3351 | ret = -ENOENT; |
| 3352 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3353 | } |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3354 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3355 | if (obj->pin_count) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3356 | ret = -EINVAL; |
| 3357 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3358 | } |
| 3359 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3360 | if (obj->madv != __I915_MADV_PURGED) |
| 3361 | obj->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3362 | |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 3363 | /* if the object is no longer bound, discard its backing storage */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3364 | if (i915_gem_object_is_purgeable(obj) && |
| 3365 | obj->gtt_space == NULL) |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 3366 | i915_gem_object_truncate(obj); |
| 3367 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3368 | args->retained = obj->madv != __I915_MADV_PURGED; |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3369 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3370 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3371 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3372 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3373 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3374 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3375 | } |
| 3376 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3377 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 3378 | size_t size) |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3379 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3380 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3381 | struct drm_i915_gem_object *obj; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3382 | struct address_space *mapping; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3383 | |
| 3384 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
| 3385 | if (obj == NULL) |
| 3386 | return NULL; |
| 3387 | |
| 3388 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
| 3389 | kfree(obj); |
| 3390 | return NULL; |
| 3391 | } |
| 3392 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3393 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
| 3394 | mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 3395 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3396 | i915_gem_info_add_obj(dev_priv, size); |
| 3397 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3398 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3399 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3400 | |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 3401 | if (HAS_LLC(dev)) { |
| 3402 | /* On some devices, we can have the GPU use the LLC (the CPU |
Eric Anholt | a187111 | 2011-03-29 16:59:55 -0700 | [diff] [blame] | 3403 | * cache) for about a 10% performance improvement |
| 3404 | * compared to uncached. Graphics requests other than |
| 3405 | * display scanout are coherent with the CPU in |
| 3406 | * accessing this cache. This means in this mode we |
| 3407 | * don't need to clflush on the CPU side, and on the |
| 3408 | * GPU side we only need to flush internal caches to |
| 3409 | * get data visible to the CPU. |
| 3410 | * |
| 3411 | * However, we maintain the display planes as UC, and so |
| 3412 | * need to rebind when first used as such. |
| 3413 | */ |
| 3414 | obj->cache_level = I915_CACHE_LLC; |
| 3415 | } else |
| 3416 | obj->cache_level = I915_CACHE_NONE; |
| 3417 | |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 3418 | obj->base.driver_private = NULL; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3419 | obj->fence_reg = I915_FENCE_REG_NONE; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3420 | INIT_LIST_HEAD(&obj->mm_list); |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 3421 | INIT_LIST_HEAD(&obj->gtt_list); |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3422 | INIT_LIST_HEAD(&obj->ring_list); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 3423 | INIT_LIST_HEAD(&obj->exec_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3424 | INIT_LIST_HEAD(&obj->gpu_write_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3425 | obj->madv = I915_MADV_WILLNEED; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3426 | /* Avoid an unnecessary call to unbind on the first bind. */ |
| 3427 | obj->map_and_fenceable = true; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3428 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3429 | return obj; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3430 | } |
| 3431 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3432 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 3433 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3434 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3435 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3436 | return 0; |
| 3437 | } |
| 3438 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3439 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3440 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3441 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3442 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3443 | int ret; |
| 3444 | |
| 3445 | ret = i915_gem_object_unbind(obj); |
| 3446 | if (ret == -ERESTARTSYS) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3447 | list_move(&obj->mm_list, |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3448 | &dev_priv->mm.deferred_free_list); |
| 3449 | return; |
| 3450 | } |
| 3451 | |
Chris Wilson | 26e12f89 | 2011-03-20 11:20:19 +0000 | [diff] [blame] | 3452 | trace_i915_gem_object_destroy(obj); |
| 3453 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3454 | if (obj->base.map_list.map) |
Rob Clark | b464e9a | 2011-08-10 08:09:08 -0500 | [diff] [blame] | 3455 | drm_gem_free_mmap_offset(&obj->base); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3456 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3457 | drm_gem_object_release(&obj->base); |
| 3458 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3459 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3460 | kfree(obj->bit_17); |
| 3461 | kfree(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3462 | } |
| 3463 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3464 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3465 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3466 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
| 3467 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3468 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3469 | while (obj->pin_count > 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3470 | i915_gem_object_unpin(obj); |
| 3471 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3472 | if (obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3473 | i915_gem_detach_phys_object(dev, obj); |
| 3474 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3475 | i915_gem_free_object_tail(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3476 | } |
| 3477 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 3478 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3479 | i915_gem_idle(struct drm_device *dev) |
| 3480 | { |
| 3481 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3482 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3483 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3484 | mutex_lock(&dev->struct_mutex); |
| 3485 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 3486 | if (dev_priv->mm.suspended) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3487 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3488 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3489 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3490 | |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 3491 | ret = i915_gpu_idle(dev, true); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3492 | if (ret) { |
| 3493 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3494 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3495 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3496 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3497 | /* Under UMS, be paranoid and evict. */ |
| 3498 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { |
Chris Wilson | 5eac3ab | 2010-10-31 08:49:47 +0000 | [diff] [blame] | 3499 | ret = i915_gem_evict_inactive(dev, false); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3500 | if (ret) { |
| 3501 | mutex_unlock(&dev->struct_mutex); |
| 3502 | return ret; |
| 3503 | } |
| 3504 | } |
| 3505 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 3506 | i915_gem_reset_fences(dev); |
| 3507 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3508 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 3509 | * We need to replace this with a semaphore, or something. |
| 3510 | * And not confound mm.suspended! |
| 3511 | */ |
| 3512 | dev_priv->mm.suspended = 1; |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 3513 | del_timer_sync(&dev_priv->hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3514 | |
| 3515 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3516 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3517 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3518 | mutex_unlock(&dev->struct_mutex); |
| 3519 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3520 | /* Cancel the retire work handler, which should be idle now. */ |
| 3521 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 3522 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3523 | return 0; |
| 3524 | } |
| 3525 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3526 | void i915_gem_init_swizzling(struct drm_device *dev) |
| 3527 | { |
| 3528 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3529 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 3530 | if (INTEL_INFO(dev)->gen < 5 || |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3531 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
| 3532 | return; |
| 3533 | |
| 3534 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
| 3535 | DISP_TILE_SURFACE_SWIZZLING); |
| 3536 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 3537 | if (IS_GEN5(dev)) |
| 3538 | return; |
| 3539 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3540 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
| 3541 | if (IS_GEN6(dev)) |
| 3542 | I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
| 3543 | else |
| 3544 | I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
| 3545 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3546 | |
| 3547 | void i915_gem_init_ppgtt(struct drm_device *dev) |
| 3548 | { |
| 3549 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3550 | uint32_t pd_offset; |
| 3551 | struct intel_ring_buffer *ring; |
| 3552 | int i; |
| 3553 | |
| 3554 | if (!dev_priv->mm.aliasing_ppgtt) |
| 3555 | return; |
| 3556 | |
| 3557 | pd_offset = dev_priv->mm.aliasing_ppgtt->pd_offset; |
| 3558 | pd_offset /= 64; /* in cachelines, */ |
| 3559 | pd_offset <<= 16; |
| 3560 | |
| 3561 | if (INTEL_INFO(dev)->gen == 6) { |
| 3562 | uint32_t ecochk = I915_READ(GAM_ECOCHK); |
| 3563 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | |
| 3564 | ECOCHK_PPGTT_CACHE64B); |
| 3565 | I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); |
| 3566 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 3567 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); |
| 3568 | /* GFX_MODE is per-ring on gen7+ */ |
| 3569 | } |
| 3570 | |
| 3571 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 3572 | ring = &dev_priv->ring[i]; |
| 3573 | |
| 3574 | if (INTEL_INFO(dev)->gen >= 7) |
| 3575 | I915_WRITE(RING_MODE_GEN7(ring), |
| 3576 | GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); |
| 3577 | |
| 3578 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
| 3579 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); |
| 3580 | } |
| 3581 | } |
| 3582 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3583 | int |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3584 | i915_gem_init_hw(struct drm_device *dev) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3585 | { |
| 3586 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3587 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3588 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3589 | i915_gem_init_swizzling(dev); |
| 3590 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3591 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3592 | if (ret) |
Chris Wilson | b6913e4 | 2010-11-12 10:46:37 +0000 | [diff] [blame] | 3593 | return ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3594 | |
| 3595 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3596 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3597 | if (ret) |
| 3598 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3599 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3600 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3601 | if (HAS_BLT(dev)) { |
| 3602 | ret = intel_init_blt_ring_buffer(dev); |
| 3603 | if (ret) |
| 3604 | goto cleanup_bsd_ring; |
| 3605 | } |
| 3606 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 3607 | dev_priv->next_seqno = 1; |
| 3608 | |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3609 | i915_gem_init_ppgtt(dev); |
| 3610 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3611 | return 0; |
| 3612 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3613 | cleanup_bsd_ring: |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3614 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3615 | cleanup_render_ring: |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3616 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3617 | return ret; |
| 3618 | } |
| 3619 | |
| 3620 | void |
| 3621 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 3622 | { |
| 3623 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3624 | int i; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3625 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3626 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 3627 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3628 | } |
| 3629 | |
| 3630 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3631 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 3632 | struct drm_file *file_priv) |
| 3633 | { |
| 3634 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3635 | int ret, i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3636 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3637 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3638 | return 0; |
| 3639 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3640 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3641 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3642 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3643 | } |
| 3644 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3645 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3646 | dev_priv->mm.suspended = 0; |
| 3647 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3648 | ret = i915_gem_init_hw(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 3649 | if (ret != 0) { |
| 3650 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3651 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 3652 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3653 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3654 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3655 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 3656 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3657 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 3658 | BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); |
| 3659 | BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); |
| 3660 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3661 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3662 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 3663 | ret = drm_irq_install(dev); |
| 3664 | if (ret) |
| 3665 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3666 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3667 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 3668 | |
| 3669 | cleanup_ringbuffer: |
| 3670 | mutex_lock(&dev->struct_mutex); |
| 3671 | i915_gem_cleanup_ringbuffer(dev); |
| 3672 | dev_priv->mm.suspended = 1; |
| 3673 | mutex_unlock(&dev->struct_mutex); |
| 3674 | |
| 3675 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3676 | } |
| 3677 | |
| 3678 | int |
| 3679 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 3680 | struct drm_file *file_priv) |
| 3681 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3682 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3683 | return 0; |
| 3684 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3685 | drm_irq_uninstall(dev); |
Linus Torvalds | e6890f6 | 2009-09-08 17:09:24 -0700 | [diff] [blame] | 3686 | return i915_gem_idle(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3687 | } |
| 3688 | |
| 3689 | void |
| 3690 | i915_gem_lastclose(struct drm_device *dev) |
| 3691 | { |
| 3692 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3693 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 3694 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3695 | return; |
| 3696 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3697 | ret = i915_gem_idle(dev); |
| 3698 | if (ret) |
| 3699 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3700 | } |
| 3701 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 3702 | static void |
| 3703 | init_ring_lists(struct intel_ring_buffer *ring) |
| 3704 | { |
| 3705 | INIT_LIST_HEAD(&ring->active_list); |
| 3706 | INIT_LIST_HEAD(&ring->request_list); |
| 3707 | INIT_LIST_HEAD(&ring->gpu_write_list); |
| 3708 | } |
| 3709 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3710 | void |
| 3711 | i915_gem_load(struct drm_device *dev) |
| 3712 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3713 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3714 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3715 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3716 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3717 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
| 3718 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 3719 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 3720 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3721 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 3722 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3723 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 3724 | init_ring_lists(&dev_priv->ring[i]); |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 3725 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 3726 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3727 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 3728 | i915_gem_retire_work_handler); |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3729 | init_completion(&dev_priv->error_completion); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3730 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 3731 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 3732 | if (IS_GEN3(dev)) { |
| 3733 | u32 tmp = I915_READ(MI_ARB_STATE); |
| 3734 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { |
| 3735 | /* arb state is a masked write, so set bit + bit in mask */ |
| 3736 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); |
| 3737 | I915_WRITE(MI_ARB_STATE, tmp); |
| 3738 | } |
| 3739 | } |
| 3740 | |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 3741 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
| 3742 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3743 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 3744 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3745 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3746 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3747 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3748 | dev_priv->num_fence_regs = 16; |
| 3749 | else |
| 3750 | dev_priv->num_fence_regs = 8; |
| 3751 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3752 | /* Initialize fence registers to zero */ |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 3753 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
| 3754 | i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]); |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3755 | } |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 3756 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3757 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3758 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3759 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 3760 | dev_priv->mm.interruptible = true; |
| 3761 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3762 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
| 3763 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
| 3764 | register_shrinker(&dev_priv->mm.inactive_shrinker); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3765 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3766 | |
| 3767 | /* |
| 3768 | * Create a physically contiguous memory object for this object |
| 3769 | * e.g. for cursor + overlay regs |
| 3770 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 3771 | static int i915_gem_init_phys_object(struct drm_device *dev, |
| 3772 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3773 | { |
| 3774 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3775 | struct drm_i915_gem_phys_object *phys_obj; |
| 3776 | int ret; |
| 3777 | |
| 3778 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 3779 | return 0; |
| 3780 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3781 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3782 | if (!phys_obj) |
| 3783 | return -ENOMEM; |
| 3784 | |
| 3785 | phys_obj->id = id; |
| 3786 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 3787 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3788 | if (!phys_obj->handle) { |
| 3789 | ret = -ENOMEM; |
| 3790 | goto kfree_obj; |
| 3791 | } |
| 3792 | #ifdef CONFIG_X86 |
| 3793 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 3794 | #endif |
| 3795 | |
| 3796 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 3797 | |
| 3798 | return 0; |
| 3799 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3800 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3801 | return ret; |
| 3802 | } |
| 3803 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 3804 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3805 | { |
| 3806 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3807 | struct drm_i915_gem_phys_object *phys_obj; |
| 3808 | |
| 3809 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 3810 | return; |
| 3811 | |
| 3812 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 3813 | if (phys_obj->cur_obj) { |
| 3814 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 3815 | } |
| 3816 | |
| 3817 | #ifdef CONFIG_X86 |
| 3818 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 3819 | #endif |
| 3820 | drm_pci_free(dev, phys_obj->handle); |
| 3821 | kfree(phys_obj); |
| 3822 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 3823 | } |
| 3824 | |
| 3825 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 3826 | { |
| 3827 | int i; |
| 3828 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 3829 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3830 | i915_gem_free_phys_object(dev, i); |
| 3831 | } |
| 3832 | |
| 3833 | void i915_gem_detach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3834 | struct drm_i915_gem_object *obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3835 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3836 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3837 | char *vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3838 | int i; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3839 | int page_count; |
| 3840 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3841 | if (!obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3842 | return; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3843 | vaddr = obj->phys_obj->handle->vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3844 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3845 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3846 | for (i = 0; i < page_count; i++) { |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3847 | struct page *page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3848 | if (!IS_ERR(page)) { |
| 3849 | char *dst = kmap_atomic(page); |
| 3850 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); |
| 3851 | kunmap_atomic(dst); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3852 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3853 | drm_clflush_pages(&page, 1); |
| 3854 | |
| 3855 | set_page_dirty(page); |
| 3856 | mark_page_accessed(page); |
| 3857 | page_cache_release(page); |
| 3858 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3859 | } |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 3860 | intel_gtt_chipset_flush(); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 3861 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3862 | obj->phys_obj->cur_obj = NULL; |
| 3863 | obj->phys_obj = NULL; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3864 | } |
| 3865 | |
| 3866 | int |
| 3867 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3868 | struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 3869 | int id, |
| 3870 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3871 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3872 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3873 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3874 | int ret = 0; |
| 3875 | int page_count; |
| 3876 | int i; |
| 3877 | |
| 3878 | if (id > I915_MAX_PHYS_OBJECT) |
| 3879 | return -EINVAL; |
| 3880 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3881 | if (obj->phys_obj) { |
| 3882 | if (obj->phys_obj->id == id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3883 | return 0; |
| 3884 | i915_gem_detach_phys_object(dev, obj); |
| 3885 | } |
| 3886 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3887 | /* create a new object */ |
| 3888 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 3889 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3890 | obj->base.size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3891 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3892 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
| 3893 | id, obj->base.size); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3894 | return ret; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3895 | } |
| 3896 | } |
| 3897 | |
| 3898 | /* bind to the object */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3899 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 3900 | obj->phys_obj->cur_obj = obj; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3901 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3902 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3903 | |
| 3904 | for (i = 0; i < page_count; i++) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3905 | struct page *page; |
| 3906 | char *dst, *src; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3907 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3908 | page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3909 | if (IS_ERR(page)) |
| 3910 | return PTR_ERR(page); |
| 3911 | |
Chris Wilson | ff75b9b | 2010-10-30 22:52:31 +0100 | [diff] [blame] | 3912 | src = kmap_atomic(page); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3913 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3914 | memcpy(dst, src, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 3915 | kunmap_atomic(src); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3916 | |
| 3917 | mark_page_accessed(page); |
| 3918 | page_cache_release(page); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3919 | } |
| 3920 | |
| 3921 | return 0; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3922 | } |
| 3923 | |
| 3924 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3925 | i915_gem_phys_pwrite(struct drm_device *dev, |
| 3926 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3927 | struct drm_i915_gem_pwrite *args, |
| 3928 | struct drm_file *file_priv) |
| 3929 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3930 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 3931 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3932 | |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 3933 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 3934 | unsigned long unwritten; |
| 3935 | |
| 3936 | /* The physical object once assigned is fixed for the lifetime |
| 3937 | * of the obj, so we can safely drop the lock and continue |
| 3938 | * to access vaddr. |
| 3939 | */ |
| 3940 | mutex_unlock(&dev->struct_mutex); |
| 3941 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 3942 | mutex_lock(&dev->struct_mutex); |
| 3943 | if (unwritten) |
| 3944 | return -EFAULT; |
| 3945 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3946 | |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 3947 | intel_gtt_chipset_flush(); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3948 | return 0; |
| 3949 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3950 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3951 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3952 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3953 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3954 | |
| 3955 | /* Clean up our request list when the client is going away, so that |
| 3956 | * later retire_requests won't dereference our soon-to-be-gone |
| 3957 | * file_priv. |
| 3958 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3959 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3960 | while (!list_empty(&file_priv->mm.request_list)) { |
| 3961 | struct drm_i915_gem_request *request; |
| 3962 | |
| 3963 | request = list_first_entry(&file_priv->mm.request_list, |
| 3964 | struct drm_i915_gem_request, |
| 3965 | client_list); |
| 3966 | list_del(&request->client_list); |
| 3967 | request->file_priv = NULL; |
| 3968 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3969 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3970 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3971 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3972 | static int |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 3973 | i915_gpu_is_active(struct drm_device *dev) |
| 3974 | { |
| 3975 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3976 | int lists_empty; |
| 3977 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 3978 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3979 | list_empty(&dev_priv->mm.active_list); |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 3980 | |
| 3981 | return !lists_empty; |
| 3982 | } |
| 3983 | |
| 3984 | static int |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 3985 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3986 | { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3987 | struct drm_i915_private *dev_priv = |
| 3988 | container_of(shrinker, |
| 3989 | struct drm_i915_private, |
| 3990 | mm.inactive_shrinker); |
| 3991 | struct drm_device *dev = dev_priv->dev; |
| 3992 | struct drm_i915_gem_object *obj, *next; |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 3993 | int nr_to_scan = sc->nr_to_scan; |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3994 | int cnt; |
| 3995 | |
| 3996 | if (!mutex_trylock(&dev->struct_mutex)) |
Chris Wilson | bbe2e11 | 2010-10-28 22:35:07 +0100 | [diff] [blame] | 3997 | return 0; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3998 | |
| 3999 | /* "fast-path" to count number of available objects */ |
| 4000 | if (nr_to_scan == 0) { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4001 | cnt = 0; |
| 4002 | list_for_each_entry(obj, |
| 4003 | &dev_priv->mm.inactive_list, |
| 4004 | mm_list) |
| 4005 | cnt++; |
| 4006 | mutex_unlock(&dev->struct_mutex); |
| 4007 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4008 | } |
| 4009 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4010 | rescan: |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4011 | /* first scan for clean buffers */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4012 | i915_gem_retire_requests(dev); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4013 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4014 | list_for_each_entry_safe(obj, next, |
| 4015 | &dev_priv->mm.inactive_list, |
| 4016 | mm_list) { |
| 4017 | if (i915_gem_object_is_purgeable(obj)) { |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 4018 | if (i915_gem_object_unbind(obj) == 0 && |
| 4019 | --nr_to_scan == 0) |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4020 | break; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4021 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4022 | } |
| 4023 | |
| 4024 | /* second pass, evict/count anything still on the inactive list */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4025 | cnt = 0; |
| 4026 | list_for_each_entry_safe(obj, next, |
| 4027 | &dev_priv->mm.inactive_list, |
| 4028 | mm_list) { |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 4029 | if (nr_to_scan && |
| 4030 | i915_gem_object_unbind(obj) == 0) |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4031 | nr_to_scan--; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 4032 | else |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4033 | cnt++; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4034 | } |
| 4035 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4036 | if (nr_to_scan && i915_gpu_is_active(dev)) { |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4037 | /* |
| 4038 | * We are desperate for pages, so as a last resort, wait |
| 4039 | * for the GPU to finish and discard whatever we can. |
| 4040 | * This has a dramatic impact to reduce the number of |
| 4041 | * OOM-killer events whilst running the GPU aggressively. |
| 4042 | */ |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 4043 | if (i915_gpu_idle(dev, true) == 0) |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4044 | goto rescan; |
| 4045 | } |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4046 | mutex_unlock(&dev->struct_mutex); |
| 4047 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4048 | } |