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Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Petr Machata803335a2018-02-27 14:53:46 +01003 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
Jiri Pirko22a67762017-02-03 10:29:07 +01004 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +020056#include <linux/netlink.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020057#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020058#include <net/pkt_cls.h>
59#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020060#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010061#include <net/tc_act/tc_sample.h>
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +020062#include <net/addrconf.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020063
64#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020065#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020066#include "core.h"
67#include "reg.h"
68#include "port.h"
69#include "trap.h"
70#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010071#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020072#include "spectrum_dpipe.h"
Yotam Gigid3b939b2017-09-19 10:00:09 +020073#include "spectrum_acl_flex_actions.h"
Petr Machataa629ef22018-02-13 11:27:48 +010074#include "spectrum_span.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020075#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020076
Yotam Gigi6b742192017-05-23 21:56:29 +020077#define MLXSW_FWREV_MAJOR 13
Shalom Toledo2f53fbd2017-11-12 09:01:24 +010078#define MLXSW_FWREV_MINOR 1530
79#define MLXSW_FWREV_SUBMINOR 152
Yuval Mintzfd5204c2018-01-18 12:55:23 +010080#define MLXSW_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
Yotam Gigi6b742192017-05-23 21:56:29 +020081
82#define MLXSW_SP_FW_FILENAME \
Yotam Gigia4e1ce22017-06-04 16:49:58 +020083 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
Yotam Gigi6b742192017-05-23 21:56:29 +020084 "." __stringify(MLXSW_FWREV_MINOR) \
85 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
86
Jiri Pirko56ade8f2015-10-16 14:01:37 +020087static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
88static const char mlxsw_sp_driver_version[] = "1.0";
89
90/* tx_hdr_version
91 * Tx header version.
92 * Must be set to 1.
93 */
94MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
95
96/* tx_hdr_ctl
97 * Packet control type.
98 * 0 - Ethernet control (e.g. EMADs, LACP)
99 * 1 - Ethernet data
100 */
101MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
102
103/* tx_hdr_proto
104 * Packet protocol type. Must be set to 1 (Ethernet).
105 */
106MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
107
108/* tx_hdr_rx_is_router
109 * Packet is sent from the router. Valid for data packets only.
110 */
111MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
112
113/* tx_hdr_fid_valid
114 * Indicates if the 'fid' field is valid and should be used for
115 * forwarding lookup. Valid for data packets only.
116 */
117MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
118
119/* tx_hdr_swid
120 * Switch partition ID. Must be set to 0.
121 */
122MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
123
124/* tx_hdr_control_tclass
125 * Indicates if the packet should use the control TClass and not one
126 * of the data TClasses.
127 */
128MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
129
130/* tx_hdr_etclass
131 * Egress TClass to be used on the egress device on the egress port.
132 */
133MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
134
135/* tx_hdr_port_mid
136 * Destination local port for unicast packets.
137 * Destination multicast ID for multicast packets.
138 *
139 * Control packets are directed to a specific egress port, while data
140 * packets are transmitted through the CPU port (0) into the switch partition,
141 * where forwarding rules are applied.
142 */
143MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
144
145/* tx_hdr_fid
146 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
147 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
148 * Valid for data packets only.
149 */
150MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
151
152/* tx_hdr_type
153 * 0 - Data packets
154 * 6 - Control packets
155 */
156MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
157
Yotam Gigie5e5c882017-05-23 21:56:27 +0200158struct mlxsw_sp_mlxfw_dev {
159 struct mlxfw_dev mlxfw_dev;
160 struct mlxsw_sp *mlxsw_sp;
161};
162
163static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
164 u16 component_index, u32 *p_max_size,
165 u8 *p_align_bits, u16 *p_max_write_size)
166{
167 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
168 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
169 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
170 char mcqi_pl[MLXSW_REG_MCQI_LEN];
171 int err;
172
173 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
174 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
175 if (err)
176 return err;
177 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
178 p_max_write_size);
179
180 *p_align_bits = max_t(u8, *p_align_bits, 2);
181 *p_max_write_size = min_t(u16, *p_max_write_size,
182 MLXSW_REG_MCDA_MAX_DATA_LEN);
183 return 0;
184}
185
186static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
187{
188 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
189 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
190 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
191 char mcc_pl[MLXSW_REG_MCC_LEN];
192 u8 control_state;
193 int err;
194
195 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
196 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
197 if (err)
198 return err;
199
200 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
201 if (control_state != MLXFW_FSM_STATE_IDLE)
202 return -EBUSY;
203
204 mlxsw_reg_mcc_pack(mcc_pl,
205 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
206 0, *fwhandle, 0);
207 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
208}
209
210static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
211 u32 fwhandle, u16 component_index,
212 u32 component_size)
213{
214 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
215 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
217 char mcc_pl[MLXSW_REG_MCC_LEN];
218
219 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
220 component_index, fwhandle, component_size);
221 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
222}
223
224static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
225 u32 fwhandle, u8 *data, u16 size,
226 u32 offset)
227{
228 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
229 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
230 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
231 char mcda_pl[MLXSW_REG_MCDA_LEN];
232
233 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
234 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
235}
236
237static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
238 u32 fwhandle, u16 component_index)
239{
240 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
241 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
242 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
243 char mcc_pl[MLXSW_REG_MCC_LEN];
244
245 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
246 component_index, fwhandle, 0);
247 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
248}
249
250static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
251{
252 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
253 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
254 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
255 char mcc_pl[MLXSW_REG_MCC_LEN];
256
257 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
258 fwhandle, 0);
259 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
260}
261
262static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
263 enum mlxfw_fsm_state *fsm_state,
264 enum mlxfw_fsm_state_err *fsm_state_err)
265{
266 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
267 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
268 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
269 char mcc_pl[MLXSW_REG_MCC_LEN];
270 u8 control_state;
271 u8 error_code;
272 int err;
273
274 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
275 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
276 if (err)
277 return err;
278
279 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
280 *fsm_state = control_state;
281 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
282 MLXFW_FSM_STATE_ERR_MAX);
283 return 0;
284}
285
286static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
287{
288 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
289 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
290 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
291 char mcc_pl[MLXSW_REG_MCC_LEN];
292
293 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
294 fwhandle, 0);
295 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
296}
297
298static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
299{
300 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
301 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
302 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
303 char mcc_pl[MLXSW_REG_MCC_LEN];
304
305 mlxsw_reg_mcc_pack(mcc_pl,
306 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
307 fwhandle, 0);
308 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
309}
310
311static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
312 .component_query = mlxsw_sp_component_query,
313 .fsm_lock = mlxsw_sp_fsm_lock,
314 .fsm_component_update = mlxsw_sp_fsm_component_update,
315 .fsm_block_download = mlxsw_sp_fsm_block_download,
316 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
317 .fsm_activate = mlxsw_sp_fsm_activate,
318 .fsm_query_state = mlxsw_sp_fsm_query_state,
319 .fsm_cancel = mlxsw_sp_fsm_cancel,
320 .fsm_release = mlxsw_sp_fsm_release
321};
322
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300323static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
324 const struct firmware *firmware)
325{
326 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
327 .mlxfw_dev = {
328 .ops = &mlxsw_sp_mlxfw_dev_ops,
329 .psid = mlxsw_sp->bus_info->psid,
330 .psid_size = strlen(mlxsw_sp->bus_info->psid),
331 },
332 .mlxsw_sp = mlxsw_sp
333 };
334
335 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
336}
337
Yotam Gigi6b742192017-05-23 21:56:29 +0200338static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
339{
340 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
Yotam Gigi6b742192017-05-23 21:56:29 +0200341 const struct firmware *firmware;
342 int err;
343
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100344 /* Validate driver & FW are compatible */
345 if (rev->major != MLXSW_FWREV_MAJOR) {
346 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
347 rev->major, MLXSW_FWREV_MAJOR);
348 return -EINVAL;
349 }
350 if (MLXSW_FWREV_MINOR_TO_BRANCH(rev->minor) ==
351 MLXSW_FWREV_MINOR_TO_BRANCH(MLXSW_FWREV_MINOR))
Yotam Gigi6b742192017-05-23 21:56:29 +0200352 return 0;
353
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100354 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200355 rev->major, rev->minor, rev->subminor);
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100356 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200357 MLXSW_SP_FW_FILENAME);
358
359 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
360 mlxsw_sp->bus_info->dev);
361 if (err) {
362 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
363 MLXSW_SP_FW_FILENAME);
364 return err;
365 }
366
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300367 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
Yotam Gigi6b742192017-05-23 21:56:29 +0200368 release_firmware(firmware);
369 return err;
370}
371
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100372int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
373 unsigned int counter_index, u64 *packets,
374 u64 *bytes)
375{
376 char mgpc_pl[MLXSW_REG_MGPC_LEN];
377 int err;
378
379 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200380 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100381 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
382 if (err)
383 return err;
Arkadi Sharshevsky7cfcbc72017-08-24 08:40:08 +0200384 if (packets)
385 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
386 if (bytes)
387 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100388 return 0;
389}
390
391static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
392 unsigned int counter_index)
393{
394 char mgpc_pl[MLXSW_REG_MGPC_LEN];
395
396 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200397 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100398 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
399}
400
401int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
402 unsigned int *p_counter_index)
403{
404 int err;
405
406 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
407 p_counter_index);
408 if (err)
409 return err;
410 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
411 if (err)
412 goto err_counter_clear;
413 return 0;
414
415err_counter_clear:
416 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
417 *p_counter_index);
418 return err;
419}
420
421void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
422 unsigned int counter_index)
423{
424 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
425 counter_index);
426}
427
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200428static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
429 const struct mlxsw_tx_info *tx_info)
430{
431 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
432
433 memset(txhdr, 0, MLXSW_TXHDR_LEN);
434
435 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
436 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
437 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
438 mlxsw_tx_hdr_swid_set(txhdr, 0);
439 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
440 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
441 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
442}
443
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200444int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
445 u8 state)
446{
447 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
448 enum mlxsw_reg_spms_state spms_state;
449 char *spms_pl;
450 int err;
451
452 switch (state) {
453 case BR_STATE_FORWARDING:
454 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
455 break;
456 case BR_STATE_LEARNING:
457 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
458 break;
459 case BR_STATE_LISTENING: /* fall-through */
460 case BR_STATE_DISABLED: /* fall-through */
461 case BR_STATE_BLOCKING:
462 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
463 break;
464 default:
465 BUG();
466 }
467
468 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
469 if (!spms_pl)
470 return -ENOMEM;
471 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
472 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
473
474 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
475 kfree(spms_pl);
476 return err;
477}
478
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200479static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
480{
Elad Raz5b090742016-10-28 21:35:46 +0200481 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200482 int err;
483
484 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
485 if (err)
486 return err;
487 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
488 return 0;
489}
490
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100491static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
492 bool enable, u32 rate)
493{
494 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
495 char mpsc_pl[MLXSW_REG_MPSC_LEN];
496
497 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
498 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
499}
500
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200501static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
502 bool is_up)
503{
504 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
505 char paos_pl[MLXSW_REG_PAOS_LEN];
506
507 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
508 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
509 MLXSW_PORT_ADMIN_STATUS_DOWN);
510 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
511}
512
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200513static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
514 unsigned char *addr)
515{
516 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
517 char ppad_pl[MLXSW_REG_PPAD_LEN];
518
519 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
520 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
521 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
522}
523
524static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
525{
526 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
527 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
528
529 ether_addr_copy(addr, mlxsw_sp->base_mac);
530 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
531 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
532}
533
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200534static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
535{
536 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
537 char pmtu_pl[MLXSW_REG_PMTU_LEN];
538 int max_mtu;
539 int err;
540
541 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
542 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
543 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
544 if (err)
545 return err;
546 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
547
548 if (mtu > max_mtu)
549 return -EINVAL;
550
551 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
552 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
553}
554
555static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
556{
557 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel5b153852017-06-08 08:47:44 +0200558 char pspa_pl[MLXSW_REG_PSPA_LEN];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200559
Ido Schimmel5b153852017-06-08 08:47:44 +0200560 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
561 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200562}
563
Ido Schimmela1107482017-05-26 08:37:39 +0200564int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200565{
566 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
567 char svpe_pl[MLXSW_REG_SVPE_LEN];
568
569 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
570 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
571}
572
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200573int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
574 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200575{
576 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
577 char *spvmlr_pl;
578 int err;
579
580 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
581 if (!spvmlr_pl)
582 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200583 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
584 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200585 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
586 kfree(spvmlr_pl);
587 return err;
588}
589
Ido Schimmelb02eae92017-05-16 19:38:34 +0200590static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
591 u16 vid)
592{
593 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
594 char spvid_pl[MLXSW_REG_SPVID_LEN];
595
596 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
597 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
598}
599
600static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
601 bool allow)
602{
603 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
604 char spaft_pl[MLXSW_REG_SPAFT_LEN];
605
606 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
607 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
608}
609
610int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
611{
612 int err;
613
614 if (!vid) {
615 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
616 if (err)
617 return err;
618 } else {
619 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
620 if (err)
621 return err;
622 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
623 if (err)
624 goto err_port_allow_untagged_set;
625 }
626
627 mlxsw_sp_port->pvid = vid;
628 return 0;
629
630err_port_allow_untagged_set:
631 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
632 return err;
633}
634
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200635static int
636mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
637{
638 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
639 char sspr_pl[MLXSW_REG_SSPR_LEN];
640
641 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
642 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
643}
644
Ido Schimmeld664b412016-06-09 09:51:40 +0200645static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
646 u8 local_port, u8 *p_module,
647 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200648{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200649 char pmlp_pl[MLXSW_REG_PMLP_LEN];
650 int err;
651
Ido Schimmel558c2d52016-02-26 17:32:29 +0100652 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200653 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
654 if (err)
655 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100656 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
657 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200658 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200659 return 0;
660}
661
Ido Schimmel2e915e02017-06-08 08:47:45 +0200662static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100663 u8 module, u8 width, u8 lane)
664{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200665 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel18f1e702016-02-26 17:32:31 +0100666 char pmlp_pl[MLXSW_REG_PMLP_LEN];
667 int i;
668
Ido Schimmel2e915e02017-06-08 08:47:45 +0200669 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel18f1e702016-02-26 17:32:31 +0100670 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
671 for (i = 0; i < width; i++) {
672 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
673 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
674 }
675
676 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
677}
678
Ido Schimmel2e915e02017-06-08 08:47:45 +0200679static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100680{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200681 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100682 char pmlp_pl[MLXSW_REG_PMLP_LEN];
683
Ido Schimmel2e915e02017-06-08 08:47:45 +0200684 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100685 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
686 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
687}
688
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200689static int mlxsw_sp_port_open(struct net_device *dev)
690{
691 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
692 int err;
693
694 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
695 if (err)
696 return err;
697 netif_start_queue(dev);
698 return 0;
699}
700
701static int mlxsw_sp_port_stop(struct net_device *dev)
702{
703 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
704
705 netif_stop_queue(dev);
706 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
707}
708
709static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
710 struct net_device *dev)
711{
712 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
713 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
714 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
715 const struct mlxsw_tx_info tx_info = {
716 .local_port = mlxsw_sp_port->local_port,
717 .is_emad = false,
718 };
719 u64 len;
720 int err;
721
Jiri Pirko307c2432016-04-08 19:11:22 +0200722 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200723 return NETDEV_TX_BUSY;
724
725 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
726 struct sk_buff *skb_orig = skb;
727
728 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
729 if (!skb) {
730 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
731 dev_kfree_skb_any(skb_orig);
732 return NETDEV_TX_OK;
733 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +0100734 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200735 }
736
737 if (eth_skb_pad(skb)) {
738 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
739 return NETDEV_TX_OK;
740 }
741
742 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +0200743 /* TX header is consumed by HW on the way so we shouldn't count its
744 * bytes as being sent.
745 */
746 len = skb->len - MLXSW_TXHDR_LEN;
747
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200748 /* Due to a race we might fail here because of a full queue. In that
749 * unlikely case we simply drop the packet.
750 */
Jiri Pirko307c2432016-04-08 19:11:22 +0200751 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200752
753 if (!err) {
754 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
755 u64_stats_update_begin(&pcpu_stats->syncp);
756 pcpu_stats->tx_packets++;
757 pcpu_stats->tx_bytes += len;
758 u64_stats_update_end(&pcpu_stats->syncp);
759 } else {
760 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
761 dev_kfree_skb_any(skb);
762 }
763 return NETDEV_TX_OK;
764}
765
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100766static void mlxsw_sp_set_rx_mode(struct net_device *dev)
767{
768}
769
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200770static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
771{
772 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
773 struct sockaddr *addr = p;
774 int err;
775
776 if (!is_valid_ether_addr(addr->sa_data))
777 return -EADDRNOTAVAIL;
778
779 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
780 if (err)
781 return err;
782 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
783 return 0;
784}
785
Ido Schimmel18281f22017-03-24 08:02:51 +0100786static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
787 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200788{
Ido Schimmel18281f22017-03-24 08:02:51 +0100789 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100790}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200791
Ido Schimmelf417f042017-03-24 08:02:50 +0100792#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +0100793
794static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
795 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +0100796{
Ido Schimmel18281f22017-03-24 08:02:51 +0100797 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
798 BITS_PER_BYTE));
799 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
800 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100801}
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200802
Ido Schimmel18281f22017-03-24 08:02:51 +0100803/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +0100804 * Assumes 100m cable and maximum MTU.
805 */
Ido Schimmel18281f22017-03-24 08:02:51 +0100806#define MLXSW_SP_PAUSE_DELAY 58752
807
808static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
809 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +0100810{
811 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +0100812 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +0100813 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +0100814 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200815 else
Ido Schimmelf417f042017-03-24 08:02:50 +0100816 return 0;
817}
818
819static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
820 bool lossy)
821{
822 if (lossy)
823 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
824 else
825 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
826 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200827}
828
829int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200830 u8 *prio_tc, bool pause_en,
831 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +0200832{
833 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200834 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
835 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200836 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200837 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200838
839 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
840 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
841 if (err)
842 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200843
844 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
845 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200846 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +0100847 bool lossy;
848 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200849
850 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
851 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200852 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200853 configure = true;
854 break;
855 }
856 }
857
858 if (!configure)
859 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +0100860
861 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +0100862 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
863 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
864 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +0100865 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200866 }
867
Ido Schimmelff6551e2016-04-06 17:10:03 +0200868 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
869}
870
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200871static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200872 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200873{
874 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
875 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200876 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200877 u8 *prio_tc;
878
879 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200880 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200881
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200882 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200883 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200884}
885
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200886static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
887{
888 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200889 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200890 int err;
891
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200892 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200893 if (err)
894 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200895 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
896 if (err)
897 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200898 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
899 if (err)
900 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200901 dev->mtu = mtu;
902 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200903
904err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +0200905 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
906err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200907 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +0200908 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200909}
910
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +0300911static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200912mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
913 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200914{
915 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
916 struct mlxsw_sp_port_pcpu_stats *p;
917 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
918 u32 tx_dropped = 0;
919 unsigned int start;
920 int i;
921
922 for_each_possible_cpu(i) {
923 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
924 do {
925 start = u64_stats_fetch_begin_irq(&p->syncp);
926 rx_packets = p->rx_packets;
927 rx_bytes = p->rx_bytes;
928 tx_packets = p->tx_packets;
929 tx_bytes = p->tx_bytes;
930 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
931
932 stats->rx_packets += rx_packets;
933 stats->rx_bytes += rx_bytes;
934 stats->tx_packets += tx_packets;
935 stats->tx_bytes += tx_bytes;
936 /* tx_dropped is u32, updated without syncp protection. */
937 tx_dropped += p->tx_dropped;
938 }
939 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200940 return 0;
941}
942
Or Gerlitz3df5b3c2016-11-22 23:09:54 +0200943static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200944{
945 switch (attr_id) {
946 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
947 return true;
948 }
949
950 return false;
951}
952
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +0300953static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
954 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200955{
956 switch (attr_id) {
957 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
958 return mlxsw_sp_port_get_sw_stats64(dev, sp);
959 }
960
961 return -EINVAL;
962}
963
964static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
965 int prio, char *ppcnt_pl)
966{
967 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
968 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
969
970 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
971 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
972}
973
974static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
975 struct rtnl_link_stats64 *stats)
976{
977 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
978 int err;
979
980 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
981 0, ppcnt_pl);
982 if (err)
983 goto out;
984
985 stats->tx_packets =
986 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
987 stats->rx_packets =
988 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
989 stats->tx_bytes =
990 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
991 stats->rx_bytes =
992 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
993 stats->multicast =
994 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
995
996 stats->rx_crc_errors =
997 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
998 stats->rx_frame_errors =
999 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1000
1001 stats->rx_length_errors = (
1002 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1003 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1004 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1005
1006 stats->rx_errors = (stats->rx_crc_errors +
1007 stats->rx_frame_errors + stats->rx_length_errors);
1008
1009out:
1010 return err;
1011}
1012
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001013static void
1014mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1015 struct mlxsw_sp_port_xstats *xstats)
1016{
1017 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1018 int err, i;
1019
1020 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1021 ppcnt_pl);
1022 if (!err)
1023 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1024
1025 for (i = 0; i < TC_MAX_QUEUE; i++) {
1026 err = mlxsw_sp_port_get_stats_raw(dev,
1027 MLXSW_REG_PPCNT_TC_CONG_TC,
1028 i, ppcnt_pl);
1029 if (!err)
1030 xstats->wred_drop[i] =
1031 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1032
1033 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1034 i, ppcnt_pl);
1035 if (err)
1036 continue;
1037
1038 xstats->backlog[i] =
1039 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1040 xstats->tail_drop[i] =
1041 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1042 }
Nogah Frankel2f880472018-02-28 10:44:59 +01001043
1044 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1045 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
1046 i, ppcnt_pl);
1047 if (err)
1048 continue;
1049
1050 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
1051 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
1052 }
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001053}
1054
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001055static void update_stats_cache(struct work_struct *work)
1056{
1057 struct mlxsw_sp_port *mlxsw_sp_port =
1058 container_of(work, struct mlxsw_sp_port,
Nogah Frankel9deef432017-10-26 10:55:32 +02001059 periodic_hw_stats.update_dw.work);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001060
1061 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1062 goto out;
1063
1064 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
Nogah Frankel9deef432017-10-26 10:55:32 +02001065 &mlxsw_sp_port->periodic_hw_stats.stats);
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001066 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1067 &mlxsw_sp_port->periodic_hw_stats.xstats);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001068
1069out:
Nogah Frankel9deef432017-10-26 10:55:32 +02001070 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001071 MLXSW_HW_STATS_UPDATE_TIME);
1072}
1073
1074/* Return the stats from a cache that is updated periodically,
1075 * as this function might get called in an atomic context.
1076 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001077static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001078mlxsw_sp_port_get_stats64(struct net_device *dev,
1079 struct rtnl_link_stats64 *stats)
1080{
1081 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1082
Nogah Frankel9deef432017-10-26 10:55:32 +02001083 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001084}
1085
Jiri Pirko93cd0812017-04-18 16:55:35 +02001086static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1087 u16 vid_begin, u16 vid_end,
1088 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001089{
1090 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1091 char *spvm_pl;
1092 int err;
1093
1094 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1095 if (!spvm_pl)
1096 return -ENOMEM;
1097
1098 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1099 vid_end, is_member, untagged);
1100 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1101 kfree(spvm_pl);
1102 return err;
1103}
1104
Jiri Pirko93cd0812017-04-18 16:55:35 +02001105int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1106 u16 vid_end, bool is_member, bool untagged)
1107{
1108 u16 vid, vid_e;
1109 int err;
1110
1111 for (vid = vid_begin; vid <= vid_end;
1112 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1113 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1114 vid_end);
1115
1116 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1117 is_member, untagged);
1118 if (err)
1119 return err;
1120 }
1121
1122 return 0;
1123}
1124
Ido Schimmelc57529e2017-05-26 08:37:31 +02001125static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001126{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001127 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001128
Ido Schimmelc57529e2017-05-26 08:37:31 +02001129 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1130 &mlxsw_sp_port->vlans_list, list)
1131 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001132}
1133
Ido Schimmel31a08a52017-05-26 08:37:26 +02001134static struct mlxsw_sp_port_vlan *
1135mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1136{
1137 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001138 bool untagged = vid == 1;
1139 int err;
1140
1141 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1142 if (err)
1143 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001144
1145 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001146 if (!mlxsw_sp_port_vlan) {
1147 err = -ENOMEM;
1148 goto err_port_vlan_alloc;
1149 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02001150
1151 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1152 mlxsw_sp_port_vlan->vid = vid;
1153 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1154
1155 return mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001156
1157err_port_vlan_alloc:
1158 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1159 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001160}
1161
1162static void
1163mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1164{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001165 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1166 u16 vid = mlxsw_sp_port_vlan->vid;
Ido Schimmel7cbecf22017-05-26 08:37:28 +02001167
Ido Schimmel31a08a52017-05-26 08:37:26 +02001168 list_del(&mlxsw_sp_port_vlan->list);
1169 kfree(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001170 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1171}
1172
1173struct mlxsw_sp_port_vlan *
1174mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1175{
1176 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1177
1178 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1179 if (mlxsw_sp_port_vlan)
1180 return mlxsw_sp_port_vlan;
1181
1182 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1183}
1184
1185void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1186{
Ido Schimmela1107482017-05-26 08:37:39 +02001187 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1188
Ido Schimmelc57529e2017-05-26 08:37:31 +02001189 if (mlxsw_sp_port_vlan->bridge_port)
1190 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
Ido Schimmela1107482017-05-26 08:37:39 +02001191 else if (fid)
1192 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001193
1194 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001195}
1196
Ido Schimmel05978482016-08-17 16:39:30 +02001197static int mlxsw_sp_port_add_vid(struct net_device *dev,
1198 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001199{
1200 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001201
1202 /* VLAN 0 is added to HW filter when device goes up, but it is
1203 * reserved in our case, so simply return.
1204 */
1205 if (!vid)
1206 return 0;
1207
Ido Schimmelc57529e2017-05-26 08:37:31 +02001208 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001209}
1210
Ido Schimmel32d863f2016-07-02 11:00:10 +02001211static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1212 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001213{
1214 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001215 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001216
1217 /* VLAN 0 is removed from HW filter when device goes down, but
1218 * it is reserved in our case, so simply return.
1219 */
1220 if (!vid)
1221 return 0;
1222
Ido Schimmel31a08a52017-05-26 08:37:26 +02001223 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001224 if (!mlxsw_sp_port_vlan)
Ido Schimmel31a08a52017-05-26 08:37:26 +02001225 return 0;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001226 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001227
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001228 return 0;
1229}
1230
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001231static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1232 size_t len)
1233{
1234 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +02001235 u8 module = mlxsw_sp_port->mapping.module;
1236 u8 width = mlxsw_sp_port->mapping.width;
1237 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001238 int err;
1239
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001240 if (!mlxsw_sp_port->split)
1241 err = snprintf(name, len, "p%d", module + 1);
1242 else
1243 err = snprintf(name, len, "p%ds%d", module + 1,
1244 lane / width);
1245
1246 if (err >= len)
1247 return -EINVAL;
1248
1249 return 0;
1250}
1251
Yotam Gigi763b4b72016-07-21 12:03:17 +02001252static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001253mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1254 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001255 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1256
1257 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1258 if (mall_tc_entry->cookie == cookie)
1259 return mall_tc_entry;
1260
1261 return NULL;
1262}
1263
1264static int
1265mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001266 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001267 const struct tc_action *a,
1268 bool ingress)
1269{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001270 enum mlxsw_sp_span_type span_type;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001271 struct net_device *to_dev;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001272
Cong Wang9f8a7392017-12-05 16:17:26 -08001273 to_dev = tcf_mirred_dev(a);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001274 if (!to_dev) {
1275 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1276 return -EINVAL;
1277 }
1278
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001279 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001280 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Petr Machata079c9f32018-02-27 14:53:44 +01001281 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type,
Petr Machata98977082018-02-27 14:53:41 +01001282 true, &mirror->span_id);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001283}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001284
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001285static void
1286mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1287 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1288{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001289 enum mlxsw_sp_span_type span_type;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001290
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001291 span_type = mirror->ingress ?
1292 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Petr Machata98977082018-02-27 14:53:41 +01001293 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +01001294 span_type, true);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001295}
1296
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001297static int
1298mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1299 struct tc_cls_matchall_offload *cls,
1300 const struct tc_action *a,
1301 bool ingress)
1302{
1303 int err;
1304
1305 if (!mlxsw_sp_port->sample)
1306 return -EOPNOTSUPP;
1307 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1308 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1309 return -EEXIST;
1310 }
1311 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1312 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1313 return -EOPNOTSUPP;
1314 }
1315
1316 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1317 tcf_sample_psample_group(a));
1318 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1319 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1320 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1321
1322 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1323 if (err)
1324 goto err_port_sample_set;
1325 return 0;
1326
1327err_port_sample_set:
1328 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1329 return err;
1330}
1331
1332static void
1333mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1334{
1335 if (!mlxsw_sp_port->sample)
1336 return;
1337
1338 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1339 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1340}
1341
Yotam Gigi763b4b72016-07-21 12:03:17 +02001342static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001343 struct tc_cls_matchall_offload *f,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001344 bool ingress)
1345{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001346 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001347 __be16 protocol = f->common.protocol;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001348 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001349 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001350 int err;
1351
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001352 if (!tcf_exts_has_one_action(f->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001353 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001354 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001355 }
1356
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001357 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1358 if (!mall_tc_entry)
1359 return -ENOMEM;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001360 mall_tc_entry->cookie = f->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001361
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001362 tcf_exts_to_list(f->exts, &actions);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001363 a = list_first_entry(&actions, struct tc_action, list);
1364
1365 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1366 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1367
1368 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1369 mirror = &mall_tc_entry->mirror;
1370 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1371 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001372 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1373 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001374 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001375 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001376 } else {
1377 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001378 }
1379
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001380 if (err)
1381 goto err_add_action;
1382
1383 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001384 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001385
1386err_add_action:
1387 kfree(mall_tc_entry);
1388 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001389}
1390
1391static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001392 struct tc_cls_matchall_offload *f)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001393{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001394 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001395
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001396 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001397 f->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001398 if (!mall_tc_entry) {
1399 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1400 return;
1401 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001402 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001403
1404 switch (mall_tc_entry->type) {
1405 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001406 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1407 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001408 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001409 case MLXSW_SP_PORT_MALL_SAMPLE:
1410 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1411 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001412 default:
1413 WARN_ON(1);
1414 }
1415
Yotam Gigi763b4b72016-07-21 12:03:17 +02001416 kfree(mall_tc_entry);
1417}
1418
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001419static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001420 struct tc_cls_matchall_offload *f,
1421 bool ingress)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001422{
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001423 switch (f->command) {
1424 case TC_CLSMATCHALL_REPLACE:
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001425 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001426 ingress);
1427 case TC_CLSMATCHALL_DESTROY:
1428 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1429 return 0;
1430 default:
1431 return -EOPNOTSUPP;
1432 }
1433}
1434
1435static int
Jiri Pirko3aaff322018-01-17 11:46:56 +01001436mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1437 struct tc_cls_flower_offload *f)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001438{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001439 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1440
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001441 switch (f->command) {
1442 case TC_CLSFLOWER_REPLACE:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001443 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001444 case TC_CLSFLOWER_DESTROY:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001445 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001446 return 0;
1447 case TC_CLSFLOWER_STATS:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001448 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001449 default:
1450 return -EOPNOTSUPP;
1451 }
1452}
1453
Jiri Pirko3aaff322018-01-17 11:46:56 +01001454static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1455 void *type_data,
1456 void *cb_priv, bool ingress)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001457{
1458 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1459
1460 switch (type) {
1461 case TC_SETUP_CLSMATCHALL:
Jakub Kicinski15f4edb2018-01-25 14:00:51 -08001462 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1463 type_data))
Jiri Pirko3aaff322018-01-17 11:46:56 +01001464 return -EOPNOTSUPP;
1465
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001466 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1467 ingress);
1468 case TC_SETUP_CLSFLOWER:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001469 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001470 default:
1471 return -EOPNOTSUPP;
1472 }
1473}
1474
Jiri Pirko3aaff322018-01-17 11:46:56 +01001475static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1476 void *type_data,
1477 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001478{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001479 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1480 cb_priv, true);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001481}
1482
Jiri Pirko3aaff322018-01-17 11:46:56 +01001483static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1484 void *type_data,
1485 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001486{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001487 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1488 cb_priv, false);
1489}
1490
1491static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1492 void *type_data, void *cb_priv)
1493{
1494 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1495
1496 switch (type) {
1497 case TC_SETUP_CLSMATCHALL:
1498 return 0;
1499 case TC_SETUP_CLSFLOWER:
1500 if (mlxsw_sp_acl_block_disabled(acl_block))
1501 return -EOPNOTSUPP;
1502
1503 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1504 default:
1505 return -EOPNOTSUPP;
1506 }
1507}
1508
1509static int
1510mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1511 struct tcf_block *block, bool ingress)
1512{
1513 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1514 struct mlxsw_sp_acl_block *acl_block;
1515 struct tcf_block_cb *block_cb;
1516 int err;
1517
1518 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1519 mlxsw_sp);
1520 if (!block_cb) {
1521 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1522 if (!acl_block)
1523 return -ENOMEM;
1524 block_cb = __tcf_block_cb_register(block,
1525 mlxsw_sp_setup_tc_block_cb_flower,
1526 mlxsw_sp, acl_block);
1527 if (IS_ERR(block_cb)) {
1528 err = PTR_ERR(block_cb);
1529 goto err_cb_register;
1530 }
1531 } else {
1532 acl_block = tcf_block_cb_priv(block_cb);
1533 }
1534 tcf_block_cb_incref(block_cb);
1535 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1536 mlxsw_sp_port, ingress);
1537 if (err)
1538 goto err_block_bind;
1539
1540 if (ingress)
1541 mlxsw_sp_port->ing_acl_block = acl_block;
1542 else
1543 mlxsw_sp_port->eg_acl_block = acl_block;
1544
1545 return 0;
1546
1547err_block_bind:
1548 if (!tcf_block_cb_decref(block_cb)) {
1549 __tcf_block_cb_unregister(block_cb);
1550err_cb_register:
1551 mlxsw_sp_acl_block_destroy(acl_block);
1552 }
1553 return err;
1554}
1555
1556static void
1557mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1558 struct tcf_block *block, bool ingress)
1559{
1560 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1561 struct mlxsw_sp_acl_block *acl_block;
1562 struct tcf_block_cb *block_cb;
1563 int err;
1564
1565 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1566 mlxsw_sp);
1567 if (!block_cb)
1568 return;
1569
1570 if (ingress)
1571 mlxsw_sp_port->ing_acl_block = NULL;
1572 else
1573 mlxsw_sp_port->eg_acl_block = NULL;
1574
1575 acl_block = tcf_block_cb_priv(block_cb);
1576 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1577 mlxsw_sp_port, ingress);
1578 if (!err && !tcf_block_cb_decref(block_cb)) {
1579 __tcf_block_cb_unregister(block_cb);
1580 mlxsw_sp_acl_block_destroy(acl_block);
1581 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001582}
1583
1584static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1585 struct tc_block_offload *f)
1586{
1587 tc_setup_cb_t *cb;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001588 bool ingress;
1589 int err;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001590
Jiri Pirko3aaff322018-01-17 11:46:56 +01001591 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1592 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1593 ingress = true;
1594 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1595 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1596 ingress = false;
1597 } else {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001598 return -EOPNOTSUPP;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001599 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001600
1601 switch (f->command) {
1602 case TC_BLOCK_BIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001603 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1604 mlxsw_sp_port);
1605 if (err)
1606 return err;
1607 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
1608 f->block, ingress);
1609 if (err) {
1610 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1611 return err;
1612 }
1613 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001614 case TC_BLOCK_UNBIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001615 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1616 f->block, ingress);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001617 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1618 return 0;
1619 default:
1620 return -EOPNOTSUPP;
1621 }
1622}
1623
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001624static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
Jiri Pirkode4784c2017-08-07 10:15:32 +02001625 void *type_data)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001626{
1627 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1628
Jiri Pirko2572ac52017-08-07 10:15:17 +02001629 switch (type) {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001630 case TC_SETUP_BLOCK:
1631 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
Nogah Frankel96f17e02017-11-06 07:23:45 +01001632 case TC_SETUP_QDISC_RED:
1633 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
Nogah Frankel46a36152018-01-14 12:33:16 +01001634 case TC_SETUP_QDISC_PRIO:
1635 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
Jiri Pirko2572ac52017-08-07 10:15:17 +02001636 default:
1637 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001638 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001639}
1640
Jiri Pirko9454d932017-12-06 09:41:12 +01001641
1642static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1643{
1644 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1645
Jiri Pirko3aaff322018-01-17 11:46:56 +01001646 if (!enable) {
1647 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1648 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1649 !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1650 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1651 return -EINVAL;
1652 }
1653 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1654 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1655 } else {
1656 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1657 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
Jiri Pirko9454d932017-12-06 09:41:12 +01001658 }
1659 return 0;
1660}
1661
1662typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1663
1664static int mlxsw_sp_handle_feature(struct net_device *dev,
1665 netdev_features_t wanted_features,
1666 netdev_features_t feature,
1667 mlxsw_sp_feature_handler feature_handler)
1668{
1669 netdev_features_t changes = wanted_features ^ dev->features;
1670 bool enable = !!(wanted_features & feature);
1671 int err;
1672
1673 if (!(changes & feature))
1674 return 0;
1675
1676 err = feature_handler(dev, enable);
1677 if (err) {
1678 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1679 enable ? "Enable" : "Disable", &feature, err);
1680 return err;
1681 }
1682
1683 if (enable)
1684 dev->features |= feature;
1685 else
1686 dev->features &= ~feature;
1687
1688 return 0;
1689}
1690static int mlxsw_sp_set_features(struct net_device *dev,
1691 netdev_features_t features)
1692{
1693 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1694 mlxsw_sp_feature_hw_tc);
1695}
1696
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001697static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1698 .ndo_open = mlxsw_sp_port_open,
1699 .ndo_stop = mlxsw_sp_port_stop,
1700 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001701 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001702 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001703 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1704 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1705 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001706 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1707 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001708 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1709 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001710 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko9454d932017-12-06 09:41:12 +01001711 .ndo_set_features = mlxsw_sp_set_features,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001712};
1713
1714static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1715 struct ethtool_drvinfo *drvinfo)
1716{
1717 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1718 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1719
1720 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1721 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1722 sizeof(drvinfo->version));
1723 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1724 "%d.%d.%d",
1725 mlxsw_sp->bus_info->fw_rev.major,
1726 mlxsw_sp->bus_info->fw_rev.minor,
1727 mlxsw_sp->bus_info->fw_rev.subminor);
1728 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1729 sizeof(drvinfo->bus_info));
1730}
1731
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001732static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1733 struct ethtool_pauseparam *pause)
1734{
1735 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1736
1737 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1738 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1739}
1740
1741static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1742 struct ethtool_pauseparam *pause)
1743{
1744 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1745
1746 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1747 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1748 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1749
1750 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1751 pfcc_pl);
1752}
1753
1754static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1755 struct ethtool_pauseparam *pause)
1756{
1757 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1758 bool pause_en = pause->tx_pause || pause->rx_pause;
1759 int err;
1760
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001761 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1762 netdev_err(dev, "PFC already enabled on port\n");
1763 return -EINVAL;
1764 }
1765
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001766 if (pause->autoneg) {
1767 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1768 return -EINVAL;
1769 }
1770
1771 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1772 if (err) {
1773 netdev_err(dev, "Failed to configure port's headroom\n");
1774 return err;
1775 }
1776
1777 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1778 if (err) {
1779 netdev_err(dev, "Failed to set PAUSE parameters\n");
1780 goto err_port_pause_configure;
1781 }
1782
1783 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1784 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1785
1786 return 0;
1787
1788err_port_pause_configure:
1789 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1790 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1791 return err;
1792}
1793
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001794struct mlxsw_sp_port_hw_stats {
1795 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02001796 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01001797 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001798};
1799
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001800static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001801 {
1802 .str = "a_frames_transmitted_ok",
1803 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1804 },
1805 {
1806 .str = "a_frames_received_ok",
1807 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1808 },
1809 {
1810 .str = "a_frame_check_sequence_errors",
1811 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1812 },
1813 {
1814 .str = "a_alignment_errors",
1815 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1816 },
1817 {
1818 .str = "a_octets_transmitted_ok",
1819 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1820 },
1821 {
1822 .str = "a_octets_received_ok",
1823 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1824 },
1825 {
1826 .str = "a_multicast_frames_xmitted_ok",
1827 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1828 },
1829 {
1830 .str = "a_broadcast_frames_xmitted_ok",
1831 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1832 },
1833 {
1834 .str = "a_multicast_frames_received_ok",
1835 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1836 },
1837 {
1838 .str = "a_broadcast_frames_received_ok",
1839 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1840 },
1841 {
1842 .str = "a_in_range_length_errors",
1843 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1844 },
1845 {
1846 .str = "a_out_of_range_length_field",
1847 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1848 },
1849 {
1850 .str = "a_frame_too_long_errors",
1851 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1852 },
1853 {
1854 .str = "a_symbol_error_during_carrier",
1855 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1856 },
1857 {
1858 .str = "a_mac_control_frames_transmitted",
1859 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1860 },
1861 {
1862 .str = "a_mac_control_frames_received",
1863 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1864 },
1865 {
1866 .str = "a_unsupported_opcodes_received",
1867 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1868 },
1869 {
1870 .str = "a_pause_mac_ctrl_frames_received",
1871 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1872 },
1873 {
1874 .str = "a_pause_mac_ctrl_frames_xmitted",
1875 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1876 },
1877};
1878
1879#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1880
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001881static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1882 {
1883 .str = "rx_octets_prio",
1884 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1885 },
1886 {
1887 .str = "rx_frames_prio",
1888 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1889 },
1890 {
1891 .str = "tx_octets_prio",
1892 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1893 },
1894 {
1895 .str = "tx_frames_prio",
1896 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1897 },
1898 {
1899 .str = "rx_pause_prio",
1900 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1901 },
1902 {
1903 .str = "rx_pause_duration_prio",
1904 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1905 },
1906 {
1907 .str = "tx_pause_prio",
1908 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1909 },
1910 {
1911 .str = "tx_pause_duration_prio",
1912 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1913 },
1914};
1915
1916#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1917
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001918static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1919 {
1920 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01001921 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1922 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001923 },
1924 {
1925 .str = "tc_no_buffer_discard_uc_tc",
1926 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1927 },
1928};
1929
1930#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1931
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001932#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001933 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1934 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001935 IEEE_8021QAZ_MAX_TCS)
1936
1937static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1938{
1939 int i;
1940
1941 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1942 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1943 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1944 *p += ETH_GSTRING_LEN;
1945 }
1946}
1947
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001948static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1949{
1950 int i;
1951
1952 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1953 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1954 mlxsw_sp_port_hw_tc_stats[i].str, tc);
1955 *p += ETH_GSTRING_LEN;
1956 }
1957}
1958
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001959static void mlxsw_sp_port_get_strings(struct net_device *dev,
1960 u32 stringset, u8 *data)
1961{
1962 u8 *p = data;
1963 int i;
1964
1965 switch (stringset) {
1966 case ETH_SS_STATS:
1967 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1968 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1969 ETH_GSTRING_LEN);
1970 p += ETH_GSTRING_LEN;
1971 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001972
1973 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1974 mlxsw_sp_port_get_prio_strings(&p, i);
1975
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001976 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1977 mlxsw_sp_port_get_tc_strings(&p, i);
1978
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001979 break;
1980 }
1981}
1982
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001983static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1984 enum ethtool_phys_id_state state)
1985{
1986 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1987 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1988 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1989 bool active;
1990
1991 switch (state) {
1992 case ETHTOOL_ID_ACTIVE:
1993 active = true;
1994 break;
1995 case ETHTOOL_ID_INACTIVE:
1996 active = false;
1997 break;
1998 default:
1999 return -EOPNOTSUPP;
2000 }
2001
2002 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2003 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2004}
2005
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002006static int
2007mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2008 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2009{
2010 switch (grp) {
2011 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2012 *p_hw_stats = mlxsw_sp_port_hw_stats;
2013 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2014 break;
2015 case MLXSW_REG_PPCNT_PRIO_CNT:
2016 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2017 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2018 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002019 case MLXSW_REG_PPCNT_TC_CNT:
2020 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2021 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2022 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002023 default:
2024 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002025 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002026 }
2027 return 0;
2028}
2029
2030static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2031 enum mlxsw_reg_ppcnt_grp grp, int prio,
2032 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002033{
Ido Schimmel18281f22017-03-24 08:02:51 +01002034 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2035 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002036 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002037 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002038 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002039 int err;
2040
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002041 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2042 if (err)
2043 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002044 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002045 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002046 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002047 if (!hw_stats[i].cells_bytes)
2048 continue;
2049 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2050 data[data_index + i]);
2051 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002052}
2053
2054static void mlxsw_sp_port_get_stats(struct net_device *dev,
2055 struct ethtool_stats *stats, u64 *data)
2056{
2057 int i, data_index = 0;
2058
2059 /* IEEE 802.3 Counters */
2060 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2061 data, data_index);
2062 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2063
2064 /* Per-Priority Counters */
2065 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2066 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2067 data, data_index);
2068 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2069 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002070
2071 /* Per-TC Counters */
2072 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2073 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2074 data, data_index);
2075 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2076 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002077}
2078
2079static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2080{
2081 switch (sset) {
2082 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002083 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002084 default:
2085 return -EOPNOTSUPP;
2086 }
2087}
2088
2089struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002090 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002091 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002092 u32 speed;
2093};
2094
2095static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2096 {
2097 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002098 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2099 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002100 },
2101 {
2102 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2103 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002104 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2105 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002106 },
2107 {
2108 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002109 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2110 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002111 },
2112 {
2113 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2114 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002115 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2116 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002117 },
2118 {
2119 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2120 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2121 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2122 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002123 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2124 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002125 },
2126 {
2127 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002128 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2129 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002130 },
2131 {
2132 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002133 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2134 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002135 },
2136 {
2137 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002138 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2139 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002140 },
2141 {
2142 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002143 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2144 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002145 },
2146 {
2147 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002148 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2149 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002150 },
2151 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002152 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2153 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2154 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002155 },
2156 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002157 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2158 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2159 .speed = SPEED_25000,
2160 },
2161 {
2162 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2163 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2164 .speed = SPEED_25000,
2165 },
2166 {
2167 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2168 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2169 .speed = SPEED_25000,
2170 },
2171 {
2172 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2173 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2174 .speed = SPEED_50000,
2175 },
2176 {
2177 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2178 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2179 .speed = SPEED_50000,
2180 },
2181 {
2182 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2183 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2184 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002185 },
2186 {
2187 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002188 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2189 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002190 },
2191 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002192 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2193 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2194 .speed = SPEED_56000,
2195 },
2196 {
2197 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2198 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2199 .speed = SPEED_56000,
2200 },
2201 {
2202 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2203 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2204 .speed = SPEED_56000,
2205 },
2206 {
2207 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2208 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2209 .speed = SPEED_100000,
2210 },
2211 {
2212 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2213 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2214 .speed = SPEED_100000,
2215 },
2216 {
2217 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2218 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2219 .speed = SPEED_100000,
2220 },
2221 {
2222 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2223 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2224 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002225 },
2226};
2227
2228#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2229
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002230static void
2231mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2232 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002233{
2234 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2235 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2236 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2237 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2238 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2239 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002240 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002241
2242 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2243 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2244 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2245 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2246 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002247 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002248}
2249
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002250static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002251{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002252 int i;
2253
2254 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2255 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002256 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2257 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002258 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002259}
2260
2261static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002262 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002263{
2264 u32 speed = SPEED_UNKNOWN;
2265 u8 duplex = DUPLEX_UNKNOWN;
2266 int i;
2267
2268 if (!carrier_ok)
2269 goto out;
2270
2271 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2272 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2273 speed = mlxsw_sp_port_link_mode[i].speed;
2274 duplex = DUPLEX_FULL;
2275 break;
2276 }
2277 }
2278out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002279 cmd->base.speed = speed;
2280 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002281}
2282
2283static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2284{
2285 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2286 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2287 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2288 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2289 return PORT_FIBRE;
2290
2291 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2292 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2293 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2294 return PORT_DA;
2295
2296 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2297 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2298 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2299 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2300 return PORT_NONE;
2301
2302 return PORT_OTHER;
2303}
2304
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002305static u32
2306mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002307{
2308 u32 ptys_proto = 0;
2309 int i;
2310
2311 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002312 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2313 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002314 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2315 }
2316 return ptys_proto;
2317}
2318
2319static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2320{
2321 u32 ptys_proto = 0;
2322 int i;
2323
2324 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2325 if (speed == mlxsw_sp_port_link_mode[i].speed)
2326 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2327 }
2328 return ptys_proto;
2329}
2330
Ido Schimmel18f1e702016-02-26 17:32:31 +01002331static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2332{
2333 u32 ptys_proto = 0;
2334 int i;
2335
2336 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2337 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2338 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2339 }
2340 return ptys_proto;
2341}
2342
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002343static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2344 struct ethtool_link_ksettings *cmd)
2345{
2346 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2347 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2348 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2349
2350 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2351 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2352}
2353
2354static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2355 struct ethtool_link_ksettings *cmd)
2356{
2357 if (!autoneg)
2358 return;
2359
2360 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2361 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2362}
2363
2364static void
2365mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2366 struct ethtool_link_ksettings *cmd)
2367{
2368 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2369 return;
2370
2371 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2372 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2373}
2374
2375static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2376 struct ethtool_link_ksettings *cmd)
2377{
2378 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2379 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2380 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2381 char ptys_pl[MLXSW_REG_PTYS_LEN];
2382 u8 autoneg_status;
2383 bool autoneg;
2384 int err;
2385
2386 autoneg = mlxsw_sp_port->link.autoneg;
Elad Raz401c8b42016-10-28 21:35:52 +02002387 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002388 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2389 if (err)
2390 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002391 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2392 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002393
2394 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2395
2396 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2397
2398 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2399 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2400 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2401
2402 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2403 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2404 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2405 cmd);
2406
2407 return 0;
2408}
2409
2410static int
2411mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2412 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002413{
2414 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2415 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2416 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002417 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002418 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002419 int err;
2420
Elad Raz401c8b42016-10-28 21:35:52 +02002421 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002422 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002423 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002424 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002425 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002426
2427 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2428 eth_proto_new = autoneg ?
2429 mlxsw_sp_to_ptys_advert_link(cmd) :
2430 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002431
2432 eth_proto_new = eth_proto_new & eth_proto_cap;
2433 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002434 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002435 return -EINVAL;
2436 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002437
Elad Raz401c8b42016-10-28 21:35:52 +02002438 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2439 eth_proto_new);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002440 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002441 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002442 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002443
Ido Schimmel6277d462016-07-15 11:14:58 +02002444 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002445 return 0;
2446
Ido Schimmel0c83f882016-09-12 13:26:23 +02002447 mlxsw_sp_port->link.autoneg = autoneg;
2448
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002449 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2450 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002451
2452 return 0;
2453}
2454
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002455static int mlxsw_sp_flash_device(struct net_device *dev,
2456 struct ethtool_flash *flash)
2457{
2458 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2459 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2460 const struct firmware *firmware;
2461 int err;
2462
2463 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2464 return -EOPNOTSUPP;
2465
2466 dev_hold(dev);
2467 rtnl_unlock();
2468
2469 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2470 if (err)
2471 goto out;
2472 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2473 release_firmware(firmware);
2474out:
2475 rtnl_lock();
2476 dev_put(dev);
2477 return err;
2478}
2479
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002480#define MLXSW_SP_I2C_ADDR_LOW 0x50
2481#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2482#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002483
2484static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2485 u16 offset, u16 size, void *data,
2486 unsigned int *p_read_size)
2487{
2488 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2489 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2490 char mcia_pl[MLXSW_REG_MCIA_LEN];
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002491 u16 i2c_addr;
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002492 int status;
2493 int err;
2494
2495 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002496
2497 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2498 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2499 /* Cross pages read, read until offset 256 in low page */
2500 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2501
2502 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2503 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2504 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2505 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2506 }
2507
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002508 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002509 0, 0, offset, size, i2c_addr);
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002510
2511 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2512 if (err)
2513 return err;
2514
2515 status = mlxsw_reg_mcia_status_get(mcia_pl);
2516 if (status)
2517 return -EIO;
2518
2519 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2520 memcpy(data, eeprom_tmp, size);
2521 *p_read_size = size;
2522
2523 return 0;
2524}
2525
2526enum mlxsw_sp_eeprom_module_info_rev_id {
2527 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2528 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2529 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2530};
2531
2532enum mlxsw_sp_eeprom_module_info_id {
2533 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2534 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2535 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2536 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2537};
2538
2539enum mlxsw_sp_eeprom_module_info {
2540 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2541 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2542 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2543};
2544
2545static int mlxsw_sp_get_module_info(struct net_device *netdev,
2546 struct ethtool_modinfo *modinfo)
2547{
2548 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2549 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2550 u8 module_rev_id, module_id;
2551 unsigned int read_size;
2552 int err;
2553
2554 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2555 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2556 module_info, &read_size);
2557 if (err)
2558 return err;
2559
2560 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2561 return -EIO;
2562
2563 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2564 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2565
2566 switch (module_id) {
2567 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2568 modinfo->type = ETH_MODULE_SFF_8436;
2569 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2570 break;
2571 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2572 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2573 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2574 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2575 modinfo->type = ETH_MODULE_SFF_8636;
2576 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2577 } else {
2578 modinfo->type = ETH_MODULE_SFF_8436;
2579 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2580 }
2581 break;
2582 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2583 modinfo->type = ETH_MODULE_SFF_8472;
2584 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2585 break;
2586 default:
2587 return -EINVAL;
2588 }
2589
2590 return 0;
2591}
2592
2593static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2594 struct ethtool_eeprom *ee,
2595 u8 *data)
2596{
2597 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2598 int offset = ee->offset;
2599 unsigned int read_size;
2600 int i = 0;
2601 int err;
2602
2603 if (!ee->len)
2604 return -EINVAL;
2605
2606 memset(data, 0, ee->len);
2607
2608 while (i < ee->len) {
2609 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2610 ee->len - i, data + i,
2611 &read_size);
2612 if (err) {
2613 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2614 return err;
2615 }
2616
2617 i += read_size;
2618 offset += read_size;
2619 }
2620
2621 return 0;
2622}
2623
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002624static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2625 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2626 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002627 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2628 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002629 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002630 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002631 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2632 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002633 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2634 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002635 .flash_device = mlxsw_sp_flash_device,
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002636 .get_module_info = mlxsw_sp_get_module_info,
2637 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002638};
2639
Ido Schimmel18f1e702016-02-26 17:32:31 +01002640static int
2641mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2642{
2643 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2644 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2645 char ptys_pl[MLXSW_REG_PTYS_LEN];
2646 u32 eth_proto_admin;
2647
2648 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002649 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2650 eth_proto_admin);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002651 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2652}
2653
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002654int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2655 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2656 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002657{
2658 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2659 char qeec_pl[MLXSW_REG_QEEC_LEN];
2660
2661 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2662 next_index);
2663 mlxsw_reg_qeec_de_set(qeec_pl, true);
2664 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2665 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2666 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2667}
2668
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002669int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2670 enum mlxsw_reg_qeec_hr hr, u8 index,
2671 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002672{
2673 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2674 char qeec_pl[MLXSW_REG_QEEC_LEN];
2675
2676 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2677 next_index);
2678 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2679 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2680 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2681}
2682
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002683int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2684 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002685{
2686 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2687 char qtct_pl[MLXSW_REG_QTCT_LEN];
2688
2689 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2690 tclass);
2691 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2692}
2693
2694static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2695{
2696 int err, i;
2697
2698 /* Setup the elements hierarcy, so that each TC is linked to
2699 * one subgroup, which are all member in the same group.
2700 */
2701 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2702 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2703 0);
2704 if (err)
2705 return err;
2706 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2707 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2708 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2709 0, false, 0);
2710 if (err)
2711 return err;
2712 }
2713 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2714 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2715 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2716 false, 0);
2717 if (err)
2718 return err;
2719 }
2720
2721 /* Make sure the max shaper is disabled in all hierarcies that
2722 * support it.
2723 */
2724 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2725 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2726 MLXSW_REG_QEEC_MAS_DIS);
2727 if (err)
2728 return err;
2729 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2730 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2731 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2732 i, 0,
2733 MLXSW_REG_QEEC_MAS_DIS);
2734 if (err)
2735 return err;
2736 }
2737 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2738 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2739 MLXSW_REG_QEEC_HIERARCY_TC,
2740 i, i,
2741 MLXSW_REG_QEEC_MAS_DIS);
2742 if (err)
2743 return err;
2744 }
2745
2746 /* Map all priorities to traffic class 0. */
2747 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2748 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2749 if (err)
2750 return err;
2751 }
2752
2753 return 0;
2754}
2755
Ido Schimmel5b153852017-06-08 08:47:44 +02002756static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2757 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002758{
Ido Schimmelc57529e2017-05-26 08:37:31 +02002759 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002760 struct mlxsw_sp_port *mlxsw_sp_port;
2761 struct net_device *dev;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002762 int err;
2763
Ido Schimmel5b153852017-06-08 08:47:44 +02002764 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2765 if (err) {
2766 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2767 local_port);
2768 return err;
2769 }
2770
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002771 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
Ido Schimmel5b153852017-06-08 08:47:44 +02002772 if (!dev) {
2773 err = -ENOMEM;
2774 goto err_alloc_etherdev;
2775 }
Jiri Pirkof20a91f2016-10-27 15:13:00 +02002776 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002777 mlxsw_sp_port = netdev_priv(dev);
2778 mlxsw_sp_port->dev = dev;
2779 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2780 mlxsw_sp_port->local_port = local_port;
Ido Schimmelc57529e2017-05-26 08:37:31 +02002781 mlxsw_sp_port->pvid = 1;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002782 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02002783 mlxsw_sp_port->mapping.module = module;
2784 mlxsw_sp_port->mapping.width = width;
2785 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002786 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02002787 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02002788 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002789
2790 mlxsw_sp_port->pcpu_stats =
2791 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2792 if (!mlxsw_sp_port->pcpu_stats) {
2793 err = -ENOMEM;
2794 goto err_alloc_stats;
2795 }
2796
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002797 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2798 GFP_KERNEL);
2799 if (!mlxsw_sp_port->sample) {
2800 err = -ENOMEM;
2801 goto err_alloc_sample;
2802 }
2803
Nogah Frankel9deef432017-10-26 10:55:32 +02002804 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002805 &update_stats_cache);
2806
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002807 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2808 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2809
Ido Schimmel2e915e02017-06-08 08:47:45 +02002810 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
Ido Schimmel5b153852017-06-08 08:47:44 +02002811 if (err) {
2812 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2813 mlxsw_sp_port->local_port);
2814 goto err_port_module_map;
2815 }
2816
Ido Schimmel3247ff22016-09-08 08:16:02 +02002817 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2818 if (err) {
2819 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2820 mlxsw_sp_port->local_port);
2821 goto err_port_swid_set;
2822 }
2823
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002824 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2825 if (err) {
2826 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2827 mlxsw_sp_port->local_port);
2828 goto err_dev_addr_init;
2829 }
2830
2831 netif_carrier_off(dev);
2832
2833 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02002834 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2835 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002836
Jarod Wilsond894be52016-10-20 13:55:16 -04002837 dev->min_mtu = 0;
2838 dev->max_mtu = ETH_MAX_MTU;
2839
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002840 /* Each packet needs to have a Tx header (metadata) on top all other
2841 * headers.
2842 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02002843 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002844
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002845 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2846 if (err) {
2847 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2848 mlxsw_sp_port->local_port);
2849 goto err_port_system_port_mapping_set;
2850 }
2851
Ido Schimmel18f1e702016-02-26 17:32:31 +01002852 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2853 if (err) {
2854 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2855 mlxsw_sp_port->local_port);
2856 goto err_port_speed_by_width_set;
2857 }
2858
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002859 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2860 if (err) {
2861 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2862 mlxsw_sp_port->local_port);
2863 goto err_port_mtu_set;
2864 }
2865
2866 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2867 if (err)
2868 goto err_port_admin_status_set;
2869
2870 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2871 if (err) {
2872 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2873 mlxsw_sp_port->local_port);
2874 goto err_port_buffers_init;
2875 }
2876
Ido Schimmel90183b92016-04-06 17:10:08 +02002877 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2878 if (err) {
2879 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2880 mlxsw_sp_port->local_port);
2881 goto err_port_ets_init;
2882 }
2883
Ido Schimmelf00817d2016-04-06 17:10:09 +02002884 /* ETS and buffers must be initialized before DCB. */
2885 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2886 if (err) {
2887 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2888 mlxsw_sp_port->local_port);
2889 goto err_port_dcb_init;
2890 }
2891
Ido Schimmela1107482017-05-26 08:37:39 +02002892 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
Ido Schimmel45a4a162017-05-16 19:38:35 +02002893 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02002894 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
Ido Schimmel45a4a162017-05-16 19:38:35 +02002895 mlxsw_sp_port->local_port);
Ido Schimmela1107482017-05-26 08:37:39 +02002896 goto err_port_fids_init;
Ido Schimmel45a4a162017-05-16 19:38:35 +02002897 }
2898
Nogah Frankel371b4372018-01-10 14:59:57 +01002899 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
2900 if (err) {
2901 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
2902 mlxsw_sp_port->local_port);
2903 goto err_port_qdiscs_init;
2904 }
2905
Ido Schimmelc57529e2017-05-26 08:37:31 +02002906 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
2907 if (IS_ERR(mlxsw_sp_port_vlan)) {
2908 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
Ido Schimmel05978482016-08-17 16:39:30 +02002909 mlxsw_sp_port->local_port);
Wei Yongjund86fd112017-11-06 11:11:28 +00002910 err = PTR_ERR(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002911 goto err_port_vlan_get;
Ido Schimmel05978482016-08-17 16:39:30 +02002912 }
2913
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002914 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02002915 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002916 err = register_netdev(dev);
2917 if (err) {
2918 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2919 mlxsw_sp_port->local_port);
2920 goto err_register_netdev;
2921 }
2922
Elad Razd808c7e2016-10-28 21:35:57 +02002923 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2924 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2925 module);
Nogah Frankel9deef432017-10-26 10:55:32 +02002926 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002927 return 0;
2928
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002929err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02002930 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002931 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002932 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
2933err_port_vlan_get:
Nogah Frankel371b4372018-01-10 14:59:57 +01002934 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
2935err_port_qdiscs_init:
Ido Schimmela1107482017-05-26 08:37:39 +02002936 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
2937err_port_fids_init:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03002938 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002939err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02002940err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002941err_port_buffers_init:
2942err_port_admin_status_set:
2943err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01002944err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002945err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002946err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02002947 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2948err_port_swid_set:
Ido Schimmel2e915e02017-06-08 08:47:45 +02002949 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Ido Schimmel5b153852017-06-08 08:47:44 +02002950err_port_module_map:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002951 kfree(mlxsw_sp_port->sample);
2952err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002953 free_percpu(mlxsw_sp_port->pcpu_stats);
2954err_alloc_stats:
2955 free_netdev(dev);
Ido Schimmel5b153852017-06-08 08:47:44 +02002956err_alloc_etherdev:
Jiri Pirko67963a32016-10-28 21:35:55 +02002957 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2958 return err;
2959}
2960
Ido Schimmel5b153852017-06-08 08:47:44 +02002961static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002962{
2963 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2964
Nogah Frankel9deef432017-10-26 10:55:32 +02002965 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02002966 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002967 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02002968 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002969 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002970 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Nogah Frankel371b4372018-01-10 14:59:57 +01002971 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
Ido Schimmela1107482017-05-26 08:37:39 +02002972 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002973 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01002974 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
Ido Schimmel2e915e02017-06-08 08:47:45 +02002975 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002976 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01002977 free_percpu(mlxsw_sp_port->pcpu_stats);
Ido Schimmel31a08a52017-05-26 08:37:26 +02002978 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002979 free_netdev(mlxsw_sp_port->dev);
Jiri Pirko67963a32016-10-28 21:35:55 +02002980 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2981}
2982
Jiri Pirkof83e2102016-10-28 21:35:49 +02002983static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2984{
2985 return mlxsw_sp->ports[local_port] != NULL;
2986}
2987
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002988static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2989{
2990 int i;
2991
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002992 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002993 if (mlxsw_sp_port_created(mlxsw_sp, i))
2994 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002995 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002996 kfree(mlxsw_sp->ports);
2997}
2998
2999static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3000{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003001 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02003002 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003003 size_t alloc_size;
3004 int i;
3005 int err;
3006
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003007 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003008 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3009 if (!mlxsw_sp->ports)
3010 return -ENOMEM;
3011
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003012 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3013 GFP_KERNEL);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003014 if (!mlxsw_sp->port_to_module) {
3015 err = -ENOMEM;
3016 goto err_port_to_module_alloc;
3017 }
3018
3019 for (i = 1; i < max_ports; i++) {
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003020 /* Mark as invalid */
3021 mlxsw_sp->port_to_module[i] = -1;
3022
Ido Schimmel558c2d52016-02-26 17:32:29 +01003023 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003024 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01003025 if (err)
3026 goto err_port_module_info_get;
3027 if (!width)
3028 continue;
3029 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02003030 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3031 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003032 if (err)
3033 goto err_port_create;
3034 }
3035 return 0;
3036
3037err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01003038err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003039 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003040 if (mlxsw_sp_port_created(mlxsw_sp, i))
3041 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003042 kfree(mlxsw_sp->port_to_module);
3043err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003044 kfree(mlxsw_sp->ports);
3045 return err;
3046}
3047
Ido Schimmel18f1e702016-02-26 17:32:31 +01003048static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3049{
3050 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3051
3052 return local_port - offset;
3053}
3054
Ido Schimmelbe945352016-06-09 09:51:39 +02003055static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3056 u8 module, unsigned int count)
3057{
3058 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3059 int err, i;
3060
3061 for (i = 0; i < count; i++) {
Ido Schimmelbe945352016-06-09 09:51:39 +02003062 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02003063 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02003064 if (err)
3065 goto err_port_create;
3066 }
3067
3068 return 0;
3069
3070err_port_create:
3071 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003072 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3073 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02003074 return err;
3075}
3076
3077static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3078 u8 base_port, unsigned int count)
3079{
3080 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3081 int i;
3082
3083 /* Split by four means we need to re-create two ports, otherwise
3084 * only one.
3085 */
3086 count = count / 2;
3087
3088 for (i = 0; i < count; i++) {
3089 local_port = base_port + i * 2;
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003090 if (mlxsw_sp->port_to_module[local_port] < 0)
3091 continue;
Ido Schimmelbe945352016-06-09 09:51:39 +02003092 module = mlxsw_sp->port_to_module[local_port];
3093
Ido Schimmelbe945352016-06-09 09:51:39 +02003094 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003095 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003096 }
3097}
3098
Jiri Pirkob2f10572016-04-08 19:11:23 +02003099static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3100 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003101{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003102 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003103 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003104 u8 module, cur_width, base_port;
3105 int i;
3106 int err;
3107
3108 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3109 if (!mlxsw_sp_port) {
3110 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3111 local_port);
3112 return -EINVAL;
3113 }
3114
Ido Schimmeld664b412016-06-09 09:51:40 +02003115 module = mlxsw_sp_port->mapping.module;
3116 cur_width = mlxsw_sp_port->mapping.width;
3117
Ido Schimmel18f1e702016-02-26 17:32:31 +01003118 if (count != 2 && count != 4) {
3119 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3120 return -EINVAL;
3121 }
3122
Ido Schimmel18f1e702016-02-26 17:32:31 +01003123 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3124 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3125 return -EINVAL;
3126 }
3127
3128 /* Make sure we have enough slave (even) ports for the split. */
3129 if (count == 2) {
3130 base_port = local_port;
3131 if (mlxsw_sp->ports[base_port + 1]) {
3132 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3133 return -EINVAL;
3134 }
3135 } else {
3136 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3137 if (mlxsw_sp->ports[base_port + 1] ||
3138 mlxsw_sp->ports[base_port + 3]) {
3139 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3140 return -EINVAL;
3141 }
3142 }
3143
3144 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003145 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3146 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003147
Ido Schimmelbe945352016-06-09 09:51:39 +02003148 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3149 if (err) {
3150 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3151 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003152 }
3153
3154 return 0;
3155
Ido Schimmelbe945352016-06-09 09:51:39 +02003156err_port_split_create:
3157 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003158 return err;
3159}
3160
Jiri Pirkob2f10572016-04-08 19:11:23 +02003161static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003162{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003163 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003164 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003165 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003166 unsigned int count;
3167 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003168
3169 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3170 if (!mlxsw_sp_port) {
3171 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3172 local_port);
3173 return -EINVAL;
3174 }
3175
3176 if (!mlxsw_sp_port->split) {
3177 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3178 return -EINVAL;
3179 }
3180
Ido Schimmeld664b412016-06-09 09:51:40 +02003181 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003182 count = cur_width == 1 ? 4 : 2;
3183
3184 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3185
3186 /* Determine which ports to remove. */
3187 if (count == 2 && local_port >= base_port + 2)
3188 base_port = base_port + 2;
3189
3190 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003191 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3192 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003193
Ido Schimmelbe945352016-06-09 09:51:39 +02003194 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003195
3196 return 0;
3197}
3198
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003199static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3200 char *pude_pl, void *priv)
3201{
3202 struct mlxsw_sp *mlxsw_sp = priv;
3203 struct mlxsw_sp_port *mlxsw_sp_port;
3204 enum mlxsw_reg_pude_oper_status status;
3205 u8 local_port;
3206
3207 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3208 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003209 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003210 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003211
3212 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3213 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3214 netdev_info(mlxsw_sp_port->dev, "link up\n");
3215 netif_carrier_on(mlxsw_sp_port->dev);
3216 } else {
3217 netdev_info(mlxsw_sp_port->dev, "link down\n");
3218 netif_carrier_off(mlxsw_sp_port->dev);
3219 }
3220}
3221
Nogah Frankel14eeda92016-11-25 10:33:32 +01003222static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3223 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003224{
3225 struct mlxsw_sp *mlxsw_sp = priv;
3226 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3227 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3228
3229 if (unlikely(!mlxsw_sp_port)) {
3230 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3231 local_port);
3232 return;
3233 }
3234
3235 skb->dev = mlxsw_sp_port->dev;
3236
3237 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3238 u64_stats_update_begin(&pcpu_stats->syncp);
3239 pcpu_stats->rx_packets++;
3240 pcpu_stats->rx_bytes += skb->len;
3241 u64_stats_update_end(&pcpu_stats->syncp);
3242
3243 skb->protocol = eth_type_trans(skb, skb->dev);
3244 netif_receive_skb(skb);
3245}
3246
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003247static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3248 void *priv)
3249{
3250 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003251 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003252}
3253
Yotam Gigia0040c82017-10-03 09:58:10 +02003254static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3255 u8 local_port, void *priv)
3256{
3257 skb->offload_mr_fwd_mark = 1;
3258 skb->offload_fwd_mark = 1;
3259 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3260}
3261
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003262static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3263 void *priv)
3264{
3265 struct mlxsw_sp *mlxsw_sp = priv;
3266 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3267 struct psample_group *psample_group;
3268 u32 size;
3269
3270 if (unlikely(!mlxsw_sp_port)) {
3271 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3272 local_port);
3273 goto out;
3274 }
3275 if (unlikely(!mlxsw_sp_port->sample)) {
3276 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3277 local_port);
3278 goto out;
3279 }
3280
3281 size = mlxsw_sp_port->sample->truncate ?
3282 mlxsw_sp_port->sample->trunc_size : skb->len;
3283
3284 rcu_read_lock();
3285 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3286 if (!psample_group)
3287 goto out_unlock;
3288 psample_sample_packet(psample_group, skb, size,
3289 mlxsw_sp_port->dev->ifindex, 0,
3290 mlxsw_sp_port->sample->rate);
3291out_unlock:
3292 rcu_read_unlock();
3293out:
3294 consume_skb(skb);
3295}
3296
Nogah Frankel117b0da2016-11-25 10:33:44 +01003297#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003298 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003299 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003300
Nogah Frankel117b0da2016-11-25 10:33:44 +01003301#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003302 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003303 _is_ctrl, SP_##_trap_group, DISCARD)
3304
Yotam Gigia0040c82017-10-03 09:58:10 +02003305#define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3306 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3307 _is_ctrl, SP_##_trap_group, DISCARD)
3308
Nogah Frankel117b0da2016-11-25 10:33:44 +01003309#define MLXSW_SP_EVENTL(_func, _trap_id) \
3310 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003311
Nogah Frankel45449132016-11-25 10:33:35 +01003312static const struct mlxsw_listener mlxsw_sp_listener[] = {
3313 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003314 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003315 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003316 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3317 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3318 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3319 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3320 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3321 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3322 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3323 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3324 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3325 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3326 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003327 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003328 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3329 false),
3330 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3331 false),
3332 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3333 false),
3334 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3335 false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003336 /* L3 traps */
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003337 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3338 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3339 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003340 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003341 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3342 false),
3343 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3344 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3345 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3346 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3347 false),
3348 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3349 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3350 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003351 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003352 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3353 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3354 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3355 false),
3356 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3357 false),
3358 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3359 false),
3360 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3361 false),
3362 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3363 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3364 false),
3365 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3366 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
Ido Schimmel7607dd32017-07-17 14:15:30 +02003367 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003368 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
Petr Machata86484de2017-09-02 23:49:27 +02003369 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003370 /* PKT Sample trap */
3371 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
Jiri Pirko0db7b382017-06-06 14:12:05 +02003372 false, SP_IP2ME, DISCARD),
3373 /* ACL trap */
3374 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
Yotam Gigib48cfc82017-09-19 10:00:20 +02003375 /* Multicast Router Traps */
3376 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3377 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3378 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
Yotam Gigia0040c82017-10-03 09:58:10 +02003379 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003380};
3381
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003382static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3383{
3384 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3385 enum mlxsw_reg_qpcr_ir_units ir_units;
3386 int max_cpu_policers;
3387 bool is_bytes;
3388 u8 burst_size;
3389 u32 rate;
3390 int i, err;
3391
3392 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3393 return -EIO;
3394
3395 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3396
3397 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3398 for (i = 0; i < max_cpu_policers; i++) {
3399 is_bytes = false;
3400 switch (i) {
3401 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3402 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3403 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3404 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003405 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3406 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003407 rate = 128;
3408 burst_size = 7;
3409 break;
3410 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003411 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003412 rate = 16 * 1024;
3413 burst_size = 10;
3414 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003415 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003416 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3417 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003418 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003419 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3420 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003421 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003422 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003423 rate = 1024;
3424 burst_size = 7;
3425 break;
3426 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3427 is_bytes = true;
3428 rate = 4 * 1024;
3429 burst_size = 4;
3430 break;
3431 default:
3432 continue;
3433 }
3434
3435 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3436 burst_size);
3437 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3438 if (err)
3439 return err;
3440 }
3441
3442 return 0;
3443}
3444
Nogah Frankel579c82e2016-11-25 10:33:42 +01003445static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003446{
3447 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003448 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003449 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003450 int max_trap_groups;
3451 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003452 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003453 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003454
3455 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3456 return -EIO;
3457
3458 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003459 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003460
3461 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003462 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003463 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003464 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3465 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3466 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3467 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003468 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003469 priority = 5;
3470 tc = 5;
3471 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003472 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003473 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3474 priority = 4;
3475 tc = 4;
3476 break;
3477 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3478 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003479 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003480 priority = 3;
3481 tc = 3;
3482 break;
3483 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003484 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003485 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003486 priority = 2;
3487 tc = 2;
3488 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003489 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003490 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3491 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003492 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003493 priority = 1;
3494 tc = 1;
3495 break;
3496 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003497 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3498 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003499 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003500 break;
3501 default:
3502 continue;
3503 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003504
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003505 if (max_cpu_policers <= policer_id &&
3506 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3507 return -EIO;
3508
3509 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003510 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3511 if (err)
3512 return err;
3513 }
3514
3515 return 0;
3516}
3517
3518static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3519{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003520 int i;
3521 int err;
3522
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003523 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3524 if (err)
3525 return err;
3526
Nogah Frankel579c82e2016-11-25 10:33:42 +01003527 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003528 if (err)
3529 return err;
3530
Nogah Frankel45449132016-11-25 10:33:35 +01003531 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003532 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003533 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003534 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003535 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003536 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003537
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003538 }
3539 return 0;
3540
Nogah Frankel45449132016-11-25 10:33:35 +01003541err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003542 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003543 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003544 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003545 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003546 }
3547 return err;
3548}
3549
3550static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3551{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003552 int i;
3553
Nogah Frankel45449132016-11-25 10:33:35 +01003554 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003555 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003556 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003557 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003558 }
3559}
3560
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003561static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3562{
3563 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003564 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003565
3566 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3567 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3568 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3569 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3570 MLXSW_REG_SLCR_LAG_HASH_SIP |
3571 MLXSW_REG_SLCR_LAG_HASH_DIP |
3572 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3573 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3574 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003575 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3576 if (err)
3577 return err;
3578
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003579 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3580 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003581 return -EIO;
3582
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003583 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003584 sizeof(struct mlxsw_sp_upper),
3585 GFP_KERNEL);
3586 if (!mlxsw_sp->lags)
3587 return -ENOMEM;
3588
3589 return 0;
3590}
3591
3592static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3593{
3594 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003595}
3596
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003597static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3598{
3599 char htgt_pl[MLXSW_REG_HTGT_LEN];
3600
Nogah Frankel579c82e2016-11-25 10:33:42 +01003601 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3602 MLXSW_REG_HTGT_INVALID_POLICER,
3603 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3604 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003605 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3606}
3607
Petr Machatac30f5d02017-10-16 16:26:35 +02003608static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3609 unsigned long event, void *ptr);
3610
Jiri Pirkob2f10572016-04-08 19:11:23 +02003611static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003612 const struct mlxsw_bus_info *mlxsw_bus_info)
3613{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003614 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003615 int err;
3616
3617 mlxsw_sp->core = mlxsw_core;
3618 mlxsw_sp->bus_info = mlxsw_bus_info;
3619
Yotam Gigi6b742192017-05-23 21:56:29 +02003620 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3621 if (err) {
3622 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3623 return err;
3624 }
3625
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003626 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3627 if (err) {
3628 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3629 return err;
3630 }
3631
Ido Schimmela875a2e2017-10-22 23:11:44 +02003632 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3633 if (err) {
3634 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3635 return err;
3636 }
3637
Ido Schimmela1107482017-05-26 08:37:39 +02003638 err = mlxsw_sp_fids_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003639 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003640 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
Ido Schimmela875a2e2017-10-22 23:11:44 +02003641 goto err_fids_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003642 }
3643
Ido Schimmela1107482017-05-26 08:37:39 +02003644 err = mlxsw_sp_traps_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003645 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003646 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3647 goto err_traps_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003648 }
3649
3650 err = mlxsw_sp_buffers_init(mlxsw_sp);
3651 if (err) {
3652 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3653 goto err_buffers_init;
3654 }
3655
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003656 err = mlxsw_sp_lag_init(mlxsw_sp);
3657 if (err) {
3658 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3659 goto err_lag_init;
3660 }
3661
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003662 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3663 if (err) {
3664 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3665 goto err_switchdev_init;
3666 }
3667
Yotam Gigie2b2d352017-09-19 10:00:08 +02003668 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3669 if (err) {
3670 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3671 goto err_counter_pool_init;
3672 }
3673
Yotam Gigid3b939b2017-09-19 10:00:09 +02003674 err = mlxsw_sp_afa_init(mlxsw_sp);
3675 if (err) {
3676 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3677 goto err_afa_init;
3678 }
3679
Petr Machata803335a2018-02-27 14:53:46 +01003680 err = mlxsw_sp_span_init(mlxsw_sp);
3681 if (err) {
3682 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3683 goto err_span_init;
3684 }
3685
3686 /* Initialize router after SPAN is initialized, so that the FIB and
3687 * neighbor event handlers can issue SPAN respin.
3688 */
Ido Schimmel464dce12016-07-02 11:00:15 +02003689 err = mlxsw_sp_router_init(mlxsw_sp);
3690 if (err) {
3691 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3692 goto err_router_init;
3693 }
3694
Petr Machata803335a2018-02-27 14:53:46 +01003695 /* Initialize netdevice notifier after router and SPAN is initialized,
3696 * so that the event handler can use router structures and call SPAN
3697 * respin.
Petr Machatac30f5d02017-10-16 16:26:35 +02003698 */
3699 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3700 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3701 if (err) {
3702 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3703 goto err_netdev_notifier;
3704 }
3705
Jiri Pirko22a67762017-02-03 10:29:07 +01003706 err = mlxsw_sp_acl_init(mlxsw_sp);
3707 if (err) {
3708 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3709 goto err_acl_init;
3710 }
3711
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003712 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3713 if (err) {
3714 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3715 goto err_dpipe_init;
3716 }
3717
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003718 err = mlxsw_sp_ports_create(mlxsw_sp);
3719 if (err) {
3720 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3721 goto err_ports_create;
3722 }
3723
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003724 return 0;
3725
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003726err_ports_create:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003727 mlxsw_sp_dpipe_fini(mlxsw_sp);
3728err_dpipe_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01003729 mlxsw_sp_acl_fini(mlxsw_sp);
3730err_acl_init:
Petr Machatac30f5d02017-10-16 16:26:35 +02003731 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3732err_netdev_notifier:
Ido Schimmel464dce12016-07-02 11:00:15 +02003733 mlxsw_sp_router_fini(mlxsw_sp);
3734err_router_init:
Petr Machata803335a2018-02-27 14:53:46 +01003735 mlxsw_sp_span_fini(mlxsw_sp);
3736err_span_init:
Yotam Gigid3b939b2017-09-19 10:00:09 +02003737 mlxsw_sp_afa_fini(mlxsw_sp);
3738err_afa_init:
Yotam Gigie2b2d352017-09-19 10:00:08 +02003739 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3740err_counter_pool_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003741 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003742err_switchdev_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003743 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003744err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02003745 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003746err_buffers_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003747 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003748err_traps_init:
3749 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003750err_fids_init:
3751 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003752 return err;
3753}
3754
Jiri Pirkob2f10572016-04-08 19:11:23 +02003755static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003756{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003757 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003758
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003759 mlxsw_sp_ports_remove(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003760 mlxsw_sp_dpipe_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01003761 mlxsw_sp_acl_fini(mlxsw_sp);
Petr Machatac30f5d02017-10-16 16:26:35 +02003762 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
Ido Schimmel464dce12016-07-02 11:00:15 +02003763 mlxsw_sp_router_fini(mlxsw_sp);
Petr Machata803335a2018-02-27 14:53:46 +01003764 mlxsw_sp_span_fini(mlxsw_sp);
Yotam Gigid3b939b2017-09-19 10:00:09 +02003765 mlxsw_sp_afa_fini(mlxsw_sp);
Yotam Gigie2b2d352017-09-19 10:00:08 +02003766 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003767 mlxsw_sp_switchdev_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003768 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02003769 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003770 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003771 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003772 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003773}
3774
Bhumika Goyal159fe882017-08-11 19:10:42 +05303775static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003776 .used_max_vepa_channels = 1,
3777 .max_vepa_channels = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003778 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01003779 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003780 .used_max_pgt = 1,
3781 .max_pgt = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003782 .used_flood_tables = 1,
3783 .used_flood_mode = 1,
3784 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003785 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003786 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003787 .max_fid_flood_tables = 3,
Ido Schimmela1107482017-05-26 08:37:39 +02003788 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003789 .used_max_ib_mc = 1,
3790 .max_ib_mc = 0,
3791 .used_max_pkey = 1,
3792 .max_pkey = 0,
Nogah Frankel403547d2016-09-20 11:16:52 +02003793 .used_kvd_split_data = 1,
3794 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
Ido Schimmelf11fbaf2017-10-22 23:11:49 +02003795 .kvd_hash_single_parts = 59,
3796 .kvd_hash_double_parts = 41,
Jiri Pirkoc6022422016-07-05 11:27:46 +02003797 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003798 .swid_config = {
3799 {
3800 .used_type = 1,
3801 .type = MLXSW_PORT_SWID_TYPE_ETH,
3802 }
3803 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02003804 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003805};
3806
Arkadi Sharshevskyafadc262018-01-15 08:59:09 +01003807static u64 mlxsw_sp_resource_kvd_linear_occ_get(struct devlink *devlink)
3808{
3809 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
3810 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3811
3812 return mlxsw_sp_kvdl_occ_get(mlxsw_sp);
3813}
3814
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003815static struct devlink_resource_ops mlxsw_sp_resource_kvd_linear_ops = {
Arkadi Sharshevskyafadc262018-01-15 08:59:09 +01003816 .occ_get = mlxsw_sp_resource_kvd_linear_occ_get,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003817};
3818
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003819static struct devlink_resource_size_params mlxsw_sp_kvd_size_params;
3820static struct devlink_resource_size_params mlxsw_sp_linear_size_params;
3821static struct devlink_resource_size_params mlxsw_sp_hash_single_size_params;
3822static struct devlink_resource_size_params mlxsw_sp_hash_double_size_params;
3823
3824static void
3825mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core)
3826{
3827 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3828 KVD_SINGLE_MIN_SIZE);
3829 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3830 KVD_DOUBLE_MIN_SIZE);
3831 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3832 u32 linear_size_min = 0;
3833
3834 /* KVD top resource */
3835 mlxsw_sp_kvd_size_params.size_min = kvd_size;
3836 mlxsw_sp_kvd_size_params.size_max = kvd_size;
3837 mlxsw_sp_kvd_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
3838 mlxsw_sp_kvd_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
3839
3840 /* Linear part init */
3841 mlxsw_sp_linear_size_params.size_min = linear_size_min;
3842 mlxsw_sp_linear_size_params.size_max = kvd_size - single_size_min -
3843 double_size_min;
3844 mlxsw_sp_linear_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
3845 mlxsw_sp_linear_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
3846
3847 /* Hash double part init */
3848 mlxsw_sp_hash_double_size_params.size_min = double_size_min;
3849 mlxsw_sp_hash_double_size_params.size_max = kvd_size - single_size_min -
3850 linear_size_min;
3851 mlxsw_sp_hash_double_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
3852 mlxsw_sp_hash_double_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
3853
3854 /* Hash single part init */
3855 mlxsw_sp_hash_single_size_params.size_min = single_size_min;
3856 mlxsw_sp_hash_single_size_params.size_max = kvd_size - double_size_min -
3857 linear_size_min;
3858 mlxsw_sp_hash_single_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY;
3859 mlxsw_sp_hash_single_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY;
3860}
3861
3862static int mlxsw_sp_resources_register(struct mlxsw_core *mlxsw_core)
3863{
3864 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3865 u32 kvd_size, single_size, double_size, linear_size;
3866 const struct mlxsw_config_profile *profile;
3867 int err;
3868
3869 profile = &mlxsw_sp_config_profile;
3870 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
3871 return -EIO;
3872
3873 mlxsw_sp_resource_size_params_prepare(mlxsw_core);
3874 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3875 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
3876 true, kvd_size,
3877 MLXSW_SP_RESOURCE_KVD,
3878 DEVLINK_RESOURCE_ID_PARENT_TOP,
3879 &mlxsw_sp_kvd_size_params,
Arkadi Sharshevsky4f4bbf72018-02-20 08:44:21 +01003880 NULL);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003881 if (err)
3882 return err;
3883
3884 linear_size = profile->kvd_linear_size;
3885 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
3886 false, linear_size,
3887 MLXSW_SP_RESOURCE_KVD_LINEAR,
3888 MLXSW_SP_RESOURCE_KVD,
3889 &mlxsw_sp_linear_size_params,
3890 &mlxsw_sp_resource_kvd_linear_ops);
3891 if (err)
3892 return err;
3893
Arkadi Sharshevsky51d3c082018-02-20 08:44:22 +01003894 err = mlxsw_sp_kvdl_resources_register(devlink);
3895 if (err)
3896 return err;
3897
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003898 double_size = kvd_size - linear_size;
3899 double_size *= profile->kvd_hash_double_parts;
3900 double_size /= profile->kvd_hash_double_parts +
3901 profile->kvd_hash_single_parts;
3902 double_size = rounddown(double_size, profile->kvd_hash_granularity);
3903 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
3904 false, double_size,
3905 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3906 MLXSW_SP_RESOURCE_KVD,
3907 &mlxsw_sp_hash_double_size_params,
Arkadi Sharshevsky4f4bbf72018-02-20 08:44:21 +01003908 NULL);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003909 if (err)
3910 return err;
3911
3912 single_size = kvd_size - double_size - linear_size;
3913 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
3914 false, single_size,
3915 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3916 MLXSW_SP_RESOURCE_KVD,
3917 &mlxsw_sp_hash_single_size_params,
Arkadi Sharshevsky4f4bbf72018-02-20 08:44:21 +01003918 NULL);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003919 if (err)
3920 return err;
3921
3922 return 0;
3923}
3924
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01003925static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
3926 const struct mlxsw_config_profile *profile,
3927 u64 *p_single_size, u64 *p_double_size,
3928 u64 *p_linear_size)
3929{
3930 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3931 u32 double_size;
3932 int err;
3933
3934 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3935 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
3936 !profile->used_kvd_split_data)
3937 return -EIO;
3938
3939 /* The hash part is what left of the kvd without the
3940 * linear part. It is split to the single size and
3941 * double size by the parts ratio from the profile.
3942 * Both sizes must be a multiplications of the
3943 * granularity from the profile. In case the user
3944 * provided the sizes they are obtained via devlink.
3945 */
3946 err = devlink_resource_size_get(devlink,
3947 MLXSW_SP_RESOURCE_KVD_LINEAR,
3948 p_linear_size);
3949 if (err)
3950 *p_linear_size = profile->kvd_linear_size;
3951
3952 err = devlink_resource_size_get(devlink,
3953 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3954 p_double_size);
3955 if (err) {
3956 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3957 *p_linear_size;
3958 double_size *= profile->kvd_hash_double_parts;
3959 double_size /= profile->kvd_hash_double_parts +
3960 profile->kvd_hash_single_parts;
3961 *p_double_size = rounddown(double_size,
3962 profile->kvd_hash_granularity);
3963 }
3964
3965 err = devlink_resource_size_get(devlink,
3966 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3967 p_single_size);
3968 if (err)
3969 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3970 *p_double_size - *p_linear_size;
3971
3972 /* Check results are legal. */
3973 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3974 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
3975 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
3976 return -EIO;
3977
3978 return 0;
3979}
3980
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003981static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02003982 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003983 .priv_size = sizeof(struct mlxsw_sp),
3984 .init = mlxsw_sp_init,
3985 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003986 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003987 .port_split = mlxsw_sp_port_split,
3988 .port_unsplit = mlxsw_sp_port_unsplit,
3989 .sb_pool_get = mlxsw_sp_sb_pool_get,
3990 .sb_pool_set = mlxsw_sp_sb_pool_set,
3991 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3992 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3993 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3994 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3995 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3996 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3997 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3998 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3999 .txhdr_construct = mlxsw_sp_txhdr_construct,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004000 .resources_register = mlxsw_sp_resources_register,
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01004001 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02004002 .txhdr_len = MLXSW_TXHDR_LEN,
4003 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004004};
4005
Jiri Pirko22a67762017-02-03 10:29:07 +01004006bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004007{
4008 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4009}
4010
Jiri Pirko1182e532017-03-06 21:25:20 +01004011static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07004012{
Jiri Pirko1182e532017-03-06 21:25:20 +01004013 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07004014 int ret = 0;
4015
4016 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01004017 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07004018 ret = 1;
4019 }
4020
4021 return ret;
4022}
4023
Ido Schimmelc57529e2017-05-26 08:37:31 +02004024struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004025{
Jiri Pirko1182e532017-03-06 21:25:20 +01004026 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004027
4028 if (mlxsw_sp_port_dev_check(dev))
4029 return netdev_priv(dev);
4030
Jiri Pirko1182e532017-03-06 21:25:20 +01004031 mlxsw_sp_port = NULL;
4032 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004033
Jiri Pirko1182e532017-03-06 21:25:20 +01004034 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004035}
4036
Ido Schimmel4724ba562017-03-10 08:53:39 +01004037struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004038{
4039 struct mlxsw_sp_port *mlxsw_sp_port;
4040
4041 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4042 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4043}
4044
Arkadi Sharshevskyaf0613782017-06-08 08:44:20 +02004045struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004046{
Jiri Pirko1182e532017-03-06 21:25:20 +01004047 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004048
4049 if (mlxsw_sp_port_dev_check(dev))
4050 return netdev_priv(dev);
4051
Jiri Pirko1182e532017-03-06 21:25:20 +01004052 mlxsw_sp_port = NULL;
4053 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4054 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004055
Jiri Pirko1182e532017-03-06 21:25:20 +01004056 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004057}
4058
4059struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4060{
4061 struct mlxsw_sp_port *mlxsw_sp_port;
4062
4063 rcu_read_lock();
4064 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4065 if (mlxsw_sp_port)
4066 dev_hold(mlxsw_sp_port->dev);
4067 rcu_read_unlock();
4068 return mlxsw_sp_port;
4069}
4070
4071void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4072{
4073 dev_put(mlxsw_sp_port->dev);
4074}
4075
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004076static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004077{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004078 char sldr_pl[MLXSW_REG_SLDR_LEN];
4079
4080 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4081 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4082}
4083
4084static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4085{
4086 char sldr_pl[MLXSW_REG_SLDR_LEN];
4087
4088 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4089 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4090}
4091
4092static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4093 u16 lag_id, u8 port_index)
4094{
4095 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4096 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4097
4098 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4099 lag_id, port_index);
4100 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4101}
4102
4103static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4104 u16 lag_id)
4105{
4106 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4107 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4108
4109 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4110 lag_id);
4111 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4112}
4113
4114static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4115 u16 lag_id)
4116{
4117 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4118 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4119
4120 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4121 lag_id);
4122 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4123}
4124
4125static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4126 u16 lag_id)
4127{
4128 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4129 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4130
4131 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4132 lag_id);
4133 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4134}
4135
4136static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4137 struct net_device *lag_dev,
4138 u16 *p_lag_id)
4139{
4140 struct mlxsw_sp_upper *lag;
4141 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004142 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004143 int i;
4144
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004145 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4146 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004147 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4148 if (lag->ref_count) {
4149 if (lag->dev == lag_dev) {
4150 *p_lag_id = i;
4151 return 0;
4152 }
4153 } else if (free_lag_id < 0) {
4154 free_lag_id = i;
4155 }
4156 }
4157 if (free_lag_id < 0)
4158 return -EBUSY;
4159 *p_lag_id = free_lag_id;
4160 return 0;
4161}
4162
4163static bool
4164mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4165 struct net_device *lag_dev,
David Aherne58376e2017-10-04 17:48:51 -07004166 struct netdev_lag_upper_info *lag_upper_info,
4167 struct netlink_ext_ack *extack)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004168{
4169 u16 lag_id;
4170
David Aherne58376e2017-10-04 17:48:51 -07004171 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004172 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004173 return false;
David Aherne58376e2017-10-04 17:48:51 -07004174 }
4175 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004176 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004177 return false;
David Aherne58376e2017-10-04 17:48:51 -07004178 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004179 return true;
4180}
4181
4182static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4183 u16 lag_id, u8 *p_port_index)
4184{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004185 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004186 int i;
4187
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004188 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4189 MAX_LAG_MEMBERS);
4190 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004191 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4192 *p_port_index = i;
4193 return 0;
4194 }
4195 }
4196 return -EBUSY;
4197}
4198
4199static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4200 struct net_device *lag_dev)
4201{
4202 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004203 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004204 struct mlxsw_sp_upper *lag;
4205 u16 lag_id;
4206 u8 port_index;
4207 int err;
4208
4209 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4210 if (err)
4211 return err;
4212 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4213 if (!lag->ref_count) {
4214 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4215 if (err)
4216 return err;
4217 lag->dev = lag_dev;
4218 }
4219
4220 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4221 if (err)
4222 return err;
4223 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4224 if (err)
4225 goto err_col_port_add;
4226 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4227 if (err)
4228 goto err_col_port_enable;
4229
4230 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4231 mlxsw_sp_port->local_port);
4232 mlxsw_sp_port->lag_id = lag_id;
4233 mlxsw_sp_port->lagged = 1;
4234 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004235
Ido Schimmelc57529e2017-05-26 08:37:31 +02004236 /* Port is no longer usable as a router interface */
4237 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4238 if (mlxsw_sp_port_vlan->fid)
Ido Schimmela1107482017-05-26 08:37:39 +02004239 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004240
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004241 return 0;
4242
Ido Schimmel51554db2016-05-06 22:18:39 +02004243err_col_port_enable:
4244 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004245err_col_port_add:
4246 if (!lag->ref_count)
4247 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004248 return err;
4249}
4250
Ido Schimmel82e6db02016-06-20 23:04:04 +02004251static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4252 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004253{
4254 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004255 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004256 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004257
4258 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004259 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004260 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4261 WARN_ON(lag->ref_count == 0);
4262
Ido Schimmel82e6db02016-06-20 23:04:04 +02004263 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4264 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004265
Ido Schimmelc57529e2017-05-26 08:37:31 +02004266 /* Any VLANs configured on the port are no longer valid */
4267 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004268
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004269 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004270 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004271
4272 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4273 mlxsw_sp_port->local_port);
4274 mlxsw_sp_port->lagged = 0;
4275 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004276
Ido Schimmelc57529e2017-05-26 08:37:31 +02004277 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4278 /* Make sure untagged frames are allowed to ingress */
4279 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004280}
4281
Jiri Pirko74581202015-12-03 12:12:30 +01004282static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4283 u16 lag_id)
4284{
4285 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4286 char sldr_pl[MLXSW_REG_SLDR_LEN];
4287
4288 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4289 mlxsw_sp_port->local_port);
4290 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4291}
4292
4293static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4294 u16 lag_id)
4295{
4296 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4297 char sldr_pl[MLXSW_REG_SLDR_LEN];
4298
4299 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4300 mlxsw_sp_port->local_port);
4301 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4302}
4303
4304static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4305 bool lag_tx_enabled)
4306{
4307 if (lag_tx_enabled)
4308 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4309 mlxsw_sp_port->lag_id);
4310 else
4311 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4312 mlxsw_sp_port->lag_id);
4313}
4314
4315static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4316 struct netdev_lag_lower_state_info *info)
4317{
4318 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4319}
4320
Jiri Pirko2b94e582017-04-18 16:55:37 +02004321static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4322 bool enable)
4323{
4324 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4325 enum mlxsw_reg_spms_state spms_state;
4326 char *spms_pl;
4327 u16 vid;
4328 int err;
4329
4330 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4331 MLXSW_REG_SPMS_STATE_DISCARDING;
4332
4333 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4334 if (!spms_pl)
4335 return -ENOMEM;
4336 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4337
4338 for (vid = 0; vid < VLAN_N_VID; vid++)
4339 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4340
4341 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4342 kfree(spms_pl);
4343 return err;
4344}
4345
4346static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4347{
Yuval Mintzfccff082017-12-15 08:44:21 +01004348 u16 vid = 1;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004349 int err;
4350
Ido Schimmel4aafc362017-05-26 08:37:25 +02004351 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004352 if (err)
4353 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02004354 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4355 if (err)
4356 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004357 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4358 true, false);
4359 if (err)
4360 goto err_port_vlan_set;
Yuval Mintzfccff082017-12-15 08:44:21 +01004361
4362 for (; vid <= VLAN_N_VID - 1; vid++) {
4363 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4364 vid, false);
4365 if (err)
4366 goto err_vid_learning_set;
4367 }
4368
Jiri Pirko2b94e582017-04-18 16:55:37 +02004369 return 0;
4370
Yuval Mintzfccff082017-12-15 08:44:21 +01004371err_vid_learning_set:
4372 for (vid--; vid >= 1; vid--)
4373 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004374err_port_vlan_set:
4375 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004376err_port_stp_set:
4377 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004378 return err;
4379}
4380
4381static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4382{
Yuval Mintzfccff082017-12-15 08:44:21 +01004383 u16 vid;
4384
4385 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4386 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4387 vid, true);
4388
Jiri Pirko2b94e582017-04-18 16:55:37 +02004389 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4390 false, false);
4391 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004392 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004393}
4394
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004395static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4396 struct net_device *dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004397 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004398{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004399 struct netdev_notifier_changeupper_info *info;
4400 struct mlxsw_sp_port *mlxsw_sp_port;
David Aherne58376e2017-10-04 17:48:51 -07004401 struct netlink_ext_ack *extack;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004402 struct net_device *upper_dev;
4403 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004404 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004405
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004406 mlxsw_sp_port = netdev_priv(dev);
4407 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4408 info = ptr;
David Aherne58376e2017-10-04 17:48:51 -07004409 extack = netdev_notifier_info_to_extack(&info->info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004410
4411 switch (event) {
4412 case NETDEV_PRECHANGEUPPER:
4413 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004414 if (!is_vlan_dev(upper_dev) &&
4415 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004416 !netif_is_bridge_master(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004417 !netif_is_ovs_master(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004418 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004419 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004420 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004421 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004422 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004423 if (netdev_has_any_upper_dev(upper_dev) &&
4424 (!netif_is_bridge_master(upper_dev) ||
4425 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4426 upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004427 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004428 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004429 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004430 if (netif_is_lag_master(upper_dev) &&
4431 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
David Aherne58376e2017-10-04 17:48:51 -07004432 info->upper_info, extack))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004433 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004434 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004435 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004436 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004437 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004438 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004439 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004440 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004441 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004442 }
4443 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004444 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004445 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004446 }
4447 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004448 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004449 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004450 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004451 break;
4452 case NETDEV_CHANGEUPPER:
4453 upper_dev = info->upper_dev;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004454 if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004455 if (info->linking)
4456 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004457 lower_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004458 upper_dev,
4459 extack);
Ido Schimmel7117a572016-06-20 23:04:06 +02004460 else
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004461 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4462 lower_dev,
4463 upper_dev);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004464 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004465 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004466 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4467 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004468 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004469 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4470 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004471 } else if (netif_is_ovs_master(upper_dev)) {
4472 if (info->linking)
4473 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4474 else
4475 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004476 }
4477 break;
4478 }
4479
Ido Schimmel80bedf12016-06-20 23:03:59 +02004480 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004481}
4482
Jiri Pirko74581202015-12-03 12:12:30 +01004483static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4484 unsigned long event, void *ptr)
4485{
4486 struct netdev_notifier_changelowerstate_info *info;
4487 struct mlxsw_sp_port *mlxsw_sp_port;
4488 int err;
4489
4490 mlxsw_sp_port = netdev_priv(dev);
4491 info = ptr;
4492
4493 switch (event) {
4494 case NETDEV_CHANGELOWERSTATE:
4495 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4496 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4497 info->lower_state_info);
4498 if (err)
4499 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4500 }
4501 break;
4502 }
4503
Ido Schimmel80bedf12016-06-20 23:03:59 +02004504 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004505}
4506
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004507static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4508 struct net_device *port_dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004509 unsigned long event, void *ptr)
4510{
4511 switch (event) {
4512 case NETDEV_PRECHANGEUPPER:
4513 case NETDEV_CHANGEUPPER:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004514 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4515 event, ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004516 case NETDEV_CHANGELOWERSTATE:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004517 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4518 ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004519 }
4520
Ido Schimmel80bedf12016-06-20 23:03:59 +02004521 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004522}
4523
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004524static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4525 unsigned long event, void *ptr)
4526{
4527 struct net_device *dev;
4528 struct list_head *iter;
4529 int ret;
4530
4531 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4532 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004533 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4534 ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004535 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004536 return ret;
4537 }
4538 }
4539
Ido Schimmel80bedf12016-06-20 23:03:59 +02004540 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004541}
4542
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004543static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4544 struct net_device *dev,
4545 unsigned long event, void *ptr,
4546 u16 vid)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004547{
4548 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel90045fc2017-12-25 09:05:33 +01004549 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004550 struct netdev_notifier_changeupper_info *info = ptr;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004551 struct netlink_ext_ack *extack;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004552 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004553 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004554
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004555 extack = netdev_notifier_info_to_extack(&info->info);
4556
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004557 switch (event) {
4558 case NETDEV_PRECHANGEUPPER:
4559 upper_dev = info->upper_dev;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004560 if (!netif_is_bridge_master(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004561 NL_SET_ERR_MSG_MOD(extack, "VLAN devices only support bridge and VRF uppers");
Ido Schimmel80bedf12016-06-20 23:03:59 +02004562 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004563 }
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004564 if (!info->linking)
4565 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004566 if (netdev_has_any_upper_dev(upper_dev) &&
4567 (!netif_is_bridge_master(upper_dev) ||
4568 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4569 upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004570 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004571 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004572 }
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004573 break;
4574 case NETDEV_CHANGEUPPER:
4575 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004576 if (netif_is_bridge_master(upper_dev)) {
4577 if (info->linking)
Ido Schimmelc57529e2017-05-26 08:37:31 +02004578 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4579 vlan_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004580 upper_dev,
4581 extack);
Ido Schimmel1f880612017-03-10 08:53:35 +01004582 else
Ido Schimmelc57529e2017-05-26 08:37:31 +02004583 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4584 vlan_dev,
4585 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004586 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004587 err = -EINVAL;
4588 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004589 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004590 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004591 }
4592
Ido Schimmel80bedf12016-06-20 23:03:59 +02004593 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004594}
4595
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004596static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4597 struct net_device *lag_dev,
4598 unsigned long event,
4599 void *ptr, u16 vid)
Ido Schimmel272c4472015-12-15 16:03:47 +01004600{
4601 struct net_device *dev;
4602 struct list_head *iter;
4603 int ret;
4604
4605 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4606 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004607 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4608 event, ptr,
4609 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004610 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004611 return ret;
4612 }
4613 }
4614
Ido Schimmel80bedf12016-06-20 23:03:59 +02004615 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004616}
4617
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004618static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4619 unsigned long event, void *ptr)
4620{
4621 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4622 u16 vid = vlan_dev_vlan_id(vlan_dev);
4623
Ido Schimmel272c4472015-12-15 16:03:47 +01004624 if (mlxsw_sp_port_dev_check(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004625 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4626 event, ptr, vid);
Ido Schimmel272c4472015-12-15 16:03:47 +01004627 else if (netif_is_lag_master(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004628 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4629 real_dev, event,
4630 ptr, vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004631
Ido Schimmel80bedf12016-06-20 23:03:59 +02004632 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004633}
4634
Ido Schimmelb1e45522017-04-30 19:47:14 +03004635static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4636{
4637 struct netdev_notifier_changeupper_info *info = ptr;
4638
4639 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4640 return false;
4641 return netif_is_l3_master(info->upper_dev);
4642}
4643
Petr Machata00635872017-10-16 16:26:37 +02004644static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004645 unsigned long event, void *ptr)
4646{
4647 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Petr Machata079c9f32018-02-27 14:53:44 +01004648 struct mlxsw_sp_span_entry *span_entry;
Petr Machata00635872017-10-16 16:26:37 +02004649 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004650 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004651
Petr Machata00635872017-10-16 16:26:37 +02004652 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
Petr Machata079c9f32018-02-27 14:53:44 +01004653 if (event == NETDEV_UNREGISTER) {
4654 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
4655 if (span_entry)
4656 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
4657 }
Petr Machata803335a2018-02-27 14:53:46 +01004658 mlxsw_sp_span_respin(mlxsw_sp);
Petr Machata079c9f32018-02-27 14:53:44 +01004659
Petr Machata796ec772017-11-03 10:03:29 +01004660 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
4661 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
4662 event, ptr);
Petr Machata61481f22017-11-03 10:03:41 +01004663 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
4664 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
4665 event, ptr);
Petr Machata00635872017-10-16 16:26:37 +02004666 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004667 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03004668 else if (mlxsw_sp_is_vrf_event(event, ptr))
4669 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004670 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004671 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004672 else if (netif_is_lag_master(dev))
4673 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4674 else if (is_vlan_dev(dev))
4675 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004676
Ido Schimmel80bedf12016-06-20 23:03:59 +02004677 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004678}
4679
David Ahern89d5dd22017-10-18 09:56:55 -07004680static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
4681 .notifier_call = mlxsw_sp_inetaddr_valid_event,
4682};
4683
Ido Schimmel99724c12016-07-04 08:23:14 +02004684static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4685 .notifier_call = mlxsw_sp_inetaddr_event,
David Ahern89d5dd22017-10-18 09:56:55 -07004686};
4687
4688static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
4689 .notifier_call = mlxsw_sp_inet6addr_valid_event,
Ido Schimmel99724c12016-07-04 08:23:14 +02004690};
4691
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004692static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
4693 .notifier_call = mlxsw_sp_inet6addr_event,
4694};
4695
Jiri Pirko1d20d232016-10-27 15:12:59 +02004696static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4697 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4698 {0, },
4699};
4700
4701static struct pci_driver mlxsw_sp_pci_driver = {
4702 .name = mlxsw_sp_driver_name,
4703 .id_table = mlxsw_sp_pci_id_table,
4704};
4705
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004706static int __init mlxsw_sp_module_init(void)
4707{
4708 int err;
4709
David Ahern89d5dd22017-10-18 09:56:55 -07004710 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004711 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004712 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004713 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004714
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004715 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4716 if (err)
4717 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02004718
4719 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4720 if (err)
4721 goto err_pci_driver_register;
4722
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004723 return 0;
4724
Jiri Pirko1d20d232016-10-27 15:12:59 +02004725err_pci_driver_register:
4726 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004727err_core_driver_register:
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004728 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004729 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02004730 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004731 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004732 return err;
4733}
4734
4735static void __exit mlxsw_sp_module_exit(void)
4736{
Jiri Pirko1d20d232016-10-27 15:12:59 +02004737 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004738 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004739 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004740 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004741 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004742 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004743}
4744
4745module_init(mlxsw_sp_module_init);
4746module_exit(mlxsw_sp_module_exit);
4747
4748MODULE_LICENSE("Dual BSD/GPL");
4749MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4750MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02004751MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Yotam Gigi6b742192017-05-23 21:56:29 +02004752MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);