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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Jesse Barnes5669fca2009-02-17 15:13:31 -080030#include <linux/device.h>
Jesse Barnese5747e32014-06-12 08:35:47 -070031#include <linux/acpi.h>
David Howells760285e2012-10-02 18:01:07 +010032#include <drm/drmP.h>
33#include <drm/i915_drm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#include "i915_drv.h"
Chris Wilson990bbda2012-07-02 11:51:02 -030035#include "i915_trace.h"
Kenneth Graunkef49f0582010-09-11 01:19:14 -070036#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
Lukas Wunner704ab612016-01-11 20:09:20 +010038#include <linux/apple-gmux.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080039#include <linux/console.h>
Paul Gortmakere0cd3602011-08-30 11:04:30 -040040#include <linux/module.h>
Imre Deakd6102972014-05-07 19:57:49 +030041#include <linux/pm_runtime.h>
Lukas Wunner704ab612016-01-11 20:09:20 +010042#include <linux/vgaarb.h>
43#include <linux/vga_switcheroo.h>
David Howells760285e2012-10-02 18:01:07 +010044#include <drm/drm_crtc_helper.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080045
Kristian Høgsberg112b7152009-01-04 16:55:33 -050046static struct drm_driver driver;
47
Antti Koskipaaa57c7742014-02-04 14:22:24 +020048#define GEN_DEFAULT_PIPEOFFSETS \
49 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
50 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
51 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
52 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
Antti Koskipaaa57c7742014-02-04 14:22:24 +020053 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
54
Rafael Barbalho84fd4f42014-04-28 14:00:42 +030055#define GEN_CHV_PIPEOFFSETS \
56 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
57 CHV_PIPE_C_OFFSET }, \
58 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
59 CHV_TRANSCODER_C_OFFSET, }, \
Rafael Barbalho84fd4f42014-04-28 14:00:42 +030060 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
61 CHV_PALETTE_C_OFFSET }
Antti Koskipaaa57c7742014-02-04 14:22:24 +020062
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030063#define CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
65
66#define IVB_CURSOR_OFFSETS \
67 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
68
Lionel Landwerlin82cf4352016-03-16 10:57:16 +000069#define BDW_COLORS \
70 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
Lionel Landwerlin29dc3732016-03-16 10:57:17 +000071#define CHV_COLORS \
72 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
Lionel Landwerlin82cf4352016-03-16 10:57:16 +000073
Tobias Klauser9a7e8492010-05-20 10:33:46 +020074static const struct intel_device_info intel_i830_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070075 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
Chris Wilson315781482010-08-12 09:42:51 +010076 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070077 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020078 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030079 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050080};
81
Tobias Klauser9a7e8492010-05-20 10:33:46 +020082static const struct intel_device_info intel_845g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070083 .gen = 2, .num_pipes = 1,
Chris Wilson315781482010-08-12 09:42:51 +010084 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070085 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020086 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030087 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050088};
89
Tobias Klauser9a7e8492010-05-20 10:33:46 +020090static const struct intel_device_info intel_i85x_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070091 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
Adam Jackson5ce8ba72010-04-15 14:03:30 -040092 .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +010093 .has_overlay = 1, .overlay_needs_physical = 1,
Ville Syrjäläfd70d522013-11-28 17:30:02 +020094 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070095 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020096 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030097 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050098};
99
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200100static const struct intel_device_info intel_i865g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700101 .gen = 2, .num_pipes = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100102 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700103 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200104 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300105 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500106};
107
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200108static const struct intel_device_info intel_i915g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700109 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
Chris Wilson315781482010-08-12 09:42:51 +0100110 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700111 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200112 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300113 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500114};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200115static const struct intel_device_info intel_i915gm_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700116 .gen = 3, .is_mobile = 1, .num_pipes = 2,
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -0500117 .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100118 .has_overlay = 1, .overlay_needs_physical = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100119 .supports_tv = 1,
Ville Syrjäläfd70d522013-11-28 17:30:02 +0200120 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700121 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200122 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300123 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500124};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200125static const struct intel_device_info intel_i945g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700126 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
Chris Wilson315781482010-08-12 09:42:51 +0100127 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700128 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200129 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300130 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500131};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200132static const struct intel_device_info intel_i945gm_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700133 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -0500134 .has_hotplug = 1, .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100135 .has_overlay = 1, .overlay_needs_physical = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100136 .supports_tv = 1,
Ville Syrjäläfd70d522013-11-28 17:30:02 +0200137 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700138 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200139 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300140 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500141};
142
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200143static const struct intel_device_info intel_i965g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700144 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100145 .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100146 .has_overlay = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700147 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200148 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300149 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500150};
151
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200152static const struct intel_device_info intel_i965gm_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700153 .gen = 4, .is_crestline = 1, .num_pipes = 2,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000154 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100155 .has_overlay = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100156 .supports_tv = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700157 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200158 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300159 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500160};
161
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200162static const struct intel_device_info intel_g33_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700163 .gen = 3, .is_g33 = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100164 .need_gfx_hws = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100165 .has_overlay = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700166 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200167 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300168 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500169};
170
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200171static const struct intel_device_info intel_g45_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700172 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100173 .has_pipe_cxsr = 1, .has_hotplug = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700174 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200175 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300176 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500177};
178
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200179static const struct intel_device_info intel_gm45_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700180 .gen = 4, .is_g4x = 1, .num_pipes = 2,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000181 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100182 .has_pipe_cxsr = 1, .has_hotplug = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100183 .supports_tv = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700184 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200185 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300186 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500187};
188
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200189static const struct intel_device_info intel_pineview_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700190 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100191 .need_gfx_hws = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100192 .has_overlay = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200193 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300194 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500195};
196
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200197static const struct intel_device_info intel_ironlake_d_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700198 .gen = 5, .num_pipes = 2,
Eugeni Dodonov5a117db2012-01-05 09:34:29 -0200199 .need_gfx_hws = 1, .has_hotplug = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700200 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200201 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300202 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500203};
204
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200205static const struct intel_device_info intel_ironlake_m_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700206 .gen = 5, .is_mobile = 1, .num_pipes = 2,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000207 .need_gfx_hws = 1, .has_hotplug = 1,
Jesse Barnesc1a9f042011-05-05 15:24:21 -0700208 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700209 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200210 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300211 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500212};
213
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200214static const struct intel_device_info intel_sandybridge_d_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700215 .gen = 6, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100216 .need_gfx_hws = 1, .has_hotplug = 1,
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200217 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700218 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200219 .has_llc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200220 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300221 CURSOR_OFFSETS,
Eric Anholtf6e450a2009-11-02 12:08:22 -0800222};
223
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200224static const struct intel_device_info intel_sandybridge_m_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700225 .gen = 6, .is_mobile = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100226 .need_gfx_hws = 1, .has_hotplug = 1,
Yuanhan Liu9c04f012010-12-15 15:42:32 +0800227 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700228 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200229 .has_llc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200230 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300231 CURSOR_OFFSETS,
Eric Anholta13e4092010-01-07 15:08:18 -0800232};
233
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700234#define GEN7_FEATURES \
235 .gen = 7, .num_pipes = 3, \
236 .need_gfx_hws = 1, .has_hotplug = 1, \
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200237 .has_fbc = 1, \
Ben Widawsky73ae4782013-10-15 10:02:57 -0700238 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
Wayne Boyer6a8beef2015-12-02 13:28:14 -0800239 .has_llc = 1, \
240 GEN_DEFAULT_PIPEOFFSETS, \
241 IVB_CURSOR_OFFSETS
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700242
Jesse Barnesc76b6152011-04-28 14:32:07 -0700243static const struct intel_device_info intel_ivybridge_d_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700244 GEN7_FEATURES,
245 .is_ivybridge = 1,
Jesse Barnesc76b6152011-04-28 14:32:07 -0700246};
247
248static const struct intel_device_info intel_ivybridge_m_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700249 GEN7_FEATURES,
250 .is_ivybridge = 1,
251 .is_mobile = 1,
Jesse Barnesc76b6152011-04-28 14:32:07 -0700252};
253
Ben Widawsky999bcde2013-04-05 13:12:45 -0700254static const struct intel_device_info intel_ivybridge_q_info = {
255 GEN7_FEATURES,
256 .is_ivybridge = 1,
257 .num_pipes = 0, /* legal, last one wins */
258};
259
Wayne Boyer6a8beef2015-12-02 13:28:14 -0800260#define VLV_FEATURES \
261 .gen = 7, .num_pipes = 2, \
262 .need_gfx_hws = 1, .has_hotplug = 1, \
263 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
264 .display_mmio_offset = VLV_DISPLAY_BASE, \
265 GEN_DEFAULT_PIPEOFFSETS, \
266 CURSOR_OFFSETS
267
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700268static const struct intel_device_info intel_valleyview_m_info = {
Wayne Boyer6a8beef2015-12-02 13:28:14 -0800269 VLV_FEATURES,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700270 .is_valleyview = 1,
Wayne Boyer6a8beef2015-12-02 13:28:14 -0800271 .is_mobile = 1,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700272};
273
274static const struct intel_device_info intel_valleyview_d_info = {
Wayne Boyer6a8beef2015-12-02 13:28:14 -0800275 VLV_FEATURES,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700276 .is_valleyview = 1,
277};
278
Wayne Boyer6a8beef2015-12-02 13:28:14 -0800279#define HSW_FEATURES \
280 GEN7_FEATURES, \
281 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
282 .has_ddi = 1, \
283 .has_fpga_dbg = 1
284
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -0300285static const struct intel_device_info intel_haswell_d_info = {
Wayne Boyer6a8beef2015-12-02 13:28:14 -0800286 HSW_FEATURES,
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700287 .is_haswell = 1,
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -0300288};
289
290static const struct intel_device_info intel_haswell_m_info = {
Wayne Boyer6a8beef2015-12-02 13:28:14 -0800291 HSW_FEATURES,
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700292 .is_haswell = 1,
293 .is_mobile = 1,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500294};
295
Lionel Landwerlin82cf4352016-03-16 10:57:16 +0000296#define BDW_FEATURES \
297 HSW_FEATURES, \
298 BDW_COLORS
299
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800300static const struct intel_device_info intel_broadwell_d_info = {
Lionel Landwerlin82cf4352016-03-16 10:57:16 +0000301 BDW_FEATURES,
Wayne Boyer6a8beef2015-12-02 13:28:14 -0800302 .gen = 8,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800303};
304
305static const struct intel_device_info intel_broadwell_m_info = {
Lionel Landwerlin82cf4352016-03-16 10:57:16 +0000306 BDW_FEATURES,
Wayne Boyer6a8beef2015-12-02 13:28:14 -0800307 .gen = 8, .is_mobile = 1,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800308};
309
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800310static const struct intel_device_info intel_broadwell_gt3d_info = {
Lionel Landwerlin82cf4352016-03-16 10:57:16 +0000311 BDW_FEATURES,
Wayne Boyer6a8beef2015-12-02 13:28:14 -0800312 .gen = 8,
Zhao Yakui845f74a2014-04-17 10:37:37 +0800313 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800314};
315
316static const struct intel_device_info intel_broadwell_gt3m_info = {
Lionel Landwerlin82cf4352016-03-16 10:57:16 +0000317 BDW_FEATURES,
Wayne Boyer6a8beef2015-12-02 13:28:14 -0800318 .gen = 8, .is_mobile = 1,
Zhao Yakui845f74a2014-04-17 10:37:37 +0800319 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800320};
321
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300322static const struct intel_device_info intel_cherryview_info = {
Ville Syrjälä07fddb12014-04-09 13:28:54 +0300323 .gen = 8, .num_pipes = 3,
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300324 .need_gfx_hws = 1, .has_hotplug = 1,
325 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
Wayne Boyer666a4532015-12-09 12:29:35 -0800326 .is_cherryview = 1,
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300327 .display_mmio_offset = VLV_DISPLAY_BASE,
Rafael Barbalho84fd4f42014-04-28 14:00:42 +0300328 GEN_CHV_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300329 CURSOR_OFFSETS,
Lionel Landwerlin29dc3732016-03-16 10:57:17 +0000330 CHV_COLORS,
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300331};
332
Damien Lespiau72bbf0a2013-02-13 15:27:37 +0000333static const struct intel_device_info intel_skylake_info = {
Lionel Landwerlin82cf4352016-03-16 10:57:16 +0000334 BDW_FEATURES,
Satheeshakrishna M7201c0b2014-04-02 11:24:50 +0530335 .is_skylake = 1,
Wayne Boyer6a8beef2015-12-02 13:28:14 -0800336 .gen = 9,
Damien Lespiau72bbf0a2013-02-13 15:27:37 +0000337};
338
Damien Lespiau719388e2015-02-04 13:22:27 +0000339static const struct intel_device_info intel_skylake_gt3_info = {
Lionel Landwerlin82cf4352016-03-16 10:57:16 +0000340 BDW_FEATURES,
Damien Lespiau719388e2015-02-04 13:22:27 +0000341 .is_skylake = 1,
Wayne Boyer6a8beef2015-12-02 13:28:14 -0800342 .gen = 9,
Damien Lespiau719388e2015-02-04 13:22:27 +0000343 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
Damien Lespiau719388e2015-02-04 13:22:27 +0000344};
345
Damien Lespiau1347f5b2015-03-17 11:39:27 +0200346static const struct intel_device_info intel_broxton_info = {
347 .is_preliminary = 1,
Rodrigo Vivi7526ac12015-10-27 10:14:54 -0700348 .is_broxton = 1,
Damien Lespiau1347f5b2015-03-17 11:39:27 +0200349 .gen = 9,
350 .need_gfx_hws = 1, .has_hotplug = 1,
351 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
352 .num_pipes = 3,
353 .has_ddi = 1,
Paulo Zanoni6c908bf2015-08-25 19:03:41 -0300354 .has_fpga_dbg = 1,
Daisy Sunce89db22015-03-17 11:39:28 +0200355 .has_fbc = 1,
Damien Lespiau1347f5b2015-03-17 11:39:27 +0200356 GEN_DEFAULT_PIPEOFFSETS,
357 IVB_CURSOR_OFFSETS,
Lionel Landwerlin82cf4352016-03-16 10:57:16 +0000358 BDW_COLORS,
Damien Lespiau1347f5b2015-03-17 11:39:27 +0200359};
360
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700361static const struct intel_device_info intel_kabylake_info = {
Lionel Landwerlin82cf4352016-03-16 10:57:16 +0000362 BDW_FEATURES,
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700363 .is_kabylake = 1,
364 .gen = 9,
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700365};
366
367static const struct intel_device_info intel_kabylake_gt3_info = {
Lionel Landwerlin82cf4352016-03-16 10:57:16 +0000368 BDW_FEATURES,
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700369 .is_kabylake = 1,
370 .gen = 9,
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700371 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700372};
373
Jesse Barnesa0a18072013-07-26 13:32:51 -0700374/*
375 * Make sure any device matches here are from most specific to most
376 * general. For example, since the Quanta match is based on the subsystem
377 * and subvendor IDs, we need it to come before the more general IVB
378 * PCI ID matches, otherwise we'll use the wrong info struct above.
379 */
Jani Nikula3cb27f32015-10-28 19:33:09 +0200380static const struct pci_device_id pciidlist[] = {
381 INTEL_I830_IDS(&intel_i830_info),
382 INTEL_I845G_IDS(&intel_845g_info),
383 INTEL_I85X_IDS(&intel_i85x_info),
384 INTEL_I865G_IDS(&intel_i865g_info),
385 INTEL_I915G_IDS(&intel_i915g_info),
386 INTEL_I915GM_IDS(&intel_i915gm_info),
387 INTEL_I945G_IDS(&intel_i945g_info),
388 INTEL_I945GM_IDS(&intel_i945gm_info),
389 INTEL_I965G_IDS(&intel_i965g_info),
390 INTEL_G33_IDS(&intel_g33_info),
391 INTEL_I965GM_IDS(&intel_i965gm_info),
392 INTEL_GM45_IDS(&intel_gm45_info),
393 INTEL_G45_IDS(&intel_g45_info),
394 INTEL_PINEVIEW_IDS(&intel_pineview_info),
395 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
396 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
397 INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
398 INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
399 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
400 INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
401 INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
402 INTEL_HSW_D_IDS(&intel_haswell_d_info),
403 INTEL_HSW_M_IDS(&intel_haswell_m_info),
404 INTEL_VLV_M_IDS(&intel_valleyview_m_info),
405 INTEL_VLV_D_IDS(&intel_valleyview_d_info),
406 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
407 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
408 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
409 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
410 INTEL_CHV_IDS(&intel_cherryview_info),
411 INTEL_SKL_GT1_IDS(&intel_skylake_info),
412 INTEL_SKL_GT2_IDS(&intel_skylake_info),
413 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
Mika Kuoppala15620202015-11-06 14:11:16 +0200414 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
Jani Nikula3cb27f32015-10-28 19:33:09 +0200415 INTEL_BXT_IDS(&intel_broxton_info),
Deepak Sd97044b2015-10-28 12:19:51 -0700416 INTEL_KBL_GT1_IDS(&intel_kabylake_info),
417 INTEL_KBL_GT2_IDS(&intel_kabylake_info),
418 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
Deepak S8b10c0c2015-10-28 12:21:12 -0700419 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
Kristian Høgsberg49ae35f2009-12-16 15:16:15 -0500420 {0, 0, 0}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700421};
422
Jesse Barnes79e53942008-11-07 14:24:08 -0800423MODULE_DEVICE_TABLE(pci, pciidlist);
Jesse Barnes79e53942008-11-07 14:24:08 -0800424
Robert Beckett30c964a2015-08-28 13:10:22 +0100425static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
426{
427 enum intel_pch ret = PCH_NOP;
428
429 /*
430 * In a virtualized passthrough environment we can be in a
431 * setup where the ISA bridge is not able to be passed through.
432 * In this case, a south bridge can be emulated and we have to
433 * make an educated guess as to which PCH is really there.
434 */
435
436 if (IS_GEN5(dev)) {
437 ret = PCH_IBX;
438 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
439 } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
440 ret = PCH_CPT;
441 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
442 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
443 ret = PCH_LPT;
444 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700445 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
Robert Beckett30c964a2015-08-28 13:10:22 +0100446 ret = PCH_SPT;
447 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
448 }
449
450 return ret;
451}
452
Akshay Joshi0206e352011-08-16 15:34:10 -0400453void intel_detect_pch(struct drm_device *dev)
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800454{
455 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deakbcdb72a2014-02-14 20:23:54 +0200456 struct pci_dev *pch = NULL;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800457
Ben Widawskyce1bb322013-04-05 13:12:44 -0700458 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
459 * (which really amounts to a PCH but no South Display).
460 */
461 if (INTEL_INFO(dev)->num_pipes == 0) {
462 dev_priv->pch_type = PCH_NOP;
Ben Widawskyce1bb322013-04-05 13:12:44 -0700463 return;
464 }
465
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800466 /*
467 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
468 * make graphics device passthrough work easy for VMM, that only
469 * need to expose ISA bridge to let driver know the real hardware
470 * underneath. This is a requirement from virtualization team.
Rui Guo6a9c4b32013-06-19 21:10:23 +0800471 *
472 * In some virtualized environments (e.g. XEN), there is irrelevant
473 * ISA bridge in the system. To work reliably, we should scan trhough
474 * all the ISA bridge devices and check for the first match, instead
475 * of only checking the first one.
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800476 */
Imre Deakbcdb72a2014-02-14 20:23:54 +0200477 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800478 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
Imre Deakbcdb72a2014-02-14 20:23:54 +0200479 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
Paulo Zanoni17a303e2012-11-20 15:12:07 -0200480 dev_priv->pch_id = id;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800481
Jesse Barnes90711d52011-04-28 14:48:02 -0700482 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
483 dev_priv->pch_type = PCH_IBX;
484 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100485 WARN_ON(!IS_GEN5(dev));
Jesse Barnes90711d52011-04-28 14:48:02 -0700486 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800487 dev_priv->pch_type = PCH_CPT;
488 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100489 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
Jesse Barnesc7925132011-04-07 12:33:56 -0700490 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
491 /* PantherPoint is CPT compatible */
492 dev_priv->pch_type = PCH_CPT;
Jani Nikula492ab662013-10-01 12:12:33 +0300493 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100494 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300495 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
496 dev_priv->pch_type = PCH_LPT;
497 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
Rodrigo Vivia35cc9d02015-01-21 10:33:53 -0800498 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
499 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
Ben Widawskye76e0632013-11-07 21:40:41 -0800500 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
501 dev_priv->pch_type = PCH_LPT;
502 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
Rodrigo Vivia35cc9d02015-01-21 10:33:53 -0800503 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
504 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +0530505 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
506 dev_priv->pch_type = PCH_SPT;
507 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700508 WARN_ON(!IS_SKYLAKE(dev) &&
509 !IS_KABYLAKE(dev));
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +0530510 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
511 dev_priv->pch_type = PCH_SPT;
512 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700513 WARN_ON(!IS_SKYLAKE(dev) &&
514 !IS_KABYLAKE(dev));
Rodrigo Vivibc7135b2016-07-01 17:07:12 -0700515 } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
516 dev_priv->pch_type = PCH_KBP;
517 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
518 WARN_ON(!IS_KABYLAKE(dev));
Gerd Hoffmann39bfcd522015-11-26 12:03:51 +0100519 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
Jesse Barnes1844a662016-03-16 13:31:30 -0700520 (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
Gerd Hoffmannf2e30512016-01-25 12:02:28 +0100521 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
522 pch->subsystem_vendor == 0x1af4 &&
523 pch->subsystem_device == 0x1100)) {
Robert Beckett30c964a2015-08-28 13:10:22 +0100524 dev_priv->pch_type = intel_virt_detect_pch(dev);
Imre Deakbcdb72a2014-02-14 20:23:54 +0200525 } else
526 continue;
527
Rui Guo6a9c4b32013-06-19 21:10:23 +0800528 break;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800529 }
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800530 }
Rui Guo6a9c4b32013-06-19 21:10:23 +0800531 if (!pch)
Imre Deakbcdb72a2014-02-14 20:23:54 +0200532 DRM_DEBUG_KMS("No PCH found.\n");
533
534 pci_dev_put(pch);
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800535}
536
Ben Widawsky2911a352012-04-05 14:47:36 -0700537bool i915_semaphore_is_enabled(struct drm_device *dev)
538{
539 if (INTEL_INFO(dev)->gen < 6)
Daniel Vettera08acaf2013-12-17 09:56:53 +0100540 return false;
Ben Widawsky2911a352012-04-05 14:47:36 -0700541
Jani Nikulad330a952014-01-21 11:24:25 +0200542 if (i915.semaphores >= 0)
543 return i915.semaphores;
Ben Widawsky2911a352012-04-05 14:47:36 -0700544
Oscar Mateo71386ef2014-07-24 17:04:44 +0100545 /* TODO: make semaphores and Execlists play nicely together */
546 if (i915.enable_execlists)
547 return false;
548
Rodrigo Vivibe71eab2014-08-04 11:15:19 -0700549 /* Until we get further testing... */
550 if (IS_GEN8(dev))
551 return false;
552
Daniel Vetter59de3292012-04-02 20:48:43 +0200553#ifdef CONFIG_INTEL_IOMMU
Ben Widawsky2911a352012-04-05 14:47:36 -0700554 /* Enable semaphores on SNB when IO remapping is off */
Daniel Vetter59de3292012-04-02 20:48:43 +0200555 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
556 return false;
557#endif
Ben Widawsky2911a352012-04-05 14:47:36 -0700558
Daniel Vettera08acaf2013-12-17 09:56:53 +0100559 return true;
Ben Widawsky2911a352012-04-05 14:47:36 -0700560}
561
Imre Deak07f9cd02014-08-18 14:42:45 +0300562static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
563{
564 struct drm_device *dev = dev_priv->dev;
Jani Nikula19c80542015-12-16 12:48:16 +0200565 struct intel_encoder *encoder;
Imre Deak07f9cd02014-08-18 14:42:45 +0300566
567 drm_modeset_lock_all(dev);
Jani Nikula19c80542015-12-16 12:48:16 +0200568 for_each_intel_encoder(dev, encoder)
569 if (encoder->suspend)
570 encoder->suspend(encoder);
Imre Deak07f9cd02014-08-18 14:42:45 +0300571 drm_modeset_unlock_all(dev);
572}
573
Paulo Zanoni1a5df182014-10-27 17:54:32 -0200574static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
575 bool rpm_resume);
Imre Deak507e1262016-04-20 20:27:54 +0300576static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
Suketu Shahf75a1982015-04-16 14:22:11 +0530577
Imre Deakbc872292015-11-18 17:32:30 +0200578static bool suspend_to_idle(struct drm_i915_private *dev_priv)
579{
580#if IS_ENABLED(CONFIG_ACPI_SLEEP)
581 if (acpi_target_system_state() < ACPI_STATE_S3)
582 return true;
583#endif
584 return false;
585}
Sagar Kambleebc32822014-08-13 23:07:05 +0530586
Imre Deak5e365c32014-10-23 19:23:25 +0300587static int i915_drm_suspend(struct drm_device *dev)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100588{
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100589 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnese5747e32014-06-12 08:35:47 -0700590 pci_power_t opregion_target_state;
Daniel Vetterd5818932015-02-23 12:03:26 +0100591 int error;
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100592
Zhang Ruib8efb172013-02-05 15:41:53 +0800593 /* ignore lid events during suspend */
594 mutex_lock(&dev_priv->modeset_restore_lock);
595 dev_priv->modeset_restore = MODESET_SUSPENDED;
596 mutex_unlock(&dev_priv->modeset_restore_lock);
597
Imre Deak1f814da2015-12-16 02:52:19 +0200598 disable_rpm_wakeref_asserts(dev_priv);
599
Paulo Zanonic67a4702013-08-19 13:18:09 -0300600 /* We do a lot of poking in a lot of registers, make sure they work
601 * properly. */
Imre Deakda7e29b2014-02-18 00:02:02 +0200602 intel_display_set_init_power(dev_priv, true);
Paulo Zanonicb107992013-01-25 16:59:15 -0200603
Dave Airlie5bcf7192010-12-07 09:20:40 +1000604 drm_kms_helper_poll_disable(dev);
605
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100606 pci_save_state(dev->pdev);
607
Daniel Vetterd5818932015-02-23 12:03:26 +0100608 error = i915_gem_suspend(dev);
609 if (error) {
610 dev_err(&dev->pdev->dev,
611 "GEM idle failed, resume might fail\n");
Imre Deak1f814da2015-12-16 02:52:19 +0200612 goto out;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100613 }
614
Alex Daia1c41992015-09-30 09:46:37 -0700615 intel_guc_suspend(dev);
616
Daniel Vetterd5818932015-02-23 12:03:26 +0100617 intel_suspend_gt_powersave(dev);
618
Maarten Lankhorst6b72d482015-06-01 12:49:47 +0200619 intel_display_suspend(dev);
Daniel Vetterd5818932015-02-23 12:03:26 +0100620
621 intel_dp_mst_suspend(dev);
622
623 intel_runtime_pm_disable_interrupts(dev_priv);
624 intel_hpd_cancel_work(dev_priv);
625
626 intel_suspend_encoders(dev_priv);
627
628 intel_suspend_hw(dev);
629
Ben Widawsky828c7902013-10-16 09:21:30 -0700630 i915_gem_suspend_gtt_mappings(dev);
631
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100632 i915_save_state(dev);
633
Imre Deakbc872292015-11-18 17:32:30 +0200634 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
Jesse Barnese5747e32014-06-12 08:35:47 -0700635 intel_opregion_notify_adapter(dev, opregion_target_state);
636
Jesse Barnes156c7ca2014-06-12 08:35:45 -0700637 intel_uncore_forcewake_reset(dev, false);
Chris Wilson44834a62010-08-19 16:09:23 +0100638 intel_opregion_fini(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100639
Chris Wilson82e3b8c2014-08-13 13:09:46 +0100640 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
Dave Airlie3fa016a2012-03-28 10:48:49 +0100641
Mika Kuoppala62d5d692014-02-25 17:11:28 +0200642 dev_priv->suspend_count++;
643
Kristen Carlson Accardi85e90672014-06-12 08:35:44 -0700644 intel_display_set_init_power(dev_priv, false);
645
Imre Deakf74ed082016-04-18 14:48:21 +0300646 intel_csr_ucode_suspend(dev_priv);
Imre Deakf514c2d2015-10-28 23:59:06 +0200647
Imre Deak1f814da2015-12-16 02:52:19 +0200648out:
649 enable_rpm_wakeref_asserts(dev_priv);
650
651 return error;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100652}
653
Imre Deakab3be732015-03-02 13:04:41 +0200654static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
Imre Deakc3c09c92014-10-23 19:23:15 +0300655{
656 struct drm_i915_private *dev_priv = drm_dev->dev_private;
Imre Deakbc872292015-11-18 17:32:30 +0200657 bool fw_csr;
Imre Deakc3c09c92014-10-23 19:23:15 +0300658 int ret;
659
Imre Deak1f814da2015-12-16 02:52:19 +0200660 disable_rpm_wakeref_asserts(dev_priv);
661
Imre Deaka7c81252016-04-01 16:02:38 +0300662 fw_csr = !IS_BROXTON(dev_priv) &&
663 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
Imre Deakbc872292015-11-18 17:32:30 +0200664 /*
665 * In case of firmware assisted context save/restore don't manually
666 * deinit the power domains. This also means the CSR/DMC firmware will
667 * stay active, it will power down any HW resources as required and
668 * also enable deeper system power states that would be blocked if the
669 * firmware was inactive.
670 */
671 if (!fw_csr)
672 intel_power_domains_suspend(dev_priv);
Imre Deak73dfc222015-11-17 17:33:53 +0200673
Imre Deak507e1262016-04-20 20:27:54 +0300674 ret = 0;
Imre Deakb8aea3d12016-04-20 20:27:55 +0300675 if (IS_BROXTON(dev_priv))
Imre Deak507e1262016-04-20 20:27:54 +0300676 bxt_enable_dc9(dev_priv);
Imre Deakb8aea3d12016-04-20 20:27:55 +0300677 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
Imre Deak507e1262016-04-20 20:27:54 +0300678 hsw_enable_pc8(dev_priv);
679 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
680 ret = vlv_suspend_complete(dev_priv);
Imre Deakc3c09c92014-10-23 19:23:15 +0300681
682 if (ret) {
683 DRM_ERROR("Suspend complete failed: %d\n", ret);
Imre Deakbc872292015-11-18 17:32:30 +0200684 if (!fw_csr)
685 intel_power_domains_init_hw(dev_priv, true);
Imre Deakc3c09c92014-10-23 19:23:15 +0300686
Imre Deak1f814da2015-12-16 02:52:19 +0200687 goto out;
Imre Deakc3c09c92014-10-23 19:23:15 +0300688 }
689
690 pci_disable_device(drm_dev->pdev);
Imre Deakab3be732015-03-02 13:04:41 +0200691 /*
Imre Deak54875572015-06-30 17:06:47 +0300692 * During hibernation on some platforms the BIOS may try to access
Imre Deakab3be732015-03-02 13:04:41 +0200693 * the device even though it's already in D3 and hang the machine. So
694 * leave the device in D0 on those platforms and hope the BIOS will
Imre Deak54875572015-06-30 17:06:47 +0300695 * power down the device properly. The issue was seen on multiple old
696 * GENs with different BIOS vendors, so having an explicit blacklist
697 * is inpractical; apply the workaround on everything pre GEN6. The
698 * platforms where the issue was seen:
699 * Lenovo Thinkpad X301, X61s, X60, T60, X41
700 * Fujitsu FSC S7110
701 * Acer Aspire 1830T
Imre Deakab3be732015-03-02 13:04:41 +0200702 */
Imre Deak54875572015-06-30 17:06:47 +0300703 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
Imre Deakab3be732015-03-02 13:04:41 +0200704 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
Imre Deakc3c09c92014-10-23 19:23:15 +0300705
Imre Deakbc872292015-11-18 17:32:30 +0200706 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
707
Imre Deak1f814da2015-12-16 02:52:19 +0200708out:
709 enable_rpm_wakeref_asserts(dev_priv);
710
711 return ret;
Imre Deakc3c09c92014-10-23 19:23:15 +0300712}
713
Maarten Lankhorst1751fcf2015-08-27 15:15:15 +0200714int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100715{
716 int error;
717
718 if (!dev || !dev->dev_private) {
719 DRM_ERROR("dev: %p\n", dev);
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700720 DRM_ERROR("DRM not initialized, aborting suspend.\n");
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000721 return -ENODEV;
722 }
723
Imre Deak0b14cbd2014-09-10 18:16:55 +0300724 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
725 state.event != PM_EVENT_FREEZE))
726 return -EINVAL;
Dave Airlie5bcf7192010-12-07 09:20:40 +1000727
728 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
729 return 0;
Chris Wilson6eecba32010-09-08 09:45:11 +0100730
Imre Deak5e365c32014-10-23 19:23:25 +0300731 error = i915_drm_suspend(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100732 if (error)
733 return error;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000734
Imre Deakab3be732015-03-02 13:04:41 +0200735 return i915_drm_suspend_late(dev, false);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000736}
737
Imre Deak5e365c32014-10-23 19:23:25 +0300738static int i915_drm_resume(struct drm_device *dev)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000739{
Jesse Barnes5669fca2009-02-17 15:13:31 -0800740 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä5fbd0412016-05-06 21:35:55 +0300741 int ret;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100742
Imre Deak1f814da2015-12-16 02:52:19 +0200743 disable_rpm_wakeref_asserts(dev_priv);
744
Ville Syrjälä5fbd0412016-05-06 21:35:55 +0300745 ret = i915_ggtt_enable_hw(dev);
746 if (ret)
747 DRM_ERROR("failed to re-enable GGTT\n");
748
Imre Deakf74ed082016-04-18 14:48:21 +0300749 intel_csr_ucode_resume(dev_priv);
750
Daniel Vetterd5818932015-02-23 12:03:26 +0100751 mutex_lock(&dev->struct_mutex);
752 i915_gem_restore_gtt_mappings(dev);
753 mutex_unlock(&dev->struct_mutex);
Paulo Zanoni9d49c0e2013-09-12 18:06:43 -0300754
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100755 i915_restore_state(dev);
Chris Wilson44834a62010-08-19 16:09:23 +0100756 intel_opregion_setup(dev);
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100757
Daniel Vetterd5818932015-02-23 12:03:26 +0100758 intel_init_pch_refclk(dev);
759 drm_mode_config_reset(dev);
Chris Wilson1833b132012-05-09 11:56:28 +0100760
Peter Antoine364aece2015-05-11 08:50:45 +0100761 /*
762 * Interrupts have to be enabled before any batches are run. If not the
763 * GPU will hang. i915_gem_init_hw() will initiate batches to
764 * update/restore the context.
765 *
766 * Modeset enabling in intel_modeset_init_hw() also needs working
767 * interrupts.
768 */
769 intel_runtime_pm_enable_interrupts(dev_priv);
770
Daniel Vetterd5818932015-02-23 12:03:26 +0100771 mutex_lock(&dev->struct_mutex);
772 if (i915_gem_init_hw(dev)) {
773 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
Peter Zijlstra805de8f42015-04-24 01:12:32 +0200774 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
Jesse Barnesd5bb0812011-01-05 12:01:26 -0800775 }
Daniel Vetterd5818932015-02-23 12:03:26 +0100776 mutex_unlock(&dev->struct_mutex);
777
Alex Daia1c41992015-09-30 09:46:37 -0700778 intel_guc_resume(dev);
779
Daniel Vetterd5818932015-02-23 12:03:26 +0100780 intel_modeset_init_hw(dev);
781
782 spin_lock_irq(&dev_priv->irq_lock);
783 if (dev_priv->display.hpd_irq_setup)
784 dev_priv->display.hpd_irq_setup(dev);
785 spin_unlock_irq(&dev_priv->irq_lock);
786
Daniel Vetterd5818932015-02-23 12:03:26 +0100787 intel_dp_mst_resume(dev);
788
Lyudea16b7652016-03-11 10:57:01 -0500789 intel_display_resume(dev);
790
Daniel Vetterd5818932015-02-23 12:03:26 +0100791 /*
792 * ... but also need to make sure that hotplug processing
793 * doesn't cause havoc. Like in the driver load code we don't
794 * bother with the tiny race here where we might loose hotplug
795 * notifications.
796 * */
797 intel_hpd_init(dev_priv);
798 /* Config may have changed between suspend and resume */
799 drm_helper_hpd_irq_event(dev);
Jesse Barnes1daed3f2011-01-05 12:01:25 -0800800
Chris Wilson44834a62010-08-19 16:09:23 +0100801 intel_opregion_init(dev);
802
Chris Wilson82e3b8c2014-08-13 13:09:46 +0100803 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
Jesse Barnes073f34d2012-11-02 11:13:59 -0700804
Zhang Ruib8efb172013-02-05 15:41:53 +0800805 mutex_lock(&dev_priv->modeset_restore_lock);
806 dev_priv->modeset_restore = MODESET_DONE;
807 mutex_unlock(&dev_priv->modeset_restore_lock);
Paulo Zanoni8a187452013-12-06 20:32:13 -0200808
Jesse Barnese5747e32014-06-12 08:35:47 -0700809 intel_opregion_notify_adapter(dev, PCI_D0);
810
Imre Deakee6f2802014-10-23 19:23:22 +0300811 drm_kms_helper_poll_enable(dev);
812
Imre Deak1f814da2015-12-16 02:52:19 +0200813 enable_rpm_wakeref_asserts(dev_priv);
814
Chris Wilson074c6ad2014-04-09 09:19:43 +0100815 return 0;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100816}
817
Imre Deak5e365c32014-10-23 19:23:25 +0300818static int i915_drm_resume_early(struct drm_device *dev)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100819{
Imre Deak36d61e62014-10-23 19:23:24 +0300820 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak44410cd2016-04-18 14:45:54 +0300821 int ret;
Imre Deak36d61e62014-10-23 19:23:24 +0300822
Imre Deak76c4b252014-04-01 19:55:22 +0300823 /*
824 * We have a resume ordering issue with the snd-hda driver also
825 * requiring our device to be power up. Due to the lack of a
826 * parent/child relationship we currently solve this with an early
827 * resume hook.
828 *
829 * FIXME: This should be solved with a special hdmi sink device or
830 * similar so that power domains can be employed.
831 */
Imre Deak44410cd2016-04-18 14:45:54 +0300832
833 /*
834 * Note that we need to set the power state explicitly, since we
835 * powered off the device during freeze and the PCI core won't power
836 * it back up for us during thaw. Powering off the device during
837 * freeze is not a hard requirement though, and during the
838 * suspend/resume phases the PCI core makes sure we get here with the
839 * device powered on. So in case we change our freeze logic and keep
840 * the device powered we can also remove the following set power state
841 * call.
842 */
843 ret = pci_set_power_state(dev->pdev, PCI_D0);
844 if (ret) {
845 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
846 goto out;
847 }
848
849 /*
850 * Note that pci_enable_device() first enables any parent bridge
851 * device and only then sets the power state for this device. The
852 * bridge enabling is a nop though, since bridge devices are resumed
853 * first. The order of enabling power and enabling the device is
854 * imposed by the PCI core as described above, so here we preserve the
855 * same order for the freeze/thaw phases.
856 *
857 * TODO: eventually we should remove pci_disable_device() /
858 * pci_enable_enable_device() from suspend/resume. Due to how they
859 * depend on the device enable refcount we can't anyway depend on them
860 * disabling/enabling the device.
861 */
Imre Deakbc872292015-11-18 17:32:30 +0200862 if (pci_enable_device(dev->pdev)) {
863 ret = -EIO;
864 goto out;
865 }
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100866
867 pci_set_master(dev->pdev);
868
Imre Deak1f814da2015-12-16 02:52:19 +0200869 disable_rpm_wakeref_asserts(dev_priv);
870
Wayne Boyer666a4532015-12-09 12:29:35 -0800871 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Paulo Zanoni1a5df182014-10-27 17:54:32 -0200872 ret = vlv_resume_prepare(dev_priv, false);
Imre Deak36d61e62014-10-23 19:23:24 +0300873 if (ret)
Damien Lespiauff0b1872015-05-20 14:45:15 +0100874 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
875 ret);
Imre Deak36d61e62014-10-23 19:23:24 +0300876
877 intel_uncore_early_sanitize(dev, true);
Paulo Zanoniefee8332014-10-27 17:54:33 -0200878
Imre Deakda2f41d2016-04-20 20:27:56 +0300879 if (IS_BROXTON(dev)) {
880 if (!dev_priv->suspended_to_idle)
881 gen9_sanitize_dc_state(dev_priv);
Imre Deak507e1262016-04-20 20:27:54 +0300882 bxt_disable_dc9(dev_priv);
Imre Deakda2f41d2016-04-20 20:27:56 +0300883 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
Damien Lespiaua9a6b732015-05-20 14:45:14 +0100884 hsw_disable_pc8(dev_priv);
Imre Deakda2f41d2016-04-20 20:27:56 +0300885 }
Paulo Zanoniefee8332014-10-27 17:54:33 -0200886
Imre Deak36d61e62014-10-23 19:23:24 +0300887 intel_uncore_sanitize(dev);
Imre Deakbc872292015-11-18 17:32:30 +0200888
Imre Deaka7c81252016-04-01 16:02:38 +0300889 if (IS_BROXTON(dev_priv) ||
890 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
Imre Deakbc872292015-11-18 17:32:30 +0200891 intel_power_domains_init_hw(dev_priv, true);
892
Imre Deak6e35e8a2016-04-18 10:04:19 +0300893 enable_rpm_wakeref_asserts(dev_priv);
894
Imre Deakbc872292015-11-18 17:32:30 +0200895out:
896 dev_priv->suspended_to_idle = false;
Imre Deak36d61e62014-10-23 19:23:24 +0300897
898 return ret;
Imre Deak76c4b252014-04-01 19:55:22 +0300899}
900
Maarten Lankhorst1751fcf2015-08-27 15:15:15 +0200901int i915_resume_switcheroo(struct drm_device *dev)
Imre Deak76c4b252014-04-01 19:55:22 +0300902{
Imre Deak50a00722014-10-23 19:23:17 +0300903 int ret;
Imre Deak76c4b252014-04-01 19:55:22 +0300904
Imre Deak097dd832014-10-23 19:23:19 +0300905 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
906 return 0;
907
Imre Deak5e365c32014-10-23 19:23:25 +0300908 ret = i915_drm_resume_early(dev);
Imre Deak50a00722014-10-23 19:23:17 +0300909 if (ret)
910 return ret;
911
Imre Deak5a175142014-10-23 19:23:18 +0300912 return i915_drm_resume(dev);
913}
914
Ben Gamari11ed50e2009-09-14 17:48:45 -0400915/**
Eugeni Dodonovf3953dc2011-11-28 16:15:17 -0200916 * i915_reset - reset chip after a hang
Ben Gamari11ed50e2009-09-14 17:48:45 -0400917 * @dev: drm device to reset
Ben Gamari11ed50e2009-09-14 17:48:45 -0400918 *
919 * Reset the chip. Useful if a hang is detected. Returns zero on successful
920 * reset or otherwise an error code.
921 *
922 * Procedure is fairly simple:
923 * - reset the chip using the reset reg
924 * - re-init context state
925 * - re-init hardware status page
926 * - re-init ring buffer
927 * - re-init interrupt state
928 * - re-init display
929 */
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200930int i915_reset(struct drm_device *dev)
Ben Gamari11ed50e2009-09-14 17:48:45 -0400931{
Jani Nikula50227e12014-03-31 14:27:21 +0300932 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond98c52c2016-04-13 17:35:05 +0100933 struct i915_gpu_error *error = &dev_priv->gpu_error;
934 unsigned reset_counter;
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700935 int ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400936
Imre Deakdbea3ce2014-12-15 18:59:28 +0200937 intel_reset_gt_powersave(dev);
938
Daniel Vetterd54a02c2012-07-04 22:18:39 +0200939 mutex_lock(&dev->struct_mutex);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400940
Chris Wilsond98c52c2016-04-13 17:35:05 +0100941 /* Clear any previous failed attempts at recovery. Time to try again. */
942 atomic_andnot(I915_WEDGED, &error->reset_counter);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400943
Chris Wilsond98c52c2016-04-13 17:35:05 +0100944 /* Clear the reset-in-progress flag and increment the reset epoch. */
945 reset_counter = atomic_inc_return(&error->reset_counter);
946 if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
947 ret = -EIO;
948 goto error;
949 }
950
951 i915_gem_reset(dev);
Chris Wilson2e7c8ee2013-05-28 10:38:44 +0100952
Mika Kuoppalaee4b6fa2016-03-16 17:54:00 +0200953 ret = intel_gpu_reset(dev, ALL_ENGINES);
Daniel Vetter350d2702012-04-27 15:17:42 +0200954
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300955 /* Also reset the gpu hangman. */
Chris Wilsond98c52c2016-04-13 17:35:05 +0100956 if (error->stop_rings != 0) {
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300957 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
Chris Wilsond98c52c2016-04-13 17:35:05 +0100958 error->stop_rings = 0;
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300959 if (ret == -ENODEV) {
Daniel Vetterf2d91a22013-11-07 09:48:57 +0100960 DRM_INFO("Reset not implemented, but ignoring "
961 "error for simulated gpu hangs\n");
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300962 ret = 0;
963 }
Chris Wilson2e7c8ee2013-05-28 10:38:44 +0100964 }
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300965
Daniel Vetterd8f27162014-10-01 01:02:04 +0200966 if (i915_stop_ring_allow_warn(dev_priv))
967 pr_notice("drm/i915: Resetting chip after gpu hang\n");
968
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700969 if (ret) {
Chris Wilson804e59a2016-04-13 17:35:09 +0100970 if (ret != -ENODEV)
971 DRM_ERROR("Failed to reset chip: %i\n", ret);
972 else
973 DRM_DEBUG_DRIVER("GPU reset disabled\n");
Chris Wilsond98c52c2016-04-13 17:35:05 +0100974 goto error;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400975 }
976
Ville Syrjälä1362b772014-11-26 17:07:29 +0200977 intel_overlay_reset(dev_priv);
978
Ben Gamari11ed50e2009-09-14 17:48:45 -0400979 /* Ok, now get things going again... */
980
981 /*
982 * Everything depends on having the GTT running, so we need to start
983 * there. Fortunately we don't need to do this unless we reset the
984 * chip at a PCI level.
985 *
986 * Next we need to restore the context, but we don't use those
987 * yet either...
988 *
989 * Ring buffer needs to be re-initialized in the KMS case, or if X
990 * was running at the time of the reset (i.e. we weren't VT
991 * switched away).
992 */
Daniel Vetter33d30a92015-02-23 12:03:27 +0100993 ret = i915_gem_init_hw(dev);
Daniel Vetter33d30a92015-02-23 12:03:27 +0100994 if (ret) {
995 DRM_ERROR("Failed hw init on reset %d\n", ret);
Chris Wilsond98c52c2016-04-13 17:35:05 +0100996 goto error;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400997 }
998
Chris Wilsond98c52c2016-04-13 17:35:05 +0100999 mutex_unlock(&dev->struct_mutex);
1000
Daniel Vetter33d30a92015-02-23 12:03:27 +01001001 /*
Daniel Vetter33d30a92015-02-23 12:03:27 +01001002 * rps/rc6 re-init is necessary to restore state lost after the
1003 * reset and the re-install of gt irqs. Skip for ironlake per
1004 * previous concerns that it doesn't respond well to some forms
1005 * of re-init after reset.
1006 */
1007 if (INTEL_INFO(dev)->gen > 5)
1008 intel_enable_gt_powersave(dev);
1009
Ben Gamari11ed50e2009-09-14 17:48:45 -04001010 return 0;
Chris Wilsond98c52c2016-04-13 17:35:05 +01001011
1012error:
1013 atomic_or(I915_WEDGED, &error->reset_counter);
1014 mutex_unlock(&dev->struct_mutex);
1015 return ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -04001016}
1017
Greg Kroah-Hartman56550d92012-12-21 15:09:25 -08001018static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
Kristian Høgsberg112b7152009-01-04 16:55:33 -05001019{
Daniel Vetter01a06852012-06-25 15:58:49 +02001020 struct intel_device_info *intel_info =
1021 (struct intel_device_info *) ent->driver_data;
1022
Jani Nikulad330a952014-01-21 11:24:25 +02001023 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
Ben Widawskyb833d682013-08-23 16:00:07 -07001024 DRM_INFO("This hardware requires preliminary hardware support.\n"
1025 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
1026 return -ENODEV;
1027 }
1028
Chris Wilson5fe49d82011-02-01 19:43:02 +00001029 /* Only bind to function 0 of the device. Early generations
1030 * used function 1 as a placeholder for multi-head. This causes
1031 * us confusion instead, especially on the systems where both
1032 * functions have the same PCI-ID!
1033 */
1034 if (PCI_FUNC(pdev->devfn))
1035 return -ENODEV;
1036
Lukas Wunner704ab612016-01-11 20:09:20 +01001037 /*
1038 * apple-gmux is needed on dual GPU MacBook Pro
1039 * to probe the panel if we're the inactive GPU.
1040 */
1041 if (IS_ENABLED(CONFIG_VGA_ARB) && IS_ENABLED(CONFIG_VGA_SWITCHEROO) &&
1042 apple_gmux_present() && pdev != vga_default_device() &&
1043 !vga_switcheroo_handler_flags())
1044 return -EPROBE_DEFER;
1045
Jordan Crousedcdb1672010-05-27 13:40:25 -06001046 return drm_get_pci_dev(pdev, ent, &driver);
Kristian Høgsberg112b7152009-01-04 16:55:33 -05001047}
1048
1049static void
1050i915_pci_remove(struct pci_dev *pdev)
1051{
1052 struct drm_device *dev = pci_get_drvdata(pdev);
1053
1054 drm_put_dev(dev);
1055}
1056
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001057static int i915_pm_suspend(struct device *dev)
Kristian Høgsberg112b7152009-01-04 16:55:33 -05001058{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001059 struct pci_dev *pdev = to_pci_dev(dev);
1060 struct drm_device *drm_dev = pci_get_drvdata(pdev);
Kristian Høgsberg112b7152009-01-04 16:55:33 -05001061
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001062 if (!drm_dev || !drm_dev->dev_private) {
1063 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1064 return -ENODEV;
1065 }
Kristian Høgsberg112b7152009-01-04 16:55:33 -05001066
Dave Airlie5bcf7192010-12-07 09:20:40 +10001067 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1068 return 0;
1069
Imre Deak5e365c32014-10-23 19:23:25 +03001070 return i915_drm_suspend(drm_dev);
Imre Deak76c4b252014-04-01 19:55:22 +03001071}
1072
1073static int i915_pm_suspend_late(struct device *dev)
1074{
Imre Deak888d0d42015-01-08 17:54:13 +02001075 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
Imre Deak76c4b252014-04-01 19:55:22 +03001076
1077 /*
Damien Lespiauc965d9952015-05-18 19:53:48 +01001078 * We have a suspend ordering issue with the snd-hda driver also
Imre Deak76c4b252014-04-01 19:55:22 +03001079 * requiring our device to be power up. Due to the lack of a
1080 * parent/child relationship we currently solve this with an late
1081 * suspend hook.
1082 *
1083 * FIXME: This should be solved with a special hdmi sink device or
1084 * similar so that power domains can be employed.
1085 */
1086 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1087 return 0;
Kristian Høgsberg112b7152009-01-04 16:55:33 -05001088
Imre Deakab3be732015-03-02 13:04:41 +02001089 return i915_drm_suspend_late(drm_dev, false);
1090}
1091
1092static int i915_pm_poweroff_late(struct device *dev)
1093{
1094 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1095
1096 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1097 return 0;
1098
1099 return i915_drm_suspend_late(drm_dev, true);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001100}
1101
Imre Deak76c4b252014-04-01 19:55:22 +03001102static int i915_pm_resume_early(struct device *dev)
1103{
Imre Deak888d0d42015-01-08 17:54:13 +02001104 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
Imre Deak76c4b252014-04-01 19:55:22 +03001105
Imre Deak097dd832014-10-23 19:23:19 +03001106 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1107 return 0;
1108
Imre Deak5e365c32014-10-23 19:23:25 +03001109 return i915_drm_resume_early(drm_dev);
Imre Deak76c4b252014-04-01 19:55:22 +03001110}
1111
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001112static int i915_pm_resume(struct device *dev)
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001113{
Imre Deak888d0d42015-01-08 17:54:13 +02001114 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001115
Imre Deak097dd832014-10-23 19:23:19 +03001116 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1117 return 0;
1118
Imre Deak5a175142014-10-23 19:23:18 +03001119 return i915_drm_resume(drm_dev);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001120}
1121
Imre Deakddeea5b2014-05-05 15:19:56 +03001122/*
1123 * Save all Gunit registers that may be lost after a D3 and a subsequent
1124 * S0i[R123] transition. The list of registers needing a save/restore is
1125 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1126 * registers in the following way:
1127 * - Driver: saved/restored by the driver
1128 * - Punit : saved/restored by the Punit firmware
1129 * - No, w/o marking: no need to save/restore, since the register is R/O or
1130 * used internally by the HW in a way that doesn't depend
1131 * keeping the content across a suspend/resume.
1132 * - Debug : used for debugging
1133 *
1134 * We save/restore all registers marked with 'Driver', with the following
1135 * exceptions:
1136 * - Registers out of use, including also registers marked with 'Debug'.
1137 * These have no effect on the driver's operation, so we don't save/restore
1138 * them to reduce the overhead.
1139 * - Registers that are fully setup by an initialization function called from
1140 * the resume path. For example many clock gating and RPS/RC6 registers.
1141 * - Registers that provide the right functionality with their reset defaults.
1142 *
1143 * TODO: Except for registers that based on the above 3 criteria can be safely
1144 * ignored, we save/restore all others, practically treating the HW context as
1145 * a black-box for the driver. Further investigation is needed to reduce the
1146 * saved/restored registers even further, by following the same 3 criteria.
1147 */
1148static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1149{
1150 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1151 int i;
1152
1153 /* GAM 0x4000-0x4770 */
1154 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1155 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1156 s->arb_mode = I915_READ(ARB_MODE);
1157 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1158 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1159
1160 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
Ville Syrjälä22dfe792015-09-18 20:03:16 +03001161 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
Imre Deakddeea5b2014-05-05 15:19:56 +03001162
1163 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
Imre Deakb5f1c972015-04-15 16:52:30 -07001164 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
Imre Deakddeea5b2014-05-05 15:19:56 +03001165
1166 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1167 s->ecochk = I915_READ(GAM_ECOCHK);
1168 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1169 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1170
1171 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1172
1173 /* MBC 0x9024-0x91D0, 0x8500 */
1174 s->g3dctl = I915_READ(VLV_G3DCTL);
1175 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1176 s->mbctl = I915_READ(GEN6_MBCTL);
1177
1178 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1179 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1180 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1181 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1182 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1183 s->rstctl = I915_READ(GEN6_RSTCTL);
1184 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1185
1186 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1187 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1188 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1189 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1190 s->ecobus = I915_READ(ECOBUS);
1191 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1192 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1193 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1194 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1195 s->rcedata = I915_READ(VLV_RCEDATA);
1196 s->spare2gh = I915_READ(VLV_SPAREG2H);
1197
1198 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1199 s->gt_imr = I915_READ(GTIMR);
1200 s->gt_ier = I915_READ(GTIER);
1201 s->pm_imr = I915_READ(GEN6_PMIMR);
1202 s->pm_ier = I915_READ(GEN6_PMIER);
1203
1204 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
Ville Syrjälä22dfe792015-09-18 20:03:16 +03001205 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
Imre Deakddeea5b2014-05-05 15:19:56 +03001206
1207 /* GT SA CZ domain, 0x100000-0x138124 */
1208 s->tilectl = I915_READ(TILECTL);
1209 s->gt_fifoctl = I915_READ(GTFIFOCTL);
1210 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1211 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1212 s->pmwgicz = I915_READ(VLV_PMWGICZ);
1213
1214 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1215 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1216 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
Jesse Barnes9c252102015-04-01 14:22:57 -07001217 s->pcbr = I915_READ(VLV_PCBR);
Imre Deakddeea5b2014-05-05 15:19:56 +03001218 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1219
1220 /*
1221 * Not saving any of:
1222 * DFT, 0x9800-0x9EC0
1223 * SARB, 0xB000-0xB1FC
1224 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1225 * PCI CFG
1226 */
1227}
1228
1229static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1230{
1231 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1232 u32 val;
1233 int i;
1234
1235 /* GAM 0x4000-0x4770 */
1236 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1237 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1238 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1239 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1240 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1241
1242 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
Ville Syrjälä22dfe792015-09-18 20:03:16 +03001243 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
Imre Deakddeea5b2014-05-05 15:19:56 +03001244
1245 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
Imre Deakb5f1c972015-04-15 16:52:30 -07001246 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
Imre Deakddeea5b2014-05-05 15:19:56 +03001247
1248 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1249 I915_WRITE(GAM_ECOCHK, s->ecochk);
1250 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1251 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1252
1253 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1254
1255 /* MBC 0x9024-0x91D0, 0x8500 */
1256 I915_WRITE(VLV_G3DCTL, s->g3dctl);
1257 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1258 I915_WRITE(GEN6_MBCTL, s->mbctl);
1259
1260 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1261 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1262 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1263 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1264 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1265 I915_WRITE(GEN6_RSTCTL, s->rstctl);
1266 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1267
1268 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1269 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1270 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1271 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1272 I915_WRITE(ECOBUS, s->ecobus);
1273 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1274 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1275 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1276 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1277 I915_WRITE(VLV_RCEDATA, s->rcedata);
1278 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1279
1280 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1281 I915_WRITE(GTIMR, s->gt_imr);
1282 I915_WRITE(GTIER, s->gt_ier);
1283 I915_WRITE(GEN6_PMIMR, s->pm_imr);
1284 I915_WRITE(GEN6_PMIER, s->pm_ier);
1285
1286 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
Ville Syrjälä22dfe792015-09-18 20:03:16 +03001287 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
Imre Deakddeea5b2014-05-05 15:19:56 +03001288
1289 /* GT SA CZ domain, 0x100000-0x138124 */
1290 I915_WRITE(TILECTL, s->tilectl);
1291 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1292 /*
1293 * Preserve the GT allow wake and GFX force clock bit, they are not
1294 * be restored, as they are used to control the s0ix suspend/resume
1295 * sequence by the caller.
1296 */
1297 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1298 val &= VLV_GTLC_ALLOWWAKEREQ;
1299 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1300 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1301
1302 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1303 val &= VLV_GFX_CLK_FORCE_ON_BIT;
1304 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1305 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1306
1307 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1308
1309 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1310 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1311 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
Jesse Barnes9c252102015-04-01 14:22:57 -07001312 I915_WRITE(VLV_PCBR, s->pcbr);
Imre Deakddeea5b2014-05-05 15:19:56 +03001313 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1314}
1315
Imre Deak650ad972014-04-18 16:35:02 +03001316int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1317{
1318 u32 val;
1319 int err;
1320
Imre Deak650ad972014-04-18 16:35:02 +03001321#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
Imre Deak650ad972014-04-18 16:35:02 +03001322
1323 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1324 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1325 if (force_on)
1326 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1327 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1328
1329 if (!force_on)
1330 return 0;
1331
Imre Deak8d4eee92014-04-14 20:24:43 +03001332 err = wait_for(COND, 20);
Imre Deak650ad972014-04-18 16:35:02 +03001333 if (err)
1334 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1335 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1336
1337 return err;
1338#undef COND
1339}
1340
Imre Deakddeea5b2014-05-05 15:19:56 +03001341static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1342{
1343 u32 val;
1344 int err = 0;
1345
1346 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1347 val &= ~VLV_GTLC_ALLOWWAKEREQ;
1348 if (allow)
1349 val |= VLV_GTLC_ALLOWWAKEREQ;
1350 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1351 POSTING_READ(VLV_GTLC_WAKE_CTRL);
1352
1353#define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1354 allow)
1355 err = wait_for(COND, 1);
1356 if (err)
1357 DRM_ERROR("timeout disabling GT waking\n");
1358 return err;
1359#undef COND
1360}
1361
1362static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1363 bool wait_for_on)
1364{
1365 u32 mask;
1366 u32 val;
1367 int err;
1368
1369 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1370 val = wait_for_on ? mask : 0;
1371#define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1372 if (COND)
1373 return 0;
1374
1375 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
Jani Nikula87ad3212016-01-14 12:53:34 +02001376 onoff(wait_for_on),
1377 I915_READ(VLV_GTLC_PW_STATUS));
Imre Deakddeea5b2014-05-05 15:19:56 +03001378
1379 /*
1380 * RC6 transitioning can be delayed up to 2 msec (see
1381 * valleyview_enable_rps), use 3 msec for safety.
1382 */
1383 err = wait_for(COND, 3);
1384 if (err)
1385 DRM_ERROR("timeout waiting for GT wells to go %s\n",
Jani Nikula87ad3212016-01-14 12:53:34 +02001386 onoff(wait_for_on));
Imre Deakddeea5b2014-05-05 15:19:56 +03001387
1388 return err;
1389#undef COND
1390}
1391
1392static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1393{
1394 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1395 return;
1396
Daniel Vetter6fa283b2016-01-19 21:00:56 +01001397 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
Imre Deakddeea5b2014-05-05 15:19:56 +03001398 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1399}
1400
Sagar Kambleebc32822014-08-13 23:07:05 +05301401static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
Imre Deakddeea5b2014-05-05 15:19:56 +03001402{
1403 u32 mask;
1404 int err;
1405
1406 /*
1407 * Bspec defines the following GT well on flags as debug only, so
1408 * don't treat them as hard failures.
1409 */
1410 (void)vlv_wait_for_gt_wells(dev_priv, false);
1411
1412 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1413 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1414
1415 vlv_check_no_gt_access(dev_priv);
1416
1417 err = vlv_force_gfx_clock(dev_priv, true);
1418 if (err)
1419 goto err1;
1420
1421 err = vlv_allow_gt_wake(dev_priv, false);
1422 if (err)
1423 goto err2;
Deepak S98711162014-12-12 14:18:16 +05301424
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03001425 if (!IS_CHERRYVIEW(dev_priv))
Deepak S98711162014-12-12 14:18:16 +05301426 vlv_save_gunit_s0ix_state(dev_priv);
Imre Deakddeea5b2014-05-05 15:19:56 +03001427
1428 err = vlv_force_gfx_clock(dev_priv, false);
1429 if (err)
1430 goto err2;
1431
1432 return 0;
1433
1434err2:
1435 /* For safety always re-enable waking and disable gfx clock forcing */
1436 vlv_allow_gt_wake(dev_priv, true);
1437err1:
1438 vlv_force_gfx_clock(dev_priv, false);
1439
1440 return err;
1441}
1442
Sagar Kamble016970b2014-08-13 23:07:06 +05301443static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1444 bool rpm_resume)
Imre Deakddeea5b2014-05-05 15:19:56 +03001445{
1446 struct drm_device *dev = dev_priv->dev;
1447 int err;
1448 int ret;
1449
1450 /*
1451 * If any of the steps fail just try to continue, that's the best we
1452 * can do at this point. Return the first error code (which will also
1453 * leave RPM permanently disabled).
1454 */
1455 ret = vlv_force_gfx_clock(dev_priv, true);
1456
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +03001457 if (!IS_CHERRYVIEW(dev_priv))
Deepak S98711162014-12-12 14:18:16 +05301458 vlv_restore_gunit_s0ix_state(dev_priv);
Imre Deakddeea5b2014-05-05 15:19:56 +03001459
1460 err = vlv_allow_gt_wake(dev_priv, true);
1461 if (!ret)
1462 ret = err;
1463
1464 err = vlv_force_gfx_clock(dev_priv, false);
1465 if (!ret)
1466 ret = err;
1467
1468 vlv_check_no_gt_access(dev_priv);
1469
Sagar Kamble016970b2014-08-13 23:07:06 +05301470 if (rpm_resume) {
1471 intel_init_clock_gating(dev);
1472 i915_gem_restore_fences(dev);
1473 }
Imre Deakddeea5b2014-05-05 15:19:56 +03001474
1475 return ret;
1476}
1477
Paulo Zanoni97bea202014-03-07 20:12:33 -03001478static int intel_runtime_suspend(struct device *device)
Paulo Zanoni8a187452013-12-06 20:32:13 -02001479{
1480 struct pci_dev *pdev = to_pci_dev(device);
1481 struct drm_device *dev = pci_get_drvdata(pdev);
1482 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001483 int ret;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001484
Imre Deakaeab0b52014-04-14 20:24:36 +03001485 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
Imre Deakc6df39b2014-04-14 20:24:29 +03001486 return -ENODEV;
1487
Imre Deak604effb2014-08-26 13:26:56 +03001488 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1489 return -ENODEV;
1490
Paulo Zanoni8a187452013-12-06 20:32:13 -02001491 DRM_DEBUG_KMS("Suspending device\n");
1492
Imre Deak9486db62014-04-22 20:21:07 +03001493 /*
Imre Deakd6102972014-05-07 19:57:49 +03001494 * We could deadlock here in case another thread holding struct_mutex
1495 * calls RPM suspend concurrently, since the RPM suspend will wait
1496 * first for this RPM suspend to finish. In this case the concurrent
1497 * RPM resume will be followed by its RPM suspend counterpart. Still
1498 * for consistency return -EAGAIN, which will reschedule this suspend.
1499 */
1500 if (!mutex_trylock(&dev->struct_mutex)) {
1501 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1502 /*
1503 * Bump the expiration timestamp, otherwise the suspend won't
1504 * be rescheduled.
1505 */
1506 pm_runtime_mark_last_busy(device);
1507
1508 return -EAGAIN;
1509 }
Imre Deak1f814da2015-12-16 02:52:19 +02001510
1511 disable_rpm_wakeref_asserts(dev_priv);
1512
Imre Deakd6102972014-05-07 19:57:49 +03001513 /*
1514 * We are safe here against re-faults, since the fault handler takes
1515 * an RPM reference.
1516 */
1517 i915_gem_release_all_mmaps(dev_priv);
1518 mutex_unlock(&dev->struct_mutex);
1519
Joonas Lahtinen825f2722015-12-09 15:56:13 +02001520 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1521
Alex Daia1c41992015-09-30 09:46:37 -07001522 intel_guc_suspend(dev);
1523
Paulo Zanonifac6adb2014-10-30 15:59:31 -02001524 intel_suspend_gt_powersave(dev);
Imre Deak2eb52522014-11-19 15:30:05 +02001525 intel_runtime_pm_disable_interrupts(dev_priv);
Imre Deakb5478bc2014-04-14 20:24:37 +03001526
Imre Deak507e1262016-04-20 20:27:54 +03001527 ret = 0;
1528 if (IS_BROXTON(dev_priv)) {
1529 bxt_display_core_uninit(dev_priv);
1530 bxt_enable_dc9(dev_priv);
1531 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1532 hsw_enable_pc8(dev_priv);
1533 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1534 ret = vlv_suspend_complete(dev_priv);
1535 }
1536
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001537 if (ret) {
1538 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
Daniel Vetterb9632912014-09-30 10:56:44 +02001539 intel_runtime_pm_enable_interrupts(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001540
Imre Deak1f814da2015-12-16 02:52:19 +02001541 enable_rpm_wakeref_asserts(dev_priv);
1542
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001543 return ret;
1544 }
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001545
Chris Wilsondc9fb092015-01-16 11:34:34 +02001546 intel_uncore_forcewake_reset(dev, false);
Imre Deak1f814da2015-12-16 02:52:19 +02001547
1548 enable_rpm_wakeref_asserts(dev_priv);
1549 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
Mika Kuoppala55ec45c2015-12-15 16:25:08 +02001550
Mika Kuoppalabc3b9342016-01-08 15:51:20 +02001551 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
Mika Kuoppala55ec45c2015-12-15 16:25:08 +02001552 DRM_ERROR("Unclaimed access detected prior to suspending\n");
1553
Paulo Zanoni8a187452013-12-06 20:32:13 -02001554 dev_priv->pm.suspended = true;
Kristen Carlson Accardi1fb23622014-01-14 15:36:15 -08001555
1556 /*
Paulo Zanonic8a0bd42014-08-21 17:09:38 -03001557 * FIXME: We really should find a document that references the arguments
1558 * used below!
Kristen Carlson Accardi1fb23622014-01-14 15:36:15 -08001559 */
Paulo Zanonid37ae192015-07-30 18:20:29 -03001560 if (IS_BROADWELL(dev)) {
1561 /*
1562 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1563 * being detected, and the call we do at intel_runtime_resume()
1564 * won't be able to restore them. Since PCI_D3hot matches the
1565 * actual specification and appears to be working, use it.
1566 */
1567 intel_opregion_notify_adapter(dev, PCI_D3hot);
1568 } else {
Paulo Zanonic8a0bd42014-08-21 17:09:38 -03001569 /*
1570 * current versions of firmware which depend on this opregion
1571 * notification have repurposed the D1 definition to mean
1572 * "runtime suspended" vs. what you would normally expect (D3)
1573 * to distinguish it from notifications that might be sent via
1574 * the suspend path.
1575 */
1576 intel_opregion_notify_adapter(dev, PCI_D1);
Paulo Zanonic8a0bd42014-08-21 17:09:38 -03001577 }
Paulo Zanoni8a187452013-12-06 20:32:13 -02001578
Mika Kuoppala59bad942015-01-16 11:34:40 +02001579 assert_forcewakes_inactive(dev_priv);
Chris Wilsondc9fb092015-01-16 11:34:34 +02001580
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001581 DRM_DEBUG_KMS("Device suspended\n");
Paulo Zanoni8a187452013-12-06 20:32:13 -02001582 return 0;
1583}
1584
Paulo Zanoni97bea202014-03-07 20:12:33 -03001585static int intel_runtime_resume(struct device *device)
Paulo Zanoni8a187452013-12-06 20:32:13 -02001586{
1587 struct pci_dev *pdev = to_pci_dev(device);
1588 struct drm_device *dev = pci_get_drvdata(pdev);
1589 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni1a5df182014-10-27 17:54:32 -02001590 int ret = 0;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001591
Imre Deak604effb2014-08-26 13:26:56 +03001592 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1593 return -ENODEV;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001594
1595 DRM_DEBUG_KMS("Resuming device\n");
1596
Imre Deak1f814da2015-12-16 02:52:19 +02001597 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1598 disable_rpm_wakeref_asserts(dev_priv);
1599
Paulo Zanonicd2e9e92013-12-06 20:34:21 -02001600 intel_opregion_notify_adapter(dev, PCI_D0);
Paulo Zanoni8a187452013-12-06 20:32:13 -02001601 dev_priv->pm.suspended = false;
Mika Kuoppala55ec45c2015-12-15 16:25:08 +02001602 if (intel_uncore_unclaimed_mmio(dev_priv))
1603 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
Paulo Zanoni8a187452013-12-06 20:32:13 -02001604
Alex Daia1c41992015-09-30 09:46:37 -07001605 intel_guc_resume(dev);
1606
Paulo Zanoni1a5df182014-10-27 17:54:32 -02001607 if (IS_GEN6(dev_priv))
1608 intel_init_pch_refclk(dev);
Suketu Shah31335ce2014-11-24 13:37:45 +05301609
Imre Deak507e1262016-04-20 20:27:54 +03001610 if (IS_BROXTON(dev)) {
1611 bxt_disable_dc9(dev_priv);
1612 bxt_display_core_init(dev_priv, true);
Imre Deakf62c79b2016-04-20 20:27:57 +03001613 if (dev_priv->csr.dmc_payload &&
1614 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
1615 gen9_enable_dc5(dev_priv);
Imre Deak507e1262016-04-20 20:27:54 +03001616 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
Paulo Zanoni1a5df182014-10-27 17:54:32 -02001617 hsw_disable_pc8(dev_priv);
Imre Deak507e1262016-04-20 20:27:54 +03001618 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
Paulo Zanoni1a5df182014-10-27 17:54:32 -02001619 ret = vlv_resume_prepare(dev_priv, true);
Imre Deak507e1262016-04-20 20:27:54 +03001620 }
Paulo Zanoni1a5df182014-10-27 17:54:32 -02001621
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001622 /*
1623 * No point of rolling back things in case of an error, as the best
1624 * we can do is to hope that things will still work (and disable RPM).
1625 */
Imre Deak92b806d2014-04-14 20:24:39 +03001626 i915_gem_init_swizzling(dev);
1627 gen6_update_ring_freq(dev);
1628
Daniel Vetterb9632912014-09-30 10:56:44 +02001629 intel_runtime_pm_enable_interrupts(dev_priv);
Ville Syrjälä08d8a232015-08-27 23:56:08 +03001630
1631 /*
1632 * On VLV/CHV display interrupts are part of the display
1633 * power well, so hpd is reinitialized from there. For
1634 * everyone else do it here.
1635 */
Wayne Boyer666a4532015-12-09 12:29:35 -08001636 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
Ville Syrjälä08d8a232015-08-27 23:56:08 +03001637 intel_hpd_init(dev_priv);
1638
Paulo Zanonifac6adb2014-10-30 15:59:31 -02001639 intel_enable_gt_powersave(dev);
Imre Deakb5478bc2014-04-14 20:24:37 +03001640
Imre Deak1f814da2015-12-16 02:52:19 +02001641 enable_rpm_wakeref_asserts(dev_priv);
1642
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001643 if (ret)
1644 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1645 else
1646 DRM_DEBUG_KMS("Device resumed\n");
1647
1648 return ret;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001649}
1650
Chris Wilsonb4b78d12010-06-06 15:40:20 +01001651static const struct dev_pm_ops i915_pm_ops = {
Imre Deak5545dbb2014-10-23 19:23:28 +03001652 /*
1653 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1654 * PMSG_RESUME]
1655 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001656 .suspend = i915_pm_suspend,
Imre Deak76c4b252014-04-01 19:55:22 +03001657 .suspend_late = i915_pm_suspend_late,
1658 .resume_early = i915_pm_resume_early,
Akshay Joshi0206e352011-08-16 15:34:10 -04001659 .resume = i915_pm_resume,
Imre Deak5545dbb2014-10-23 19:23:28 +03001660
1661 /*
1662 * S4 event handlers
1663 * @freeze, @freeze_late : called (1) before creating the
1664 * hibernation image [PMSG_FREEZE] and
1665 * (2) after rebooting, before restoring
1666 * the image [PMSG_QUIESCE]
1667 * @thaw, @thaw_early : called (1) after creating the hibernation
1668 * image, before writing it [PMSG_THAW]
1669 * and (2) after failing to create or
1670 * restore the image [PMSG_RECOVER]
1671 * @poweroff, @poweroff_late: called after writing the hibernation
1672 * image, before rebooting [PMSG_HIBERNATE]
1673 * @restore, @restore_early : called after rebooting and restoring the
1674 * hibernation image [PMSG_RESTORE]
1675 */
Imre Deak36d61e62014-10-23 19:23:24 +03001676 .freeze = i915_pm_suspend,
1677 .freeze_late = i915_pm_suspend_late,
1678 .thaw_early = i915_pm_resume_early,
1679 .thaw = i915_pm_resume,
1680 .poweroff = i915_pm_suspend,
Imre Deakab3be732015-03-02 13:04:41 +02001681 .poweroff_late = i915_pm_poweroff_late,
Imre Deak76c4b252014-04-01 19:55:22 +03001682 .restore_early = i915_pm_resume_early,
Akshay Joshi0206e352011-08-16 15:34:10 -04001683 .restore = i915_pm_resume,
Imre Deak5545dbb2014-10-23 19:23:28 +03001684
1685 /* S0ix (via runtime suspend) event handlers */
Paulo Zanoni97bea202014-03-07 20:12:33 -03001686 .runtime_suspend = intel_runtime_suspend,
1687 .runtime_resume = intel_runtime_resume,
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001688};
1689
Laurent Pinchart78b68552012-05-17 13:27:22 +02001690static const struct vm_operations_struct i915_gem_vm_ops = {
Jesse Barnesde151cf2008-11-12 10:03:55 -08001691 .fault = i915_gem_fault,
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001692 .open = drm_gem_vm_open,
1693 .close = drm_gem_vm_close,
Jesse Barnesde151cf2008-11-12 10:03:55 -08001694};
1695
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001696static const struct file_operations i915_driver_fops = {
1697 .owner = THIS_MODULE,
1698 .open = drm_open,
1699 .release = drm_release,
1700 .unlocked_ioctl = drm_ioctl,
1701 .mmap = drm_gem_mmap,
1702 .poll = drm_poll,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001703 .read = drm_read,
1704#ifdef CONFIG_COMPAT
1705 .compat_ioctl = i915_compat_ioctl,
1706#endif
1707 .llseek = noop_llseek,
1708};
1709
Linus Torvalds1da177e2005-04-16 15:20:36 -07001710static struct drm_driver driver = {
Michael Witten0c547812011-08-25 17:55:54 +00001711 /* Don't use MTRRs here; the Xserver or userspace app should
1712 * deal with them for Intel hardware.
Dave Airlie792d2b92005-11-11 23:30:27 +11001713 */
Eric Anholt673a3942008-07-30 12:06:12 -07001714 .driver_features =
Kristian Høgsberg10ba5012013-08-25 18:29:01 +02001715 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
Maarten Lankhorst1751fcf2015-08-27 15:15:15 +02001716 DRIVER_RENDER | DRIVER_MODESET,
Dave Airlie22eae942005-11-10 22:16:34 +11001717 .load = i915_driver_load,
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001718 .unload = i915_driver_unload,
Eric Anholt673a3942008-07-30 12:06:12 -07001719 .open = i915_driver_open,
Dave Airlie22eae942005-11-10 22:16:34 +11001720 .lastclose = i915_driver_lastclose,
1721 .preclose = i915_driver_preclose,
Eric Anholt673a3942008-07-30 12:06:12 -07001722 .postclose = i915_driver_postclose,
David Herrmann915b4d12014-08-29 12:12:43 +02001723 .set_busid = drm_pci_set_busid,
Rafael J. Wysockid8e29202010-01-09 00:45:33 +01001724
Ben Gamari955b12d2009-02-17 20:08:49 -05001725#if defined(CONFIG_DEBUG_FS)
Ben Gamari27c202a2009-07-01 22:26:52 -04001726 .debugfs_init = i915_debugfs_init,
1727 .debugfs_cleanup = i915_debugfs_cleanup,
Ben Gamari955b12d2009-02-17 20:08:49 -05001728#endif
Eric Anholt673a3942008-07-30 12:06:12 -07001729 .gem_free_object = i915_gem_free_object,
Jesse Barnesde151cf2008-11-12 10:03:55 -08001730 .gem_vm_ops = &i915_gem_vm_ops,
Daniel Vetter1286ff72012-05-10 15:25:09 +02001731
1732 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1733 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1734 .gem_prime_export = i915_gem_prime_export,
1735 .gem_prime_import = i915_gem_prime_import,
1736
Dave Airlieff72145b2011-02-07 12:16:14 +10001737 .dumb_create = i915_gem_dumb_create,
Dave Airlieda6b51d2014-12-24 13:11:17 +10001738 .dumb_map_offset = i915_gem_mmap_gtt,
Daniel Vetter43387b32013-07-16 09:12:04 +02001739 .dumb_destroy = drm_gem_dumb_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001740 .ioctls = i915_ioctls,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001741 .fops = &i915_driver_fops,
Dave Airlie22eae942005-11-10 22:16:34 +11001742 .name = DRIVER_NAME,
1743 .desc = DRIVER_DESC,
1744 .date = DRIVER_DATE,
1745 .major = DRIVER_MAJOR,
1746 .minor = DRIVER_MINOR,
1747 .patchlevel = DRIVER_PATCHLEVEL,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001748};
1749
Dave Airlie8410ea32010-12-15 03:16:38 +10001750static struct pci_driver i915_pci_driver = {
1751 .name = DRIVER_NAME,
1752 .id_table = pciidlist,
1753 .probe = i915_pci_probe,
1754 .remove = i915_pci_remove,
1755 .driver.pm = &i915_pm_ops,
1756};
1757
Linus Torvalds1da177e2005-04-16 15:20:36 -07001758static int __init i915_init(void)
1759{
1760 driver.num_ioctls = i915_max_ioctl;
Jesse Barnes79e53942008-11-07 14:24:08 -08001761
1762 /*
Chris Wilsonfd930472015-06-19 20:27:27 +01001763 * Enable KMS by default, unless explicitly overriden by
1764 * either the i915.modeset prarameter or by the
1765 * vga_text_mode_force boot option.
Jesse Barnes79e53942008-11-07 14:24:08 -08001766 */
Chris Wilsonfd930472015-06-19 20:27:27 +01001767
1768 if (i915.modeset == 0)
1769 driver.driver_features &= ~DRIVER_MODESET;
Jesse Barnes79e53942008-11-07 14:24:08 -08001770
Jani Nikulad330a952014-01-21 11:24:25 +02001771 if (vgacon_text_force() && i915.modeset == -1)
Jesse Barnes79e53942008-11-07 14:24:08 -08001772 driver.driver_features &= ~DRIVER_MODESET;
Jesse Barnes79e53942008-11-07 14:24:08 -08001773
Daniel Vetterb30324a2013-11-13 22:11:25 +01001774 if (!(driver.driver_features & DRIVER_MODESET)) {
Daniel Vetterb30324a2013-11-13 22:11:25 +01001775 /* Silently fail loading to not upset userspace. */
Jani Nikulac9cd7b62014-06-02 16:58:30 +03001776 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
Daniel Vetterb30324a2013-11-13 22:11:25 +01001777 return 0;
Daniel Vetterb30324a2013-11-13 22:11:25 +01001778 }
Chris Wilson3885c6b2011-01-23 10:45:14 +00001779
Maarten Lankhorstc5b852f2015-08-26 09:29:56 +02001780 if (i915.nuclear_pageflip)
Matt Roperb2e77232015-01-22 16:53:12 -08001781 driver.driver_features |= DRIVER_ATOMIC;
1782
Dave Airlie8410ea32010-12-15 03:16:38 +10001783 return drm_pci_init(&driver, &i915_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001784}
1785
1786static void __exit i915_exit(void)
1787{
Daniel Vetterb33ecdd2013-11-15 17:16:33 +01001788 if (!(driver.driver_features & DRIVER_MODESET))
1789 return; /* Never loaded a driver. */
Daniel Vetterb33ecdd2013-11-15 17:16:33 +01001790
Dave Airlie8410ea32010-12-15 03:16:38 +10001791 drm_pci_exit(&driver, &i915_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001792}
1793
1794module_init(i915_init);
1795module_exit(i915_exit);
1796
Damien Lespiau0a6d1632014-08-27 11:30:20 +01001797MODULE_AUTHOR("Tungsten Graphics, Inc.");
Damien Lespiau1eab9232014-08-27 11:30:21 +01001798MODULE_AUTHOR("Intel Corporation");
Damien Lespiau0a6d1632014-08-27 11:30:20 +01001799
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001800MODULE_DESCRIPTION(DRIVER_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001801MODULE_LICENSE("GPL and additional rights");