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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Jesse Barnes5669fca2009-02-17 15:13:31 -080030#include <linux/device.h>
Jesse Barnese5747e32014-06-12 08:35:47 -070031#include <linux/acpi.h>
David Howells760285e2012-10-02 18:01:07 +010032#include <drm/drmP.h>
33#include <drm/i915_drm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#include "i915_drv.h"
Chris Wilson990bbda2012-07-02 11:51:02 -030035#include "i915_trace.h"
Kenneth Graunkef49f0582010-09-11 01:19:14 -070036#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include <linux/console.h>
Paul Gortmakere0cd3602011-08-30 11:04:30 -040039#include <linux/module.h>
Imre Deakd6102972014-05-07 19:57:49 +030040#include <linux/pm_runtime.h>
David Howells760285e2012-10-02 18:01:07 +010041#include <drm/drm_crtc_helper.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080042
Kristian Høgsberg112b7152009-01-04 16:55:33 -050043static struct drm_driver driver;
44
Antti Koskipaaa57c7742014-02-04 14:22:24 +020045#define GEN_DEFAULT_PIPEOFFSETS \
46 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
47 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
48 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
49 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
Antti Koskipaaa57c7742014-02-04 14:22:24 +020050 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
51
Rafael Barbalho84fd4f42014-04-28 14:00:42 +030052#define GEN_CHV_PIPEOFFSETS \
53 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
54 CHV_PIPE_C_OFFSET }, \
55 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
56 CHV_TRANSCODER_C_OFFSET, }, \
Rafael Barbalho84fd4f42014-04-28 14:00:42 +030057 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
58 CHV_PALETTE_C_OFFSET }
Antti Koskipaaa57c7742014-02-04 14:22:24 +020059
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030060#define CURSOR_OFFSETS \
61 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
62
63#define IVB_CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
65
Tobias Klauser9a7e8492010-05-20 10:33:46 +020066static const struct intel_device_info intel_i830_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070067 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
Chris Wilson315781482010-08-12 09:42:51 +010068 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070069 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020070 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030071 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050072};
73
Tobias Klauser9a7e8492010-05-20 10:33:46 +020074static const struct intel_device_info intel_845g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070075 .gen = 2, .num_pipes = 1,
Chris Wilson315781482010-08-12 09:42:51 +010076 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070077 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020078 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030079 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050080};
81
Tobias Klauser9a7e8492010-05-20 10:33:46 +020082static const struct intel_device_info intel_i85x_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070083 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
Adam Jackson5ce8ba72010-04-15 14:03:30 -040084 .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +010085 .has_overlay = 1, .overlay_needs_physical = 1,
Ville Syrjäläfd70d522013-11-28 17:30:02 +020086 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070087 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020088 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030089 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050090};
91
Tobias Klauser9a7e8492010-05-20 10:33:46 +020092static const struct intel_device_info intel_i865g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070093 .gen = 2, .num_pipes = 1,
Chris Wilson315781482010-08-12 09:42:51 +010094 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070095 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020096 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030097 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050098};
99
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200100static const struct intel_device_info intel_i915g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700101 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
Chris Wilson315781482010-08-12 09:42:51 +0100102 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700103 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200104 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300105 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500106};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200107static const struct intel_device_info intel_i915gm_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700108 .gen = 3, .is_mobile = 1, .num_pipes = 2,
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -0500109 .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100110 .has_overlay = 1, .overlay_needs_physical = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100111 .supports_tv = 1,
Ville Syrjäläfd70d522013-11-28 17:30:02 +0200112 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700113 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200114 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300115 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500116};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200117static const struct intel_device_info intel_i945g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700118 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
Chris Wilson315781482010-08-12 09:42:51 +0100119 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700120 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200121 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300122 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500123};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200124static const struct intel_device_info intel_i945gm_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700125 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -0500126 .has_hotplug = 1, .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100127 .has_overlay = 1, .overlay_needs_physical = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100128 .supports_tv = 1,
Ville Syrjäläfd70d522013-11-28 17:30:02 +0200129 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700130 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200131 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300132 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500133};
134
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200135static const struct intel_device_info intel_i965g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700136 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100137 .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100138 .has_overlay = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700139 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200140 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300141 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500142};
143
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200144static const struct intel_device_info intel_i965gm_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700145 .gen = 4, .is_crestline = 1, .num_pipes = 2,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000146 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100147 .has_overlay = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100148 .supports_tv = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700149 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200150 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300151 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500152};
153
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200154static const struct intel_device_info intel_g33_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700155 .gen = 3, .is_g33 = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100156 .need_gfx_hws = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100157 .has_overlay = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700158 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200159 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300160 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500161};
162
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200163static const struct intel_device_info intel_g45_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700164 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100165 .has_pipe_cxsr = 1, .has_hotplug = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700166 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200167 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300168 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500169};
170
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200171static const struct intel_device_info intel_gm45_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700172 .gen = 4, .is_g4x = 1, .num_pipes = 2,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000173 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100174 .has_pipe_cxsr = 1, .has_hotplug = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100175 .supports_tv = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700176 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200177 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300178 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500179};
180
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200181static const struct intel_device_info intel_pineview_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700182 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100183 .need_gfx_hws = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100184 .has_overlay = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200185 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300186 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500187};
188
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200189static const struct intel_device_info intel_ironlake_d_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700190 .gen = 5, .num_pipes = 2,
Eugeni Dodonov5a117db2012-01-05 09:34:29 -0200191 .need_gfx_hws = 1, .has_hotplug = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700192 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200193 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300194 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500195};
196
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200197static const struct intel_device_info intel_ironlake_m_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700198 .gen = 5, .is_mobile = 1, .num_pipes = 2,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000199 .need_gfx_hws = 1, .has_hotplug = 1,
Jesse Barnesc1a9f042011-05-05 15:24:21 -0700200 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700201 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200202 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300203 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500204};
205
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200206static const struct intel_device_info intel_sandybridge_d_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700207 .gen = 6, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100208 .need_gfx_hws = 1, .has_hotplug = 1,
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200209 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700210 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200211 .has_llc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200212 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300213 CURSOR_OFFSETS,
Eric Anholtf6e450a2009-11-02 12:08:22 -0800214};
215
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200216static const struct intel_device_info intel_sandybridge_m_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700217 .gen = 6, .is_mobile = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100218 .need_gfx_hws = 1, .has_hotplug = 1,
Yuanhan Liu9c04f012010-12-15 15:42:32 +0800219 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700220 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200221 .has_llc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200222 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300223 CURSOR_OFFSETS,
Eric Anholta13e4092010-01-07 15:08:18 -0800224};
225
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700226#define GEN7_FEATURES \
227 .gen = 7, .num_pipes = 3, \
228 .need_gfx_hws = 1, .has_hotplug = 1, \
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200229 .has_fbc = 1, \
Ben Widawsky73ae4782013-10-15 10:02:57 -0700230 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
Ben Widawskyab484f82013-10-05 17:57:11 -0700231 .has_llc = 1
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700232
Jesse Barnesc76b6152011-04-28 14:32:07 -0700233static const struct intel_device_info intel_ivybridge_d_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700234 GEN7_FEATURES,
235 .is_ivybridge = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200236 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300237 IVB_CURSOR_OFFSETS,
Jesse Barnesc76b6152011-04-28 14:32:07 -0700238};
239
240static const struct intel_device_info intel_ivybridge_m_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700241 GEN7_FEATURES,
242 .is_ivybridge = 1,
243 .is_mobile = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200244 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300245 IVB_CURSOR_OFFSETS,
Jesse Barnesc76b6152011-04-28 14:32:07 -0700246};
247
Ben Widawsky999bcde2013-04-05 13:12:45 -0700248static const struct intel_device_info intel_ivybridge_q_info = {
249 GEN7_FEATURES,
250 .is_ivybridge = 1,
251 .num_pipes = 0, /* legal, last one wins */
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200252 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300253 IVB_CURSOR_OFFSETS,
Ben Widawsky999bcde2013-04-05 13:12:45 -0700254};
255
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700256static const struct intel_device_info intel_valleyview_m_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700257 GEN7_FEATURES,
258 .is_mobile = 1,
259 .num_pipes = 2,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700260 .is_valleyview = 1,
Ville Syrjäläfba5d532013-01-24 15:29:56 +0200261 .display_mmio_offset = VLV_DISPLAY_BASE,
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200262 .has_fbc = 0, /* legal, last one wins */
Ben Widawsky30ccd962013-04-15 21:48:03 -0700263 .has_llc = 0, /* legal, last one wins */
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200264 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300265 CURSOR_OFFSETS,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700266};
267
268static const struct intel_device_info intel_valleyview_d_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700269 GEN7_FEATURES,
270 .num_pipes = 2,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700271 .is_valleyview = 1,
Ville Syrjäläfba5d532013-01-24 15:29:56 +0200272 .display_mmio_offset = VLV_DISPLAY_BASE,
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200273 .has_fbc = 0, /* legal, last one wins */
Ben Widawsky30ccd962013-04-15 21:48:03 -0700274 .has_llc = 0, /* legal, last one wins */
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200275 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300276 CURSOR_OFFSETS,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700277};
278
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -0300279static const struct intel_device_info intel_haswell_d_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700280 GEN7_FEATURES,
281 .is_haswell = 1,
Damien Lespiaudd93be52013-04-22 18:40:39 +0100282 .has_ddi = 1,
Damien Lespiau30568c42013-04-22 18:40:41 +0100283 .has_fpga_dbg = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700284 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200285 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300286 IVB_CURSOR_OFFSETS,
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -0300287};
288
289static const struct intel_device_info intel_haswell_m_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700290 GEN7_FEATURES,
291 .is_haswell = 1,
292 .is_mobile = 1,
Damien Lespiaudd93be52013-04-22 18:40:39 +0100293 .has_ddi = 1,
Damien Lespiau30568c42013-04-22 18:40:41 +0100294 .has_fpga_dbg = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700295 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200296 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300297 IVB_CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500298};
299
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800300static const struct intel_device_info intel_broadwell_d_info = {
Damien Lespiau4b305532013-11-02 21:07:32 -0700301 .gen = 8, .num_pipes = 3,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800302 .need_gfx_hws = 1, .has_hotplug = 1,
303 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
304 .has_llc = 1,
305 .has_ddi = 1,
Paulo Zanoni66bc2ca2014-07-16 17:49:30 -0300306 .has_fpga_dbg = 1,
Ben Widawsky8f94d242014-02-20 16:01:20 -0800307 .has_fbc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200308 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300309 IVB_CURSOR_OFFSETS,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800310};
311
312static const struct intel_device_info intel_broadwell_m_info = {
Damien Lespiau4b305532013-11-02 21:07:32 -0700313 .gen = 8, .is_mobile = 1, .num_pipes = 3,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800314 .need_gfx_hws = 1, .has_hotplug = 1,
315 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
316 .has_llc = 1,
317 .has_ddi = 1,
Paulo Zanoni66bc2ca2014-07-16 17:49:30 -0300318 .has_fpga_dbg = 1,
Ben Widawsky8f94d242014-02-20 16:01:20 -0800319 .has_fbc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200320 GEN_DEFAULT_PIPEOFFSETS,
Rodrigo Vivi15d24aa2014-06-04 17:09:30 -0700321 IVB_CURSOR_OFFSETS,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800322};
323
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800324static const struct intel_device_info intel_broadwell_gt3d_info = {
325 .gen = 8, .num_pipes = 3,
326 .need_gfx_hws = 1, .has_hotplug = 1,
Zhao Yakui845f74a2014-04-17 10:37:37 +0800327 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800328 .has_llc = 1,
329 .has_ddi = 1,
Paulo Zanoni66bc2ca2014-07-16 17:49:30 -0300330 .has_fpga_dbg = 1,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800331 .has_fbc = 1,
332 GEN_DEFAULT_PIPEOFFSETS,
Rodrigo Vivi15d24aa2014-06-04 17:09:30 -0700333 IVB_CURSOR_OFFSETS,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800334};
335
336static const struct intel_device_info intel_broadwell_gt3m_info = {
337 .gen = 8, .is_mobile = 1, .num_pipes = 3,
338 .need_gfx_hws = 1, .has_hotplug = 1,
Zhao Yakui845f74a2014-04-17 10:37:37 +0800339 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800340 .has_llc = 1,
341 .has_ddi = 1,
Paulo Zanoni66bc2ca2014-07-16 17:49:30 -0300342 .has_fpga_dbg = 1,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800343 .has_fbc = 1,
344 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300345 IVB_CURSOR_OFFSETS,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800346};
347
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300348static const struct intel_device_info intel_cherryview_info = {
Ville Syrjälä07fddb12014-04-09 13:28:54 +0300349 .gen = 8, .num_pipes = 3,
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300350 .need_gfx_hws = 1, .has_hotplug = 1,
351 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
352 .is_valleyview = 1,
353 .display_mmio_offset = VLV_DISPLAY_BASE,
Rafael Barbalho84fd4f42014-04-28 14:00:42 +0300354 GEN_CHV_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300355 CURSOR_OFFSETS,
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300356};
357
Damien Lespiau72bbf0a2013-02-13 15:27:37 +0000358static const struct intel_device_info intel_skylake_info = {
359 .is_preliminary = 1,
Satheeshakrishna M7201c0b2014-04-02 11:24:50 +0530360 .is_skylake = 1,
Damien Lespiau72bbf0a2013-02-13 15:27:37 +0000361 .gen = 9, .num_pipes = 3,
362 .need_gfx_hws = 1, .has_hotplug = 1,
363 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
364 .has_llc = 1,
365 .has_ddi = 1,
Daisy Sun043efb12014-04-23 17:13:09 -0700366 .has_fbc = 1,
Damien Lespiau72bbf0a2013-02-13 15:27:37 +0000367 GEN_DEFAULT_PIPEOFFSETS,
368 IVB_CURSOR_OFFSETS,
369};
370
Damien Lespiau719388e2015-02-04 13:22:27 +0000371static const struct intel_device_info intel_skylake_gt3_info = {
372 .is_preliminary = 1,
373 .is_skylake = 1,
374 .gen = 9, .num_pipes = 3,
375 .need_gfx_hws = 1, .has_hotplug = 1,
376 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
377 .has_llc = 1,
378 .has_ddi = 1,
379 .has_fbc = 1,
380 GEN_DEFAULT_PIPEOFFSETS,
381 IVB_CURSOR_OFFSETS,
382};
383
Damien Lespiau1347f5b2015-03-17 11:39:27 +0200384static const struct intel_device_info intel_broxton_info = {
385 .is_preliminary = 1,
386 .gen = 9,
387 .need_gfx_hws = 1, .has_hotplug = 1,
388 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
389 .num_pipes = 3,
390 .has_ddi = 1,
Daisy Sunce89db22015-03-17 11:39:28 +0200391 .has_fbc = 1,
Damien Lespiau1347f5b2015-03-17 11:39:27 +0200392 GEN_DEFAULT_PIPEOFFSETS,
393 IVB_CURSOR_OFFSETS,
394};
395
Jesse Barnesa0a18072013-07-26 13:32:51 -0700396/*
397 * Make sure any device matches here are from most specific to most
398 * general. For example, since the Quanta match is based on the subsystem
399 * and subvendor IDs, we need it to come before the more general IVB
400 * PCI ID matches, otherwise we'll use the wrong info struct above.
401 */
402#define INTEL_PCI_IDS \
403 INTEL_I830_IDS(&intel_i830_info), \
404 INTEL_I845G_IDS(&intel_845g_info), \
405 INTEL_I85X_IDS(&intel_i85x_info), \
406 INTEL_I865G_IDS(&intel_i865g_info), \
407 INTEL_I915G_IDS(&intel_i915g_info), \
408 INTEL_I915GM_IDS(&intel_i915gm_info), \
409 INTEL_I945G_IDS(&intel_i945g_info), \
410 INTEL_I945GM_IDS(&intel_i945gm_info), \
411 INTEL_I965G_IDS(&intel_i965g_info), \
412 INTEL_G33_IDS(&intel_g33_info), \
413 INTEL_I965GM_IDS(&intel_i965gm_info), \
414 INTEL_GM45_IDS(&intel_gm45_info), \
415 INTEL_G45_IDS(&intel_g45_info), \
416 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
417 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
418 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
419 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
420 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
421 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
422 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
423 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
424 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
425 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
426 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800427 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800428 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
429 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
430 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300431 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
Damien Lespiau72bbf0a2013-02-13 15:27:37 +0000432 INTEL_CHV_IDS(&intel_cherryview_info), \
Damien Lespiau719388e2015-02-04 13:22:27 +0000433 INTEL_SKL_GT1_IDS(&intel_skylake_info), \
434 INTEL_SKL_GT2_IDS(&intel_skylake_info), \
Damien Lespiau1347f5b2015-03-17 11:39:27 +0200435 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), \
436 INTEL_BXT_IDS(&intel_broxton_info)
Jesse Barnesa0a18072013-07-26 13:32:51 -0700437
Chris Wilson6103da02010-07-05 18:01:47 +0100438static const struct pci_device_id pciidlist[] = { /* aka */
Jesse Barnesa0a18072013-07-26 13:32:51 -0700439 INTEL_PCI_IDS,
Kristian Høgsberg49ae35f2009-12-16 15:16:15 -0500440 {0, 0, 0}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441};
442
Jesse Barnes79e53942008-11-07 14:24:08 -0800443#if defined(CONFIG_DRM_I915_KMS)
444MODULE_DEVICE_TABLE(pci, pciidlist);
445#endif
446
Akshay Joshi0206e352011-08-16 15:34:10 -0400447void intel_detect_pch(struct drm_device *dev)
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800448{
449 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deakbcdb72a2014-02-14 20:23:54 +0200450 struct pci_dev *pch = NULL;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800451
Ben Widawskyce1bb322013-04-05 13:12:44 -0700452 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
453 * (which really amounts to a PCH but no South Display).
454 */
455 if (INTEL_INFO(dev)->num_pipes == 0) {
456 dev_priv->pch_type = PCH_NOP;
Ben Widawskyce1bb322013-04-05 13:12:44 -0700457 return;
458 }
459
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800460 /*
461 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
462 * make graphics device passthrough work easy for VMM, that only
463 * need to expose ISA bridge to let driver know the real hardware
464 * underneath. This is a requirement from virtualization team.
Rui Guo6a9c4b32013-06-19 21:10:23 +0800465 *
466 * In some virtualized environments (e.g. XEN), there is irrelevant
467 * ISA bridge in the system. To work reliably, we should scan trhough
468 * all the ISA bridge devices and check for the first match, instead
469 * of only checking the first one.
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800470 */
Imre Deakbcdb72a2014-02-14 20:23:54 +0200471 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800472 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
Imre Deakbcdb72a2014-02-14 20:23:54 +0200473 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
Paulo Zanoni17a303e2012-11-20 15:12:07 -0200474 dev_priv->pch_id = id;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800475
Jesse Barnes90711d52011-04-28 14:48:02 -0700476 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
477 dev_priv->pch_type = PCH_IBX;
478 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100479 WARN_ON(!IS_GEN5(dev));
Jesse Barnes90711d52011-04-28 14:48:02 -0700480 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800481 dev_priv->pch_type = PCH_CPT;
482 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100483 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
Jesse Barnesc7925132011-04-07 12:33:56 -0700484 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
485 /* PantherPoint is CPT compatible */
486 dev_priv->pch_type = PCH_CPT;
Jani Nikula492ab662013-10-01 12:12:33 +0300487 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100488 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300489 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
490 dev_priv->pch_type = PCH_LPT;
491 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
Rodrigo Vivia35cc9d02015-01-21 10:33:53 -0800492 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
493 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
Ben Widawskye76e0632013-11-07 21:40:41 -0800494 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
495 dev_priv->pch_type = PCH_LPT;
496 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
Rodrigo Vivia35cc9d02015-01-21 10:33:53 -0800497 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
498 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +0530499 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
500 dev_priv->pch_type = PCH_SPT;
501 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
502 WARN_ON(!IS_SKYLAKE(dev));
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +0530503 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
504 dev_priv->pch_type = PCH_SPT;
505 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
506 WARN_ON(!IS_SKYLAKE(dev));
Imre Deakbcdb72a2014-02-14 20:23:54 +0200507 } else
508 continue;
509
Rui Guo6a9c4b32013-06-19 21:10:23 +0800510 break;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800511 }
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800512 }
Rui Guo6a9c4b32013-06-19 21:10:23 +0800513 if (!pch)
Imre Deakbcdb72a2014-02-14 20:23:54 +0200514 DRM_DEBUG_KMS("No PCH found.\n");
515
516 pci_dev_put(pch);
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800517}
518
Ben Widawsky2911a352012-04-05 14:47:36 -0700519bool i915_semaphore_is_enabled(struct drm_device *dev)
520{
521 if (INTEL_INFO(dev)->gen < 6)
Daniel Vettera08acaf2013-12-17 09:56:53 +0100522 return false;
Ben Widawsky2911a352012-04-05 14:47:36 -0700523
Jani Nikulad330a952014-01-21 11:24:25 +0200524 if (i915.semaphores >= 0)
525 return i915.semaphores;
Ben Widawsky2911a352012-04-05 14:47:36 -0700526
Oscar Mateo71386ef2014-07-24 17:04:44 +0100527 /* TODO: make semaphores and Execlists play nicely together */
528 if (i915.enable_execlists)
529 return false;
530
Rodrigo Vivibe71eab2014-08-04 11:15:19 -0700531 /* Until we get further testing... */
532 if (IS_GEN8(dev))
533 return false;
534
Daniel Vetter59de3292012-04-02 20:48:43 +0200535#ifdef CONFIG_INTEL_IOMMU
Ben Widawsky2911a352012-04-05 14:47:36 -0700536 /* Enable semaphores on SNB when IO remapping is off */
Daniel Vetter59de3292012-04-02 20:48:43 +0200537 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
538 return false;
539#endif
Ben Widawsky2911a352012-04-05 14:47:36 -0700540
Daniel Vettera08acaf2013-12-17 09:56:53 +0100541 return true;
Ben Widawsky2911a352012-04-05 14:47:36 -0700542}
543
Imre Deak1d0d3432014-08-18 14:42:44 +0300544void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
545{
546 spin_lock_irq(&dev_priv->irq_lock);
547
548 dev_priv->long_hpd_port_mask = 0;
549 dev_priv->short_hpd_port_mask = 0;
550 dev_priv->hpd_event_bits = 0;
551
552 spin_unlock_irq(&dev_priv->irq_lock);
553
554 cancel_work_sync(&dev_priv->dig_port_work);
555 cancel_work_sync(&dev_priv->hotplug_work);
556 cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work);
557}
558
Daniel Vettereb805622015-05-04 14:58:44 +0200559void i915_firmware_load_error_print(const char *fw_path, int err)
560{
561 DRM_ERROR("failed to load firmware %s (%d)\n", fw_path, err);
562
563 /*
564 * If the reason is not known assume -ENOENT since that's the most
565 * usual failure mode.
566 */
567 if (!err)
568 err = -ENOENT;
569
570 if (!(IS_BUILTIN(CONFIG_DRM_I915) && err == -ENOENT))
571 return;
572
573 DRM_ERROR(
574 "The driver is built-in, so to load the firmware you need to\n"
575 "include it either in the kernel (see CONFIG_EXTRA_FIRMWARE) or\n"
576 "in your initrd/initramfs image.\n");
577}
578
Imre Deak07f9cd02014-08-18 14:42:45 +0300579static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
580{
581 struct drm_device *dev = dev_priv->dev;
582 struct drm_encoder *encoder;
583
584 drm_modeset_lock_all(dev);
585 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
586 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
587
588 if (intel_encoder->suspend)
589 intel_encoder->suspend(intel_encoder);
590 }
591 drm_modeset_unlock_all(dev);
592}
593
Sagar Kambleebc32822014-08-13 23:07:05 +0530594static int intel_suspend_complete(struct drm_i915_private *dev_priv);
Paulo Zanoni1a5df182014-10-27 17:54:32 -0200595static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
596 bool rpm_resume);
Suketu Shahf75a1982015-04-16 14:22:11 +0530597static int skl_resume_prepare(struct drm_i915_private *dev_priv);
598
Sagar Kambleebc32822014-08-13 23:07:05 +0530599
Imre Deak5e365c32014-10-23 19:23:25 +0300600static int i915_drm_suspend(struct drm_device *dev)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100601{
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100602 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes24576d22013-03-26 09:25:45 -0700603 struct drm_crtc *crtc;
Jesse Barnese5747e32014-06-12 08:35:47 -0700604 pci_power_t opregion_target_state;
Daniel Vetterd5818932015-02-23 12:03:26 +0100605 int error;
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100606
Zhang Ruib8efb172013-02-05 15:41:53 +0800607 /* ignore lid events during suspend */
608 mutex_lock(&dev_priv->modeset_restore_lock);
609 dev_priv->modeset_restore = MODESET_SUSPENDED;
610 mutex_unlock(&dev_priv->modeset_restore_lock);
611
Paulo Zanonic67a4702013-08-19 13:18:09 -0300612 /* We do a lot of poking in a lot of registers, make sure they work
613 * properly. */
Imre Deakda7e29b2014-02-18 00:02:02 +0200614 intel_display_set_init_power(dev_priv, true);
Paulo Zanonicb107992013-01-25 16:59:15 -0200615
Dave Airlie5bcf7192010-12-07 09:20:40 +1000616 drm_kms_helper_poll_disable(dev);
617
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100618 pci_save_state(dev->pdev);
619
Daniel Vetterd5818932015-02-23 12:03:26 +0100620 error = i915_gem_suspend(dev);
621 if (error) {
622 dev_err(&dev->pdev->dev,
623 "GEM idle failed, resume might fail\n");
624 return error;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100625 }
626
Daniel Vetterd5818932015-02-23 12:03:26 +0100627 intel_suspend_gt_powersave(dev);
628
629 /*
630 * Disable CRTCs directly since we want to preserve sw state
631 * for _thaw. Also, power gate the CRTC power wells.
632 */
633 drm_modeset_lock_all(dev);
634 for_each_crtc(dev, crtc)
635 intel_crtc_control(crtc, false);
636 drm_modeset_unlock_all(dev);
637
638 intel_dp_mst_suspend(dev);
639
640 intel_runtime_pm_disable_interrupts(dev_priv);
641 intel_hpd_cancel_work(dev_priv);
642
643 intel_suspend_encoders(dev_priv);
644
645 intel_suspend_hw(dev);
646
Ben Widawsky828c7902013-10-16 09:21:30 -0700647 i915_gem_suspend_gtt_mappings(dev);
648
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100649 i915_save_state(dev);
650
Imre Deak95fa2ee2014-06-23 15:46:02 +0300651 opregion_target_state = PCI_D3cold;
652#if IS_ENABLED(CONFIG_ACPI_SLEEP)
653 if (acpi_target_system_state() < ACPI_STATE_S3)
Jesse Barnese5747e32014-06-12 08:35:47 -0700654 opregion_target_state = PCI_D1;
Imre Deak95fa2ee2014-06-23 15:46:02 +0300655#endif
Jesse Barnese5747e32014-06-12 08:35:47 -0700656 intel_opregion_notify_adapter(dev, opregion_target_state);
657
Jesse Barnes156c7ca2014-06-12 08:35:45 -0700658 intel_uncore_forcewake_reset(dev, false);
Chris Wilson44834a62010-08-19 16:09:23 +0100659 intel_opregion_fini(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100660
Chris Wilson82e3b8c2014-08-13 13:09:46 +0100661 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
Dave Airlie3fa016a2012-03-28 10:48:49 +0100662
Mika Kuoppala62d5d692014-02-25 17:11:28 +0200663 dev_priv->suspend_count++;
664
Kristen Carlson Accardi85e90672014-06-12 08:35:44 -0700665 intel_display_set_init_power(dev_priv, false);
666
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100667 return 0;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100668}
669
Imre Deakab3be732015-03-02 13:04:41 +0200670static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
Imre Deakc3c09c92014-10-23 19:23:15 +0300671{
672 struct drm_i915_private *dev_priv = drm_dev->dev_private;
673 int ret;
674
675 ret = intel_suspend_complete(dev_priv);
676
677 if (ret) {
678 DRM_ERROR("Suspend complete failed: %d\n", ret);
679
680 return ret;
681 }
682
683 pci_disable_device(drm_dev->pdev);
Imre Deakab3be732015-03-02 13:04:41 +0200684 /*
685 * During hibernation on some GEN4 platforms the BIOS may try to access
686 * the device even though it's already in D3 and hang the machine. So
687 * leave the device in D0 on those platforms and hope the BIOS will
688 * power down the device properly. Platforms where this was seen:
689 * Lenovo Thinkpad X301, X61s
690 */
691 if (!(hibernation &&
692 drm_dev->pdev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
693 INTEL_INFO(dev_priv)->gen == 4))
694 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
Imre Deakc3c09c92014-10-23 19:23:15 +0300695
696 return 0;
697}
698
Imre Deakfc49b3d2014-10-23 19:23:27 +0300699int i915_suspend_legacy(struct drm_device *dev, pm_message_t state)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100700{
701 int error;
702
703 if (!dev || !dev->dev_private) {
704 DRM_ERROR("dev: %p\n", dev);
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700705 DRM_ERROR("DRM not initialized, aborting suspend.\n");
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000706 return -ENODEV;
707 }
708
Imre Deak0b14cbd2014-09-10 18:16:55 +0300709 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
710 state.event != PM_EVENT_FREEZE))
711 return -EINVAL;
Dave Airlie5bcf7192010-12-07 09:20:40 +1000712
713 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
714 return 0;
Chris Wilson6eecba32010-09-08 09:45:11 +0100715
Imre Deak5e365c32014-10-23 19:23:25 +0300716 error = i915_drm_suspend(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100717 if (error)
718 return error;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000719
Imre Deakab3be732015-03-02 13:04:41 +0200720 return i915_drm_suspend_late(dev, false);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000721}
722
Imre Deak5e365c32014-10-23 19:23:25 +0300723static int i915_drm_resume(struct drm_device *dev)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000724{
Jesse Barnes5669fca2009-02-17 15:13:31 -0800725 struct drm_i915_private *dev_priv = dev->dev_private;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100726
Daniel Vetterd5818932015-02-23 12:03:26 +0100727 mutex_lock(&dev->struct_mutex);
728 i915_gem_restore_gtt_mappings(dev);
729 mutex_unlock(&dev->struct_mutex);
Paulo Zanoni9d49c0e2013-09-12 18:06:43 -0300730
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100731 i915_restore_state(dev);
Chris Wilson44834a62010-08-19 16:09:23 +0100732 intel_opregion_setup(dev);
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100733
Daniel Vetterd5818932015-02-23 12:03:26 +0100734 intel_init_pch_refclk(dev);
735 drm_mode_config_reset(dev);
Chris Wilson1833b132012-05-09 11:56:28 +0100736
Daniel Vetterd5818932015-02-23 12:03:26 +0100737 mutex_lock(&dev->struct_mutex);
738 if (i915_gem_init_hw(dev)) {
739 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
740 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
Jesse Barnesd5bb0812011-01-05 12:01:26 -0800741 }
Daniel Vetterd5818932015-02-23 12:03:26 +0100742 mutex_unlock(&dev->struct_mutex);
743
744 /* We need working interrupts for modeset enabling ... */
745 intel_runtime_pm_enable_interrupts(dev_priv);
746
747 intel_modeset_init_hw(dev);
748
749 spin_lock_irq(&dev_priv->irq_lock);
750 if (dev_priv->display.hpd_irq_setup)
751 dev_priv->display.hpd_irq_setup(dev);
752 spin_unlock_irq(&dev_priv->irq_lock);
753
754 drm_modeset_lock_all(dev);
755 intel_modeset_setup_hw_state(dev, true);
756 drm_modeset_unlock_all(dev);
757
758 intel_dp_mst_resume(dev);
759
760 /*
761 * ... but also need to make sure that hotplug processing
762 * doesn't cause havoc. Like in the driver load code we don't
763 * bother with the tiny race here where we might loose hotplug
764 * notifications.
765 * */
766 intel_hpd_init(dev_priv);
767 /* Config may have changed between suspend and resume */
768 drm_helper_hpd_irq_event(dev);
Jesse Barnes1daed3f2011-01-05 12:01:25 -0800769
Chris Wilson44834a62010-08-19 16:09:23 +0100770 intel_opregion_init(dev);
771
Chris Wilson82e3b8c2014-08-13 13:09:46 +0100772 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
Jesse Barnes073f34d2012-11-02 11:13:59 -0700773
Zhang Ruib8efb172013-02-05 15:41:53 +0800774 mutex_lock(&dev_priv->modeset_restore_lock);
775 dev_priv->modeset_restore = MODESET_DONE;
776 mutex_unlock(&dev_priv->modeset_restore_lock);
Paulo Zanoni8a187452013-12-06 20:32:13 -0200777
Jesse Barnese5747e32014-06-12 08:35:47 -0700778 intel_opregion_notify_adapter(dev, PCI_D0);
779
Imre Deakee6f2802014-10-23 19:23:22 +0300780 drm_kms_helper_poll_enable(dev);
781
Chris Wilson074c6ad2014-04-09 09:19:43 +0100782 return 0;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100783}
784
Imre Deak5e365c32014-10-23 19:23:25 +0300785static int i915_drm_resume_early(struct drm_device *dev)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100786{
Imre Deak36d61e62014-10-23 19:23:24 +0300787 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni1a5df182014-10-27 17:54:32 -0200788 int ret = 0;
Imre Deak36d61e62014-10-23 19:23:24 +0300789
Imre Deak76c4b252014-04-01 19:55:22 +0300790 /*
791 * We have a resume ordering issue with the snd-hda driver also
792 * requiring our device to be power up. Due to the lack of a
793 * parent/child relationship we currently solve this with an early
794 * resume hook.
795 *
796 * FIXME: This should be solved with a special hdmi sink device or
797 * similar so that power domains can be employed.
798 */
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100799 if (pci_enable_device(dev->pdev))
800 return -EIO;
801
802 pci_set_master(dev->pdev);
803
Paulo Zanoniefee8332014-10-27 17:54:33 -0200804 if (IS_VALLEYVIEW(dev_priv))
Paulo Zanoni1a5df182014-10-27 17:54:32 -0200805 ret = vlv_resume_prepare(dev_priv, false);
Imre Deak36d61e62014-10-23 19:23:24 +0300806 if (ret)
807 DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
808
809 intel_uncore_early_sanitize(dev, true);
Paulo Zanoniefee8332014-10-27 17:54:33 -0200810
811 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
812 hsw_disable_pc8(dev_priv);
Suketu Shahf75a1982015-04-16 14:22:11 +0530813 else if (IS_SKYLAKE(dev_priv))
814 ret = skl_resume_prepare(dev_priv);
Paulo Zanoniefee8332014-10-27 17:54:33 -0200815
Imre Deak36d61e62014-10-23 19:23:24 +0300816 intel_uncore_sanitize(dev);
817 intel_power_domains_init_hw(dev_priv);
818
819 return ret;
Imre Deak76c4b252014-04-01 19:55:22 +0300820}
821
Imre Deakfc49b3d2014-10-23 19:23:27 +0300822int i915_resume_legacy(struct drm_device *dev)
Imre Deak76c4b252014-04-01 19:55:22 +0300823{
Imre Deak50a00722014-10-23 19:23:17 +0300824 int ret;
Imre Deak76c4b252014-04-01 19:55:22 +0300825
Imre Deak097dd832014-10-23 19:23:19 +0300826 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
827 return 0;
828
Imre Deak5e365c32014-10-23 19:23:25 +0300829 ret = i915_drm_resume_early(dev);
Imre Deak50a00722014-10-23 19:23:17 +0300830 if (ret)
831 return ret;
832
Imre Deak5a175142014-10-23 19:23:18 +0300833 return i915_drm_resume(dev);
834}
835
Ben Gamari11ed50e2009-09-14 17:48:45 -0400836/**
Eugeni Dodonovf3953dc2011-11-28 16:15:17 -0200837 * i915_reset - reset chip after a hang
Ben Gamari11ed50e2009-09-14 17:48:45 -0400838 * @dev: drm device to reset
Ben Gamari11ed50e2009-09-14 17:48:45 -0400839 *
840 * Reset the chip. Useful if a hang is detected. Returns zero on successful
841 * reset or otherwise an error code.
842 *
843 * Procedure is fairly simple:
844 * - reset the chip using the reset reg
845 * - re-init context state
846 * - re-init hardware status page
847 * - re-init ring buffer
848 * - re-init interrupt state
849 * - re-init display
850 */
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200851int i915_reset(struct drm_device *dev)
Ben Gamari11ed50e2009-09-14 17:48:45 -0400852{
Jani Nikula50227e12014-03-31 14:27:21 +0300853 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson2e7c8ee2013-05-28 10:38:44 +0100854 bool simulated;
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700855 int ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400856
Jani Nikulad330a952014-01-21 11:24:25 +0200857 if (!i915.reset)
Chris Wilsond78cb502010-12-23 13:33:15 +0000858 return 0;
859
Imre Deakdbea3ce2014-12-15 18:59:28 +0200860 intel_reset_gt_powersave(dev);
861
Daniel Vetterd54a02c2012-07-04 22:18:39 +0200862 mutex_lock(&dev->struct_mutex);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400863
Chris Wilson069efc12010-09-30 16:53:18 +0100864 i915_gem_reset(dev);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400865
Chris Wilson2e7c8ee2013-05-28 10:38:44 +0100866 simulated = dev_priv->gpu_error.stop_rings != 0;
867
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300868 ret = intel_gpu_reset(dev);
Daniel Vetter350d2702012-04-27 15:17:42 +0200869
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300870 /* Also reset the gpu hangman. */
871 if (simulated) {
872 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
873 dev_priv->gpu_error.stop_rings = 0;
874 if (ret == -ENODEV) {
Daniel Vetterf2d91a22013-11-07 09:48:57 +0100875 DRM_INFO("Reset not implemented, but ignoring "
876 "error for simulated gpu hangs\n");
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300877 ret = 0;
878 }
Chris Wilson2e7c8ee2013-05-28 10:38:44 +0100879 }
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300880
Daniel Vetterd8f27162014-10-01 01:02:04 +0200881 if (i915_stop_ring_allow_warn(dev_priv))
882 pr_notice("drm/i915: Resetting chip after gpu hang\n");
883
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700884 if (ret) {
Daniel Vetterf2d91a22013-11-07 09:48:57 +0100885 DRM_ERROR("Failed to reset chip: %i\n", ret);
Daniel J Bluemanf953c932010-05-17 14:23:52 +0100886 mutex_unlock(&dev->struct_mutex);
Chris Wilsonf803aa52010-09-19 12:38:26 +0100887 return ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400888 }
889
Ville Syrjälä1362b772014-11-26 17:07:29 +0200890 intel_overlay_reset(dev_priv);
891
Ben Gamari11ed50e2009-09-14 17:48:45 -0400892 /* Ok, now get things going again... */
893
894 /*
895 * Everything depends on having the GTT running, so we need to start
896 * there. Fortunately we don't need to do this unless we reset the
897 * chip at a PCI level.
898 *
899 * Next we need to restore the context, but we don't use those
900 * yet either...
901 *
902 * Ring buffer needs to be re-initialized in the KMS case, or if X
903 * was running at the time of the reset (i.e. we weren't VT
904 * switched away).
905 */
McAulay, Alistair6689c162014-08-15 18:51:35 +0100906
Daniel Vetter33d30a92015-02-23 12:03:27 +0100907 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
908 dev_priv->gpu_error.reload_in_reset = true;
McAulay, Alistair6689c162014-08-15 18:51:35 +0100909
Daniel Vetter33d30a92015-02-23 12:03:27 +0100910 ret = i915_gem_init_hw(dev);
McAulay, Alistair6689c162014-08-15 18:51:35 +0100911
Daniel Vetter33d30a92015-02-23 12:03:27 +0100912 dev_priv->gpu_error.reload_in_reset = false;
Daniel Vetterf8175862012-04-10 15:50:11 +0200913
Daniel Vetter33d30a92015-02-23 12:03:27 +0100914 mutex_unlock(&dev->struct_mutex);
915 if (ret) {
916 DRM_ERROR("Failed hw init on reset %d\n", ret);
917 return ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400918 }
919
Daniel Vetter33d30a92015-02-23 12:03:27 +0100920 /*
Daniel Vetter33d30a92015-02-23 12:03:27 +0100921 * rps/rc6 re-init is necessary to restore state lost after the
922 * reset and the re-install of gt irqs. Skip for ironlake per
923 * previous concerns that it doesn't respond well to some forms
924 * of re-init after reset.
925 */
926 if (INTEL_INFO(dev)->gen > 5)
927 intel_enable_gt_powersave(dev);
928
Ben Gamari11ed50e2009-09-14 17:48:45 -0400929 return 0;
930}
931
Greg Kroah-Hartman56550d92012-12-21 15:09:25 -0800932static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500933{
Daniel Vetter01a06852012-06-25 15:58:49 +0200934 struct intel_device_info *intel_info =
935 (struct intel_device_info *) ent->driver_data;
936
Jani Nikulad330a952014-01-21 11:24:25 +0200937 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
Ben Widawskyb833d682013-08-23 16:00:07 -0700938 DRM_INFO("This hardware requires preliminary hardware support.\n"
939 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
940 return -ENODEV;
941 }
942
Chris Wilson5fe49d82011-02-01 19:43:02 +0000943 /* Only bind to function 0 of the device. Early generations
944 * used function 1 as a placeholder for multi-head. This causes
945 * us confusion instead, especially on the systems where both
946 * functions have the same PCI-ID!
947 */
948 if (PCI_FUNC(pdev->devfn))
949 return -ENODEV;
950
Daniel Vetter24986ee2013-12-11 11:34:33 +0100951 driver.driver_features &= ~(DRIVER_USE_AGP);
Daniel Vetter01a06852012-06-25 15:58:49 +0200952
Jordan Crousedcdb1672010-05-27 13:40:25 -0600953 return drm_get_pci_dev(pdev, ent, &driver);
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500954}
955
956static void
957i915_pci_remove(struct pci_dev *pdev)
958{
959 struct drm_device *dev = pci_get_drvdata(pdev);
960
961 drm_put_dev(dev);
962}
963
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100964static int i915_pm_suspend(struct device *dev)
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500965{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100966 struct pci_dev *pdev = to_pci_dev(dev);
967 struct drm_device *drm_dev = pci_get_drvdata(pdev);
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500968
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100969 if (!drm_dev || !drm_dev->dev_private) {
970 dev_err(dev, "DRM not initialized, aborting suspend.\n");
971 return -ENODEV;
972 }
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500973
Dave Airlie5bcf7192010-12-07 09:20:40 +1000974 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
975 return 0;
976
Imre Deak5e365c32014-10-23 19:23:25 +0300977 return i915_drm_suspend(drm_dev);
Imre Deak76c4b252014-04-01 19:55:22 +0300978}
979
980static int i915_pm_suspend_late(struct device *dev)
981{
Imre Deak888d0d42015-01-08 17:54:13 +0200982 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
Imre Deak76c4b252014-04-01 19:55:22 +0300983
984 /*
985 * We have a suspedn ordering issue with the snd-hda driver also
986 * requiring our device to be power up. Due to the lack of a
987 * parent/child relationship we currently solve this with an late
988 * suspend hook.
989 *
990 * FIXME: This should be solved with a special hdmi sink device or
991 * similar so that power domains can be employed.
992 */
993 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
994 return 0;
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500995
Imre Deakab3be732015-03-02 13:04:41 +0200996 return i915_drm_suspend_late(drm_dev, false);
997}
998
999static int i915_pm_poweroff_late(struct device *dev)
1000{
1001 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1002
1003 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1004 return 0;
1005
1006 return i915_drm_suspend_late(drm_dev, true);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001007}
1008
Imre Deak76c4b252014-04-01 19:55:22 +03001009static int i915_pm_resume_early(struct device *dev)
1010{
Imre Deak888d0d42015-01-08 17:54:13 +02001011 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
Imre Deak76c4b252014-04-01 19:55:22 +03001012
Imre Deak097dd832014-10-23 19:23:19 +03001013 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1014 return 0;
1015
Imre Deak5e365c32014-10-23 19:23:25 +03001016 return i915_drm_resume_early(drm_dev);
Imre Deak76c4b252014-04-01 19:55:22 +03001017}
1018
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001019static int i915_pm_resume(struct device *dev)
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001020{
Imre Deak888d0d42015-01-08 17:54:13 +02001021 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001022
Imre Deak097dd832014-10-23 19:23:19 +03001023 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1024 return 0;
1025
Imre Deak5a175142014-10-23 19:23:18 +03001026 return i915_drm_resume(drm_dev);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001027}
1028
Suketu Shahf75a1982015-04-16 14:22:11 +05301029static int skl_suspend_complete(struct drm_i915_private *dev_priv)
1030{
1031 /* Enabling DC6 is not a hard requirement to enter runtime D3 */
1032
1033 /*
1034 * This is to ensure that CSR isn't identified as loaded before
1035 * CSR-loading program is called during runtime-resume.
1036 */
1037 intel_csr_load_status_set(dev_priv, FW_UNINITIALIZED);
1038
1039 return 0;
1040}
1041
Sagar Kambleebc32822014-08-13 23:07:05 +05301042static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
Paulo Zanoni97bea202014-03-07 20:12:33 -03001043{
Paulo Zanoni414de7a2014-03-07 20:12:35 -03001044 hsw_enable_pc8(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001045
1046 return 0;
Paulo Zanoni97bea202014-03-07 20:12:33 -03001047}
1048
Suketu Shah31335ce2014-11-24 13:37:45 +05301049static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
1050{
1051 struct drm_device *dev = dev_priv->dev;
1052
1053 /* TODO: when DC5 support is added disable DC5 here. */
1054
1055 broxton_ddi_phy_uninit(dev);
1056 broxton_uninit_cdclk(dev);
1057 bxt_enable_dc9(dev_priv);
1058
1059 return 0;
1060}
1061
1062static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
1063{
1064 struct drm_device *dev = dev_priv->dev;
1065
1066 /* TODO: when CSR FW support is added make sure the FW is loaded */
1067
1068 bxt_disable_dc9(dev_priv);
1069
1070 /*
1071 * TODO: when DC5 support is added enable DC5 here if the CSR FW
1072 * is available.
1073 */
1074 broxton_init_cdclk(dev);
1075 broxton_ddi_phy_init(dev);
1076 intel_prepare_ddi(dev);
1077
1078 return 0;
1079}
1080
Suketu Shahf75a1982015-04-16 14:22:11 +05301081static int skl_resume_prepare(struct drm_i915_private *dev_priv)
1082{
1083 struct drm_device *dev = dev_priv->dev;
1084
1085 intel_csr_load_program(dev);
1086
1087 return 0;
1088}
1089
Imre Deakddeea5b2014-05-05 15:19:56 +03001090/*
1091 * Save all Gunit registers that may be lost after a D3 and a subsequent
1092 * S0i[R123] transition. The list of registers needing a save/restore is
1093 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1094 * registers in the following way:
1095 * - Driver: saved/restored by the driver
1096 * - Punit : saved/restored by the Punit firmware
1097 * - No, w/o marking: no need to save/restore, since the register is R/O or
1098 * used internally by the HW in a way that doesn't depend
1099 * keeping the content across a suspend/resume.
1100 * - Debug : used for debugging
1101 *
1102 * We save/restore all registers marked with 'Driver', with the following
1103 * exceptions:
1104 * - Registers out of use, including also registers marked with 'Debug'.
1105 * These have no effect on the driver's operation, so we don't save/restore
1106 * them to reduce the overhead.
1107 * - Registers that are fully setup by an initialization function called from
1108 * the resume path. For example many clock gating and RPS/RC6 registers.
1109 * - Registers that provide the right functionality with their reset defaults.
1110 *
1111 * TODO: Except for registers that based on the above 3 criteria can be safely
1112 * ignored, we save/restore all others, practically treating the HW context as
1113 * a black-box for the driver. Further investigation is needed to reduce the
1114 * saved/restored registers even further, by following the same 3 criteria.
1115 */
1116static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1117{
1118 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1119 int i;
1120
1121 /* GAM 0x4000-0x4770 */
1122 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1123 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1124 s->arb_mode = I915_READ(ARB_MODE);
1125 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1126 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1127
1128 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1129 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1130
1131 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
Imre Deakb5f1c972015-04-15 16:52:30 -07001132 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
Imre Deakddeea5b2014-05-05 15:19:56 +03001133
1134 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1135 s->ecochk = I915_READ(GAM_ECOCHK);
1136 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1137 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1138
1139 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1140
1141 /* MBC 0x9024-0x91D0, 0x8500 */
1142 s->g3dctl = I915_READ(VLV_G3DCTL);
1143 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1144 s->mbctl = I915_READ(GEN6_MBCTL);
1145
1146 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1147 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1148 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1149 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1150 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1151 s->rstctl = I915_READ(GEN6_RSTCTL);
1152 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1153
1154 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1155 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1156 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1157 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1158 s->ecobus = I915_READ(ECOBUS);
1159 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1160 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1161 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1162 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1163 s->rcedata = I915_READ(VLV_RCEDATA);
1164 s->spare2gh = I915_READ(VLV_SPAREG2H);
1165
1166 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1167 s->gt_imr = I915_READ(GTIMR);
1168 s->gt_ier = I915_READ(GTIER);
1169 s->pm_imr = I915_READ(GEN6_PMIMR);
1170 s->pm_ier = I915_READ(GEN6_PMIER);
1171
1172 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1173 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1174
1175 /* GT SA CZ domain, 0x100000-0x138124 */
1176 s->tilectl = I915_READ(TILECTL);
1177 s->gt_fifoctl = I915_READ(GTFIFOCTL);
1178 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1179 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1180 s->pmwgicz = I915_READ(VLV_PMWGICZ);
1181
1182 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1183 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1184 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
Jesse Barnes9c252102015-04-01 14:22:57 -07001185 s->pcbr = I915_READ(VLV_PCBR);
Imre Deakddeea5b2014-05-05 15:19:56 +03001186 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1187
1188 /*
1189 * Not saving any of:
1190 * DFT, 0x9800-0x9EC0
1191 * SARB, 0xB000-0xB1FC
1192 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1193 * PCI CFG
1194 */
1195}
1196
1197static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1198{
1199 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1200 u32 val;
1201 int i;
1202
1203 /* GAM 0x4000-0x4770 */
1204 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1205 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1206 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1207 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1208 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1209
1210 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1211 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1212
1213 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
Imre Deakb5f1c972015-04-15 16:52:30 -07001214 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
Imre Deakddeea5b2014-05-05 15:19:56 +03001215
1216 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1217 I915_WRITE(GAM_ECOCHK, s->ecochk);
1218 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1219 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1220
1221 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1222
1223 /* MBC 0x9024-0x91D0, 0x8500 */
1224 I915_WRITE(VLV_G3DCTL, s->g3dctl);
1225 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1226 I915_WRITE(GEN6_MBCTL, s->mbctl);
1227
1228 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1229 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1230 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1231 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1232 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1233 I915_WRITE(GEN6_RSTCTL, s->rstctl);
1234 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1235
1236 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1237 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1238 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1239 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1240 I915_WRITE(ECOBUS, s->ecobus);
1241 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1242 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1243 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1244 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1245 I915_WRITE(VLV_RCEDATA, s->rcedata);
1246 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1247
1248 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1249 I915_WRITE(GTIMR, s->gt_imr);
1250 I915_WRITE(GTIER, s->gt_ier);
1251 I915_WRITE(GEN6_PMIMR, s->pm_imr);
1252 I915_WRITE(GEN6_PMIER, s->pm_ier);
1253
1254 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1255 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1256
1257 /* GT SA CZ domain, 0x100000-0x138124 */
1258 I915_WRITE(TILECTL, s->tilectl);
1259 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1260 /*
1261 * Preserve the GT allow wake and GFX force clock bit, they are not
1262 * be restored, as they are used to control the s0ix suspend/resume
1263 * sequence by the caller.
1264 */
1265 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1266 val &= VLV_GTLC_ALLOWWAKEREQ;
1267 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1268 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1269
1270 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1271 val &= VLV_GFX_CLK_FORCE_ON_BIT;
1272 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1273 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1274
1275 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1276
1277 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1278 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1279 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
Jesse Barnes9c252102015-04-01 14:22:57 -07001280 I915_WRITE(VLV_PCBR, s->pcbr);
Imre Deakddeea5b2014-05-05 15:19:56 +03001281 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1282}
1283
Imre Deak650ad972014-04-18 16:35:02 +03001284int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1285{
1286 u32 val;
1287 int err;
1288
1289 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
Imre Deak650ad972014-04-18 16:35:02 +03001290
1291#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1292 /* Wait for a previous force-off to settle */
Deepak S85250dd2015-03-28 15:23:34 +05301293 if (force_on && !IS_CHERRYVIEW(dev_priv->dev)) {
1294 /* WARN_ON only for the Valleyview */
1295 WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1296
Imre Deak8d4eee92014-04-14 20:24:43 +03001297 err = wait_for(!COND, 20);
Imre Deak650ad972014-04-18 16:35:02 +03001298 if (err) {
1299 DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1300 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1301 return err;
1302 }
1303 }
1304
1305 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1306 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1307 if (force_on)
1308 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1309 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1310
1311 if (!force_on)
1312 return 0;
1313
Imre Deak8d4eee92014-04-14 20:24:43 +03001314 err = wait_for(COND, 20);
Imre Deak650ad972014-04-18 16:35:02 +03001315 if (err)
1316 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1317 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1318
1319 return err;
1320#undef COND
1321}
1322
Imre Deakddeea5b2014-05-05 15:19:56 +03001323static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1324{
1325 u32 val;
1326 int err = 0;
1327
1328 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1329 val &= ~VLV_GTLC_ALLOWWAKEREQ;
1330 if (allow)
1331 val |= VLV_GTLC_ALLOWWAKEREQ;
1332 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1333 POSTING_READ(VLV_GTLC_WAKE_CTRL);
1334
1335#define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1336 allow)
1337 err = wait_for(COND, 1);
1338 if (err)
1339 DRM_ERROR("timeout disabling GT waking\n");
1340 return err;
1341#undef COND
1342}
1343
1344static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1345 bool wait_for_on)
1346{
1347 u32 mask;
1348 u32 val;
1349 int err;
1350
1351 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1352 val = wait_for_on ? mask : 0;
1353#define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1354 if (COND)
1355 return 0;
1356
1357 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1358 wait_for_on ? "on" : "off",
1359 I915_READ(VLV_GTLC_PW_STATUS));
1360
1361 /*
1362 * RC6 transitioning can be delayed up to 2 msec (see
1363 * valleyview_enable_rps), use 3 msec for safety.
1364 */
1365 err = wait_for(COND, 3);
1366 if (err)
1367 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1368 wait_for_on ? "on" : "off");
1369
1370 return err;
1371#undef COND
1372}
1373
1374static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1375{
1376 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1377 return;
1378
1379 DRM_ERROR("GT register access while GT waking disabled\n");
1380 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1381}
1382
Sagar Kambleebc32822014-08-13 23:07:05 +05301383static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
Imre Deakddeea5b2014-05-05 15:19:56 +03001384{
1385 u32 mask;
1386 int err;
1387
1388 /*
1389 * Bspec defines the following GT well on flags as debug only, so
1390 * don't treat them as hard failures.
1391 */
1392 (void)vlv_wait_for_gt_wells(dev_priv, false);
1393
1394 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1395 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1396
1397 vlv_check_no_gt_access(dev_priv);
1398
1399 err = vlv_force_gfx_clock(dev_priv, true);
1400 if (err)
1401 goto err1;
1402
1403 err = vlv_allow_gt_wake(dev_priv, false);
1404 if (err)
1405 goto err2;
Deepak S98711162014-12-12 14:18:16 +05301406
1407 if (!IS_CHERRYVIEW(dev_priv->dev))
1408 vlv_save_gunit_s0ix_state(dev_priv);
Imre Deakddeea5b2014-05-05 15:19:56 +03001409
1410 err = vlv_force_gfx_clock(dev_priv, false);
1411 if (err)
1412 goto err2;
1413
1414 return 0;
1415
1416err2:
1417 /* For safety always re-enable waking and disable gfx clock forcing */
1418 vlv_allow_gt_wake(dev_priv, true);
1419err1:
1420 vlv_force_gfx_clock(dev_priv, false);
1421
1422 return err;
1423}
1424
Sagar Kamble016970b2014-08-13 23:07:06 +05301425static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1426 bool rpm_resume)
Imre Deakddeea5b2014-05-05 15:19:56 +03001427{
1428 struct drm_device *dev = dev_priv->dev;
1429 int err;
1430 int ret;
1431
1432 /*
1433 * If any of the steps fail just try to continue, that's the best we
1434 * can do at this point. Return the first error code (which will also
1435 * leave RPM permanently disabled).
1436 */
1437 ret = vlv_force_gfx_clock(dev_priv, true);
1438
Deepak S98711162014-12-12 14:18:16 +05301439 if (!IS_CHERRYVIEW(dev_priv->dev))
1440 vlv_restore_gunit_s0ix_state(dev_priv);
Imre Deakddeea5b2014-05-05 15:19:56 +03001441
1442 err = vlv_allow_gt_wake(dev_priv, true);
1443 if (!ret)
1444 ret = err;
1445
1446 err = vlv_force_gfx_clock(dev_priv, false);
1447 if (!ret)
1448 ret = err;
1449
1450 vlv_check_no_gt_access(dev_priv);
1451
Sagar Kamble016970b2014-08-13 23:07:06 +05301452 if (rpm_resume) {
1453 intel_init_clock_gating(dev);
1454 i915_gem_restore_fences(dev);
1455 }
Imre Deakddeea5b2014-05-05 15:19:56 +03001456
1457 return ret;
1458}
1459
Paulo Zanoni97bea202014-03-07 20:12:33 -03001460static int intel_runtime_suspend(struct device *device)
Paulo Zanoni8a187452013-12-06 20:32:13 -02001461{
1462 struct pci_dev *pdev = to_pci_dev(device);
1463 struct drm_device *dev = pci_get_drvdata(pdev);
1464 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001465 int ret;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001466
Imre Deakaeab0b52014-04-14 20:24:36 +03001467 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
Imre Deakc6df39b2014-04-14 20:24:29 +03001468 return -ENODEV;
1469
Imre Deak604effb2014-08-26 13:26:56 +03001470 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1471 return -ENODEV;
1472
Paulo Zanoni8a187452013-12-06 20:32:13 -02001473 DRM_DEBUG_KMS("Suspending device\n");
1474
Imre Deak9486db62014-04-22 20:21:07 +03001475 /*
Imre Deakd6102972014-05-07 19:57:49 +03001476 * We could deadlock here in case another thread holding struct_mutex
1477 * calls RPM suspend concurrently, since the RPM suspend will wait
1478 * first for this RPM suspend to finish. In this case the concurrent
1479 * RPM resume will be followed by its RPM suspend counterpart. Still
1480 * for consistency return -EAGAIN, which will reschedule this suspend.
1481 */
1482 if (!mutex_trylock(&dev->struct_mutex)) {
1483 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1484 /*
1485 * Bump the expiration timestamp, otherwise the suspend won't
1486 * be rescheduled.
1487 */
1488 pm_runtime_mark_last_busy(device);
1489
1490 return -EAGAIN;
1491 }
1492 /*
1493 * We are safe here against re-faults, since the fault handler takes
1494 * an RPM reference.
1495 */
1496 i915_gem_release_all_mmaps(dev_priv);
1497 mutex_unlock(&dev->struct_mutex);
1498
Paulo Zanonifac6adb2014-10-30 15:59:31 -02001499 intel_suspend_gt_powersave(dev);
Imre Deak2eb52522014-11-19 15:30:05 +02001500 intel_runtime_pm_disable_interrupts(dev_priv);
Imre Deakb5478bc2014-04-14 20:24:37 +03001501
Sagar Kambleebc32822014-08-13 23:07:05 +05301502 ret = intel_suspend_complete(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001503 if (ret) {
1504 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
Daniel Vetterb9632912014-09-30 10:56:44 +02001505 intel_runtime_pm_enable_interrupts(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001506
1507 return ret;
1508 }
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001509
Chris Wilson737b1502015-01-26 18:03:03 +02001510 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
Chris Wilsondc9fb092015-01-16 11:34:34 +02001511 intel_uncore_forcewake_reset(dev, false);
Paulo Zanoni8a187452013-12-06 20:32:13 -02001512 dev_priv->pm.suspended = true;
Kristen Carlson Accardi1fb23622014-01-14 15:36:15 -08001513
1514 /*
Paulo Zanonic8a0bd42014-08-21 17:09:38 -03001515 * FIXME: We really should find a document that references the arguments
1516 * used below!
Kristen Carlson Accardi1fb23622014-01-14 15:36:15 -08001517 */
Paulo Zanonic8a0bd42014-08-21 17:09:38 -03001518 if (IS_HASWELL(dev)) {
1519 /*
1520 * current versions of firmware which depend on this opregion
1521 * notification have repurposed the D1 definition to mean
1522 * "runtime suspended" vs. what you would normally expect (D3)
1523 * to distinguish it from notifications that might be sent via
1524 * the suspend path.
1525 */
1526 intel_opregion_notify_adapter(dev, PCI_D1);
1527 } else {
1528 /*
1529 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1530 * being detected, and the call we do at intel_runtime_resume()
1531 * won't be able to restore them. Since PCI_D3hot matches the
1532 * actual specification and appears to be working, use it. Let's
1533 * assume the other non-Haswell platforms will stay the same as
1534 * Broadwell.
1535 */
1536 intel_opregion_notify_adapter(dev, PCI_D3hot);
1537 }
Paulo Zanoni8a187452013-12-06 20:32:13 -02001538
Mika Kuoppala59bad942015-01-16 11:34:40 +02001539 assert_forcewakes_inactive(dev_priv);
Chris Wilsondc9fb092015-01-16 11:34:34 +02001540
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001541 DRM_DEBUG_KMS("Device suspended\n");
Paulo Zanoni8a187452013-12-06 20:32:13 -02001542 return 0;
1543}
1544
Paulo Zanoni97bea202014-03-07 20:12:33 -03001545static int intel_runtime_resume(struct device *device)
Paulo Zanoni8a187452013-12-06 20:32:13 -02001546{
1547 struct pci_dev *pdev = to_pci_dev(device);
1548 struct drm_device *dev = pci_get_drvdata(pdev);
1549 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni1a5df182014-10-27 17:54:32 -02001550 int ret = 0;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001551
Imre Deak604effb2014-08-26 13:26:56 +03001552 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1553 return -ENODEV;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001554
1555 DRM_DEBUG_KMS("Resuming device\n");
1556
Paulo Zanonicd2e9e92013-12-06 20:34:21 -02001557 intel_opregion_notify_adapter(dev, PCI_D0);
Paulo Zanoni8a187452013-12-06 20:32:13 -02001558 dev_priv->pm.suspended = false;
1559
Paulo Zanoni1a5df182014-10-27 17:54:32 -02001560 if (IS_GEN6(dev_priv))
1561 intel_init_pch_refclk(dev);
Suketu Shah31335ce2014-11-24 13:37:45 +05301562
1563 if (IS_BROXTON(dev))
1564 ret = bxt_resume_prepare(dev_priv);
Suketu Shahf75a1982015-04-16 14:22:11 +05301565 else if (IS_SKYLAKE(dev))
1566 ret = skl_resume_prepare(dev_priv);
Paulo Zanoni1a5df182014-10-27 17:54:32 -02001567 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1568 hsw_disable_pc8(dev_priv);
1569 else if (IS_VALLEYVIEW(dev_priv))
1570 ret = vlv_resume_prepare(dev_priv, true);
1571
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001572 /*
1573 * No point of rolling back things in case of an error, as the best
1574 * we can do is to hope that things will still work (and disable RPM).
1575 */
Imre Deak92b806d2014-04-14 20:24:39 +03001576 i915_gem_init_swizzling(dev);
1577 gen6_update_ring_freq(dev);
1578
Daniel Vetterb9632912014-09-30 10:56:44 +02001579 intel_runtime_pm_enable_interrupts(dev_priv);
Paulo Zanonifac6adb2014-10-30 15:59:31 -02001580 intel_enable_gt_powersave(dev);
Imre Deakb5478bc2014-04-14 20:24:37 +03001581
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001582 if (ret)
1583 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1584 else
1585 DRM_DEBUG_KMS("Device resumed\n");
1586
1587 return ret;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001588}
1589
Sagar Kamble016970b2014-08-13 23:07:06 +05301590/*
1591 * This function implements common functionality of runtime and system
1592 * suspend sequence.
1593 */
Sagar Kambleebc32822014-08-13 23:07:05 +05301594static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1595{
1596 struct drm_device *dev = dev_priv->dev;
1597 int ret;
1598
Suketu Shah31335ce2014-11-24 13:37:45 +05301599 if (IS_BROXTON(dev))
1600 ret = bxt_suspend_complete(dev_priv);
Suketu Shahf75a1982015-04-16 14:22:11 +05301601 else if (IS_SKYLAKE(dev))
1602 ret = skl_suspend_complete(dev_priv);
Suketu Shah31335ce2014-11-24 13:37:45 +05301603 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Sagar Kambleebc32822014-08-13 23:07:05 +05301604 ret = hsw_suspend_complete(dev_priv);
Imre Deak604effb2014-08-26 13:26:56 +03001605 else if (IS_VALLEYVIEW(dev))
Sagar Kambleebc32822014-08-13 23:07:05 +05301606 ret = vlv_suspend_complete(dev_priv);
Imre Deak604effb2014-08-26 13:26:56 +03001607 else
1608 ret = 0;
Sagar Kambleebc32822014-08-13 23:07:05 +05301609
1610 return ret;
1611}
1612
Chris Wilsonb4b78d12010-06-06 15:40:20 +01001613static const struct dev_pm_ops i915_pm_ops = {
Imre Deak5545dbb2014-10-23 19:23:28 +03001614 /*
1615 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1616 * PMSG_RESUME]
1617 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001618 .suspend = i915_pm_suspend,
Imre Deak76c4b252014-04-01 19:55:22 +03001619 .suspend_late = i915_pm_suspend_late,
1620 .resume_early = i915_pm_resume_early,
Akshay Joshi0206e352011-08-16 15:34:10 -04001621 .resume = i915_pm_resume,
Imre Deak5545dbb2014-10-23 19:23:28 +03001622
1623 /*
1624 * S4 event handlers
1625 * @freeze, @freeze_late : called (1) before creating the
1626 * hibernation image [PMSG_FREEZE] and
1627 * (2) after rebooting, before restoring
1628 * the image [PMSG_QUIESCE]
1629 * @thaw, @thaw_early : called (1) after creating the hibernation
1630 * image, before writing it [PMSG_THAW]
1631 * and (2) after failing to create or
1632 * restore the image [PMSG_RECOVER]
1633 * @poweroff, @poweroff_late: called after writing the hibernation
1634 * image, before rebooting [PMSG_HIBERNATE]
1635 * @restore, @restore_early : called after rebooting and restoring the
1636 * hibernation image [PMSG_RESTORE]
1637 */
Imre Deak36d61e62014-10-23 19:23:24 +03001638 .freeze = i915_pm_suspend,
1639 .freeze_late = i915_pm_suspend_late,
1640 .thaw_early = i915_pm_resume_early,
1641 .thaw = i915_pm_resume,
1642 .poweroff = i915_pm_suspend,
Imre Deakab3be732015-03-02 13:04:41 +02001643 .poweroff_late = i915_pm_poweroff_late,
Imre Deak76c4b252014-04-01 19:55:22 +03001644 .restore_early = i915_pm_resume_early,
Akshay Joshi0206e352011-08-16 15:34:10 -04001645 .restore = i915_pm_resume,
Imre Deak5545dbb2014-10-23 19:23:28 +03001646
1647 /* S0ix (via runtime suspend) event handlers */
Paulo Zanoni97bea202014-03-07 20:12:33 -03001648 .runtime_suspend = intel_runtime_suspend,
1649 .runtime_resume = intel_runtime_resume,
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001650};
1651
Laurent Pinchart78b68552012-05-17 13:27:22 +02001652static const struct vm_operations_struct i915_gem_vm_ops = {
Jesse Barnesde151cf2008-11-12 10:03:55 -08001653 .fault = i915_gem_fault,
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001654 .open = drm_gem_vm_open,
1655 .close = drm_gem_vm_close,
Jesse Barnesde151cf2008-11-12 10:03:55 -08001656};
1657
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001658static const struct file_operations i915_driver_fops = {
1659 .owner = THIS_MODULE,
1660 .open = drm_open,
1661 .release = drm_release,
1662 .unlocked_ioctl = drm_ioctl,
1663 .mmap = drm_gem_mmap,
1664 .poll = drm_poll,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001665 .read = drm_read,
1666#ifdef CONFIG_COMPAT
1667 .compat_ioctl = i915_compat_ioctl,
1668#endif
1669 .llseek = noop_llseek,
1670};
1671
Linus Torvalds1da177e2005-04-16 15:20:36 -07001672static struct drm_driver driver = {
Michael Witten0c547812011-08-25 17:55:54 +00001673 /* Don't use MTRRs here; the Xserver or userspace app should
1674 * deal with them for Intel hardware.
Dave Airlie792d2b92005-11-11 23:30:27 +11001675 */
Eric Anholt673a3942008-07-30 12:06:12 -07001676 .driver_features =
Daniel Vetter24986ee2013-12-11 11:34:33 +01001677 DRIVER_USE_AGP |
Kristian Høgsberg10ba5012013-08-25 18:29:01 +02001678 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1679 DRIVER_RENDER,
Dave Airlie22eae942005-11-10 22:16:34 +11001680 .load = i915_driver_load,
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001681 .unload = i915_driver_unload,
Eric Anholt673a3942008-07-30 12:06:12 -07001682 .open = i915_driver_open,
Dave Airlie22eae942005-11-10 22:16:34 +11001683 .lastclose = i915_driver_lastclose,
1684 .preclose = i915_driver_preclose,
Eric Anholt673a3942008-07-30 12:06:12 -07001685 .postclose = i915_driver_postclose,
David Herrmann915b4d12014-08-29 12:12:43 +02001686 .set_busid = drm_pci_set_busid,
Rafael J. Wysockid8e29202010-01-09 00:45:33 +01001687
1688 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
Imre Deakfc49b3d2014-10-23 19:23:27 +03001689 .suspend = i915_suspend_legacy,
Imre Deak76c4b252014-04-01 19:55:22 +03001690 .resume = i915_resume_legacy,
Rafael J. Wysockid8e29202010-01-09 00:45:33 +01001691
Dave Airliecda17382005-07-10 17:31:26 +10001692 .device_is_agp = i915_driver_device_is_agp,
Ben Gamari955b12d2009-02-17 20:08:49 -05001693#if defined(CONFIG_DEBUG_FS)
Ben Gamari27c202a2009-07-01 22:26:52 -04001694 .debugfs_init = i915_debugfs_init,
1695 .debugfs_cleanup = i915_debugfs_cleanup,
Ben Gamari955b12d2009-02-17 20:08:49 -05001696#endif
Eric Anholt673a3942008-07-30 12:06:12 -07001697 .gem_free_object = i915_gem_free_object,
Jesse Barnesde151cf2008-11-12 10:03:55 -08001698 .gem_vm_ops = &i915_gem_vm_ops,
Daniel Vetter1286ff72012-05-10 15:25:09 +02001699
1700 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1701 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1702 .gem_prime_export = i915_gem_prime_export,
1703 .gem_prime_import = i915_gem_prime_import,
1704
Dave Airlieff72145b2011-02-07 12:16:14 +10001705 .dumb_create = i915_gem_dumb_create,
Dave Airlieda6b51d2014-12-24 13:11:17 +10001706 .dumb_map_offset = i915_gem_mmap_gtt,
Daniel Vetter43387b32013-07-16 09:12:04 +02001707 .dumb_destroy = drm_gem_dumb_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001708 .ioctls = i915_ioctls,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001709 .fops = &i915_driver_fops,
Dave Airlie22eae942005-11-10 22:16:34 +11001710 .name = DRIVER_NAME,
1711 .desc = DRIVER_DESC,
1712 .date = DRIVER_DATE,
1713 .major = DRIVER_MAJOR,
1714 .minor = DRIVER_MINOR,
1715 .patchlevel = DRIVER_PATCHLEVEL,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001716};
1717
Dave Airlie8410ea32010-12-15 03:16:38 +10001718static struct pci_driver i915_pci_driver = {
1719 .name = DRIVER_NAME,
1720 .id_table = pciidlist,
1721 .probe = i915_pci_probe,
1722 .remove = i915_pci_remove,
1723 .driver.pm = &i915_pm_ops,
1724};
1725
Linus Torvalds1da177e2005-04-16 15:20:36 -07001726static int __init i915_init(void)
1727{
1728 driver.num_ioctls = i915_max_ioctl;
Jesse Barnes79e53942008-11-07 14:24:08 -08001729
1730 /*
1731 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1732 * explicitly disabled with the module pararmeter.
1733 *
1734 * Otherwise, just follow the parameter (defaulting to off).
1735 *
1736 * Allow optional vga_text_mode_force boot option to override
1737 * the default behavior.
1738 */
1739#if defined(CONFIG_DRM_I915_KMS)
Jani Nikulad330a952014-01-21 11:24:25 +02001740 if (i915.modeset != 0)
Jesse Barnes79e53942008-11-07 14:24:08 -08001741 driver.driver_features |= DRIVER_MODESET;
1742#endif
Jani Nikulad330a952014-01-21 11:24:25 +02001743 if (i915.modeset == 1)
Jesse Barnes79e53942008-11-07 14:24:08 -08001744 driver.driver_features |= DRIVER_MODESET;
1745
1746#ifdef CONFIG_VGA_CONSOLE
Jani Nikulad330a952014-01-21 11:24:25 +02001747 if (vgacon_text_force() && i915.modeset == -1)
Jesse Barnes79e53942008-11-07 14:24:08 -08001748 driver.driver_features &= ~DRIVER_MODESET;
1749#endif
1750
Daniel Vetterb30324a2013-11-13 22:11:25 +01001751 if (!(driver.driver_features & DRIVER_MODESET)) {
Chris Wilson3885c6b2011-01-23 10:45:14 +00001752 driver.get_vblank_timestamp = NULL;
Daniel Vetterb30324a2013-11-13 22:11:25 +01001753 /* Silently fail loading to not upset userspace. */
Jani Nikulac9cd7b62014-06-02 16:58:30 +03001754 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
Daniel Vetterb30324a2013-11-13 22:11:25 +01001755 return 0;
Daniel Vetterb30324a2013-11-13 22:11:25 +01001756 }
Chris Wilson3885c6b2011-01-23 10:45:14 +00001757
Matt Roperb2e77232015-01-22 16:53:12 -08001758 /*
1759 * FIXME: Note that we're lying to the DRM core here so that we can get access
1760 * to the atomic ioctl and the atomic properties. Only plane operations on
1761 * a single CRTC will actually work.
1762 */
1763 if (i915.nuclear_pageflip)
1764 driver.driver_features |= DRIVER_ATOMIC;
1765
Dave Airlie8410ea32010-12-15 03:16:38 +10001766 return drm_pci_init(&driver, &i915_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001767}
1768
1769static void __exit i915_exit(void)
1770{
Daniel Vetterb33ecdd2013-11-15 17:16:33 +01001771 if (!(driver.driver_features & DRIVER_MODESET))
1772 return; /* Never loaded a driver. */
Daniel Vetterb33ecdd2013-11-15 17:16:33 +01001773
Dave Airlie8410ea32010-12-15 03:16:38 +10001774 drm_pci_exit(&driver, &i915_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001775}
1776
1777module_init(i915_init);
1778module_exit(i915_exit);
1779
Damien Lespiau0a6d1632014-08-27 11:30:20 +01001780MODULE_AUTHOR("Tungsten Graphics, Inc.");
Damien Lespiau1eab9232014-08-27 11:30:21 +01001781MODULE_AUTHOR("Intel Corporation");
Damien Lespiau0a6d1632014-08-27 11:30:20 +01001782
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001783MODULE_DESCRIPTION(DRIVER_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001784MODULE_LICENSE("GPL and additional rights");