Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 5 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the |
| 9 | * "Software"), to deal in the Software without restriction, including |
| 10 | * without limitation the rights to use, copy, modify, merge, publish, |
| 11 | * distribute, sub license, and/or sell copies of the Software, and to |
| 12 | * permit persons to whom the Software is furnished to do so, subject to |
| 13 | * the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the |
| 16 | * next paragraph) shall be included in all copies or substantial portions |
| 17 | * of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 26 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 27 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame^] | 29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 30 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 31 | #include <linux/sysrq.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 32 | #include <linux/slab.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | #include "drmP.h" |
| 34 | #include "drm.h" |
| 35 | #include "i915_drm.h" |
| 36 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 37 | #include "i915_trace.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 38 | #include "intel_drv.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | #define MAX_NOPID ((u32)~0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 42 | /** |
| 43 | * Interrupts that are always left unmasked. |
| 44 | * |
| 45 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, |
| 46 | * we leave them always unmasked in IMR and then control enabling them through |
| 47 | * PIPESTAT alone. |
| 48 | */ |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 49 | #define I915_INTERRUPT_ENABLE_FIX \ |
| 50 | (I915_ASLE_INTERRUPT | \ |
| 51 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ |
| 52 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ |
| 53 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ |
| 54 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ |
| 55 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 56 | |
| 57 | /** Interrupts that we mask and unmask at runtime. */ |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 58 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 59 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 60 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
| 61 | PIPE_VBLANK_INTERRUPT_STATUS) |
| 62 | |
| 63 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ |
| 64 | PIPE_VBLANK_INTERRUPT_ENABLE) |
| 65 | |
| 66 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ |
| 67 | DRM_I915_VBLANK_PIPE_B) |
| 68 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 69 | /* For display hotplug interrupt */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 70 | static void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 71 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 72 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 73 | if ((dev_priv->irq_mask & mask) != 0) { |
| 74 | dev_priv->irq_mask &= ~mask; |
| 75 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 76 | POSTING_READ(DEIMR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 77 | } |
| 78 | } |
| 79 | |
| 80 | static inline void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 81 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 82 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 83 | if ((dev_priv->irq_mask & mask) != mask) { |
| 84 | dev_priv->irq_mask |= mask; |
| 85 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 86 | POSTING_READ(DEIMR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 87 | } |
| 88 | } |
| 89 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 90 | void |
| 91 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 92 | { |
| 93 | if ((dev_priv->pipestat[pipe] & mask) != mask) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 94 | u32 reg = PIPESTAT(pipe); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 95 | |
| 96 | dev_priv->pipestat[pipe] |= mask; |
| 97 | /* Enable the interrupt, clear any pending status */ |
| 98 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 99 | POSTING_READ(reg); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 100 | } |
| 101 | } |
| 102 | |
| 103 | void |
| 104 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 105 | { |
| 106 | if ((dev_priv->pipestat[pipe] & mask) != 0) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 107 | u32 reg = PIPESTAT(pipe); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 108 | |
| 109 | dev_priv->pipestat[pipe] &= ~mask; |
| 110 | I915_WRITE(reg, dev_priv->pipestat[pipe]); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 111 | POSTING_READ(reg); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 112 | } |
| 113 | } |
| 114 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 115 | /** |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 116 | * intel_enable_asle - enable ASLE interrupt for OpRegion |
| 117 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 118 | void intel_enable_asle(struct drm_device *dev) |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 119 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 120 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 121 | unsigned long irqflags; |
| 122 | |
| 123 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 124 | |
Eric Anholt | c619eed | 2010-01-28 16:45:52 -0800 | [diff] [blame] | 125 | if (HAS_PCH_SPLIT(dev)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 126 | ironlake_enable_display_irq(dev_priv, DE_GSE); |
Zhao Yakui | edcb49c | 2010-04-07 17:11:21 +0800 | [diff] [blame] | 127 | else { |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 128 | i915_enable_pipestat(dev_priv, 1, |
Jesse Barnes | d874bcf | 2010-06-30 13:16:00 -0700 | [diff] [blame] | 129 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 130 | if (INTEL_INFO(dev)->gen >= 4) |
Zhao Yakui | edcb49c | 2010-04-07 17:11:21 +0800 | [diff] [blame] | 131 | i915_enable_pipestat(dev_priv, 0, |
Jesse Barnes | d874bcf | 2010-06-30 13:16:00 -0700 | [diff] [blame] | 132 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
Zhao Yakui | edcb49c | 2010-04-07 17:11:21 +0800 | [diff] [blame] | 133 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 134 | |
| 135 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | /** |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 139 | * i915_pipe_enabled - check if a pipe is enabled |
| 140 | * @dev: DRM device |
| 141 | * @pipe: pipe to check |
| 142 | * |
| 143 | * Reading certain registers when the pipe is disabled can hang the chip. |
| 144 | * Use this routine to make sure the PLL is running and the pipe is active |
| 145 | * before reading such registers if unsure. |
| 146 | */ |
| 147 | static int |
| 148 | i915_pipe_enabled(struct drm_device *dev, int pipe) |
| 149 | { |
| 150 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 151 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 152 | } |
| 153 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 154 | /* Called from drm generic code, passed a 'crtc', which |
| 155 | * we use as a pipe index |
| 156 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 157 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 158 | { |
| 159 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 160 | unsigned long high_frame; |
| 161 | unsigned long low_frame; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 162 | u32 high1, high2, low; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 163 | |
| 164 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 165 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 166 | "pipe %c\n", pipe_name(pipe)); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 167 | return 0; |
| 168 | } |
| 169 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 170 | high_frame = PIPEFRAME(pipe); |
| 171 | low_frame = PIPEFRAMEPIXEL(pipe); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 172 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 173 | /* |
| 174 | * High & low register fields aren't synchronized, so make sure |
| 175 | * we get a low value that's stable across two reads of the high |
| 176 | * register. |
| 177 | */ |
| 178 | do { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 179 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
| 180 | low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; |
| 181 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 182 | } while (high1 != high2); |
| 183 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 184 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
| 185 | low >>= PIPE_FRAME_LOW_SHIFT; |
| 186 | return (high1 << 8) | low; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 187 | } |
| 188 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 189 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 190 | { |
| 191 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 192 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 193 | |
| 194 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 195 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 196 | "pipe %c\n", pipe_name(pipe)); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 197 | return 0; |
| 198 | } |
| 199 | |
| 200 | return I915_READ(reg); |
| 201 | } |
| 202 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 203 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 204 | int *vpos, int *hpos) |
| 205 | { |
| 206 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 207 | u32 vbl = 0, position = 0; |
| 208 | int vbl_start, vbl_end, htotal, vtotal; |
| 209 | bool in_vbl = true; |
| 210 | int ret = 0; |
| 211 | |
| 212 | if (!i915_pipe_enabled(dev, pipe)) { |
| 213 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 214 | "pipe %c\n", pipe_name(pipe)); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 215 | return 0; |
| 216 | } |
| 217 | |
| 218 | /* Get vtotal. */ |
| 219 | vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff); |
| 220 | |
| 221 | if (INTEL_INFO(dev)->gen >= 4) { |
| 222 | /* No obvious pixelcount register. Only query vertical |
| 223 | * scanout position from Display scan line register. |
| 224 | */ |
| 225 | position = I915_READ(PIPEDSL(pipe)); |
| 226 | |
| 227 | /* Decode into vertical scanout position. Don't have |
| 228 | * horizontal scanout position. |
| 229 | */ |
| 230 | *vpos = position & 0x1fff; |
| 231 | *hpos = 0; |
| 232 | } else { |
| 233 | /* Have access to pixelcount since start of frame. |
| 234 | * We can split this into vertical and horizontal |
| 235 | * scanout position. |
| 236 | */ |
| 237 | position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
| 238 | |
| 239 | htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff); |
| 240 | *vpos = position / htotal; |
| 241 | *hpos = position - (*vpos * htotal); |
| 242 | } |
| 243 | |
| 244 | /* Query vblank area. */ |
| 245 | vbl = I915_READ(VBLANK(pipe)); |
| 246 | |
| 247 | /* Test position against vblank region. */ |
| 248 | vbl_start = vbl & 0x1fff; |
| 249 | vbl_end = (vbl >> 16) & 0x1fff; |
| 250 | |
| 251 | if ((*vpos < vbl_start) || (*vpos > vbl_end)) |
| 252 | in_vbl = false; |
| 253 | |
| 254 | /* Inside "upper part" of vblank area? Apply corrective offset: */ |
| 255 | if (in_vbl && (*vpos >= vbl_start)) |
| 256 | *vpos = *vpos - vtotal; |
| 257 | |
| 258 | /* Readouts valid? */ |
| 259 | if (vbl > 0) |
| 260 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
| 261 | |
| 262 | /* In vblank? */ |
| 263 | if (in_vbl) |
| 264 | ret |= DRM_SCANOUTPOS_INVBL; |
| 265 | |
| 266 | return ret; |
| 267 | } |
| 268 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 269 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 270 | int *max_error, |
| 271 | struct timeval *vblank_time, |
| 272 | unsigned flags) |
| 273 | { |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 274 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 275 | struct drm_crtc *crtc; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 276 | |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 277 | if (pipe < 0 || pipe >= dev_priv->num_pipe) { |
| 278 | DRM_ERROR("Invalid crtc %d\n", pipe); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 279 | return -EINVAL; |
| 280 | } |
| 281 | |
| 282 | /* Get drm_crtc to timestamp: */ |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 283 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
| 284 | if (crtc == NULL) { |
| 285 | DRM_ERROR("Invalid crtc %d\n", pipe); |
| 286 | return -EINVAL; |
| 287 | } |
| 288 | |
| 289 | if (!crtc->enabled) { |
| 290 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); |
| 291 | return -EBUSY; |
| 292 | } |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 293 | |
| 294 | /* Helper routine in DRM core does all the work: */ |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 295 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
| 296 | vblank_time, flags, |
| 297 | crtc); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 298 | } |
| 299 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 300 | /* |
| 301 | * Handle hotplug events outside the interrupt handler proper. |
| 302 | */ |
| 303 | static void i915_hotplug_work_func(struct work_struct *work) |
| 304 | { |
| 305 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 306 | hotplug_work); |
| 307 | struct drm_device *dev = dev_priv->dev; |
Keith Packard | c31c4ba | 2009-05-06 11:48:58 -0700 | [diff] [blame] | 308 | struct drm_mode_config *mode_config = &dev->mode_config; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 309 | struct intel_encoder *encoder; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 310 | |
Keith Packard | a65e34c | 2011-07-25 10:04:56 -0700 | [diff] [blame] | 311 | mutex_lock(&mode_config->mutex); |
Jesse Barnes | e67189ab | 2011-02-11 14:44:51 -0800 | [diff] [blame] | 312 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
| 313 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 314 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) |
| 315 | if (encoder->hot_plug) |
| 316 | encoder->hot_plug(encoder); |
| 317 | |
Keith Packard | 40ee338 | 2011-07-28 15:31:19 -0700 | [diff] [blame] | 318 | mutex_unlock(&mode_config->mutex); |
| 319 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 320 | /* Just fire off a uevent and let userspace tell us what to do */ |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 321 | drm_helper_hpd_irq_event(dev); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 322 | } |
| 323 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 324 | static void i915_handle_rps_change(struct drm_device *dev) |
| 325 | { |
| 326 | drm_i915_private_t *dev_priv = dev->dev_private; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 327 | u32 busy_up, busy_down, max_avg, min_avg; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 328 | u8 new_delay = dev_priv->cur_delay; |
| 329 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 330 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 331 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
| 332 | busy_down = I915_READ(RCPREVBSYTDNAVG); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 333 | max_avg = I915_READ(RCBMAXAVG); |
| 334 | min_avg = I915_READ(RCBMINAVG); |
| 335 | |
| 336 | /* Handle RCS change request from hw */ |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 337 | if (busy_up > max_avg) { |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 338 | if (dev_priv->cur_delay != dev_priv->max_delay) |
| 339 | new_delay = dev_priv->cur_delay - 1; |
| 340 | if (new_delay < dev_priv->max_delay) |
| 341 | new_delay = dev_priv->max_delay; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 342 | } else if (busy_down < min_avg) { |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 343 | if (dev_priv->cur_delay != dev_priv->min_delay) |
| 344 | new_delay = dev_priv->cur_delay + 1; |
| 345 | if (new_delay > dev_priv->min_delay) |
| 346 | new_delay = dev_priv->min_delay; |
| 347 | } |
| 348 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 349 | if (ironlake_set_drps(dev, new_delay)) |
| 350 | dev_priv->cur_delay = new_delay; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 351 | |
| 352 | return; |
| 353 | } |
| 354 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 355 | static void notify_ring(struct drm_device *dev, |
| 356 | struct intel_ring_buffer *ring) |
| 357 | { |
| 358 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 475553d | 2011-01-20 09:52:56 +0000 | [diff] [blame] | 359 | u32 seqno; |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 360 | |
Chris Wilson | 475553d | 2011-01-20 09:52:56 +0000 | [diff] [blame] | 361 | if (ring->obj == NULL) |
| 362 | return; |
| 363 | |
| 364 | seqno = ring->get_seqno(ring); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 365 | trace_i915_gem_request_complete(ring, seqno); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 366 | |
| 367 | ring->irq_seqno = seqno; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 368 | wake_up_all(&ring->irq_queue); |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 369 | if (i915_enable_hangcheck) { |
| 370 | dev_priv->hangcheck_count = 0; |
| 371 | mod_timer(&dev_priv->hangcheck_timer, |
| 372 | jiffies + |
| 373 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
| 374 | } |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 375 | } |
| 376 | |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 377 | static void gen6_pm_rps_work(struct work_struct *work) |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 378 | { |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 379 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 380 | rps_work); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 381 | u8 new_delay = dev_priv->cur_delay; |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 382 | u32 pm_iir, pm_imr; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 383 | |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 384 | spin_lock_irq(&dev_priv->rps_lock); |
| 385 | pm_iir = dev_priv->pm_iir; |
| 386 | dev_priv->pm_iir = 0; |
| 387 | pm_imr = I915_READ(GEN6_PMIMR); |
Daniel Vetter | a9e2641 | 2011-09-08 14:00:21 +0200 | [diff] [blame] | 388 | I915_WRITE(GEN6_PMIMR, 0); |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 389 | spin_unlock_irq(&dev_priv->rps_lock); |
| 390 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 391 | if (!pm_iir) |
| 392 | return; |
| 393 | |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 394 | mutex_lock(&dev_priv->dev->struct_mutex); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 395 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
| 396 | if (dev_priv->cur_delay != dev_priv->max_delay) |
| 397 | new_delay = dev_priv->cur_delay + 1; |
| 398 | if (new_delay > dev_priv->max_delay) |
| 399 | new_delay = dev_priv->max_delay; |
| 400 | } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) { |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 401 | gen6_gt_force_wake_get(dev_priv); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 402 | if (dev_priv->cur_delay != dev_priv->min_delay) |
| 403 | new_delay = dev_priv->cur_delay - 1; |
| 404 | if (new_delay < dev_priv->min_delay) { |
| 405 | new_delay = dev_priv->min_delay; |
| 406 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, |
| 407 | I915_READ(GEN6_RP_INTERRUPT_LIMITS) | |
| 408 | ((new_delay << 16) & 0x3f0000)); |
| 409 | } else { |
| 410 | /* Make sure we continue to get down interrupts |
| 411 | * until we hit the minimum frequency */ |
| 412 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, |
| 413 | I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000); |
| 414 | } |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 415 | gen6_gt_force_wake_put(dev_priv); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 416 | } |
| 417 | |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 418 | gen6_set_rps(dev_priv->dev, new_delay); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 419 | dev_priv->cur_delay = new_delay; |
| 420 | |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 421 | /* |
| 422 | * rps_lock not held here because clearing is non-destructive. There is |
| 423 | * an *extremely* unlikely race with gen6_rps_enable() that is prevented |
| 424 | * by holding struct_mutex for the duration of the write. |
| 425 | */ |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 426 | mutex_unlock(&dev_priv->dev->struct_mutex); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 427 | } |
| 428 | |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 429 | static void pch_irq_handler(struct drm_device *dev) |
| 430 | { |
| 431 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 432 | u32 pch_iir; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 433 | int pipe; |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 434 | |
| 435 | pch_iir = I915_READ(SDEIIR); |
| 436 | |
| 437 | if (pch_iir & SDE_AUDIO_POWER_MASK) |
| 438 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
| 439 | (pch_iir & SDE_AUDIO_POWER_MASK) >> |
| 440 | SDE_AUDIO_POWER_SHIFT); |
| 441 | |
| 442 | if (pch_iir & SDE_GMBUS) |
| 443 | DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); |
| 444 | |
| 445 | if (pch_iir & SDE_AUDIO_HDCP_MASK) |
| 446 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); |
| 447 | |
| 448 | if (pch_iir & SDE_AUDIO_TRANS_MASK) |
| 449 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); |
| 450 | |
| 451 | if (pch_iir & SDE_POISON) |
| 452 | DRM_ERROR("PCH poison interrupt\n"); |
| 453 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 454 | if (pch_iir & SDE_FDI_MASK) |
| 455 | for_each_pipe(pipe) |
| 456 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
| 457 | pipe_name(pipe), |
| 458 | I915_READ(FDI_RX_IIR(pipe))); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 459 | |
| 460 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) |
| 461 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); |
| 462 | |
| 463 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) |
| 464 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); |
| 465 | |
| 466 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) |
| 467 | DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n"); |
| 468 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
| 469 | DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); |
| 470 | } |
| 471 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 472 | static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS) |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 473 | { |
| 474 | struct drm_device *dev = (struct drm_device *) arg; |
| 475 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 476 | int ret = IRQ_NONE; |
| 477 | u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; |
| 478 | struct drm_i915_master_private *master_priv; |
| 479 | |
| 480 | atomic_inc(&dev_priv->irq_received); |
| 481 | |
| 482 | /* disable master interrupt before clearing iir */ |
| 483 | de_ier = I915_READ(DEIER); |
| 484 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); |
| 485 | POSTING_READ(DEIER); |
| 486 | |
| 487 | de_iir = I915_READ(DEIIR); |
| 488 | gt_iir = I915_READ(GTIIR); |
| 489 | pch_iir = I915_READ(SDEIIR); |
| 490 | pm_iir = I915_READ(GEN6_PMIIR); |
| 491 | |
| 492 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0) |
| 493 | goto done; |
| 494 | |
| 495 | ret = IRQ_HANDLED; |
| 496 | |
| 497 | if (dev->primary->master) { |
| 498 | master_priv = dev->primary->master->driver_priv; |
| 499 | if (master_priv->sarea_priv) |
| 500 | master_priv->sarea_priv->last_dispatch = |
| 501 | READ_BREADCRUMB(dev_priv); |
| 502 | } |
| 503 | |
| 504 | if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) |
| 505 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 506 | if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT) |
| 507 | notify_ring(dev, &dev_priv->ring[VCS]); |
| 508 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
| 509 | notify_ring(dev, &dev_priv->ring[BCS]); |
| 510 | |
| 511 | if (de_iir & DE_GSE_IVB) |
| 512 | intel_opregion_gse_intr(dev); |
| 513 | |
| 514 | if (de_iir & DE_PLANEA_FLIP_DONE_IVB) { |
| 515 | intel_prepare_page_flip(dev, 0); |
| 516 | intel_finish_page_flip_plane(dev, 0); |
| 517 | } |
| 518 | |
| 519 | if (de_iir & DE_PLANEB_FLIP_DONE_IVB) { |
| 520 | intel_prepare_page_flip(dev, 1); |
| 521 | intel_finish_page_flip_plane(dev, 1); |
| 522 | } |
| 523 | |
| 524 | if (de_iir & DE_PIPEA_VBLANK_IVB) |
| 525 | drm_handle_vblank(dev, 0); |
| 526 | |
Dan Carpenter | f6b07f4 | 2011-05-25 12:56:56 +0300 | [diff] [blame] | 527 | if (de_iir & DE_PIPEB_VBLANK_IVB) |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 528 | drm_handle_vblank(dev, 1); |
| 529 | |
| 530 | /* check event from PCH */ |
| 531 | if (de_iir & DE_PCH_EVENT_IVB) { |
| 532 | if (pch_iir & SDE_HOTPLUG_MASK_CPT) |
| 533 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); |
| 534 | pch_irq_handler(dev); |
| 535 | } |
| 536 | |
| 537 | if (pm_iir & GEN6_PM_DEFERRED_EVENTS) { |
| 538 | unsigned long flags; |
| 539 | spin_lock_irqsave(&dev_priv->rps_lock, flags); |
| 540 | WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 541 | dev_priv->pm_iir |= pm_iir; |
Daniel Vetter | 4fb066a | 2011-09-08 14:00:20 +0200 | [diff] [blame] | 542 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); |
| 543 | POSTING_READ(GEN6_PMIMR); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 544 | spin_unlock_irqrestore(&dev_priv->rps_lock, flags); |
| 545 | queue_work(dev_priv->wq, &dev_priv->rps_work); |
| 546 | } |
| 547 | |
| 548 | /* should clear PCH hotplug event before clear CPU irq */ |
| 549 | I915_WRITE(SDEIIR, pch_iir); |
| 550 | I915_WRITE(GTIIR, gt_iir); |
| 551 | I915_WRITE(DEIIR, de_iir); |
| 552 | I915_WRITE(GEN6_PMIIR, pm_iir); |
| 553 | |
| 554 | done: |
| 555 | I915_WRITE(DEIER, de_ier); |
| 556 | POSTING_READ(DEIER); |
| 557 | |
| 558 | return ret; |
| 559 | } |
| 560 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 561 | static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 562 | { |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 563 | struct drm_device *dev = (struct drm_device *) arg; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 564 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 565 | int ret = IRQ_NONE; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 566 | u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 567 | u32 hotplug_mask; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 568 | struct drm_i915_master_private *master_priv; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 569 | u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT; |
| 570 | |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 571 | atomic_inc(&dev_priv->irq_received); |
| 572 | |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 573 | if (IS_GEN6(dev)) |
| 574 | bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 575 | |
Zou, Nanhai | 2d109a8 | 2009-11-06 02:13:01 +0000 | [diff] [blame] | 576 | /* disable master interrupt before clearing iir */ |
| 577 | de_ier = I915_READ(DEIER); |
| 578 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 579 | POSTING_READ(DEIER); |
Zou, Nanhai | 2d109a8 | 2009-11-06 02:13:01 +0000 | [diff] [blame] | 580 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 581 | de_iir = I915_READ(DEIIR); |
| 582 | gt_iir = I915_READ(GTIIR); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 583 | pch_iir = I915_READ(SDEIIR); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 584 | pm_iir = I915_READ(GEN6_PMIIR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 585 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 586 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && |
| 587 | (!IS_GEN6(dev) || pm_iir == 0)) |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 588 | goto done; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 589 | |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 590 | if (HAS_PCH_CPT(dev)) |
| 591 | hotplug_mask = SDE_HOTPLUG_MASK_CPT; |
| 592 | else |
| 593 | hotplug_mask = SDE_HOTPLUG_MASK; |
| 594 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 595 | ret = IRQ_HANDLED; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 596 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 597 | if (dev->primary->master) { |
| 598 | master_priv = dev->primary->master->driver_priv; |
| 599 | if (master_priv->sarea_priv) |
| 600 | master_priv->sarea_priv->last_dispatch = |
| 601 | READ_BREADCRUMB(dev_priv); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 602 | } |
| 603 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 604 | if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 605 | notify_ring(dev, &dev_priv->ring[RCS]); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 606 | if (gt_iir & bsd_usr_interrupt) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 607 | notify_ring(dev, &dev_priv->ring[VCS]); |
| 608 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
| 609 | notify_ring(dev, &dev_priv->ring[BCS]); |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 610 | |
| 611 | if (de_iir & DE_GSE) |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 612 | intel_opregion_gse_intr(dev); |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 613 | |
Zhenyu Wang | f072d2e | 2010-02-09 09:46:19 +0800 | [diff] [blame] | 614 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 615 | intel_prepare_page_flip(dev, 0); |
Chris Wilson | 2bbda38 | 2010-09-02 17:59:39 +0100 | [diff] [blame] | 616 | intel_finish_page_flip_plane(dev, 0); |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 617 | } |
| 618 | |
Zhenyu Wang | f072d2e | 2010-02-09 09:46:19 +0800 | [diff] [blame] | 619 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
| 620 | intel_prepare_page_flip(dev, 1); |
Chris Wilson | 2bbda38 | 2010-09-02 17:59:39 +0100 | [diff] [blame] | 621 | intel_finish_page_flip_plane(dev, 1); |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 622 | } |
Li Peng | c062df6 | 2010-01-23 00:12:58 +0800 | [diff] [blame] | 623 | |
Zhenyu Wang | f072d2e | 2010-02-09 09:46:19 +0800 | [diff] [blame] | 624 | if (de_iir & DE_PIPEA_VBLANK) |
| 625 | drm_handle_vblank(dev, 0); |
| 626 | |
| 627 | if (de_iir & DE_PIPEB_VBLANK) |
| 628 | drm_handle_vblank(dev, 1); |
| 629 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 630 | /* check event from PCH */ |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 631 | if (de_iir & DE_PCH_EVENT) { |
| 632 | if (pch_iir & hotplug_mask) |
| 633 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); |
| 634 | pch_irq_handler(dev); |
| 635 | } |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 636 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 637 | if (de_iir & DE_PCU_EVENT) { |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 638 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 639 | i915_handle_rps_change(dev); |
| 640 | } |
| 641 | |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 642 | if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) { |
| 643 | /* |
| 644 | * IIR bits should never already be set because IMR should |
| 645 | * prevent an interrupt from being shown in IIR. The warning |
| 646 | * displays a case where we've unsafely cleared |
| 647 | * dev_priv->pm_iir. Although missing an interrupt of the same |
| 648 | * type is not a problem, it displays a problem in the logic. |
| 649 | * |
| 650 | * The mask bit in IMR is cleared by rps_work. |
| 651 | */ |
| 652 | unsigned long flags; |
| 653 | spin_lock_irqsave(&dev_priv->rps_lock, flags); |
| 654 | WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 655 | dev_priv->pm_iir |= pm_iir; |
Daniel Vetter | 4fb066a | 2011-09-08 14:00:20 +0200 | [diff] [blame] | 656 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); |
| 657 | POSTING_READ(GEN6_PMIMR); |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 658 | spin_unlock_irqrestore(&dev_priv->rps_lock, flags); |
| 659 | queue_work(dev_priv->wq, &dev_priv->rps_work); |
| 660 | } |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 661 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 662 | /* should clear PCH hotplug event before clear CPU irq */ |
| 663 | I915_WRITE(SDEIIR, pch_iir); |
| 664 | I915_WRITE(GTIIR, gt_iir); |
| 665 | I915_WRITE(DEIIR, de_iir); |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 666 | I915_WRITE(GEN6_PMIIR, pm_iir); |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 667 | |
| 668 | done: |
Zou, Nanhai | 2d109a8 | 2009-11-06 02:13:01 +0000 | [diff] [blame] | 669 | I915_WRITE(DEIER, de_ier); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 670 | POSTING_READ(DEIER); |
Zou, Nanhai | 2d109a8 | 2009-11-06 02:13:01 +0000 | [diff] [blame] | 671 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 672 | return ret; |
| 673 | } |
| 674 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 675 | /** |
| 676 | * i915_error_work_func - do process context error handling work |
| 677 | * @work: work struct |
| 678 | * |
| 679 | * Fire an error uevent so userspace can see that a hang or error |
| 680 | * was detected. |
| 681 | */ |
| 682 | static void i915_error_work_func(struct work_struct *work) |
| 683 | { |
| 684 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 685 | error_work); |
| 686 | struct drm_device *dev = dev_priv->dev; |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 687 | char *error_event[] = { "ERROR=1", NULL }; |
| 688 | char *reset_event[] = { "RESET=1", NULL }; |
| 689 | char *reset_done_event[] = { "ERROR=0", NULL }; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 690 | |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 691 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 692 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 693 | if (atomic_read(&dev_priv->mm.wedged)) { |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 694 | DRM_DEBUG_DRIVER("resetting chip\n"); |
| 695 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); |
| 696 | if (!i915_reset(dev, GRDOM_RENDER)) { |
| 697 | atomic_set(&dev_priv->mm.wedged, 0); |
| 698 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 699 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 700 | complete_all(&dev_priv->error_completion); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 701 | } |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 702 | } |
| 703 | |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 704 | #ifdef CONFIG_DEBUG_FS |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 705 | static struct drm_i915_error_object * |
Chris Wilson | bcfb2e2 | 2011-01-07 21:06:07 +0000 | [diff] [blame] | 706 | i915_error_object_create(struct drm_i915_private *dev_priv, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 707 | struct drm_i915_gem_object *src) |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 708 | { |
| 709 | struct drm_i915_error_object *dst; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 710 | int page, page_count; |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 711 | u32 reloc_offset; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 712 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 713 | if (src == NULL || src->pages == NULL) |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 714 | return NULL; |
| 715 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 716 | page_count = src->base.size / PAGE_SIZE; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 717 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 718 | dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 719 | if (dst == NULL) |
| 720 | return NULL; |
| 721 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 722 | reloc_offset = src->gtt_offset; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 723 | for (page = 0; page < page_count; page++) { |
Andrew Morton | 788885a | 2010-05-11 14:07:05 -0700 | [diff] [blame] | 724 | unsigned long flags; |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 725 | void *d; |
Andrew Morton | 788885a | 2010-05-11 14:07:05 -0700 | [diff] [blame] | 726 | |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 727 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 728 | if (d == NULL) |
| 729 | goto unwind; |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 730 | |
Andrew Morton | 788885a | 2010-05-11 14:07:05 -0700 | [diff] [blame] | 731 | local_irq_save(flags); |
Chris Wilson | 172975aa | 2011-12-14 13:57:25 +0100 | [diff] [blame] | 732 | if (reloc_offset < dev_priv->mm.gtt_mappable_end) { |
| 733 | void __iomem *s; |
| 734 | |
| 735 | /* Simply ignore tiling or any overlapping fence. |
| 736 | * It's part of the error state, and this hopefully |
| 737 | * captures what the GPU read. |
| 738 | */ |
| 739 | |
| 740 | s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
| 741 | reloc_offset); |
| 742 | memcpy_fromio(d, s, PAGE_SIZE); |
| 743 | io_mapping_unmap_atomic(s); |
| 744 | } else { |
| 745 | void *s; |
| 746 | |
| 747 | drm_clflush_pages(&src->pages[page], 1); |
| 748 | |
| 749 | s = kmap_atomic(src->pages[page]); |
| 750 | memcpy(d, s, PAGE_SIZE); |
| 751 | kunmap_atomic(s); |
| 752 | |
| 753 | drm_clflush_pages(&src->pages[page], 1); |
| 754 | } |
Andrew Morton | 788885a | 2010-05-11 14:07:05 -0700 | [diff] [blame] | 755 | local_irq_restore(flags); |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 756 | |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 757 | dst->pages[page] = d; |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 758 | |
| 759 | reloc_offset += PAGE_SIZE; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 760 | } |
| 761 | dst->page_count = page_count; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 762 | dst->gtt_offset = src->gtt_offset; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 763 | |
| 764 | return dst; |
| 765 | |
| 766 | unwind: |
| 767 | while (page--) |
| 768 | kfree(dst->pages[page]); |
| 769 | kfree(dst); |
| 770 | return NULL; |
| 771 | } |
| 772 | |
| 773 | static void |
| 774 | i915_error_object_free(struct drm_i915_error_object *obj) |
| 775 | { |
| 776 | int page; |
| 777 | |
| 778 | if (obj == NULL) |
| 779 | return; |
| 780 | |
| 781 | for (page = 0; page < obj->page_count; page++) |
| 782 | kfree(obj->pages[page]); |
| 783 | |
| 784 | kfree(obj); |
| 785 | } |
| 786 | |
| 787 | static void |
| 788 | i915_error_state_free(struct drm_device *dev, |
| 789 | struct drm_i915_error_state *error) |
| 790 | { |
Chris Wilson | e2f973d | 2011-01-27 19:15:11 +0000 | [diff] [blame] | 791 | int i; |
| 792 | |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 793 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { |
| 794 | i915_error_object_free(error->ring[i].batchbuffer); |
| 795 | i915_error_object_free(error->ring[i].ringbuffer); |
| 796 | kfree(error->ring[i].requests); |
| 797 | } |
Chris Wilson | e2f973d | 2011-01-27 19:15:11 +0000 | [diff] [blame] | 798 | |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 799 | kfree(error->active_bo); |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 800 | kfree(error->overlay); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 801 | kfree(error); |
| 802 | } |
| 803 | |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 804 | static u32 capture_bo_list(struct drm_i915_error_buffer *err, |
| 805 | int count, |
| 806 | struct list_head *head) |
| 807 | { |
| 808 | struct drm_i915_gem_object *obj; |
| 809 | int i = 0; |
| 810 | |
| 811 | list_for_each_entry(obj, head, mm_list) { |
| 812 | err->size = obj->base.size; |
| 813 | err->name = obj->base.name; |
| 814 | err->seqno = obj->last_rendering_seqno; |
| 815 | err->gtt_offset = obj->gtt_offset; |
| 816 | err->read_domains = obj->base.read_domains; |
| 817 | err->write_domain = obj->base.write_domain; |
| 818 | err->fence_reg = obj->fence_reg; |
| 819 | err->pinned = 0; |
| 820 | if (obj->pin_count > 0) |
| 821 | err->pinned = 1; |
| 822 | if (obj->user_pin_count > 0) |
| 823 | err->pinned = -1; |
| 824 | err->tiling = obj->tiling_mode; |
| 825 | err->dirty = obj->dirty; |
| 826 | err->purgeable = obj->madv != I915_MADV_WILLNEED; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 827 | err->ring = obj->ring ? obj->ring->id : -1; |
Chris Wilson | 93dfb40 | 2011-03-29 16:59:50 -0700 | [diff] [blame] | 828 | err->cache_level = obj->cache_level; |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 829 | |
| 830 | if (++i == count) |
| 831 | break; |
| 832 | |
| 833 | err++; |
| 834 | } |
| 835 | |
| 836 | return i; |
| 837 | } |
| 838 | |
Chris Wilson | 748ebc6 | 2010-10-24 10:28:47 +0100 | [diff] [blame] | 839 | static void i915_gem_record_fences(struct drm_device *dev, |
| 840 | struct drm_i915_error_state *error) |
| 841 | { |
| 842 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 843 | int i; |
| 844 | |
| 845 | /* Fences */ |
| 846 | switch (INTEL_INFO(dev)->gen) { |
Daniel Vetter | 775d17b | 2011-10-09 21:52:01 +0200 | [diff] [blame] | 847 | case 7: |
Chris Wilson | 748ebc6 | 2010-10-24 10:28:47 +0100 | [diff] [blame] | 848 | case 6: |
| 849 | for (i = 0; i < 16; i++) |
| 850 | error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); |
| 851 | break; |
| 852 | case 5: |
| 853 | case 4: |
| 854 | for (i = 0; i < 16; i++) |
| 855 | error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); |
| 856 | break; |
| 857 | case 3: |
| 858 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 859 | for (i = 0; i < 8; i++) |
| 860 | error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); |
| 861 | case 2: |
| 862 | for (i = 0; i < 8; i++) |
| 863 | error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); |
| 864 | break; |
| 865 | |
| 866 | } |
| 867 | } |
| 868 | |
Chris Wilson | bcfb2e2 | 2011-01-07 21:06:07 +0000 | [diff] [blame] | 869 | static struct drm_i915_error_object * |
| 870 | i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, |
| 871 | struct intel_ring_buffer *ring) |
| 872 | { |
| 873 | struct drm_i915_gem_object *obj; |
| 874 | u32 seqno; |
| 875 | |
| 876 | if (!ring->get_seqno) |
| 877 | return NULL; |
| 878 | |
| 879 | seqno = ring->get_seqno(ring); |
| 880 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { |
| 881 | if (obj->ring != ring) |
| 882 | continue; |
| 883 | |
Chris Wilson | c37d9a5 | 2011-01-12 20:33:01 +0000 | [diff] [blame] | 884 | if (i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
Chris Wilson | bcfb2e2 | 2011-01-07 21:06:07 +0000 | [diff] [blame] | 885 | continue; |
| 886 | |
| 887 | if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) |
| 888 | continue; |
| 889 | |
| 890 | /* We need to copy these to an anonymous buffer as the simplest |
| 891 | * method to avoid being overwritten by userspace. |
| 892 | */ |
| 893 | return i915_error_object_create(dev_priv, obj); |
| 894 | } |
| 895 | |
| 896 | return NULL; |
| 897 | } |
| 898 | |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 899 | static void i915_record_ring_state(struct drm_device *dev, |
| 900 | struct drm_i915_error_state *error, |
| 901 | struct intel_ring_buffer *ring) |
| 902 | { |
| 903 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 904 | |
Daniel Vetter | 33f3f51 | 2011-12-14 13:57:39 +0100 | [diff] [blame] | 905 | if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | c1cd90e | 2011-12-14 13:57:02 +0100 | [diff] [blame] | 906 | error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base)); |
Daniel Vetter | 33f3f51 | 2011-12-14 13:57:39 +0100 | [diff] [blame] | 907 | error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring)); |
Daniel Vetter | 7e3b873 | 2012-02-01 22:26:45 +0100 | [diff] [blame] | 908 | error->semaphore_mboxes[ring->id][0] |
| 909 | = I915_READ(RING_SYNC_0(ring->mmio_base)); |
| 910 | error->semaphore_mboxes[ring->id][1] |
| 911 | = I915_READ(RING_SYNC_1(ring->mmio_base)); |
Daniel Vetter | 33f3f51 | 2011-12-14 13:57:39 +0100 | [diff] [blame] | 912 | } |
Daniel Vetter | c1cd90e | 2011-12-14 13:57:02 +0100 | [diff] [blame] | 913 | |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 914 | if (INTEL_INFO(dev)->gen >= 4) { |
| 915 | error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base)); |
| 916 | error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base)); |
| 917 | error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base)); |
Daniel Vetter | c1cd90e | 2011-12-14 13:57:02 +0100 | [diff] [blame] | 918 | error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base)); |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 919 | if (ring->id == RCS) { |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 920 | error->instdone1 = I915_READ(INSTDONE1); |
| 921 | error->bbaddr = I915_READ64(BB_ADDR); |
| 922 | } |
| 923 | } else { |
| 924 | error->ipeir[ring->id] = I915_READ(IPEIR); |
| 925 | error->ipehr[ring->id] = I915_READ(IPEHR); |
| 926 | error->instdone[ring->id] = I915_READ(INSTDONE); |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 927 | } |
| 928 | |
Daniel Vetter | c1cd90e | 2011-12-14 13:57:02 +0100 | [diff] [blame] | 929 | error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base)); |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 930 | error->seqno[ring->id] = ring->get_seqno(ring); |
| 931 | error->acthd[ring->id] = intel_ring_get_active_head(ring); |
Daniel Vetter | c1cd90e | 2011-12-14 13:57:02 +0100 | [diff] [blame] | 932 | error->head[ring->id] = I915_READ_HEAD(ring); |
| 933 | error->tail[ring->id] = I915_READ_TAIL(ring); |
Daniel Vetter | 7e3b873 | 2012-02-01 22:26:45 +0100 | [diff] [blame] | 934 | |
| 935 | error->cpu_ring_head[ring->id] = ring->head; |
| 936 | error->cpu_ring_tail[ring->id] = ring->tail; |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 937 | } |
| 938 | |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 939 | static void i915_gem_record_rings(struct drm_device *dev, |
| 940 | struct drm_i915_error_state *error) |
| 941 | { |
| 942 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 943 | struct drm_i915_gem_request *request; |
| 944 | int i, count; |
| 945 | |
| 946 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 947 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; |
| 948 | |
| 949 | if (ring->obj == NULL) |
| 950 | continue; |
| 951 | |
| 952 | i915_record_ring_state(dev, error, ring); |
| 953 | |
| 954 | error->ring[i].batchbuffer = |
| 955 | i915_error_first_batchbuffer(dev_priv, ring); |
| 956 | |
| 957 | error->ring[i].ringbuffer = |
| 958 | i915_error_object_create(dev_priv, ring->obj); |
| 959 | |
| 960 | count = 0; |
| 961 | list_for_each_entry(request, &ring->request_list, list) |
| 962 | count++; |
| 963 | |
| 964 | error->ring[i].num_requests = count; |
| 965 | error->ring[i].requests = |
| 966 | kmalloc(count*sizeof(struct drm_i915_error_request), |
| 967 | GFP_ATOMIC); |
| 968 | if (error->ring[i].requests == NULL) { |
| 969 | error->ring[i].num_requests = 0; |
| 970 | continue; |
| 971 | } |
| 972 | |
| 973 | count = 0; |
| 974 | list_for_each_entry(request, &ring->request_list, list) { |
| 975 | struct drm_i915_error_request *erq; |
| 976 | |
| 977 | erq = &error->ring[i].requests[count++]; |
| 978 | erq->seqno = request->seqno; |
| 979 | erq->jiffies = request->emitted_jiffies; |
Chris Wilson | ee4f42b | 2012-02-15 11:25:38 +0000 | [diff] [blame] | 980 | erq->tail = request->tail; |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 981 | } |
| 982 | } |
| 983 | } |
| 984 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 985 | /** |
| 986 | * i915_capture_error_state - capture an error record for later analysis |
| 987 | * @dev: drm device |
| 988 | * |
| 989 | * Should be called when an error is detected (either a hang or an error |
| 990 | * interrupt) to capture error state from the time of the error. Fills |
| 991 | * out a structure which becomes available in debugfs for user level tools |
| 992 | * to pick up. |
| 993 | */ |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 994 | static void i915_capture_error_state(struct drm_device *dev) |
| 995 | { |
| 996 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 997 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 998 | struct drm_i915_error_state *error; |
| 999 | unsigned long flags; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1000 | int i, pipe; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1001 | |
| 1002 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1003 | error = dev_priv->first_error; |
| 1004 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
| 1005 | if (error) |
| 1006 | return; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1007 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1008 | /* Account for pipe specific data like PIPE*STAT */ |
Daniel Vetter | 33f3f51 | 2011-12-14 13:57:39 +0100 | [diff] [blame] | 1009 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1010 | if (!error) { |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1011 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); |
| 1012 | return; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1013 | } |
| 1014 | |
Chris Wilson | b6f7833 | 2011-02-01 14:15:55 +0000 | [diff] [blame] | 1015 | DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n", |
| 1016 | dev->primary->index); |
Chris Wilson | 2fa772f | 2010-10-01 13:23:27 +0100 | [diff] [blame] | 1017 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1018 | error->eir = I915_READ(EIR); |
| 1019 | error->pgtbl_er = I915_READ(PGTBL_ER); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1020 | for_each_pipe(pipe) |
| 1021 | error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 1022 | |
Daniel Vetter | 33f3f51 | 2011-12-14 13:57:39 +0100 | [diff] [blame] | 1023 | if (INTEL_INFO(dev)->gen >= 6) { |
Chris Wilson | f406839 | 2010-10-27 20:36:41 +0100 | [diff] [blame] | 1024 | error->error = I915_READ(ERROR_GEN6); |
Daniel Vetter | 33f3f51 | 2011-12-14 13:57:39 +0100 | [diff] [blame] | 1025 | error->done_reg = I915_READ(DONE_REG); |
| 1026 | } |
Chris Wilson | add354d | 2010-10-29 19:00:51 +0100 | [diff] [blame] | 1027 | |
Chris Wilson | 748ebc6 | 2010-10-24 10:28:47 +0100 | [diff] [blame] | 1028 | i915_gem_record_fences(dev, error); |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 1029 | i915_gem_record_rings(dev, error); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1030 | |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 1031 | /* Record buffers on the active and pinned lists. */ |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1032 | error->active_bo = NULL; |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 1033 | error->pinned_bo = NULL; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1034 | |
Chris Wilson | bcfb2e2 | 2011-01-07 21:06:07 +0000 | [diff] [blame] | 1035 | i = 0; |
| 1036 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) |
| 1037 | i++; |
| 1038 | error->active_bo_count = i; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1039 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
Chris Wilson | bcfb2e2 | 2011-01-07 21:06:07 +0000 | [diff] [blame] | 1040 | i++; |
| 1041 | error->pinned_bo_count = i - error->active_bo_count; |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 1042 | |
Chris Wilson | 8e934db | 2011-01-24 12:34:00 +0000 | [diff] [blame] | 1043 | error->active_bo = NULL; |
| 1044 | error->pinned_bo = NULL; |
Chris Wilson | bcfb2e2 | 2011-01-07 21:06:07 +0000 | [diff] [blame] | 1045 | if (i) { |
| 1046 | error->active_bo = kmalloc(sizeof(*error->active_bo)*i, |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1047 | GFP_ATOMIC); |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 1048 | if (error->active_bo) |
| 1049 | error->pinned_bo = |
| 1050 | error->active_bo + error->active_bo_count; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1051 | } |
| 1052 | |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 1053 | if (error->active_bo) |
| 1054 | error->active_bo_count = |
| 1055 | capture_bo_list(error->active_bo, |
| 1056 | error->active_bo_count, |
| 1057 | &dev_priv->mm.active_list); |
| 1058 | |
| 1059 | if (error->pinned_bo) |
| 1060 | error->pinned_bo_count = |
| 1061 | capture_bo_list(error->pinned_bo, |
| 1062 | error->pinned_bo_count, |
| 1063 | &dev_priv->mm.pinned_list); |
| 1064 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1065 | do_gettimeofday(&error->time); |
| 1066 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1067 | error->overlay = intel_overlay_capture_error_state(dev); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 1068 | error->display = intel_display_capture_error_state(dev); |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1069 | |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1070 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
| 1071 | if (dev_priv->first_error == NULL) { |
| 1072 | dev_priv->first_error = error; |
| 1073 | error = NULL; |
| 1074 | } |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1075 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1076 | |
| 1077 | if (error) |
| 1078 | i915_error_state_free(dev, error); |
| 1079 | } |
| 1080 | |
| 1081 | void i915_destroy_error_state(struct drm_device *dev) |
| 1082 | { |
| 1083 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1084 | struct drm_i915_error_state *error; |
Ben Widawsky | 6dc0e81 | 2012-01-23 15:30:02 -0800 | [diff] [blame] | 1085 | unsigned long flags; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1086 | |
Ben Widawsky | 6dc0e81 | 2012-01-23 15:30:02 -0800 | [diff] [blame] | 1087 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1088 | error = dev_priv->first_error; |
| 1089 | dev_priv->first_error = NULL; |
Ben Widawsky | 6dc0e81 | 2012-01-23 15:30:02 -0800 | [diff] [blame] | 1090 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1091 | |
| 1092 | if (error) |
| 1093 | i915_error_state_free(dev, error); |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1094 | } |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 1095 | #else |
| 1096 | #define i915_capture_error_state(x) |
| 1097 | #endif |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1098 | |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 1099 | static void i915_report_and_clear_eir(struct drm_device *dev) |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1100 | { |
| 1101 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1102 | u32 eir = I915_READ(EIR); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1103 | int pipe; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1104 | |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 1105 | if (!eir) |
| 1106 | return; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1107 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame^] | 1108 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1109 | |
| 1110 | if (IS_G4X(dev)) { |
| 1111 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { |
| 1112 | u32 ipeir = I915_READ(IPEIR_I965); |
| 1113 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame^] | 1114 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
| 1115 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); |
| 1116 | pr_err(" INSTDONE: 0x%08x\n", |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1117 | I915_READ(INSTDONE_I965)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame^] | 1118 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
| 1119 | pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1)); |
| 1120 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1121 | I915_WRITE(IPEIR_I965, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1122 | POSTING_READ(IPEIR_I965); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1123 | } |
| 1124 | if (eir & GM45_ERROR_PAGE_TABLE) { |
| 1125 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame^] | 1126 | pr_err("page table error\n"); |
| 1127 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1128 | I915_WRITE(PGTBL_ER, pgtbl_err); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1129 | POSTING_READ(PGTBL_ER); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1130 | } |
| 1131 | } |
| 1132 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1133 | if (!IS_GEN2(dev)) { |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1134 | if (eir & I915_ERROR_PAGE_TABLE) { |
| 1135 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame^] | 1136 | pr_err("page table error\n"); |
| 1137 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1138 | I915_WRITE(PGTBL_ER, pgtbl_err); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1139 | POSTING_READ(PGTBL_ER); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1140 | } |
| 1141 | } |
| 1142 | |
| 1143 | if (eir & I915_ERROR_MEMORY_REFRESH) { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame^] | 1144 | pr_err("memory refresh error:\n"); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1145 | for_each_pipe(pipe) |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame^] | 1146 | pr_err("pipe %c stat: 0x%08x\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1147 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1148 | /* pipestat has already been acked */ |
| 1149 | } |
| 1150 | if (eir & I915_ERROR_INSTRUCTION) { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame^] | 1151 | pr_err("instruction error\n"); |
| 1152 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1153 | if (INTEL_INFO(dev)->gen < 4) { |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1154 | u32 ipeir = I915_READ(IPEIR); |
| 1155 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame^] | 1156 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
| 1157 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); |
| 1158 | pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE)); |
| 1159 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1160 | I915_WRITE(IPEIR, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1161 | POSTING_READ(IPEIR); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1162 | } else { |
| 1163 | u32 ipeir = I915_READ(IPEIR_I965); |
| 1164 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame^] | 1165 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
| 1166 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); |
| 1167 | pr_err(" INSTDONE: 0x%08x\n", |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1168 | I915_READ(INSTDONE_I965)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame^] | 1169 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
| 1170 | pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1)); |
| 1171 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1172 | I915_WRITE(IPEIR_I965, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1173 | POSTING_READ(IPEIR_I965); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1174 | } |
| 1175 | } |
| 1176 | |
| 1177 | I915_WRITE(EIR, eir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1178 | POSTING_READ(EIR); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1179 | eir = I915_READ(EIR); |
| 1180 | if (eir) { |
| 1181 | /* |
| 1182 | * some errors might have become stuck, |
| 1183 | * mask them. |
| 1184 | */ |
| 1185 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); |
| 1186 | I915_WRITE(EMR, I915_READ(EMR) | eir); |
| 1187 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 1188 | } |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 1189 | } |
| 1190 | |
| 1191 | /** |
| 1192 | * i915_handle_error - handle an error interrupt |
| 1193 | * @dev: drm device |
| 1194 | * |
| 1195 | * Do some basic checking of regsiter state at error interrupt time and |
| 1196 | * dump it to the syslog. Also call i915_capture_error_state() to make |
| 1197 | * sure we get a record and make it available in debugfs. Fire a uevent |
| 1198 | * so userspace knows something bad happened (should trigger collection |
| 1199 | * of a ring dump etc.). |
| 1200 | */ |
Chris Wilson | 527f9e9 | 2010-11-11 01:16:58 +0000 | [diff] [blame] | 1201 | void i915_handle_error(struct drm_device *dev, bool wedged) |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 1202 | { |
| 1203 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1204 | |
| 1205 | i915_capture_error_state(dev); |
| 1206 | i915_report_and_clear_eir(dev); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1207 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1208 | if (wedged) { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 1209 | INIT_COMPLETION(dev_priv->error_completion); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1210 | atomic_set(&dev_priv->mm.wedged, 1); |
| 1211 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 1212 | /* |
| 1213 | * Wakeup waiting processes so they don't hang |
| 1214 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1215 | wake_up_all(&dev_priv->ring[RCS].irq_queue); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1216 | if (HAS_BSD(dev)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1217 | wake_up_all(&dev_priv->ring[VCS].irq_queue); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1218 | if (HAS_BLT(dev)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1219 | wake_up_all(&dev_priv->ring[BCS].irq_queue); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 1220 | } |
| 1221 | |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1222 | queue_work(dev_priv->wq, &dev_priv->error_work); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1223 | } |
| 1224 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1225 | static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
| 1226 | { |
| 1227 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1228 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 1229 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1230 | struct drm_i915_gem_object *obj; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1231 | struct intel_unpin_work *work; |
| 1232 | unsigned long flags; |
| 1233 | bool stall_detected; |
| 1234 | |
| 1235 | /* Ignore early vblank irqs */ |
| 1236 | if (intel_crtc == NULL) |
| 1237 | return; |
| 1238 | |
| 1239 | spin_lock_irqsave(&dev->event_lock, flags); |
| 1240 | work = intel_crtc->unpin_work; |
| 1241 | |
| 1242 | if (work == NULL || work->pending || !work->enable_stall_check) { |
| 1243 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ |
| 1244 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 1245 | return; |
| 1246 | } |
| 1247 | |
| 1248 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1249 | obj = work->pending_flip_obj; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1250 | if (INTEL_INFO(dev)->gen >= 4) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1251 | int dspsurf = DSPSURF(intel_crtc->plane); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1252 | stall_detected = I915_READ(dspsurf) == obj->gtt_offset; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1253 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1254 | int dspaddr = DSPADDR(intel_crtc->plane); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1255 | stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 1256 | crtc->y * crtc->fb->pitches[0] + |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1257 | crtc->x * crtc->fb->bits_per_pixel/8); |
| 1258 | } |
| 1259 | |
| 1260 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 1261 | |
| 1262 | if (stall_detected) { |
| 1263 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); |
| 1264 | intel_prepare_page_flip(dev, intel_crtc->plane); |
| 1265 | } |
| 1266 | } |
| 1267 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1268 | static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1269 | { |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1270 | struct drm_device *dev = (struct drm_device *) arg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1271 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1272 | struct drm_i915_master_private *master_priv; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1273 | u32 iir, new_iir; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1274 | u32 pipe_stats[I915_MAX_PIPES]; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1275 | u32 vblank_status; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1276 | int vblank = 0; |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1277 | unsigned long irqflags; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1278 | int irq_received; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1279 | int ret = IRQ_NONE, pipe; |
| 1280 | bool blc_event = false; |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 1281 | |
Eric Anholt | 630681d | 2008-10-06 15:14:12 -0700 | [diff] [blame] | 1282 | atomic_inc(&dev_priv->irq_received); |
| 1283 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1284 | iir = I915_READ(IIR); |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 1285 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1286 | if (INTEL_INFO(dev)->gen >= 4) |
Jesse Barnes | d874bcf | 2010-06-30 13:16:00 -0700 | [diff] [blame] | 1287 | vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS; |
Jesse Barnes | e25e660 | 2010-06-30 13:15:19 -0700 | [diff] [blame] | 1288 | else |
Jesse Barnes | d874bcf | 2010-06-30 13:16:00 -0700 | [diff] [blame] | 1289 | vblank_status = PIPE_VBLANK_INTERRUPT_STATUS; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1290 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1291 | for (;;) { |
| 1292 | irq_received = iir != 0; |
| 1293 | |
| 1294 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 1295 | * have been cleared after the pipestat interrupt was received. |
| 1296 | * It doesn't set the bit in iir again, but it still produces |
| 1297 | * interrupts (for non-MSI). |
| 1298 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1299 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1300 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1301 | i915_handle_error(dev, false); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1302 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1303 | for_each_pipe(pipe) { |
| 1304 | int reg = PIPESTAT(pipe); |
| 1305 | pipe_stats[pipe] = I915_READ(reg); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1306 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1307 | /* |
| 1308 | * Clear the PIPE*STAT regs before the IIR |
| 1309 | */ |
| 1310 | if (pipe_stats[pipe] & 0x8000ffff) { |
| 1311 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 1312 | DRM_DEBUG_DRIVER("pipe %c underrun\n", |
| 1313 | pipe_name(pipe)); |
| 1314 | I915_WRITE(reg, pipe_stats[pipe]); |
| 1315 | irq_received = 1; |
| 1316 | } |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1317 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1318 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1319 | |
| 1320 | if (!irq_received) |
| 1321 | break; |
| 1322 | |
| 1323 | ret = IRQ_HANDLED; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1324 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1325 | /* Consume port. Then clear IIR or we'll miss events */ |
| 1326 | if ((I915_HAS_HOTPLUG(dev)) && |
| 1327 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { |
| 1328 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
| 1329 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 1330 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1331 | hotplug_status); |
| 1332 | if (hotplug_status & dev_priv->hotplug_supported_mask) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1333 | queue_work(dev_priv->wq, |
| 1334 | &dev_priv->hotplug_work); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1335 | |
| 1336 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
| 1337 | I915_READ(PORT_HOTPLUG_STAT); |
| 1338 | } |
| 1339 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1340 | I915_WRITE(IIR, iir); |
| 1341 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 1342 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1343 | if (dev->primary->master) { |
| 1344 | master_priv = dev->primary->master->driver_priv; |
| 1345 | if (master_priv->sarea_priv) |
| 1346 | master_priv->sarea_priv->last_dispatch = |
| 1347 | READ_BREADCRUMB(dev_priv); |
| 1348 | } |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1349 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1350 | if (iir & I915_USER_INTERRUPT) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1351 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 1352 | if (iir & I915_BSD_USER_INTERRUPT) |
| 1353 | notify_ring(dev, &dev_priv->ring[VCS]); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1354 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1355 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1356 | intel_prepare_page_flip(dev, 0); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1357 | if (dev_priv->flip_pending_is_done) |
| 1358 | intel_finish_page_flip_plane(dev, 0); |
| 1359 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1360 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1361 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { |
Jesse Barnes | 70565d0 | 2010-07-01 04:45:43 -0700 | [diff] [blame] | 1362 | intel_prepare_page_flip(dev, 1); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1363 | if (dev_priv->flip_pending_is_done) |
| 1364 | intel_finish_page_flip_plane(dev, 1); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1365 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1366 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1367 | for_each_pipe(pipe) { |
| 1368 | if (pipe_stats[pipe] & vblank_status && |
| 1369 | drm_handle_vblank(dev, pipe)) { |
| 1370 | vblank++; |
| 1371 | if (!dev_priv->flip_pending_is_done) { |
| 1372 | i915_pageflip_stall_check(dev, pipe); |
| 1373 | intel_finish_page_flip(dev, pipe); |
| 1374 | } |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1375 | } |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1376 | |
| 1377 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
| 1378 | blc_event = true; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1379 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1380 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1381 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1382 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 1383 | intel_opregion_asle_intr(dev); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1384 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 1385 | /* With MSI, interrupts are only generated when iir |
| 1386 | * transitions from zero to nonzero. If another bit got |
| 1387 | * set while we were handling the existing iir bits, then |
| 1388 | * we would never get another interrupt. |
| 1389 | * |
| 1390 | * This is fine on non-MSI as well, as if we hit this path |
| 1391 | * we avoid exiting the interrupt handler only to generate |
| 1392 | * another one. |
| 1393 | * |
| 1394 | * Note that for MSI this could cause a stray interrupt report |
| 1395 | * if an interrupt landed in the time between writing IIR and |
| 1396 | * the posting read. This should be rare enough to never |
| 1397 | * trigger the 99% of 100,000 interrupts test for disabling |
| 1398 | * stray interrupts. |
| 1399 | */ |
| 1400 | iir = new_iir; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1401 | } |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1402 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1403 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1404 | } |
| 1405 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 1406 | static int i915_emit_irq(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1407 | { |
| 1408 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1409 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1410 | |
| 1411 | i915_kernel_lost_context(dev); |
| 1412 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 1413 | DRM_DEBUG_DRIVER("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1414 | |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 1415 | dev_priv->counter++; |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 1416 | if (dev_priv->counter > 0x7FFFFFFFUL) |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 1417 | dev_priv->counter = 1; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1418 | if (master_priv->sarea_priv) |
| 1419 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 1420 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1421 | if (BEGIN_LP_RING(4) == 0) { |
| 1422 | OUT_RING(MI_STORE_DWORD_INDEX); |
| 1423 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 1424 | OUT_RING(dev_priv->counter); |
| 1425 | OUT_RING(MI_USER_INTERRUPT); |
| 1426 | ADVANCE_LP_RING(); |
| 1427 | } |
Dave Airlie | bc5f452 | 2007-11-05 12:50:58 +1000 | [diff] [blame] | 1428 | |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 1429 | return dev_priv->counter; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1430 | } |
| 1431 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1432 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1433 | { |
| 1434 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1435 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1436 | int ret = 0; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1437 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1438 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 1439 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1440 | READ_BREADCRUMB(dev_priv)); |
| 1441 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1442 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1443 | if (master_priv->sarea_priv) |
| 1444 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1445 | return 0; |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1446 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1447 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1448 | if (master_priv->sarea_priv) |
| 1449 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1450 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1451 | if (ring->irq_get(ring)) { |
| 1452 | DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ, |
| 1453 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
| 1454 | ring->irq_put(ring); |
Chris Wilson | 5a9a8d1 | 2011-01-23 13:03:24 +0000 | [diff] [blame] | 1455 | } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) |
| 1456 | ret = -EBUSY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1457 | |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1458 | if (ret == -EBUSY) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1459 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1460 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
| 1461 | } |
| 1462 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 1463 | return ret; |
| 1464 | } |
| 1465 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1466 | /* Needs the lock as it touches the ring. |
| 1467 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1468 | int i915_irq_emit(struct drm_device *dev, void *data, |
| 1469 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1470 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1471 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1472 | drm_i915_irq_emit_t *emit = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1473 | int result; |
| 1474 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1475 | if (!dev_priv || !LP_RING(dev_priv)->virtual_start) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1476 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1477 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1478 | } |
Eric Anholt | 299eb93 | 2009-02-24 22:14:12 -0800 | [diff] [blame] | 1479 | |
| 1480 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
| 1481 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 1482 | mutex_lock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1483 | result = i915_emit_irq(dev); |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 1484 | mutex_unlock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1485 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1486 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1487 | DRM_ERROR("copy_to_user\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1488 | return -EFAULT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1489 | } |
| 1490 | |
| 1491 | return 0; |
| 1492 | } |
| 1493 | |
| 1494 | /* Doesn't need the hardware lock. |
| 1495 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1496 | int i915_irq_wait(struct drm_device *dev, void *data, |
| 1497 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1498 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1499 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1500 | drm_i915_irq_wait_t *irqwait = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1501 | |
| 1502 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1503 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1504 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1505 | } |
| 1506 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1507 | return i915_wait_irq(dev, irqwait->irq_seq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1508 | } |
| 1509 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 1510 | /* Called from drm generic code, passed 'crtc' which |
| 1511 | * we use as a pipe index |
| 1512 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1513 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1514 | { |
| 1515 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1516 | unsigned long irqflags; |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 1517 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1518 | if (!i915_pipe_enabled(dev, pipe)) |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 1519 | return -EINVAL; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1520 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1521 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1522 | if (INTEL_INFO(dev)->gen >= 4) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1523 | i915_enable_pipestat(dev_priv, pipe, |
| 1524 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1525 | else |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1526 | i915_enable_pipestat(dev_priv, pipe, |
| 1527 | PIPE_VBLANK_INTERRUPT_ENABLE); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 1528 | |
| 1529 | /* maintain vblank delivery even in deep C-states */ |
| 1530 | if (dev_priv->info->gen == 3) |
| 1531 | I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1532 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 1533 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1534 | return 0; |
| 1535 | } |
| 1536 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1537 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1538 | { |
| 1539 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1540 | unsigned long irqflags; |
| 1541 | |
| 1542 | if (!i915_pipe_enabled(dev, pipe)) |
| 1543 | return -EINVAL; |
| 1544 | |
| 1545 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 1546 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1547 | DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1548 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1549 | |
| 1550 | return 0; |
| 1551 | } |
| 1552 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1553 | static int ivybridge_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1554 | { |
| 1555 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1556 | unsigned long irqflags; |
| 1557 | |
| 1558 | if (!i915_pipe_enabled(dev, pipe)) |
| 1559 | return -EINVAL; |
| 1560 | |
| 1561 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 1562 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? |
| 1563 | DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); |
| 1564 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1565 | |
| 1566 | return 0; |
| 1567 | } |
| 1568 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 1569 | /* Called from drm generic code, passed 'crtc' which |
| 1570 | * we use as a pipe index |
| 1571 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1572 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1573 | { |
| 1574 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1575 | unsigned long irqflags; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1576 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1577 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 1578 | if (dev_priv->info->gen == 3) |
| 1579 | I915_WRITE(INSTPM, |
| 1580 | INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS); |
| 1581 | |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1582 | i915_disable_pipestat(dev_priv, pipe, |
| 1583 | PIPE_VBLANK_INTERRUPT_ENABLE | |
| 1584 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
| 1585 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1586 | } |
| 1587 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1588 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1589 | { |
| 1590 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1591 | unsigned long irqflags; |
| 1592 | |
| 1593 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 1594 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1595 | DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1596 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1597 | } |
| 1598 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1599 | static void ivybridge_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1600 | { |
| 1601 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1602 | unsigned long irqflags; |
| 1603 | |
| 1604 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 1605 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? |
| 1606 | DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); |
| 1607 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1608 | } |
| 1609 | |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1610 | /* Set the vblank monitor pipe |
| 1611 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1612 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
| 1613 | struct drm_file *file_priv) |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1614 | { |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1615 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1616 | |
| 1617 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1618 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1619 | return -EINVAL; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1620 | } |
| 1621 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | 5b51694 | 2006-10-25 00:08:23 +1000 | [diff] [blame] | 1622 | return 0; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1623 | } |
| 1624 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1625 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
| 1626 | struct drm_file *file_priv) |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1627 | { |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1628 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1629 | drm_i915_vblank_pipe_t *pipe = data; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1630 | |
| 1631 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1632 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1633 | return -EINVAL; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1634 | } |
| 1635 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1636 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1637 | |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1638 | return 0; |
| 1639 | } |
| 1640 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 1641 | /** |
| 1642 | * Schedule buffer swap at given vertical blank. |
| 1643 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1644 | int i915_vblank_swap(struct drm_device *dev, void *data, |
| 1645 | struct drm_file *file_priv) |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 1646 | { |
Eric Anholt | bd95e0a | 2008-11-04 12:01:24 -0800 | [diff] [blame] | 1647 | /* The delayed swap mechanism was fundamentally racy, and has been |
| 1648 | * removed. The model was that the client requested a delayed flip/swap |
| 1649 | * from the kernel, then waited for vblank before continuing to perform |
| 1650 | * rendering. The problem was that the kernel might wake the client |
| 1651 | * up before it dispatched the vblank swap (since the lock has to be |
| 1652 | * held while touching the ringbuffer), in which case the client would |
| 1653 | * clear and start the next frame before the swap occurred, and |
| 1654 | * flicker would occur in addition to likely missing the vblank. |
| 1655 | * |
| 1656 | * In the absence of this ioctl, userland falls back to a correct path |
| 1657 | * of waiting for a vblank, then dispatching the swap on its own. |
| 1658 | * Context switching to userland and back is plenty fast enough for |
| 1659 | * meeting the requirements of vblank swapping. |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1660 | */ |
Eric Anholt | bd95e0a | 2008-11-04 12:01:24 -0800 | [diff] [blame] | 1661 | return -EINVAL; |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 1662 | } |
| 1663 | |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1664 | static u32 |
| 1665 | ring_last_seqno(struct intel_ring_buffer *ring) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1666 | { |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1667 | return list_entry(ring->request_list.prev, |
| 1668 | struct drm_i915_gem_request, list)->seqno; |
| 1669 | } |
| 1670 | |
| 1671 | static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) |
| 1672 | { |
| 1673 | if (list_empty(&ring->request_list) || |
| 1674 | i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) { |
| 1675 | /* Issue a wake-up to catch stuck h/w. */ |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 1676 | if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) { |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1677 | DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n", |
| 1678 | ring->name, |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 1679 | ring->waiting_seqno, |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1680 | ring->get_seqno(ring)); |
| 1681 | wake_up_all(&ring->irq_queue); |
| 1682 | *err = true; |
| 1683 | } |
| 1684 | return true; |
| 1685 | } |
| 1686 | return false; |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1687 | } |
| 1688 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1689 | static bool kick_ring(struct intel_ring_buffer *ring) |
| 1690 | { |
| 1691 | struct drm_device *dev = ring->dev; |
| 1692 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1693 | u32 tmp = I915_READ_CTL(ring); |
| 1694 | if (tmp & RING_WAIT) { |
| 1695 | DRM_ERROR("Kicking stuck wait on %s\n", |
| 1696 | ring->name); |
| 1697 | I915_WRITE_CTL(ring, tmp); |
| 1698 | return true; |
| 1699 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1700 | return false; |
| 1701 | } |
| 1702 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1703 | /** |
| 1704 | * This is called when the chip hasn't reported back with completed |
| 1705 | * batchbuffers in a long time. The first time this is called we simply record |
| 1706 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses |
| 1707 | * again, we assume the chip is wedged and try to fix it. |
| 1708 | */ |
| 1709 | void i915_hangcheck_elapsed(unsigned long data) |
| 1710 | { |
| 1711 | struct drm_device *dev = (struct drm_device *)data; |
| 1712 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 097354e | 2011-11-27 18:58:17 +0100 | [diff] [blame] | 1713 | uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt; |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1714 | bool err = false; |
| 1715 | |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 1716 | if (!i915_enable_hangcheck) |
| 1717 | return; |
| 1718 | |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1719 | /* If all work is done then ACTHD clearly hasn't advanced. */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1720 | if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) && |
| 1721 | i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) && |
| 1722 | i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) { |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1723 | dev_priv->hangcheck_count = 0; |
| 1724 | if (err) |
| 1725 | goto repeat; |
| 1726 | return; |
| 1727 | } |
Eric Anholt | b9201c1 | 2010-01-08 14:25:16 -0800 | [diff] [blame] | 1728 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1729 | if (INTEL_INFO(dev)->gen < 4) { |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1730 | instdone = I915_READ(INSTDONE); |
| 1731 | instdone1 = 0; |
| 1732 | } else { |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1733 | instdone = I915_READ(INSTDONE_I965); |
| 1734 | instdone1 = I915_READ(INSTDONE1); |
| 1735 | } |
Daniel Vetter | 097354e | 2011-11-27 18:58:17 +0100 | [diff] [blame] | 1736 | acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]); |
| 1737 | acthd_bsd = HAS_BSD(dev) ? |
| 1738 | intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0; |
| 1739 | acthd_blt = HAS_BLT(dev) ? |
| 1740 | intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0; |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1741 | |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1742 | if (dev_priv->last_acthd == acthd && |
Daniel Vetter | 097354e | 2011-11-27 18:58:17 +0100 | [diff] [blame] | 1743 | dev_priv->last_acthd_bsd == acthd_bsd && |
| 1744 | dev_priv->last_acthd_blt == acthd_blt && |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1745 | dev_priv->last_instdone == instdone && |
| 1746 | dev_priv->last_instdone1 == instdone1) { |
| 1747 | if (dev_priv->hangcheck_count++ > 1) { |
| 1748 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); |
Daniel Vetter | 653d7be | 2011-12-14 13:57:21 +0100 | [diff] [blame] | 1749 | i915_handle_error(dev, true); |
Chris Wilson | 8c80b59 | 2010-08-08 20:38:12 +0100 | [diff] [blame] | 1750 | |
| 1751 | if (!IS_GEN2(dev)) { |
| 1752 | /* Is the chip hanging on a WAIT_FOR_EVENT? |
| 1753 | * If so we can simply poke the RB_WAIT bit |
| 1754 | * and break the hang. This should work on |
| 1755 | * all but the second generation chipsets. |
| 1756 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1757 | if (kick_ring(&dev_priv->ring[RCS])) |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1758 | goto repeat; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1759 | |
| 1760 | if (HAS_BSD(dev) && |
| 1761 | kick_ring(&dev_priv->ring[VCS])) |
| 1762 | goto repeat; |
| 1763 | |
| 1764 | if (HAS_BLT(dev) && |
| 1765 | kick_ring(&dev_priv->ring[BCS])) |
| 1766 | goto repeat; |
Chris Wilson | 8c80b59 | 2010-08-08 20:38:12 +0100 | [diff] [blame] | 1767 | } |
| 1768 | |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1769 | return; |
| 1770 | } |
| 1771 | } else { |
| 1772 | dev_priv->hangcheck_count = 0; |
| 1773 | |
| 1774 | dev_priv->last_acthd = acthd; |
Daniel Vetter | 097354e | 2011-11-27 18:58:17 +0100 | [diff] [blame] | 1775 | dev_priv->last_acthd_bsd = acthd_bsd; |
| 1776 | dev_priv->last_acthd_blt = acthd_blt; |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1777 | dev_priv->last_instdone = instdone; |
| 1778 | dev_priv->last_instdone1 = instdone1; |
| 1779 | } |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1780 | |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1781 | repeat: |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1782 | /* Reset timer case chip hangs without another request being added */ |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1783 | mod_timer(&dev_priv->hangcheck_timer, |
| 1784 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1785 | } |
| 1786 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1787 | /* drm_dma.h hooks |
| 1788 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1789 | static void ironlake_irq_preinstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1790 | { |
| 1791 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1792 | |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 1793 | atomic_set(&dev_priv->irq_received, 0); |
| 1794 | |
| 1795 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
| 1796 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
Jesse Barnes | 9e3c256 | 2011-05-18 13:51:43 -0700 | [diff] [blame] | 1797 | if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
| 1798 | INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work); |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 1799 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1800 | I915_WRITE(HWSTAM, 0xeffe); |
Daniel Vetter | bdfcdb6 | 2012-01-05 01:05:26 +0100 | [diff] [blame] | 1801 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1802 | /* XXX hotplug from PCH */ |
| 1803 | |
| 1804 | I915_WRITE(DEIMR, 0xffffffff); |
| 1805 | I915_WRITE(DEIER, 0x0); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1806 | POSTING_READ(DEIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1807 | |
| 1808 | /* and GT */ |
| 1809 | I915_WRITE(GTIMR, 0xffffffff); |
| 1810 | I915_WRITE(GTIER, 0x0); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1811 | POSTING_READ(GTIER); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 1812 | |
| 1813 | /* south display irq */ |
| 1814 | I915_WRITE(SDEIMR, 0xffffffff); |
| 1815 | I915_WRITE(SDEIER, 0x0); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1816 | POSTING_READ(SDEIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1817 | } |
| 1818 | |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 1819 | /* |
| 1820 | * Enable digital hotplug on the PCH, and configure the DP short pulse |
| 1821 | * duration to 2ms (which is the minimum in the Display Port spec) |
| 1822 | * |
| 1823 | * This register is the same on all known PCH chips. |
| 1824 | */ |
| 1825 | |
| 1826 | static void ironlake_enable_pch_hotplug(struct drm_device *dev) |
| 1827 | { |
| 1828 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1829 | u32 hotplug; |
| 1830 | |
| 1831 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
| 1832 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); |
| 1833 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; |
| 1834 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; |
| 1835 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; |
| 1836 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
| 1837 | } |
| 1838 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1839 | static int ironlake_irq_postinstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1840 | { |
| 1841 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1842 | /* enable kind of interrupts always enabled */ |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 1843 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
| 1844 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1845 | u32 render_irqs; |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 1846 | u32 hotplug_mask; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1847 | |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 1848 | DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); |
| 1849 | if (HAS_BSD(dev)) |
| 1850 | DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); |
| 1851 | if (HAS_BLT(dev)) |
| 1852 | DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); |
| 1853 | |
| 1854 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1855 | dev_priv->irq_mask = ~display_mask; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1856 | |
| 1857 | /* should always can generate irq */ |
| 1858 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1859 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
| 1860 | I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1861 | POSTING_READ(DEIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1862 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1863 | dev_priv->gt_irq_mask = ~0; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1864 | |
| 1865 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1866 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1867 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1868 | if (IS_GEN6(dev)) |
| 1869 | render_irqs = |
| 1870 | GT_USER_INTERRUPT | |
| 1871 | GT_GEN6_BSD_USER_INTERRUPT | |
| 1872 | GT_BLT_USER_INTERRUPT; |
| 1873 | else |
| 1874 | render_irqs = |
Chris Wilson | 88f23b8 | 2010-12-05 15:08:31 +0000 | [diff] [blame] | 1875 | GT_USER_INTERRUPT | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1876 | GT_PIPE_NOTIFY | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1877 | GT_BSD_USER_INTERRUPT; |
| 1878 | I915_WRITE(GTIER, render_irqs); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1879 | POSTING_READ(GTIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1880 | |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 1881 | if (HAS_PCH_CPT(dev)) { |
Chris Wilson | 9035a97 | 2011-02-16 09:36:05 +0000 | [diff] [blame] | 1882 | hotplug_mask = (SDE_CRT_HOTPLUG_CPT | |
| 1883 | SDE_PORTB_HOTPLUG_CPT | |
| 1884 | SDE_PORTC_HOTPLUG_CPT | |
| 1885 | SDE_PORTD_HOTPLUG_CPT); |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 1886 | } else { |
Chris Wilson | 9035a97 | 2011-02-16 09:36:05 +0000 | [diff] [blame] | 1887 | hotplug_mask = (SDE_CRT_HOTPLUG | |
| 1888 | SDE_PORTB_HOTPLUG | |
| 1889 | SDE_PORTC_HOTPLUG | |
| 1890 | SDE_PORTD_HOTPLUG | |
| 1891 | SDE_AUX_MASK); |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 1892 | } |
| 1893 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1894 | dev_priv->pch_irq_mask = ~hotplug_mask; |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 1895 | |
| 1896 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1897 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); |
| 1898 | I915_WRITE(SDEIER, hotplug_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1899 | POSTING_READ(SDEIER); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 1900 | |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 1901 | ironlake_enable_pch_hotplug(dev); |
| 1902 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1903 | if (IS_IRONLAKE_M(dev)) { |
| 1904 | /* Clear & enable PCU event interrupts */ |
| 1905 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
| 1906 | I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); |
| 1907 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
| 1908 | } |
| 1909 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1910 | return 0; |
| 1911 | } |
| 1912 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1913 | static int ivybridge_irq_postinstall(struct drm_device *dev) |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1914 | { |
| 1915 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1916 | /* enable kind of interrupts always enabled */ |
| 1917 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | |
| 1918 | DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB | |
| 1919 | DE_PLANEB_FLIP_DONE_IVB; |
| 1920 | u32 render_irqs; |
| 1921 | u32 hotplug_mask; |
| 1922 | |
| 1923 | DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); |
| 1924 | if (HAS_BSD(dev)) |
| 1925 | DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); |
| 1926 | if (HAS_BLT(dev)) |
| 1927 | DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); |
| 1928 | |
| 1929 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
| 1930 | dev_priv->irq_mask = ~display_mask; |
| 1931 | |
| 1932 | /* should always can generate irq */ |
| 1933 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
| 1934 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
| 1935 | I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB | |
| 1936 | DE_PIPEB_VBLANK_IVB); |
| 1937 | POSTING_READ(DEIER); |
| 1938 | |
| 1939 | dev_priv->gt_irq_mask = ~0; |
| 1940 | |
| 1941 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 1942 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 1943 | |
| 1944 | render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT | |
| 1945 | GT_BLT_USER_INTERRUPT; |
| 1946 | I915_WRITE(GTIER, render_irqs); |
| 1947 | POSTING_READ(GTIER); |
| 1948 | |
| 1949 | hotplug_mask = (SDE_CRT_HOTPLUG_CPT | |
| 1950 | SDE_PORTB_HOTPLUG_CPT | |
| 1951 | SDE_PORTC_HOTPLUG_CPT | |
| 1952 | SDE_PORTD_HOTPLUG_CPT); |
| 1953 | dev_priv->pch_irq_mask = ~hotplug_mask; |
| 1954 | |
| 1955 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
| 1956 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); |
| 1957 | I915_WRITE(SDEIER, hotplug_mask); |
| 1958 | POSTING_READ(SDEIER); |
| 1959 | |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 1960 | ironlake_enable_pch_hotplug(dev); |
| 1961 | |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1962 | return 0; |
| 1963 | } |
| 1964 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1965 | static void i915_driver_irq_preinstall(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1966 | { |
| 1967 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1968 | int pipe; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1969 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1970 | atomic_set(&dev_priv->irq_received, 0); |
| 1971 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1972 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1973 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1974 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1975 | if (I915_HAS_HOTPLUG(dev)) { |
| 1976 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 1977 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 1978 | } |
| 1979 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1980 | I915_WRITE(HWSTAM, 0xeffe); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1981 | for_each_pipe(pipe) |
| 1982 | I915_WRITE(PIPESTAT(pipe), 0); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1983 | I915_WRITE(IMR, 0xffffffff); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1984 | I915_WRITE(IER, 0x0); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1985 | POSTING_READ(IER); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1986 | } |
| 1987 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 1988 | /* |
| 1989 | * Must be called after intel_modeset_init or hotplug interrupts won't be |
| 1990 | * enabled correctly. |
| 1991 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1992 | static int i915_driver_irq_postinstall(struct drm_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1993 | { |
| 1994 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1995 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1996 | u32 error_mask; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1997 | |
| 1998 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1999 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 2000 | /* Unmask the interrupts that we always want on. */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2001 | dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX; |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 2002 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 2003 | dev_priv->pipestat[0] = 0; |
| 2004 | dev_priv->pipestat[1] = 0; |
| 2005 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 2006 | if (I915_HAS_HOTPLUG(dev)) { |
Adam Jackson | c496fa1 | 2010-05-27 17:26:45 -0400 | [diff] [blame] | 2007 | /* Enable in IER... */ |
| 2008 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; |
| 2009 | /* and unmask in IMR */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2010 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; |
Adam Jackson | c496fa1 | 2010-05-27 17:26:45 -0400 | [diff] [blame] | 2011 | } |
| 2012 | |
| 2013 | /* |
| 2014 | * Enable some error detection, note the instruction error mask |
| 2015 | * bit is reserved, so we leave it masked. |
| 2016 | */ |
| 2017 | if (IS_G4X(dev)) { |
| 2018 | error_mask = ~(GM45_ERROR_PAGE_TABLE | |
| 2019 | GM45_ERROR_MEM_PRIV | |
| 2020 | GM45_ERROR_CP_PRIV | |
| 2021 | I915_ERROR_MEMORY_REFRESH); |
| 2022 | } else { |
| 2023 | error_mask = ~(I915_ERROR_PAGE_TABLE | |
| 2024 | I915_ERROR_MEMORY_REFRESH); |
| 2025 | } |
| 2026 | I915_WRITE(EMR, error_mask); |
| 2027 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2028 | I915_WRITE(IMR, dev_priv->irq_mask); |
Adam Jackson | c496fa1 | 2010-05-27 17:26:45 -0400 | [diff] [blame] | 2029 | I915_WRITE(IER, enable_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2030 | POSTING_READ(IER); |
Adam Jackson | c496fa1 | 2010-05-27 17:26:45 -0400 | [diff] [blame] | 2031 | |
| 2032 | if (I915_HAS_HOTPLUG(dev)) { |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 2033 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
| 2034 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2035 | /* Note HDMI and DP share bits */ |
| 2036 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) |
| 2037 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; |
| 2038 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) |
| 2039 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; |
| 2040 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) |
| 2041 | hotplug_en |= HDMID_HOTPLUG_INT_EN; |
| 2042 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) |
| 2043 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; |
| 2044 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) |
| 2045 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; |
Andy Lutomirski | 2d1c975 | 2010-06-12 05:21:18 -0400 | [diff] [blame] | 2046 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2047 | hotplug_en |= CRT_HOTPLUG_INT_EN; |
Andy Lutomirski | 2d1c975 | 2010-06-12 05:21:18 -0400 | [diff] [blame] | 2048 | |
| 2049 | /* Programming the CRT detection parameters tends |
| 2050 | to generate a spurious hotplug event about three |
| 2051 | seconds later. So just do it once. |
| 2052 | */ |
| 2053 | if (IS_G4X(dev)) |
| 2054 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; |
| 2055 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
| 2056 | } |
| 2057 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2058 | /* Ignore TV since it's buggy */ |
| 2059 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 2060 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 2061 | } |
| 2062 | |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 2063 | intel_opregion_enable_asle(dev); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2064 | |
| 2065 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2066 | } |
| 2067 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2068 | static void ironlake_irq_uninstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2069 | { |
| 2070 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 2071 | |
| 2072 | if (!dev_priv) |
| 2073 | return; |
| 2074 | |
| 2075 | dev_priv->vblank_pipe = 0; |
| 2076 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2077 | I915_WRITE(HWSTAM, 0xffffffff); |
| 2078 | |
| 2079 | I915_WRITE(DEIMR, 0xffffffff); |
| 2080 | I915_WRITE(DEIER, 0x0); |
| 2081 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
| 2082 | |
| 2083 | I915_WRITE(GTIMR, 0xffffffff); |
| 2084 | I915_WRITE(GTIER, 0x0); |
| 2085 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
Keith Packard | 192aac1f | 2011-09-20 10:12:44 -0700 | [diff] [blame] | 2086 | |
| 2087 | I915_WRITE(SDEIMR, 0xffffffff); |
| 2088 | I915_WRITE(SDEIER, 0x0); |
| 2089 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2090 | } |
| 2091 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2092 | static void i915_driver_irq_uninstall(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2093 | { |
| 2094 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2095 | int pipe; |
Dave Airlie | 91e3738 | 2006-02-18 15:17:04 +1100 | [diff] [blame] | 2096 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2097 | if (!dev_priv) |
| 2098 | return; |
| 2099 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2100 | dev_priv->vblank_pipe = 0; |
| 2101 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 2102 | if (I915_HAS_HOTPLUG(dev)) { |
| 2103 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2104 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 2105 | } |
| 2106 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2107 | I915_WRITE(HWSTAM, 0xffffffff); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2108 | for_each_pipe(pipe) |
| 2109 | I915_WRITE(PIPESTAT(pipe), 0); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2110 | I915_WRITE(IMR, 0xffffffff); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 2111 | I915_WRITE(IER, 0x0); |
Dave Airlie | 91e3738 | 2006-02-18 15:17:04 +1100 | [diff] [blame] | 2112 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2113 | for_each_pipe(pipe) |
| 2114 | I915_WRITE(PIPESTAT(pipe), |
| 2115 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 2116 | I915_WRITE(IIR, I915_READ(IIR)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2117 | } |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2118 | |
| 2119 | void intel_irq_init(struct drm_device *dev) |
| 2120 | { |
| 2121 | dev->driver->get_vblank_counter = i915_get_vblank_counter; |
| 2122 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ |
| 2123 | if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { |
| 2124 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
| 2125 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; |
| 2126 | } |
| 2127 | |
Keith Packard | c3613de | 2011-08-12 17:05:54 -0700 | [diff] [blame] | 2128 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 2129 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
| 2130 | else |
| 2131 | dev->driver->get_vblank_timestamp = NULL; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2132 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
| 2133 | |
| 2134 | if (IS_IVYBRIDGE(dev)) { |
| 2135 | /* Share pre & uninstall handlers with ILK/SNB */ |
| 2136 | dev->driver->irq_handler = ivybridge_irq_handler; |
| 2137 | dev->driver->irq_preinstall = ironlake_irq_preinstall; |
| 2138 | dev->driver->irq_postinstall = ivybridge_irq_postinstall; |
| 2139 | dev->driver->irq_uninstall = ironlake_irq_uninstall; |
| 2140 | dev->driver->enable_vblank = ivybridge_enable_vblank; |
| 2141 | dev->driver->disable_vblank = ivybridge_disable_vblank; |
| 2142 | } else if (HAS_PCH_SPLIT(dev)) { |
| 2143 | dev->driver->irq_handler = ironlake_irq_handler; |
| 2144 | dev->driver->irq_preinstall = ironlake_irq_preinstall; |
| 2145 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
| 2146 | dev->driver->irq_uninstall = ironlake_irq_uninstall; |
| 2147 | dev->driver->enable_vblank = ironlake_enable_vblank; |
| 2148 | dev->driver->disable_vblank = ironlake_disable_vblank; |
| 2149 | } else { |
| 2150 | dev->driver->irq_preinstall = i915_driver_irq_preinstall; |
| 2151 | dev->driver->irq_postinstall = i915_driver_irq_postinstall; |
| 2152 | dev->driver->irq_uninstall = i915_driver_irq_uninstall; |
| 2153 | dev->driver->irq_handler = i915_driver_irq_handler; |
| 2154 | dev->driver->enable_vblank = i915_enable_vblank; |
| 2155 | dev->driver->disable_vblank = i915_disable_vblank; |
| 2156 | } |
| 2157 | } |