Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 34 | #include <linux/shmem_fs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 35 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 36 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 37 | #include <linux/pci.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 38 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 39 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
| 41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 42 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
| 43 | unsigned alignment, |
| 44 | bool map_and_fenceable); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 45 | static void i915_gem_clear_fence_reg(struct drm_device *dev, |
| 46 | struct drm_i915_fence_reg *reg); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 47 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
| 48 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 49 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 50 | struct drm_file *file); |
| 51 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 52 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 53 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 54 | struct shrink_control *sc); |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 55 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 56 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 57 | /* some bookkeeping */ |
| 58 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 59 | size_t size) |
| 60 | { |
| 61 | dev_priv->mm.object_count++; |
| 62 | dev_priv->mm.object_memory += size; |
| 63 | } |
| 64 | |
| 65 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 66 | size_t size) |
| 67 | { |
| 68 | dev_priv->mm.object_count--; |
| 69 | dev_priv->mm.object_memory -= size; |
| 70 | } |
| 71 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 72 | static int |
| 73 | i915_gem_wait_for_error(struct drm_device *dev) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 74 | { |
| 75 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 76 | struct completion *x = &dev_priv->error_completion; |
| 77 | unsigned long flags; |
| 78 | int ret; |
| 79 | |
| 80 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 81 | return 0; |
| 82 | |
| 83 | ret = wait_for_completion_interruptible(x); |
| 84 | if (ret) |
| 85 | return ret; |
| 86 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 87 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 88 | /* GPU is hung, bump the completion count to account for |
| 89 | * the token we just consumed so that we never hit zero and |
| 90 | * end up waiting upon a subsequent completion event that |
| 91 | * will never happen. |
| 92 | */ |
| 93 | spin_lock_irqsave(&x->wait.lock, flags); |
| 94 | x->done++; |
| 95 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 96 | } |
| 97 | return 0; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 98 | } |
| 99 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 100 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 101 | { |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 102 | int ret; |
| 103 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 104 | ret = i915_gem_wait_for_error(dev); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 105 | if (ret) |
| 106 | return ret; |
| 107 | |
| 108 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 109 | if (ret) |
| 110 | return ret; |
| 111 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 112 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 113 | return 0; |
| 114 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 115 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 116 | static inline bool |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 117 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 118 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 119 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 120 | } |
| 121 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 122 | int |
| 123 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 124 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 125 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 126 | struct drm_i915_gem_init *args = data; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 127 | |
| 128 | if (args->gtt_start >= args->gtt_end || |
| 129 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) |
| 130 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 131 | |
Daniel Vetter | f534bc0 | 2012-03-26 22:37:04 +0200 | [diff] [blame^] | 132 | /* GEM with user mode setting was never supported on ilk and later. */ |
| 133 | if (INTEL_INFO(dev)->gen >= 5) |
| 134 | return -ENODEV; |
| 135 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 136 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 137 | i915_gem_init_global_gtt(dev, args->gtt_start, |
| 138 | args->gtt_end, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 139 | mutex_unlock(&dev->struct_mutex); |
| 140 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 141 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 142 | } |
| 143 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 144 | int |
| 145 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 146 | struct drm_file *file) |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 147 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 148 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 149 | struct drm_i915_gem_get_aperture *args = data; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 150 | struct drm_i915_gem_object *obj; |
| 151 | size_t pinned; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 152 | |
| 153 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 154 | return -ENODEV; |
| 155 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 156 | pinned = 0; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 157 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 158 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
| 159 | pinned += obj->gtt_space->size; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 160 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 161 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 162 | args->aper_size = dev_priv->mm.gtt_total; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 163 | args->aper_available_size = args->aper_size - pinned; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 164 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 165 | return 0; |
| 166 | } |
| 167 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 168 | static int |
| 169 | i915_gem_create(struct drm_file *file, |
| 170 | struct drm_device *dev, |
| 171 | uint64_t size, |
| 172 | uint32_t *handle_p) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 173 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 174 | struct drm_i915_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 175 | int ret; |
| 176 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 177 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 178 | size = roundup(size, PAGE_SIZE); |
Chris Wilson | 8ffc024 | 2011-09-14 14:14:28 +0200 | [diff] [blame] | 179 | if (size == 0) |
| 180 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 181 | |
| 182 | /* Allocate the new object */ |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 183 | obj = i915_gem_alloc_object(dev, size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 184 | if (obj == NULL) |
| 185 | return -ENOMEM; |
| 186 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 187 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 188 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 189 | drm_gem_object_release(&obj->base); |
| 190 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 191 | kfree(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 192 | return ret; |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 193 | } |
| 194 | |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 195 | /* drop reference from allocate - handle holds it now */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 196 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 197 | trace_i915_gem_object_create(obj); |
| 198 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 199 | *handle_p = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 200 | return 0; |
| 201 | } |
| 202 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 203 | int |
| 204 | i915_gem_dumb_create(struct drm_file *file, |
| 205 | struct drm_device *dev, |
| 206 | struct drm_mode_create_dumb *args) |
| 207 | { |
| 208 | /* have to work out size/pitch and return them */ |
Chris Wilson | ed0291f | 2011-03-19 08:21:45 +0000 | [diff] [blame] | 209 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 210 | args->size = args->pitch * args->height; |
| 211 | return i915_gem_create(file, dev, |
| 212 | args->size, &args->handle); |
| 213 | } |
| 214 | |
| 215 | int i915_gem_dumb_destroy(struct drm_file *file, |
| 216 | struct drm_device *dev, |
| 217 | uint32_t handle) |
| 218 | { |
| 219 | return drm_gem_handle_delete(file, handle); |
| 220 | } |
| 221 | |
| 222 | /** |
| 223 | * Creates a new mm object and returns a handle to it. |
| 224 | */ |
| 225 | int |
| 226 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 227 | struct drm_file *file) |
| 228 | { |
| 229 | struct drm_i915_gem_create *args = data; |
| 230 | return i915_gem_create(file, dev, |
| 231 | args->size, &args->handle); |
| 232 | } |
| 233 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 234 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 235 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 236 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 237 | |
| 238 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 239 | obj->tiling_mode != I915_TILING_NONE; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 240 | } |
| 241 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 242 | static inline int |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 243 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
| 244 | const char *gpu_vaddr, int gpu_offset, |
| 245 | int length) |
| 246 | { |
| 247 | int ret, cpu_offset = 0; |
| 248 | |
| 249 | while (length > 0) { |
| 250 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 251 | int this_length = min(cacheline_end - gpu_offset, length); |
| 252 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 253 | |
| 254 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
| 255 | gpu_vaddr + swizzled_gpu_offset, |
| 256 | this_length); |
| 257 | if (ret) |
| 258 | return ret + length; |
| 259 | |
| 260 | cpu_offset += this_length; |
| 261 | gpu_offset += this_length; |
| 262 | length -= this_length; |
| 263 | } |
| 264 | |
| 265 | return 0; |
| 266 | } |
| 267 | |
| 268 | static inline int |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 269 | __copy_from_user_swizzled(char __user *gpu_vaddr, int gpu_offset, |
| 270 | const char *cpu_vaddr, |
| 271 | int length) |
| 272 | { |
| 273 | int ret, cpu_offset = 0; |
| 274 | |
| 275 | while (length > 0) { |
| 276 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 277 | int this_length = min(cacheline_end - gpu_offset, length); |
| 278 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 279 | |
| 280 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
| 281 | cpu_vaddr + cpu_offset, |
| 282 | this_length); |
| 283 | if (ret) |
| 284 | return ret + length; |
| 285 | |
| 286 | cpu_offset += this_length; |
| 287 | gpu_offset += this_length; |
| 288 | length -= this_length; |
| 289 | } |
| 290 | |
| 291 | return 0; |
| 292 | } |
| 293 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 294 | /* Per-page copy function for the shmem pread fastpath. |
| 295 | * Flushes invalid cachelines before reading the target if |
| 296 | * needs_clflush is set. */ |
| 297 | static int |
| 298 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
| 299 | char __user *user_data, |
| 300 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 301 | { |
| 302 | char *vaddr; |
| 303 | int ret; |
| 304 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 305 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 306 | return -EINVAL; |
| 307 | |
| 308 | vaddr = kmap_atomic(page); |
| 309 | if (needs_clflush) |
| 310 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 311 | page_length); |
| 312 | ret = __copy_to_user_inatomic(user_data, |
| 313 | vaddr + shmem_page_offset, |
| 314 | page_length); |
| 315 | kunmap_atomic(vaddr); |
| 316 | |
| 317 | return ret; |
| 318 | } |
| 319 | |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 320 | static void |
| 321 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
| 322 | bool swizzled) |
| 323 | { |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 324 | if (unlikely(swizzled)) { |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 325 | unsigned long start = (unsigned long) addr; |
| 326 | unsigned long end = (unsigned long) addr + length; |
| 327 | |
| 328 | /* For swizzling simply ensure that we always flush both |
| 329 | * channels. Lame, but simple and it works. Swizzled |
| 330 | * pwrite/pread is far from a hotpath - current userspace |
| 331 | * doesn't use it at all. */ |
| 332 | start = round_down(start, 128); |
| 333 | end = round_up(end, 128); |
| 334 | |
| 335 | drm_clflush_virt_range((void *)start, end - start); |
| 336 | } else { |
| 337 | drm_clflush_virt_range(addr, length); |
| 338 | } |
| 339 | |
| 340 | } |
| 341 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 342 | /* Only difference to the fast-path function is that this can handle bit17 |
| 343 | * and uses non-atomic copy and kmap functions. */ |
| 344 | static int |
| 345 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
| 346 | char __user *user_data, |
| 347 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 348 | { |
| 349 | char *vaddr; |
| 350 | int ret; |
| 351 | |
| 352 | vaddr = kmap(page); |
| 353 | if (needs_clflush) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 354 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 355 | page_length, |
| 356 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 357 | |
| 358 | if (page_do_bit17_swizzling) |
| 359 | ret = __copy_to_user_swizzled(user_data, |
| 360 | vaddr, shmem_page_offset, |
| 361 | page_length); |
| 362 | else |
| 363 | ret = __copy_to_user(user_data, |
| 364 | vaddr + shmem_page_offset, |
| 365 | page_length); |
| 366 | kunmap(page); |
| 367 | |
| 368 | return ret; |
| 369 | } |
| 370 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 371 | static int |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 372 | i915_gem_shmem_pread(struct drm_device *dev, |
| 373 | struct drm_i915_gem_object *obj, |
| 374 | struct drm_i915_gem_pread *args, |
| 375 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 376 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 377 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 378 | char __user *user_data; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 379 | ssize_t remain; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 380 | loff_t offset; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 381 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 382 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 383 | int hit_slowpath = 0; |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 384 | int prefaulted = 0; |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 385 | int needs_clflush = 0; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 386 | int release_page; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 387 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 388 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 389 | remain = args->size; |
| 390 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 391 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 392 | |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 393 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
| 394 | /* If we're not in the cpu read domain, set ourself into the gtt |
| 395 | * read domain and manually flush cachelines (if required). This |
| 396 | * optimizes for the case when the gpu will dirty the data |
| 397 | * anyway again before the next pread happens. */ |
| 398 | if (obj->cache_level == I915_CACHE_NONE) |
| 399 | needs_clflush = 1; |
| 400 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
| 401 | if (ret) |
| 402 | return ret; |
| 403 | } |
| 404 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 405 | offset = args->offset; |
| 406 | |
| 407 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 408 | struct page *page; |
| 409 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 410 | /* Operation in this page |
| 411 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 412 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 413 | * page_length = bytes to copy for this page |
| 414 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 415 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 416 | page_length = remain; |
| 417 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 418 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 419 | |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 420 | if (obj->pages) { |
| 421 | page = obj->pages[offset >> PAGE_SHIFT]; |
| 422 | release_page = 0; |
| 423 | } else { |
| 424 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
| 425 | if (IS_ERR(page)) { |
| 426 | ret = PTR_ERR(page); |
| 427 | goto out; |
| 428 | } |
| 429 | release_page = 1; |
Jesper Juhl | b65552f | 2011-06-12 20:53:44 +0000 | [diff] [blame] | 430 | } |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 431 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 432 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 433 | (page_to_phys(page) & (1 << 17)) != 0; |
| 434 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 435 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
| 436 | user_data, page_do_bit17_swizzling, |
| 437 | needs_clflush); |
| 438 | if (ret == 0) |
| 439 | goto next_page; |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 440 | |
| 441 | hit_slowpath = 1; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 442 | page_cache_get(page); |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 443 | mutex_unlock(&dev->struct_mutex); |
| 444 | |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 445 | if (!prefaulted) { |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 446 | ret = fault_in_multipages_writeable(user_data, remain); |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 447 | /* Userspace is tricking us, but we've already clobbered |
| 448 | * its pages with the prefault and promised to write the |
| 449 | * data up to the first fault. Hence ignore any errors |
| 450 | * and just continue. */ |
| 451 | (void)ret; |
| 452 | prefaulted = 1; |
| 453 | } |
| 454 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 455 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
| 456 | user_data, page_do_bit17_swizzling, |
| 457 | needs_clflush); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 458 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 459 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 460 | page_cache_release(page); |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 461 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 462 | mark_page_accessed(page); |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 463 | if (release_page) |
| 464 | page_cache_release(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 465 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 466 | if (ret) { |
| 467 | ret = -EFAULT; |
| 468 | goto out; |
| 469 | } |
| 470 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 471 | remain -= page_length; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 472 | user_data += page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 473 | offset += page_length; |
| 474 | } |
| 475 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 476 | out: |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 477 | if (hit_slowpath) { |
| 478 | /* Fixup: Kill any reinstated backing storage pages */ |
| 479 | if (obj->madv == __I915_MADV_PURGED) |
| 480 | i915_gem_object_truncate(obj); |
| 481 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 482 | |
| 483 | return ret; |
| 484 | } |
| 485 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 486 | /** |
| 487 | * Reads data from the object referenced by handle. |
| 488 | * |
| 489 | * On error, the contents of *data are undefined. |
| 490 | */ |
| 491 | int |
| 492 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 493 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 494 | { |
| 495 | struct drm_i915_gem_pread *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 496 | struct drm_i915_gem_object *obj; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 497 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 498 | |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 499 | if (args->size == 0) |
| 500 | return 0; |
| 501 | |
| 502 | if (!access_ok(VERIFY_WRITE, |
| 503 | (char __user *)(uintptr_t)args->data_ptr, |
| 504 | args->size)) |
| 505 | return -EFAULT; |
| 506 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 507 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 508 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 509 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 510 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 511 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 512 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 513 | ret = -ENOENT; |
| 514 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 515 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 516 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 517 | /* Bounds check source. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 518 | if (args->offset > obj->base.size || |
| 519 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 520 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 521 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 522 | } |
| 523 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 524 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
| 525 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 526 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 527 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 528 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 529 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 530 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 531 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 532 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 533 | } |
| 534 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 535 | /* This is the fast write path which cannot handle |
| 536 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 537 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 538 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 539 | static inline int |
| 540 | fast_user_write(struct io_mapping *mapping, |
| 541 | loff_t page_base, int page_offset, |
| 542 | char __user *user_data, |
| 543 | int length) |
| 544 | { |
| 545 | char *vaddr_atomic; |
| 546 | unsigned long unwritten; |
| 547 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 548 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 549 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
| 550 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 551 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 552 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 553 | } |
| 554 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 555 | /** |
| 556 | * This is the fast pwrite path, where we copy the data directly from the |
| 557 | * user into the GTT, uncached. |
| 558 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 559 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 560 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 561 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 562 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 563 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 564 | { |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 565 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 566 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 567 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 568 | char __user *user_data; |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 569 | int page_offset, page_length, ret; |
| 570 | |
| 571 | ret = i915_gem_object_pin(obj, 0, true); |
| 572 | if (ret) |
| 573 | goto out; |
| 574 | |
| 575 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 576 | if (ret) |
| 577 | goto out_unpin; |
| 578 | |
| 579 | ret = i915_gem_object_put_fence(obj); |
| 580 | if (ret) |
| 581 | goto out_unpin; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 582 | |
| 583 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 584 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 585 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 586 | offset = obj->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 587 | |
| 588 | while (remain > 0) { |
| 589 | /* Operation in this page |
| 590 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 591 | * page_base = page offset within aperture |
| 592 | * page_offset = offset within page |
| 593 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 594 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 595 | page_base = offset & PAGE_MASK; |
| 596 | page_offset = offset_in_page(offset); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 597 | page_length = remain; |
| 598 | if ((page_offset + remain) > PAGE_SIZE) |
| 599 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 600 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 601 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 602 | * source page isn't available. Return the error and we'll |
| 603 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 604 | */ |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 605 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 606 | page_offset, user_data, page_length)) { |
| 607 | ret = -EFAULT; |
| 608 | goto out_unpin; |
| 609 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 610 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 611 | remain -= page_length; |
| 612 | user_data += page_length; |
| 613 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 614 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 615 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 616 | out_unpin: |
| 617 | i915_gem_object_unpin(obj); |
| 618 | out: |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 619 | return ret; |
| 620 | } |
| 621 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 622 | /* Per-page copy function for the shmem pwrite fastpath. |
| 623 | * Flushes invalid cachelines before writing to the target if |
| 624 | * needs_clflush_before is set and flushes out any written cachelines after |
| 625 | * writing if needs_clflush is set. */ |
| 626 | static int |
| 627 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
| 628 | char __user *user_data, |
| 629 | bool page_do_bit17_swizzling, |
| 630 | bool needs_clflush_before, |
| 631 | bool needs_clflush_after) |
| 632 | { |
| 633 | char *vaddr; |
| 634 | int ret; |
| 635 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 636 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 637 | return -EINVAL; |
| 638 | |
| 639 | vaddr = kmap_atomic(page); |
| 640 | if (needs_clflush_before) |
| 641 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 642 | page_length); |
| 643 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, |
| 644 | user_data, |
| 645 | page_length); |
| 646 | if (needs_clflush_after) |
| 647 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 648 | page_length); |
| 649 | kunmap_atomic(vaddr); |
| 650 | |
| 651 | return ret; |
| 652 | } |
| 653 | |
| 654 | /* Only difference to the fast-path function is that this can handle bit17 |
| 655 | * and uses non-atomic copy and kmap functions. */ |
| 656 | static int |
| 657 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
| 658 | char __user *user_data, |
| 659 | bool page_do_bit17_swizzling, |
| 660 | bool needs_clflush_before, |
| 661 | bool needs_clflush_after) |
| 662 | { |
| 663 | char *vaddr; |
| 664 | int ret; |
| 665 | |
| 666 | vaddr = kmap(page); |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 667 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 668 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 669 | page_length, |
| 670 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 671 | if (page_do_bit17_swizzling) |
| 672 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
| 673 | user_data, |
| 674 | page_length); |
| 675 | else |
| 676 | ret = __copy_from_user(vaddr + shmem_page_offset, |
| 677 | user_data, |
| 678 | page_length); |
| 679 | if (needs_clflush_after) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 680 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 681 | page_length, |
| 682 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 683 | kunmap(page); |
| 684 | |
| 685 | return ret; |
| 686 | } |
| 687 | |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 688 | static int |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 689 | i915_gem_shmem_pwrite(struct drm_device *dev, |
| 690 | struct drm_i915_gem_object *obj, |
| 691 | struct drm_i915_gem_pwrite *args, |
| 692 | struct drm_file *file) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 693 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 694 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 695 | ssize_t remain; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 696 | loff_t offset; |
| 697 | char __user *user_data; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 698 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 699 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 700 | int hit_slowpath = 0; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 701 | int needs_clflush_after = 0; |
| 702 | int needs_clflush_before = 0; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 703 | int release_page; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 704 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 705 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 706 | remain = args->size; |
| 707 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 708 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 709 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 710 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 711 | /* If we're not in the cpu write domain, set ourself into the gtt |
| 712 | * write domain and manually flush cachelines (if required). This |
| 713 | * optimizes for the case when the gpu will use the data |
| 714 | * right away and we therefore have to clflush anyway. */ |
| 715 | if (obj->cache_level == I915_CACHE_NONE) |
| 716 | needs_clflush_after = 1; |
| 717 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 718 | if (ret) |
| 719 | return ret; |
| 720 | } |
| 721 | /* Same trick applies for invalidate partially written cachelines before |
| 722 | * writing. */ |
| 723 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) |
| 724 | && obj->cache_level == I915_CACHE_NONE) |
| 725 | needs_clflush_before = 1; |
| 726 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 727 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 728 | obj->dirty = 1; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 729 | |
| 730 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 731 | struct page *page; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 732 | int partial_cacheline_write; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 733 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 734 | /* Operation in this page |
| 735 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 736 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 737 | * page_length = bytes to copy for this page |
| 738 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 739 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 740 | |
| 741 | page_length = remain; |
| 742 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 743 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 744 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 745 | /* If we don't overwrite a cacheline completely we need to be |
| 746 | * careful to have up-to-date data by first clflushing. Don't |
| 747 | * overcomplicate things and flush the entire patch. */ |
| 748 | partial_cacheline_write = needs_clflush_before && |
| 749 | ((shmem_page_offset | page_length) |
| 750 | & (boot_cpu_data.x86_clflush_size - 1)); |
| 751 | |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 752 | if (obj->pages) { |
| 753 | page = obj->pages[offset >> PAGE_SHIFT]; |
| 754 | release_page = 0; |
| 755 | } else { |
| 756 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
| 757 | if (IS_ERR(page)) { |
| 758 | ret = PTR_ERR(page); |
| 759 | goto out; |
| 760 | } |
| 761 | release_page = 1; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 762 | } |
| 763 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 764 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 765 | (page_to_phys(page) & (1 << 17)) != 0; |
| 766 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 767 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
| 768 | user_data, page_do_bit17_swizzling, |
| 769 | partial_cacheline_write, |
| 770 | needs_clflush_after); |
| 771 | if (ret == 0) |
| 772 | goto next_page; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 773 | |
| 774 | hit_slowpath = 1; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 775 | page_cache_get(page); |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 776 | mutex_unlock(&dev->struct_mutex); |
| 777 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 778 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
| 779 | user_data, page_do_bit17_swizzling, |
| 780 | partial_cacheline_write, |
| 781 | needs_clflush_after); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 782 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 783 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 784 | page_cache_release(page); |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 785 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 786 | set_page_dirty(page); |
| 787 | mark_page_accessed(page); |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 788 | if (release_page) |
| 789 | page_cache_release(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 790 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 791 | if (ret) { |
| 792 | ret = -EFAULT; |
| 793 | goto out; |
| 794 | } |
| 795 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 796 | remain -= page_length; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 797 | user_data += page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 798 | offset += page_length; |
| 799 | } |
| 800 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 801 | out: |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 802 | if (hit_slowpath) { |
| 803 | /* Fixup: Kill any reinstated backing storage pages */ |
| 804 | if (obj->madv == __I915_MADV_PURGED) |
| 805 | i915_gem_object_truncate(obj); |
| 806 | /* and flush dirty cachelines in case the object isn't in the cpu write |
| 807 | * domain anymore. */ |
| 808 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 809 | i915_gem_clflush_object(obj); |
| 810 | intel_gtt_chipset_flush(); |
| 811 | } |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 812 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 813 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 814 | if (needs_clflush_after) |
| 815 | intel_gtt_chipset_flush(); |
| 816 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 817 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 818 | } |
| 819 | |
| 820 | /** |
| 821 | * Writes data to the object referenced by handle. |
| 822 | * |
| 823 | * On error, the contents of the buffer that were to be modified are undefined. |
| 824 | */ |
| 825 | int |
| 826 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 827 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 828 | { |
| 829 | struct drm_i915_gem_pwrite *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 830 | struct drm_i915_gem_object *obj; |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 831 | int ret; |
| 832 | |
| 833 | if (args->size == 0) |
| 834 | return 0; |
| 835 | |
| 836 | if (!access_ok(VERIFY_READ, |
| 837 | (char __user *)(uintptr_t)args->data_ptr, |
| 838 | args->size)) |
| 839 | return -EFAULT; |
| 840 | |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 841 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
| 842 | args->size); |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 843 | if (ret) |
| 844 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 845 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 846 | ret = i915_mutex_lock_interruptible(dev); |
| 847 | if (ret) |
| 848 | return ret; |
| 849 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 850 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 851 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 852 | ret = -ENOENT; |
| 853 | goto unlock; |
| 854 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 855 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 856 | /* Bounds check destination. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 857 | if (args->offset > obj->base.size || |
| 858 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 859 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 860 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 861 | } |
| 862 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 863 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
| 864 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 865 | ret = -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 866 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 867 | * it would end up going through the fenced access, and we'll get |
| 868 | * different detiling behavior between reading and writing. |
| 869 | * pread/pwrite currently are reading and writing from the CPU |
| 870 | * perspective, requiring manual detiling by the client. |
| 871 | */ |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 872 | if (obj->phys_obj) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 873 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 874 | goto out; |
| 875 | } |
| 876 | |
| 877 | if (obj->gtt_space && |
Daniel Vetter | 3ae5378 | 2012-03-25 19:47:33 +0200 | [diff] [blame] | 878 | obj->cache_level == I915_CACHE_NONE && |
Daniel Vetter | ffc6297 | 2012-03-25 19:47:38 +0200 | [diff] [blame] | 879 | obj->map_and_fenceable && |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 880 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 881 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 882 | /* Note that the gtt paths might fail with non-page-backed user |
| 883 | * pointers (e.g. gtt mappings when moving data between |
| 884 | * textures). Fallback to the shmem path in that case. */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 885 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 886 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 887 | if (ret == -EFAULT) |
| 888 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 889 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 890 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 891 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 892 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 893 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 894 | return ret; |
| 895 | } |
| 896 | |
| 897 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 898 | * Called when user space prepares to use an object with the CPU, either |
| 899 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 900 | */ |
| 901 | int |
| 902 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 903 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 904 | { |
| 905 | struct drm_i915_gem_set_domain *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 906 | struct drm_i915_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 907 | uint32_t read_domains = args->read_domains; |
| 908 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 909 | int ret; |
| 910 | |
| 911 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 912 | return -ENODEV; |
| 913 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 914 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 915 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 916 | return -EINVAL; |
| 917 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 918 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 919 | return -EINVAL; |
| 920 | |
| 921 | /* Having something in the write domain implies it's in the read |
| 922 | * domain, and only that read domain. Enforce that in the request. |
| 923 | */ |
| 924 | if (write_domain != 0 && read_domains != write_domain) |
| 925 | return -EINVAL; |
| 926 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 927 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 928 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 929 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 930 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 931 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 932 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 933 | ret = -ENOENT; |
| 934 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 935 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 936 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 937 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 938 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 939 | |
| 940 | /* Silently promote "you're not bound, there was nothing to do" |
| 941 | * to success, since the client was just asking us to |
| 942 | * make sure everything was done. |
| 943 | */ |
| 944 | if (ret == -EINVAL) |
| 945 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 946 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 947 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 948 | } |
| 949 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 950 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 951 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 952 | mutex_unlock(&dev->struct_mutex); |
| 953 | return ret; |
| 954 | } |
| 955 | |
| 956 | /** |
| 957 | * Called when user space has done writes to this buffer |
| 958 | */ |
| 959 | int |
| 960 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 961 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 962 | { |
| 963 | struct drm_i915_gem_sw_finish *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 964 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 965 | int ret = 0; |
| 966 | |
| 967 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 968 | return -ENODEV; |
| 969 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 970 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 971 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 972 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 973 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 974 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 975 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 976 | ret = -ENOENT; |
| 977 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 978 | } |
| 979 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 980 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 981 | if (obj->pin_count) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 982 | i915_gem_object_flush_cpu_write_domain(obj); |
| 983 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 984 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 985 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 986 | mutex_unlock(&dev->struct_mutex); |
| 987 | return ret; |
| 988 | } |
| 989 | |
| 990 | /** |
| 991 | * Maps the contents of an object, returning the address it is mapped |
| 992 | * into. |
| 993 | * |
| 994 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 995 | * imply a ref on the object itself. |
| 996 | */ |
| 997 | int |
| 998 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 999 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1000 | { |
| 1001 | struct drm_i915_gem_mmap *args = data; |
| 1002 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1003 | unsigned long addr; |
| 1004 | |
| 1005 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1006 | return -ENODEV; |
| 1007 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1008 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1009 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1010 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1011 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1012 | down_write(¤t->mm->mmap_sem); |
| 1013 | addr = do_mmap(obj->filp, 0, args->size, |
| 1014 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1015 | args->offset); |
| 1016 | up_write(¤t->mm->mmap_sem); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1017 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1018 | if (IS_ERR((void *)addr)) |
| 1019 | return addr; |
| 1020 | |
| 1021 | args->addr_ptr = (uint64_t) addr; |
| 1022 | |
| 1023 | return 0; |
| 1024 | } |
| 1025 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1026 | /** |
| 1027 | * i915_gem_fault - fault a page into the GTT |
| 1028 | * vma: VMA in question |
| 1029 | * vmf: fault info |
| 1030 | * |
| 1031 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1032 | * from userspace. The fault handler takes care of binding the object to |
| 1033 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1034 | * only if needed based on whether the old reg is still valid or the object |
| 1035 | * is tiled) and inserting a new PTE into the faulting process. |
| 1036 | * |
| 1037 | * Note that the faulting process may involve evicting existing objects |
| 1038 | * from the GTT and/or fence registers to make room. So performance may |
| 1039 | * suffer if the GTT working set is large or there are few fence registers |
| 1040 | * left. |
| 1041 | */ |
| 1042 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1043 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1044 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1045 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1046 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1047 | pgoff_t page_offset; |
| 1048 | unsigned long pfn; |
| 1049 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1050 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1051 | |
| 1052 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1053 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1054 | PAGE_SHIFT; |
| 1055 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1056 | ret = i915_mutex_lock_interruptible(dev); |
| 1057 | if (ret) |
| 1058 | goto out; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1059 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1060 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
| 1061 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1062 | /* Now bind it into the GTT if needed */ |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 1063 | if (!obj->map_and_fenceable) { |
| 1064 | ret = i915_gem_object_unbind(obj); |
| 1065 | if (ret) |
| 1066 | goto unlock; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1067 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1068 | if (!obj->gtt_space) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1069 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1070 | if (ret) |
| 1071 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1072 | |
Eric Anholt | e92d03b | 2011-06-14 16:43:09 -0700 | [diff] [blame] | 1073 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1074 | if (ret) |
| 1075 | goto unlock; |
| 1076 | } |
Chris Wilson | 4a684a4 | 2010-10-28 14:44:08 +0100 | [diff] [blame] | 1077 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 1078 | if (!obj->has_global_gtt_mapping) |
| 1079 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
| 1080 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1081 | if (obj->tiling_mode == I915_TILING_NONE) |
| 1082 | ret = i915_gem_object_put_fence(obj); |
| 1083 | else |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1084 | ret = i915_gem_object_get_fence(obj, NULL); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1085 | if (ret) |
| 1086 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1087 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1088 | if (i915_gem_object_is_inactive(obj)) |
| 1089 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1090 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1091 | obj->fault_mappable = true; |
| 1092 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1093 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1094 | page_offset; |
| 1095 | |
| 1096 | /* Finally, remap it using the new GTT offset */ |
| 1097 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1098 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1099 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1100 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1101 | switch (ret) { |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1102 | case -EIO: |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1103 | case -EAGAIN: |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1104 | /* Give the error handler a chance to run and move the |
| 1105 | * objects off the GPU active list. Next time we service the |
| 1106 | * fault, we should be able to transition the page into the |
| 1107 | * GTT without touching the GPU (and so avoid further |
| 1108 | * EIO/EGAIN). If the GPU is wedged, then there is no issue |
| 1109 | * with coherency, just lost writes. |
| 1110 | */ |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1111 | set_need_resched(); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1112 | case 0: |
| 1113 | case -ERESTARTSYS: |
Chris Wilson | bed636a | 2011-02-11 20:31:19 +0000 | [diff] [blame] | 1114 | case -EINTR: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1115 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1116 | case -ENOMEM: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1117 | return VM_FAULT_OOM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1118 | default: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1119 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1120 | } |
| 1121 | } |
| 1122 | |
| 1123 | /** |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1124 | * i915_gem_release_mmap - remove physical page mappings |
| 1125 | * @obj: obj in question |
| 1126 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1127 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1128 | * relinquish ownership of the pages back to the system. |
| 1129 | * |
| 1130 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1131 | * object through the GTT and then lose the fence register due to |
| 1132 | * resource pressure. Similarly if the object has been moved out of the |
| 1133 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1134 | * mapping will then trigger a page fault on the next user access, allowing |
| 1135 | * fixup by i915_gem_fault(). |
| 1136 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1137 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1138 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1139 | { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1140 | if (!obj->fault_mappable) |
| 1141 | return; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1142 | |
Chris Wilson | f6e4788 | 2011-03-20 21:09:12 +0000 | [diff] [blame] | 1143 | if (obj->base.dev->dev_mapping) |
| 1144 | unmap_mapping_range(obj->base.dev->dev_mapping, |
| 1145 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, |
| 1146 | obj->base.size, 1); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1147 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1148 | obj->fault_mappable = false; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1149 | } |
| 1150 | |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1151 | static uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1152 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1153 | { |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1154 | uint32_t gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1155 | |
| 1156 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1157 | tiling_mode == I915_TILING_NONE) |
| 1158 | return size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1159 | |
| 1160 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1161 | if (INTEL_INFO(dev)->gen == 3) |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1162 | gtt_size = 1024*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1163 | else |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1164 | gtt_size = 512*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1165 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1166 | while (gtt_size < size) |
| 1167 | gtt_size <<= 1; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1168 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1169 | return gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1170 | } |
| 1171 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1172 | /** |
| 1173 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1174 | * @obj: object to check |
| 1175 | * |
| 1176 | * Return the required GTT alignment for an object, taking into account |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1177 | * potential fence register mapping. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1178 | */ |
| 1179 | static uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1180 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
| 1181 | uint32_t size, |
| 1182 | int tiling_mode) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1183 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1184 | /* |
| 1185 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1186 | * if a fence register is needed for the object. |
| 1187 | */ |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1188 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1189 | tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1190 | return 4096; |
| 1191 | |
| 1192 | /* |
| 1193 | * Previous chips need to be aligned to the size of the smallest |
| 1194 | * fence register that can contain the object. |
| 1195 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1196 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1197 | } |
| 1198 | |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1199 | /** |
| 1200 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an |
| 1201 | * unfenced object |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1202 | * @dev: the device |
| 1203 | * @size: size of the object |
| 1204 | * @tiling_mode: tiling mode of the object |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1205 | * |
| 1206 | * Return the required GTT alignment for an object, only taking into account |
| 1207 | * unfenced tiled surface requirements. |
| 1208 | */ |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 1209 | uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1210 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
| 1211 | uint32_t size, |
| 1212 | int tiling_mode) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1213 | { |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1214 | /* |
| 1215 | * Minimum alignment is 4k (GTT page size) for sane hw. |
| 1216 | */ |
| 1217 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1218 | tiling_mode == I915_TILING_NONE) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1219 | return 4096; |
| 1220 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1221 | /* Previous hardware however needs to be aligned to a power-of-two |
| 1222 | * tile height. The simplest method for determining this is to reuse |
| 1223 | * the power-of-tile object size. |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1224 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1225 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1226 | } |
| 1227 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1228 | int |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1229 | i915_gem_mmap_gtt(struct drm_file *file, |
| 1230 | struct drm_device *dev, |
| 1231 | uint32_t handle, |
| 1232 | uint64_t *offset) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1233 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1234 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1235 | struct drm_i915_gem_object *obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1236 | int ret; |
| 1237 | |
| 1238 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1239 | return -ENODEV; |
| 1240 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1241 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1242 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1243 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1244 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1245 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1246 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1247 | ret = -ENOENT; |
| 1248 | goto unlock; |
| 1249 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1250 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1251 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1252 | ret = -E2BIG; |
Eric Anholt | ff56b0b | 2011-10-31 23:16:21 -0700 | [diff] [blame] | 1253 | goto out; |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1254 | } |
| 1255 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1256 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1257 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1258 | ret = -EINVAL; |
| 1259 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1260 | } |
| 1261 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1262 | if (!obj->base.map_list.map) { |
Rob Clark | b464e9a | 2011-08-10 08:09:08 -0500 | [diff] [blame] | 1263 | ret = drm_gem_create_mmap_offset(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1264 | if (ret) |
| 1265 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1266 | } |
| 1267 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1268 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1269 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1270 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1271 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1272 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1273 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1274 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1275 | } |
| 1276 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1277 | /** |
| 1278 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1279 | * @dev: DRM device |
| 1280 | * @data: GTT mapping ioctl data |
| 1281 | * @file: GEM object info |
| 1282 | * |
| 1283 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1284 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1285 | * up so we can get faults in the handler above. |
| 1286 | * |
| 1287 | * The fault handler will take care of binding the object into the GTT |
| 1288 | * (since it may have been evicted to make room for something), allocating |
| 1289 | * a fence register, and mapping the appropriate aperture address into |
| 1290 | * userspace. |
| 1291 | */ |
| 1292 | int |
| 1293 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1294 | struct drm_file *file) |
| 1295 | { |
| 1296 | struct drm_i915_gem_mmap_gtt *args = data; |
| 1297 | |
| 1298 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1299 | return -ENODEV; |
| 1300 | |
| 1301 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
| 1302 | } |
| 1303 | |
| 1304 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1305 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1306 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1307 | gfp_t gfpmask) |
| 1308 | { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1309 | int page_count, i; |
| 1310 | struct address_space *mapping; |
| 1311 | struct inode *inode; |
| 1312 | struct page *page; |
| 1313 | |
| 1314 | /* Get the list of pages out of our struct file. They'll be pinned |
| 1315 | * at this point until we release them. |
| 1316 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1317 | page_count = obj->base.size / PAGE_SIZE; |
| 1318 | BUG_ON(obj->pages != NULL); |
| 1319 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); |
| 1320 | if (obj->pages == NULL) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1321 | return -ENOMEM; |
| 1322 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1323 | inode = obj->base.filp->f_path.dentry->d_inode; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1324 | mapping = inode->i_mapping; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 1325 | gfpmask |= mapping_gfp_mask(mapping); |
| 1326 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1327 | for (i = 0; i < page_count; i++) { |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 1328 | page = shmem_read_mapping_page_gfp(mapping, i, gfpmask); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1329 | if (IS_ERR(page)) |
| 1330 | goto err_pages; |
| 1331 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1332 | obj->pages[i] = page; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1333 | } |
| 1334 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 1335 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1336 | i915_gem_object_do_bit_17_swizzle(obj); |
| 1337 | |
| 1338 | return 0; |
| 1339 | |
| 1340 | err_pages: |
| 1341 | while (i--) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1342 | page_cache_release(obj->pages[i]); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1343 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1344 | drm_free_large(obj->pages); |
| 1345 | obj->pages = NULL; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1346 | return PTR_ERR(page); |
| 1347 | } |
| 1348 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1349 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1350 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1351 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1352 | int page_count = obj->base.size / PAGE_SIZE; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1353 | int i; |
| 1354 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1355 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1356 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 1357 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1358 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1359 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1360 | if (obj->madv == I915_MADV_DONTNEED) |
| 1361 | obj->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1362 | |
| 1363 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1364 | if (obj->dirty) |
| 1365 | set_page_dirty(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1366 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1367 | if (obj->madv == I915_MADV_WILLNEED) |
| 1368 | mark_page_accessed(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1369 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1370 | page_cache_release(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1371 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1372 | obj->dirty = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1373 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1374 | drm_free_large(obj->pages); |
| 1375 | obj->pages = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1376 | } |
| 1377 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1378 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1379 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1380 | struct intel_ring_buffer *ring, |
| 1381 | u32 seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1382 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1383 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1384 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1385 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1386 | BUG_ON(ring == NULL); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1387 | obj->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1388 | |
| 1389 | /* Add a reference if we're newly entering the active list. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1390 | if (!obj->active) { |
| 1391 | drm_gem_object_reference(&obj->base); |
| 1392 | obj->active = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1393 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1394 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1395 | /* Move from whatever list we were on to the tail of execution. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1396 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
| 1397 | list_move_tail(&obj->ring_list, &ring->active_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1398 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1399 | obj->last_rendering_seqno = seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1400 | if (obj->fenced_gpu_access) { |
| 1401 | struct drm_i915_fence_reg *reg; |
| 1402 | |
| 1403 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); |
| 1404 | |
| 1405 | obj->last_fenced_seqno = seqno; |
| 1406 | obj->last_fenced_ring = ring; |
| 1407 | |
| 1408 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
| 1409 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
| 1410 | } |
| 1411 | } |
| 1412 | |
| 1413 | static void |
| 1414 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) |
| 1415 | { |
| 1416 | list_del_init(&obj->ring_list); |
| 1417 | obj->last_rendering_seqno = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1418 | } |
| 1419 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1420 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1421 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1422 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1423 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1424 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1425 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1426 | BUG_ON(!obj->active); |
| 1427 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1428 | |
| 1429 | i915_gem_object_move_off_active(obj); |
| 1430 | } |
| 1431 | |
| 1432 | static void |
| 1433 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
| 1434 | { |
| 1435 | struct drm_device *dev = obj->base.dev; |
| 1436 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1437 | |
| 1438 | if (obj->pin_count != 0) |
| 1439 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); |
| 1440 | else |
| 1441 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
| 1442 | |
| 1443 | BUG_ON(!list_empty(&obj->gpu_write_list)); |
| 1444 | BUG_ON(!obj->active); |
| 1445 | obj->ring = NULL; |
| 1446 | |
| 1447 | i915_gem_object_move_off_active(obj); |
| 1448 | obj->fenced_gpu_access = false; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1449 | |
| 1450 | obj->active = 0; |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 1451 | obj->pending_gpu_write = false; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1452 | drm_gem_object_unreference(&obj->base); |
| 1453 | |
| 1454 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1455 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1456 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1457 | /* Immediately discard the backing storage */ |
| 1458 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1459 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1460 | { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1461 | struct inode *inode; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1462 | |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1463 | /* Our goal here is to return as much of the memory as |
| 1464 | * is possible back to the system as we are called from OOM. |
| 1465 | * To do this we must instruct the shmfs to drop all of its |
Hugh Dickins | e2377fe | 2011-06-27 16:18:19 -0700 | [diff] [blame] | 1466 | * backing pages, *now*. |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1467 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1468 | inode = obj->base.filp->f_path.dentry->d_inode; |
Hugh Dickins | e2377fe | 2011-06-27 16:18:19 -0700 | [diff] [blame] | 1469 | shmem_truncate_range(inode, 0, (loff_t)-1); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1470 | |
Chris Wilson | a14917e | 2012-02-24 21:13:38 +0000 | [diff] [blame] | 1471 | if (obj->base.map_list.map) |
| 1472 | drm_gem_free_mmap_offset(&obj->base); |
| 1473 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1474 | obj->madv = __I915_MADV_PURGED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1475 | } |
| 1476 | |
| 1477 | static inline int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1478 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1479 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1480 | return obj->madv == I915_MADV_DONTNEED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1481 | } |
| 1482 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1483 | static void |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1484 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
| 1485 | uint32_t flush_domains) |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1486 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1487 | struct drm_i915_gem_object *obj, *next; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1488 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1489 | list_for_each_entry_safe(obj, next, |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 1490 | &ring->gpu_write_list, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1491 | gpu_write_list) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1492 | if (obj->base.write_domain & flush_domains) { |
| 1493 | uint32_t old_write_domain = obj->base.write_domain; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1494 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1495 | obj->base.write_domain = 0; |
| 1496 | list_del_init(&obj->gpu_write_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1497 | i915_gem_object_move_to_active(obj, ring, |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1498 | i915_gem_next_request_seqno(ring)); |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1499 | |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1500 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1501 | obj->base.read_domains, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1502 | old_write_domain); |
| 1503 | } |
| 1504 | } |
| 1505 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1506 | |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1507 | static u32 |
| 1508 | i915_gem_get_seqno(struct drm_device *dev) |
| 1509 | { |
| 1510 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1511 | u32 seqno = dev_priv->next_seqno; |
| 1512 | |
| 1513 | /* reserve 0 for non-seqno */ |
| 1514 | if (++dev_priv->next_seqno == 0) |
| 1515 | dev_priv->next_seqno = 1; |
| 1516 | |
| 1517 | return seqno; |
| 1518 | } |
| 1519 | |
| 1520 | u32 |
| 1521 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) |
| 1522 | { |
| 1523 | if (ring->outstanding_lazy_request == 0) |
| 1524 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); |
| 1525 | |
| 1526 | return ring->outstanding_lazy_request; |
| 1527 | } |
| 1528 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1529 | int |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1530 | i915_add_request(struct intel_ring_buffer *ring, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1531 | struct drm_file *file, |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1532 | struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1533 | { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1534 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1535 | uint32_t seqno; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1536 | u32 request_ring_position; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1537 | int was_empty; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1538 | int ret; |
| 1539 | |
| 1540 | BUG_ON(request == NULL); |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1541 | seqno = i915_gem_next_request_seqno(ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1542 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1543 | /* Record the position of the start of the request so that |
| 1544 | * should we detect the updated seqno part-way through the |
| 1545 | * GPU processing the request, we never over-estimate the |
| 1546 | * position of the head. |
| 1547 | */ |
| 1548 | request_ring_position = intel_ring_get_tail(ring); |
| 1549 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1550 | ret = ring->add_request(ring, &seqno); |
| 1551 | if (ret) |
| 1552 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1553 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1554 | trace_i915_gem_request_add(ring, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1555 | |
| 1556 | request->seqno = seqno; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1557 | request->ring = ring; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1558 | request->tail = request_ring_position; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1559 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1560 | was_empty = list_empty(&ring->request_list); |
| 1561 | list_add_tail(&request->list, &ring->request_list); |
| 1562 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1563 | if (file) { |
| 1564 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 1565 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1566 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1567 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1568 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1569 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1570 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1571 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1572 | |
Daniel Vetter | 5391d0c | 2012-01-25 14:03:57 +0100 | [diff] [blame] | 1573 | ring->outstanding_lazy_request = 0; |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1574 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1575 | if (!dev_priv->mm.suspended) { |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 1576 | if (i915_enable_hangcheck) { |
| 1577 | mod_timer(&dev_priv->hangcheck_timer, |
| 1578 | jiffies + |
| 1579 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
| 1580 | } |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1581 | if (was_empty) |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1582 | queue_delayed_work(dev_priv->wq, |
| 1583 | &dev_priv->mm.retire_work, HZ); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1584 | } |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1585 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1586 | } |
| 1587 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1588 | static inline void |
| 1589 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1590 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1591 | struct drm_i915_file_private *file_priv = request->file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1592 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1593 | if (!file_priv) |
| 1594 | return; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1595 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1596 | spin_lock(&file_priv->mm.lock); |
Herton Ronaldo Krzesinski | 09bfa51 | 2011-03-17 13:45:12 +0000 | [diff] [blame] | 1597 | if (request->file_priv) { |
| 1598 | list_del(&request->client_list); |
| 1599 | request->file_priv = NULL; |
| 1600 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1601 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1602 | } |
| 1603 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1604 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
| 1605 | struct intel_ring_buffer *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1606 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1607 | while (!list_empty(&ring->request_list)) { |
| 1608 | struct drm_i915_gem_request *request; |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1609 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1610 | request = list_first_entry(&ring->request_list, |
| 1611 | struct drm_i915_gem_request, |
| 1612 | list); |
| 1613 | |
| 1614 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1615 | i915_gem_request_remove_from_client(request); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1616 | kfree(request); |
| 1617 | } |
| 1618 | |
| 1619 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1620 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1621 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1622 | obj = list_first_entry(&ring->active_list, |
| 1623 | struct drm_i915_gem_object, |
| 1624 | ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1625 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1626 | obj->base.write_domain = 0; |
| 1627 | list_del_init(&obj->gpu_write_list); |
| 1628 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1629 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1630 | } |
| 1631 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1632 | static void i915_gem_reset_fences(struct drm_device *dev) |
| 1633 | { |
| 1634 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1635 | int i; |
| 1636 | |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 1637 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1638 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 1639 | struct drm_i915_gem_object *obj = reg->obj; |
| 1640 | |
| 1641 | if (!obj) |
| 1642 | continue; |
| 1643 | |
| 1644 | if (obj->tiling_mode) |
| 1645 | i915_gem_release_mmap(obj); |
| 1646 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1647 | reg->obj->fence_reg = I915_FENCE_REG_NONE; |
| 1648 | reg->obj->fenced_gpu_access = false; |
| 1649 | reg->obj->last_fenced_seqno = 0; |
| 1650 | reg->obj->last_fenced_ring = NULL; |
| 1651 | i915_gem_clear_fence_reg(dev, reg); |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1652 | } |
| 1653 | } |
| 1654 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1655 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1656 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1657 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1658 | struct drm_i915_gem_object *obj; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1659 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1660 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1661 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 1662 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1663 | |
| 1664 | /* Remove anything from the flushing lists. The GPU cache is likely |
| 1665 | * to be lost on reset along with the data, so simply move the |
| 1666 | * lost bo to the inactive list. |
| 1667 | */ |
| 1668 | while (!list_empty(&dev_priv->mm.flushing_list)) { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1669 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1670 | struct drm_i915_gem_object, |
| 1671 | mm_list); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1672 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1673 | obj->base.write_domain = 0; |
| 1674 | list_del_init(&obj->gpu_write_list); |
| 1675 | i915_gem_object_move_to_inactive(obj); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1676 | } |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1677 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1678 | /* Move everything out of the GPU domains to ensure we do any |
| 1679 | * necessary invalidation upon reuse. |
| 1680 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1681 | list_for_each_entry(obj, |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1682 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1683 | mm_list) |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1684 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1685 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1686 | } |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1687 | |
| 1688 | /* The fence registers are invalidated so clear them out */ |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1689 | i915_gem_reset_fences(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1690 | } |
| 1691 | |
| 1692 | /** |
| 1693 | * This function clears the request list as sequence numbers are passed. |
| 1694 | */ |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1695 | void |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1696 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1697 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1698 | uint32_t seqno; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1699 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1700 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1701 | if (list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 1702 | return; |
| 1703 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1704 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1705 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1706 | seqno = ring->get_seqno(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1707 | |
Chris Wilson | 076e2c0 | 2011-01-21 10:07:18 +0000 | [diff] [blame] | 1708 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1709 | if (seqno >= ring->sync_seqno[i]) |
| 1710 | ring->sync_seqno[i] = 0; |
| 1711 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1712 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1713 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1714 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1715 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1716 | struct drm_i915_gem_request, |
| 1717 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1718 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1719 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1720 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1721 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1722 | trace_i915_gem_request_retire(ring, request->seqno); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1723 | /* We know the GPU must have read the request to have |
| 1724 | * sent us the seqno + interrupt, so use the position |
| 1725 | * of tail of the request to update the last known position |
| 1726 | * of the GPU head. |
| 1727 | */ |
| 1728 | ring->last_retired_head = request->tail; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1729 | |
| 1730 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1731 | i915_gem_request_remove_from_client(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1732 | kfree(request); |
| 1733 | } |
| 1734 | |
| 1735 | /* Move any buffers on the active list that are no longer referenced |
| 1736 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 1737 | */ |
| 1738 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1739 | struct drm_i915_gem_object *obj; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1740 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1741 | obj = list_first_entry(&ring->active_list, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1742 | struct drm_i915_gem_object, |
| 1743 | ring_list); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1744 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1745 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1746 | break; |
| 1747 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1748 | if (obj->base.write_domain != 0) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1749 | i915_gem_object_move_to_flushing(obj); |
| 1750 | else |
| 1751 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1752 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1753 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1754 | if (unlikely(ring->trace_irq_seqno && |
| 1755 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1756 | ring->irq_put(ring); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1757 | ring->trace_irq_seqno = 0; |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1758 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1759 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1760 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1761 | } |
| 1762 | |
| 1763 | void |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1764 | i915_gem_retire_requests(struct drm_device *dev) |
| 1765 | { |
| 1766 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1767 | int i; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1768 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1769 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1770 | struct drm_i915_gem_object *obj, *next; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1771 | |
| 1772 | /* We must be careful that during unbind() we do not |
| 1773 | * accidentally infinitely recurse into retire requests. |
| 1774 | * Currently: |
| 1775 | * retire -> free -> unbind -> wait -> retire_ring |
| 1776 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1777 | list_for_each_entry_safe(obj, next, |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1778 | &dev_priv->mm.deferred_free_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1779 | mm_list) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1780 | i915_gem_free_object_tail(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1781 | } |
| 1782 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1783 | for (i = 0; i < I915_NUM_RINGS; i++) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1784 | i915_gem_retire_requests_ring(&dev_priv->ring[i]); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1785 | } |
| 1786 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 1787 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1788 | i915_gem_retire_work_handler(struct work_struct *work) |
| 1789 | { |
| 1790 | drm_i915_private_t *dev_priv; |
| 1791 | struct drm_device *dev; |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1792 | bool idle; |
| 1793 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1794 | |
| 1795 | dev_priv = container_of(work, drm_i915_private_t, |
| 1796 | mm.retire_work.work); |
| 1797 | dev = dev_priv->dev; |
| 1798 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 1799 | /* Come back later if the device is busy... */ |
| 1800 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 1801 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 1802 | return; |
| 1803 | } |
| 1804 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1805 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1806 | |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1807 | /* Send a periodic flush down the ring so we don't hold onto GEM |
| 1808 | * objects indefinitely. |
| 1809 | */ |
| 1810 | idle = true; |
| 1811 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 1812 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; |
| 1813 | |
| 1814 | if (!list_empty(&ring->gpu_write_list)) { |
| 1815 | struct drm_i915_gem_request *request; |
| 1816 | int ret; |
| 1817 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1818 | ret = i915_gem_flush_ring(ring, |
| 1819 | 0, I915_GEM_GPU_DOMAINS); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1820 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 1821 | if (ret || request == NULL || |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1822 | i915_add_request(ring, NULL, request)) |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1823 | kfree(request); |
| 1824 | } |
| 1825 | |
| 1826 | idle &= list_empty(&ring->request_list); |
| 1827 | } |
| 1828 | |
| 1829 | if (!dev_priv->mm.suspended && !idle) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1830 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1831 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1832 | mutex_unlock(&dev->struct_mutex); |
| 1833 | } |
| 1834 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1835 | /** |
| 1836 | * Waits for a sequence number to be signaled, and cleans up the |
| 1837 | * request and object lists appropriately for that event. |
| 1838 | */ |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 1839 | int |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1840 | i915_wait_request(struct intel_ring_buffer *ring, |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 1841 | uint32_t seqno, |
| 1842 | bool do_retire) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1843 | { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1844 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1845 | u32 ier; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1846 | int ret = 0; |
| 1847 | |
| 1848 | BUG_ON(seqno == 0); |
| 1849 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1850 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 1851 | struct completion *x = &dev_priv->error_completion; |
| 1852 | bool recovery_complete; |
| 1853 | unsigned long flags; |
| 1854 | |
| 1855 | /* Give the error handler a chance to run. */ |
| 1856 | spin_lock_irqsave(&x->wait.lock, flags); |
| 1857 | recovery_complete = x->done > 0; |
| 1858 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 1859 | |
| 1860 | return recovery_complete ? -EIO : -EAGAIN; |
| 1861 | } |
Ben Gamari | ffed1d0 | 2009-09-14 17:48:41 -0400 | [diff] [blame] | 1862 | |
Chris Wilson | 5d97eb6 | 2010-11-10 20:40:02 +0000 | [diff] [blame] | 1863 | if (seqno == ring->outstanding_lazy_request) { |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1864 | struct drm_i915_gem_request *request; |
| 1865 | |
| 1866 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 1867 | if (request == NULL) |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1868 | return -ENOMEM; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1869 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1870 | ret = i915_add_request(ring, NULL, request); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1871 | if (ret) { |
| 1872 | kfree(request); |
| 1873 | return ret; |
| 1874 | } |
| 1875 | |
| 1876 | seqno = request->seqno; |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1877 | } |
| 1878 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1879 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1880 | if (HAS_PCH_SPLIT(ring->dev)) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1881 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
Jesse Barnes | 23e3f9b | 2012-03-28 13:39:39 -0700 | [diff] [blame] | 1882 | else if (IS_VALLEYVIEW(ring->dev)) |
| 1883 | ier = I915_READ(GTIER) | I915_READ(VLV_IER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1884 | else |
| 1885 | ier = I915_READ(IER); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1886 | if (!ier) { |
| 1887 | DRM_ERROR("something (likely vbetool) disabled " |
| 1888 | "interrupts, re-enabling\n"); |
Chris Wilson | f01c22f | 2011-06-28 11:48:51 +0100 | [diff] [blame] | 1889 | ring->dev->driver->irq_preinstall(ring->dev); |
| 1890 | ring->dev->driver->irq_postinstall(ring->dev); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1891 | } |
| 1892 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1893 | trace_i915_gem_request_wait_begin(ring, seqno); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1894 | |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 1895 | ring->waiting_seqno = seqno; |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1896 | if (ring->irq_get(ring)) { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1897 | if (dev_priv->mm.interruptible) |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1898 | ret = wait_event_interruptible(ring->irq_queue, |
| 1899 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
| 1900 | || atomic_read(&dev_priv->mm.wedged)); |
| 1901 | else |
| 1902 | wait_event(ring->irq_queue, |
| 1903 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
| 1904 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1905 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1906 | ring->irq_put(ring); |
Eric Anholt | e959b5d | 2011-12-22 14:55:01 -0800 | [diff] [blame] | 1907 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
| 1908 | seqno) || |
| 1909 | atomic_read(&dev_priv->mm.wedged), 3000)) |
Chris Wilson | b5ba177 | 2010-12-14 12:17:15 +0000 | [diff] [blame] | 1910 | ret = -EBUSY; |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 1911 | ring->waiting_seqno = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1912 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1913 | trace_i915_gem_request_wait_end(ring, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1914 | } |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1915 | if (atomic_read(&dev_priv->mm.wedged)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 1916 | ret = -EAGAIN; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1917 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1918 | /* Directly dispatch request retiring. While we have the work queue |
| 1919 | * to handle this, the waiter on a request often wants an associated |
| 1920 | * buffer to have made it to the inactive list, and we would need |
| 1921 | * a separate wait queue to handle that. |
| 1922 | */ |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 1923 | if (ret == 0 && do_retire) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1924 | i915_gem_retire_requests_ring(ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1925 | |
| 1926 | return ret; |
| 1927 | } |
| 1928 | |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1929 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1930 | * Ensures that all rendering to the object has completed and the object is |
| 1931 | * safe to unbind from the GTT or access from the CPU. |
| 1932 | */ |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1933 | int |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1934 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1935 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1936 | int ret; |
| 1937 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1938 | /* This function only exists to support waiting for existing rendering, |
| 1939 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1940 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1941 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1942 | |
| 1943 | /* If there is rendering queued on the buffer being evicted, wait for |
| 1944 | * it. |
| 1945 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1946 | if (obj->active) { |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 1947 | ret = i915_wait_request(obj->ring, obj->last_rendering_seqno, |
| 1948 | true); |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 1949 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1950 | return ret; |
| 1951 | } |
| 1952 | |
| 1953 | return 0; |
| 1954 | } |
| 1955 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 1956 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
| 1957 | { |
| 1958 | u32 old_write_domain, old_read_domains; |
| 1959 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 1960 | /* Act a barrier for all accesses through the GTT */ |
| 1961 | mb(); |
| 1962 | |
| 1963 | /* Force a pagefault for domain tracking on next user access */ |
| 1964 | i915_gem_release_mmap(obj); |
| 1965 | |
Keith Packard | b97c3d9 | 2011-06-24 21:02:59 -0700 | [diff] [blame] | 1966 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 1967 | return; |
| 1968 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 1969 | old_read_domains = obj->base.read_domains; |
| 1970 | old_write_domain = obj->base.write_domain; |
| 1971 | |
| 1972 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
| 1973 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
| 1974 | |
| 1975 | trace_i915_gem_object_change_domain(obj, |
| 1976 | old_read_domains, |
| 1977 | old_write_domain); |
| 1978 | } |
| 1979 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1980 | /** |
| 1981 | * Unbinds an object from the GTT aperture. |
| 1982 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1983 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1984 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1985 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 1986 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1987 | int ret = 0; |
| 1988 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1989 | if (obj->gtt_space == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1990 | return 0; |
| 1991 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1992 | if (obj->pin_count != 0) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1993 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
| 1994 | return -EINVAL; |
| 1995 | } |
| 1996 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 1997 | ret = i915_gem_object_finish_gpu(obj); |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 1998 | if (ret == -ERESTARTSYS) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1999 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2000 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2001 | * should be safe and we need to cleanup or else we might |
| 2002 | * cause memory corruption through use-after-free. |
| 2003 | */ |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2004 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2005 | i915_gem_object_finish_gtt(obj); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2006 | |
| 2007 | /* Move the object to the CPU domain to ensure that |
| 2008 | * any possible CPU writes while it's not in the GTT |
| 2009 | * are flushed when we go to remap it. |
| 2010 | */ |
| 2011 | if (ret == 0) |
| 2012 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 2013 | if (ret == -ERESTARTSYS) |
| 2014 | return ret; |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2015 | if (ret) { |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2016 | /* In the event of a disaster, abandon all caches and |
| 2017 | * hope for the best. |
| 2018 | */ |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2019 | i915_gem_clflush_object(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2020 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2021 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2022 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2023 | /* release the fence reg _after_ flushing */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2024 | ret = i915_gem_object_put_fence(obj); |
| 2025 | if (ret == -ERESTARTSYS) |
| 2026 | return ret; |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2027 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2028 | trace_i915_gem_object_unbind(obj); |
| 2029 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 2030 | if (obj->has_global_gtt_mapping) |
| 2031 | i915_gem_gtt_unbind_object(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2032 | if (obj->has_aliasing_ppgtt_mapping) { |
| 2033 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); |
| 2034 | obj->has_aliasing_ppgtt_mapping = 0; |
| 2035 | } |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2036 | i915_gem_gtt_finish_object(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2037 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2038 | i915_gem_object_put_pages_gtt(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2039 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2040 | list_del_init(&obj->gtt_list); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2041 | list_del_init(&obj->mm_list); |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2042 | /* Avoid an unnecessary call to unbind on rebind. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2043 | obj->map_and_fenceable = true; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2044 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2045 | drm_mm_put_block(obj->gtt_space); |
| 2046 | obj->gtt_space = NULL; |
| 2047 | obj->gtt_offset = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2048 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2049 | if (i915_gem_object_is_purgeable(obj)) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2050 | i915_gem_object_truncate(obj); |
| 2051 | |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2052 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2053 | } |
| 2054 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2055 | int |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2056 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2057 | uint32_t invalidate_domains, |
| 2058 | uint32_t flush_domains) |
| 2059 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2060 | int ret; |
| 2061 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 2062 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
| 2063 | return 0; |
| 2064 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2065 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
| 2066 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2067 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
| 2068 | if (ret) |
| 2069 | return ret; |
| 2070 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 2071 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
| 2072 | i915_gem_process_flushing_list(ring, flush_domains); |
| 2073 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2074 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2075 | } |
| 2076 | |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 2077 | static int i915_ring_idle(struct intel_ring_buffer *ring, bool do_retire) |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2078 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2079 | int ret; |
| 2080 | |
Chris Wilson | 395b70b | 2010-10-28 21:28:46 +0100 | [diff] [blame] | 2081 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 2082 | return 0; |
| 2083 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2084 | if (!list_empty(&ring->gpu_write_list)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2085 | ret = i915_gem_flush_ring(ring, |
Chris Wilson | 0ac74c6 | 2010-12-06 14:36:02 +0000 | [diff] [blame] | 2086 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2087 | if (ret) |
| 2088 | return ret; |
| 2089 | } |
| 2090 | |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 2091 | return i915_wait_request(ring, i915_gem_next_request_seqno(ring), |
| 2092 | do_retire); |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2093 | } |
| 2094 | |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 2095 | int i915_gpu_idle(struct drm_device *dev, bool do_retire) |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2096 | { |
| 2097 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2098 | int ret, i; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2099 | |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2100 | /* Flush everything onto the inactive list. */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2101 | for (i = 0; i < I915_NUM_RINGS; i++) { |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 2102 | ret = i915_ring_idle(&dev_priv->ring[i], do_retire); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2103 | if (ret) |
| 2104 | return ret; |
| 2105 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2106 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2107 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2108 | } |
| 2109 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2110 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2111 | struct intel_ring_buffer *pipelined) |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2112 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2113 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2114 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2115 | u32 size = obj->gtt_space->size; |
| 2116 | int regnum = obj->fence_reg; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2117 | uint64_t val; |
| 2118 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2119 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2120 | 0xfffff000) << 32; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2121 | val |= obj->gtt_offset & 0xfffff000; |
| 2122 | val |= (uint64_t)((obj->stride / 128) - 1) << |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2123 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 2124 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2125 | if (obj->tiling_mode == I915_TILING_Y) |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2126 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2127 | val |= I965_FENCE_REG_VALID; |
| 2128 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2129 | if (pipelined) { |
| 2130 | int ret = intel_ring_begin(pipelined, 6); |
| 2131 | if (ret) |
| 2132 | return ret; |
| 2133 | |
| 2134 | intel_ring_emit(pipelined, MI_NOOP); |
| 2135 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); |
| 2136 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); |
| 2137 | intel_ring_emit(pipelined, (u32)val); |
| 2138 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); |
| 2139 | intel_ring_emit(pipelined, (u32)(val >> 32)); |
| 2140 | intel_ring_advance(pipelined); |
| 2141 | } else |
| 2142 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); |
| 2143 | |
| 2144 | return 0; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2145 | } |
| 2146 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2147 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2148 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2149 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2150 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2151 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2152 | u32 size = obj->gtt_space->size; |
| 2153 | int regnum = obj->fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2154 | uint64_t val; |
| 2155 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2156 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2157 | 0xfffff000) << 32; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2158 | val |= obj->gtt_offset & 0xfffff000; |
| 2159 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2160 | if (obj->tiling_mode == I915_TILING_Y) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2161 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2162 | val |= I965_FENCE_REG_VALID; |
| 2163 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2164 | if (pipelined) { |
| 2165 | int ret = intel_ring_begin(pipelined, 6); |
| 2166 | if (ret) |
| 2167 | return ret; |
| 2168 | |
| 2169 | intel_ring_emit(pipelined, MI_NOOP); |
| 2170 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); |
| 2171 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); |
| 2172 | intel_ring_emit(pipelined, (u32)val); |
| 2173 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); |
| 2174 | intel_ring_emit(pipelined, (u32)(val >> 32)); |
| 2175 | intel_ring_advance(pipelined); |
| 2176 | } else |
| 2177 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); |
| 2178 | |
| 2179 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2180 | } |
| 2181 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2182 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2183 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2184 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2185 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2186 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2187 | u32 size = obj->gtt_space->size; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2188 | u32 fence_reg, val, pitch_val; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2189 | int tile_width; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2190 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2191 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2192 | (size & -size) != size || |
| 2193 | (obj->gtt_offset & (size - 1)), |
| 2194 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
| 2195 | obj->gtt_offset, obj->map_and_fenceable, size)) |
| 2196 | return -EINVAL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2197 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2198 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2199 | tile_width = 128; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2200 | else |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2201 | tile_width = 512; |
| 2202 | |
| 2203 | /* Note: pitch better be a power of two tile widths */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2204 | pitch_val = obj->stride / tile_width; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2205 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2206 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2207 | val = obj->gtt_offset; |
| 2208 | if (obj->tiling_mode == I915_TILING_Y) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2209 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2210 | val |= I915_FENCE_SIZE_BITS(size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2211 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2212 | val |= I830_FENCE_REG_VALID; |
| 2213 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2214 | fence_reg = obj->fence_reg; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2215 | if (fence_reg < 8) |
| 2216 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2217 | else |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2218 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2219 | |
| 2220 | if (pipelined) { |
| 2221 | int ret = intel_ring_begin(pipelined, 4); |
| 2222 | if (ret) |
| 2223 | return ret; |
| 2224 | |
| 2225 | intel_ring_emit(pipelined, MI_NOOP); |
| 2226 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); |
| 2227 | intel_ring_emit(pipelined, fence_reg); |
| 2228 | intel_ring_emit(pipelined, val); |
| 2229 | intel_ring_advance(pipelined); |
| 2230 | } else |
| 2231 | I915_WRITE(fence_reg, val); |
| 2232 | |
| 2233 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2234 | } |
| 2235 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2236 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
| 2237 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2238 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2239 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2240 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2241 | u32 size = obj->gtt_space->size; |
| 2242 | int regnum = obj->fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2243 | uint32_t val; |
| 2244 | uint32_t pitch_val; |
| 2245 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2246 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
| 2247 | (size & -size) != size || |
| 2248 | (obj->gtt_offset & (size - 1)), |
| 2249 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", |
| 2250 | obj->gtt_offset, size)) |
| 2251 | return -EINVAL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2252 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2253 | pitch_val = obj->stride / 128; |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2254 | pitch_val = ffs(pitch_val) - 1; |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2255 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2256 | val = obj->gtt_offset; |
| 2257 | if (obj->tiling_mode == I915_TILING_Y) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2258 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2259 | val |= I830_FENCE_SIZE_BITS(size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2260 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2261 | val |= I830_FENCE_REG_VALID; |
| 2262 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2263 | if (pipelined) { |
| 2264 | int ret = intel_ring_begin(pipelined, 4); |
| 2265 | if (ret) |
| 2266 | return ret; |
| 2267 | |
| 2268 | intel_ring_emit(pipelined, MI_NOOP); |
| 2269 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); |
| 2270 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); |
| 2271 | intel_ring_emit(pipelined, val); |
| 2272 | intel_ring_advance(pipelined); |
| 2273 | } else |
| 2274 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); |
| 2275 | |
| 2276 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2277 | } |
| 2278 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2279 | static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 2280 | { |
| 2281 | return i915_seqno_passed(ring->get_seqno(ring), seqno); |
| 2282 | } |
| 2283 | |
| 2284 | static int |
| 2285 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj, |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2286 | struct intel_ring_buffer *pipelined) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2287 | { |
| 2288 | int ret; |
| 2289 | |
| 2290 | if (obj->fenced_gpu_access) { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2291 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2292 | ret = i915_gem_flush_ring(obj->last_fenced_ring, |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2293 | 0, obj->base.write_domain); |
| 2294 | if (ret) |
| 2295 | return ret; |
| 2296 | } |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2297 | |
| 2298 | obj->fenced_gpu_access = false; |
| 2299 | } |
| 2300 | |
| 2301 | if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) { |
| 2302 | if (!ring_passed_seqno(obj->last_fenced_ring, |
| 2303 | obj->last_fenced_seqno)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2304 | ret = i915_wait_request(obj->last_fenced_ring, |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 2305 | obj->last_fenced_seqno, |
| 2306 | true); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2307 | if (ret) |
| 2308 | return ret; |
| 2309 | } |
| 2310 | |
| 2311 | obj->last_fenced_seqno = 0; |
| 2312 | obj->last_fenced_ring = NULL; |
| 2313 | } |
| 2314 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2315 | /* Ensure that all CPU reads are completed before installing a fence |
| 2316 | * and all writes before removing the fence. |
| 2317 | */ |
| 2318 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) |
| 2319 | mb(); |
| 2320 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2321 | return 0; |
| 2322 | } |
| 2323 | |
| 2324 | int |
| 2325 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
| 2326 | { |
| 2327 | int ret; |
| 2328 | |
| 2329 | if (obj->tiling_mode) |
| 2330 | i915_gem_release_mmap(obj); |
| 2331 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2332 | ret = i915_gem_object_flush_fence(obj, NULL); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2333 | if (ret) |
| 2334 | return ret; |
| 2335 | |
| 2336 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2337 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2338 | |
| 2339 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2340 | i915_gem_clear_fence_reg(obj->base.dev, |
| 2341 | &dev_priv->fence_regs[obj->fence_reg]); |
| 2342 | |
| 2343 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 2344 | } |
| 2345 | |
| 2346 | return 0; |
| 2347 | } |
| 2348 | |
| 2349 | static struct drm_i915_fence_reg * |
| 2350 | i915_find_fence_reg(struct drm_device *dev, |
| 2351 | struct intel_ring_buffer *pipelined) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2352 | { |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2353 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2354 | struct drm_i915_fence_reg *reg, *first, *avail; |
| 2355 | int i; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2356 | |
| 2357 | /* First try to find a free reg */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2358 | avail = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2359 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2360 | reg = &dev_priv->fence_regs[i]; |
| 2361 | if (!reg->obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2362 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2363 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2364 | if (!reg->pin_count) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2365 | avail = reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2366 | } |
| 2367 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2368 | if (avail == NULL) |
| 2369 | return NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2370 | |
| 2371 | /* None available, try to steal one or wait for a user to finish */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2372 | avail = first = NULL; |
| 2373 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2374 | if (reg->pin_count) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2375 | continue; |
| 2376 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2377 | if (first == NULL) |
| 2378 | first = reg; |
| 2379 | |
| 2380 | if (!pipelined || |
| 2381 | !reg->obj->last_fenced_ring || |
| 2382 | reg->obj->last_fenced_ring == pipelined) { |
| 2383 | avail = reg; |
| 2384 | break; |
| 2385 | } |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2386 | } |
| 2387 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2388 | if (avail == NULL) |
| 2389 | avail = first; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2390 | |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2391 | return avail; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2392 | } |
| 2393 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2394 | /** |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2395 | * i915_gem_object_get_fence - set up a fence reg for an object |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2396 | * @obj: object to map through a fence reg |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2397 | * @pipelined: ring on which to queue the change, or NULL for CPU access |
| 2398 | * @interruptible: must we wait uninterruptibly for the register to retire? |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2399 | * |
| 2400 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2401 | * to them without having to worry about swizzling if the object is tiled. |
| 2402 | * |
| 2403 | * This function walks the fence regs looking for a free one for @obj, |
| 2404 | * stealing one if it can't find any. |
| 2405 | * |
| 2406 | * It then sets up the reg based on the object's properties: address, pitch |
| 2407 | * and tiling format. |
| 2408 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2409 | int |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2410 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2411 | struct intel_ring_buffer *pipelined) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2412 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2413 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2414 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2415 | struct drm_i915_fence_reg *reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2416 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2417 | |
Chris Wilson | 6bda10d | 2010-12-05 21:04:18 +0000 | [diff] [blame] | 2418 | /* XXX disable pipelining. There are bugs. Shocking. */ |
| 2419 | pipelined = NULL; |
| 2420 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2421 | /* Just update our place in the LRU if our fence is getting reused. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2422 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2423 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2424 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2425 | |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 2426 | if (obj->tiling_changed) { |
| 2427 | ret = i915_gem_object_flush_fence(obj, pipelined); |
| 2428 | if (ret) |
| 2429 | return ret; |
| 2430 | |
| 2431 | if (!obj->fenced_gpu_access && !obj->last_fenced_seqno) |
| 2432 | pipelined = NULL; |
| 2433 | |
| 2434 | if (pipelined) { |
| 2435 | reg->setup_seqno = |
| 2436 | i915_gem_next_request_seqno(pipelined); |
| 2437 | obj->last_fenced_seqno = reg->setup_seqno; |
| 2438 | obj->last_fenced_ring = pipelined; |
| 2439 | } |
| 2440 | |
| 2441 | goto update; |
| 2442 | } |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2443 | |
| 2444 | if (!pipelined) { |
| 2445 | if (reg->setup_seqno) { |
| 2446 | if (!ring_passed_seqno(obj->last_fenced_ring, |
| 2447 | reg->setup_seqno)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2448 | ret = i915_wait_request(obj->last_fenced_ring, |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 2449 | reg->setup_seqno, |
| 2450 | true); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2451 | if (ret) |
| 2452 | return ret; |
| 2453 | } |
| 2454 | |
| 2455 | reg->setup_seqno = 0; |
| 2456 | } |
| 2457 | } else if (obj->last_fenced_ring && |
| 2458 | obj->last_fenced_ring != pipelined) { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2459 | ret = i915_gem_object_flush_fence(obj, pipelined); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2460 | if (ret) |
| 2461 | return ret; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2462 | } |
| 2463 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2464 | return 0; |
| 2465 | } |
| 2466 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2467 | reg = i915_find_fence_reg(dev, pipelined); |
| 2468 | if (reg == NULL) |
Daniel Vetter | 39965b3 | 2011-12-14 13:57:09 +0100 | [diff] [blame] | 2469 | return -EDEADLK; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2470 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2471 | ret = i915_gem_object_flush_fence(obj, pipelined); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2472 | if (ret) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2473 | return ret; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2474 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2475 | if (reg->obj) { |
| 2476 | struct drm_i915_gem_object *old = reg->obj; |
| 2477 | |
| 2478 | drm_gem_object_reference(&old->base); |
| 2479 | |
| 2480 | if (old->tiling_mode) |
| 2481 | i915_gem_release_mmap(old); |
| 2482 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2483 | ret = i915_gem_object_flush_fence(old, pipelined); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2484 | if (ret) { |
| 2485 | drm_gem_object_unreference(&old->base); |
| 2486 | return ret; |
| 2487 | } |
| 2488 | |
| 2489 | if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0) |
| 2490 | pipelined = NULL; |
| 2491 | |
| 2492 | old->fence_reg = I915_FENCE_REG_NONE; |
| 2493 | old->last_fenced_ring = pipelined; |
| 2494 | old->last_fenced_seqno = |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2495 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2496 | |
| 2497 | drm_gem_object_unreference(&old->base); |
| 2498 | } else if (obj->last_fenced_seqno == 0) |
| 2499 | pipelined = NULL; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2500 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2501 | reg->obj = obj; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2502 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
| 2503 | obj->fence_reg = reg - dev_priv->fence_regs; |
| 2504 | obj->last_fenced_ring = pipelined; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2505 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2506 | reg->setup_seqno = |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2507 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2508 | obj->last_fenced_seqno = reg->setup_seqno; |
| 2509 | |
| 2510 | update: |
| 2511 | obj->tiling_changed = false; |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2512 | switch (INTEL_INFO(dev)->gen) { |
Eric Anholt | 25aebfc3 | 2011-05-06 13:55:53 -0700 | [diff] [blame] | 2513 | case 7: |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2514 | case 6: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2515 | ret = sandybridge_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2516 | break; |
| 2517 | case 5: |
| 2518 | case 4: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2519 | ret = i965_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2520 | break; |
| 2521 | case 3: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2522 | ret = i915_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2523 | break; |
| 2524 | case 2: |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2525 | ret = i830_write_fence_reg(obj, pipelined); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2526 | break; |
| 2527 | } |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2528 | |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2529 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2530 | } |
| 2531 | |
| 2532 | /** |
| 2533 | * i915_gem_clear_fence_reg - clear out fence register info |
| 2534 | * @obj: object to clear |
| 2535 | * |
| 2536 | * Zeroes out the fence register itself and clears out the associated |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2537 | * data structures in dev_priv and obj. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2538 | */ |
| 2539 | static void |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2540 | i915_gem_clear_fence_reg(struct drm_device *dev, |
| 2541 | struct drm_i915_fence_reg *reg) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2542 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2543 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2544 | uint32_t fence_reg = reg - dev_priv->fence_regs; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2545 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2546 | switch (INTEL_INFO(dev)->gen) { |
Eric Anholt | 25aebfc3 | 2011-05-06 13:55:53 -0700 | [diff] [blame] | 2547 | case 7: |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2548 | case 6: |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2549 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2550 | break; |
| 2551 | case 5: |
| 2552 | case 4: |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2553 | I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2554 | break; |
| 2555 | case 3: |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2556 | if (fence_reg >= 8) |
| 2557 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2558 | else |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2559 | case 2: |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2560 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2561 | |
| 2562 | I915_WRITE(fence_reg, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2563 | break; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2564 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2565 | |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2566 | list_del_init(®->lru_list); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2567 | reg->obj = NULL; |
| 2568 | reg->setup_seqno = 0; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2569 | reg->pin_count = 0; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2570 | } |
| 2571 | |
| 2572 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2573 | * Finds free space in the GTT aperture and binds the object there. |
| 2574 | */ |
| 2575 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2576 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2577 | unsigned alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2578 | bool map_and_fenceable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2579 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2580 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2581 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2582 | struct drm_mm_node *free_space; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2583 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2584 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2585 | bool mappable, fenceable; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2586 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2587 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2588 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2589 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2590 | return -EINVAL; |
| 2591 | } |
| 2592 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2593 | fence_size = i915_gem_get_gtt_size(dev, |
| 2594 | obj->base.size, |
| 2595 | obj->tiling_mode); |
| 2596 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 2597 | obj->base.size, |
| 2598 | obj->tiling_mode); |
| 2599 | unfenced_alignment = |
| 2600 | i915_gem_get_unfenced_gtt_alignment(dev, |
| 2601 | obj->base.size, |
| 2602 | obj->tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2603 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2604 | if (alignment == 0) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2605 | alignment = map_and_fenceable ? fence_alignment : |
| 2606 | unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2607 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2608 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2609 | return -EINVAL; |
| 2610 | } |
| 2611 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2612 | size = map_and_fenceable ? fence_size : obj->base.size; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2613 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2614 | /* If the object is bigger than the entire aperture, reject it early |
| 2615 | * before evicting everything in a vain attempt to find space. |
| 2616 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2617 | if (obj->base.size > |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2618 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2619 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
| 2620 | return -E2BIG; |
| 2621 | } |
| 2622 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2623 | search_free: |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2624 | if (map_and_fenceable) |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2625 | free_space = |
| 2626 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2627 | size, alignment, 0, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2628 | dev_priv->mm.gtt_mappable_end, |
| 2629 | 0); |
| 2630 | else |
| 2631 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2632 | size, alignment, 0); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2633 | |
| 2634 | if (free_space != NULL) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2635 | if (map_and_fenceable) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2636 | obj->gtt_space = |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2637 | drm_mm_get_block_range_generic(free_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2638 | size, alignment, 0, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2639 | dev_priv->mm.gtt_mappable_end, |
| 2640 | 0); |
| 2641 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2642 | obj->gtt_space = |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2643 | drm_mm_get_block(free_space, size, alignment); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2644 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2645 | if (obj->gtt_space == NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2646 | /* If the gtt is empty and we're still having trouble |
| 2647 | * fitting our object in, we're out of memory. |
| 2648 | */ |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2649 | ret = i915_gem_evict_something(dev, size, alignment, |
| 2650 | map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2651 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2652 | return ret; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2653 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2654 | goto search_free; |
| 2655 | } |
| 2656 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2657 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2658 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2659 | drm_mm_put_block(obj->gtt_space); |
| 2660 | obj->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2661 | |
| 2662 | if (ret == -ENOMEM) { |
Chris Wilson | 809b633 | 2011-01-10 17:33:15 +0000 | [diff] [blame] | 2663 | /* first try to reclaim some memory by clearing the GTT */ |
| 2664 | ret = i915_gem_evict_everything(dev, false); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2665 | if (ret) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2666 | /* now try to shrink everyone else */ |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2667 | if (gfpmask) { |
| 2668 | gfpmask = 0; |
| 2669 | goto search_free; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2670 | } |
| 2671 | |
Chris Wilson | 809b633 | 2011-01-10 17:33:15 +0000 | [diff] [blame] | 2672 | return -ENOMEM; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2673 | } |
| 2674 | |
| 2675 | goto search_free; |
| 2676 | } |
| 2677 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2678 | return ret; |
| 2679 | } |
| 2680 | |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2681 | ret = i915_gem_gtt_prepare_object(obj); |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 2682 | if (ret) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2683 | i915_gem_object_put_pages_gtt(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2684 | drm_mm_put_block(obj->gtt_space); |
| 2685 | obj->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2686 | |
Chris Wilson | 809b633 | 2011-01-10 17:33:15 +0000 | [diff] [blame] | 2687 | if (i915_gem_evict_everything(dev, false)) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2688 | return ret; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2689 | |
| 2690 | goto search_free; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2691 | } |
Daniel Vetter | 0ebb982 | 2012-02-15 23:50:24 +0100 | [diff] [blame] | 2692 | |
| 2693 | if (!dev_priv->mm.aliasing_ppgtt) |
| 2694 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2695 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2696 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2697 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2698 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2699 | /* Assert that the object is not currently in any GPU domain. As it |
| 2700 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2701 | * a GPU cache |
| 2702 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2703 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 2704 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2705 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2706 | obj->gtt_offset = obj->gtt_space->start; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2707 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2708 | fenceable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2709 | obj->gtt_space->size == fence_size && |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2710 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2711 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2712 | mappable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2713 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2714 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2715 | obj->map_and_fenceable = mappable && fenceable; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2716 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2717 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2718 | return 0; |
| 2719 | } |
| 2720 | |
| 2721 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2722 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2723 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2724 | /* If we don't have a page list set up, then we're not pinned |
| 2725 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2726 | * again at bind time. |
| 2727 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2728 | if (obj->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2729 | return; |
| 2730 | |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 2731 | /* If the GPU is snooping the contents of the CPU cache, |
| 2732 | * we do not need to manually clear the CPU cache lines. However, |
| 2733 | * the caches are only snooped when the render cache is |
| 2734 | * flushed/invalidated. As we always have to emit invalidations |
| 2735 | * and flushes when moving into and out of the RENDER domain, correct |
| 2736 | * snooping behaviour occurs naturally as the result of our domain |
| 2737 | * tracking. |
| 2738 | */ |
| 2739 | if (obj->cache_level != I915_CACHE_NONE) |
| 2740 | return; |
| 2741 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2742 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 2743 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2744 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2745 | } |
| 2746 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2747 | /** Flushes any GPU write domain for the object if it's dirty. */ |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2748 | static int |
Chris Wilson | 3619df0 | 2010-11-28 15:37:17 +0000 | [diff] [blame] | 2749 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2750 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2751 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2752 | return 0; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2753 | |
| 2754 | /* Queue the GPU write cache flushing we need. */ |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2755 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2756 | } |
| 2757 | |
| 2758 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 2759 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2760 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2761 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2762 | uint32_t old_write_domain; |
| 2763 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2764 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2765 | return; |
| 2766 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2767 | /* No actual flushing is required for the GTT write domain. Writes |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2768 | * to it immediately go to main memory as far as we know, so there's |
| 2769 | * no chipset flush. It also doesn't land in render cache. |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2770 | * |
| 2771 | * However, we do have to enforce the order so that all writes through |
| 2772 | * the GTT land before any writes to the device, such as updates to |
| 2773 | * the GATT itself. |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2774 | */ |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2775 | wmb(); |
| 2776 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2777 | old_write_domain = obj->base.write_domain; |
| 2778 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2779 | |
| 2780 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2781 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2782 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2783 | } |
| 2784 | |
| 2785 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 2786 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2787 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2788 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2789 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2790 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2791 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2792 | return; |
| 2793 | |
| 2794 | i915_gem_clflush_object(obj); |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 2795 | intel_gtt_chipset_flush(); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2796 | old_write_domain = obj->base.write_domain; |
| 2797 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2798 | |
| 2799 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2800 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2801 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2802 | } |
| 2803 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2804 | /** |
| 2805 | * Moves a single object to the GTT read, and possibly write domain. |
| 2806 | * |
| 2807 | * This function returns when the move is complete, including waiting on |
| 2808 | * flushes to occur. |
| 2809 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2810 | int |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2811 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2812 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2813 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2814 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2815 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2816 | /* Not valid to be called on unbound objects. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2817 | if (obj->gtt_space == NULL) |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2818 | return -EINVAL; |
| 2819 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 2820 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
| 2821 | return 0; |
| 2822 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2823 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 2824 | if (ret) |
| 2825 | return ret; |
| 2826 | |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 2827 | if (obj->pending_gpu_write || write) { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2828 | ret = i915_gem_object_wait_rendering(obj); |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 2829 | if (ret) |
| 2830 | return ret; |
| 2831 | } |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2832 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2833 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2834 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2835 | old_write_domain = obj->base.write_domain; |
| 2836 | old_read_domains = obj->base.read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2837 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2838 | /* It should now be out of any other write domains, and we can update |
| 2839 | * the domain values for our changes. |
| 2840 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2841 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2842 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2843 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2844 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 2845 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 2846 | obj->dirty = 1; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2847 | } |
| 2848 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2849 | trace_i915_gem_object_change_domain(obj, |
| 2850 | old_read_domains, |
| 2851 | old_write_domain); |
| 2852 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2853 | return 0; |
| 2854 | } |
| 2855 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2856 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 2857 | enum i915_cache_level cache_level) |
| 2858 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2859 | struct drm_device *dev = obj->base.dev; |
| 2860 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2861 | int ret; |
| 2862 | |
| 2863 | if (obj->cache_level == cache_level) |
| 2864 | return 0; |
| 2865 | |
| 2866 | if (obj->pin_count) { |
| 2867 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
| 2868 | return -EBUSY; |
| 2869 | } |
| 2870 | |
| 2871 | if (obj->gtt_space) { |
| 2872 | ret = i915_gem_object_finish_gpu(obj); |
| 2873 | if (ret) |
| 2874 | return ret; |
| 2875 | |
| 2876 | i915_gem_object_finish_gtt(obj); |
| 2877 | |
| 2878 | /* Before SandyBridge, you could not use tiling or fence |
| 2879 | * registers with snooped memory, so relinquish any fences |
| 2880 | * currently pointing to our region in the aperture. |
| 2881 | */ |
| 2882 | if (INTEL_INFO(obj->base.dev)->gen < 6) { |
| 2883 | ret = i915_gem_object_put_fence(obj); |
| 2884 | if (ret) |
| 2885 | return ret; |
| 2886 | } |
| 2887 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 2888 | if (obj->has_global_gtt_mapping) |
| 2889 | i915_gem_gtt_bind_object(obj, cache_level); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2890 | if (obj->has_aliasing_ppgtt_mapping) |
| 2891 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, |
| 2892 | obj, cache_level); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2893 | } |
| 2894 | |
| 2895 | if (cache_level == I915_CACHE_NONE) { |
| 2896 | u32 old_read_domains, old_write_domain; |
| 2897 | |
| 2898 | /* If we're coming from LLC cached, then we haven't |
| 2899 | * actually been tracking whether the data is in the |
| 2900 | * CPU cache or not, since we only allow one bit set |
| 2901 | * in obj->write_domain and have been skipping the clflushes. |
| 2902 | * Just set it to the CPU cache for now. |
| 2903 | */ |
| 2904 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
| 2905 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); |
| 2906 | |
| 2907 | old_read_domains = obj->base.read_domains; |
| 2908 | old_write_domain = obj->base.write_domain; |
| 2909 | |
| 2910 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 2911 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 2912 | |
| 2913 | trace_i915_gem_object_change_domain(obj, |
| 2914 | old_read_domains, |
| 2915 | old_write_domain); |
| 2916 | } |
| 2917 | |
| 2918 | obj->cache_level = cache_level; |
| 2919 | return 0; |
| 2920 | } |
| 2921 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2922 | /* |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2923 | * Prepare buffer for display plane (scanout, cursors, etc). |
| 2924 | * Can be called from an uninterruptible phase (modesetting) and allows |
| 2925 | * any flushes to be pipelined (for pageflips). |
| 2926 | * |
| 2927 | * For the display plane, we want to be in the GTT but out of any write |
| 2928 | * domains. So in many ways this looks like set_to_gtt_domain() apart from the |
| 2929 | * ability to pipeline the waits, pinning and any additional subtleties |
| 2930 | * that may differentiate the display plane from ordinary buffers. |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2931 | */ |
| 2932 | int |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2933 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 2934 | u32 alignment, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2935 | struct intel_ring_buffer *pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2936 | { |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2937 | u32 old_read_domains, old_write_domain; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2938 | int ret; |
| 2939 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2940 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 2941 | if (ret) |
| 2942 | return ret; |
| 2943 | |
Chris Wilson | 0be7328 | 2010-12-06 14:36:27 +0000 | [diff] [blame] | 2944 | if (pipelined != obj->ring) { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2945 | ret = i915_gem_object_wait_rendering(obj); |
Keith Packard | f0b69ef | 2011-07-19 16:21:40 -0700 | [diff] [blame] | 2946 | if (ret == -ERESTARTSYS) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2947 | return ret; |
| 2948 | } |
| 2949 | |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 2950 | /* The display engine is not coherent with the LLC cache on gen6. As |
| 2951 | * a result, we make sure that the pinning that is about to occur is |
| 2952 | * done with uncached PTEs. This is lowest common denominator for all |
| 2953 | * chipsets. |
| 2954 | * |
| 2955 | * However for gen6+, we could do better by using the GFDT bit instead |
| 2956 | * of uncaching, which would allow us to flush all the LLC-cached data |
| 2957 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
| 2958 | */ |
| 2959 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); |
| 2960 | if (ret) |
| 2961 | return ret; |
| 2962 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2963 | /* As the user may map the buffer once pinned in the display plane |
| 2964 | * (e.g. libkms for the bootup splash), we have to ensure that we |
| 2965 | * always use map_and_fenceable for all scanout buffers. |
| 2966 | */ |
| 2967 | ret = i915_gem_object_pin(obj, alignment, true); |
| 2968 | if (ret) |
| 2969 | return ret; |
| 2970 | |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 2971 | i915_gem_object_flush_cpu_write_domain(obj); |
| 2972 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2973 | old_write_domain = obj->base.write_domain; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2974 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2975 | |
| 2976 | /* It should now be out of any other write domains, and we can update |
| 2977 | * the domain values for our changes. |
| 2978 | */ |
| 2979 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2980 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2981 | |
| 2982 | trace_i915_gem_object_change_domain(obj, |
| 2983 | old_read_domains, |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2984 | old_write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2985 | |
| 2986 | return 0; |
| 2987 | } |
| 2988 | |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 2989 | int |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2990 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 2991 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2992 | int ret; |
| 2993 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2994 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 2995 | return 0; |
| 2996 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2997 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2998 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2999 | if (ret) |
| 3000 | return ret; |
| 3001 | } |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3002 | |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 3003 | ret = i915_gem_object_wait_rendering(obj); |
| 3004 | if (ret) |
| 3005 | return ret; |
| 3006 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3007 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
| 3008 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 3009 | return 0; |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3010 | } |
| 3011 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3012 | /** |
| 3013 | * Moves a single object to the CPU read, and possibly write domain. |
| 3014 | * |
| 3015 | * This function returns when the move is complete, including waiting on |
| 3016 | * flushes to occur. |
| 3017 | */ |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 3018 | int |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3019 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3020 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3021 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3022 | int ret; |
| 3023 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3024 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
| 3025 | return 0; |
| 3026 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3027 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 3028 | if (ret) |
| 3029 | return ret; |
| 3030 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 3031 | ret = i915_gem_object_wait_rendering(obj); |
Daniel Vetter | de18a29 | 2010-11-27 22:30:41 +0100 | [diff] [blame] | 3032 | if (ret) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3033 | return ret; |
| 3034 | |
| 3035 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3036 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3037 | old_write_domain = obj->base.write_domain; |
| 3038 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3039 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3040 | /* Flush the CPU cache if it's still invalid. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3041 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3042 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3043 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3044 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3045 | } |
| 3046 | |
| 3047 | /* It should now be out of any other write domains, and we can update |
| 3048 | * the domain values for our changes. |
| 3049 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3050 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3051 | |
| 3052 | /* If we're writing through the CPU, then the GPU read domains will |
| 3053 | * need to be invalidated at next use. |
| 3054 | */ |
| 3055 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3056 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3057 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3058 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3059 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3060 | trace_i915_gem_object_change_domain(obj, |
| 3061 | old_read_domains, |
| 3062 | old_write_domain); |
| 3063 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3064 | return 0; |
| 3065 | } |
| 3066 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3067 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3068 | * emitted over 20 msec ago. |
| 3069 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3070 | * Note that if we were to use the current jiffies each time around the loop, |
| 3071 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3072 | * render a frame was over 20ms. |
| 3073 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3074 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3075 | * relatively low latency when blocking on a particular request to finish. |
| 3076 | */ |
| 3077 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3078 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3079 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3080 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3081 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3082 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3083 | struct drm_i915_gem_request *request; |
| 3084 | struct intel_ring_buffer *ring = NULL; |
| 3085 | u32 seqno = 0; |
| 3086 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3087 | |
Chris Wilson | e110e8d | 2011-01-26 15:39:14 +0000 | [diff] [blame] | 3088 | if (atomic_read(&dev_priv->mm.wedged)) |
| 3089 | return -EIO; |
| 3090 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3091 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3092 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3093 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3094 | break; |
| 3095 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3096 | ring = request->ring; |
| 3097 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3098 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3099 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3100 | |
| 3101 | if (seqno == 0) |
| 3102 | return 0; |
| 3103 | |
| 3104 | ret = 0; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3105 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3106 | /* And wait for the seqno passing without holding any locks and |
| 3107 | * causing extra latency for others. This is safe as the irq |
| 3108 | * generation is designed to be run atomically and so is |
| 3109 | * lockless. |
| 3110 | */ |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 3111 | if (ring->irq_get(ring)) { |
| 3112 | ret = wait_event_interruptible(ring->irq_queue, |
| 3113 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
| 3114 | || atomic_read(&dev_priv->mm.wedged)); |
| 3115 | ring->irq_put(ring); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3116 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 3117 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
| 3118 | ret = -EIO; |
Eric Anholt | e959b5d | 2011-12-22 14:55:01 -0800 | [diff] [blame] | 3119 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
| 3120 | seqno) || |
Eric Anholt | 7ea29b1 | 2011-12-22 14:54:59 -0800 | [diff] [blame] | 3121 | atomic_read(&dev_priv->mm.wedged), 3000)) { |
| 3122 | ret = -EBUSY; |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 3123 | } |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3124 | } |
| 3125 | |
| 3126 | if (ret == 0) |
| 3127 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3128 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3129 | return ret; |
| 3130 | } |
| 3131 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3132 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3133 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 3134 | uint32_t alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3135 | bool map_and_fenceable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3136 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3137 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 3138 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3139 | int ret; |
| 3140 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3141 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3142 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3143 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3144 | if (obj->gtt_space != NULL) { |
| 3145 | if ((alignment && obj->gtt_offset & (alignment - 1)) || |
| 3146 | (map_and_fenceable && !obj->map_and_fenceable)) { |
| 3147 | WARN(obj->pin_count, |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 3148 | "bo is already pinned with incorrect alignment:" |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3149 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
| 3150 | " obj->map_and_fenceable=%d\n", |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3151 | obj->gtt_offset, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3152 | map_and_fenceable, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3153 | obj->map_and_fenceable); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3154 | ret = i915_gem_object_unbind(obj); |
| 3155 | if (ret) |
| 3156 | return ret; |
| 3157 | } |
| 3158 | } |
| 3159 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3160 | if (obj->gtt_space == NULL) { |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3161 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3162 | map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3163 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3164 | return ret; |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 3165 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3166 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 3167 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
| 3168 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
| 3169 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3170 | if (obj->pin_count++ == 0) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3171 | if (!obj->active) |
| 3172 | list_move_tail(&obj->mm_list, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 3173 | &dev_priv->mm.pinned_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3174 | } |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3175 | obj->pin_mappable |= map_and_fenceable; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3176 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3177 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3178 | return 0; |
| 3179 | } |
| 3180 | |
| 3181 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3182 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3183 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3184 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3185 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3186 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3187 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3188 | BUG_ON(obj->pin_count == 0); |
| 3189 | BUG_ON(obj->gtt_space == NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3190 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3191 | if (--obj->pin_count == 0) { |
| 3192 | if (!obj->active) |
| 3193 | list_move_tail(&obj->mm_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3194 | &dev_priv->mm.inactive_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3195 | obj->pin_mappable = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3196 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3197 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3198 | } |
| 3199 | |
| 3200 | int |
| 3201 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3202 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3203 | { |
| 3204 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3205 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3206 | int ret; |
| 3207 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3208 | ret = i915_mutex_lock_interruptible(dev); |
| 3209 | if (ret) |
| 3210 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3211 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3212 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3213 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3214 | ret = -ENOENT; |
| 3215 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3216 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3217 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3218 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3219 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3220 | ret = -EINVAL; |
| 3221 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3222 | } |
| 3223 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3224 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3225 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 3226 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3227 | ret = -EINVAL; |
| 3228 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3229 | } |
| 3230 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3231 | obj->user_pin_count++; |
| 3232 | obj->pin_filp = file; |
| 3233 | if (obj->user_pin_count == 1) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3234 | ret = i915_gem_object_pin(obj, args->alignment, true); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3235 | if (ret) |
| 3236 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3237 | } |
| 3238 | |
| 3239 | /* XXX - flush the CPU caches for pinned objects |
| 3240 | * as the X server doesn't manage domains yet |
| 3241 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3242 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3243 | args->offset = obj->gtt_offset; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3244 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3245 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3246 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3247 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3248 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3249 | } |
| 3250 | |
| 3251 | int |
| 3252 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3253 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3254 | { |
| 3255 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3256 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3257 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3258 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3259 | ret = i915_mutex_lock_interruptible(dev); |
| 3260 | if (ret) |
| 3261 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3262 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3263 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3264 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3265 | ret = -ENOENT; |
| 3266 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3267 | } |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3268 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3269 | if (obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3270 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 3271 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3272 | ret = -EINVAL; |
| 3273 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3274 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3275 | obj->user_pin_count--; |
| 3276 | if (obj->user_pin_count == 0) { |
| 3277 | obj->pin_filp = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3278 | i915_gem_object_unpin(obj); |
| 3279 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3280 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3281 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3282 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3283 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3284 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3285 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3286 | } |
| 3287 | |
| 3288 | int |
| 3289 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3290 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3291 | { |
| 3292 | struct drm_i915_gem_busy *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3293 | struct drm_i915_gem_object *obj; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3294 | int ret; |
| 3295 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3296 | ret = i915_mutex_lock_interruptible(dev); |
| 3297 | if (ret) |
| 3298 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3299 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3300 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3301 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3302 | ret = -ENOENT; |
| 3303 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3304 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3305 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3306 | /* Count all active objects as busy, even if they are currently not used |
| 3307 | * by the gpu. Users of this interface expect objects to eventually |
| 3308 | * become non-busy without any further actions, therefore emit any |
| 3309 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 3310 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3311 | args->busy = obj->active; |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3312 | if (args->busy) { |
| 3313 | /* Unconditionally flush objects, even when the gpu still uses this |
| 3314 | * object. Userspace calling this function indicates that it wants to |
| 3315 | * use this buffer rather sooner than later, so issuing the required |
| 3316 | * flush earlier is beneficial. |
| 3317 | */ |
Chris Wilson | 1a1c697 | 2010-12-07 23:00:20 +0000 | [diff] [blame] | 3318 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3319 | ret = i915_gem_flush_ring(obj->ring, |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3320 | 0, obj->base.write_domain); |
Chris Wilson | 1a1c697 | 2010-12-07 23:00:20 +0000 | [diff] [blame] | 3321 | } else if (obj->ring->outstanding_lazy_request == |
| 3322 | obj->last_rendering_seqno) { |
| 3323 | struct drm_i915_gem_request *request; |
| 3324 | |
Chris Wilson | 7a19487 | 2010-12-07 10:38:40 +0000 | [diff] [blame] | 3325 | /* This ring is not being cleared by active usage, |
| 3326 | * so emit a request to do so. |
| 3327 | */ |
Chris Wilson | 1a1c697 | 2010-12-07 23:00:20 +0000 | [diff] [blame] | 3328 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
Rakib Mullick | 457eafc | 2011-11-16 00:49:28 +0600 | [diff] [blame] | 3329 | if (request) { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3330 | ret = i915_add_request(obj->ring, NULL, request); |
Rakib Mullick | 457eafc | 2011-11-16 00:49:28 +0600 | [diff] [blame] | 3331 | if (ret) |
| 3332 | kfree(request); |
| 3333 | } else |
Chris Wilson | 7a19487 | 2010-12-07 10:38:40 +0000 | [diff] [blame] | 3334 | ret = -ENOMEM; |
| 3335 | } |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3336 | |
| 3337 | /* Update the active list for the hardware's current position. |
| 3338 | * Otherwise this only updates on a delayed timer or when irqs |
| 3339 | * are actually unmasked, and our working set ends up being |
| 3340 | * larger than required. |
| 3341 | */ |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3342 | i915_gem_retire_requests_ring(obj->ring); |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3343 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3344 | args->busy = obj->active; |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3345 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3346 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3347 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3348 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3349 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3350 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3351 | } |
| 3352 | |
| 3353 | int |
| 3354 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 3355 | struct drm_file *file_priv) |
| 3356 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3357 | return i915_gem_ring_throttle(dev, file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3358 | } |
| 3359 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3360 | int |
| 3361 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 3362 | struct drm_file *file_priv) |
| 3363 | { |
| 3364 | struct drm_i915_gem_madvise *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3365 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3366 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3367 | |
| 3368 | switch (args->madv) { |
| 3369 | case I915_MADV_DONTNEED: |
| 3370 | case I915_MADV_WILLNEED: |
| 3371 | break; |
| 3372 | default: |
| 3373 | return -EINVAL; |
| 3374 | } |
| 3375 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3376 | ret = i915_mutex_lock_interruptible(dev); |
| 3377 | if (ret) |
| 3378 | return ret; |
| 3379 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3380 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3381 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3382 | ret = -ENOENT; |
| 3383 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3384 | } |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3385 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3386 | if (obj->pin_count) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3387 | ret = -EINVAL; |
| 3388 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3389 | } |
| 3390 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3391 | if (obj->madv != __I915_MADV_PURGED) |
| 3392 | obj->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3393 | |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 3394 | /* if the object is no longer bound, discard its backing storage */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3395 | if (i915_gem_object_is_purgeable(obj) && |
| 3396 | obj->gtt_space == NULL) |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 3397 | i915_gem_object_truncate(obj); |
| 3398 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3399 | args->retained = obj->madv != __I915_MADV_PURGED; |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3400 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3401 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3402 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3403 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3404 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3405 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3406 | } |
| 3407 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3408 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 3409 | size_t size) |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3410 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3411 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3412 | struct drm_i915_gem_object *obj; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3413 | struct address_space *mapping; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3414 | |
| 3415 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
| 3416 | if (obj == NULL) |
| 3417 | return NULL; |
| 3418 | |
| 3419 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
| 3420 | kfree(obj); |
| 3421 | return NULL; |
| 3422 | } |
| 3423 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3424 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
| 3425 | mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 3426 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3427 | i915_gem_info_add_obj(dev_priv, size); |
| 3428 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3429 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3430 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3431 | |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 3432 | if (HAS_LLC(dev)) { |
| 3433 | /* On some devices, we can have the GPU use the LLC (the CPU |
Eric Anholt | a187111 | 2011-03-29 16:59:55 -0700 | [diff] [blame] | 3434 | * cache) for about a 10% performance improvement |
| 3435 | * compared to uncached. Graphics requests other than |
| 3436 | * display scanout are coherent with the CPU in |
| 3437 | * accessing this cache. This means in this mode we |
| 3438 | * don't need to clflush on the CPU side, and on the |
| 3439 | * GPU side we only need to flush internal caches to |
| 3440 | * get data visible to the CPU. |
| 3441 | * |
| 3442 | * However, we maintain the display planes as UC, and so |
| 3443 | * need to rebind when first used as such. |
| 3444 | */ |
| 3445 | obj->cache_level = I915_CACHE_LLC; |
| 3446 | } else |
| 3447 | obj->cache_level = I915_CACHE_NONE; |
| 3448 | |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 3449 | obj->base.driver_private = NULL; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3450 | obj->fence_reg = I915_FENCE_REG_NONE; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3451 | INIT_LIST_HEAD(&obj->mm_list); |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 3452 | INIT_LIST_HEAD(&obj->gtt_list); |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3453 | INIT_LIST_HEAD(&obj->ring_list); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 3454 | INIT_LIST_HEAD(&obj->exec_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3455 | INIT_LIST_HEAD(&obj->gpu_write_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3456 | obj->madv = I915_MADV_WILLNEED; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3457 | /* Avoid an unnecessary call to unbind on the first bind. */ |
| 3458 | obj->map_and_fenceable = true; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3459 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3460 | return obj; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3461 | } |
| 3462 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3463 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 3464 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3465 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3466 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3467 | return 0; |
| 3468 | } |
| 3469 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3470 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3471 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3472 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3473 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3474 | int ret; |
| 3475 | |
| 3476 | ret = i915_gem_object_unbind(obj); |
| 3477 | if (ret == -ERESTARTSYS) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3478 | list_move(&obj->mm_list, |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3479 | &dev_priv->mm.deferred_free_list); |
| 3480 | return; |
| 3481 | } |
| 3482 | |
Chris Wilson | 26e12f89 | 2011-03-20 11:20:19 +0000 | [diff] [blame] | 3483 | trace_i915_gem_object_destroy(obj); |
| 3484 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3485 | if (obj->base.map_list.map) |
Rob Clark | b464e9a | 2011-08-10 08:09:08 -0500 | [diff] [blame] | 3486 | drm_gem_free_mmap_offset(&obj->base); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3487 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3488 | drm_gem_object_release(&obj->base); |
| 3489 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3490 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3491 | kfree(obj->bit_17); |
| 3492 | kfree(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3493 | } |
| 3494 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3495 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3496 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3497 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
| 3498 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3499 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3500 | while (obj->pin_count > 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3501 | i915_gem_object_unpin(obj); |
| 3502 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3503 | if (obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3504 | i915_gem_detach_phys_object(dev, obj); |
| 3505 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3506 | i915_gem_free_object_tail(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3507 | } |
| 3508 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 3509 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3510 | i915_gem_idle(struct drm_device *dev) |
| 3511 | { |
| 3512 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3513 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3514 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3515 | mutex_lock(&dev->struct_mutex); |
| 3516 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 3517 | if (dev_priv->mm.suspended) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3518 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3519 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3520 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3521 | |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 3522 | ret = i915_gpu_idle(dev, true); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3523 | if (ret) { |
| 3524 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3525 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3526 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3527 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3528 | /* Under UMS, be paranoid and evict. */ |
| 3529 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { |
Chris Wilson | 5eac3ab | 2010-10-31 08:49:47 +0000 | [diff] [blame] | 3530 | ret = i915_gem_evict_inactive(dev, false); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3531 | if (ret) { |
| 3532 | mutex_unlock(&dev->struct_mutex); |
| 3533 | return ret; |
| 3534 | } |
| 3535 | } |
| 3536 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 3537 | i915_gem_reset_fences(dev); |
| 3538 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3539 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 3540 | * We need to replace this with a semaphore, or something. |
| 3541 | * And not confound mm.suspended! |
| 3542 | */ |
| 3543 | dev_priv->mm.suspended = 1; |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 3544 | del_timer_sync(&dev_priv->hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3545 | |
| 3546 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3547 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3548 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3549 | mutex_unlock(&dev->struct_mutex); |
| 3550 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3551 | /* Cancel the retire work handler, which should be idle now. */ |
| 3552 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 3553 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3554 | return 0; |
| 3555 | } |
| 3556 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3557 | void i915_gem_init_swizzling(struct drm_device *dev) |
| 3558 | { |
| 3559 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3560 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 3561 | if (INTEL_INFO(dev)->gen < 5 || |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3562 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
| 3563 | return; |
| 3564 | |
| 3565 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
| 3566 | DISP_TILE_SURFACE_SWIZZLING); |
| 3567 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 3568 | if (IS_GEN5(dev)) |
| 3569 | return; |
| 3570 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3571 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
| 3572 | if (IS_GEN6(dev)) |
| 3573 | I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
| 3574 | else |
| 3575 | I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
| 3576 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3577 | |
| 3578 | void i915_gem_init_ppgtt(struct drm_device *dev) |
| 3579 | { |
| 3580 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3581 | uint32_t pd_offset; |
| 3582 | struct intel_ring_buffer *ring; |
| 3583 | int i; |
| 3584 | |
| 3585 | if (!dev_priv->mm.aliasing_ppgtt) |
| 3586 | return; |
| 3587 | |
| 3588 | pd_offset = dev_priv->mm.aliasing_ppgtt->pd_offset; |
| 3589 | pd_offset /= 64; /* in cachelines, */ |
| 3590 | pd_offset <<= 16; |
| 3591 | |
| 3592 | if (INTEL_INFO(dev)->gen == 6) { |
| 3593 | uint32_t ecochk = I915_READ(GAM_ECOCHK); |
| 3594 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | |
| 3595 | ECOCHK_PPGTT_CACHE64B); |
| 3596 | I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); |
| 3597 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 3598 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); |
| 3599 | /* GFX_MODE is per-ring on gen7+ */ |
| 3600 | } |
| 3601 | |
| 3602 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 3603 | ring = &dev_priv->ring[i]; |
| 3604 | |
| 3605 | if (INTEL_INFO(dev)->gen >= 7) |
| 3606 | I915_WRITE(RING_MODE_GEN7(ring), |
| 3607 | GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); |
| 3608 | |
| 3609 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
| 3610 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); |
| 3611 | } |
| 3612 | } |
| 3613 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3614 | int |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3615 | i915_gem_init_hw(struct drm_device *dev) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3616 | { |
| 3617 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3618 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3619 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3620 | i915_gem_init_swizzling(dev); |
| 3621 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3622 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3623 | if (ret) |
Chris Wilson | b6913e4 | 2010-11-12 10:46:37 +0000 | [diff] [blame] | 3624 | return ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3625 | |
| 3626 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3627 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3628 | if (ret) |
| 3629 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3630 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3631 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3632 | if (HAS_BLT(dev)) { |
| 3633 | ret = intel_init_blt_ring_buffer(dev); |
| 3634 | if (ret) |
| 3635 | goto cleanup_bsd_ring; |
| 3636 | } |
| 3637 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 3638 | dev_priv->next_seqno = 1; |
| 3639 | |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3640 | i915_gem_init_ppgtt(dev); |
| 3641 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3642 | return 0; |
| 3643 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3644 | cleanup_bsd_ring: |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3645 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3646 | cleanup_render_ring: |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3647 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3648 | return ret; |
| 3649 | } |
| 3650 | |
| 3651 | void |
| 3652 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 3653 | { |
| 3654 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3655 | int i; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3656 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3657 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 3658 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3659 | } |
| 3660 | |
| 3661 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3662 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 3663 | struct drm_file *file_priv) |
| 3664 | { |
| 3665 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3666 | int ret, i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3667 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3668 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3669 | return 0; |
| 3670 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3671 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3672 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3673 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3674 | } |
| 3675 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3676 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3677 | dev_priv->mm.suspended = 0; |
| 3678 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3679 | ret = i915_gem_init_hw(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 3680 | if (ret != 0) { |
| 3681 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3682 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 3683 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3684 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3685 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3686 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 3687 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3688 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 3689 | BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); |
| 3690 | BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); |
| 3691 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3692 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3693 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 3694 | ret = drm_irq_install(dev); |
| 3695 | if (ret) |
| 3696 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3697 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3698 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 3699 | |
| 3700 | cleanup_ringbuffer: |
| 3701 | mutex_lock(&dev->struct_mutex); |
| 3702 | i915_gem_cleanup_ringbuffer(dev); |
| 3703 | dev_priv->mm.suspended = 1; |
| 3704 | mutex_unlock(&dev->struct_mutex); |
| 3705 | |
| 3706 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3707 | } |
| 3708 | |
| 3709 | int |
| 3710 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 3711 | struct drm_file *file_priv) |
| 3712 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3713 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3714 | return 0; |
| 3715 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3716 | drm_irq_uninstall(dev); |
Linus Torvalds | e6890f6 | 2009-09-08 17:09:24 -0700 | [diff] [blame] | 3717 | return i915_gem_idle(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3718 | } |
| 3719 | |
| 3720 | void |
| 3721 | i915_gem_lastclose(struct drm_device *dev) |
| 3722 | { |
| 3723 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3724 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 3725 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3726 | return; |
| 3727 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3728 | ret = i915_gem_idle(dev); |
| 3729 | if (ret) |
| 3730 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3731 | } |
| 3732 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 3733 | static void |
| 3734 | init_ring_lists(struct intel_ring_buffer *ring) |
| 3735 | { |
| 3736 | INIT_LIST_HEAD(&ring->active_list); |
| 3737 | INIT_LIST_HEAD(&ring->request_list); |
| 3738 | INIT_LIST_HEAD(&ring->gpu_write_list); |
| 3739 | } |
| 3740 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3741 | void |
| 3742 | i915_gem_load(struct drm_device *dev) |
| 3743 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3744 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3745 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3746 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3747 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3748 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
| 3749 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 3750 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 3751 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3752 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 3753 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3754 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 3755 | init_ring_lists(&dev_priv->ring[i]); |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 3756 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 3757 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3758 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 3759 | i915_gem_retire_work_handler); |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3760 | init_completion(&dev_priv->error_completion); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3761 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 3762 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 3763 | if (IS_GEN3(dev)) { |
| 3764 | u32 tmp = I915_READ(MI_ARB_STATE); |
| 3765 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { |
| 3766 | /* arb state is a masked write, so set bit + bit in mask */ |
| 3767 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); |
| 3768 | I915_WRITE(MI_ARB_STATE, tmp); |
| 3769 | } |
| 3770 | } |
| 3771 | |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 3772 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
| 3773 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3774 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 3775 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3776 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3777 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3778 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3779 | dev_priv->num_fence_regs = 16; |
| 3780 | else |
| 3781 | dev_priv->num_fence_regs = 8; |
| 3782 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3783 | /* Initialize fence registers to zero */ |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 3784 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
| 3785 | i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]); |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3786 | } |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 3787 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3788 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3789 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3790 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 3791 | dev_priv->mm.interruptible = true; |
| 3792 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3793 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
| 3794 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
| 3795 | register_shrinker(&dev_priv->mm.inactive_shrinker); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3796 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3797 | |
| 3798 | /* |
| 3799 | * Create a physically contiguous memory object for this object |
| 3800 | * e.g. for cursor + overlay regs |
| 3801 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 3802 | static int i915_gem_init_phys_object(struct drm_device *dev, |
| 3803 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3804 | { |
| 3805 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3806 | struct drm_i915_gem_phys_object *phys_obj; |
| 3807 | int ret; |
| 3808 | |
| 3809 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 3810 | return 0; |
| 3811 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3812 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3813 | if (!phys_obj) |
| 3814 | return -ENOMEM; |
| 3815 | |
| 3816 | phys_obj->id = id; |
| 3817 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 3818 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3819 | if (!phys_obj->handle) { |
| 3820 | ret = -ENOMEM; |
| 3821 | goto kfree_obj; |
| 3822 | } |
| 3823 | #ifdef CONFIG_X86 |
| 3824 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 3825 | #endif |
| 3826 | |
| 3827 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 3828 | |
| 3829 | return 0; |
| 3830 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3831 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3832 | return ret; |
| 3833 | } |
| 3834 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 3835 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3836 | { |
| 3837 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3838 | struct drm_i915_gem_phys_object *phys_obj; |
| 3839 | |
| 3840 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 3841 | return; |
| 3842 | |
| 3843 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 3844 | if (phys_obj->cur_obj) { |
| 3845 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 3846 | } |
| 3847 | |
| 3848 | #ifdef CONFIG_X86 |
| 3849 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 3850 | #endif |
| 3851 | drm_pci_free(dev, phys_obj->handle); |
| 3852 | kfree(phys_obj); |
| 3853 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 3854 | } |
| 3855 | |
| 3856 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 3857 | { |
| 3858 | int i; |
| 3859 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 3860 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3861 | i915_gem_free_phys_object(dev, i); |
| 3862 | } |
| 3863 | |
| 3864 | void i915_gem_detach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3865 | struct drm_i915_gem_object *obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3866 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3867 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3868 | char *vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3869 | int i; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3870 | int page_count; |
| 3871 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3872 | if (!obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3873 | return; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3874 | vaddr = obj->phys_obj->handle->vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3875 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3876 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3877 | for (i = 0; i < page_count; i++) { |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3878 | struct page *page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3879 | if (!IS_ERR(page)) { |
| 3880 | char *dst = kmap_atomic(page); |
| 3881 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); |
| 3882 | kunmap_atomic(dst); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3883 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3884 | drm_clflush_pages(&page, 1); |
| 3885 | |
| 3886 | set_page_dirty(page); |
| 3887 | mark_page_accessed(page); |
| 3888 | page_cache_release(page); |
| 3889 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3890 | } |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 3891 | intel_gtt_chipset_flush(); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 3892 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3893 | obj->phys_obj->cur_obj = NULL; |
| 3894 | obj->phys_obj = NULL; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3895 | } |
| 3896 | |
| 3897 | int |
| 3898 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3899 | struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 3900 | int id, |
| 3901 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3902 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3903 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3904 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3905 | int ret = 0; |
| 3906 | int page_count; |
| 3907 | int i; |
| 3908 | |
| 3909 | if (id > I915_MAX_PHYS_OBJECT) |
| 3910 | return -EINVAL; |
| 3911 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3912 | if (obj->phys_obj) { |
| 3913 | if (obj->phys_obj->id == id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3914 | return 0; |
| 3915 | i915_gem_detach_phys_object(dev, obj); |
| 3916 | } |
| 3917 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3918 | /* create a new object */ |
| 3919 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 3920 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3921 | obj->base.size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3922 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3923 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
| 3924 | id, obj->base.size); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3925 | return ret; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3926 | } |
| 3927 | } |
| 3928 | |
| 3929 | /* bind to the object */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3930 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 3931 | obj->phys_obj->cur_obj = obj; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3932 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3933 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3934 | |
| 3935 | for (i = 0; i < page_count; i++) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3936 | struct page *page; |
| 3937 | char *dst, *src; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3938 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3939 | page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3940 | if (IS_ERR(page)) |
| 3941 | return PTR_ERR(page); |
| 3942 | |
Chris Wilson | ff75b9b | 2010-10-30 22:52:31 +0100 | [diff] [blame] | 3943 | src = kmap_atomic(page); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3944 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3945 | memcpy(dst, src, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 3946 | kunmap_atomic(src); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3947 | |
| 3948 | mark_page_accessed(page); |
| 3949 | page_cache_release(page); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3950 | } |
| 3951 | |
| 3952 | return 0; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3953 | } |
| 3954 | |
| 3955 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3956 | i915_gem_phys_pwrite(struct drm_device *dev, |
| 3957 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3958 | struct drm_i915_gem_pwrite *args, |
| 3959 | struct drm_file *file_priv) |
| 3960 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3961 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 3962 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3963 | |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 3964 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 3965 | unsigned long unwritten; |
| 3966 | |
| 3967 | /* The physical object once assigned is fixed for the lifetime |
| 3968 | * of the obj, so we can safely drop the lock and continue |
| 3969 | * to access vaddr. |
| 3970 | */ |
| 3971 | mutex_unlock(&dev->struct_mutex); |
| 3972 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 3973 | mutex_lock(&dev->struct_mutex); |
| 3974 | if (unwritten) |
| 3975 | return -EFAULT; |
| 3976 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3977 | |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 3978 | intel_gtt_chipset_flush(); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3979 | return 0; |
| 3980 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3981 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3982 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3983 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3984 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3985 | |
| 3986 | /* Clean up our request list when the client is going away, so that |
| 3987 | * later retire_requests won't dereference our soon-to-be-gone |
| 3988 | * file_priv. |
| 3989 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3990 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3991 | while (!list_empty(&file_priv->mm.request_list)) { |
| 3992 | struct drm_i915_gem_request *request; |
| 3993 | |
| 3994 | request = list_first_entry(&file_priv->mm.request_list, |
| 3995 | struct drm_i915_gem_request, |
| 3996 | client_list); |
| 3997 | list_del(&request->client_list); |
| 3998 | request->file_priv = NULL; |
| 3999 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4000 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4001 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4002 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4003 | static int |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4004 | i915_gpu_is_active(struct drm_device *dev) |
| 4005 | { |
| 4006 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4007 | int lists_empty; |
| 4008 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4009 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4010 | list_empty(&dev_priv->mm.active_list); |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4011 | |
| 4012 | return !lists_empty; |
| 4013 | } |
| 4014 | |
| 4015 | static int |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 4016 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4017 | { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4018 | struct drm_i915_private *dev_priv = |
| 4019 | container_of(shrinker, |
| 4020 | struct drm_i915_private, |
| 4021 | mm.inactive_shrinker); |
| 4022 | struct drm_device *dev = dev_priv->dev; |
| 4023 | struct drm_i915_gem_object *obj, *next; |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 4024 | int nr_to_scan = sc->nr_to_scan; |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4025 | int cnt; |
| 4026 | |
| 4027 | if (!mutex_trylock(&dev->struct_mutex)) |
Chris Wilson | bbe2e11 | 2010-10-28 22:35:07 +0100 | [diff] [blame] | 4028 | return 0; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4029 | |
| 4030 | /* "fast-path" to count number of available objects */ |
| 4031 | if (nr_to_scan == 0) { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4032 | cnt = 0; |
| 4033 | list_for_each_entry(obj, |
| 4034 | &dev_priv->mm.inactive_list, |
| 4035 | mm_list) |
| 4036 | cnt++; |
| 4037 | mutex_unlock(&dev->struct_mutex); |
| 4038 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4039 | } |
| 4040 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4041 | rescan: |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4042 | /* first scan for clean buffers */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4043 | i915_gem_retire_requests(dev); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4044 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4045 | list_for_each_entry_safe(obj, next, |
| 4046 | &dev_priv->mm.inactive_list, |
| 4047 | mm_list) { |
| 4048 | if (i915_gem_object_is_purgeable(obj)) { |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 4049 | if (i915_gem_object_unbind(obj) == 0 && |
| 4050 | --nr_to_scan == 0) |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4051 | break; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4052 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4053 | } |
| 4054 | |
| 4055 | /* second pass, evict/count anything still on the inactive list */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4056 | cnt = 0; |
| 4057 | list_for_each_entry_safe(obj, next, |
| 4058 | &dev_priv->mm.inactive_list, |
| 4059 | mm_list) { |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 4060 | if (nr_to_scan && |
| 4061 | i915_gem_object_unbind(obj) == 0) |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4062 | nr_to_scan--; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 4063 | else |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4064 | cnt++; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4065 | } |
| 4066 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4067 | if (nr_to_scan && i915_gpu_is_active(dev)) { |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4068 | /* |
| 4069 | * We are desperate for pages, so as a last resort, wait |
| 4070 | * for the GPU to finish and discard whatever we can. |
| 4071 | * This has a dramatic impact to reduce the number of |
| 4072 | * OOM-killer events whilst running the GPU aggressively. |
| 4073 | */ |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 4074 | if (i915_gpu_idle(dev, true) == 0) |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4075 | goto rescan; |
| 4076 | } |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4077 | mutex_unlock(&dev->struct_mutex); |
| 4078 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4079 | } |