blob: 7885fc475f7e85cce875833facb79a18ef4e475a [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Petr Machata803335a2018-02-27 14:53:46 +01003 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
Jiri Pirko22a67762017-02-03 10:29:07 +01004 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +020056#include <linux/netlink.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020057#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020058#include <net/pkt_cls.h>
59#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020060#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010061#include <net/tc_act/tc_sample.h>
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +020062#include <net/addrconf.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020063
64#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020065#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020066#include "core.h"
67#include "reg.h"
68#include "port.h"
69#include "trap.h"
70#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010071#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020072#include "spectrum_dpipe.h"
Yotam Gigid3b939b2017-09-19 10:00:09 +020073#include "spectrum_acl_flex_actions.h"
Petr Machataa629ef22018-02-13 11:27:48 +010074#include "spectrum_span.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020075#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020076
Yotam Gigi6b742192017-05-23 21:56:29 +020077#define MLXSW_FWREV_MAJOR 13
Tal Bar1c6e1032018-03-21 09:34:05 +020078#define MLXSW_FWREV_MINOR 1620
79#define MLXSW_FWREV_SUBMINOR 192
Yuval Mintzfd5204c2018-01-18 12:55:23 +010080#define MLXSW_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
Yotam Gigi6b742192017-05-23 21:56:29 +020081
82#define MLXSW_SP_FW_FILENAME \
Yotam Gigia4e1ce22017-06-04 16:49:58 +020083 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
Yotam Gigi6b742192017-05-23 21:56:29 +020084 "." __stringify(MLXSW_FWREV_MINOR) \
85 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
86
Jiri Pirko56ade8f2015-10-16 14:01:37 +020087static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
88static const char mlxsw_sp_driver_version[] = "1.0";
89
90/* tx_hdr_version
91 * Tx header version.
92 * Must be set to 1.
93 */
94MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
95
96/* tx_hdr_ctl
97 * Packet control type.
98 * 0 - Ethernet control (e.g. EMADs, LACP)
99 * 1 - Ethernet data
100 */
101MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
102
103/* tx_hdr_proto
104 * Packet protocol type. Must be set to 1 (Ethernet).
105 */
106MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
107
108/* tx_hdr_rx_is_router
109 * Packet is sent from the router. Valid for data packets only.
110 */
111MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
112
113/* tx_hdr_fid_valid
114 * Indicates if the 'fid' field is valid and should be used for
115 * forwarding lookup. Valid for data packets only.
116 */
117MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
118
119/* tx_hdr_swid
120 * Switch partition ID. Must be set to 0.
121 */
122MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
123
124/* tx_hdr_control_tclass
125 * Indicates if the packet should use the control TClass and not one
126 * of the data TClasses.
127 */
128MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
129
130/* tx_hdr_etclass
131 * Egress TClass to be used on the egress device on the egress port.
132 */
133MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
134
135/* tx_hdr_port_mid
136 * Destination local port for unicast packets.
137 * Destination multicast ID for multicast packets.
138 *
139 * Control packets are directed to a specific egress port, while data
140 * packets are transmitted through the CPU port (0) into the switch partition,
141 * where forwarding rules are applied.
142 */
143MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
144
145/* tx_hdr_fid
146 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
147 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
148 * Valid for data packets only.
149 */
150MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
151
152/* tx_hdr_type
153 * 0 - Data packets
154 * 6 - Control packets
155 */
156MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
157
Yotam Gigie5e5c882017-05-23 21:56:27 +0200158struct mlxsw_sp_mlxfw_dev {
159 struct mlxfw_dev mlxfw_dev;
160 struct mlxsw_sp *mlxsw_sp;
161};
162
163static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
164 u16 component_index, u32 *p_max_size,
165 u8 *p_align_bits, u16 *p_max_write_size)
166{
167 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
168 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
169 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
170 char mcqi_pl[MLXSW_REG_MCQI_LEN];
171 int err;
172
173 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
174 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
175 if (err)
176 return err;
177 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
178 p_max_write_size);
179
180 *p_align_bits = max_t(u8, *p_align_bits, 2);
181 *p_max_write_size = min_t(u16, *p_max_write_size,
182 MLXSW_REG_MCDA_MAX_DATA_LEN);
183 return 0;
184}
185
186static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
187{
188 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
189 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
190 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
191 char mcc_pl[MLXSW_REG_MCC_LEN];
192 u8 control_state;
193 int err;
194
195 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
196 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
197 if (err)
198 return err;
199
200 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
201 if (control_state != MLXFW_FSM_STATE_IDLE)
202 return -EBUSY;
203
204 mlxsw_reg_mcc_pack(mcc_pl,
205 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
206 0, *fwhandle, 0);
207 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
208}
209
210static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
211 u32 fwhandle, u16 component_index,
212 u32 component_size)
213{
214 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
215 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
217 char mcc_pl[MLXSW_REG_MCC_LEN];
218
219 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
220 component_index, fwhandle, component_size);
221 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
222}
223
224static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
225 u32 fwhandle, u8 *data, u16 size,
226 u32 offset)
227{
228 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
229 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
230 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
231 char mcda_pl[MLXSW_REG_MCDA_LEN];
232
233 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
234 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
235}
236
237static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
238 u32 fwhandle, u16 component_index)
239{
240 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
241 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
242 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
243 char mcc_pl[MLXSW_REG_MCC_LEN];
244
245 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
246 component_index, fwhandle, 0);
247 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
248}
249
250static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
251{
252 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
253 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
254 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
255 char mcc_pl[MLXSW_REG_MCC_LEN];
256
257 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
258 fwhandle, 0);
259 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
260}
261
262static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
263 enum mlxfw_fsm_state *fsm_state,
264 enum mlxfw_fsm_state_err *fsm_state_err)
265{
266 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
267 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
268 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
269 char mcc_pl[MLXSW_REG_MCC_LEN];
270 u8 control_state;
271 u8 error_code;
272 int err;
273
274 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
275 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
276 if (err)
277 return err;
278
279 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
280 *fsm_state = control_state;
281 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
282 MLXFW_FSM_STATE_ERR_MAX);
283 return 0;
284}
285
286static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
287{
288 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
289 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
290 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
291 char mcc_pl[MLXSW_REG_MCC_LEN];
292
293 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
294 fwhandle, 0);
295 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
296}
297
298static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
299{
300 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
301 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
302 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
303 char mcc_pl[MLXSW_REG_MCC_LEN];
304
305 mlxsw_reg_mcc_pack(mcc_pl,
306 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
307 fwhandle, 0);
308 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
309}
310
311static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
312 .component_query = mlxsw_sp_component_query,
313 .fsm_lock = mlxsw_sp_fsm_lock,
314 .fsm_component_update = mlxsw_sp_fsm_component_update,
315 .fsm_block_download = mlxsw_sp_fsm_block_download,
316 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
317 .fsm_activate = mlxsw_sp_fsm_activate,
318 .fsm_query_state = mlxsw_sp_fsm_query_state,
319 .fsm_cancel = mlxsw_sp_fsm_cancel,
320 .fsm_release = mlxsw_sp_fsm_release
321};
322
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300323static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
324 const struct firmware *firmware)
325{
326 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
327 .mlxfw_dev = {
328 .ops = &mlxsw_sp_mlxfw_dev_ops,
329 .psid = mlxsw_sp->bus_info->psid,
330 .psid_size = strlen(mlxsw_sp->bus_info->psid),
331 },
332 .mlxsw_sp = mlxsw_sp
333 };
334
335 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
336}
337
Yotam Gigi6b742192017-05-23 21:56:29 +0200338static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
339{
340 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
Yotam Gigi6b742192017-05-23 21:56:29 +0200341 const struct firmware *firmware;
342 int err;
343
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100344 /* Validate driver & FW are compatible */
345 if (rev->major != MLXSW_FWREV_MAJOR) {
346 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
347 rev->major, MLXSW_FWREV_MAJOR);
348 return -EINVAL;
349 }
350 if (MLXSW_FWREV_MINOR_TO_BRANCH(rev->minor) ==
351 MLXSW_FWREV_MINOR_TO_BRANCH(MLXSW_FWREV_MINOR))
Yotam Gigi6b742192017-05-23 21:56:29 +0200352 return 0;
353
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100354 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200355 rev->major, rev->minor, rev->subminor);
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100356 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200357 MLXSW_SP_FW_FILENAME);
358
359 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
360 mlxsw_sp->bus_info->dev);
361 if (err) {
362 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
363 MLXSW_SP_FW_FILENAME);
364 return err;
365 }
366
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300367 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
Yotam Gigi6b742192017-05-23 21:56:29 +0200368 release_firmware(firmware);
369 return err;
370}
371
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100372int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
373 unsigned int counter_index, u64 *packets,
374 u64 *bytes)
375{
376 char mgpc_pl[MLXSW_REG_MGPC_LEN];
377 int err;
378
379 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200380 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100381 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
382 if (err)
383 return err;
Arkadi Sharshevsky7cfcbc72017-08-24 08:40:08 +0200384 if (packets)
385 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
386 if (bytes)
387 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100388 return 0;
389}
390
391static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
392 unsigned int counter_index)
393{
394 char mgpc_pl[MLXSW_REG_MGPC_LEN];
395
396 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200397 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100398 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
399}
400
401int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
402 unsigned int *p_counter_index)
403{
404 int err;
405
406 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
407 p_counter_index);
408 if (err)
409 return err;
410 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
411 if (err)
412 goto err_counter_clear;
413 return 0;
414
415err_counter_clear:
416 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
417 *p_counter_index);
418 return err;
419}
420
421void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
422 unsigned int counter_index)
423{
424 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
425 counter_index);
426}
427
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200428static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
429 const struct mlxsw_tx_info *tx_info)
430{
431 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
432
433 memset(txhdr, 0, MLXSW_TXHDR_LEN);
434
435 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
436 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
437 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
438 mlxsw_tx_hdr_swid_set(txhdr, 0);
439 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
440 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
441 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
442}
443
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200444int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
445 u8 state)
446{
447 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
448 enum mlxsw_reg_spms_state spms_state;
449 char *spms_pl;
450 int err;
451
452 switch (state) {
453 case BR_STATE_FORWARDING:
454 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
455 break;
456 case BR_STATE_LEARNING:
457 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
458 break;
459 case BR_STATE_LISTENING: /* fall-through */
460 case BR_STATE_DISABLED: /* fall-through */
461 case BR_STATE_BLOCKING:
462 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
463 break;
464 default:
465 BUG();
466 }
467
468 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
469 if (!spms_pl)
470 return -ENOMEM;
471 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
472 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
473
474 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
475 kfree(spms_pl);
476 return err;
477}
478
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200479static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
480{
Elad Raz5b090742016-10-28 21:35:46 +0200481 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200482 int err;
483
484 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
485 if (err)
486 return err;
487 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
488 return 0;
489}
490
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100491static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
492 bool enable, u32 rate)
493{
494 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
495 char mpsc_pl[MLXSW_REG_MPSC_LEN];
496
497 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
498 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
499}
500
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200501static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
502 bool is_up)
503{
504 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
505 char paos_pl[MLXSW_REG_PAOS_LEN];
506
507 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
508 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
509 MLXSW_PORT_ADMIN_STATUS_DOWN);
510 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
511}
512
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200513static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
514 unsigned char *addr)
515{
516 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
517 char ppad_pl[MLXSW_REG_PPAD_LEN];
518
519 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
520 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
521 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
522}
523
524static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
525{
526 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
527 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
528
529 ether_addr_copy(addr, mlxsw_sp->base_mac);
530 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
531 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
532}
533
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200534static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
535{
536 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
537 char pmtu_pl[MLXSW_REG_PMTU_LEN];
538 int max_mtu;
539 int err;
540
541 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
542 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
543 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
544 if (err)
545 return err;
546 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
547
548 if (mtu > max_mtu)
549 return -EINVAL;
550
551 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
552 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
553}
554
555static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
556{
557 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel5b153852017-06-08 08:47:44 +0200558 char pspa_pl[MLXSW_REG_PSPA_LEN];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200559
Ido Schimmel5b153852017-06-08 08:47:44 +0200560 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
561 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200562}
563
Ido Schimmela1107482017-05-26 08:37:39 +0200564int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200565{
566 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
567 char svpe_pl[MLXSW_REG_SVPE_LEN];
568
569 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
570 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
571}
572
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200573int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
574 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200575{
576 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
577 char *spvmlr_pl;
578 int err;
579
580 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
581 if (!spvmlr_pl)
582 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200583 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
584 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200585 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
586 kfree(spvmlr_pl);
587 return err;
588}
589
Ido Schimmelb02eae92017-05-16 19:38:34 +0200590static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
591 u16 vid)
592{
593 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
594 char spvid_pl[MLXSW_REG_SPVID_LEN];
595
596 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
597 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
598}
599
600static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
601 bool allow)
602{
603 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
604 char spaft_pl[MLXSW_REG_SPAFT_LEN];
605
606 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
607 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
608}
609
610int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
611{
612 int err;
613
614 if (!vid) {
615 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
616 if (err)
617 return err;
618 } else {
619 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
620 if (err)
621 return err;
622 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
623 if (err)
624 goto err_port_allow_untagged_set;
625 }
626
627 mlxsw_sp_port->pvid = vid;
628 return 0;
629
630err_port_allow_untagged_set:
631 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
632 return err;
633}
634
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200635static int
636mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
637{
638 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
639 char sspr_pl[MLXSW_REG_SSPR_LEN];
640
641 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
642 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
643}
644
Ido Schimmeld664b412016-06-09 09:51:40 +0200645static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
646 u8 local_port, u8 *p_module,
647 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200648{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200649 char pmlp_pl[MLXSW_REG_PMLP_LEN];
650 int err;
651
Ido Schimmel558c2d52016-02-26 17:32:29 +0100652 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200653 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
654 if (err)
655 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100656 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
657 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200658 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200659 return 0;
660}
661
Ido Schimmel2e915e02017-06-08 08:47:45 +0200662static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100663 u8 module, u8 width, u8 lane)
664{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200665 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel18f1e702016-02-26 17:32:31 +0100666 char pmlp_pl[MLXSW_REG_PMLP_LEN];
667 int i;
668
Ido Schimmel2e915e02017-06-08 08:47:45 +0200669 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel18f1e702016-02-26 17:32:31 +0100670 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
671 for (i = 0; i < width; i++) {
672 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
673 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
674 }
675
676 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
677}
678
Ido Schimmel2e915e02017-06-08 08:47:45 +0200679static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100680{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200681 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100682 char pmlp_pl[MLXSW_REG_PMLP_LEN];
683
Ido Schimmel2e915e02017-06-08 08:47:45 +0200684 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100685 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
686 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
687}
688
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200689static int mlxsw_sp_port_open(struct net_device *dev)
690{
691 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
692 int err;
693
694 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
695 if (err)
696 return err;
697 netif_start_queue(dev);
698 return 0;
699}
700
701static int mlxsw_sp_port_stop(struct net_device *dev)
702{
703 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
704
705 netif_stop_queue(dev);
706 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
707}
708
709static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
710 struct net_device *dev)
711{
712 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
713 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
714 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
715 const struct mlxsw_tx_info tx_info = {
716 .local_port = mlxsw_sp_port->local_port,
717 .is_emad = false,
718 };
719 u64 len;
720 int err;
721
Jiri Pirko307c2432016-04-08 19:11:22 +0200722 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200723 return NETDEV_TX_BUSY;
724
725 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
726 struct sk_buff *skb_orig = skb;
727
728 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
729 if (!skb) {
730 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
731 dev_kfree_skb_any(skb_orig);
732 return NETDEV_TX_OK;
733 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +0100734 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200735 }
736
737 if (eth_skb_pad(skb)) {
738 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
739 return NETDEV_TX_OK;
740 }
741
742 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +0200743 /* TX header is consumed by HW on the way so we shouldn't count its
744 * bytes as being sent.
745 */
746 len = skb->len - MLXSW_TXHDR_LEN;
747
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200748 /* Due to a race we might fail here because of a full queue. In that
749 * unlikely case we simply drop the packet.
750 */
Jiri Pirko307c2432016-04-08 19:11:22 +0200751 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200752
753 if (!err) {
754 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
755 u64_stats_update_begin(&pcpu_stats->syncp);
756 pcpu_stats->tx_packets++;
757 pcpu_stats->tx_bytes += len;
758 u64_stats_update_end(&pcpu_stats->syncp);
759 } else {
760 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
761 dev_kfree_skb_any(skb);
762 }
763 return NETDEV_TX_OK;
764}
765
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100766static void mlxsw_sp_set_rx_mode(struct net_device *dev)
767{
768}
769
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200770static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
771{
772 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
773 struct sockaddr *addr = p;
774 int err;
775
776 if (!is_valid_ether_addr(addr->sa_data))
777 return -EADDRNOTAVAIL;
778
779 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
780 if (err)
781 return err;
782 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
783 return 0;
784}
785
Ido Schimmel18281f22017-03-24 08:02:51 +0100786static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
787 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200788{
Ido Schimmel18281f22017-03-24 08:02:51 +0100789 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100790}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200791
Ido Schimmelf417f042017-03-24 08:02:50 +0100792#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +0100793
794static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
795 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +0100796{
Ido Schimmel18281f22017-03-24 08:02:51 +0100797 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
798 BITS_PER_BYTE));
799 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
800 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100801}
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200802
Ido Schimmel18281f22017-03-24 08:02:51 +0100803/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +0100804 * Assumes 100m cable and maximum MTU.
805 */
Ido Schimmel18281f22017-03-24 08:02:51 +0100806#define MLXSW_SP_PAUSE_DELAY 58752
807
808static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
809 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +0100810{
811 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +0100812 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +0100813 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +0100814 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200815 else
Ido Schimmelf417f042017-03-24 08:02:50 +0100816 return 0;
817}
818
819static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
820 bool lossy)
821{
822 if (lossy)
823 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
824 else
825 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
826 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200827}
828
829int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200830 u8 *prio_tc, bool pause_en,
831 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +0200832{
833 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200834 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
835 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200836 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200837 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200838
839 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
840 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
841 if (err)
842 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200843
844 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
845 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200846 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +0100847 bool lossy;
848 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200849
850 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
851 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200852 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200853 configure = true;
854 break;
855 }
856 }
857
858 if (!configure)
859 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +0100860
861 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +0100862 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
863 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
864 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +0100865 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200866 }
867
Ido Schimmelff6551e2016-04-06 17:10:03 +0200868 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
869}
870
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200871static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200872 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200873{
874 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
875 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200876 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200877 u8 *prio_tc;
878
879 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200880 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200881
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200882 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200883 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200884}
885
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200886static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
887{
888 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200889 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200890 int err;
891
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200892 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200893 if (err)
894 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200895 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
896 if (err)
897 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200898 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
899 if (err)
900 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200901 dev->mtu = mtu;
902 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200903
904err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +0200905 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
906err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200907 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +0200908 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200909}
910
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +0300911static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200912mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
913 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200914{
915 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
916 struct mlxsw_sp_port_pcpu_stats *p;
917 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
918 u32 tx_dropped = 0;
919 unsigned int start;
920 int i;
921
922 for_each_possible_cpu(i) {
923 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
924 do {
925 start = u64_stats_fetch_begin_irq(&p->syncp);
926 rx_packets = p->rx_packets;
927 rx_bytes = p->rx_bytes;
928 tx_packets = p->tx_packets;
929 tx_bytes = p->tx_bytes;
930 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
931
932 stats->rx_packets += rx_packets;
933 stats->rx_bytes += rx_bytes;
934 stats->tx_packets += tx_packets;
935 stats->tx_bytes += tx_bytes;
936 /* tx_dropped is u32, updated without syncp protection. */
937 tx_dropped += p->tx_dropped;
938 }
939 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200940 return 0;
941}
942
Or Gerlitz3df5b3c2016-11-22 23:09:54 +0200943static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200944{
945 switch (attr_id) {
946 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
947 return true;
948 }
949
950 return false;
951}
952
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +0300953static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
954 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200955{
956 switch (attr_id) {
957 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
958 return mlxsw_sp_port_get_sw_stats64(dev, sp);
959 }
960
961 return -EINVAL;
962}
963
964static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
965 int prio, char *ppcnt_pl)
966{
967 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
968 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
969
970 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
971 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
972}
973
974static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
975 struct rtnl_link_stats64 *stats)
976{
977 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
978 int err;
979
980 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
981 0, ppcnt_pl);
982 if (err)
983 goto out;
984
985 stats->tx_packets =
986 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
987 stats->rx_packets =
988 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
989 stats->tx_bytes =
990 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
991 stats->rx_bytes =
992 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
993 stats->multicast =
994 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
995
996 stats->rx_crc_errors =
997 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
998 stats->rx_frame_errors =
999 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1000
1001 stats->rx_length_errors = (
1002 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1003 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1004 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1005
1006 stats->rx_errors = (stats->rx_crc_errors +
1007 stats->rx_frame_errors + stats->rx_length_errors);
1008
1009out:
1010 return err;
1011}
1012
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001013static void
1014mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1015 struct mlxsw_sp_port_xstats *xstats)
1016{
1017 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1018 int err, i;
1019
1020 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1021 ppcnt_pl);
1022 if (!err)
1023 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1024
1025 for (i = 0; i < TC_MAX_QUEUE; i++) {
1026 err = mlxsw_sp_port_get_stats_raw(dev,
1027 MLXSW_REG_PPCNT_TC_CONG_TC,
1028 i, ppcnt_pl);
1029 if (!err)
1030 xstats->wred_drop[i] =
1031 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1032
1033 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1034 i, ppcnt_pl);
1035 if (err)
1036 continue;
1037
1038 xstats->backlog[i] =
1039 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1040 xstats->tail_drop[i] =
1041 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1042 }
Nogah Frankel2f880472018-02-28 10:44:59 +01001043
1044 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1045 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
1046 i, ppcnt_pl);
1047 if (err)
1048 continue;
1049
1050 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
1051 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
1052 }
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001053}
1054
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001055static void update_stats_cache(struct work_struct *work)
1056{
1057 struct mlxsw_sp_port *mlxsw_sp_port =
1058 container_of(work, struct mlxsw_sp_port,
Nogah Frankel9deef432017-10-26 10:55:32 +02001059 periodic_hw_stats.update_dw.work);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001060
1061 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1062 goto out;
1063
1064 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
Nogah Frankel9deef432017-10-26 10:55:32 +02001065 &mlxsw_sp_port->periodic_hw_stats.stats);
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001066 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1067 &mlxsw_sp_port->periodic_hw_stats.xstats);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001068
1069out:
Nogah Frankel9deef432017-10-26 10:55:32 +02001070 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001071 MLXSW_HW_STATS_UPDATE_TIME);
1072}
1073
1074/* Return the stats from a cache that is updated periodically,
1075 * as this function might get called in an atomic context.
1076 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001077static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001078mlxsw_sp_port_get_stats64(struct net_device *dev,
1079 struct rtnl_link_stats64 *stats)
1080{
1081 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1082
Nogah Frankel9deef432017-10-26 10:55:32 +02001083 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001084}
1085
Jiri Pirko93cd0812017-04-18 16:55:35 +02001086static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1087 u16 vid_begin, u16 vid_end,
1088 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001089{
1090 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1091 char *spvm_pl;
1092 int err;
1093
1094 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1095 if (!spvm_pl)
1096 return -ENOMEM;
1097
1098 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1099 vid_end, is_member, untagged);
1100 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1101 kfree(spvm_pl);
1102 return err;
1103}
1104
Jiri Pirko93cd0812017-04-18 16:55:35 +02001105int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1106 u16 vid_end, bool is_member, bool untagged)
1107{
1108 u16 vid, vid_e;
1109 int err;
1110
1111 for (vid = vid_begin; vid <= vid_end;
1112 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1113 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1114 vid_end);
1115
1116 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1117 is_member, untagged);
1118 if (err)
1119 return err;
1120 }
1121
1122 return 0;
1123}
1124
Ido Schimmelc57529e2017-05-26 08:37:31 +02001125static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001126{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001127 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001128
Ido Schimmelc57529e2017-05-26 08:37:31 +02001129 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1130 &mlxsw_sp_port->vlans_list, list)
1131 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001132}
1133
Ido Schimmel31a08a52017-05-26 08:37:26 +02001134static struct mlxsw_sp_port_vlan *
1135mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1136{
1137 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001138 bool untagged = vid == 1;
1139 int err;
1140
1141 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1142 if (err)
1143 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001144
1145 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001146 if (!mlxsw_sp_port_vlan) {
1147 err = -ENOMEM;
1148 goto err_port_vlan_alloc;
1149 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02001150
1151 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
Ido Schimmelb3529af2018-02-28 13:12:11 +01001152 mlxsw_sp_port_vlan->ref_count = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02001153 mlxsw_sp_port_vlan->vid = vid;
1154 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1155
1156 return mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001157
1158err_port_vlan_alloc:
1159 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1160 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001161}
1162
1163static void
1164mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1165{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001166 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1167 u16 vid = mlxsw_sp_port_vlan->vid;
Ido Schimmel7cbecf22017-05-26 08:37:28 +02001168
Ido Schimmel31a08a52017-05-26 08:37:26 +02001169 list_del(&mlxsw_sp_port_vlan->list);
1170 kfree(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001171 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1172}
1173
1174struct mlxsw_sp_port_vlan *
1175mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1176{
1177 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1178
1179 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelb3529af2018-02-28 13:12:11 +01001180 if (mlxsw_sp_port_vlan) {
1181 mlxsw_sp_port_vlan->ref_count++;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001182 return mlxsw_sp_port_vlan;
Ido Schimmelb3529af2018-02-28 13:12:11 +01001183 }
Ido Schimmelc57529e2017-05-26 08:37:31 +02001184
1185 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1186}
1187
1188void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1189{
Ido Schimmela1107482017-05-26 08:37:39 +02001190 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1191
Ido Schimmelb3529af2018-02-28 13:12:11 +01001192 if (--mlxsw_sp_port_vlan->ref_count != 0)
1193 return;
1194
Ido Schimmelc57529e2017-05-26 08:37:31 +02001195 if (mlxsw_sp_port_vlan->bridge_port)
1196 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
Ido Schimmela1107482017-05-26 08:37:39 +02001197 else if (fid)
1198 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001199
1200 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001201}
1202
Ido Schimmel05978482016-08-17 16:39:30 +02001203static int mlxsw_sp_port_add_vid(struct net_device *dev,
1204 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001205{
1206 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001207
1208 /* VLAN 0 is added to HW filter when device goes up, but it is
1209 * reserved in our case, so simply return.
1210 */
1211 if (!vid)
1212 return 0;
1213
Ido Schimmelc57529e2017-05-26 08:37:31 +02001214 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001215}
1216
Ido Schimmel32d863f2016-07-02 11:00:10 +02001217static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1218 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001219{
1220 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001221 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001222
1223 /* VLAN 0 is removed from HW filter when device goes down, but
1224 * it is reserved in our case, so simply return.
1225 */
1226 if (!vid)
1227 return 0;
1228
Ido Schimmel31a08a52017-05-26 08:37:26 +02001229 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001230 if (!mlxsw_sp_port_vlan)
Ido Schimmel31a08a52017-05-26 08:37:26 +02001231 return 0;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001232 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001233
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001234 return 0;
1235}
1236
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001237static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1238 size_t len)
1239{
1240 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +02001241 u8 module = mlxsw_sp_port->mapping.module;
1242 u8 width = mlxsw_sp_port->mapping.width;
1243 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001244 int err;
1245
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001246 if (!mlxsw_sp_port->split)
1247 err = snprintf(name, len, "p%d", module + 1);
1248 else
1249 err = snprintf(name, len, "p%ds%d", module + 1,
1250 lane / width);
1251
1252 if (err >= len)
1253 return -EINVAL;
1254
1255 return 0;
1256}
1257
Yotam Gigi763b4b72016-07-21 12:03:17 +02001258static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001259mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1260 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001261 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1262
1263 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1264 if (mall_tc_entry->cookie == cookie)
1265 return mall_tc_entry;
1266
1267 return NULL;
1268}
1269
1270static int
1271mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001272 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001273 const struct tc_action *a,
1274 bool ingress)
1275{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001276 enum mlxsw_sp_span_type span_type;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001277 struct net_device *to_dev;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001278
Cong Wang9f8a7392017-12-05 16:17:26 -08001279 to_dev = tcf_mirred_dev(a);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001280 if (!to_dev) {
1281 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1282 return -EINVAL;
1283 }
1284
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001285 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001286 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Petr Machata079c9f32018-02-27 14:53:44 +01001287 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type,
Petr Machata98977082018-02-27 14:53:41 +01001288 true, &mirror->span_id);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001289}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001290
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001291static void
1292mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1293 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1294{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001295 enum mlxsw_sp_span_type span_type;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001296
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001297 span_type = mirror->ingress ?
1298 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Petr Machata98977082018-02-27 14:53:41 +01001299 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +01001300 span_type, true);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001301}
1302
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001303static int
1304mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1305 struct tc_cls_matchall_offload *cls,
1306 const struct tc_action *a,
1307 bool ingress)
1308{
1309 int err;
1310
1311 if (!mlxsw_sp_port->sample)
1312 return -EOPNOTSUPP;
1313 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1314 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1315 return -EEXIST;
1316 }
1317 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1318 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1319 return -EOPNOTSUPP;
1320 }
1321
1322 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1323 tcf_sample_psample_group(a));
1324 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1325 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1326 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1327
1328 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1329 if (err)
1330 goto err_port_sample_set;
1331 return 0;
1332
1333err_port_sample_set:
1334 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1335 return err;
1336}
1337
1338static void
1339mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1340{
1341 if (!mlxsw_sp_port->sample)
1342 return;
1343
1344 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1345 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1346}
1347
Yotam Gigi763b4b72016-07-21 12:03:17 +02001348static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001349 struct tc_cls_matchall_offload *f,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001350 bool ingress)
1351{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001352 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001353 __be16 protocol = f->common.protocol;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001354 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001355 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001356 int err;
1357
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001358 if (!tcf_exts_has_one_action(f->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001359 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001360 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001361 }
1362
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001363 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1364 if (!mall_tc_entry)
1365 return -ENOMEM;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001366 mall_tc_entry->cookie = f->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001367
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001368 tcf_exts_to_list(f->exts, &actions);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001369 a = list_first_entry(&actions, struct tc_action, list);
1370
1371 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1372 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1373
1374 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1375 mirror = &mall_tc_entry->mirror;
1376 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1377 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001378 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1379 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001380 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001381 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001382 } else {
1383 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001384 }
1385
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001386 if (err)
1387 goto err_add_action;
1388
1389 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001390 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001391
1392err_add_action:
1393 kfree(mall_tc_entry);
1394 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001395}
1396
1397static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001398 struct tc_cls_matchall_offload *f)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001399{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001400 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001401
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001402 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001403 f->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001404 if (!mall_tc_entry) {
1405 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1406 return;
1407 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001408 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001409
1410 switch (mall_tc_entry->type) {
1411 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001412 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1413 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001414 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001415 case MLXSW_SP_PORT_MALL_SAMPLE:
1416 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1417 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001418 default:
1419 WARN_ON(1);
1420 }
1421
Yotam Gigi763b4b72016-07-21 12:03:17 +02001422 kfree(mall_tc_entry);
1423}
1424
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001425static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001426 struct tc_cls_matchall_offload *f,
1427 bool ingress)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001428{
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001429 switch (f->command) {
1430 case TC_CLSMATCHALL_REPLACE:
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001431 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001432 ingress);
1433 case TC_CLSMATCHALL_DESTROY:
1434 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1435 return 0;
1436 default:
1437 return -EOPNOTSUPP;
1438 }
1439}
1440
1441static int
Jiri Pirko3aaff322018-01-17 11:46:56 +01001442mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1443 struct tc_cls_flower_offload *f)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001444{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001445 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1446
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001447 switch (f->command) {
1448 case TC_CLSFLOWER_REPLACE:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001449 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001450 case TC_CLSFLOWER_DESTROY:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001451 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001452 return 0;
1453 case TC_CLSFLOWER_STATS:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001454 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001455 default:
1456 return -EOPNOTSUPP;
1457 }
1458}
1459
Jiri Pirko3aaff322018-01-17 11:46:56 +01001460static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1461 void *type_data,
1462 void *cb_priv, bool ingress)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001463{
1464 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1465
1466 switch (type) {
1467 case TC_SETUP_CLSMATCHALL:
Jakub Kicinski15f4edb2018-01-25 14:00:51 -08001468 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1469 type_data))
Jiri Pirko3aaff322018-01-17 11:46:56 +01001470 return -EOPNOTSUPP;
1471
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001472 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1473 ingress);
1474 case TC_SETUP_CLSFLOWER:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001475 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001476 default:
1477 return -EOPNOTSUPP;
1478 }
1479}
1480
Jiri Pirko3aaff322018-01-17 11:46:56 +01001481static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1482 void *type_data,
1483 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001484{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001485 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1486 cb_priv, true);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001487}
1488
Jiri Pirko3aaff322018-01-17 11:46:56 +01001489static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1490 void *type_data,
1491 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001492{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001493 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1494 cb_priv, false);
1495}
1496
1497static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1498 void *type_data, void *cb_priv)
1499{
1500 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1501
1502 switch (type) {
1503 case TC_SETUP_CLSMATCHALL:
1504 return 0;
1505 case TC_SETUP_CLSFLOWER:
1506 if (mlxsw_sp_acl_block_disabled(acl_block))
1507 return -EOPNOTSUPP;
1508
1509 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1510 default:
1511 return -EOPNOTSUPP;
1512 }
1513}
1514
1515static int
1516mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1517 struct tcf_block *block, bool ingress)
1518{
1519 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1520 struct mlxsw_sp_acl_block *acl_block;
1521 struct tcf_block_cb *block_cb;
1522 int err;
1523
1524 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1525 mlxsw_sp);
1526 if (!block_cb) {
1527 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1528 if (!acl_block)
1529 return -ENOMEM;
1530 block_cb = __tcf_block_cb_register(block,
1531 mlxsw_sp_setup_tc_block_cb_flower,
1532 mlxsw_sp, acl_block);
1533 if (IS_ERR(block_cb)) {
1534 err = PTR_ERR(block_cb);
1535 goto err_cb_register;
1536 }
1537 } else {
1538 acl_block = tcf_block_cb_priv(block_cb);
1539 }
1540 tcf_block_cb_incref(block_cb);
1541 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1542 mlxsw_sp_port, ingress);
1543 if (err)
1544 goto err_block_bind;
1545
1546 if (ingress)
1547 mlxsw_sp_port->ing_acl_block = acl_block;
1548 else
1549 mlxsw_sp_port->eg_acl_block = acl_block;
1550
1551 return 0;
1552
1553err_block_bind:
1554 if (!tcf_block_cb_decref(block_cb)) {
1555 __tcf_block_cb_unregister(block_cb);
1556err_cb_register:
1557 mlxsw_sp_acl_block_destroy(acl_block);
1558 }
1559 return err;
1560}
1561
1562static void
1563mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1564 struct tcf_block *block, bool ingress)
1565{
1566 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1567 struct mlxsw_sp_acl_block *acl_block;
1568 struct tcf_block_cb *block_cb;
1569 int err;
1570
1571 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1572 mlxsw_sp);
1573 if (!block_cb)
1574 return;
1575
1576 if (ingress)
1577 mlxsw_sp_port->ing_acl_block = NULL;
1578 else
1579 mlxsw_sp_port->eg_acl_block = NULL;
1580
1581 acl_block = tcf_block_cb_priv(block_cb);
1582 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1583 mlxsw_sp_port, ingress);
1584 if (!err && !tcf_block_cb_decref(block_cb)) {
1585 __tcf_block_cb_unregister(block_cb);
1586 mlxsw_sp_acl_block_destroy(acl_block);
1587 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001588}
1589
1590static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1591 struct tc_block_offload *f)
1592{
1593 tc_setup_cb_t *cb;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001594 bool ingress;
1595 int err;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001596
Jiri Pirko3aaff322018-01-17 11:46:56 +01001597 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1598 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1599 ingress = true;
1600 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1601 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1602 ingress = false;
1603 } else {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001604 return -EOPNOTSUPP;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001605 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001606
1607 switch (f->command) {
1608 case TC_BLOCK_BIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001609 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1610 mlxsw_sp_port);
1611 if (err)
1612 return err;
1613 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
1614 f->block, ingress);
1615 if (err) {
1616 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1617 return err;
1618 }
1619 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001620 case TC_BLOCK_UNBIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001621 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1622 f->block, ingress);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001623 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1624 return 0;
1625 default:
1626 return -EOPNOTSUPP;
1627 }
1628}
1629
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001630static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
Jiri Pirkode4784c2017-08-07 10:15:32 +02001631 void *type_data)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001632{
1633 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1634
Jiri Pirko2572ac52017-08-07 10:15:17 +02001635 switch (type) {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001636 case TC_SETUP_BLOCK:
1637 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
Nogah Frankel96f17e02017-11-06 07:23:45 +01001638 case TC_SETUP_QDISC_RED:
1639 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
Nogah Frankel46a36152018-01-14 12:33:16 +01001640 case TC_SETUP_QDISC_PRIO:
1641 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
Jiri Pirko2572ac52017-08-07 10:15:17 +02001642 default:
1643 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001644 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001645}
1646
Jiri Pirko9454d932017-12-06 09:41:12 +01001647
1648static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1649{
1650 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1651
Jiri Pirko3aaff322018-01-17 11:46:56 +01001652 if (!enable) {
1653 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1654 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1655 !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1656 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1657 return -EINVAL;
1658 }
1659 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1660 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1661 } else {
1662 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1663 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
Jiri Pirko9454d932017-12-06 09:41:12 +01001664 }
1665 return 0;
1666}
1667
1668typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1669
1670static int mlxsw_sp_handle_feature(struct net_device *dev,
1671 netdev_features_t wanted_features,
1672 netdev_features_t feature,
1673 mlxsw_sp_feature_handler feature_handler)
1674{
1675 netdev_features_t changes = wanted_features ^ dev->features;
1676 bool enable = !!(wanted_features & feature);
1677 int err;
1678
1679 if (!(changes & feature))
1680 return 0;
1681
1682 err = feature_handler(dev, enable);
1683 if (err) {
1684 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1685 enable ? "Enable" : "Disable", &feature, err);
1686 return err;
1687 }
1688
1689 if (enable)
1690 dev->features |= feature;
1691 else
1692 dev->features &= ~feature;
1693
1694 return 0;
1695}
1696static int mlxsw_sp_set_features(struct net_device *dev,
1697 netdev_features_t features)
1698{
1699 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1700 mlxsw_sp_feature_hw_tc);
1701}
1702
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001703static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1704 .ndo_open = mlxsw_sp_port_open,
1705 .ndo_stop = mlxsw_sp_port_stop,
1706 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001707 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001708 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001709 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1710 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1711 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001712 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1713 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001714 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1715 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001716 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko9454d932017-12-06 09:41:12 +01001717 .ndo_set_features = mlxsw_sp_set_features,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001718};
1719
1720static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1721 struct ethtool_drvinfo *drvinfo)
1722{
1723 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1724 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1725
1726 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1727 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1728 sizeof(drvinfo->version));
1729 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1730 "%d.%d.%d",
1731 mlxsw_sp->bus_info->fw_rev.major,
1732 mlxsw_sp->bus_info->fw_rev.minor,
1733 mlxsw_sp->bus_info->fw_rev.subminor);
1734 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1735 sizeof(drvinfo->bus_info));
1736}
1737
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001738static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1739 struct ethtool_pauseparam *pause)
1740{
1741 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1742
1743 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1744 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1745}
1746
1747static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1748 struct ethtool_pauseparam *pause)
1749{
1750 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1751
1752 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1753 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1754 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1755
1756 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1757 pfcc_pl);
1758}
1759
1760static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1761 struct ethtool_pauseparam *pause)
1762{
1763 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1764 bool pause_en = pause->tx_pause || pause->rx_pause;
1765 int err;
1766
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001767 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1768 netdev_err(dev, "PFC already enabled on port\n");
1769 return -EINVAL;
1770 }
1771
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001772 if (pause->autoneg) {
1773 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1774 return -EINVAL;
1775 }
1776
1777 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1778 if (err) {
1779 netdev_err(dev, "Failed to configure port's headroom\n");
1780 return err;
1781 }
1782
1783 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1784 if (err) {
1785 netdev_err(dev, "Failed to set PAUSE parameters\n");
1786 goto err_port_pause_configure;
1787 }
1788
1789 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1790 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1791
1792 return 0;
1793
1794err_port_pause_configure:
1795 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1796 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1797 return err;
1798}
1799
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001800struct mlxsw_sp_port_hw_stats {
1801 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02001802 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01001803 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001804};
1805
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001806static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001807 {
1808 .str = "a_frames_transmitted_ok",
1809 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1810 },
1811 {
1812 .str = "a_frames_received_ok",
1813 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1814 },
1815 {
1816 .str = "a_frame_check_sequence_errors",
1817 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1818 },
1819 {
1820 .str = "a_alignment_errors",
1821 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1822 },
1823 {
1824 .str = "a_octets_transmitted_ok",
1825 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1826 },
1827 {
1828 .str = "a_octets_received_ok",
1829 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1830 },
1831 {
1832 .str = "a_multicast_frames_xmitted_ok",
1833 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1834 },
1835 {
1836 .str = "a_broadcast_frames_xmitted_ok",
1837 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1838 },
1839 {
1840 .str = "a_multicast_frames_received_ok",
1841 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1842 },
1843 {
1844 .str = "a_broadcast_frames_received_ok",
1845 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1846 },
1847 {
1848 .str = "a_in_range_length_errors",
1849 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1850 },
1851 {
1852 .str = "a_out_of_range_length_field",
1853 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1854 },
1855 {
1856 .str = "a_frame_too_long_errors",
1857 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1858 },
1859 {
1860 .str = "a_symbol_error_during_carrier",
1861 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1862 },
1863 {
1864 .str = "a_mac_control_frames_transmitted",
1865 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1866 },
1867 {
1868 .str = "a_mac_control_frames_received",
1869 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1870 },
1871 {
1872 .str = "a_unsupported_opcodes_received",
1873 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1874 },
1875 {
1876 .str = "a_pause_mac_ctrl_frames_received",
1877 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1878 },
1879 {
1880 .str = "a_pause_mac_ctrl_frames_xmitted",
1881 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1882 },
1883};
1884
1885#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1886
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001887static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1888 {
1889 .str = "rx_octets_prio",
1890 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1891 },
1892 {
1893 .str = "rx_frames_prio",
1894 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1895 },
1896 {
1897 .str = "tx_octets_prio",
1898 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1899 },
1900 {
1901 .str = "tx_frames_prio",
1902 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1903 },
1904 {
1905 .str = "rx_pause_prio",
1906 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1907 },
1908 {
1909 .str = "rx_pause_duration_prio",
1910 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1911 },
1912 {
1913 .str = "tx_pause_prio",
1914 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1915 },
1916 {
1917 .str = "tx_pause_duration_prio",
1918 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1919 },
1920};
1921
1922#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1923
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001924static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1925 {
1926 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01001927 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1928 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001929 },
1930 {
1931 .str = "tc_no_buffer_discard_uc_tc",
1932 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1933 },
1934};
1935
1936#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1937
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001938#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001939 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1940 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001941 IEEE_8021QAZ_MAX_TCS)
1942
1943static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1944{
1945 int i;
1946
1947 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1948 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1949 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1950 *p += ETH_GSTRING_LEN;
1951 }
1952}
1953
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001954static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1955{
1956 int i;
1957
1958 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1959 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1960 mlxsw_sp_port_hw_tc_stats[i].str, tc);
1961 *p += ETH_GSTRING_LEN;
1962 }
1963}
1964
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001965static void mlxsw_sp_port_get_strings(struct net_device *dev,
1966 u32 stringset, u8 *data)
1967{
1968 u8 *p = data;
1969 int i;
1970
1971 switch (stringset) {
1972 case ETH_SS_STATS:
1973 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1974 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1975 ETH_GSTRING_LEN);
1976 p += ETH_GSTRING_LEN;
1977 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001978
1979 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1980 mlxsw_sp_port_get_prio_strings(&p, i);
1981
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001982 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1983 mlxsw_sp_port_get_tc_strings(&p, i);
1984
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001985 break;
1986 }
1987}
1988
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001989static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1990 enum ethtool_phys_id_state state)
1991{
1992 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1993 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1994 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1995 bool active;
1996
1997 switch (state) {
1998 case ETHTOOL_ID_ACTIVE:
1999 active = true;
2000 break;
2001 case ETHTOOL_ID_INACTIVE:
2002 active = false;
2003 break;
2004 default:
2005 return -EOPNOTSUPP;
2006 }
2007
2008 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2009 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2010}
2011
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002012static int
2013mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2014 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2015{
2016 switch (grp) {
2017 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2018 *p_hw_stats = mlxsw_sp_port_hw_stats;
2019 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2020 break;
2021 case MLXSW_REG_PPCNT_PRIO_CNT:
2022 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2023 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2024 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002025 case MLXSW_REG_PPCNT_TC_CNT:
2026 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2027 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2028 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002029 default:
2030 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002031 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002032 }
2033 return 0;
2034}
2035
2036static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2037 enum mlxsw_reg_ppcnt_grp grp, int prio,
2038 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002039{
Ido Schimmel18281f22017-03-24 08:02:51 +01002040 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2041 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002042 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002043 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002044 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002045 int err;
2046
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002047 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2048 if (err)
2049 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002050 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002051 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002052 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002053 if (!hw_stats[i].cells_bytes)
2054 continue;
2055 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2056 data[data_index + i]);
2057 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002058}
2059
2060static void mlxsw_sp_port_get_stats(struct net_device *dev,
2061 struct ethtool_stats *stats, u64 *data)
2062{
2063 int i, data_index = 0;
2064
2065 /* IEEE 802.3 Counters */
2066 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2067 data, data_index);
2068 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2069
2070 /* Per-Priority Counters */
2071 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2072 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2073 data, data_index);
2074 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2075 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002076
2077 /* Per-TC Counters */
2078 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2079 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2080 data, data_index);
2081 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2082 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002083}
2084
2085static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2086{
2087 switch (sset) {
2088 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002089 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002090 default:
2091 return -EOPNOTSUPP;
2092 }
2093}
2094
2095struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002096 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002097 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002098 u32 speed;
2099};
2100
2101static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2102 {
2103 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002104 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2105 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002106 },
2107 {
2108 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2109 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002110 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2111 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002112 },
2113 {
2114 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002115 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2116 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002117 },
2118 {
2119 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2120 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002121 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2122 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002123 },
2124 {
2125 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2126 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2127 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2128 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002129 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2130 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002131 },
2132 {
2133 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002134 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2135 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002136 },
2137 {
2138 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002139 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2140 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002141 },
2142 {
2143 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002144 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2145 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002146 },
2147 {
2148 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002149 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2150 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002151 },
2152 {
2153 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002154 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2155 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002156 },
2157 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002158 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2159 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2160 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002161 },
2162 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002163 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2164 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2165 .speed = SPEED_25000,
2166 },
2167 {
2168 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2169 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2170 .speed = SPEED_25000,
2171 },
2172 {
2173 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2174 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2175 .speed = SPEED_25000,
2176 },
2177 {
2178 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2179 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2180 .speed = SPEED_50000,
2181 },
2182 {
2183 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2184 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2185 .speed = SPEED_50000,
2186 },
2187 {
2188 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2189 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2190 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002191 },
2192 {
2193 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002194 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2195 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002196 },
2197 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002198 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2199 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2200 .speed = SPEED_56000,
2201 },
2202 {
2203 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2204 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2205 .speed = SPEED_56000,
2206 },
2207 {
2208 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2209 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2210 .speed = SPEED_56000,
2211 },
2212 {
2213 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2214 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2215 .speed = SPEED_100000,
2216 },
2217 {
2218 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2219 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2220 .speed = SPEED_100000,
2221 },
2222 {
2223 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2224 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2225 .speed = SPEED_100000,
2226 },
2227 {
2228 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2229 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2230 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002231 },
2232};
2233
2234#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2235
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002236static void
2237mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2238 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002239{
2240 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2241 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2242 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2243 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2244 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2245 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002246 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002247
2248 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2249 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2250 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2251 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2252 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002253 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002254}
2255
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002256static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002257{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002258 int i;
2259
2260 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2261 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002262 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2263 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002264 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002265}
2266
2267static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002268 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002269{
2270 u32 speed = SPEED_UNKNOWN;
2271 u8 duplex = DUPLEX_UNKNOWN;
2272 int i;
2273
2274 if (!carrier_ok)
2275 goto out;
2276
2277 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2278 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2279 speed = mlxsw_sp_port_link_mode[i].speed;
2280 duplex = DUPLEX_FULL;
2281 break;
2282 }
2283 }
2284out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002285 cmd->base.speed = speed;
2286 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002287}
2288
2289static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2290{
2291 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2292 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2293 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2294 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2295 return PORT_FIBRE;
2296
2297 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2298 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2299 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2300 return PORT_DA;
2301
2302 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2303 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2304 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2305 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2306 return PORT_NONE;
2307
2308 return PORT_OTHER;
2309}
2310
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002311static u32
2312mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002313{
2314 u32 ptys_proto = 0;
2315 int i;
2316
2317 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002318 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2319 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002320 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2321 }
2322 return ptys_proto;
2323}
2324
2325static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2326{
2327 u32 ptys_proto = 0;
2328 int i;
2329
2330 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2331 if (speed == mlxsw_sp_port_link_mode[i].speed)
2332 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2333 }
2334 return ptys_proto;
2335}
2336
Ido Schimmel18f1e702016-02-26 17:32:31 +01002337static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2338{
2339 u32 ptys_proto = 0;
2340 int i;
2341
2342 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2343 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2344 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2345 }
2346 return ptys_proto;
2347}
2348
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002349static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2350 struct ethtool_link_ksettings *cmd)
2351{
2352 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2353 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2354 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2355
2356 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2357 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2358}
2359
2360static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2361 struct ethtool_link_ksettings *cmd)
2362{
2363 if (!autoneg)
2364 return;
2365
2366 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2367 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2368}
2369
2370static void
2371mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2372 struct ethtool_link_ksettings *cmd)
2373{
2374 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2375 return;
2376
2377 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2378 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2379}
2380
2381static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2382 struct ethtool_link_ksettings *cmd)
2383{
2384 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2385 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2386 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2387 char ptys_pl[MLXSW_REG_PTYS_LEN];
2388 u8 autoneg_status;
2389 bool autoneg;
2390 int err;
2391
2392 autoneg = mlxsw_sp_port->link.autoneg;
Tal Bar8e1ed732018-03-21 09:34:06 +02002393 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002394 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2395 if (err)
2396 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002397 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2398 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002399
2400 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2401
2402 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2403
2404 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2405 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2406 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2407
2408 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2409 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2410 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2411 cmd);
2412
2413 return 0;
2414}
2415
2416static int
2417mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2418 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002419{
2420 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2421 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2422 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002423 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002424 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002425 int err;
2426
Tal Bar8e1ed732018-03-21 09:34:06 +02002427 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002428 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002429 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002430 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002431 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002432
2433 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2434 eth_proto_new = autoneg ?
2435 mlxsw_sp_to_ptys_advert_link(cmd) :
2436 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002437
2438 eth_proto_new = eth_proto_new & eth_proto_cap;
2439 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002440 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002441 return -EINVAL;
2442 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002443
Elad Raz401c8b42016-10-28 21:35:52 +02002444 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
Tal Bar8e1ed732018-03-21 09:34:06 +02002445 eth_proto_new, autoneg);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002446 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002447 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002448 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002449
Ido Schimmel6277d462016-07-15 11:14:58 +02002450 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002451 return 0;
2452
Ido Schimmel0c83f882016-09-12 13:26:23 +02002453 mlxsw_sp_port->link.autoneg = autoneg;
2454
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002455 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2456 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002457
2458 return 0;
2459}
2460
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002461static int mlxsw_sp_flash_device(struct net_device *dev,
2462 struct ethtool_flash *flash)
2463{
2464 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2465 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2466 const struct firmware *firmware;
2467 int err;
2468
2469 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2470 return -EOPNOTSUPP;
2471
2472 dev_hold(dev);
2473 rtnl_unlock();
2474
2475 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2476 if (err)
2477 goto out;
2478 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2479 release_firmware(firmware);
2480out:
2481 rtnl_lock();
2482 dev_put(dev);
2483 return err;
2484}
2485
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002486#define MLXSW_SP_I2C_ADDR_LOW 0x50
2487#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2488#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002489
2490static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2491 u16 offset, u16 size, void *data,
2492 unsigned int *p_read_size)
2493{
2494 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2495 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2496 char mcia_pl[MLXSW_REG_MCIA_LEN];
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002497 u16 i2c_addr;
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002498 int status;
2499 int err;
2500
2501 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002502
2503 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2504 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2505 /* Cross pages read, read until offset 256 in low page */
2506 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2507
2508 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2509 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2510 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2511 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2512 }
2513
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002514 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002515 0, 0, offset, size, i2c_addr);
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002516
2517 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2518 if (err)
2519 return err;
2520
2521 status = mlxsw_reg_mcia_status_get(mcia_pl);
2522 if (status)
2523 return -EIO;
2524
2525 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2526 memcpy(data, eeprom_tmp, size);
2527 *p_read_size = size;
2528
2529 return 0;
2530}
2531
2532enum mlxsw_sp_eeprom_module_info_rev_id {
2533 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2534 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2535 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2536};
2537
2538enum mlxsw_sp_eeprom_module_info_id {
2539 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2540 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2541 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2542 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2543};
2544
2545enum mlxsw_sp_eeprom_module_info {
2546 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2547 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2548 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2549};
2550
2551static int mlxsw_sp_get_module_info(struct net_device *netdev,
2552 struct ethtool_modinfo *modinfo)
2553{
2554 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2555 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2556 u8 module_rev_id, module_id;
2557 unsigned int read_size;
2558 int err;
2559
2560 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2561 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2562 module_info, &read_size);
2563 if (err)
2564 return err;
2565
2566 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2567 return -EIO;
2568
2569 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2570 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2571
2572 switch (module_id) {
2573 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2574 modinfo->type = ETH_MODULE_SFF_8436;
2575 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2576 break;
2577 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2578 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2579 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2580 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2581 modinfo->type = ETH_MODULE_SFF_8636;
2582 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2583 } else {
2584 modinfo->type = ETH_MODULE_SFF_8436;
2585 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2586 }
2587 break;
2588 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2589 modinfo->type = ETH_MODULE_SFF_8472;
2590 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2591 break;
2592 default:
2593 return -EINVAL;
2594 }
2595
2596 return 0;
2597}
2598
2599static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2600 struct ethtool_eeprom *ee,
2601 u8 *data)
2602{
2603 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2604 int offset = ee->offset;
2605 unsigned int read_size;
2606 int i = 0;
2607 int err;
2608
2609 if (!ee->len)
2610 return -EINVAL;
2611
2612 memset(data, 0, ee->len);
2613
2614 while (i < ee->len) {
2615 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2616 ee->len - i, data + i,
2617 &read_size);
2618 if (err) {
2619 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2620 return err;
2621 }
2622
2623 i += read_size;
2624 offset += read_size;
2625 }
2626
2627 return 0;
2628}
2629
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002630static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2631 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2632 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002633 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2634 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002635 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002636 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002637 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2638 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002639 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2640 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002641 .flash_device = mlxsw_sp_flash_device,
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002642 .get_module_info = mlxsw_sp_get_module_info,
2643 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002644};
2645
Ido Schimmel18f1e702016-02-26 17:32:31 +01002646static int
2647mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2648{
2649 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2650 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2651 char ptys_pl[MLXSW_REG_PTYS_LEN];
2652 u32 eth_proto_admin;
2653
2654 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002655 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
Tal Bar8e1ed732018-03-21 09:34:06 +02002656 eth_proto_admin, mlxsw_sp_port->link.autoneg);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002657 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2658}
2659
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002660int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2661 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2662 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002663{
2664 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2665 char qeec_pl[MLXSW_REG_QEEC_LEN];
2666
2667 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2668 next_index);
2669 mlxsw_reg_qeec_de_set(qeec_pl, true);
2670 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2671 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2672 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2673}
2674
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002675int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2676 enum mlxsw_reg_qeec_hr hr, u8 index,
2677 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002678{
2679 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2680 char qeec_pl[MLXSW_REG_QEEC_LEN];
2681
2682 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2683 next_index);
2684 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2685 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2686 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2687}
2688
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002689int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2690 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002691{
2692 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2693 char qtct_pl[MLXSW_REG_QTCT_LEN];
2694
2695 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2696 tclass);
2697 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2698}
2699
2700static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2701{
2702 int err, i;
2703
2704 /* Setup the elements hierarcy, so that each TC is linked to
2705 * one subgroup, which are all member in the same group.
2706 */
2707 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2708 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2709 0);
2710 if (err)
2711 return err;
2712 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2713 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2714 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2715 0, false, 0);
2716 if (err)
2717 return err;
2718 }
2719 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2720 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2721 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2722 false, 0);
2723 if (err)
2724 return err;
2725 }
2726
2727 /* Make sure the max shaper is disabled in all hierarcies that
2728 * support it.
2729 */
2730 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2731 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2732 MLXSW_REG_QEEC_MAS_DIS);
2733 if (err)
2734 return err;
2735 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2736 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2737 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2738 i, 0,
2739 MLXSW_REG_QEEC_MAS_DIS);
2740 if (err)
2741 return err;
2742 }
2743 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2744 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2745 MLXSW_REG_QEEC_HIERARCY_TC,
2746 i, i,
2747 MLXSW_REG_QEEC_MAS_DIS);
2748 if (err)
2749 return err;
2750 }
2751
2752 /* Map all priorities to traffic class 0. */
2753 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2754 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2755 if (err)
2756 return err;
2757 }
2758
2759 return 0;
2760}
2761
Ido Schimmel5b153852017-06-08 08:47:44 +02002762static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2763 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002764{
Ido Schimmelc57529e2017-05-26 08:37:31 +02002765 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002766 struct mlxsw_sp_port *mlxsw_sp_port;
2767 struct net_device *dev;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002768 int err;
2769
Ido Schimmel5b153852017-06-08 08:47:44 +02002770 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2771 if (err) {
2772 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2773 local_port);
2774 return err;
2775 }
2776
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002777 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
Ido Schimmel5b153852017-06-08 08:47:44 +02002778 if (!dev) {
2779 err = -ENOMEM;
2780 goto err_alloc_etherdev;
2781 }
Jiri Pirkof20a91f2016-10-27 15:13:00 +02002782 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002783 mlxsw_sp_port = netdev_priv(dev);
2784 mlxsw_sp_port->dev = dev;
2785 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2786 mlxsw_sp_port->local_port = local_port;
Ido Schimmelc57529e2017-05-26 08:37:31 +02002787 mlxsw_sp_port->pvid = 1;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002788 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02002789 mlxsw_sp_port->mapping.module = module;
2790 mlxsw_sp_port->mapping.width = width;
2791 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002792 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02002793 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02002794 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002795
2796 mlxsw_sp_port->pcpu_stats =
2797 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2798 if (!mlxsw_sp_port->pcpu_stats) {
2799 err = -ENOMEM;
2800 goto err_alloc_stats;
2801 }
2802
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002803 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2804 GFP_KERNEL);
2805 if (!mlxsw_sp_port->sample) {
2806 err = -ENOMEM;
2807 goto err_alloc_sample;
2808 }
2809
Nogah Frankel9deef432017-10-26 10:55:32 +02002810 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002811 &update_stats_cache);
2812
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002813 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2814 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2815
Ido Schimmel2e915e02017-06-08 08:47:45 +02002816 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
Ido Schimmel5b153852017-06-08 08:47:44 +02002817 if (err) {
2818 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2819 mlxsw_sp_port->local_port);
2820 goto err_port_module_map;
2821 }
2822
Ido Schimmel3247ff22016-09-08 08:16:02 +02002823 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2824 if (err) {
2825 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2826 mlxsw_sp_port->local_port);
2827 goto err_port_swid_set;
2828 }
2829
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002830 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2831 if (err) {
2832 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2833 mlxsw_sp_port->local_port);
2834 goto err_dev_addr_init;
2835 }
2836
2837 netif_carrier_off(dev);
2838
2839 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02002840 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2841 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002842
Jarod Wilsond894be52016-10-20 13:55:16 -04002843 dev->min_mtu = 0;
2844 dev->max_mtu = ETH_MAX_MTU;
2845
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002846 /* Each packet needs to have a Tx header (metadata) on top all other
2847 * headers.
2848 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02002849 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002850
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002851 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2852 if (err) {
2853 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2854 mlxsw_sp_port->local_port);
2855 goto err_port_system_port_mapping_set;
2856 }
2857
Ido Schimmel18f1e702016-02-26 17:32:31 +01002858 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2859 if (err) {
2860 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2861 mlxsw_sp_port->local_port);
2862 goto err_port_speed_by_width_set;
2863 }
2864
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002865 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2866 if (err) {
2867 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2868 mlxsw_sp_port->local_port);
2869 goto err_port_mtu_set;
2870 }
2871
2872 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2873 if (err)
2874 goto err_port_admin_status_set;
2875
2876 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2877 if (err) {
2878 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2879 mlxsw_sp_port->local_port);
2880 goto err_port_buffers_init;
2881 }
2882
Ido Schimmel90183b92016-04-06 17:10:08 +02002883 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2884 if (err) {
2885 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2886 mlxsw_sp_port->local_port);
2887 goto err_port_ets_init;
2888 }
2889
Ido Schimmelf00817d2016-04-06 17:10:09 +02002890 /* ETS and buffers must be initialized before DCB. */
2891 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2892 if (err) {
2893 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2894 mlxsw_sp_port->local_port);
2895 goto err_port_dcb_init;
2896 }
2897
Ido Schimmela1107482017-05-26 08:37:39 +02002898 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
Ido Schimmel45a4a162017-05-16 19:38:35 +02002899 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02002900 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
Ido Schimmel45a4a162017-05-16 19:38:35 +02002901 mlxsw_sp_port->local_port);
Ido Schimmela1107482017-05-26 08:37:39 +02002902 goto err_port_fids_init;
Ido Schimmel45a4a162017-05-16 19:38:35 +02002903 }
2904
Nogah Frankel371b4372018-01-10 14:59:57 +01002905 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
2906 if (err) {
2907 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
2908 mlxsw_sp_port->local_port);
2909 goto err_port_qdiscs_init;
2910 }
2911
Ido Schimmelc57529e2017-05-26 08:37:31 +02002912 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
2913 if (IS_ERR(mlxsw_sp_port_vlan)) {
2914 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
Ido Schimmel05978482016-08-17 16:39:30 +02002915 mlxsw_sp_port->local_port);
Wei Yongjund86fd112017-11-06 11:11:28 +00002916 err = PTR_ERR(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002917 goto err_port_vlan_get;
Ido Schimmel05978482016-08-17 16:39:30 +02002918 }
2919
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002920 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02002921 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002922 err = register_netdev(dev);
2923 if (err) {
2924 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2925 mlxsw_sp_port->local_port);
2926 goto err_register_netdev;
2927 }
2928
Elad Razd808c7e2016-10-28 21:35:57 +02002929 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2930 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2931 module);
Nogah Frankel9deef432017-10-26 10:55:32 +02002932 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002933 return 0;
2934
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002935err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02002936 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002937 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002938 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
2939err_port_vlan_get:
Nogah Frankel371b4372018-01-10 14:59:57 +01002940 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
2941err_port_qdiscs_init:
Ido Schimmela1107482017-05-26 08:37:39 +02002942 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
2943err_port_fids_init:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03002944 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002945err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02002946err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002947err_port_buffers_init:
2948err_port_admin_status_set:
2949err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01002950err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002951err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002952err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02002953 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2954err_port_swid_set:
Ido Schimmel2e915e02017-06-08 08:47:45 +02002955 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Ido Schimmel5b153852017-06-08 08:47:44 +02002956err_port_module_map:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002957 kfree(mlxsw_sp_port->sample);
2958err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002959 free_percpu(mlxsw_sp_port->pcpu_stats);
2960err_alloc_stats:
2961 free_netdev(dev);
Ido Schimmel5b153852017-06-08 08:47:44 +02002962err_alloc_etherdev:
Jiri Pirko67963a32016-10-28 21:35:55 +02002963 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2964 return err;
2965}
2966
Ido Schimmel5b153852017-06-08 08:47:44 +02002967static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002968{
2969 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2970
Nogah Frankel9deef432017-10-26 10:55:32 +02002971 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02002972 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002973 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02002974 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002975 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002976 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Nogah Frankel371b4372018-01-10 14:59:57 +01002977 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
Ido Schimmela1107482017-05-26 08:37:39 +02002978 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002979 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01002980 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
Ido Schimmel2e915e02017-06-08 08:47:45 +02002981 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002982 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01002983 free_percpu(mlxsw_sp_port->pcpu_stats);
Ido Schimmel31a08a52017-05-26 08:37:26 +02002984 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002985 free_netdev(mlxsw_sp_port->dev);
Jiri Pirko67963a32016-10-28 21:35:55 +02002986 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2987}
2988
Jiri Pirkof83e2102016-10-28 21:35:49 +02002989static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2990{
2991 return mlxsw_sp->ports[local_port] != NULL;
2992}
2993
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002994static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2995{
2996 int i;
2997
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002998 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002999 if (mlxsw_sp_port_created(mlxsw_sp, i))
3000 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003001 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003002 kfree(mlxsw_sp->ports);
3003}
3004
3005static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3006{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003007 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02003008 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003009 size_t alloc_size;
3010 int i;
3011 int err;
3012
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003013 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003014 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3015 if (!mlxsw_sp->ports)
3016 return -ENOMEM;
3017
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003018 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3019 GFP_KERNEL);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003020 if (!mlxsw_sp->port_to_module) {
3021 err = -ENOMEM;
3022 goto err_port_to_module_alloc;
3023 }
3024
3025 for (i = 1; i < max_ports; i++) {
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003026 /* Mark as invalid */
3027 mlxsw_sp->port_to_module[i] = -1;
3028
Ido Schimmel558c2d52016-02-26 17:32:29 +01003029 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003030 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01003031 if (err)
3032 goto err_port_module_info_get;
3033 if (!width)
3034 continue;
3035 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02003036 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3037 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003038 if (err)
3039 goto err_port_create;
3040 }
3041 return 0;
3042
3043err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01003044err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003045 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003046 if (mlxsw_sp_port_created(mlxsw_sp, i))
3047 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003048 kfree(mlxsw_sp->port_to_module);
3049err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003050 kfree(mlxsw_sp->ports);
3051 return err;
3052}
3053
Ido Schimmel18f1e702016-02-26 17:32:31 +01003054static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3055{
3056 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3057
3058 return local_port - offset;
3059}
3060
Ido Schimmelbe945352016-06-09 09:51:39 +02003061static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3062 u8 module, unsigned int count)
3063{
3064 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3065 int err, i;
3066
3067 for (i = 0; i < count; i++) {
Ido Schimmelbe945352016-06-09 09:51:39 +02003068 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02003069 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02003070 if (err)
3071 goto err_port_create;
3072 }
3073
3074 return 0;
3075
3076err_port_create:
3077 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003078 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3079 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02003080 return err;
3081}
3082
3083static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3084 u8 base_port, unsigned int count)
3085{
3086 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3087 int i;
3088
3089 /* Split by four means we need to re-create two ports, otherwise
3090 * only one.
3091 */
3092 count = count / 2;
3093
3094 for (i = 0; i < count; i++) {
3095 local_port = base_port + i * 2;
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003096 if (mlxsw_sp->port_to_module[local_port] < 0)
3097 continue;
Ido Schimmelbe945352016-06-09 09:51:39 +02003098 module = mlxsw_sp->port_to_module[local_port];
3099
Ido Schimmelbe945352016-06-09 09:51:39 +02003100 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003101 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003102 }
3103}
3104
Jiri Pirkob2f10572016-04-08 19:11:23 +02003105static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3106 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003107{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003108 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003109 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003110 u8 module, cur_width, base_port;
3111 int i;
3112 int err;
3113
3114 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3115 if (!mlxsw_sp_port) {
3116 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3117 local_port);
3118 return -EINVAL;
3119 }
3120
Ido Schimmeld664b412016-06-09 09:51:40 +02003121 module = mlxsw_sp_port->mapping.module;
3122 cur_width = mlxsw_sp_port->mapping.width;
3123
Ido Schimmel18f1e702016-02-26 17:32:31 +01003124 if (count != 2 && count != 4) {
3125 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3126 return -EINVAL;
3127 }
3128
Ido Schimmel18f1e702016-02-26 17:32:31 +01003129 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3130 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3131 return -EINVAL;
3132 }
3133
3134 /* Make sure we have enough slave (even) ports for the split. */
3135 if (count == 2) {
3136 base_port = local_port;
3137 if (mlxsw_sp->ports[base_port + 1]) {
3138 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3139 return -EINVAL;
3140 }
3141 } else {
3142 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3143 if (mlxsw_sp->ports[base_port + 1] ||
3144 mlxsw_sp->ports[base_port + 3]) {
3145 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3146 return -EINVAL;
3147 }
3148 }
3149
3150 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003151 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3152 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003153
Ido Schimmelbe945352016-06-09 09:51:39 +02003154 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3155 if (err) {
3156 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3157 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003158 }
3159
3160 return 0;
3161
Ido Schimmelbe945352016-06-09 09:51:39 +02003162err_port_split_create:
3163 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003164 return err;
3165}
3166
Jiri Pirkob2f10572016-04-08 19:11:23 +02003167static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003168{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003169 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003170 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003171 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003172 unsigned int count;
3173 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003174
3175 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3176 if (!mlxsw_sp_port) {
3177 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3178 local_port);
3179 return -EINVAL;
3180 }
3181
3182 if (!mlxsw_sp_port->split) {
3183 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3184 return -EINVAL;
3185 }
3186
Ido Schimmeld664b412016-06-09 09:51:40 +02003187 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003188 count = cur_width == 1 ? 4 : 2;
3189
3190 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3191
3192 /* Determine which ports to remove. */
3193 if (count == 2 && local_port >= base_port + 2)
3194 base_port = base_port + 2;
3195
3196 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003197 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3198 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003199
Ido Schimmelbe945352016-06-09 09:51:39 +02003200 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003201
3202 return 0;
3203}
3204
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003205static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3206 char *pude_pl, void *priv)
3207{
3208 struct mlxsw_sp *mlxsw_sp = priv;
3209 struct mlxsw_sp_port *mlxsw_sp_port;
3210 enum mlxsw_reg_pude_oper_status status;
3211 u8 local_port;
3212
3213 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3214 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003215 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003216 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003217
3218 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3219 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3220 netdev_info(mlxsw_sp_port->dev, "link up\n");
3221 netif_carrier_on(mlxsw_sp_port->dev);
3222 } else {
3223 netdev_info(mlxsw_sp_port->dev, "link down\n");
3224 netif_carrier_off(mlxsw_sp_port->dev);
3225 }
3226}
3227
Nogah Frankel14eeda92016-11-25 10:33:32 +01003228static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3229 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003230{
3231 struct mlxsw_sp *mlxsw_sp = priv;
3232 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3233 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3234
3235 if (unlikely(!mlxsw_sp_port)) {
3236 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3237 local_port);
3238 return;
3239 }
3240
3241 skb->dev = mlxsw_sp_port->dev;
3242
3243 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3244 u64_stats_update_begin(&pcpu_stats->syncp);
3245 pcpu_stats->rx_packets++;
3246 pcpu_stats->rx_bytes += skb->len;
3247 u64_stats_update_end(&pcpu_stats->syncp);
3248
3249 skb->protocol = eth_type_trans(skb, skb->dev);
3250 netif_receive_skb(skb);
3251}
3252
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003253static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3254 void *priv)
3255{
3256 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003257 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003258}
3259
Yotam Gigia0040c82017-10-03 09:58:10 +02003260static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3261 u8 local_port, void *priv)
3262{
3263 skb->offload_mr_fwd_mark = 1;
3264 skb->offload_fwd_mark = 1;
3265 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3266}
3267
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003268static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3269 void *priv)
3270{
3271 struct mlxsw_sp *mlxsw_sp = priv;
3272 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3273 struct psample_group *psample_group;
3274 u32 size;
3275
3276 if (unlikely(!mlxsw_sp_port)) {
3277 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3278 local_port);
3279 goto out;
3280 }
3281 if (unlikely(!mlxsw_sp_port->sample)) {
3282 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3283 local_port);
3284 goto out;
3285 }
3286
3287 size = mlxsw_sp_port->sample->truncate ?
3288 mlxsw_sp_port->sample->trunc_size : skb->len;
3289
3290 rcu_read_lock();
3291 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3292 if (!psample_group)
3293 goto out_unlock;
3294 psample_sample_packet(psample_group, skb, size,
3295 mlxsw_sp_port->dev->ifindex, 0,
3296 mlxsw_sp_port->sample->rate);
3297out_unlock:
3298 rcu_read_unlock();
3299out:
3300 consume_skb(skb);
3301}
3302
Nogah Frankel117b0da2016-11-25 10:33:44 +01003303#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003304 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003305 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003306
Nogah Frankel117b0da2016-11-25 10:33:44 +01003307#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003308 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003309 _is_ctrl, SP_##_trap_group, DISCARD)
3310
Yotam Gigia0040c82017-10-03 09:58:10 +02003311#define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3312 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3313 _is_ctrl, SP_##_trap_group, DISCARD)
3314
Nogah Frankel117b0da2016-11-25 10:33:44 +01003315#define MLXSW_SP_EVENTL(_func, _trap_id) \
3316 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003317
Nogah Frankel45449132016-11-25 10:33:35 +01003318static const struct mlxsw_listener mlxsw_sp_listener[] = {
3319 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003320 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003321 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003322 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3323 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3324 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3325 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3326 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3327 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3328 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3329 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3330 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3331 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3332 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003333 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003334 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3335 false),
3336 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3337 false),
3338 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3339 false),
3340 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3341 false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003342 /* L3 traps */
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003343 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3344 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3345 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003346 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003347 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3348 false),
3349 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3350 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3351 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3352 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3353 false),
3354 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3355 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3356 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003357 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003358 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3359 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3360 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3361 false),
3362 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3363 false),
3364 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3365 false),
3366 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3367 false),
3368 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3369 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3370 false),
3371 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3372 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
Ido Schimmel7607dd32017-07-17 14:15:30 +02003373 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003374 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
Petr Machata86484de2017-09-02 23:49:27 +02003375 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003376 /* PKT Sample trap */
3377 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
Jiri Pirko0db7b382017-06-06 14:12:05 +02003378 false, SP_IP2ME, DISCARD),
3379 /* ACL trap */
3380 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
Yotam Gigib48cfc82017-09-19 10:00:20 +02003381 /* Multicast Router Traps */
3382 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3383 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3384 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
Yotam Gigia0040c82017-10-03 09:58:10 +02003385 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003386};
3387
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003388static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3389{
3390 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3391 enum mlxsw_reg_qpcr_ir_units ir_units;
3392 int max_cpu_policers;
3393 bool is_bytes;
3394 u8 burst_size;
3395 u32 rate;
3396 int i, err;
3397
3398 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3399 return -EIO;
3400
3401 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3402
3403 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3404 for (i = 0; i < max_cpu_policers; i++) {
3405 is_bytes = false;
3406 switch (i) {
3407 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3408 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3409 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3410 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003411 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3412 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003413 rate = 128;
3414 burst_size = 7;
3415 break;
3416 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003417 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003418 rate = 16 * 1024;
3419 burst_size = 10;
3420 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003421 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003422 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3423 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003424 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003425 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3426 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003427 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003428 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003429 rate = 1024;
3430 burst_size = 7;
3431 break;
3432 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3433 is_bytes = true;
3434 rate = 4 * 1024;
3435 burst_size = 4;
3436 break;
3437 default:
3438 continue;
3439 }
3440
3441 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3442 burst_size);
3443 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3444 if (err)
3445 return err;
3446 }
3447
3448 return 0;
3449}
3450
Nogah Frankel579c82e2016-11-25 10:33:42 +01003451static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003452{
3453 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003454 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003455 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003456 int max_trap_groups;
3457 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003458 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003459 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003460
3461 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3462 return -EIO;
3463
3464 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003465 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003466
3467 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003468 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003469 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003470 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3471 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3472 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3473 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003474 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003475 priority = 5;
3476 tc = 5;
3477 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003478 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003479 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3480 priority = 4;
3481 tc = 4;
3482 break;
3483 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3484 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003485 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003486 priority = 3;
3487 tc = 3;
3488 break;
3489 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003490 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003491 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003492 priority = 2;
3493 tc = 2;
3494 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003495 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003496 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3497 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003498 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003499 priority = 1;
3500 tc = 1;
3501 break;
3502 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003503 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3504 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003505 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003506 break;
3507 default:
3508 continue;
3509 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003510
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003511 if (max_cpu_policers <= policer_id &&
3512 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3513 return -EIO;
3514
3515 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003516 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3517 if (err)
3518 return err;
3519 }
3520
3521 return 0;
3522}
3523
3524static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3525{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003526 int i;
3527 int err;
3528
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003529 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3530 if (err)
3531 return err;
3532
Nogah Frankel579c82e2016-11-25 10:33:42 +01003533 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003534 if (err)
3535 return err;
3536
Nogah Frankel45449132016-11-25 10:33:35 +01003537 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003538 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003539 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003540 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003541 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003542 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003543
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003544 }
3545 return 0;
3546
Nogah Frankel45449132016-11-25 10:33:35 +01003547err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003548 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003549 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003550 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003551 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003552 }
3553 return err;
3554}
3555
3556static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3557{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003558 int i;
3559
Nogah Frankel45449132016-11-25 10:33:35 +01003560 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003561 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003562 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003563 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003564 }
3565}
3566
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003567static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3568{
3569 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003570 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003571
3572 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3573 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3574 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3575 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3576 MLXSW_REG_SLCR_LAG_HASH_SIP |
3577 MLXSW_REG_SLCR_LAG_HASH_DIP |
3578 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3579 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3580 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003581 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3582 if (err)
3583 return err;
3584
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003585 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3586 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003587 return -EIO;
3588
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003589 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003590 sizeof(struct mlxsw_sp_upper),
3591 GFP_KERNEL);
3592 if (!mlxsw_sp->lags)
3593 return -ENOMEM;
3594
3595 return 0;
3596}
3597
3598static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3599{
3600 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003601}
3602
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003603static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3604{
3605 char htgt_pl[MLXSW_REG_HTGT_LEN];
3606
Nogah Frankel579c82e2016-11-25 10:33:42 +01003607 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3608 MLXSW_REG_HTGT_INVALID_POLICER,
3609 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3610 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003611 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3612}
3613
Petr Machatac30f5d02017-10-16 16:26:35 +02003614static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3615 unsigned long event, void *ptr);
3616
Jiri Pirkob2f10572016-04-08 19:11:23 +02003617static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003618 const struct mlxsw_bus_info *mlxsw_bus_info)
3619{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003620 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003621 int err;
3622
3623 mlxsw_sp->core = mlxsw_core;
3624 mlxsw_sp->bus_info = mlxsw_bus_info;
3625
Yotam Gigi6b742192017-05-23 21:56:29 +02003626 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3627 if (err) {
3628 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3629 return err;
3630 }
3631
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003632 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3633 if (err) {
3634 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3635 return err;
3636 }
3637
Ido Schimmela875a2e2017-10-22 23:11:44 +02003638 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3639 if (err) {
3640 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3641 return err;
3642 }
3643
Ido Schimmela1107482017-05-26 08:37:39 +02003644 err = mlxsw_sp_fids_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003645 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003646 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
Ido Schimmela875a2e2017-10-22 23:11:44 +02003647 goto err_fids_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003648 }
3649
Ido Schimmela1107482017-05-26 08:37:39 +02003650 err = mlxsw_sp_traps_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003651 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003652 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3653 goto err_traps_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003654 }
3655
3656 err = mlxsw_sp_buffers_init(mlxsw_sp);
3657 if (err) {
3658 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3659 goto err_buffers_init;
3660 }
3661
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003662 err = mlxsw_sp_lag_init(mlxsw_sp);
3663 if (err) {
3664 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3665 goto err_lag_init;
3666 }
3667
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003668 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3669 if (err) {
3670 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3671 goto err_switchdev_init;
3672 }
3673
Yotam Gigie2b2d352017-09-19 10:00:08 +02003674 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3675 if (err) {
3676 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3677 goto err_counter_pool_init;
3678 }
3679
Yotam Gigid3b939b2017-09-19 10:00:09 +02003680 err = mlxsw_sp_afa_init(mlxsw_sp);
3681 if (err) {
3682 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3683 goto err_afa_init;
3684 }
3685
Petr Machata803335a2018-02-27 14:53:46 +01003686 err = mlxsw_sp_span_init(mlxsw_sp);
3687 if (err) {
3688 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3689 goto err_span_init;
3690 }
3691
3692 /* Initialize router after SPAN is initialized, so that the FIB and
3693 * neighbor event handlers can issue SPAN respin.
3694 */
Ido Schimmel464dce12016-07-02 11:00:15 +02003695 err = mlxsw_sp_router_init(mlxsw_sp);
3696 if (err) {
3697 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3698 goto err_router_init;
3699 }
3700
Petr Machata803335a2018-02-27 14:53:46 +01003701 /* Initialize netdevice notifier after router and SPAN is initialized,
3702 * so that the event handler can use router structures and call SPAN
3703 * respin.
Petr Machatac30f5d02017-10-16 16:26:35 +02003704 */
3705 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3706 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3707 if (err) {
3708 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3709 goto err_netdev_notifier;
3710 }
3711
Jiri Pirko22a67762017-02-03 10:29:07 +01003712 err = mlxsw_sp_acl_init(mlxsw_sp);
3713 if (err) {
3714 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3715 goto err_acl_init;
3716 }
3717
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003718 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3719 if (err) {
3720 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3721 goto err_dpipe_init;
3722 }
3723
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003724 err = mlxsw_sp_ports_create(mlxsw_sp);
3725 if (err) {
3726 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3727 goto err_ports_create;
3728 }
3729
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003730 return 0;
3731
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003732err_ports_create:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003733 mlxsw_sp_dpipe_fini(mlxsw_sp);
3734err_dpipe_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01003735 mlxsw_sp_acl_fini(mlxsw_sp);
3736err_acl_init:
Petr Machatac30f5d02017-10-16 16:26:35 +02003737 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3738err_netdev_notifier:
Ido Schimmel464dce12016-07-02 11:00:15 +02003739 mlxsw_sp_router_fini(mlxsw_sp);
3740err_router_init:
Petr Machata803335a2018-02-27 14:53:46 +01003741 mlxsw_sp_span_fini(mlxsw_sp);
3742err_span_init:
Yotam Gigid3b939b2017-09-19 10:00:09 +02003743 mlxsw_sp_afa_fini(mlxsw_sp);
3744err_afa_init:
Yotam Gigie2b2d352017-09-19 10:00:08 +02003745 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3746err_counter_pool_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003747 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003748err_switchdev_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003749 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003750err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02003751 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003752err_buffers_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003753 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003754err_traps_init:
3755 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003756err_fids_init:
3757 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003758 return err;
3759}
3760
Jiri Pirkob2f10572016-04-08 19:11:23 +02003761static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003762{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003763 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003764
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003765 mlxsw_sp_ports_remove(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003766 mlxsw_sp_dpipe_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01003767 mlxsw_sp_acl_fini(mlxsw_sp);
Petr Machatac30f5d02017-10-16 16:26:35 +02003768 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
Ido Schimmel464dce12016-07-02 11:00:15 +02003769 mlxsw_sp_router_fini(mlxsw_sp);
Petr Machata803335a2018-02-27 14:53:46 +01003770 mlxsw_sp_span_fini(mlxsw_sp);
Yotam Gigid3b939b2017-09-19 10:00:09 +02003771 mlxsw_sp_afa_fini(mlxsw_sp);
Yotam Gigie2b2d352017-09-19 10:00:08 +02003772 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003773 mlxsw_sp_switchdev_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003774 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02003775 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003776 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003777 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003778 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003779}
3780
Bhumika Goyal159fe882017-08-11 19:10:42 +05303781static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003782 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01003783 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003784 .used_flood_tables = 1,
3785 .used_flood_mode = 1,
3786 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003787 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003788 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003789 .max_fid_flood_tables = 3,
Ido Schimmela1107482017-05-26 08:37:39 +02003790 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003791 .used_max_ib_mc = 1,
3792 .max_ib_mc = 0,
3793 .used_max_pkey = 1,
3794 .max_pkey = 0,
Nogah Frankel403547d2016-09-20 11:16:52 +02003795 .used_kvd_split_data = 1,
3796 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
Ido Schimmelf11fbaf2017-10-22 23:11:49 +02003797 .kvd_hash_single_parts = 59,
3798 .kvd_hash_double_parts = 41,
Jiri Pirkoc6022422016-07-05 11:27:46 +02003799 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003800 .swid_config = {
3801 {
3802 .used_type = 1,
3803 .type = MLXSW_PORT_SWID_TYPE_ETH,
3804 }
3805 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02003806 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003807};
3808
Arkadi Sharshevskyafadc262018-01-15 08:59:09 +01003809static u64 mlxsw_sp_resource_kvd_linear_occ_get(struct devlink *devlink)
3810{
3811 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
3812 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3813
3814 return mlxsw_sp_kvdl_occ_get(mlxsw_sp);
3815}
3816
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003817static struct devlink_resource_ops mlxsw_sp_resource_kvd_linear_ops = {
Arkadi Sharshevskyafadc262018-01-15 08:59:09 +01003818 .occ_get = mlxsw_sp_resource_kvd_linear_occ_get,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003819};
3820
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003821static void
Jiri Pirko77d27092018-02-28 13:12:09 +01003822mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
3823 struct devlink_resource_size_params *kvd_size_params,
3824 struct devlink_resource_size_params *linear_size_params,
3825 struct devlink_resource_size_params *hash_double_size_params,
3826 struct devlink_resource_size_params *hash_single_size_params)
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003827{
3828 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3829 KVD_SINGLE_MIN_SIZE);
3830 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3831 KVD_DOUBLE_MIN_SIZE);
3832 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3833 u32 linear_size_min = 0;
3834
Jiri Pirko77d27092018-02-28 13:12:09 +01003835 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
3836 MLXSW_SP_KVD_GRANULARITY,
3837 DEVLINK_RESOURCE_UNIT_ENTRY);
3838 devlink_resource_size_params_init(linear_size_params, linear_size_min,
3839 kvd_size - single_size_min -
3840 double_size_min,
3841 MLXSW_SP_KVD_GRANULARITY,
3842 DEVLINK_RESOURCE_UNIT_ENTRY);
3843 devlink_resource_size_params_init(hash_double_size_params,
3844 double_size_min,
3845 kvd_size - single_size_min -
3846 linear_size_min,
3847 MLXSW_SP_KVD_GRANULARITY,
3848 DEVLINK_RESOURCE_UNIT_ENTRY);
3849 devlink_resource_size_params_init(hash_single_size_params,
3850 single_size_min,
3851 kvd_size - double_size_min -
3852 linear_size_min,
3853 MLXSW_SP_KVD_GRANULARITY,
3854 DEVLINK_RESOURCE_UNIT_ENTRY);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003855}
3856
3857static int mlxsw_sp_resources_register(struct mlxsw_core *mlxsw_core)
3858{
3859 struct devlink *devlink = priv_to_devlink(mlxsw_core);
Jiri Pirko77d27092018-02-28 13:12:09 +01003860 struct devlink_resource_size_params hash_single_size_params;
3861 struct devlink_resource_size_params hash_double_size_params;
3862 struct devlink_resource_size_params linear_size_params;
3863 struct devlink_resource_size_params kvd_size_params;
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003864 u32 kvd_size, single_size, double_size, linear_size;
3865 const struct mlxsw_config_profile *profile;
3866 int err;
3867
3868 profile = &mlxsw_sp_config_profile;
3869 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
3870 return -EIO;
3871
Jiri Pirko77d27092018-02-28 13:12:09 +01003872 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
3873 &linear_size_params,
3874 &hash_double_size_params,
3875 &hash_single_size_params);
3876
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003877 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3878 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
David Ahern14530742018-03-20 19:31:14 -07003879 kvd_size, MLXSW_SP_RESOURCE_KVD,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003880 DEVLINK_RESOURCE_ID_PARENT_TOP,
Jiri Pirko77d27092018-02-28 13:12:09 +01003881 &kvd_size_params,
Arkadi Sharshevsky4f4bbf72018-02-20 08:44:21 +01003882 NULL);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003883 if (err)
3884 return err;
3885
3886 linear_size = profile->kvd_linear_size;
3887 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
David Ahern14530742018-03-20 19:31:14 -07003888 linear_size,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003889 MLXSW_SP_RESOURCE_KVD_LINEAR,
3890 MLXSW_SP_RESOURCE_KVD,
Jiri Pirko77d27092018-02-28 13:12:09 +01003891 &linear_size_params,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003892 &mlxsw_sp_resource_kvd_linear_ops);
3893 if (err)
3894 return err;
3895
Arkadi Sharshevsky51d3c082018-02-20 08:44:22 +01003896 err = mlxsw_sp_kvdl_resources_register(devlink);
3897 if (err)
3898 return err;
3899
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003900 double_size = kvd_size - linear_size;
3901 double_size *= profile->kvd_hash_double_parts;
3902 double_size /= profile->kvd_hash_double_parts +
3903 profile->kvd_hash_single_parts;
3904 double_size = rounddown(double_size, profile->kvd_hash_granularity);
3905 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
David Ahern14530742018-03-20 19:31:14 -07003906 double_size,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003907 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3908 MLXSW_SP_RESOURCE_KVD,
Jiri Pirko77d27092018-02-28 13:12:09 +01003909 &hash_double_size_params,
Arkadi Sharshevsky4f4bbf72018-02-20 08:44:21 +01003910 NULL);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003911 if (err)
3912 return err;
3913
3914 single_size = kvd_size - double_size - linear_size;
3915 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
David Ahern14530742018-03-20 19:31:14 -07003916 single_size,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003917 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3918 MLXSW_SP_RESOURCE_KVD,
Jiri Pirko77d27092018-02-28 13:12:09 +01003919 &hash_single_size_params,
Arkadi Sharshevsky4f4bbf72018-02-20 08:44:21 +01003920 NULL);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003921 if (err)
3922 return err;
3923
3924 return 0;
3925}
3926
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01003927static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
3928 const struct mlxsw_config_profile *profile,
3929 u64 *p_single_size, u64 *p_double_size,
3930 u64 *p_linear_size)
3931{
3932 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3933 u32 double_size;
3934 int err;
3935
3936 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3937 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
3938 !profile->used_kvd_split_data)
3939 return -EIO;
3940
3941 /* The hash part is what left of the kvd without the
3942 * linear part. It is split to the single size and
3943 * double size by the parts ratio from the profile.
3944 * Both sizes must be a multiplications of the
3945 * granularity from the profile. In case the user
3946 * provided the sizes they are obtained via devlink.
3947 */
3948 err = devlink_resource_size_get(devlink,
3949 MLXSW_SP_RESOURCE_KVD_LINEAR,
3950 p_linear_size);
3951 if (err)
3952 *p_linear_size = profile->kvd_linear_size;
3953
3954 err = devlink_resource_size_get(devlink,
3955 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3956 p_double_size);
3957 if (err) {
3958 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3959 *p_linear_size;
3960 double_size *= profile->kvd_hash_double_parts;
3961 double_size /= profile->kvd_hash_double_parts +
3962 profile->kvd_hash_single_parts;
3963 *p_double_size = rounddown(double_size,
3964 profile->kvd_hash_granularity);
3965 }
3966
3967 err = devlink_resource_size_get(devlink,
3968 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3969 p_single_size);
3970 if (err)
3971 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3972 *p_double_size - *p_linear_size;
3973
3974 /* Check results are legal. */
3975 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3976 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
3977 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
3978 return -EIO;
3979
3980 return 0;
3981}
3982
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003983static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02003984 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003985 .priv_size = sizeof(struct mlxsw_sp),
3986 .init = mlxsw_sp_init,
3987 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003988 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003989 .port_split = mlxsw_sp_port_split,
3990 .port_unsplit = mlxsw_sp_port_unsplit,
3991 .sb_pool_get = mlxsw_sp_sb_pool_get,
3992 .sb_pool_set = mlxsw_sp_sb_pool_set,
3993 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3994 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3995 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3996 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3997 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3998 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3999 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4000 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4001 .txhdr_construct = mlxsw_sp_txhdr_construct,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004002 .resources_register = mlxsw_sp_resources_register,
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01004003 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02004004 .txhdr_len = MLXSW_TXHDR_LEN,
4005 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004006};
4007
Jiri Pirko22a67762017-02-03 10:29:07 +01004008bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004009{
4010 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4011}
4012
Jiri Pirko1182e532017-03-06 21:25:20 +01004013static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07004014{
Jiri Pirko1182e532017-03-06 21:25:20 +01004015 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07004016 int ret = 0;
4017
4018 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01004019 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07004020 ret = 1;
4021 }
4022
4023 return ret;
4024}
4025
Ido Schimmelc57529e2017-05-26 08:37:31 +02004026struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004027{
Jiri Pirko1182e532017-03-06 21:25:20 +01004028 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004029
4030 if (mlxsw_sp_port_dev_check(dev))
4031 return netdev_priv(dev);
4032
Jiri Pirko1182e532017-03-06 21:25:20 +01004033 mlxsw_sp_port = NULL;
4034 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004035
Jiri Pirko1182e532017-03-06 21:25:20 +01004036 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004037}
4038
Ido Schimmel4724ba562017-03-10 08:53:39 +01004039struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004040{
4041 struct mlxsw_sp_port *mlxsw_sp_port;
4042
4043 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4044 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4045}
4046
Arkadi Sharshevskyaf0613782017-06-08 08:44:20 +02004047struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004048{
Jiri Pirko1182e532017-03-06 21:25:20 +01004049 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004050
4051 if (mlxsw_sp_port_dev_check(dev))
4052 return netdev_priv(dev);
4053
Jiri Pirko1182e532017-03-06 21:25:20 +01004054 mlxsw_sp_port = NULL;
4055 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4056 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004057
Jiri Pirko1182e532017-03-06 21:25:20 +01004058 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004059}
4060
4061struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4062{
4063 struct mlxsw_sp_port *mlxsw_sp_port;
4064
4065 rcu_read_lock();
4066 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4067 if (mlxsw_sp_port)
4068 dev_hold(mlxsw_sp_port->dev);
4069 rcu_read_unlock();
4070 return mlxsw_sp_port;
4071}
4072
4073void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4074{
4075 dev_put(mlxsw_sp_port->dev);
4076}
4077
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004078static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004079{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004080 char sldr_pl[MLXSW_REG_SLDR_LEN];
4081
4082 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4083 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4084}
4085
4086static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4087{
4088 char sldr_pl[MLXSW_REG_SLDR_LEN];
4089
4090 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4091 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4092}
4093
4094static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4095 u16 lag_id, u8 port_index)
4096{
4097 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4098 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4099
4100 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4101 lag_id, port_index);
4102 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4103}
4104
4105static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4106 u16 lag_id)
4107{
4108 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4109 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4110
4111 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4112 lag_id);
4113 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4114}
4115
4116static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4117 u16 lag_id)
4118{
4119 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4120 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4121
4122 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4123 lag_id);
4124 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4125}
4126
4127static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4128 u16 lag_id)
4129{
4130 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4131 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4132
4133 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4134 lag_id);
4135 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4136}
4137
4138static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4139 struct net_device *lag_dev,
4140 u16 *p_lag_id)
4141{
4142 struct mlxsw_sp_upper *lag;
4143 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004144 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004145 int i;
4146
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004147 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4148 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004149 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4150 if (lag->ref_count) {
4151 if (lag->dev == lag_dev) {
4152 *p_lag_id = i;
4153 return 0;
4154 }
4155 } else if (free_lag_id < 0) {
4156 free_lag_id = i;
4157 }
4158 }
4159 if (free_lag_id < 0)
4160 return -EBUSY;
4161 *p_lag_id = free_lag_id;
4162 return 0;
4163}
4164
4165static bool
4166mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4167 struct net_device *lag_dev,
David Aherne58376e2017-10-04 17:48:51 -07004168 struct netdev_lag_upper_info *lag_upper_info,
4169 struct netlink_ext_ack *extack)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004170{
4171 u16 lag_id;
4172
David Aherne58376e2017-10-04 17:48:51 -07004173 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004174 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004175 return false;
David Aherne58376e2017-10-04 17:48:51 -07004176 }
4177 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004178 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004179 return false;
David Aherne58376e2017-10-04 17:48:51 -07004180 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004181 return true;
4182}
4183
4184static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4185 u16 lag_id, u8 *p_port_index)
4186{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004187 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004188 int i;
4189
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004190 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4191 MAX_LAG_MEMBERS);
4192 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004193 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4194 *p_port_index = i;
4195 return 0;
4196 }
4197 }
4198 return -EBUSY;
4199}
4200
4201static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4202 struct net_device *lag_dev)
4203{
4204 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004205 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004206 struct mlxsw_sp_upper *lag;
4207 u16 lag_id;
4208 u8 port_index;
4209 int err;
4210
4211 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4212 if (err)
4213 return err;
4214 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4215 if (!lag->ref_count) {
4216 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4217 if (err)
4218 return err;
4219 lag->dev = lag_dev;
4220 }
4221
4222 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4223 if (err)
4224 return err;
4225 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4226 if (err)
4227 goto err_col_port_add;
4228 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4229 if (err)
4230 goto err_col_port_enable;
4231
4232 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4233 mlxsw_sp_port->local_port);
4234 mlxsw_sp_port->lag_id = lag_id;
4235 mlxsw_sp_port->lagged = 1;
4236 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004237
Ido Schimmelc57529e2017-05-26 08:37:31 +02004238 /* Port is no longer usable as a router interface */
4239 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4240 if (mlxsw_sp_port_vlan->fid)
Ido Schimmela1107482017-05-26 08:37:39 +02004241 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004242
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004243 return 0;
4244
Ido Schimmel51554db2016-05-06 22:18:39 +02004245err_col_port_enable:
4246 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004247err_col_port_add:
4248 if (!lag->ref_count)
4249 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004250 return err;
4251}
4252
Ido Schimmel82e6db02016-06-20 23:04:04 +02004253static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4254 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004255{
4256 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004257 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004258 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004259
4260 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004261 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004262 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4263 WARN_ON(lag->ref_count == 0);
4264
Ido Schimmel82e6db02016-06-20 23:04:04 +02004265 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4266 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004267
Ido Schimmelc57529e2017-05-26 08:37:31 +02004268 /* Any VLANs configured on the port are no longer valid */
4269 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004270
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004271 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004272 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004273
4274 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4275 mlxsw_sp_port->local_port);
4276 mlxsw_sp_port->lagged = 0;
4277 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004278
Ido Schimmelc57529e2017-05-26 08:37:31 +02004279 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4280 /* Make sure untagged frames are allowed to ingress */
4281 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004282}
4283
Jiri Pirko74581202015-12-03 12:12:30 +01004284static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4285 u16 lag_id)
4286{
4287 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4288 char sldr_pl[MLXSW_REG_SLDR_LEN];
4289
4290 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4291 mlxsw_sp_port->local_port);
4292 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4293}
4294
4295static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4296 u16 lag_id)
4297{
4298 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4299 char sldr_pl[MLXSW_REG_SLDR_LEN];
4300
4301 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4302 mlxsw_sp_port->local_port);
4303 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4304}
4305
4306static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4307 bool lag_tx_enabled)
4308{
4309 if (lag_tx_enabled)
4310 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4311 mlxsw_sp_port->lag_id);
4312 else
4313 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4314 mlxsw_sp_port->lag_id);
4315}
4316
4317static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4318 struct netdev_lag_lower_state_info *info)
4319{
4320 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4321}
4322
Jiri Pirko2b94e582017-04-18 16:55:37 +02004323static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4324 bool enable)
4325{
4326 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4327 enum mlxsw_reg_spms_state spms_state;
4328 char *spms_pl;
4329 u16 vid;
4330 int err;
4331
4332 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4333 MLXSW_REG_SPMS_STATE_DISCARDING;
4334
4335 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4336 if (!spms_pl)
4337 return -ENOMEM;
4338 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4339
4340 for (vid = 0; vid < VLAN_N_VID; vid++)
4341 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4342
4343 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4344 kfree(spms_pl);
4345 return err;
4346}
4347
4348static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4349{
Yuval Mintzfccff082017-12-15 08:44:21 +01004350 u16 vid = 1;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004351 int err;
4352
Ido Schimmel4aafc362017-05-26 08:37:25 +02004353 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004354 if (err)
4355 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02004356 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4357 if (err)
4358 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004359 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4360 true, false);
4361 if (err)
4362 goto err_port_vlan_set;
Yuval Mintzfccff082017-12-15 08:44:21 +01004363
4364 for (; vid <= VLAN_N_VID - 1; vid++) {
4365 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4366 vid, false);
4367 if (err)
4368 goto err_vid_learning_set;
4369 }
4370
Jiri Pirko2b94e582017-04-18 16:55:37 +02004371 return 0;
4372
Yuval Mintzfccff082017-12-15 08:44:21 +01004373err_vid_learning_set:
4374 for (vid--; vid >= 1; vid--)
4375 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004376err_port_vlan_set:
4377 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004378err_port_stp_set:
4379 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004380 return err;
4381}
4382
4383static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4384{
Yuval Mintzfccff082017-12-15 08:44:21 +01004385 u16 vid;
4386
4387 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4388 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4389 vid, true);
4390
Jiri Pirko2b94e582017-04-18 16:55:37 +02004391 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4392 false, false);
4393 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004394 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004395}
4396
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004397static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4398 struct net_device *dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004399 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004400{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004401 struct netdev_notifier_changeupper_info *info;
4402 struct mlxsw_sp_port *mlxsw_sp_port;
David Aherne58376e2017-10-04 17:48:51 -07004403 struct netlink_ext_ack *extack;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004404 struct net_device *upper_dev;
4405 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004406 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004407
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004408 mlxsw_sp_port = netdev_priv(dev);
4409 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4410 info = ptr;
David Aherne58376e2017-10-04 17:48:51 -07004411 extack = netdev_notifier_info_to_extack(&info->info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004412
4413 switch (event) {
4414 case NETDEV_PRECHANGEUPPER:
4415 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004416 if (!is_vlan_dev(upper_dev) &&
4417 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004418 !netif_is_bridge_master(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004419 !netif_is_ovs_master(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004420 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004421 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004422 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004423 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004424 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004425 if (netdev_has_any_upper_dev(upper_dev) &&
4426 (!netif_is_bridge_master(upper_dev) ||
4427 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4428 upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004429 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004430 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004431 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004432 if (netif_is_lag_master(upper_dev) &&
4433 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
David Aherne58376e2017-10-04 17:48:51 -07004434 info->upper_info, extack))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004435 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004436 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004437 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004438 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004439 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004440 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004441 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004442 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004443 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004444 }
4445 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004446 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004447 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004448 }
4449 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004450 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004451 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004452 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004453 break;
4454 case NETDEV_CHANGEUPPER:
4455 upper_dev = info->upper_dev;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004456 if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004457 if (info->linking)
4458 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004459 lower_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004460 upper_dev,
4461 extack);
Ido Schimmel7117a572016-06-20 23:04:06 +02004462 else
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004463 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4464 lower_dev,
4465 upper_dev);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004466 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004467 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004468 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4469 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004470 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004471 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4472 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004473 } else if (netif_is_ovs_master(upper_dev)) {
4474 if (info->linking)
4475 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4476 else
4477 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004478 }
4479 break;
4480 }
4481
Ido Schimmel80bedf12016-06-20 23:03:59 +02004482 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004483}
4484
Jiri Pirko74581202015-12-03 12:12:30 +01004485static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4486 unsigned long event, void *ptr)
4487{
4488 struct netdev_notifier_changelowerstate_info *info;
4489 struct mlxsw_sp_port *mlxsw_sp_port;
4490 int err;
4491
4492 mlxsw_sp_port = netdev_priv(dev);
4493 info = ptr;
4494
4495 switch (event) {
4496 case NETDEV_CHANGELOWERSTATE:
4497 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4498 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4499 info->lower_state_info);
4500 if (err)
4501 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4502 }
4503 break;
4504 }
4505
Ido Schimmel80bedf12016-06-20 23:03:59 +02004506 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004507}
4508
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004509static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4510 struct net_device *port_dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004511 unsigned long event, void *ptr)
4512{
4513 switch (event) {
4514 case NETDEV_PRECHANGEUPPER:
4515 case NETDEV_CHANGEUPPER:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004516 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4517 event, ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004518 case NETDEV_CHANGELOWERSTATE:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004519 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4520 ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004521 }
4522
Ido Schimmel80bedf12016-06-20 23:03:59 +02004523 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004524}
4525
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004526static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4527 unsigned long event, void *ptr)
4528{
4529 struct net_device *dev;
4530 struct list_head *iter;
4531 int ret;
4532
4533 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4534 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004535 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4536 ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004537 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004538 return ret;
4539 }
4540 }
4541
Ido Schimmel80bedf12016-06-20 23:03:59 +02004542 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004543}
4544
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004545static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4546 struct net_device *dev,
4547 unsigned long event, void *ptr,
4548 u16 vid)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004549{
4550 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel90045fc2017-12-25 09:05:33 +01004551 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004552 struct netdev_notifier_changeupper_info *info = ptr;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004553 struct netlink_ext_ack *extack;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004554 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004555 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004556
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004557 extack = netdev_notifier_info_to_extack(&info->info);
4558
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004559 switch (event) {
4560 case NETDEV_PRECHANGEUPPER:
4561 upper_dev = info->upper_dev;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004562 if (!netif_is_bridge_master(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004563 NL_SET_ERR_MSG_MOD(extack, "VLAN devices only support bridge and VRF uppers");
Ido Schimmel80bedf12016-06-20 23:03:59 +02004564 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004565 }
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004566 if (!info->linking)
4567 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004568 if (netdev_has_any_upper_dev(upper_dev) &&
4569 (!netif_is_bridge_master(upper_dev) ||
4570 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4571 upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004572 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004573 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004574 }
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004575 break;
4576 case NETDEV_CHANGEUPPER:
4577 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004578 if (netif_is_bridge_master(upper_dev)) {
4579 if (info->linking)
Ido Schimmelc57529e2017-05-26 08:37:31 +02004580 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4581 vlan_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004582 upper_dev,
4583 extack);
Ido Schimmel1f880612017-03-10 08:53:35 +01004584 else
Ido Schimmelc57529e2017-05-26 08:37:31 +02004585 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4586 vlan_dev,
4587 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004588 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004589 err = -EINVAL;
4590 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004591 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004592 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004593 }
4594
Ido Schimmel80bedf12016-06-20 23:03:59 +02004595 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004596}
4597
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004598static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4599 struct net_device *lag_dev,
4600 unsigned long event,
4601 void *ptr, u16 vid)
Ido Schimmel272c4472015-12-15 16:03:47 +01004602{
4603 struct net_device *dev;
4604 struct list_head *iter;
4605 int ret;
4606
4607 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4608 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004609 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4610 event, ptr,
4611 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004612 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004613 return ret;
4614 }
4615 }
4616
Ido Schimmel80bedf12016-06-20 23:03:59 +02004617 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004618}
4619
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004620static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4621 unsigned long event, void *ptr)
4622{
4623 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4624 u16 vid = vlan_dev_vlan_id(vlan_dev);
4625
Ido Schimmel272c4472015-12-15 16:03:47 +01004626 if (mlxsw_sp_port_dev_check(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004627 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4628 event, ptr, vid);
Ido Schimmel272c4472015-12-15 16:03:47 +01004629 else if (netif_is_lag_master(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004630 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4631 real_dev, event,
4632 ptr, vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004633
Ido Schimmel80bedf12016-06-20 23:03:59 +02004634 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004635}
4636
Ido Schimmelb1e45522017-04-30 19:47:14 +03004637static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4638{
4639 struct netdev_notifier_changeupper_info *info = ptr;
4640
4641 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4642 return false;
4643 return netif_is_l3_master(info->upper_dev);
4644}
4645
Petr Machata00635872017-10-16 16:26:37 +02004646static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004647 unsigned long event, void *ptr)
4648{
4649 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Petr Machata079c9f32018-02-27 14:53:44 +01004650 struct mlxsw_sp_span_entry *span_entry;
Petr Machata00635872017-10-16 16:26:37 +02004651 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004652 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004653
Petr Machata00635872017-10-16 16:26:37 +02004654 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
Petr Machata079c9f32018-02-27 14:53:44 +01004655 if (event == NETDEV_UNREGISTER) {
4656 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
4657 if (span_entry)
4658 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
4659 }
Petr Machata803335a2018-02-27 14:53:46 +01004660 mlxsw_sp_span_respin(mlxsw_sp);
Petr Machata079c9f32018-02-27 14:53:44 +01004661
Petr Machata796ec772017-11-03 10:03:29 +01004662 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
4663 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
4664 event, ptr);
Petr Machata61481f22017-11-03 10:03:41 +01004665 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
4666 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
4667 event, ptr);
Petr Machata00635872017-10-16 16:26:37 +02004668 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004669 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03004670 else if (mlxsw_sp_is_vrf_event(event, ptr))
4671 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004672 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004673 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004674 else if (netif_is_lag_master(dev))
4675 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4676 else if (is_vlan_dev(dev))
4677 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004678
Ido Schimmel80bedf12016-06-20 23:03:59 +02004679 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004680}
4681
David Ahern89d5dd22017-10-18 09:56:55 -07004682static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
4683 .notifier_call = mlxsw_sp_inetaddr_valid_event,
4684};
4685
Ido Schimmel99724c12016-07-04 08:23:14 +02004686static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4687 .notifier_call = mlxsw_sp_inetaddr_event,
David Ahern89d5dd22017-10-18 09:56:55 -07004688};
4689
4690static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
4691 .notifier_call = mlxsw_sp_inet6addr_valid_event,
Ido Schimmel99724c12016-07-04 08:23:14 +02004692};
4693
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004694static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
4695 .notifier_call = mlxsw_sp_inet6addr_event,
4696};
4697
Jiri Pirko1d20d232016-10-27 15:12:59 +02004698static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4699 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4700 {0, },
4701};
4702
4703static struct pci_driver mlxsw_sp_pci_driver = {
4704 .name = mlxsw_sp_driver_name,
4705 .id_table = mlxsw_sp_pci_id_table,
4706};
4707
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004708static int __init mlxsw_sp_module_init(void)
4709{
4710 int err;
4711
David Ahern89d5dd22017-10-18 09:56:55 -07004712 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004713 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004714 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004715 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004716
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004717 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4718 if (err)
4719 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02004720
4721 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4722 if (err)
4723 goto err_pci_driver_register;
4724
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004725 return 0;
4726
Jiri Pirko1d20d232016-10-27 15:12:59 +02004727err_pci_driver_register:
4728 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004729err_core_driver_register:
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004730 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004731 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02004732 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004733 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004734 return err;
4735}
4736
4737static void __exit mlxsw_sp_module_exit(void)
4738{
Jiri Pirko1d20d232016-10-27 15:12:59 +02004739 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004740 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004741 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004742 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004743 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004744 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004745}
4746
4747module_init(mlxsw_sp_module_init);
4748module_exit(mlxsw_sp_module_exit);
4749
4750MODULE_LICENSE("Dual BSD/GPL");
4751MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4752MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02004753MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Yotam Gigi6b742192017-05-23 21:56:29 +02004754MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);