Blame - llvm/lib/Target/AMDGPU/SIInstructions.td - toolchain/llvm-project

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Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1	//===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
				2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
				9	// This file was originally auto-generated from a GPU register header file and
				10	// all the instruction definitions were originally commented out. Instructions
				11	// that are not yet supported remain commented out.
				12	//===----------------------------------------------------------------------===//
				13
Eric Christopher	7792e32	2015-01-30 23:24:40 +0000	[diff] [blame]	14	def isGCN : Predicate<"Subtarget->getGeneration() "
Matt Arsenault	43e92fe	2016-06-24 06:30:11 +0000	[diff] [blame]	15	">= SISubtarget::SOUTHERN_ISLANDS">,
Tom Stellard	d7e6f13	2015-04-08 01:09:26 +0000	[diff] [blame]	16	AssemblerPredicate<"FeatureGCN">;
Marek Olsak	7d77728	2015-03-24 13:40:15 +0000	[diff] [blame]	17	def isSI : Predicate<"Subtarget->getGeneration() "
Matt Arsenault	43e92fe	2016-06-24 06:30:11 +0000	[diff] [blame]	18	"== SISubtarget::SOUTHERN_ISLANDS">,
Matt Arsenault	d6adfb4	2015-09-24 19:52:21 +0000	[diff] [blame]	19	AssemblerPredicate<"FeatureSouthernIslands">;
				20
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	21	def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
				22	def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
				23
Valery Pykhtin	a34fb49	2016-08-30 15:20:31 +0000	[diff] [blame]	24	include "SOPInstructions.td"
Valery Pykhtin	1b13886	2016-09-01 09:56:47 +0000	[diff] [blame]	25	include "SMInstructions.td"
Valery Pykhtin	8bc6596	2016-09-05 11:22:51 +0000	[diff] [blame]	26	include "FLATInstructions.td"
Valery Pykhtin	b66e5eb	2016-09-10 13:09:16 +0000	[diff] [blame]	27	include "BUFInstructions.td"
Valery Pykhtin	a34fb49	2016-08-30 15:20:31 +0000	[diff] [blame]	28
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	29	let SubtargetPredicate = isGCN in {
Tom Stellard	0e70de5	2014-05-16 20:56:45 +0000	[diff] [blame]	30
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	31	//===----------------------------------------------------------------------===//
Tom Stellard	3a35d8f	2014-10-01 14:44:45 +0000	[diff] [blame]	32	// EXP Instructions
				33	//===----------------------------------------------------------------------===//
				34
				35	defm EXP : EXP_m;
				36
				37	//===----------------------------------------------------------------------===//
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	38	// VOPC Instructions
				39	//===----------------------------------------------------------------------===//
				40
Matt Arsenault	0943b0e	2015-03-23 18:45:38 +0000	[diff] [blame]	41	let isCompare = 1, isCommutable = 1 in {
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	42
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	43	defm V_CMP_F_F32 : VOPC_F32 <vopc<0x0, 0x40>, "v_cmp_f_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	44	defm V_CMP_LT_F32 : VOPC_F32 <vopc<0x1, 0x41>, "v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	45	defm V_CMP_EQ_F32 : VOPC_F32 <vopc<0x2, 0x42>, "v_cmp_eq_f32", COND_OEQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	46	defm V_CMP_LE_F32 : VOPC_F32 <vopc<0x3, 0x43>, "v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	47	defm V_CMP_GT_F32 : VOPC_F32 <vopc<0x4, 0x44>, "v_cmp_gt_f32", COND_OGT>;
Matt Arsenault	9cded7a	2014-12-11 22:15:35 +0000	[diff] [blame]	48	defm V_CMP_LG_F32 : VOPC_F32 <vopc<0x5, 0x45>, "v_cmp_lg_f32", COND_ONE>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	49	defm V_CMP_GE_F32 : VOPC_F32 <vopc<0x6, 0x46>, "v_cmp_ge_f32", COND_OGE>;
				50	defm V_CMP_O_F32 : VOPC_F32 <vopc<0x7, 0x47>, "v_cmp_o_f32", COND_O>;
				51	defm V_CMP_U_F32 : VOPC_F32 <vopc<0x8, 0x48>, "v_cmp_u_f32", COND_UO>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	52	defm V_CMP_NGE_F32 : VOPC_F32 <vopc<0x9, 0x49>, "v_cmp_nge_f32", COND_ULT, "v_cmp_nle_f32">;
Matt Arsenault	58d502f	2014-12-11 22:15:43 +0000	[diff] [blame]	53	defm V_CMP_NLG_F32 : VOPC_F32 <vopc<0xa, 0x4a>, "v_cmp_nlg_f32", COND_UEQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	54	defm V_CMP_NGT_F32 : VOPC_F32 <vopc<0xb, 0x4b>, "v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">;
Matt Arsenault	8b989ef	2014-12-11 22:15:39 +0000	[diff] [blame]	55	defm V_CMP_NLE_F32 : VOPC_F32 <vopc<0xc, 0x4c>, "v_cmp_nle_f32", COND_UGT>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	56	defm V_CMP_NEQ_F32 : VOPC_F32 <vopc<0xd, 0x4d>, "v_cmp_neq_f32", COND_UNE>;
Matt Arsenault	8b989ef	2014-12-11 22:15:39 +0000	[diff] [blame]	57	defm V_CMP_NLT_F32 : VOPC_F32 <vopc<0xe, 0x4e>, "v_cmp_nlt_f32", COND_UGE>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	58	defm V_CMP_TRU_F32 : VOPC_F32 <vopc<0xf, 0x4f>, "v_cmp_tru_f32">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	59
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	60
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	61	defm V_CMPX_F_F32 : VOPCX_F32 <vopc<0x10, 0x50>, "v_cmpx_f_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	62	defm V_CMPX_LT_F32 : VOPCX_F32 <vopc<0x11, 0x51>, "v_cmpx_lt_f32", "v_cmpx_gt_f32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	63	defm V_CMPX_EQ_F32 : VOPCX_F32 <vopc<0x12, 0x52>, "v_cmpx_eq_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	64	defm V_CMPX_LE_F32 : VOPCX_F32 <vopc<0x13, 0x53>, "v_cmpx_le_f32", "v_cmpx_ge_f32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	65	defm V_CMPX_GT_F32 : VOPCX_F32 <vopc<0x14, 0x54>, "v_cmpx_gt_f32">;
				66	defm V_CMPX_LG_F32 : VOPCX_F32 <vopc<0x15, 0x55>, "v_cmpx_lg_f32">;
				67	defm V_CMPX_GE_F32 : VOPCX_F32 <vopc<0x16, 0x56>, "v_cmpx_ge_f32">;
				68	defm V_CMPX_O_F32 : VOPCX_F32 <vopc<0x17, 0x57>, "v_cmpx_o_f32">;
				69	defm V_CMPX_U_F32 : VOPCX_F32 <vopc<0x18, 0x58>, "v_cmpx_u_f32">;
				70	defm V_CMPX_NGE_F32 : VOPCX_F32 <vopc<0x19, 0x59>, "v_cmpx_nge_f32">;
				71	defm V_CMPX_NLG_F32 : VOPCX_F32 <vopc<0x1a, 0x5a>, "v_cmpx_nlg_f32">;
				72	defm V_CMPX_NGT_F32 : VOPCX_F32 <vopc<0x1b, 0x5b>, "v_cmpx_ngt_f32">;
				73	defm V_CMPX_NLE_F32 : VOPCX_F32 <vopc<0x1c, 0x5c>, "v_cmpx_nle_f32">;
				74	defm V_CMPX_NEQ_F32 : VOPCX_F32 <vopc<0x1d, 0x5d>, "v_cmpx_neq_f32">;
				75	defm V_CMPX_NLT_F32 : VOPCX_F32 <vopc<0x1e, 0x5e>, "v_cmpx_nlt_f32">;
				76	defm V_CMPX_TRU_F32 : VOPCX_F32 <vopc<0x1f, 0x5f>, "v_cmpx_tru_f32">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	77
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	78
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	79	defm V_CMP_F_F64 : VOPC_F64 <vopc<0x20, 0x60>, "v_cmp_f_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	80	defm V_CMP_LT_F64 : VOPC_F64 <vopc<0x21, 0x61>, "v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	81	defm V_CMP_EQ_F64 : VOPC_F64 <vopc<0x22, 0x62>, "v_cmp_eq_f64", COND_OEQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	82	defm V_CMP_LE_F64 : VOPC_F64 <vopc<0x23, 0x63>, "v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	83	defm V_CMP_GT_F64 : VOPC_F64 <vopc<0x24, 0x64>, "v_cmp_gt_f64", COND_OGT>;
Matt Arsenault	9cded7a	2014-12-11 22:15:35 +0000	[diff] [blame]	84	defm V_CMP_LG_F64 : VOPC_F64 <vopc<0x25, 0x65>, "v_cmp_lg_f64", COND_ONE>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	85	defm V_CMP_GE_F64 : VOPC_F64 <vopc<0x26, 0x66>, "v_cmp_ge_f64", COND_OGE>;
				86	defm V_CMP_O_F64 : VOPC_F64 <vopc<0x27, 0x67>, "v_cmp_o_f64", COND_O>;
				87	defm V_CMP_U_F64 : VOPC_F64 <vopc<0x28, 0x68>, "v_cmp_u_f64", COND_UO>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	88	defm V_CMP_NGE_F64 : VOPC_F64 <vopc<0x29, 0x69>, "v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">;
Matt Arsenault	58d502f	2014-12-11 22:15:43 +0000	[diff] [blame]	89	defm V_CMP_NLG_F64 : VOPC_F64 <vopc<0x2a, 0x6a>, "v_cmp_nlg_f64", COND_UEQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	90	defm V_CMP_NGT_F64 : VOPC_F64 <vopc<0x2b, 0x6b>, "v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">;
Matt Arsenault	8b989ef	2014-12-11 22:15:39 +0000	[diff] [blame]	91	defm V_CMP_NLE_F64 : VOPC_F64 <vopc<0x2c, 0x6c>, "v_cmp_nle_f64", COND_UGT>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	92	defm V_CMP_NEQ_F64 : VOPC_F64 <vopc<0x2d, 0x6d>, "v_cmp_neq_f64", COND_UNE>;
Matt Arsenault	8b989ef	2014-12-11 22:15:39 +0000	[diff] [blame]	93	defm V_CMP_NLT_F64 : VOPC_F64 <vopc<0x2e, 0x6e>, "v_cmp_nlt_f64", COND_UGE>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	94	defm V_CMP_TRU_F64 : VOPC_F64 <vopc<0x2f, 0x6f>, "v_cmp_tru_f64">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	95
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	96
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	97	defm V_CMPX_F_F64 : VOPCX_F64 <vopc<0x30, 0x70>, "v_cmpx_f_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	98	defm V_CMPX_LT_F64 : VOPCX_F64 <vopc<0x31, 0x71>, "v_cmpx_lt_f64", "v_cmpx_gt_f64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	99	defm V_CMPX_EQ_F64 : VOPCX_F64 <vopc<0x32, 0x72>, "v_cmpx_eq_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	100	defm V_CMPX_LE_F64 : VOPCX_F64 <vopc<0x33, 0x73>, "v_cmpx_le_f64", "v_cmpx_ge_f64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	101	defm V_CMPX_GT_F64 : VOPCX_F64 <vopc<0x34, 0x74>, "v_cmpx_gt_f64">;
				102	defm V_CMPX_LG_F64 : VOPCX_F64 <vopc<0x35, 0x75>, "v_cmpx_lg_f64">;
				103	defm V_CMPX_GE_F64 : VOPCX_F64 <vopc<0x36, 0x76>, "v_cmpx_ge_f64">;
				104	defm V_CMPX_O_F64 : VOPCX_F64 <vopc<0x37, 0x77>, "v_cmpx_o_f64">;
				105	defm V_CMPX_U_F64 : VOPCX_F64 <vopc<0x38, 0x78>, "v_cmpx_u_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	106	defm V_CMPX_NGE_F64 : VOPCX_F64 <vopc<0x39, 0x79>, "v_cmpx_nge_f64", "v_cmpx_nle_f64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	107	defm V_CMPX_NLG_F64 : VOPCX_F64 <vopc<0x3a, 0x7a>, "v_cmpx_nlg_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	108	defm V_CMPX_NGT_F64 : VOPCX_F64 <vopc<0x3b, 0x7b>, "v_cmpx_ngt_f64", "v_cmpx_nlt_f64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	109	defm V_CMPX_NLE_F64 : VOPCX_F64 <vopc<0x3c, 0x7c>, "v_cmpx_nle_f64">;
				110	defm V_CMPX_NEQ_F64 : VOPCX_F64 <vopc<0x3d, 0x7d>, "v_cmpx_neq_f64">;
				111	defm V_CMPX_NLT_F64 : VOPCX_F64 <vopc<0x3e, 0x7e>, "v_cmpx_nlt_f64">;
				112	defm V_CMPX_TRU_F64 : VOPCX_F64 <vopc<0x3f, 0x7f>, "v_cmpx_tru_f64">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	113
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	114
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	115	let SubtargetPredicate = isSICI in {
				116
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	117	defm V_CMPS_F_F32 : VOPC_F32 <vopc<0x40>, "v_cmps_f_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	118	defm V_CMPS_LT_F32 : VOPC_F32 <vopc<0x41>, "v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	119	defm V_CMPS_EQ_F32 : VOPC_F32 <vopc<0x42>, "v_cmps_eq_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	120	defm V_CMPS_LE_F32 : VOPC_F32 <vopc<0x43>, "v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	121	defm V_CMPS_GT_F32 : VOPC_F32 <vopc<0x44>, "v_cmps_gt_f32">;
				122	defm V_CMPS_LG_F32 : VOPC_F32 <vopc<0x45>, "v_cmps_lg_f32">;
				123	defm V_CMPS_GE_F32 : VOPC_F32 <vopc<0x46>, "v_cmps_ge_f32">;
				124	defm V_CMPS_O_F32 : VOPC_F32 <vopc<0x47>, "v_cmps_o_f32">;
				125	defm V_CMPS_U_F32 : VOPC_F32 <vopc<0x48>, "v_cmps_u_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	126	defm V_CMPS_NGE_F32 : VOPC_F32 <vopc<0x49>, "v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	127	defm V_CMPS_NLG_F32 : VOPC_F32 <vopc<0x4a>, "v_cmps_nlg_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	128	defm V_CMPS_NGT_F32 : VOPC_F32 <vopc<0x4b>, "v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	129	defm V_CMPS_NLE_F32 : VOPC_F32 <vopc<0x4c>, "v_cmps_nle_f32">;
				130	defm V_CMPS_NEQ_F32 : VOPC_F32 <vopc<0x4d>, "v_cmps_neq_f32">;
				131	defm V_CMPS_NLT_F32 : VOPC_F32 <vopc<0x4e>, "v_cmps_nlt_f32">;
				132	defm V_CMPS_TRU_F32 : VOPC_F32 <vopc<0x4f>, "v_cmps_tru_f32">;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	133
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	134
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	135	defm V_CMPSX_F_F32 : VOPCX_F32 <vopc<0x50>, "v_cmpsx_f_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	136	defm V_CMPSX_LT_F32 : VOPCX_F32 <vopc<0x51>, "v_cmpsx_lt_f32", "v_cmpsx_gt_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	137	defm V_CMPSX_EQ_F32 : VOPCX_F32 <vopc<0x52>, "v_cmpsx_eq_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	138	defm V_CMPSX_LE_F32 : VOPCX_F32 <vopc<0x53>, "v_cmpsx_le_f32", "v_cmpsx_ge_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	139	defm V_CMPSX_GT_F32 : VOPCX_F32 <vopc<0x54>, "v_cmpsx_gt_f32">;
				140	defm V_CMPSX_LG_F32 : VOPCX_F32 <vopc<0x55>, "v_cmpsx_lg_f32">;
				141	defm V_CMPSX_GE_F32 : VOPCX_F32 <vopc<0x56>, "v_cmpsx_ge_f32">;
				142	defm V_CMPSX_O_F32 : VOPCX_F32 <vopc<0x57>, "v_cmpsx_o_f32">;
				143	defm V_CMPSX_U_F32 : VOPCX_F32 <vopc<0x58>, "v_cmpsx_u_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	144	defm V_CMPSX_NGE_F32 : VOPCX_F32 <vopc<0x59>, "v_cmpsx_nge_f32", "v_cmpsx_nle_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	145	defm V_CMPSX_NLG_F32 : VOPCX_F32 <vopc<0x5a>, "v_cmpsx_nlg_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	146	defm V_CMPSX_NGT_F32 : VOPCX_F32 <vopc<0x5b>, "v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	147	defm V_CMPSX_NLE_F32 : VOPCX_F32 <vopc<0x5c>, "v_cmpsx_nle_f32">;
				148	defm V_CMPSX_NEQ_F32 : VOPCX_F32 <vopc<0x5d>, "v_cmpsx_neq_f32">;
				149	defm V_CMPSX_NLT_F32 : VOPCX_F32 <vopc<0x5e>, "v_cmpsx_nlt_f32">;
				150	defm V_CMPSX_TRU_F32 : VOPCX_F32 <vopc<0x5f>, "v_cmpsx_tru_f32">;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	151
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	152
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	153	defm V_CMPS_F_F64 : VOPC_F64 <vopc<0x60>, "v_cmps_f_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	154	defm V_CMPS_LT_F64 : VOPC_F64 <vopc<0x61>, "v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	155	defm V_CMPS_EQ_F64 : VOPC_F64 <vopc<0x62>, "v_cmps_eq_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	156	defm V_CMPS_LE_F64 : VOPC_F64 <vopc<0x63>, "v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	157	defm V_CMPS_GT_F64 : VOPC_F64 <vopc<0x64>, "v_cmps_gt_f64">;
				158	defm V_CMPS_LG_F64 : VOPC_F64 <vopc<0x65>, "v_cmps_lg_f64">;
				159	defm V_CMPS_GE_F64 : VOPC_F64 <vopc<0x66>, "v_cmps_ge_f64">;
				160	defm V_CMPS_O_F64 : VOPC_F64 <vopc<0x67>, "v_cmps_o_f64">;
				161	defm V_CMPS_U_F64 : VOPC_F64 <vopc<0x68>, "v_cmps_u_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	162	defm V_CMPS_NGE_F64 : VOPC_F64 <vopc<0x69>, "v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	163	defm V_CMPS_NLG_F64 : VOPC_F64 <vopc<0x6a>, "v_cmps_nlg_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	164	defm V_CMPS_NGT_F64 : VOPC_F64 <vopc<0x6b>, "v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	165	defm V_CMPS_NLE_F64 : VOPC_F64 <vopc<0x6c>, "v_cmps_nle_f64">;
				166	defm V_CMPS_NEQ_F64 : VOPC_F64 <vopc<0x6d>, "v_cmps_neq_f64">;
				167	defm V_CMPS_NLT_F64 : VOPC_F64 <vopc<0x6e>, "v_cmps_nlt_f64">;
				168	defm V_CMPS_TRU_F64 : VOPC_F64 <vopc<0x6f>, "v_cmps_tru_f64">;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	169
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	170
Matt Arsenault	05b617f	2015-03-23 18:45:23 +0000	[diff] [blame]	171	defm V_CMPSX_F_F64 : VOPCX_F64 <vopc<0x70>, "v_cmpsx_f_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	172	defm V_CMPSX_LT_F64 : VOPCX_F64 <vopc<0x71>, "v_cmpsx_lt_f64", "v_cmpsx_gt_f64">;
Matt Arsenault	05b617f	2015-03-23 18:45:23 +0000	[diff] [blame]	173	defm V_CMPSX_EQ_F64 : VOPCX_F64 <vopc<0x72>, "v_cmpsx_eq_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	174	defm V_CMPSX_LE_F64 : VOPCX_F64 <vopc<0x73>, "v_cmpsx_le_f64", "v_cmpsx_ge_f64">;
Matt Arsenault	05b617f	2015-03-23 18:45:23 +0000	[diff] [blame]	175	defm V_CMPSX_GT_F64 : VOPCX_F64 <vopc<0x74>, "v_cmpsx_gt_f64">;
				176	defm V_CMPSX_LG_F64 : VOPCX_F64 <vopc<0x75>, "v_cmpsx_lg_f64">;
				177	defm V_CMPSX_GE_F64 : VOPCX_F64 <vopc<0x76>, "v_cmpsx_ge_f64">;
				178	defm V_CMPSX_O_F64 : VOPCX_F64 <vopc<0x77>, "v_cmpsx_o_f64">;
				179	defm V_CMPSX_U_F64 : VOPCX_F64 <vopc<0x78>, "v_cmpsx_u_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	180	defm V_CMPSX_NGE_F64 : VOPCX_F64 <vopc<0x79>, "v_cmpsx_nge_f64", "v_cmpsx_nle_f64">;
Matt Arsenault	05b617f	2015-03-23 18:45:23 +0000	[diff] [blame]	181	defm V_CMPSX_NLG_F64 : VOPCX_F64 <vopc<0x7a>, "v_cmpsx_nlg_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	182	defm V_CMPSX_NGT_F64 : VOPCX_F64 <vopc<0x7b>, "v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">;
Matt Arsenault	05b617f	2015-03-23 18:45:23 +0000	[diff] [blame]	183	defm V_CMPSX_NLE_F64 : VOPCX_F64 <vopc<0x7c>, "v_cmpsx_nle_f64">;
				184	defm V_CMPSX_NEQ_F64 : VOPCX_F64 <vopc<0x7d>, "v_cmpsx_neq_f64">;
				185	defm V_CMPSX_NLT_F64 : VOPCX_F64 <vopc<0x7e>, "v_cmpsx_nlt_f64">;
				186	defm V_CMPSX_TRU_F64 : VOPCX_F64 <vopc<0x7f>, "v_cmpsx_tru_f64">;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	187
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	188	} // End SubtargetPredicate = isSICI
				189
				190	defm V_CMP_F_I32 : VOPC_I32 <vopc<0x80, 0xc0>, "v_cmp_f_i32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	191	defm V_CMP_LT_I32 : VOPC_I32 <vopc<0x81, 0xc1>, "v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	192	defm V_CMP_EQ_I32 : VOPC_I32 <vopc<0x82, 0xc2>, "v_cmp_eq_i32", COND_EQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	193	defm V_CMP_LE_I32 : VOPC_I32 <vopc<0x83, 0xc3>, "v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	194	defm V_CMP_GT_I32 : VOPC_I32 <vopc<0x84, 0xc4>, "v_cmp_gt_i32", COND_SGT>;
				195	defm V_CMP_NE_I32 : VOPC_I32 <vopc<0x85, 0xc5>, "v_cmp_ne_i32", COND_NE>;
				196	defm V_CMP_GE_I32 : VOPC_I32 <vopc<0x86, 0xc6>, "v_cmp_ge_i32", COND_SGE>;
				197	defm V_CMP_T_I32 : VOPC_I32 <vopc<0x87, 0xc7>, "v_cmp_t_i32">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	198
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	199
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	200	defm V_CMPX_F_I32 : VOPCX_I32 <vopc<0x90, 0xd0>, "v_cmpx_f_i32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	201	defm V_CMPX_LT_I32 : VOPCX_I32 <vopc<0x91, 0xd1>, "v_cmpx_lt_i32", "v_cmpx_gt_i32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	202	defm V_CMPX_EQ_I32 : VOPCX_I32 <vopc<0x92, 0xd2>, "v_cmpx_eq_i32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	203	defm V_CMPX_LE_I32 : VOPCX_I32 <vopc<0x93, 0xd3>, "v_cmpx_le_i32", "v_cmpx_ge_i32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	204	defm V_CMPX_GT_I32 : VOPCX_I32 <vopc<0x94, 0xd4>, "v_cmpx_gt_i32">;
				205	defm V_CMPX_NE_I32 : VOPCX_I32 <vopc<0x95, 0xd5>, "v_cmpx_ne_i32">;
				206	defm V_CMPX_GE_I32 : VOPCX_I32 <vopc<0x96, 0xd6>, "v_cmpx_ge_i32">;
				207	defm V_CMPX_T_I32 : VOPCX_I32 <vopc<0x97, 0xd7>, "v_cmpx_t_i32">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	208
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	209
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	210	defm V_CMP_F_I64 : VOPC_I64 <vopc<0xa0, 0xe0>, "v_cmp_f_i64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	211	defm V_CMP_LT_I64 : VOPC_I64 <vopc<0xa1, 0xe1>, "v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	212	defm V_CMP_EQ_I64 : VOPC_I64 <vopc<0xa2, 0xe2>, "v_cmp_eq_i64", COND_EQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	213	defm V_CMP_LE_I64 : VOPC_I64 <vopc<0xa3, 0xe3>, "v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	214	defm V_CMP_GT_I64 : VOPC_I64 <vopc<0xa4, 0xe4>, "v_cmp_gt_i64", COND_SGT>;
				215	defm V_CMP_NE_I64 : VOPC_I64 <vopc<0xa5, 0xe5>, "v_cmp_ne_i64", COND_NE>;
				216	defm V_CMP_GE_I64 : VOPC_I64 <vopc<0xa6, 0xe6>, "v_cmp_ge_i64", COND_SGE>;
				217	defm V_CMP_T_I64 : VOPC_I64 <vopc<0xa7, 0xe7>, "v_cmp_t_i64">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	218
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	219
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	220	defm V_CMPX_F_I64 : VOPCX_I64 <vopc<0xb0, 0xf0>, "v_cmpx_f_i64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	221	defm V_CMPX_LT_I64 : VOPCX_I64 <vopc<0xb1, 0xf1>, "v_cmpx_lt_i64", "v_cmpx_gt_i64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	222	defm V_CMPX_EQ_I64 : VOPCX_I64 <vopc<0xb2, 0xf2>, "v_cmpx_eq_i64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	223	defm V_CMPX_LE_I64 : VOPCX_I64 <vopc<0xb3, 0xf3>, "v_cmpx_le_i64", "v_cmpx_ge_i64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	224	defm V_CMPX_GT_I64 : VOPCX_I64 <vopc<0xb4, 0xf4>, "v_cmpx_gt_i64">;
				225	defm V_CMPX_NE_I64 : VOPCX_I64 <vopc<0xb5, 0xf5>, "v_cmpx_ne_i64">;
				226	defm V_CMPX_GE_I64 : VOPCX_I64 <vopc<0xb6, 0xf6>, "v_cmpx_ge_i64">;
				227	defm V_CMPX_T_I64 : VOPCX_I64 <vopc<0xb7, 0xf7>, "v_cmpx_t_i64">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	228
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	229
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	230	defm V_CMP_F_U32 : VOPC_I32 <vopc<0xc0, 0xc8>, "v_cmp_f_u32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	231	defm V_CMP_LT_U32 : VOPC_I32 <vopc<0xc1, 0xc9>, "v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	232	defm V_CMP_EQ_U32 : VOPC_I32 <vopc<0xc2, 0xca>, "v_cmp_eq_u32", COND_EQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	233	defm V_CMP_LE_U32 : VOPC_I32 <vopc<0xc3, 0xcb>, "v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	234	defm V_CMP_GT_U32 : VOPC_I32 <vopc<0xc4, 0xcc>, "v_cmp_gt_u32", COND_UGT>;
				235	defm V_CMP_NE_U32 : VOPC_I32 <vopc<0xc5, 0xcd>, "v_cmp_ne_u32", COND_NE>;
				236	defm V_CMP_GE_U32 : VOPC_I32 <vopc<0xc6, 0xce>, "v_cmp_ge_u32", COND_UGE>;
				237	defm V_CMP_T_U32 : VOPC_I32 <vopc<0xc7, 0xcf>, "v_cmp_t_u32">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	238
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	239
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	240	defm V_CMPX_F_U32 : VOPCX_I32 <vopc<0xd0, 0xd8>, "v_cmpx_f_u32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	241	defm V_CMPX_LT_U32 : VOPCX_I32 <vopc<0xd1, 0xd9>, "v_cmpx_lt_u32", "v_cmpx_gt_u32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	242	defm V_CMPX_EQ_U32 : VOPCX_I32 <vopc<0xd2, 0xda>, "v_cmpx_eq_u32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	243	defm V_CMPX_LE_U32 : VOPCX_I32 <vopc<0xd3, 0xdb>, "v_cmpx_le_u32", "v_cmpx_le_u32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	244	defm V_CMPX_GT_U32 : VOPCX_I32 <vopc<0xd4, 0xdc>, "v_cmpx_gt_u32">;
				245	defm V_CMPX_NE_U32 : VOPCX_I32 <vopc<0xd5, 0xdd>, "v_cmpx_ne_u32">;
				246	defm V_CMPX_GE_U32 : VOPCX_I32 <vopc<0xd6, 0xde>, "v_cmpx_ge_u32">;
				247	defm V_CMPX_T_U32 : VOPCX_I32 <vopc<0xd7, 0xdf>, "v_cmpx_t_u32">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	248
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	249
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	250	defm V_CMP_F_U64 : VOPC_I64 <vopc<0xe0, 0xe8>, "v_cmp_f_u64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	251	defm V_CMP_LT_U64 : VOPC_I64 <vopc<0xe1, 0xe9>, "v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	252	defm V_CMP_EQ_U64 : VOPC_I64 <vopc<0xe2, 0xea>, "v_cmp_eq_u64", COND_EQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	253	defm V_CMP_LE_U64 : VOPC_I64 <vopc<0xe3, 0xeb>, "v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	254	defm V_CMP_GT_U64 : VOPC_I64 <vopc<0xe4, 0xec>, "v_cmp_gt_u64", COND_UGT>;
				255	defm V_CMP_NE_U64 : VOPC_I64 <vopc<0xe5, 0xed>, "v_cmp_ne_u64", COND_NE>;
				256	defm V_CMP_GE_U64 : VOPC_I64 <vopc<0xe6, 0xee>, "v_cmp_ge_u64", COND_UGE>;
				257	defm V_CMP_T_U64 : VOPC_I64 <vopc<0xe7, 0xef>, "v_cmp_t_u64">;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	258
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	259	defm V_CMPX_F_U64 : VOPCX_I64 <vopc<0xf0, 0xf8>, "v_cmpx_f_u64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	260	defm V_CMPX_LT_U64 : VOPCX_I64 <vopc<0xf1, 0xf9>, "v_cmpx_lt_u64", "v_cmpx_gt_u64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	261	defm V_CMPX_EQ_U64 : VOPCX_I64 <vopc<0xf2, 0xfa>, "v_cmpx_eq_u64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	262	defm V_CMPX_LE_U64 : VOPCX_I64 <vopc<0xf3, 0xfb>, "v_cmpx_le_u64", "v_cmpx_ge_u64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	263	defm V_CMPX_GT_U64 : VOPCX_I64 <vopc<0xf4, 0xfc>, "v_cmpx_gt_u64">;
				264	defm V_CMPX_NE_U64 : VOPCX_I64 <vopc<0xf5, 0xfd>, "v_cmpx_ne_u64">;
				265	defm V_CMPX_GE_U64 : VOPCX_I64 <vopc<0xf6, 0xfe>, "v_cmpx_ge_u64">;
				266	defm V_CMPX_T_U64 : VOPCX_I64 <vopc<0xf7, 0xff>, "v_cmpx_t_u64">;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	267
Matt Arsenault	0943b0e	2015-03-23 18:45:38 +0000	[diff] [blame]	268	} // End isCompare = 1, isCommutable = 1
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	269
Matt Arsenault	4831ce5	2015-01-06 23:00:37 +0000	[diff] [blame]	270	defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <vopc<0x88, 0x10>, "v_cmp_class_f32">;
Matt Arsenault	4831ce5	2015-01-06 23:00:37 +0000	[diff] [blame]	271	defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <vopc<0x98, 0x11>, "v_cmpx_class_f32">;
Matt Arsenault	4831ce5	2015-01-06 23:00:37 +0000	[diff] [blame]	272	defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <vopc<0xa8, 0x12>, "v_cmp_class_f64">;
Matt Arsenault	4831ce5	2015-01-06 23:00:37 +0000	[diff] [blame]	273	defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <vopc<0xb8, 0x13>, "v_cmpx_class_f64">;
Matt Arsenault	42f39e1	2015-03-23 18:45:35 +0000	[diff] [blame]	274
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	275	//===----------------------------------------------------------------------===//
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	276	// VOP1 Instructions
				277	//===----------------------------------------------------------------------===//
				278
Tom Stellard	88e0b25	2015-10-06 15:57:53 +0000	[diff] [blame]	279	let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in {
				280	defm V_NOP : VOP1Inst <vop1<0x0>, "v_nop", VOP_NONE>;
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	281	}
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	282
Matthias Braun	e1a6741	2015-04-24 00:25:50 +0000	[diff] [blame]	283	let isMoveImm = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in {
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	284	defm V_MOV_B32 : VOP1Inst <vop1<0x1>, "v_mov_b32", VOP_I32_I32>;
Matt Arsenault	f273370	2014-07-30 03:18:57 +0000	[diff] [blame]	285	} // End isMoveImm = 1
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	286
Tom Stellard	fbe435d	2014-03-17 17:03:51 +0000	[diff] [blame]	287	let Uses = [EXEC] in {
				288
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	289	// FIXME: Specify SchedRW for READFIRSTLANE_B32
				290
Tom Stellard	fbe435d	2014-03-17 17:03:51 +0000	[diff] [blame]	291	def V_READFIRSTLANE_B32 : VOP1 <
				292	0x00000002,
				293	(outs SReg_32:$vdst),
Changpeng Fang	75f0968	2016-08-24 20:35:23 +0000	[diff] [blame]	294	(ins VGPR_32:$src0),
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	295	"v_readfirstlane_b32 $vdst, $src0",
Changpeng Fang	75f0968	2016-08-24 20:35:23 +0000	[diff] [blame]	296	[(set i32:$vdst, (int_amdgcn_readfirstlane i32:$src0))]
Matt Arsenault	4234542	2016-05-11 00:32:31 +0000	[diff] [blame]	297	> {
				298	let isConvergent = 1;
				299	}
Tom Stellard	fbe435d	2014-03-17 17:03:51 +0000	[diff] [blame]	300
				301	}
				302
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	303	let SchedRW = [WriteQuarterRate32] in {
				304
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	305	defm V_CVT_I32_F64 : VOP1Inst <vop1<0x3>, "v_cvt_i32_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	306	VOP_I32_F64, fp_to_sint
Niels Ole Salscheider	4715d88	2013-08-08 16:06:08 +0000	[diff] [blame]	307	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	308	defm V_CVT_F64_I32 : VOP1Inst <vop1<0x4>, "v_cvt_f64_i32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	309	VOP_F64_I32, sint_to_fp
Niels Ole Salscheider	4715d88	2013-08-08 16:06:08 +0000	[diff] [blame]	310	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	311	defm V_CVT_F32_I32 : VOP1Inst <vop1<0x5>, "v_cvt_f32_i32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	312	VOP_F32_I32, sint_to_fp
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	313	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	314	defm V_CVT_F32_U32 : VOP1Inst <vop1<0x6>, "v_cvt_f32_u32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	315	VOP_F32_I32, uint_to_fp
Tom Stellard	c932d73	2013-05-06 23:02:07 +0000	[diff] [blame]	316	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	317	defm V_CVT_U32_F32 : VOP1Inst <vop1<0x7>, "v_cvt_u32_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	318	VOP_I32_F32, fp_to_uint
Tom Stellard	73c31d5	2013-08-14 22:21:57 +0000	[diff] [blame]	319	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	320	defm V_CVT_I32_F32 : VOP1Inst <vop1<0x8>, "v_cvt_i32_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	321	VOP_I32_F32, fp_to_sint
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	322	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	323	defm V_CVT_F16_F32 : VOP1Inst <vop1<0xa>, "v_cvt_f16_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	324	VOP_I32_F32, fp_to_f16
Matt Arsenault	b0df925	2014-07-10 03:22:20 +0000	[diff] [blame]	325	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	326	defm V_CVT_F32_F16 : VOP1Inst <vop1<0xb>, "v_cvt_f32_f16",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	327	VOP_F32_I32, f16_to_fp
Matt Arsenault	b0df925	2014-07-10 03:22:20 +0000	[diff] [blame]	328	>;
Matt Arsenault	eeb2a7e	2015-01-15 23:58:35 +0000	[diff] [blame]	329	defm V_CVT_RPI_I32_F32 : VOP1Inst <vop1<0xc>, "v_cvt_rpi_i32_f32",
				330	VOP_I32_F32, cvt_rpi_i32_f32>;
				331	defm V_CVT_FLR_I32_F32 : VOP1Inst <vop1<0xd>, "v_cvt_flr_i32_f32",
				332	VOP_I32_F32, cvt_flr_i32_f32>;
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	333	defm V_CVT_OFF_F32_I4 : VOP1Inst <vop1<0x0e>, "v_cvt_off_f32_i4", VOP_F32_I32>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	334	defm V_CVT_F32_F64 : VOP1Inst <vop1<0xf>, "v_cvt_f32_f64",
Michael Kuperstein	2bc3d4d	2016-08-18 20:08:15 +0000	[diff] [blame]	335	VOP_F32_F64, fpround
Niels Ole Salscheider	719fbc9	2013-08-08 16:06:15 +0000	[diff] [blame]	336	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	337	defm V_CVT_F64_F32 : VOP1Inst <vop1<0x10>, "v_cvt_f64_f32",
Michael Kuperstein	2bc3d4d	2016-08-18 20:08:15 +0000	[diff] [blame]	338	VOP_F64_F32, fpextend
Niels Ole Salscheider	719fbc9	2013-08-08 16:06:15 +0000	[diff] [blame]	339	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	340	defm V_CVT_F32_UBYTE0 : VOP1Inst <vop1<0x11>, "v_cvt_f32_ubyte0",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	341	VOP_F32_I32, AMDGPUcvt_f32_ubyte0
Matt Arsenault	364a674	2014-06-11 17:50:44 +0000	[diff] [blame]	342	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	343	defm V_CVT_F32_UBYTE1 : VOP1Inst <vop1<0x12>, "v_cvt_f32_ubyte1",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	344	VOP_F32_I32, AMDGPUcvt_f32_ubyte1
Matt Arsenault	364a674	2014-06-11 17:50:44 +0000	[diff] [blame]	345	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	346	defm V_CVT_F32_UBYTE2 : VOP1Inst <vop1<0x13>, "v_cvt_f32_ubyte2",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	347	VOP_F32_I32, AMDGPUcvt_f32_ubyte2
Matt Arsenault	364a674	2014-06-11 17:50:44 +0000	[diff] [blame]	348	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	349	defm V_CVT_F32_UBYTE3 : VOP1Inst <vop1<0x14>, "v_cvt_f32_ubyte3",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	350	VOP_F32_I32, AMDGPUcvt_f32_ubyte3
Matt Arsenault	364a674	2014-06-11 17:50:44 +0000	[diff] [blame]	351	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	352	defm V_CVT_U32_F64 : VOP1Inst <vop1<0x15>, "v_cvt_u32_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	353	VOP_I32_F64, fp_to_uint
Matt Arsenault	c3a73c3	2014-05-22 03:20:30 +0000	[diff] [blame]	354	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	355	defm V_CVT_F64_U32 : VOP1Inst <vop1<0x16>, "v_cvt_f64_u32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	356	VOP_F64_I32, uint_to_fp
Matt Arsenault	c3a73c3	2014-05-22 03:20:30 +0000	[diff] [blame]	357	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	358
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	359	} // End SchedRW = [WriteQuarterRate32]
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	360
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	361	defm V_FRACT_F32 : VOP1Inst <vop1<0x20, 0x1b>, "v_fract_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	362	VOP_F32_F32, AMDGPUfract
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	363	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	364	defm V_TRUNC_F32 : VOP1Inst <vop1<0x21, 0x1c>, "v_trunc_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	365	VOP_F32_F32, ftrunc
Tom Stellard	9b3d253	2013-05-06 23:02:00 +0000	[diff] [blame]	366	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	367	defm V_CEIL_F32 : VOP1Inst <vop1<0x22, 0x1d>, "v_ceil_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	368	VOP_F32_F32, fceil
Michel Danzer	c3ea404	2013-02-22 11:22:49 +0000	[diff] [blame]	369	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	370	defm V_RNDNE_F32 : VOP1Inst <vop1<0x23, 0x1e>, "v_rndne_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	371	VOP_F32_F32, frint
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	372	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	373	defm V_FLOOR_F32 : VOP1Inst <vop1<0x24, 0x1f>, "v_floor_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	374	VOP_F32_F32, ffloor
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	375	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	376	defm V_EXP_F32 : VOP1Inst <vop1<0x25, 0x20>, "v_exp_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	377	VOP_F32_F32, fexp2
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	378	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	379
				380	let SchedRW = [WriteQuarterRate32] in {
				381
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	382	defm V_LOG_F32 : VOP1Inst <vop1<0x27, 0x21>, "v_log_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	383	VOP_F32_F32, flog2
Michel Danzer	349cabe	2013-02-07 14:55:16 +0000	[diff] [blame]	384	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	385	defm V_RCP_F32 : VOP1Inst <vop1<0x2a, 0x22>, "v_rcp_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	386	VOP_F32_F32, AMDGPUrcp
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	387	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	388	defm V_RCP_IFLAG_F32 : VOP1Inst <vop1<0x2b, 0x23>, "v_rcp_iflag_f32",
				389	VOP_F32_F32
Matt Arsenault	257d48d	2014-06-24 22:13:39 +0000	[diff] [blame]	390	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	391	defm V_RSQ_F32 : VOP1Inst <vop1<0x2e, 0x24>, "v_rsq_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	392	VOP_F32_F32, AMDGPUrsq
Matt Arsenault	1513046	2014-06-05 00:15:55 +0000	[diff] [blame]	393	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	394
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	395	} // End SchedRW = [WriteQuarterRate32]
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	396
				397	let SchedRW = [WriteDouble] in {
				398
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	399	defm V_RCP_F64 : VOP1Inst <vop1<0x2f, 0x25>, "v_rcp_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	400	VOP_F64_F64, AMDGPUrcp
Tom Stellard	7512c08	2013-07-12 18:14:56 +0000	[diff] [blame]	401	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	402	defm V_RSQ_F64 : VOP1Inst <vop1<0x31, 0x26>, "v_rsq_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	403	VOP_F64_F64, AMDGPUrsq
Matt Arsenault	1513046	2014-06-05 00:15:55 +0000	[diff] [blame]	404	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	405
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	406	} // End SchedRW = [WriteDouble];
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	407
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	408	defm V_SQRT_F32 : VOP1Inst <vop1<0x33, 0x27>, "v_sqrt_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	409	VOP_F32_F32, fsqrt
Tom Stellard	8ed7b45	2013-07-12 18:15:13 +0000	[diff] [blame]	410	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	411
				412	let SchedRW = [WriteDouble] in {
				413
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	414	defm V_SQRT_F64 : VOP1Inst <vop1<0x34, 0x28>, "v_sqrt_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	415	VOP_F64_F64, fsqrt
Tom Stellard	8ed7b45	2013-07-12 18:15:13 +0000	[diff] [blame]	416	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	417
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	418	} // End SchedRW = [WriteDouble]
				419
				420	let SchedRW = [WriteQuarterRate32] in {
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	421
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	422	defm V_SIN_F32 : VOP1Inst <vop1<0x35, 0x29>, "v_sin_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	423	VOP_F32_F32, AMDGPUsin
Matt Arsenault	ad14ce8	2014-07-19 18:44:39 +0000	[diff] [blame]	424	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	425	defm V_COS_F32 : VOP1Inst <vop1<0x36, 0x2a>, "v_cos_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	426	VOP_F32_F32, AMDGPUcos
Matt Arsenault	ad14ce8	2014-07-19 18:44:39 +0000	[diff] [blame]	427	>;
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	428
				429	} // End SchedRW = [WriteQuarterRate32]
				430
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	431	defm V_NOT_B32 : VOP1Inst <vop1<0x37, 0x2b>, "v_not_b32", VOP_I32_I32>;
				432	defm V_BFREV_B32 : VOP1Inst <vop1<0x38, 0x2c>, "v_bfrev_b32", VOP_I32_I32>;
				433	defm V_FFBH_U32 : VOP1Inst <vop1<0x39, 0x2d>, "v_ffbh_u32", VOP_I32_I32>;
				434	defm V_FFBL_B32 : VOP1Inst <vop1<0x3a, 0x2e>, "v_ffbl_b32", VOP_I32_I32>;
				435	defm V_FFBH_I32 : VOP1Inst <vop1<0x3b, 0x2f>, "v_ffbh_i32", VOP_I32_I32>;
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	436	defm V_FREXP_EXP_I32_F64 : VOP1Inst <vop1<0x3c,0x30>, "v_frexp_exp_i32_f64",
Matt Arsenault	2fe4fbc	2016-03-30 22:28:52 +0000	[diff] [blame]	437	VOP_I32_F64, int_amdgcn_frexp_exp
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	438	>;
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	439
				440	let SchedRW = [WriteDoubleAdd] in {
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	441	defm V_FREXP_MANT_F64 : VOP1Inst <vop1<0x3d, 0x31>, "v_frexp_mant_f64",
Matt Arsenault	b96b573	2016-03-21 16:11:05 +0000	[diff] [blame]	442	VOP_F64_F64, int_amdgcn_frexp_mant
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	443	>;
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	444
				445	defm V_FRACT_F64 : VOP1Inst <vop1<0x3e, 0x32>, "v_fract_f64",
Matt Arsenault	7401516	2016-05-28 00:19:52 +0000	[diff] [blame]	446	VOP_F64_F64, AMDGPUfract
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	447	>;
				448	} // End SchedRW = [WriteDoubleAdd]
				449
				450
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	451	defm V_FREXP_EXP_I32_F32 : VOP1Inst <vop1<0x3f, 0x33>, "v_frexp_exp_i32_f32",
Matt Arsenault	2fe4fbc	2016-03-30 22:28:52 +0000	[diff] [blame]	452	VOP_I32_F32, int_amdgcn_frexp_exp
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	453	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	454	defm V_FREXP_MANT_F32 : VOP1Inst <vop1<0x40, 0x34>, "v_frexp_mant_f32",
Matt Arsenault	b96b573	2016-03-21 16:11:05 +0000	[diff] [blame]	455	VOP_F32_F32, int_amdgcn_frexp_mant
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	456	>;
Tom Stellard	88e0b25	2015-10-06 15:57:53 +0000	[diff] [blame]	457	let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in {
Sam Kolton	3025e7f	2016-04-26 13:33:56 +0000	[diff] [blame]	458	defm V_CLREXCP : VOP1Inst <vop1<0x41,0x35>, "v_clrexcp", VOP_NO_EXT<VOP_NONE>>;
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	459	}
Matt Arsenault	fc0ad42	2015-10-07 17:46:32 +0000	[diff] [blame]	460
				461	let Uses = [M0, EXEC] in {
Matt Arsenault	cb540bc	2016-07-19 00:35:03 +0000	[diff] [blame]	462	// v_movreld_b32 is a special case because the destination output
				463	// register is really a source. It isn't actually read (but may be
				464	// written), and is only to provide the base register to start
				465	// indexing from. Tablegen seems to not let you define an implicit
				466	// virtual register output for the super register being written into,
				467	// so this must have an implicit def of the register added to it.
				468	defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42, 0x36>, "v_movreld_b32", VOP_MOVRELD>;
				469	defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43, 0x37>, "v_movrels_b32", VOP_I32_VI32_NO_EXT>;
Sam Kolton	3025e7f	2016-04-26 13:33:56 +0000	[diff] [blame]	470	defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44, 0x38>, "v_movrelsd_b32", VOP_NO_EXT<VOP_I32_I32>>;
Matt Arsenault	cb540bc	2016-07-19 00:35:03 +0000	[diff] [blame]	471
Matt Arsenault	fc0ad42	2015-10-07 17:46:32 +0000	[diff] [blame]	472	} // End Uses = [M0, EXEC]
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	473
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	474	// These instruction only exist on SI and CI
				475	let SubtargetPredicate = isSICI in {
				476
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	477	let SchedRW = [WriteQuarterRate32] in {
				478
Tom Stellard	4b3e755	2015-04-23 19:33:52 +0000	[diff] [blame]	479	defm V_MOV_FED_B32 : VOP1InstSI <vop1<0x9>, "v_mov_fed_b32", VOP_I32_I32>;
Matt Arsenault	ce56a0e	2016-02-13 01:19:56 +0000	[diff] [blame]	480	defm V_LOG_CLAMP_F32 : VOP1InstSI <vop1<0x26>, "v_log_clamp_f32",
				481	VOP_F32_F32, int_amdgcn_log_clamp>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	482	defm V_RCP_CLAMP_F32 : VOP1InstSI <vop1<0x28>, "v_rcp_clamp_f32", VOP_F32_F32>;
Matt Arsenault	32fc527	2016-07-26 16:45:45 +0000	[diff] [blame]	483	defm V_RCP_LEGACY_F32 : VOP1InstSI <vop1<0x29>, "v_rcp_legacy_f32",
				484	VOP_F32_F32, AMDGPUrcp_legacy>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	485	defm V_RSQ_CLAMP_F32 : VOP1InstSI <vop1<0x2c>, "v_rsq_clamp_f32",
Matt Arsenault	79963e8	2016-02-13 01:03:00 +0000	[diff] [blame]	486	VOP_F32_F32, AMDGPUrsq_clamp
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	487	>;
				488	defm V_RSQ_LEGACY_F32 : VOP1InstSI <vop1<0x2d>, "v_rsq_legacy_f32",
				489	VOP_F32_F32, AMDGPUrsq_legacy
				490	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	491
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	492	} // End SchedRW = [WriteQuarterRate32]
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	493
				494	let SchedRW = [WriteDouble] in {
				495
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	496	defm V_RCP_CLAMP_F64 : VOP1InstSI <vop1<0x30>, "v_rcp_clamp_f64", VOP_F64_F64>;
				497	defm V_RSQ_CLAMP_F64 : VOP1InstSI <vop1<0x32>, "v_rsq_clamp_f64",
Matt Arsenault	79963e8	2016-02-13 01:03:00 +0000	[diff] [blame]	498	VOP_F64_F64, AMDGPUrsq_clamp
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	499	>;
				500
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	501	} // End SchedRW = [WriteDouble]
				502
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	503	} // End SubtargetPredicate = isSICI
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	504
				505	//===----------------------------------------------------------------------===//
				506	// VINTRP Instructions
				507	//===----------------------------------------------------------------------===//
				508
Matt Arsenault	80f766a	2015-09-10 01:23:28 +0000	[diff] [blame]	509	let Uses = [M0, EXEC] in {
Tom Stellard	2a9d947	2015-05-12 15:00:46 +0000	[diff] [blame]	510
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	511	// FIXME: Specify SchedRW for VINTRP insturctions.
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	512
				513	multiclass V_INTERP_P1_F32_m : VINTRP_m <
				514	0x00000000,
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	515	(outs VGPR_32:$dst),
Tom Stellard	2a9d947	2015-05-12 15:00:46 +0000	[diff] [blame]	516	(ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr),
				517	"v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [m0]",
				518	[(set f32:$dst, (AMDGPUinterp_p1 i32:$i, (i32 imm:$attr_chan),
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	519	(i32 imm:$attr)))]
				520	>;
				521
				522	let OtherPredicates = [has32BankLDS] in {
				523
				524	defm V_INTERP_P1_F32 : V_INTERP_P1_F32_m;
				525
				526	} // End OtherPredicates = [has32BankLDS]
				527
Tom Stellard	e1818af	2016-02-18 03:42:32 +0000	[diff] [blame]	528	let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1 in {
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	529
				530	defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m;
				531
Tom Stellard	e1818af	2016-02-18 03:42:32 +0000	[diff] [blame]	532	} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	533
Tom Stellard	5082816	2015-05-25 16:15:56 +0000	[diff] [blame]	534	let DisableEncoding = "$src0", Constraints = "$src0 = $dst" in {
				535
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	536	defm V_INTERP_P2_F32 : VINTRP_m <
Tom Stellard	c70cf90	2015-05-25 16:15:50 +0000	[diff] [blame]	537	0x00000001,
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	538	(outs VGPR_32:$dst),
Tom Stellard	2a9d947	2015-05-12 15:00:46 +0000	[diff] [blame]	539	(ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr),
				540	"v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [m0]",
				541	[(set f32:$dst, (AMDGPUinterp_p2 f32:$src0, i32:$j, (i32 imm:$attr_chan),
Tom Stellard	5082816	2015-05-25 16:15:56 +0000	[diff] [blame]	542	(i32 imm:$attr)))]>;
				543
				544	} // End DisableEncoding = "$src0", Constraints = "$src0 = $dst"
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	545
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	546	defm V_INTERP_MOV_F32 : VINTRP_m <
Tom Stellard	c70cf90	2015-05-25 16:15:50 +0000	[diff] [blame]	547	0x00000002,
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	548	(outs VGPR_32:$dst),
Tom Stellard	2a9d947	2015-05-12 15:00:46 +0000	[diff] [blame]	549	(ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr),
				550	"v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [m0]",
				551	[(set f32:$dst, (AMDGPUinterp_mov (i32 imm:$src0), (i32 imm:$attr_chan),
				552	(i32 imm:$attr)))]>;
				553
Matt Arsenault	80f766a	2015-09-10 01:23:28 +0000	[diff] [blame]	554	} // End Uses = [M0, EXEC]
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	555
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	556	//===----------------------------------------------------------------------===//
				557	// VOP2 Instructions
				558	//===----------------------------------------------------------------------===//
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	559
Artem Tamazov	1354877	2016-06-06 15:23:43 +0000	[diff] [blame]	560	defm V_CNDMASK_B32 : VOP2eInst <vop2<0x0, 0x0>, "v_cndmask_b32",
				561	VOP2e_I32_I32_I32_I1
				562	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	563
				564	let isCommutable = 1 in {
				565	defm V_ADD_F32 : VOP2Inst <vop2<0x3, 0x1>, "v_add_f32",
				566	VOP_F32_F32_F32, fadd
				567	>;
				568
				569	defm V_SUB_F32 : VOP2Inst <vop2<0x4, 0x2>, "v_sub_f32", VOP_F32_F32_F32, fsub>;
				570	defm V_SUBREV_F32 : VOP2Inst <vop2<0x5, 0x3>, "v_subrev_f32",
				571	VOP_F32_F32_F32, null_frag, "v_sub_f32"
				572	>;
				573	} // End isCommutable = 1
				574
				575	let isCommutable = 1 in {
				576
				577	defm V_MUL_LEGACY_F32 : VOP2Inst <vop2<0x7, 0x4>, "v_mul_legacy_f32",
Matt Arsenault	32fc527	2016-07-26 16:45:45 +0000	[diff] [blame]	578	VOP_F32_F32_F32, AMDGPUfmul_legacy
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	579	>;
				580
				581	defm V_MUL_F32 : VOP2Inst <vop2<0x8, 0x5>, "v_mul_f32",
				582	VOP_F32_F32_F32, fmul
				583	>;
				584
				585	defm V_MUL_I32_I24 : VOP2Inst <vop2<0x9, 0x6>, "v_mul_i32_i24",
				586	VOP_I32_I32_I32, AMDGPUmul_i24
				587	>;
Tom Stellard	894b988	2015-02-18 16:08:14 +0000	[diff] [blame]	588
				589	defm V_MUL_HI_I32_I24 : VOP2Inst <vop2<0xa,0x7>, "v_mul_hi_i32_i24",
Matt Arsenault	2712d4a	2016-08-27 01:32:27 +0000	[diff] [blame]	590	VOP_I32_I32_I32, AMDGPUmulhi_i24
Tom Stellard	894b988	2015-02-18 16:08:14 +0000	[diff] [blame]	591	>;
				592
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	593	defm V_MUL_U32_U24 : VOP2Inst <vop2<0xb, 0x8>, "v_mul_u32_u24",
				594	VOP_I32_I32_I32, AMDGPUmul_u24
				595	>;
Tom Stellard	894b988	2015-02-18 16:08:14 +0000	[diff] [blame]	596
				597	defm V_MUL_HI_U32_U24 : VOP2Inst <vop2<0xc,0x9>, "v_mul_hi_u32_u24",
Matt Arsenault	2712d4a	2016-08-27 01:32:27 +0000	[diff] [blame]	598	VOP_I32_I32_I32, AMDGPUmulhi_u24
Tom Stellard	894b988	2015-02-18 16:08:14 +0000	[diff] [blame]	599	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	600
				601	defm V_MIN_F32 : VOP2Inst <vop2<0xf, 0xa>, "v_min_f32", VOP_F32_F32_F32,
				602	fminnum>;
				603	defm V_MAX_F32 : VOP2Inst <vop2<0x10, 0xb>, "v_max_f32", VOP_F32_F32_F32,
				604	fmaxnum>;
Marek Olsak	24ae2cd	2015-02-03 21:53:08 +0000	[diff] [blame]	605	defm V_MIN_I32 : VOP2Inst <vop2<0x11, 0xc>, "v_min_i32", VOP_I32_I32_I32>;
				606	defm V_MAX_I32 : VOP2Inst <vop2<0x12, 0xd>, "v_max_i32", VOP_I32_I32_I32>;
				607	defm V_MIN_U32 : VOP2Inst <vop2<0x13, 0xe>, "v_min_u32", VOP_I32_I32_I32>;
				608	defm V_MAX_U32 : VOP2Inst <vop2<0x14, 0xf>, "v_max_u32", VOP_I32_I32_I32>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	609
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	610	defm V_LSHRREV_B32 : VOP2Inst <
				611	vop2<0x16, 0x10>, "v_lshrrev_b32", VOP_I32_I32_I32, null_frag,
Marek Olsak	7585a29	2015-02-03 17:38:05 +0000	[diff] [blame]	612	"v_lshr_b32"
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	613	>;
				614
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	615	defm V_ASHRREV_I32 : VOP2Inst <
				616	vop2<0x18, 0x11>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag,
Marek Olsak	7585a29	2015-02-03 17:38:05 +0000	[diff] [blame]	617	"v_ashr_i32"
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	618	>;
				619
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	620	defm V_LSHLREV_B32 : VOP2Inst <
				621	vop2<0x1a, 0x12>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag,
Marek Olsak	7585a29	2015-02-03 17:38:05 +0000	[diff] [blame]	622	"v_lshl_b32"
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	623	>;
				624
Marek Olsak	24ae2cd	2015-02-03 21:53:08 +0000	[diff] [blame]	625	defm V_AND_B32 : VOP2Inst <vop2<0x1b, 0x13>, "v_and_b32", VOP_I32_I32_I32>;
				626	defm V_OR_B32 : VOP2Inst <vop2<0x1c, 0x14>, "v_or_b32", VOP_I32_I32_I32>;
				627	defm V_XOR_B32 : VOP2Inst <vop2<0x1d, 0x15>, "v_xor_b32", VOP_I32_I32_I32>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	628
Tom Stellard	cc4c871	2016-02-16 18:14:56 +0000	[diff] [blame]	629	let Constraints = "$vdst = $src2", DisableEncoding="$src2",
Tom Stellard	db5a11f	2015-07-13 15:47:57 +0000	[diff] [blame]	630	isConvertibleToThreeAddress = 1 in {
				631	defm V_MAC_F32 : VOP2Inst <vop2<0x1f, 0x16>, "v_mac_f32", VOP_MAC>;
				632	}
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	633	} // End isCommutable = 1
				634
Nikolay Haustov	6560781	2016-03-11 09:27:25 +0000	[diff] [blame]	635	defm V_MADMK_F32 : VOP2MADK <vop2<0x20, 0x17>, "v_madmk_f32", VOP_MADMK>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	636
				637	let isCommutable = 1 in {
Nikolay Haustov	6560781	2016-03-11 09:27:25 +0000	[diff] [blame]	638	defm V_MADAK_F32 : VOP2MADK <vop2<0x21, 0x18>, "v_madak_f32", VOP_MADAK>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	639	} // End isCommutable = 1
				640
Matt Arsenault	86d336e	2015-09-08 21:15:00 +0000	[diff] [blame]	641	let isCommutable = 1 in {
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	642	// No patterns so that the scalar instructions are always selected.
				643	// The scalar versions will be replaced with vector when needed later.
				644
				645	// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in VI,
				646	// but the VI instructions behave the same as the SI versions.
				647	defm V_ADD_I32 : VOP2bInst <vop2<0x25, 0x19>, "v_add_i32",
Matt Arsenault	e4d0c14	2015-08-29 07:16:50 +0000	[diff] [blame]	648	VOP2b_I32_I1_I32_I32
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	649	>;
Matt Arsenault	e4d0c14	2015-08-29 07:16:50 +0000	[diff] [blame]	650	defm V_SUB_I32 : VOP2bInst <vop2<0x26, 0x1a>, "v_sub_i32", VOP2b_I32_I1_I32_I32>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	651
				652	defm V_SUBREV_I32 : VOP2bInst <vop2<0x27, 0x1b>, "v_subrev_i32",
Matt Arsenault	e4d0c14	2015-08-29 07:16:50 +0000	[diff] [blame]	653	VOP2b_I32_I1_I32_I32, null_frag, "v_sub_i32"
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	654	>;
				655
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	656	defm V_ADDC_U32 : VOP2bInst <vop2<0x28, 0x1c>, "v_addc_u32",
Matt Arsenault	86d336e	2015-09-08 21:15:00 +0000	[diff] [blame]	657	VOP2b_I32_I1_I32_I32_I1
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	658	>;
				659	defm V_SUBB_U32 : VOP2bInst <vop2<0x29, 0x1d>, "v_subb_u32",
Matt Arsenault	86d336e	2015-09-08 21:15:00 +0000	[diff] [blame]	660	VOP2b_I32_I1_I32_I32_I1
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	661	>;
				662	defm V_SUBBREV_U32 : VOP2bInst <vop2<0x2a, 0x1e>, "v_subbrev_u32",
Matt Arsenault	86d336e	2015-09-08 21:15:00 +0000	[diff] [blame]	663	VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32"
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	664	>;
				665
Matt Arsenault	86d336e	2015-09-08 21:15:00 +0000	[diff] [blame]	666	} // End isCommutable = 1
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	667
Matt Arsenault	529cf25	2016-06-23 01:26:16 +0000	[diff] [blame]	668	// These are special and do not read the exec mask.
				669	let isConvergent = 1, Uses = []<Register> in {
Matt Arsenault	4234542	2016-05-11 00:32:31 +0000	[diff] [blame]	670
Marek Olsak	15e4a59	2015-01-15 18:42:55 +0000	[diff] [blame]	671	defm V_READLANE_B32 : VOP2SI_3VI_m <
				672	vop3 <0x001, 0x289>,
				673	"v_readlane_b32",
Tom Stellard	c149dc0	2013-11-27 21:23:35 +0000	[diff] [blame]	674	(outs SReg_32:$vdst),
Sam Kolton	1eeb11b	2016-09-09 14:44:04 +0000	[diff] [blame]	675	(ins VGPR_32:$src0, SCSrc_b32:$src1),
Changpeng Fang	75f0968	2016-08-24 20:35:23 +0000	[diff] [blame]	676	"v_readlane_b32 $vdst, $src0, $src1",
				677	[(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))]
Tom Stellard	c149dc0	2013-11-27 21:23:35 +0000	[diff] [blame]	678	>;
				679
Marek Olsak	15e4a59	2015-01-15 18:42:55 +0000	[diff] [blame]	680	defm V_WRITELANE_B32 : VOP2SI_3VI_m <
				681	vop3 <0x002, 0x28a>,
				682	"v_writelane_b32",
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	683	(outs VGPR_32:$vdst),
Sam Kolton	1eeb11b	2016-09-09 14:44:04 +0000	[diff] [blame]	684	(ins SReg_32:$src0, SCSrc_b32:$src1),
Marek Olsak	9b8f32e	2015-02-18 22:12:45 +0000	[diff] [blame]	685	"v_writelane_b32 $vdst, $src0, $src1"
Tom Stellard	c149dc0	2013-11-27 21:23:35 +0000	[diff] [blame]	686	>;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	687
Matt Arsenault	4234542	2016-05-11 00:32:31 +0000	[diff] [blame]	688	} // End isConvergent = 1
				689
Marek Olsak	15e4a59	2015-01-15 18:42:55 +0000	[diff] [blame]	690	// These instructions only exist on SI and CI
				691	let SubtargetPredicate = isSICI in {
				692
Tom Stellard	85656ca	2015-08-07 15:34:30 +0000	[diff] [blame]	693	let isCommutable = 1 in {
				694	defm V_MAC_LEGACY_F32 : VOP2InstSI <vop2<0x6>, "v_mac_legacy_f32",
				695	VOP_F32_F32_F32
				696	>;
				697	} // End isCommutable = 1
				698
Marek Olsak	191507e	2015-02-03 17:38:12 +0000	[diff] [blame]	699	defm V_MIN_LEGACY_F32 : VOP2InstSI <vop2<0xd>, "v_min_legacy_f32",
Matt Arsenault	da59f3d	2014-11-13 23:03:09 +0000	[diff] [blame]	700	VOP_F32_F32_F32, AMDGPUfmin_legacy
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	701	>;
Marek Olsak	191507e	2015-02-03 17:38:12 +0000	[diff] [blame]	702	defm V_MAX_LEGACY_F32 : VOP2InstSI <vop2<0xe>, "v_max_legacy_f32",
Matt Arsenault	da59f3d	2014-11-13 23:03:09 +0000	[diff] [blame]	703	VOP_F32_F32_F32, AMDGPUfmax_legacy
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	704	>;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	705
Matt Arsenault	1e3a4eb	2014-12-12 02:30:37 +0000	[diff] [blame]	706	let isCommutable = 1 in {
Marek Olsak	24ae2cd	2015-02-03 21:53:08 +0000	[diff] [blame]	707	defm V_LSHR_B32 : VOP2InstSI <vop2<0x15>, "v_lshr_b32", VOP_I32_I32_I32>;
				708	defm V_ASHR_I32 : VOP2InstSI <vop2<0x17>, "v_ashr_i32", VOP_I32_I32_I32>;
				709	defm V_LSHL_B32 : VOP2InstSI <vop2<0x19>, "v_lshl_b32", VOP_I32_I32_I32>;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	710	} // End isCommutable = 1
Marek Olsak	f0b130a	2015-01-15 18:43:06 +0000	[diff] [blame]	711	} // End let SubtargetPredicate = SICI
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	712
Marek Olsak	63a7b08	2015-03-24 13:40:21 +0000	[diff] [blame]	713	defm V_BFM_B32 : VOP2_VI3_Inst <vop23<0x1e, 0x293>, "v_bfm_b32",
				714	VOP_I32_I32_I32
Marek Olsak	f0b130a	2015-01-15 18:43:06 +0000	[diff] [blame]	715	>;
				716	defm V_BCNT_U32_B32 : VOP2_VI3_Inst <vop23<0x22, 0x28b>, "v_bcnt_u32_b32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	717	VOP_I32_I32_I32
				718	>;
Marek Olsak	f0b130a	2015-01-15 18:43:06 +0000	[diff] [blame]	719	defm V_MBCNT_LO_U32_B32 : VOP2_VI3_Inst <vop23<0x23, 0x28c>, "v_mbcnt_lo_u32_b32",
Tom Stellard	43f52df	2015-12-15 17:02:52 +0000	[diff] [blame]	720	VOP_I32_I32_I32, int_amdgcn_mbcnt_lo
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	721	>;
Marek Olsak	f0b130a	2015-01-15 18:43:06 +0000	[diff] [blame]	722	defm V_MBCNT_HI_U32_B32 : VOP2_VI3_Inst <vop23<0x24, 0x28d>, "v_mbcnt_hi_u32_b32",
Tom Stellard	43f52df	2015-12-15 17:02:52 +0000	[diff] [blame]	723	VOP_I32_I32_I32, int_amdgcn_mbcnt_hi
Marek Olsak	f0b130a	2015-01-15 18:43:06 +0000	[diff] [blame]	724	>;
				725	defm V_LDEXP_F32 : VOP2_VI3_Inst <vop23<0x2b, 0x288>, "v_ldexp_f32",
Matt Arsenault	2e7cc48	2014-08-15 17:30:25 +0000	[diff] [blame]	726	VOP_F32_F32_I32, AMDGPUldexp
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	727	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	728
Marek Olsak	11057ee	2015-02-03 17:38:01 +0000	[diff] [blame]	729	defm V_CVT_PKACCUM_U8_F32 : VOP2_VI3_Inst <vop23<0x2c, 0x1f0>, "v_cvt_pkaccum_u8_f32",
				730	VOP_I32_F32_I32>; // TODO: set "Uses = dst"
				731
				732	defm V_CVT_PKNORM_I16_F32 : VOP2_VI3_Inst <vop23<0x2d, 0x294>, "v_cvt_pknorm_i16_f32",
				733	VOP_I32_F32_F32
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	734	>;
Marek Olsak	11057ee	2015-02-03 17:38:01 +0000	[diff] [blame]	735	defm V_CVT_PKNORM_U16_F32 : VOP2_VI3_Inst <vop23<0x2e, 0x295>, "v_cvt_pknorm_u16_f32",
				736	VOP_I32_F32_F32
				737	>;
				738	defm V_CVT_PKRTZ_F16_F32 : VOP2_VI3_Inst <vop23<0x2f, 0x296>, "v_cvt_pkrtz_f16_f32",
				739	VOP_I32_F32_F32, int_SI_packf16
				740	>;
				741	defm V_CVT_PK_U16_U32 : VOP2_VI3_Inst <vop23<0x30, 0x297>, "v_cvt_pk_u16_u32",
				742	VOP_I32_I32_I32
				743	>;
				744	defm V_CVT_PK_I16_I32 : VOP2_VI3_Inst <vop23<0x31, 0x298>, "v_cvt_pk_i16_i32",
				745	VOP_I32_I32_I32
				746	>;
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	747
				748	//===----------------------------------------------------------------------===//
				749	// VOP3 Instructions
				750	//===----------------------------------------------------------------------===//
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	751
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	752	let isCommutable = 1 in {
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	753	defm V_MAD_LEGACY_F32 : VOP3Inst <vop3<0x140, 0x1c0>, "v_mad_legacy_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	754	VOP_F32_F32_F32_F32
Matt Arsenault	f37abc7	2014-05-22 17:45:20 +0000	[diff] [blame]	755	>;
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	756
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	757	defm V_MAD_F32 : VOP3Inst <vop3<0x141, 0x1c1>, "v_mad_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	758	VOP_F32_F32_F32_F32, fmad
Tom Stellard	5263948	2013-07-23 01:48:49 +0000	[diff] [blame]	759	>;
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	760
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	761	defm V_MAD_I32_I24 : VOP3Inst <vop3<0x142, 0x1c2>, "v_mad_i32_i24",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	762	VOP_I32_I32_I32_I32, AMDGPUmad_i24
				763	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	764	defm V_MAD_U32_U24 : VOP3Inst <vop3<0x143, 0x1c3>, "v_mad_u32_u24",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	765	VOP_I32_I32_I32_I32, AMDGPUmad_u24
Tom Stellard	5263948	2013-07-23 01:48:49 +0000	[diff] [blame]	766	>;
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	767	} // End isCommutable = 1
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	768
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	769	defm V_CUBEID_F32 : VOP3Inst <vop3<0x144, 0x1c4>, "v_cubeid_f32",
Matt Arsenault	051d6f9	2016-01-26 04:29:56 +0000	[diff] [blame]	770	VOP_F32_F32_F32_F32, int_amdgcn_cubeid
Niels Ole Salscheider	6509ac6	2013-08-10 10:38:47 +0000	[diff] [blame]	771	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	772	defm V_CUBESC_F32 : VOP3Inst <vop3<0x145, 0x1c5>, "v_cubesc_f32",
Matt Arsenault	051d6f9	2016-01-26 04:29:56 +0000	[diff] [blame]	773	VOP_F32_F32_F32_F32, int_amdgcn_cubesc
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	774	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	775	defm V_CUBETC_F32 : VOP3Inst <vop3<0x146, 0x1c6>, "v_cubetc_f32",
Matt Arsenault	051d6f9	2016-01-26 04:29:56 +0000	[diff] [blame]	776	VOP_F32_F32_F32_F32, int_amdgcn_cubetc
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	777	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	778	defm V_CUBEMA_F32 : VOP3Inst <vop3<0x147, 0x1c7>, "v_cubema_f32",
Matt Arsenault	051d6f9	2016-01-26 04:29:56 +0000	[diff] [blame]	779	VOP_F32_F32_F32_F32, int_amdgcn_cubema
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	780	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	781
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	782	defm V_BFE_U32 : VOP3Inst <vop3<0x148, 0x1c8>, "v_bfe_u32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	783	VOP_I32_I32_I32_I32, AMDGPUbfe_u32
				784	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	785	defm V_BFE_I32 : VOP3Inst <vop3<0x149, 0x1c9>, "v_bfe_i32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	786	VOP_I32_I32_I32_I32, AMDGPUbfe_i32
				787	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	788
				789	defm V_BFI_B32 : VOP3Inst <vop3<0x14a, 0x1ca>, "v_bfi_b32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	790	VOP_I32_I32_I32_I32, AMDGPUbfi
				791	>;
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	792
				793	let isCommutable = 1 in {
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	794	defm V_FMA_F32 : VOP3Inst <vop3<0x14b, 0x1cb>, "v_fma_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	795	VOP_F32_F32_F32_F32, fma
				796	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	797	defm V_FMA_F64 : VOP3Inst <vop3<0x14c, 0x1cc>, "v_fma_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	798	VOP_F64_F64_F64_F64, fma
Niels Ole Salscheider	6509ac6	2013-08-10 10:38:47 +0000	[diff] [blame]	799	>;
Wei Ding	5b2636a	2016-07-12 18:02:14 +0000	[diff] [blame]	800
				801	defm V_LERP_U8 : VOP3Inst <vop3<0x14d, 0x1cd>, "v_lerp_u8",
				802	VOP_I32_I32_I32_I32, int_amdgcn_lerp
				803	>;
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	804	} // End isCommutable = 1
				805
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	806	//def V_LERP_U8 : VOP3_U8 <0x0000014d, "v_lerp_u8", []>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	807	defm V_ALIGNBIT_B32 : VOP3Inst <vop3<0x14e, 0x1ce>, "v_alignbit_b32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	808	VOP_I32_I32_I32_I32
				809	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	810	defm V_ALIGNBYTE_B32 : VOP3Inst <vop3<0x14f, 0x1cf>, "v_alignbyte_b32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	811	VOP_I32_I32_I32_I32
				812	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	813
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	814	defm V_MIN3_F32 : VOP3Inst <vop3<0x151, 0x1d0>, "v_min3_f32",
Matt Arsenault	cc3c2b3	2014-11-14 20:08:52 +0000	[diff] [blame]	815	VOP_F32_F32_F32_F32, AMDGPUfmin3>;
				816
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	817	defm V_MIN3_I32 : VOP3Inst <vop3<0x152, 0x1d1>, "v_min3_i32",
Matt Arsenault	cc3c2b3	2014-11-14 20:08:52 +0000	[diff] [blame]	818	VOP_I32_I32_I32_I32, AMDGPUsmin3
				819	>;
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	820	defm V_MIN3_U32 : VOP3Inst <vop3<0x153, 0x1d2>, "v_min3_u32",
Matt Arsenault	cc3c2b3	2014-11-14 20:08:52 +0000	[diff] [blame]	821	VOP_I32_I32_I32_I32, AMDGPUumin3
				822	>;
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	823	defm V_MAX3_F32 : VOP3Inst <vop3<0x154, 0x1d3>, "v_max3_f32",
Matt Arsenault	cc3c2b3	2014-11-14 20:08:52 +0000	[diff] [blame]	824	VOP_F32_F32_F32_F32, AMDGPUfmax3
				825	>;
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	826	defm V_MAX3_I32 : VOP3Inst <vop3<0x155, 0x1d4>, "v_max3_i32",
Matt Arsenault	cc3c2b3	2014-11-14 20:08:52 +0000	[diff] [blame]	827	VOP_I32_I32_I32_I32, AMDGPUsmax3
				828	>;
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	829	defm V_MAX3_U32 : VOP3Inst <vop3<0x156, 0x1d5>, "v_max3_u32",
Matt Arsenault	cc3c2b3	2014-11-14 20:08:52 +0000	[diff] [blame]	830	VOP_I32_I32_I32_I32, AMDGPUumax3
				831	>;
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	832	defm V_MED3_F32 : VOP3Inst <vop3<0x157, 0x1d6>, "v_med3_f32",
Matt Arsenault	f639c32	2016-01-28 20:53:42 +0000	[diff] [blame]	833	VOP_F32_F32_F32_F32, AMDGPUfmed3
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	834	>;
				835	defm V_MED3_I32 : VOP3Inst <vop3<0x158, 0x1d7>, "v_med3_i32",
Matt Arsenault	f639c32	2016-01-28 20:53:42 +0000	[diff] [blame]	836	VOP_I32_I32_I32_I32, AMDGPUsmed3
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	837	>;
				838	defm V_MED3_U32 : VOP3Inst <vop3<0x159, 0x1d8>, "v_med3_u32",
Matt Arsenault	f639c32	2016-01-28 20:53:42 +0000	[diff] [blame]	839	VOP_I32_I32_I32_I32, AMDGPUumed3
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	840	>;
				841
Wei Ding	34e1753	2016-08-11 16:33:53 +0000	[diff] [blame]	842	defm V_SAD_U8 : VOP3Inst <vop3 <0x15a, 0x1d9>, "v_sad_u8",
				843	VOP_I32_I32_I32_I32, int_amdgcn_sad_u8>;
				844
				845	defm V_SAD_HI_U8 : VOP3Inst <vop3 <0x15b, 0x1da>, "v_sad_hi_u8",
				846	VOP_I32_I32_I32_I32, int_amdgcn_sad_hi_u8>;
				847
				848	defm V_SAD_U16 : VOP3Inst <vop3<0x15c, 0x1db>, "v_sad_u16",
				849	VOP_I32_I32_I32_I32, int_amdgcn_sad_u16>;
				850
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	851	defm V_SAD_U32 : VOP3Inst <vop3<0x15d, 0x1dc>, "v_sad_u32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	852	VOP_I32_I32_I32_I32
				853	>;
Wei Ding	70cda07	2016-08-11 20:34:48 +0000	[diff] [blame]	854
				855	defm V_CVT_PK_U8_F32 : VOP3Inst<vop3<0x15e, 0x1dd>, "v_cvt_pk_u8_f32",
				856	VOP_I32_F32_I32_I32, int_amdgcn_cvt_pk_u8_f32
				857	>;
				858
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	859	//def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "v_cvt_pk_u8_f32", []>;
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	860	defm V_DIV_FIXUP_F32 : VOP3Inst <
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	861	vop3<0x15f, 0x1de>, "v_div_fixup_f32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	862	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	863
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	864	let SchedRW = [WriteDoubleAdd] in {
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	865
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	866	defm V_DIV_FIXUP_F64 : VOP3Inst <
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	867	vop3<0x160, 0x1df>, "v_div_fixup_f64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	868	>;
Tom Stellard	1cfd7a5	2013-05-20 15:02:12 +0000	[diff] [blame]	869
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	870	} // End SchedRW = [WriteDouble]
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	871
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	872	let SchedRW = [WriteDoubleAdd] in {
Tom Stellard	7512c08	2013-07-12 18:14:56 +0000	[diff] [blame]	873	let isCommutable = 1 in {
				874
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	875	defm V_ADD_F64 : VOP3Inst <vop3<0x164, 0x280>, "v_add_f64",
Tom Stellard	a90b952	2016-02-11 03:28:15 +0000	[diff] [blame]	876	VOP_F64_F64_F64, fadd, 1
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	877	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	878	defm V_MUL_F64 : VOP3Inst <vop3<0x165, 0x281>, "v_mul_f64",
Tom Stellard	a90b952	2016-02-11 03:28:15 +0000	[diff] [blame]	879	VOP_F64_F64_F64, fmul, 1
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	880	>;
Matt Arsenault	7c93690	2014-10-21 23:01:01 +0000	[diff] [blame]	881
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	882	defm V_MIN_F64 : VOP3Inst <vop3<0x166, 0x282>, "v_min_f64",
Tom Stellard	a90b952	2016-02-11 03:28:15 +0000	[diff] [blame]	883	VOP_F64_F64_F64, fminnum, 1
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	884	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	885	defm V_MAX_F64 : VOP3Inst <vop3<0x167, 0x283>, "v_max_f64",
Tom Stellard	a90b952	2016-02-11 03:28:15 +0000	[diff] [blame]	886	VOP_F64_F64_F64, fmaxnum, 1
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	887	>;
Tom Stellard	7512c08	2013-07-12 18:14:56 +0000	[diff] [blame]	888
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	889	} // End isCommutable = 1
Tom Stellard	7512c08	2013-07-12 18:14:56 +0000	[diff] [blame]	890
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	891	defm V_LDEXP_F64 : VOP3Inst <vop3<0x168, 0x284>, "v_ldexp_f64",
Tom Stellard	a90b952	2016-02-11 03:28:15 +0000	[diff] [blame]	892	VOP_F64_F64_I32, AMDGPUldexp, 1
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	893	>;
Christian Konig	70a5032	2013-03-27 09:12:51 +0000	[diff] [blame]	894
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	895	} // End let SchedRW = [WriteDoubleAdd]
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	896
				897	let isCommutable = 1, SchedRW = [WriteQuarterRate32] in {
Christian Konig	70a5032	2013-03-27 09:12:51 +0000	[diff] [blame]	898
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	899	defm V_MUL_LO_U32 : VOP3Inst <vop3<0x169, 0x285>, "v_mul_lo_u32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	900	VOP_I32_I32_I32
				901	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	902	defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a, 0x286>, "v_mul_hi_u32",
Matt Arsenault	8d90302	2016-01-22 18:42:49 +0000	[diff] [blame]	903	VOP_I32_I32_I32, mulhu
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	904	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	905
Tom Stellard	e1818af	2016-02-18 03:42:32 +0000	[diff] [blame]	906	let DisableVIDecoder=1 in { // removed from VI as identical to V_MUL_LO_U32
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	907	defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b, 0x285>, "v_mul_lo_i32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	908	VOP_I32_I32_I32
				909	>;
Tom Stellard	e1818af	2016-02-18 03:42:32 +0000	[diff] [blame]	910	}
				911
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	912	defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32",
Matt Arsenault	8d90302	2016-01-22 18:42:49 +0000	[diff] [blame]	913	VOP_I32_I32_I32, mulhs
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	914	>;
Christian Konig	70a5032	2013-03-27 09:12:51 +0000	[diff] [blame]	915
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	916	} // End isCommutable = 1, SchedRW = [WriteQuarterRate32]
Christian Konig	70a5032	2013-03-27 09:12:51 +0000	[diff] [blame]	917
Matt Arsenault	6e26b8d	2015-02-14 04:03:18 +0000	[diff] [blame]	918	let SchedRW = [WriteFloatFMA, WriteSALU] in {
Matt Arsenault	e98a074	2015-09-26 02:25:48 +0000	[diff] [blame]	919	defm V_DIV_SCALE_F32 : VOP3bInst <vop3<0x16d, 0x1e0>, "v_div_scale_f32",
Tom Stellard	e993451	2016-02-11 18:25:26 +0000	[diff] [blame]	920	VOP3b_F32_I1_F32_F32_F32, [], 1
Matt Arsenault	e98a074	2015-09-26 02:25:48 +0000	[diff] [blame]	921	>;
Matt Arsenault	6e26b8d	2015-02-14 04:03:18 +0000	[diff] [blame]	922	}
Matt Arsenault	f2b0aeb	2014-06-23 18:28:28 +0000	[diff] [blame]	923
Matt Arsenault	6e26b8d	2015-02-14 04:03:18 +0000	[diff] [blame]	924	let SchedRW = [WriteDouble, WriteSALU] in {
Matt Arsenault	f2b0aeb	2014-06-23 18:28:28 +0000	[diff] [blame]	925	// Double precision division pre-scale.
Matt Arsenault	e98a074	2015-09-26 02:25:48 +0000	[diff] [blame]	926	defm V_DIV_SCALE_F64 : VOP3bInst <vop3<0x16e, 0x1e1>, "v_div_scale_f64",
Tom Stellard	e993451	2016-02-11 18:25:26 +0000	[diff] [blame]	927	VOP3b_F64_I1_F64_F64_F64, [], 1
Matt Arsenault	e98a074	2015-09-26 02:25:48 +0000	[diff] [blame]	928	>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	929	} // End SchedRW = [WriteDouble]
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	930
Matt Arsenault	80f766a	2015-09-10 01:23:28 +0000	[diff] [blame]	931	let isCommutable = 1, Uses = [VCC, EXEC] in {
Matt Arsenault	1bc9d95	2015-02-14 04:22:00 +0000	[diff] [blame]	932
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	933	let SchedRW = [WriteFloatFMA] in {
Matt Arsenault	1bc9d95	2015-02-14 04:22:00 +0000	[diff] [blame]	934	// v_div_fmas_f32:
				935	// result = src0 * src1 + src2
				936	// if (vcc)
				937	// result *= 2^32
				938	//
				939	defm V_DIV_FMAS_F32 : VOP3_VCC_Inst <vop3<0x16f, 0x1e2>, "v_div_fmas_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	940	VOP_F32_F32_F32_F32, AMDGPUdiv_fmas
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	941	>;
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	942	}
Matt Arsenault	1bc9d95	2015-02-14 04:22:00 +0000	[diff] [blame]	943
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	944	let SchedRW = [WriteDouble] in {
Matt Arsenault	1bc9d95	2015-02-14 04:22:00 +0000	[diff] [blame]	945	// v_div_fmas_f64:
				946	// result = src0 * src1 + src2
				947	// if (vcc)
				948	// result *= 2^64
				949	//
				950	defm V_DIV_FMAS_F64 : VOP3_VCC_Inst <vop3<0x170, 0x1e3>, "v_div_fmas_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	951	VOP_F64_F64_F64_F64, AMDGPUdiv_fmas
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	952	>;
Matt Arsenault	1bc9d95	2015-02-14 04:22:00 +0000	[diff] [blame]	953
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	954	} // End SchedRW = [WriteDouble]
Matt Arsenault	80f766a	2015-09-10 01:23:28 +0000	[diff] [blame]	955	} // End isCommutable = 1, Uses = [VCC, EXEC]
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	956
Wei Ding	34e1753	2016-08-11 16:33:53 +0000	[diff] [blame]	957	defm V_MSAD_U8 : VOP3Inst <vop3<0x171, 0x1e4>, "v_msad_u8",
				958	VOP_I32_I32_I32_I32, int_amdgcn_msad_u8>;
				959
				960	defm V_MQSAD_PK_U16_U8 : VOP3Inst <vop3<0x173, 0x1e6>, "v_mqsad_pk_u16_u8",
Wei Ding	52bb661	2016-08-18 19:51:14 +0000	[diff] [blame]	961	VOP_I64_I64_I32_I64, int_amdgcn_mqsad_pk_u16_u8>;
Wei Ding	34e1753	2016-08-11 16:33:53 +0000	[diff] [blame]	962
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	963	//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "v_mqsad_u8", []>;
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	964
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	965	let SchedRW = [WriteDouble] in {
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	966	defm V_TRIG_PREOP_F64 : VOP3Inst <
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	967	vop3<0x174, 0x292>, "v_trig_preop_f64", VOP_F64_F64_I32, AMDGPUtrig_preop
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	968	>;
Matt Arsenault	e27a41b	2013-11-18 20:09:32 +0000	[diff] [blame]	969
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	970	} // End SchedRW = [WriteDouble]
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	971
Marek Olsak	eae20ab	2015-01-15 18:42:40 +0000	[diff] [blame]	972	// These instructions only exist on SI and CI
				973	let SubtargetPredicate = isSICI in {
				974
Marek Olsak	24ae2cd	2015-02-03 21:53:08 +0000	[diff] [blame]	975	defm V_LSHL_B64 : VOP3Inst <vop3<0x161>, "v_lshl_b64", VOP_I64_I64_I32>;
				976	defm V_LSHR_B64 : VOP3Inst <vop3<0x162>, "v_lshr_b64", VOP_I64_I64_I32>;
				977	defm V_ASHR_I64 : VOP3Inst <vop3<0x163>, "v_ashr_i64", VOP_I64_I64_I32>;
Marek Olsak	eae20ab	2015-01-15 18:42:40 +0000	[diff] [blame]	978
				979	defm V_MULLIT_F32 : VOP3Inst <vop3<0x150>, "v_mullit_f32",
				980	VOP_F32_F32_F32_F32>;
				981
				982	} // End SubtargetPredicate = isSICI
				983
Tom Stellard	e1818af	2016-02-18 03:42:32 +0000	[diff] [blame]	984	let SubtargetPredicate = isVI, DisableSIDecoder = 1 in {
Marek Olsak	707a6d0	2015-02-03 21:53:01 +0000	[diff] [blame]	985
				986	defm V_LSHLREV_B64 : VOP3Inst <vop3<0, 0x28f>, "v_lshlrev_b64",
				987	VOP_I64_I32_I64
				988	>;
				989	defm V_LSHRREV_B64 : VOP3Inst <vop3<0, 0x290>, "v_lshrrev_b64",
				990	VOP_I64_I32_I64
				991	>;
				992	defm V_ASHRREV_I64 : VOP3Inst <vop3<0, 0x291>, "v_ashrrev_i64",
				993	VOP_I64_I32_I64
				994	>;
				995
				996	} // End SubtargetPredicate = isVI
				997
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	998	//===----------------------------------------------------------------------===//
				999	// Pseudo Instructions
				1000	//===----------------------------------------------------------------------===//
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1001
				1002	let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in {
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1003
Marek Olsak	7d77728	2015-03-24 13:40:15 +0000	[diff] [blame]	1004	// For use in patterns
Tom Stellard	cc4c871	2016-02-16 18:14:56 +0000	[diff] [blame]	1005	def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$vdst),
Sam Kolton	1eeb11b	2016-09-09 14:44:04 +0000	[diff] [blame]	1006	(ins VSrc_b64:$src0, VSrc_b64:$src1, SSrc_b64:$src2), "", []> {
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1007	let isPseudo = 1;
				1008	let isCodeGenOnly = 1;
Matt Arsenault	22e4179	2016-08-27 01:00:37 +0000	[diff] [blame]	1009	let usesCustomInserter = 1;
Tom Stellard	60024a0	2014-09-24 01:33:24 +0000	[diff] [blame]	1010	}
				1011
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1012	// 64-bit vector move instruction. This is mainly used by the SIFoldOperands
				1013	// pass to enable folding of inline immediates.
Sam Kolton	1eeb11b	2016-09-09 14:44:04 +0000	[diff] [blame]	1014	def V_MOV_B64_PSEUDO : PseudoInstSI <(outs VReg_64:$vdst), (ins VSrc_b64:$src0)> {
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1015	let VALU = 1;
				1016	}
				1017	} // End let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC]
				1018
Changpeng Fang	01f6062	2016-03-15 17:28:44 +0000	[diff] [blame]	1019	let usesCustomInserter = 1, SALU = 1 in {
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1020	def GET_GROUPSTATICSIZE : PseudoInstSI <(outs SReg_32:$sdst), (ins),
Changpeng Fang	01f6062	2016-03-15 17:28:44 +0000	[diff] [blame]	1021	[(set SReg_32:$sdst, (int_amdgcn_groupstaticsize))]>;
				1022	} // End let usesCustomInserter = 1, SALU = 1
				1023
Matt Arsenault	8fb3738	2013-10-11 21:03:36 +0000	[diff] [blame]	1024	// SI pseudo instructions. These are used by the CFG structurizer pass
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1025	// and should be lowered to ISA instructions prior to codegen.
				1026
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1027	// Dummy terminator instruction to use after control flow instructions
				1028	// replaced with exec mask operations.
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1029	def SI_MASK_BRANCH : PseudoInstSI <
Matt Arsenault	f98a596	2016-08-27 00:42:21 +0000	[diff] [blame]	1030	(outs), (ins brtarget:$target)> {
Matt Arsenault	57431c9	2016-08-10 19:11:42 +0000	[diff] [blame]	1031	let isBranch = 0;
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1032	let isTerminator = 1;
Matt Arsenault	57431c9	2016-08-10 19:11:42 +0000	[diff] [blame]	1033	let isBarrier = 0;
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1034	let SALU = 1;
Matt Arsenault	78fc9da	2016-08-22 19:33:16 +0000	[diff] [blame]	1035	let Uses = [EXEC];
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1036	}
				1037
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1038	let isTerminator = 1 in {
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1039
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1040	def SI_IF: CFPseudoInstSI <
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1041	(outs SReg_64:$dst), (ins SReg_64:$vcc, brtarget:$target),
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1042	[(set i64:$dst, (int_amdgcn_if i1:$vcc, bb:$target))], 1, 1> {
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1043	let Constraints = "";
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1044	let Size = 8;
Matt Arsenault	6408c91	2016-09-16 22:11:18 +0000	[diff] [blame]	1045	let mayStore = 1;
				1046	let mayLoad = 1;
				1047	let hasSideEffects = 1;
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1048	}
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1049
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1050	def SI_ELSE : CFPseudoInstSI <
				1051	(outs SReg_64:$dst), (ins SReg_64:$src, brtarget:$target, i1imm:$execfix), [], 1, 1> {
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1052	let Constraints = "$src = $dst";
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1053	let Size = 12;
Matt Arsenault	6408c91	2016-09-16 22:11:18 +0000	[diff] [blame]	1054	let mayStore = 1;
				1055	let mayLoad = 1;
				1056	let hasSideEffects = 1;
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1057	}
				1058
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1059	def SI_LOOP : CFPseudoInstSI <
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1060	(outs), (ins SReg_64:$saved, brtarget:$target),
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1061	[(int_amdgcn_loop i64:$saved, bb:$target)], 1, 1> {
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1062	let Size = 8;
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1063	let isBranch = 1;
Matt Arsenault	6408c91	2016-09-16 22:11:18 +0000	[diff] [blame]	1064	let hasSideEffects = 1;
				1065	let mayLoad = 1;
				1066	let mayStore = 1;
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1067	}
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1068
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1069	} // End isBranch = 1, isTerminator = 1
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1070
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1071	def SI_END_CF : CFPseudoInstSI <
				1072	(outs), (ins SReg_64:$saved),
				1073	[(int_amdgcn_end_cf i64:$saved)], 1, 1> {
				1074	let Size = 4;
Matt Arsenault	6408c91	2016-09-16 22:11:18 +0000	[diff] [blame]	1075	let isAsCheapAsAMove = 1;
				1076	let isReMaterializable = 1;
				1077	let mayLoad = 1;
				1078	let mayStore = 1;
				1079	let hasSideEffects = 1;
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1080	}
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1081
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1082	def SI_BREAK : CFPseudoInstSI <
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1083	(outs SReg_64:$dst), (ins SReg_64:$src),
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1084	[(set i64:$dst, (int_amdgcn_break i64:$src))], 1> {
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1085	let Size = 4;
Matt Arsenault	6408c91	2016-09-16 22:11:18 +0000	[diff] [blame]	1086	let isAsCheapAsAMove = 1;
				1087	let isReMaterializable = 1;
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1088	}
Matt Arsenault	48d70cb	2016-07-09 17:18:39 +0000	[diff] [blame]	1089
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1090	def SI_IF_BREAK : CFPseudoInstSI <
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1091	(outs SReg_64:$dst), (ins SReg_64:$vcc, SReg_64:$src),
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1092	[(set i64:$dst, (int_amdgcn_if_break i1:$vcc, i64:$src))]> {
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1093	let Size = 4;
Matt Arsenault	6408c91	2016-09-16 22:11:18 +0000	[diff] [blame]	1094	let isAsCheapAsAMove = 1;
				1095	let isReMaterializable = 1;
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1096	}
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1097
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1098	def SI_ELSE_BREAK : CFPseudoInstSI <
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1099	(outs SReg_64:$dst), (ins SReg_64:$src0, SReg_64:$src1),
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1100	[(set i64:$dst, (int_amdgcn_else_break i64:$src0, i64:$src1))]> {
				1101	let Size = 4;
Matt Arsenault	6408c91	2016-09-16 22:11:18 +0000	[diff] [blame]	1102	let isAsCheapAsAMove = 1;
				1103	let isReMaterializable = 1;
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1104	}
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1105
Tom Stellard	aa79834	2015-05-01 03:44:09 +0000	[diff] [blame]	1106	let Uses = [EXEC], Defs = [EXEC,VCC] in {
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1107	def SI_KILL : PseudoInstSI <
Sam Kolton	1eeb11b	2016-09-09 14:44:04 +0000	[diff] [blame]	1108	(outs), (ins VSrc_b32:$src),
Matt Arsenault	03006fd	2016-07-19 16:27:56 +0000	[diff] [blame]	1109	[(AMDGPUkill i32:$src)]> {
Matt Arsenault	786724a	2016-07-12 21:41:32 +0000	[diff] [blame]	1110	let isConvergent = 1;
				1111	let usesCustomInserter = 1;
				1112	}
				1113
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1114	def SI_KILL_TERMINATOR : SPseudoInstSI <
Sam Kolton	1eeb11b	2016-09-09 14:44:04 +0000	[diff] [blame]	1115	(outs), (ins VSrc_b32:$src)> {
Matt Arsenault	786724a	2016-07-12 21:41:32 +0000	[diff] [blame]	1116	let isTerminator = 1;
				1117	}
				1118
Tom Stellard	aa79834	2015-05-01 03:44:09 +0000	[diff] [blame]	1119	} // End Uses = [EXEC], Defs = [EXEC,VCC]
Tom Stellard	be8ebee	2013-01-18 21:15:50 +0000	[diff] [blame]	1120
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1121
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1122	def SI_PS_LIVE : PseudoInstSI <
				1123	(outs SReg_64:$dst), (ins),
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1124	[(set i1:$dst, (int_amdgcn_ps_live))]> {
				1125	let SALU = 1;
				1126	}
Nicolai Haehnle	b0c9748	2016-04-22 04:04:08 +0000	[diff] [blame]	1127
Matt Arsenault	4ac341c	2016-04-14 21:58:15 +0000	[diff] [blame]	1128	// Used as an isel pseudo to directly emit initialization with an
				1129	// s_mov_b32 rather than a copy of another initialized
				1130	// register. MachineCSE skips copies, and we don't want to have to
				1131	// fold operands before it runs.
Sam Kolton	1eeb11b	2016-09-09 14:44:04 +0000	[diff] [blame]	1132	def SI_INIT_M0 : SPseudoInstSI <(outs), (ins SSrc_b32:$src)> {
Matt Arsenault	4ac341c	2016-04-14 21:58:15 +0000	[diff] [blame]	1133	let Defs = [M0];
				1134	let usesCustomInserter = 1;
Matt Arsenault	4ac341c	2016-04-14 21:58:15 +0000	[diff] [blame]	1135	let isAsCheapAsAMove = 1;
Matt Arsenault	4ac341c	2016-04-14 21:58:15 +0000	[diff] [blame]	1136	let isReMaterializable = 1;
				1137	}
				1138
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1139	def SI_RETURN : SPseudoInstSI <
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1140	(outs), (ins variable_ops), [(AMDGPUreturn)]> {
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1141	let isTerminator = 1;
				1142	let isBarrier = 1;
				1143	let isReturn = 1;
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1144	let hasSideEffects = 1;
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1145	let hasNoSchedulingInfo = 1;
Nicolai Haehnle	a246dcc	2016-09-03 12:26:32 +0000	[diff] [blame]	1146	let DisableWQM = 1;
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1147	}
				1148
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1149	let Defs = [M0, EXEC],
Matt Arsenault	3cb4dde	2016-06-22 23:40:57 +0000	[diff] [blame]	1150	UseNamedOperandTable = 1 in {
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1151
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1152	class SI_INDIRECT_SRC<RegisterClass rc> : VPseudoInstSI <
Matt Arsenault	cb540bc	2016-07-19 00:35:03 +0000	[diff] [blame]	1153	(outs VGPR_32:$vdst),
				1154	(ins rc:$src, VS_32:$idx, i32imm:$offset)> {
				1155	let usesCustomInserter = 1;
				1156	}
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1157
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1158	class SI_INDIRECT_DST<RegisterClass rc> : VPseudoInstSI <
Matt Arsenault	cb540bc	2016-07-19 00:35:03 +0000	[diff] [blame]	1159	(outs rc:$vdst),
				1160	(ins rc:$src, VS_32:$idx, i32imm:$offset, VGPR_32:$val)> {
Matt Arsenault	3cb4dde	2016-06-22 23:40:57 +0000	[diff] [blame]	1161	let Constraints = "$src = $vdst";
Matt Arsenault	cb540bc	2016-07-19 00:35:03 +0000	[diff] [blame]	1162	let usesCustomInserter = 1;
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1163	}
				1164
Matt Arsenault	2841927	2015-10-07 00:42:51 +0000	[diff] [blame]	1165	// TODO: We can support indirect SGPR access.
				1166	def SI_INDIRECT_SRC_V1 : SI_INDIRECT_SRC<VGPR_32>;
				1167	def SI_INDIRECT_SRC_V2 : SI_INDIRECT_SRC<VReg_64>;
				1168	def SI_INDIRECT_SRC_V4 : SI_INDIRECT_SRC<VReg_128>;
				1169	def SI_INDIRECT_SRC_V8 : SI_INDIRECT_SRC<VReg_256>;
				1170	def SI_INDIRECT_SRC_V16 : SI_INDIRECT_SRC<VReg_512>;
				1171
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	1172	def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VGPR_32>;
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1173	def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
				1174	def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
				1175	def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
				1176	def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
				1177
Matt Arsenault	cb540bc	2016-07-19 00:35:03 +0000	[diff] [blame]	1178	} // End Uses = [EXEC], Defs = [M0, EXEC]
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1179
Tom Stellard	eba6107	2014-05-02 15:41:42 +0000	[diff] [blame]	1180	multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
Matt Arsenault	3354f42	2016-09-10 01:20:33 +0000	[diff] [blame]	1181	let UseNamedOperandTable = 1, SGPRSpill = 1, Uses = [EXEC] in {
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1182	def _SAVE : PseudoInstSI <
Tom Stellard	42fb60e	2015-01-14 15:42:31 +0000	[diff] [blame]	1183	(outs),
Matt Arsenault	3354f42	2016-09-10 01:20:33 +0000	[diff] [blame]	1184	(ins sgpr_class:$data, i32imm:$addr)> {
Matt Arsenault	9a32cd3	2015-08-29 06:48:57 +0000	[diff] [blame]	1185	let mayStore = 1;
				1186	let mayLoad = 0;
				1187	}
Tom Stellard	eba6107	2014-05-02 15:41:42 +0000	[diff] [blame]	1188
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1189	def _RESTORE : PseudoInstSI <
Matt Arsenault	3354f42	2016-09-10 01:20:33 +0000	[diff] [blame]	1190	(outs sgpr_class:$data),
				1191	(ins i32imm:$addr)> {
Matt Arsenault	9a32cd3	2015-08-29 06:48:57 +0000	[diff] [blame]	1192	let mayStore = 0;
				1193	let mayLoad = 1;
				1194	}
Tom Stellard	42fb60e	2015-01-14 15:42:31 +0000	[diff] [blame]	1195	} // End UseNamedOperandTable = 1
Tom Stellard	eba6107	2014-05-02 15:41:42 +0000	[diff] [blame]	1196	}
				1197
Matt Arsenault	2510a31	2016-09-03 06:57:55 +0000	[diff] [blame]	1198	// You cannot use M0 as the output of v_readlane_b32 instructions or
				1199	// use it in the sdata operand of SMEM instructions. We still need to
				1200	// be able to spill the physical register m0, so allow it for
				1201	// SI_SPILL_32_* instructions.
				1202	defm SI_SPILL_S32 : SI_SPILL_SGPR <SReg_32>;
Tom Stellard	eba6107	2014-05-02 15:41:42 +0000	[diff] [blame]	1203	defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
				1204	defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
				1205	defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;
				1206	defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
				1207
Tom Stellard	9646890	2014-09-24 01:33:17 +0000	[diff] [blame]	1208	multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> {
Matt Arsenault	7348a7e	2016-09-10 01:20:28 +0000	[diff] [blame]	1209	let UseNamedOperandTable = 1, VGPRSpill = 1,
				1210	SchedRW = [WriteVMEM] in {
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1211	def _SAVE : VPseudoInstSI <
Tom Stellard	42fb60e	2015-01-14 15:42:31 +0000	[diff] [blame]	1212	(outs),
Matt Arsenault	3354f42	2016-09-10 01:20:33 +0000	[diff] [blame]	1213	(ins vgpr_class:$vdata, i32imm:$vaddr, SReg_128:$scratch_rsrc,
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1214	SReg_32:$scratch_offset, i32imm:$offset)> {
Matt Arsenault	9a32cd3	2015-08-29 06:48:57 +0000	[diff] [blame]	1215	let mayStore = 1;
				1216	let mayLoad = 0;
Matt Arsenault	ac42ba8	2016-09-03 17:25:44 +0000	[diff] [blame]	1217	// (2 * 4) + (8 * num_subregs) bytes maximum
				1218	let Size = !add(!shl(!srl(vgpr_class.Size, 5), 3), 8);
Matt Arsenault	9a32cd3	2015-08-29 06:48:57 +0000	[diff] [blame]	1219	}
Tom Stellard	9646890	2014-09-24 01:33:17 +0000	[diff] [blame]	1220
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1221	def _RESTORE : VPseudoInstSI <
Matt Arsenault	3354f42	2016-09-10 01:20:33 +0000	[diff] [blame]	1222	(outs vgpr_class:$vdata),
				1223	(ins i32imm:$vaddr, SReg_128:$scratch_rsrc, SReg_32:$scratch_offset,
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1224	i32imm:$offset)> {
Matt Arsenault	9a32cd3	2015-08-29 06:48:57 +0000	[diff] [blame]	1225	let mayStore = 0;
				1226	let mayLoad = 1;
Matt Arsenault	ac42ba8	2016-09-03 17:25:44 +0000	[diff] [blame]	1227
				1228	// (2 * 4) + (8 * num_subregs) bytes maximum
				1229	let Size = !add(!shl(!srl(vgpr_class.Size, 5), 3), 8);
Matt Arsenault	9a32cd3	2015-08-29 06:48:57 +0000	[diff] [blame]	1230	}
Matt Arsenault	7348a7e	2016-09-10 01:20:28 +0000	[diff] [blame]	1231	} // End UseNamedOperandTable = 1, VGPRSpill = 1, SchedRW = [WriteVMEM]
Tom Stellard	9646890	2014-09-24 01:33:17 +0000	[diff] [blame]	1232	}
				1233
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	1234	defm SI_SPILL_V32 : SI_SPILL_VGPR <VGPR_32>;
Tom Stellard	9646890	2014-09-24 01:33:17 +0000	[diff] [blame]	1235	defm SI_SPILL_V64 : SI_SPILL_VGPR <VReg_64>;
				1236	defm SI_SPILL_V96 : SI_SPILL_VGPR <VReg_96>;
				1237	defm SI_SPILL_V128 : SI_SPILL_VGPR <VReg_128>;
				1238	defm SI_SPILL_V256 : SI_SPILL_VGPR <VReg_256>;
				1239	defm SI_SPILL_V512 : SI_SPILL_VGPR <VReg_512>;
				1240
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1241	def SI_PC_ADD_REL_OFFSET : SPseudoInstSI <
Tom Stellard	067c815	2014-07-21 14:01:14 +0000	[diff] [blame]	1242	(outs SReg_64:$dst),
Tom Stellard	bf3e6e5	2016-06-14 20:29:59 +0000	[diff] [blame]	1243	(ins si_ga:$ptr),
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1244	[(set SReg_64:$dst, (i64 (SIpc_add_rel_offset (tglobaladdr:$ptr))))]> {
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1245	let Defs = [SCC];
Matt Arsenault	d092a06	2015-10-02 18:58:37 +0000	[diff] [blame]	1246	}
Tom Stellard	067c815	2014-07-21 14:01:14 +0000	[diff] [blame]	1247
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1248	} // End SubtargetPredicate = isGCN
Tom Stellard	0e70de5	2014-05-16 20:56:45 +0000	[diff] [blame]	1249
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1250	let Predicates = [isGCN] in {
Tom Stellard	0e70de5	2014-05-16 20:56:45 +0000	[diff] [blame]	1251
Nicolai Haehnle	3b57200	2016-07-28 11:39:24 +0000	[diff] [blame]	1252	def : Pat<
				1253	(int_amdgcn_else i64:$src, bb:$target),
				1254	(SI_ELSE $src, $target, 0)
				1255	>;
				1256
Tom Stellard	be8ebee	2013-01-18 21:15:50 +0000	[diff] [blame]	1257	def : Pat <
				1258	(int_AMDGPU_kilp),
Michel Danzer	9e61c4b	2014-02-27 01:47:09 +0000	[diff] [blame]	1259	(SI_KILL 0xbf800000)
Tom Stellard	be8ebee	2013-01-18 21:15:50 +0000	[diff] [blame]	1260	>;
				1261
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1262	def : Pat <
				1263	(int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1264	f32:$src0, f32:$src1, f32:$src2, f32:$src3),
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1265	(EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1266	$src0, $src1, $src2, $src3)
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1267	>;
				1268
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	1269	//===----------------------------------------------------------------------===//
Wei Ding	07e0371	2016-07-28 16:42:13 +0000	[diff] [blame]	1270	// V_ICMPIntrinsic Pattern.
				1271	//===----------------------------------------------------------------------===//
				1272	class ICMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> : Pat <
				1273	(AMDGPUsetcc vt:$src0, vt:$src1, cond),
				1274	(inst $src0, $src1)
				1275	>;
				1276
				1277	def : ICMP_Pattern <COND_EQ, V_CMP_EQ_I32_e64, i32>;
				1278	def : ICMP_Pattern <COND_NE, V_CMP_NE_I32_e64, i32>;
				1279	def : ICMP_Pattern <COND_UGT, V_CMP_GT_U32_e64, i32>;
				1280	def : ICMP_Pattern <COND_UGE, V_CMP_GE_U32_e64, i32>;
				1281	def : ICMP_Pattern <COND_ULT, V_CMP_LT_U32_e64, i32>;
				1282	def : ICMP_Pattern <COND_ULE, V_CMP_LE_U32_e64, i32>;
				1283	def : ICMP_Pattern <COND_SGT, V_CMP_GT_I32_e64, i32>;
				1284	def : ICMP_Pattern <COND_SGE, V_CMP_GE_I32_e64, i32>;
				1285	def : ICMP_Pattern <COND_SLT, V_CMP_LT_I32_e64, i32>;
				1286	def : ICMP_Pattern <COND_SLE, V_CMP_LE_I32_e64, i32>;
				1287
				1288	def : ICMP_Pattern <COND_EQ, V_CMP_EQ_I64_e64, i64>;
				1289	def : ICMP_Pattern <COND_NE, V_CMP_NE_I64_e64, i64>;
				1290	def : ICMP_Pattern <COND_UGT, V_CMP_GT_U64_e64, i64>;
				1291	def : ICMP_Pattern <COND_UGE, V_CMP_GE_U64_e64, i64>;
				1292	def : ICMP_Pattern <COND_ULT, V_CMP_LT_U64_e64, i64>;
				1293	def : ICMP_Pattern <COND_ULE, V_CMP_LE_U64_e64, i64>;
				1294	def : ICMP_Pattern <COND_SGT, V_CMP_GT_I64_e64, i64>;
				1295	def : ICMP_Pattern <COND_SGE, V_CMP_GE_I64_e64, i64>;
				1296	def : ICMP_Pattern <COND_SLT, V_CMP_LT_I64_e64, i64>;
				1297	def : ICMP_Pattern <COND_SLE, V_CMP_LE_I64_e64, i64>;
				1298
				1299	class FCMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> : Pat <
				1300	(i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
				1301	(vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),
				1302	(inst $src0_modifiers, $src0, $src1_modifiers, $src1,
				1303	DSTCLAMP.NONE, DSTOMOD.NONE)
				1304	>;
				1305
				1306	def : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F32_e64, f32>;
				1307	def : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F32_e64, f32>;
				1308	def : FCMP_Pattern <COND_OGT, V_CMP_GT_F32_e64, f32>;
				1309	def : FCMP_Pattern <COND_OGE, V_CMP_GE_F32_e64, f32>;
				1310	def : FCMP_Pattern <COND_OLT, V_CMP_LT_F32_e64, f32>;
				1311	def : FCMP_Pattern <COND_OLE, V_CMP_LE_F32_e64, f32>;
				1312
				1313	def : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F64_e64, f64>;
				1314	def : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F64_e64, f64>;
				1315	def : FCMP_Pattern <COND_OGT, V_CMP_GT_F64_e64, f64>;
				1316	def : FCMP_Pattern <COND_OGE, V_CMP_GE_F64_e64, f64>;
				1317	def : FCMP_Pattern <COND_OLT, V_CMP_LT_F64_e64, f64>;
				1318	def : FCMP_Pattern <COND_OLE, V_CMP_LE_F64_e64, f64>;
				1319
				1320	def : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F32_e64, f32>;
				1321	def : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F32_e64, f32>;
				1322	def : FCMP_Pattern <COND_UGT, V_CMP_NLE_F32_e64, f32>;
				1323	def : FCMP_Pattern <COND_UGE, V_CMP_NLT_F32_e64, f32>;
				1324	def : FCMP_Pattern <COND_ULT, V_CMP_NGE_F32_e64, f32>;
				1325	def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F32_e64, f32>;
				1326
				1327	def : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F64_e64, f64>;
				1328	def : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F64_e64, f64>;
				1329	def : FCMP_Pattern <COND_UGT, V_CMP_NLE_F64_e64, f64>;
				1330	def : FCMP_Pattern <COND_UGE, V_CMP_NLT_F64_e64, f64>;
				1331	def : FCMP_Pattern <COND_ULT, V_CMP_NGE_F64_e64, f64>;
				1332	def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F64_e64, f64>;
Tom Stellard	a6f24c6	2015-12-15 20:55:55 +0000	[diff] [blame]	1333
Tom Stellard	ae4c9e7	2014-06-20 17:06:11 +0000	[diff] [blame]	1334	//===----------------------------------------------------------------------===//
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	1335	// VOP1 Patterns
				1336	//===----------------------------------------------------------------------===//
				1337
Matt Arsenault	22ca3f8	2014-07-15 23:50:10 +0000	[diff] [blame]	1338	let Predicates = [UnsafeFPMath] in {
Matt Arsenault	0bbcd8b	2015-02-14 04:30:08 +0000	[diff] [blame]	1339
				1340	//def : RcpPat<V_RCP_F64_e32, f64>;
				1341	//defm : RsqPat<V_RSQ_F64_e32, f64>;
				1342	//defm : RsqPat<V_RSQ_F32_e32, f32>;
				1343
				1344	def : RsqPat<V_RSQ_F32_e32, f32>;
				1345	def : RsqPat<V_RSQ_F64_e32, f64>;
Matt Arsenault	7401516	2016-05-28 00:19:52 +0000	[diff] [blame]	1346
				1347	// Convert (x - floor(x)) to fract(x)
				1348	def : Pat <
				1349	(f32 (fsub (f32 (VOP3Mods f32:$x, i32:$mods)),
				1350	(f32 (ffloor (f32 (VOP3Mods f32:$x, i32:$mods)))))),
				1351	(V_FRACT_F32_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)
				1352	>;
				1353
				1354	// Convert (x + (-floor(x))) to fract(x)
				1355	def : Pat <
				1356	(f64 (fadd (f64 (VOP3Mods f64:$x, i32:$mods)),
				1357	(f64 (fneg (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))))))),
				1358	(V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)
				1359	>;
				1360
				1361	} // End Predicates = [UnsafeFPMath]
Matt Arsenault	e9fa3b8	2014-07-15 20:18:31 +0000	[diff] [blame]	1362
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	1363	//===----------------------------------------------------------------------===//
Tom Stellard	58ac744	2014-04-29 23:12:48 +0000	[diff] [blame]	1364	// VOP2 Patterns
				1365	//===----------------------------------------------------------------------===//
				1366
Tom Stellard	ae4c9e7	2014-06-20 17:06:11 +0000	[diff] [blame]	1367	def : Pat <
				1368	(i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)),
Matt Arsenault	49dd428	2014-09-15 17:15:02 +0000	[diff] [blame]	1369	(V_BCNT_U32_B32_e64 $popcnt, $val)
Tom Stellard	ae4c9e7	2014-06-20 17:06:11 +0000	[diff] [blame]	1370	>;
				1371
Tom Stellard	5224df3	2015-03-10 16:16:44 +0000	[diff] [blame]	1372	def : Pat <
				1373	(i32 (select i1:$src0, i32:$src1, i32:$src2)),
				1374	(V_CNDMASK_B32_e64 $src2, $src1, $src0)
				1375	>;
				1376
Tom Stellard	db5a11f	2015-07-13 15:47:57 +0000	[diff] [blame]	1377	// Pattern for V_MAC_F32
				1378	def : Pat <
				1379	(fmad (VOP3NoMods0 f32:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
				1380	(VOP3NoMods f32:$src1, i32:$src1_modifiers),
				1381	(VOP3NoMods f32:$src2, i32:$src2_modifiers)),
				1382	(V_MAC_F32_e64 $src0_modifiers, $src0, $src1_modifiers, $src1,
				1383	$src2_modifiers, $src2, $clamp, $omod)
				1384	>;
				1385
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1386	/******** ============================================ ********/
				1387	/******** Extraction, Insertion, Building and Casting ********/
				1388	/******** ============================================ ********/
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1389
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1390	foreach Index = 0-2 in {
				1391	def Extract_Element_v2i32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1392	i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1393	>;
				1394	def Insert_Element_v2i32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1395	i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1396	>;
				1397
				1398	def Extract_Element_v2f32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1399	f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1400	>;
				1401	def Insert_Element_v2f32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1402	f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1403	>;
				1404	}
				1405
				1406	foreach Index = 0-3 in {
				1407	def Extract_Element_v4i32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1408	i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1409	>;
				1410	def Insert_Element_v4i32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1411	i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1412	>;
				1413
				1414	def Extract_Element_v4f32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1415	f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1416	>;
				1417	def Insert_Element_v4f32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1418	f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1419	>;
				1420	}
				1421
				1422	foreach Index = 0-7 in {
				1423	def Extract_Element_v8i32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1424	i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1425	>;
				1426	def Insert_Element_v8i32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1427	i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1428	>;
				1429
				1430	def Extract_Element_v8f32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1431	f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1432	>;
				1433	def Insert_Element_v8f32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1434	f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1435	>;
				1436	}
				1437
				1438	foreach Index = 0-15 in {
				1439	def Extract_Element_v16i32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1440	i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1441	>;
				1442	def Insert_Element_v16i32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1443	i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1444	>;
				1445
				1446	def Extract_Element_v16f32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1447	f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1448	>;
				1449	def Insert_Element_v16f32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1450	f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1451	>;
				1452	}
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1453
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1454	// FIXME: Why do only some of these type combinations for SReg and
				1455	// VReg?
				1456	// 32-bit bitcast
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	1457	def : BitConvert <i32, f32, VGPR_32>;
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	1458	def : BitConvert <f32, i32, VGPR_32>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1459	def : BitConvert <i32, f32, SReg_32>;
				1460	def : BitConvert <f32, i32, SReg_32>;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1461
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1462	// 64-bit bitcast
Tom Stellard	7512c08	2013-07-12 18:14:56 +0000	[diff] [blame]	1463	def : BitConvert <i64, f64, VReg_64>;
Tom Stellard	7512c08	2013-07-12 18:14:56 +0000	[diff] [blame]	1464	def : BitConvert <f64, i64, VReg_64>;
Tom Stellard	ed2f614	2013-07-18 21:43:42 +0000	[diff] [blame]	1465	def : BitConvert <v2i32, v2f32, VReg_64>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1466	def : BitConvert <v2f32, v2i32, VReg_64>;
Tom Stellard	7ea3d6d	2014-03-31 14:01:55 +0000	[diff] [blame]	1467	def : BitConvert <i64, v2i32, VReg_64>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1468	def : BitConvert <v2i32, i64, VReg_64>;
Matt Arsenault	064c206	2014-06-11 17:40:32 +0000	[diff] [blame]	1469	def : BitConvert <i64, v2f32, VReg_64>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1470	def : BitConvert <v2f32, i64, VReg_64>;
Tom Stellard	8f30721	2015-12-15 17:11:17 +0000	[diff] [blame]	1471	def : BitConvert <f64, v2f32, VReg_64>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1472	def : BitConvert <v2f32, f64, VReg_64>;
Matt Arsenault	2acc7a4	2014-06-11 19:31:13 +0000	[diff] [blame]	1473	def : BitConvert <f64, v2i32, VReg_64>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1474	def : BitConvert <v2i32, f64, VReg_64>;
Tom Stellard	8374720	2013-07-18 21:43:53 +0000	[diff] [blame]	1475	def : BitConvert <v4i32, v4f32, VReg_128>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1476	def : BitConvert <v4f32, v4i32, VReg_128>;
Tom Stellard	8374720	2013-07-18 21:43:53 +0000	[diff] [blame]	1477
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1478	// 128-bit bitcast
Matt Arsenault	61001bb	2015-11-25 19:58:34 +0000	[diff] [blame]	1479	def : BitConvert <v2i64, v4i32, SReg_128>;
				1480	def : BitConvert <v4i32, v2i64, SReg_128>;
Tom Stellard	8f30721	2015-12-15 17:11:17 +0000	[diff] [blame]	1481	def : BitConvert <v2f64, v4f32, VReg_128>;
Matt Arsenault	61001bb	2015-11-25 19:58:34 +0000	[diff] [blame]	1482	def : BitConvert <v2f64, v4i32, VReg_128>;
Tom Stellard	8f30721	2015-12-15 17:11:17 +0000	[diff] [blame]	1483	def : BitConvert <v4f32, v2f64, VReg_128>;
Matt Arsenault	61001bb	2015-11-25 19:58:34 +0000	[diff] [blame]	1484	def : BitConvert <v4i32, v2f64, VReg_128>;
Matt Arsenault	e57206d	2016-05-25 18:07:36 +0000	[diff] [blame]	1485	def : BitConvert <v2i64, v2f64, VReg_128>;
				1486	def : BitConvert <v2f64, v2i64, VReg_128>;
Matt Arsenault	61001bb	2015-11-25 19:58:34 +0000	[diff] [blame]	1487
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1488	// 256-bit bitcast
Tom Stellard	967bf58	2014-02-13 23:34:15 +0000	[diff] [blame]	1489	def : BitConvert <v8i32, v8f32, SReg_256>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1490	def : BitConvert <v8f32, v8i32, SReg_256>;
Matt Arsenault	f5958dd	2014-02-02 00:05:35 +0000	[diff] [blame]	1491	def : BitConvert <v8i32, v8f32, VReg_256>;
				1492	def : BitConvert <v8f32, v8i32, VReg_256>;
Tom Stellard	20ee94f	2013-08-14 22:22:09 +0000	[diff] [blame]	1493
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1494	// 512-bit bitcast
Matt Arsenault	f5958dd	2014-02-02 00:05:35 +0000	[diff] [blame]	1495	def : BitConvert <v16i32, v16f32, VReg_512>;
				1496	def : BitConvert <v16f32, v16i32, VReg_512>;
				1497
Christian Konig	8dbe6f6	2013-02-21 15:17:27 +0000	[diff] [blame]	1498	/******** =================== ********/
				1499	/******** Src & Dst modifiers ********/
				1500	/******** =================== ********/
				1501
				1502	def : Pat <
Matt Arsenault	1cffa4c	2014-11-13 19:49:04 +0000	[diff] [blame]	1503	(AMDGPUclamp (VOP3Mods0Clamp f32:$src0, i32:$src0_modifiers, i32:$omod),
				1504	(f32 FP_ZERO), (f32 FP_ONE)),
				1505	(V_ADD_F32_e64 $src0_modifiers, $src0, 0, 0, 1, $omod)
Christian Konig	8dbe6f6	2013-02-21 15:17:27 +0000	[diff] [blame]	1506	>;
				1507
Michel Danzer	624b02a	2014-02-04 07:12:38 +0000	[diff] [blame]	1508	/******** ================================ ********/
				1509	/******** Floating point absolute/negative ********/
				1510	/******** ================================ ********/
				1511
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1512	// Prevent expanding both fneg and fabs.
Michel Danzer	624b02a	2014-02-04 07:12:38 +0000	[diff] [blame]	1513
Michel Danzer	624b02a	2014-02-04 07:12:38 +0000	[diff] [blame]	1514	def : Pat <
				1515	(fneg (fabs f32:$src)),
Matt Arsenault	124384f	2016-09-09 23:32:53 +0000	[diff] [blame]	1516	(S_OR_B32 $src, (S_MOV_B32 0x80000000)) // Set sign bit
Michel Danzer	624b02a	2014-02-04 07:12:38 +0000	[diff] [blame]	1517	>;
				1518
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1519	// FIXME: Should use S_OR_B32
Matt Arsenault	13623d0	2014-08-15 18:42:18 +0000	[diff] [blame]	1520	def : Pat <
				1521	(fneg (fabs f64:$src)),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1522	(REG_SEQUENCE VReg_64,
				1523	(i32 (EXTRACT_SUBREG f64:$src, sub0)),
				1524	sub0,
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1525	(V_OR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1526	(V_MOV_B32_e32 0x80000000)), // Set sign bit.
				1527	sub1)
Matt Arsenault	13623d0	2014-08-15 18:42:18 +0000	[diff] [blame]	1528	>;
				1529
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1530	def : Pat <
				1531	(fabs f32:$src),
Matt Arsenault	fa5f767	2016-09-14 15:19:03 +0000	[diff] [blame]	1532	(V_AND_B32_e64 $src, (V_MOV_B32_e32 0x7fffffff))
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1533	>;
Vincent Lejeune	79a5834	2014-05-10 19:18:25 +0000	[diff] [blame]	1534
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1535	def : Pat <
				1536	(fneg f32:$src),
				1537	(V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000))
				1538	>;
Christian Konig	8dbe6f6	2013-02-21 15:17:27 +0000	[diff] [blame]	1539
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1540	def : Pat <
				1541	(fabs f64:$src),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1542	(REG_SEQUENCE VReg_64,
				1543	(i32 (EXTRACT_SUBREG f64:$src, sub0)),
				1544	sub0,
Matt Arsenault	fa5f767	2016-09-14 15:19:03 +0000	[diff] [blame]	1545	(V_AND_B32_e64 (EXTRACT_SUBREG f64:$src, sub1),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1546	(V_MOV_B32_e32 0x7fffffff)), // Set sign bit.
				1547	sub1)
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1548	>;
Vincent Lejeune	79a5834	2014-05-10 19:18:25 +0000	[diff] [blame]	1549
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1550	def : Pat <
				1551	(fneg f64:$src),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1552	(REG_SEQUENCE VReg_64,
				1553	(i32 (EXTRACT_SUBREG f64:$src, sub0)),
				1554	sub0,
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1555	(V_XOR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1556	(V_MOV_B32_e32 0x80000000)),
				1557	sub1)
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1558	>;
Christian Konig	8dbe6f6	2013-02-21 15:17:27 +0000	[diff] [blame]	1559
Christian Konig	c756cb99	2013-02-16 11:28:22 +0000	[diff] [blame]	1560	/******** ================== ********/
				1561	/******** Immediate Patterns ********/
				1562	/******** ================== ********/
				1563
				1564	def : Pat <
Tom Stellard	df94dc3	2013-08-14 23:24:24 +0000	[diff] [blame]	1565	(SGPRImm<(i32 imm)>:$imm),
				1566	(S_MOV_B32 imm:$imm)
				1567	>;
				1568
				1569	def : Pat <
				1570	(SGPRImm<(f32 fpimm)>:$imm),
Tom Stellard	fb77f00	2015-01-13 22:59:41 +0000	[diff] [blame]	1571	(S_MOV_B32 (f32 (bitcast_fpimm_to_i32 $imm)))
Tom Stellard	df94dc3	2013-08-14 23:24:24 +0000	[diff] [blame]	1572	>;
				1573
				1574	def : Pat <
Christian Konig	c756cb99	2013-02-16 11:28:22 +0000	[diff] [blame]	1575	(i32 imm:$imm),
				1576	(V_MOV_B32_e32 imm:$imm)
				1577	>;
				1578
				1579	def : Pat <
				1580	(f32 fpimm:$imm),
Tom Stellard	fb77f00	2015-01-13 22:59:41 +0000	[diff] [blame]	1581	(V_MOV_B32_e32 (f32 (bitcast_fpimm_to_i32 $imm)))
Christian Konig	c756cb99	2013-02-16 11:28:22 +0000	[diff] [blame]	1582	>;
				1583
				1584	def : Pat <
Christian Konig	b559b07	2013-02-16 11:28:36 +0000	[diff] [blame]	1585	(i64 InlineImm<i64>:$imm),
				1586	(S_MOV_B64 InlineImm<i64>:$imm)
				1587	>;
				1588
Matt Arsenault	becd656	2014-12-03 05:22:35 +0000	[diff] [blame]	1589	// XXX - Should this use a s_cmp to set SCC?
				1590
				1591	// Set to sign-extended 64-bit value (true = -1, false = 0)
				1592	def : Pat <
				1593	(i1 imm:$imm),
				1594	(S_MOV_B64 (i64 (as_i64imm $imm)))
				1595	>;
				1596
Matt Arsenault	303011a	2014-12-17 21:04:08 +0000	[diff] [blame]	1597	def : Pat <
				1598	(f64 InlineFPImm<f64>:$imm),
Tom Stellard	fb77f00	2015-01-13 22:59:41 +0000	[diff] [blame]	1599	(S_MOV_B64 (f64 (bitcast_fpimm_to_i64 InlineFPImm<f64>:$imm)))
Matt Arsenault	303011a	2014-12-17 21:04:08 +0000	[diff] [blame]	1600	>;
				1601
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1602	/******** ================== ********/
				1603	/******** Intrinsic Patterns ********/
				1604	/******** ================== ********/
				1605
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1606	def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1607
				1608	def : Pat <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1609	(int_AMDGPU_cube v4f32:$src),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1610	(REG_SEQUENCE VReg_128,
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1611	(V_CUBETC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
				1612	0 /* src1_modifiers */, (EXTRACT_SUBREG $src, sub1),
				1613	0 /* src2_modifiers */, (EXTRACT_SUBREG $src, sub2),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1614	0 /* clamp /, 0 / omod */), sub0,
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1615	(V_CUBESC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
				1616	0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
				1617	0 /* src2_modifiers */,(EXTRACT_SUBREG $src, sub2),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1618	0 /* clamp /, 0 / omod */), sub1,
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1619	(V_CUBEMA_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
				1620	0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
				1621	0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1622	0 /* clamp /, 0 / omod */), sub2,
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1623	(V_CUBEID_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
				1624	0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
				1625	0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1626	0 /* clamp /, 0 / omod */), sub3)
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1627	>;
				1628
Michel Danzer	0cc991e	2013-02-22 11:22:58 +0000	[diff] [blame]	1629	def : Pat <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1630	(i32 (sext i1:$src0)),
				1631	(V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
Michel Danzer	0cc991e	2013-02-22 11:22:58 +0000	[diff] [blame]	1632	>;
				1633
Tom Stellard	f16d38c	2014-02-13 23:34:13 +0000	[diff] [blame]	1634	class Ext32Pat <SDNode ext> : Pat <
				1635	(i32 (ext i1:$src0)),
Michel Danzer	5d26fdf	2014-02-05 09:48:05 +0000	[diff] [blame]	1636	(V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
				1637	>;
				1638
Tom Stellard	f16d38c	2014-02-13 23:34:13 +0000	[diff] [blame]	1639	def : Ext32Pat <zext>;
				1640	def : Ext32Pat <anyext>;
				1641
Michel Danzer	8caa904	2013-04-10 17:17:56 +0000	[diff] [blame]	1642	// The multiplication scales from [0,1] to the unsigned integer range
				1643	def : Pat <
				1644	(AMDGPUurecip i32:$src0),
				1645	(V_CVT_U32_F32_e32
				1646	(V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
				1647	(V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
				1648	>;
				1649
Tom Stellard	0289ff4	2014-05-16 20:56:44 +0000	[diff] [blame]	1650	//===----------------------------------------------------------------------===//
				1651	// VOP3 Patterns
				1652	//===----------------------------------------------------------------------===//
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1653
Matt Arsenault	eb26020	2014-05-22 18:00:15 +0000	[diff] [blame]	1654	def : IMad24Pat<V_MAD_I32_I24>;
				1655	def : UMad24Pat<V_MAD_U32_U24>;
				1656
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1657	defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>;
Tom Stellard	0289ff4	2014-05-16 20:56:44 +0000	[diff] [blame]	1658	def : ROTRPattern <V_ALIGNBIT_B32>;
				1659
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1660	/******** ====================== ********/
				1661	/******** Indirect adressing ********/
				1662	/******** ====================== ********/
				1663
Matt Arsenault	2841927	2015-10-07 00:42:51 +0000	[diff] [blame]	1664	multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, string VecSize> {
Matt Arsenault	1322b6f	2016-07-09 01:13:56 +0000	[diff] [blame]	1665	// Extract with offset
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1666	def : Pat<
Nicolai Haehnle	7968c34	2016-07-12 08:12:16 +0000	[diff] [blame]	1667	(eltvt (extractelt vt:$src, (MOVRELOffset i32:$idx, (i32 imm:$offset)))),
Matt Arsenault	1322b6f	2016-07-09 01:13:56 +0000	[diff] [blame]	1668	(!cast<Instruction>("SI_INDIRECT_SRC_"#VecSize) $src, $idx, imm:$offset)
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1669	>;
				1670
Matt Arsenault	1322b6f	2016-07-09 01:13:56 +0000	[diff] [blame]	1671	// Insert with offset
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1672	def : Pat<
Nicolai Haehnle	7968c34	2016-07-12 08:12:16 +0000	[diff] [blame]	1673	(insertelt vt:$src, eltvt:$val, (MOVRELOffset i32:$idx, (i32 imm:$offset))),
Matt Arsenault	1322b6f	2016-07-09 01:13:56 +0000	[diff] [blame]	1674	(!cast<Instruction>("SI_INDIRECT_DST_"#VecSize) $src, $idx, imm:$offset, $val)
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1675	>;
				1676	}
				1677
Matt Arsenault	2841927	2015-10-07 00:42:51 +0000	[diff] [blame]	1678	defm : SI_INDIRECT_Pattern <v2f32, f32, "V2">;
				1679	defm : SI_INDIRECT_Pattern <v4f32, f32, "V4">;
				1680	defm : SI_INDIRECT_Pattern <v8f32, f32, "V8">;
				1681	defm : SI_INDIRECT_Pattern <v16f32, f32, "V16">;
Matt Arsenault	f5958dd	2014-02-02 00:05:35 +0000	[diff] [blame]	1682
Matt Arsenault	2841927	2015-10-07 00:42:51 +0000	[diff] [blame]	1683	defm : SI_INDIRECT_Pattern <v2i32, i32, "V2">;
				1684	defm : SI_INDIRECT_Pattern <v4i32, i32, "V4">;
				1685	defm : SI_INDIRECT_Pattern <v8i32, i32, "V8">;
				1686	defm : SI_INDIRECT_Pattern <v16i32, i32, "V16">;
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1687
Tom Stellard	81d871d	2013-11-13 23:36:50 +0000	[diff] [blame]	1688	//===----------------------------------------------------------------------===//
Wei Ding	1041a64	2016-08-24 14:59:47 +0000	[diff] [blame]	1689	// SAD Patterns
				1690	//===----------------------------------------------------------------------===//
				1691
				1692	def : Pat <
				1693	(add (sub_oneuse (umax i32:$src0, i32:$src1),
				1694	(umin i32:$src0, i32:$src1)),
				1695	i32:$src2),
				1696	(V_SAD_U32 $src0, $src1, $src2)
				1697	>;
				1698
				1699	def : Pat <
				1700	(add (select_oneuse (i1 (setugt i32:$src0, i32:$src1)),
				1701	(sub i32:$src0, i32:$src1),
				1702	(sub i32:$src1, i32:$src0)),
				1703	i32:$src2),
				1704	(V_SAD_U32 $src0, $src1, $src2)
				1705	>;
				1706
				1707	//===----------------------------------------------------------------------===//
Matt Arsenault	5dbd5db	2014-04-22 03:49:30 +0000	[diff] [blame]	1708	// Conversion Patterns
				1709	//===----------------------------------------------------------------------===//
				1710
				1711	def : Pat<(i32 (sext_inreg i32:$src, i1)),
				1712	(S_BFE_I32 i32:$src, 65536)>; // 0 \| 1 << 16
				1713
Matt Arsenault	5dbd5db	2014-04-22 03:49:30 +0000	[diff] [blame]	1714	// Handle sext_inreg in i64
				1715	def : Pat <
				1716	(i64 (sext_inreg i64:$src, i1)),
Matt Arsenault	9481221	2014-11-14 18:18:16 +0000	[diff] [blame]	1717	(S_BFE_I64 i64:$src, 0x10000) // 0 \| 1 << 16
Matt Arsenault	5dbd5db	2014-04-22 03:49:30 +0000	[diff] [blame]	1718	>;
				1719
				1720	def : Pat <
				1721	(i64 (sext_inreg i64:$src, i8)),
Matt Arsenault	9481221	2014-11-14 18:18:16 +0000	[diff] [blame]	1722	(S_BFE_I64 i64:$src, 0x80000) // 0 \| 8 << 16
Matt Arsenault	5dbd5db	2014-04-22 03:49:30 +0000	[diff] [blame]	1723	>;
				1724
				1725	def : Pat <
				1726	(i64 (sext_inreg i64:$src, i16)),
Matt Arsenault	9481221	2014-11-14 18:18:16 +0000	[diff] [blame]	1727	(S_BFE_I64 i64:$src, 0x100000) // 0 \| 16 << 16
				1728	>;
				1729
				1730	def : Pat <
				1731	(i64 (sext_inreg i64:$src, i32)),
				1732	(S_BFE_I64 i64:$src, 0x200000) // 0 \| 32 << 16
Matt Arsenault	5dbd5db	2014-04-22 03:49:30 +0000	[diff] [blame]	1733	>;
				1734
Matt Arsenault	c6b69a9	2016-07-26 23:06:33 +0000	[diff] [blame]	1735	def : Pat <
				1736	(i64 (zext i32:$src)),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1737	(REG_SEQUENCE SReg_64, $src, sub0, (S_MOV_B32 0), sub1)
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	1738	>;
				1739
Matt Arsenault	c6b69a9	2016-07-26 23:06:33 +0000	[diff] [blame]	1740	def : Pat <
				1741	(i64 (anyext i32:$src)),
				1742	(REG_SEQUENCE SReg_64, $src, sub0, (i32 (IMPLICIT_DEF)), sub1)
				1743	>;
				1744
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	1745	class ZExt_i64_i1_Pat <SDNode ext> : Pat <
				1746	(i64 (ext i1:$src)),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1747	(REG_SEQUENCE VReg_64,
				1748	(V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0,
				1749	(S_MOV_B32 0), sub1)
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	1750	>;
				1751
				1752
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	1753	def : ZExt_i64_i1_Pat<zext>;
				1754	def : ZExt_i64_i1_Pat<anyext>;
				1755
Tom Stellard	bc4497b	2016-02-12 23:45:29 +0000	[diff] [blame]	1756	// FIXME: We need to use COPY_TO_REGCLASS to work-around the fact that
				1757	// REG_SEQUENCE patterns don't support instructions with multiple outputs.
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	1758	def : Pat <
				1759	(i64 (sext i32:$src)),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1760	(REG_SEQUENCE SReg_64, $src, sub0,
Artem Tamazov	38e496b	2016-04-29 17:04:50 +0000	[diff] [blame]	1761	(i32 (COPY_TO_REGCLASS (S_ASHR_I32 $src, 31), SReg_32_XM0)), sub1)
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	1762	>;
				1763
				1764	def : Pat <
				1765	(i64 (sext i1:$src)),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1766	(REG_SEQUENCE VReg_64,
				1767	(V_CNDMASK_B32_e64 0, -1, $src), sub0,
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	1768	(V_CNDMASK_B32_e64 0, -1, $src), sub1)
				1769	>;
				1770
Matt Arsenault	7fb961f	2016-07-22 17:01:21 +0000	[diff] [blame]	1771	class FPToI1Pat<Instruction Inst, int KOne, ValueType vt, SDPatternOperator fp_to_int> : Pat <
				1772	(i1 (fp_to_int (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)))),
				1773	(i1 (Inst 0, KOne, $src0_modifiers, $src0, DSTCLAMP.NONE, DSTOMOD.NONE))
				1774	>;
				1775
				1776	def : FPToI1Pat<V_CMP_EQ_F32_e64, CONST.FP32_ONE, f32, fp_to_uint>;
				1777	def : FPToI1Pat<V_CMP_EQ_F32_e64, CONST.FP32_NEG_ONE, f32, fp_to_sint>;
				1778	def : FPToI1Pat<V_CMP_EQ_F64_e64, CONST.FP64_ONE, f64, fp_to_uint>;
				1779	def : FPToI1Pat<V_CMP_EQ_F64_e64, CONST.FP64_NEG_ONE, f64, fp_to_sint>;
				1780
Matt Arsenault	becd656	2014-12-03 05:22:35 +0000	[diff] [blame]	1781	// If we need to perform a logical operation on i1 values, we need to
				1782	// use vector comparisons since there is only one SCC register. Vector
				1783	// comparisions still write to a pair of SGPRs, so treat these as
				1784	// 64-bit comparisons. When legalizing SGPR copies, instructions
				1785	// resulting in the copies from SCC to these instructions will be
				1786	// moved to the VALU.
				1787	def : Pat <
				1788	(i1 (and i1:$src0, i1:$src1)),
				1789	(S_AND_B64 $src0, $src1)
				1790	>;
				1791
				1792	def : Pat <
				1793	(i1 (or i1:$src0, i1:$src1)),
				1794	(S_OR_B64 $src0, $src1)
				1795	>;
				1796
				1797	def : Pat <
				1798	(i1 (xor i1:$src0, i1:$src1)),
				1799	(S_XOR_B64 $src0, $src1)
				1800	>;
				1801
Matt Arsenault	aeca2fa	2014-05-31 06:47:42 +0000	[diff] [blame]	1802	def : Pat <
				1803	(f32 (sint_to_fp i1:$src)),
				1804	(V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src)
				1805	>;
				1806
				1807	def : Pat <
				1808	(f32 (uint_to_fp i1:$src)),
				1809	(V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src)
				1810	>;
				1811
				1812	def : Pat <
				1813	(f64 (sint_to_fp i1:$src)),
Matt Arsenault	becd656	2014-12-03 05:22:35 +0000	[diff] [blame]	1814	(V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src))
Matt Arsenault	aeca2fa	2014-05-31 06:47:42 +0000	[diff] [blame]	1815	>;
				1816
				1817	def : Pat <
				1818	(f64 (uint_to_fp i1:$src)),
				1819	(V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src))
				1820	>;
				1821
Matt Arsenault	5dbd5db	2014-04-22 03:49:30 +0000	[diff] [blame]	1822	//===----------------------------------------------------------------------===//
Tom Stellard	fb96169	2013-10-23 00:44:19 +0000	[diff] [blame]	1823	// Miscellaneous Patterns
				1824	//===----------------------------------------------------------------------===//
				1825
				1826	def : Pat <
Tom Stellard	81d871d	2013-11-13 23:36:50 +0000	[diff] [blame]	1827	(i32 (trunc i64:$a)),
				1828	(EXTRACT_SUBREG $a, sub0)
				1829	>;
				1830
Michel Danzer	bf1a641	2014-01-28 03:01:16 +0000	[diff] [blame]	1831	def : Pat <
				1832	(i1 (trunc i32:$a)),
Marek Olsak	f924dd6	2015-10-29 15:05:03 +0000	[diff] [blame]	1833	(V_CMP_EQ_I32_e64 (S_AND_B32 (i32 1), $a), 1)
Michel Danzer	bf1a641	2014-01-28 03:01:16 +0000	[diff] [blame]	1834	>;
				1835
Matt Arsenault	e306a32	2014-10-21 16:25:08 +0000	[diff] [blame]	1836	def : Pat <
Matt Arsenault	abd271b	2015-02-05 06:05:13 +0000	[diff] [blame]	1837	(i1 (trunc i64:$a)),
Marek Olsak	f924dd6	2015-10-29 15:05:03 +0000	[diff] [blame]	1838	(V_CMP_EQ_I32_e64 (S_AND_B32 (i32 1),
Matt Arsenault	abd271b	2015-02-05 06:05:13 +0000	[diff] [blame]	1839	(EXTRACT_SUBREG $a, sub0)), 1)
				1840	>;
				1841
				1842	def : Pat <
Matt Arsenault	e306a32	2014-10-21 16:25:08 +0000	[diff] [blame]	1843	(i32 (bswap i32:$a)),
				1844	(V_BFI_B32 (S_MOV_B32 0x00ff00ff),
				1845	(V_ALIGNBIT_B32 $a, $a, 24),
				1846	(V_ALIGNBIT_B32 $a, $a, 8))
				1847	>;
				1848
Matt Arsenault	477b1782	2014-12-12 02:30:29 +0000	[diff] [blame]	1849	def : Pat <
				1850	(f32 (select i1:$src2, f32:$src1, f32:$src0)),
				1851	(V_CNDMASK_B32_e64 $src0, $src1, $src2)
				1852	>;
				1853
Marek Olsak	63a7b08	2015-03-24 13:40:21 +0000	[diff] [blame]	1854	multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> {
				1855	def : Pat <
				1856	(vt (shl (vt (add (vt (shl 1, vt:$a)), -1)), vt:$b)),
				1857	(BFM $a, $b)
				1858	>;
				1859
				1860	def : Pat <
				1861	(vt (add (vt (shl 1, vt:$a)), -1)),
				1862	(BFM $a, (MOV 0))
				1863	>;
				1864	}
				1865
				1866	defm : BFMPatterns <i32, S_BFM_B32, S_MOV_B32>;
				1867	// FIXME: defm : BFMPatterns <i64, S_BFM_B64, S_MOV_B64>;
				1868
Marek Olsak	949f5da	2015-03-24 13:40:34 +0000	[diff] [blame]	1869	def : BFEPattern <V_BFE_U32, S_MOV_B32>;
				1870
Matt Arsenault	9cd9071	2016-04-14 01:42:16 +0000	[diff] [blame]	1871	def : Pat<
				1872	(fcanonicalize f32:$src),
				1873	(V_MUL_F32_e64 0, CONST.FP32_ONE, 0, $src, 0, 0)
				1874	>;
				1875
				1876	def : Pat<
				1877	(fcanonicalize f64:$src),
				1878	(V_MUL_F64 0, CONST.FP64_ONE, 0, $src, 0, 0)
				1879	>;
				1880
Marek Olsak	43650e4	2015-03-24 13:40:08 +0000	[diff] [blame]	1881	//===----------------------------------------------------------------------===//
				1882	// Fract Patterns
				1883	//===----------------------------------------------------------------------===//
				1884
Marek Olsak	7d77728	2015-03-24 13:40:15 +0000	[diff] [blame]	1885	let Predicates = [isSI] in {
				1886
				1887	// V_FRACT is buggy on SI, so the F32 version is never used and (x-floor(x)) is
				1888	// used instead. However, SI doesn't have V_FLOOR_F64, so the most efficient
				1889	// way to implement it is using V_FRACT_F64.
				1890	// The workaround for the V_FRACT bug is:
				1891	// fract(x) = isnan(x) ? x : min(V_FRACT(x), 0.99999999999999999)
				1892
Marek Olsak	7d77728	2015-03-24 13:40:15 +0000	[diff] [blame]	1893	// Convert floor(x) to (x - fract(x))
				1894	def : Pat <
				1895	(f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))),
				1896	(V_ADD_F64
				1897	$mods,
				1898	$x,
				1899	SRCMODS.NEG,
				1900	(V_CNDMASK_B64_PSEUDO
Marek Olsak	7d77728	2015-03-24 13:40:15 +0000	[diff] [blame]	1901	(V_MIN_F64
				1902	SRCMODS.NONE,
				1903	(V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE),
				1904	SRCMODS.NONE,
				1905	(V_MOV_B64_PSEUDO 0x3fefffffffffffff),
				1906	DSTCLAMP.NONE, DSTOMOD.NONE),
Marek Olsak	1354b87	2015-07-27 11:37:42 +0000	[diff] [blame]	1907	$x,
Marek Olsak	7d77728	2015-03-24 13:40:15 +0000	[diff] [blame]	1908	(V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, 3/NaN/)),
				1909	DSTCLAMP.NONE, DSTOMOD.NONE)
				1910	>;
				1911
				1912	} // End Predicates = [isSI]
				1913
Tom Stellard	fb96169	2013-10-23 00:44:19 +0000	[diff] [blame]	1914	//============================================================================//
Tom Stellard	eac65dd	2013-05-03 17:21:20 +0000	[diff] [blame]	1915	// Miscellaneous Optimization Patterns
				1916	//============================================================================//
				1917
Matt Arsenault	49dd428	2014-09-15 17:15:02 +0000	[diff] [blame]	1918	def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64>;
Tom Stellard	eac65dd	2013-05-03 17:21:20 +0000	[diff] [blame]	1919
Matt Arsenault	c89f291	2016-03-07 21:54:48 +0000	[diff] [blame]	1920	def : IntMed3Pat<V_MED3_I32, smax, smax_oneuse, smin_oneuse>;
				1921	def : IntMed3Pat<V_MED3_U32, umax, umax_oneuse, umin_oneuse>;
				1922
Tom Stellard	245c15f	2015-05-26 15:55:52 +0000	[diff] [blame]	1923	//============================================================================//
				1924	// Assembler aliases
				1925	//============================================================================//
				1926
				1927	def : MnemonicAlias<"v_add_u32", "v_add_i32">;
				1928	def : MnemonicAlias<"v_sub_u32", "v_sub_i32">;
				1929	def : MnemonicAlias<"v_subrev_u32", "v_subrev_i32">;
				1930
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1931	} // End isGCN predicate