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Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1	//===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
				2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
				9	// This file was originally auto-generated from a GPU register header file and
				10	// all the instruction definitions were originally commented out. Instructions
				11	// that are not yet supported remain commented out.
				12	//===----------------------------------------------------------------------===//
				13
Eric Christopher	7792e32	2015-01-30 23:24:40 +0000	[diff] [blame]	14	def isGCN : Predicate<"Subtarget->getGeneration() "
Matt Arsenault	43e92fe	2016-06-24 06:30:11 +0000	[diff] [blame]	15	">= SISubtarget::SOUTHERN_ISLANDS">,
Tom Stellard	d7e6f13	2015-04-08 01:09:26 +0000	[diff] [blame]	16	AssemblerPredicate<"FeatureGCN">;
Marek Olsak	7d77728	2015-03-24 13:40:15 +0000	[diff] [blame]	17	def isSI : Predicate<"Subtarget->getGeneration() "
Matt Arsenault	43e92fe	2016-06-24 06:30:11 +0000	[diff] [blame]	18	"== SISubtarget::SOUTHERN_ISLANDS">,
Matt Arsenault	d6adfb4	2015-09-24 19:52:21 +0000	[diff] [blame]	19	AssemblerPredicate<"FeatureSouthernIslands">;
				20
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	21	def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
				22	def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
				23
Valery Pykhtin	a34fb49	2016-08-30 15:20:31 +0000	[diff] [blame]	24	include "SOPInstructions.td"
Valery Pykhtin	1b13886	2016-09-01 09:56:47 +0000	[diff] [blame]	25	include "SMInstructions.td"
Valery Pykhtin	a34fb49	2016-08-30 15:20:31 +0000	[diff] [blame]	26
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	27	let SubtargetPredicate = isGCN in {
Tom Stellard	0e70de5	2014-05-16 20:56:45 +0000	[diff] [blame]	28
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	29	//===----------------------------------------------------------------------===//
Tom Stellard	3a35d8f	2014-10-01 14:44:45 +0000	[diff] [blame]	30	// EXP Instructions
				31	//===----------------------------------------------------------------------===//
				32
				33	defm EXP : EXP_m;
				34
				35	//===----------------------------------------------------------------------===//
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	36	// VOPC Instructions
				37	//===----------------------------------------------------------------------===//
				38
Matt Arsenault	0943b0e	2015-03-23 18:45:38 +0000	[diff] [blame]	39	let isCompare = 1, isCommutable = 1 in {
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	40
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	41	defm V_CMP_F_F32 : VOPC_F32 <vopc<0x0, 0x40>, "v_cmp_f_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	42	defm V_CMP_LT_F32 : VOPC_F32 <vopc<0x1, 0x41>, "v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	43	defm V_CMP_EQ_F32 : VOPC_F32 <vopc<0x2, 0x42>, "v_cmp_eq_f32", COND_OEQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	44	defm V_CMP_LE_F32 : VOPC_F32 <vopc<0x3, 0x43>, "v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	45	defm V_CMP_GT_F32 : VOPC_F32 <vopc<0x4, 0x44>, "v_cmp_gt_f32", COND_OGT>;
Matt Arsenault	9cded7a	2014-12-11 22:15:35 +0000	[diff] [blame]	46	defm V_CMP_LG_F32 : VOPC_F32 <vopc<0x5, 0x45>, "v_cmp_lg_f32", COND_ONE>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	47	defm V_CMP_GE_F32 : VOPC_F32 <vopc<0x6, 0x46>, "v_cmp_ge_f32", COND_OGE>;
				48	defm V_CMP_O_F32 : VOPC_F32 <vopc<0x7, 0x47>, "v_cmp_o_f32", COND_O>;
				49	defm V_CMP_U_F32 : VOPC_F32 <vopc<0x8, 0x48>, "v_cmp_u_f32", COND_UO>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	50	defm V_CMP_NGE_F32 : VOPC_F32 <vopc<0x9, 0x49>, "v_cmp_nge_f32", COND_ULT, "v_cmp_nle_f32">;
Matt Arsenault	58d502f	2014-12-11 22:15:43 +0000	[diff] [blame]	51	defm V_CMP_NLG_F32 : VOPC_F32 <vopc<0xa, 0x4a>, "v_cmp_nlg_f32", COND_UEQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	52	defm V_CMP_NGT_F32 : VOPC_F32 <vopc<0xb, 0x4b>, "v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">;
Matt Arsenault	8b989ef	2014-12-11 22:15:39 +0000	[diff] [blame]	53	defm V_CMP_NLE_F32 : VOPC_F32 <vopc<0xc, 0x4c>, "v_cmp_nle_f32", COND_UGT>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	54	defm V_CMP_NEQ_F32 : VOPC_F32 <vopc<0xd, 0x4d>, "v_cmp_neq_f32", COND_UNE>;
Matt Arsenault	8b989ef	2014-12-11 22:15:39 +0000	[diff] [blame]	55	defm V_CMP_NLT_F32 : VOPC_F32 <vopc<0xe, 0x4e>, "v_cmp_nlt_f32", COND_UGE>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	56	defm V_CMP_TRU_F32 : VOPC_F32 <vopc<0xf, 0x4f>, "v_cmp_tru_f32">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	57
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	58
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	59	defm V_CMPX_F_F32 : VOPCX_F32 <vopc<0x10, 0x50>, "v_cmpx_f_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	60	defm V_CMPX_LT_F32 : VOPCX_F32 <vopc<0x11, 0x51>, "v_cmpx_lt_f32", "v_cmpx_gt_f32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	61	defm V_CMPX_EQ_F32 : VOPCX_F32 <vopc<0x12, 0x52>, "v_cmpx_eq_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	62	defm V_CMPX_LE_F32 : VOPCX_F32 <vopc<0x13, 0x53>, "v_cmpx_le_f32", "v_cmpx_ge_f32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	63	defm V_CMPX_GT_F32 : VOPCX_F32 <vopc<0x14, 0x54>, "v_cmpx_gt_f32">;
				64	defm V_CMPX_LG_F32 : VOPCX_F32 <vopc<0x15, 0x55>, "v_cmpx_lg_f32">;
				65	defm V_CMPX_GE_F32 : VOPCX_F32 <vopc<0x16, 0x56>, "v_cmpx_ge_f32">;
				66	defm V_CMPX_O_F32 : VOPCX_F32 <vopc<0x17, 0x57>, "v_cmpx_o_f32">;
				67	defm V_CMPX_U_F32 : VOPCX_F32 <vopc<0x18, 0x58>, "v_cmpx_u_f32">;
				68	defm V_CMPX_NGE_F32 : VOPCX_F32 <vopc<0x19, 0x59>, "v_cmpx_nge_f32">;
				69	defm V_CMPX_NLG_F32 : VOPCX_F32 <vopc<0x1a, 0x5a>, "v_cmpx_nlg_f32">;
				70	defm V_CMPX_NGT_F32 : VOPCX_F32 <vopc<0x1b, 0x5b>, "v_cmpx_ngt_f32">;
				71	defm V_CMPX_NLE_F32 : VOPCX_F32 <vopc<0x1c, 0x5c>, "v_cmpx_nle_f32">;
				72	defm V_CMPX_NEQ_F32 : VOPCX_F32 <vopc<0x1d, 0x5d>, "v_cmpx_neq_f32">;
				73	defm V_CMPX_NLT_F32 : VOPCX_F32 <vopc<0x1e, 0x5e>, "v_cmpx_nlt_f32">;
				74	defm V_CMPX_TRU_F32 : VOPCX_F32 <vopc<0x1f, 0x5f>, "v_cmpx_tru_f32">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	75
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	76
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	77	defm V_CMP_F_F64 : VOPC_F64 <vopc<0x20, 0x60>, "v_cmp_f_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	78	defm V_CMP_LT_F64 : VOPC_F64 <vopc<0x21, 0x61>, "v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	79	defm V_CMP_EQ_F64 : VOPC_F64 <vopc<0x22, 0x62>, "v_cmp_eq_f64", COND_OEQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	80	defm V_CMP_LE_F64 : VOPC_F64 <vopc<0x23, 0x63>, "v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	81	defm V_CMP_GT_F64 : VOPC_F64 <vopc<0x24, 0x64>, "v_cmp_gt_f64", COND_OGT>;
Matt Arsenault	9cded7a	2014-12-11 22:15:35 +0000	[diff] [blame]	82	defm V_CMP_LG_F64 : VOPC_F64 <vopc<0x25, 0x65>, "v_cmp_lg_f64", COND_ONE>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	83	defm V_CMP_GE_F64 : VOPC_F64 <vopc<0x26, 0x66>, "v_cmp_ge_f64", COND_OGE>;
				84	defm V_CMP_O_F64 : VOPC_F64 <vopc<0x27, 0x67>, "v_cmp_o_f64", COND_O>;
				85	defm V_CMP_U_F64 : VOPC_F64 <vopc<0x28, 0x68>, "v_cmp_u_f64", COND_UO>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	86	defm V_CMP_NGE_F64 : VOPC_F64 <vopc<0x29, 0x69>, "v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">;
Matt Arsenault	58d502f	2014-12-11 22:15:43 +0000	[diff] [blame]	87	defm V_CMP_NLG_F64 : VOPC_F64 <vopc<0x2a, 0x6a>, "v_cmp_nlg_f64", COND_UEQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	88	defm V_CMP_NGT_F64 : VOPC_F64 <vopc<0x2b, 0x6b>, "v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">;
Matt Arsenault	8b989ef	2014-12-11 22:15:39 +0000	[diff] [blame]	89	defm V_CMP_NLE_F64 : VOPC_F64 <vopc<0x2c, 0x6c>, "v_cmp_nle_f64", COND_UGT>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	90	defm V_CMP_NEQ_F64 : VOPC_F64 <vopc<0x2d, 0x6d>, "v_cmp_neq_f64", COND_UNE>;
Matt Arsenault	8b989ef	2014-12-11 22:15:39 +0000	[diff] [blame]	91	defm V_CMP_NLT_F64 : VOPC_F64 <vopc<0x2e, 0x6e>, "v_cmp_nlt_f64", COND_UGE>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	92	defm V_CMP_TRU_F64 : VOPC_F64 <vopc<0x2f, 0x6f>, "v_cmp_tru_f64">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	93
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	94
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	95	defm V_CMPX_F_F64 : VOPCX_F64 <vopc<0x30, 0x70>, "v_cmpx_f_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	96	defm V_CMPX_LT_F64 : VOPCX_F64 <vopc<0x31, 0x71>, "v_cmpx_lt_f64", "v_cmpx_gt_f64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	97	defm V_CMPX_EQ_F64 : VOPCX_F64 <vopc<0x32, 0x72>, "v_cmpx_eq_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	98	defm V_CMPX_LE_F64 : VOPCX_F64 <vopc<0x33, 0x73>, "v_cmpx_le_f64", "v_cmpx_ge_f64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	99	defm V_CMPX_GT_F64 : VOPCX_F64 <vopc<0x34, 0x74>, "v_cmpx_gt_f64">;
				100	defm V_CMPX_LG_F64 : VOPCX_F64 <vopc<0x35, 0x75>, "v_cmpx_lg_f64">;
				101	defm V_CMPX_GE_F64 : VOPCX_F64 <vopc<0x36, 0x76>, "v_cmpx_ge_f64">;
				102	defm V_CMPX_O_F64 : VOPCX_F64 <vopc<0x37, 0x77>, "v_cmpx_o_f64">;
				103	defm V_CMPX_U_F64 : VOPCX_F64 <vopc<0x38, 0x78>, "v_cmpx_u_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	104	defm V_CMPX_NGE_F64 : VOPCX_F64 <vopc<0x39, 0x79>, "v_cmpx_nge_f64", "v_cmpx_nle_f64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	105	defm V_CMPX_NLG_F64 : VOPCX_F64 <vopc<0x3a, 0x7a>, "v_cmpx_nlg_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	106	defm V_CMPX_NGT_F64 : VOPCX_F64 <vopc<0x3b, 0x7b>, "v_cmpx_ngt_f64", "v_cmpx_nlt_f64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	107	defm V_CMPX_NLE_F64 : VOPCX_F64 <vopc<0x3c, 0x7c>, "v_cmpx_nle_f64">;
				108	defm V_CMPX_NEQ_F64 : VOPCX_F64 <vopc<0x3d, 0x7d>, "v_cmpx_neq_f64">;
				109	defm V_CMPX_NLT_F64 : VOPCX_F64 <vopc<0x3e, 0x7e>, "v_cmpx_nlt_f64">;
				110	defm V_CMPX_TRU_F64 : VOPCX_F64 <vopc<0x3f, 0x7f>, "v_cmpx_tru_f64">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	111
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	112
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	113	let SubtargetPredicate = isSICI in {
				114
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	115	defm V_CMPS_F_F32 : VOPC_F32 <vopc<0x40>, "v_cmps_f_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	116	defm V_CMPS_LT_F32 : VOPC_F32 <vopc<0x41>, "v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	117	defm V_CMPS_EQ_F32 : VOPC_F32 <vopc<0x42>, "v_cmps_eq_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	118	defm V_CMPS_LE_F32 : VOPC_F32 <vopc<0x43>, "v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	119	defm V_CMPS_GT_F32 : VOPC_F32 <vopc<0x44>, "v_cmps_gt_f32">;
				120	defm V_CMPS_LG_F32 : VOPC_F32 <vopc<0x45>, "v_cmps_lg_f32">;
				121	defm V_CMPS_GE_F32 : VOPC_F32 <vopc<0x46>, "v_cmps_ge_f32">;
				122	defm V_CMPS_O_F32 : VOPC_F32 <vopc<0x47>, "v_cmps_o_f32">;
				123	defm V_CMPS_U_F32 : VOPC_F32 <vopc<0x48>, "v_cmps_u_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	124	defm V_CMPS_NGE_F32 : VOPC_F32 <vopc<0x49>, "v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	125	defm V_CMPS_NLG_F32 : VOPC_F32 <vopc<0x4a>, "v_cmps_nlg_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	126	defm V_CMPS_NGT_F32 : VOPC_F32 <vopc<0x4b>, "v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	127	defm V_CMPS_NLE_F32 : VOPC_F32 <vopc<0x4c>, "v_cmps_nle_f32">;
				128	defm V_CMPS_NEQ_F32 : VOPC_F32 <vopc<0x4d>, "v_cmps_neq_f32">;
				129	defm V_CMPS_NLT_F32 : VOPC_F32 <vopc<0x4e>, "v_cmps_nlt_f32">;
				130	defm V_CMPS_TRU_F32 : VOPC_F32 <vopc<0x4f>, "v_cmps_tru_f32">;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	131
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	132
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	133	defm V_CMPSX_F_F32 : VOPCX_F32 <vopc<0x50>, "v_cmpsx_f_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	134	defm V_CMPSX_LT_F32 : VOPCX_F32 <vopc<0x51>, "v_cmpsx_lt_f32", "v_cmpsx_gt_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	135	defm V_CMPSX_EQ_F32 : VOPCX_F32 <vopc<0x52>, "v_cmpsx_eq_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	136	defm V_CMPSX_LE_F32 : VOPCX_F32 <vopc<0x53>, "v_cmpsx_le_f32", "v_cmpsx_ge_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	137	defm V_CMPSX_GT_F32 : VOPCX_F32 <vopc<0x54>, "v_cmpsx_gt_f32">;
				138	defm V_CMPSX_LG_F32 : VOPCX_F32 <vopc<0x55>, "v_cmpsx_lg_f32">;
				139	defm V_CMPSX_GE_F32 : VOPCX_F32 <vopc<0x56>, "v_cmpsx_ge_f32">;
				140	defm V_CMPSX_O_F32 : VOPCX_F32 <vopc<0x57>, "v_cmpsx_o_f32">;
				141	defm V_CMPSX_U_F32 : VOPCX_F32 <vopc<0x58>, "v_cmpsx_u_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	142	defm V_CMPSX_NGE_F32 : VOPCX_F32 <vopc<0x59>, "v_cmpsx_nge_f32", "v_cmpsx_nle_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	143	defm V_CMPSX_NLG_F32 : VOPCX_F32 <vopc<0x5a>, "v_cmpsx_nlg_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	144	defm V_CMPSX_NGT_F32 : VOPCX_F32 <vopc<0x5b>, "v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	145	defm V_CMPSX_NLE_F32 : VOPCX_F32 <vopc<0x5c>, "v_cmpsx_nle_f32">;
				146	defm V_CMPSX_NEQ_F32 : VOPCX_F32 <vopc<0x5d>, "v_cmpsx_neq_f32">;
				147	defm V_CMPSX_NLT_F32 : VOPCX_F32 <vopc<0x5e>, "v_cmpsx_nlt_f32">;
				148	defm V_CMPSX_TRU_F32 : VOPCX_F32 <vopc<0x5f>, "v_cmpsx_tru_f32">;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	149
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	150
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	151	defm V_CMPS_F_F64 : VOPC_F64 <vopc<0x60>, "v_cmps_f_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	152	defm V_CMPS_LT_F64 : VOPC_F64 <vopc<0x61>, "v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	153	defm V_CMPS_EQ_F64 : VOPC_F64 <vopc<0x62>, "v_cmps_eq_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	154	defm V_CMPS_LE_F64 : VOPC_F64 <vopc<0x63>, "v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	155	defm V_CMPS_GT_F64 : VOPC_F64 <vopc<0x64>, "v_cmps_gt_f64">;
				156	defm V_CMPS_LG_F64 : VOPC_F64 <vopc<0x65>, "v_cmps_lg_f64">;
				157	defm V_CMPS_GE_F64 : VOPC_F64 <vopc<0x66>, "v_cmps_ge_f64">;
				158	defm V_CMPS_O_F64 : VOPC_F64 <vopc<0x67>, "v_cmps_o_f64">;
				159	defm V_CMPS_U_F64 : VOPC_F64 <vopc<0x68>, "v_cmps_u_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	160	defm V_CMPS_NGE_F64 : VOPC_F64 <vopc<0x69>, "v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	161	defm V_CMPS_NLG_F64 : VOPC_F64 <vopc<0x6a>, "v_cmps_nlg_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	162	defm V_CMPS_NGT_F64 : VOPC_F64 <vopc<0x6b>, "v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	163	defm V_CMPS_NLE_F64 : VOPC_F64 <vopc<0x6c>, "v_cmps_nle_f64">;
				164	defm V_CMPS_NEQ_F64 : VOPC_F64 <vopc<0x6d>, "v_cmps_neq_f64">;
				165	defm V_CMPS_NLT_F64 : VOPC_F64 <vopc<0x6e>, "v_cmps_nlt_f64">;
				166	defm V_CMPS_TRU_F64 : VOPC_F64 <vopc<0x6f>, "v_cmps_tru_f64">;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	167
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	168
Matt Arsenault	05b617f	2015-03-23 18:45:23 +0000	[diff] [blame]	169	defm V_CMPSX_F_F64 : VOPCX_F64 <vopc<0x70>, "v_cmpsx_f_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	170	defm V_CMPSX_LT_F64 : VOPCX_F64 <vopc<0x71>, "v_cmpsx_lt_f64", "v_cmpsx_gt_f64">;
Matt Arsenault	05b617f	2015-03-23 18:45:23 +0000	[diff] [blame]	171	defm V_CMPSX_EQ_F64 : VOPCX_F64 <vopc<0x72>, "v_cmpsx_eq_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	172	defm V_CMPSX_LE_F64 : VOPCX_F64 <vopc<0x73>, "v_cmpsx_le_f64", "v_cmpsx_ge_f64">;
Matt Arsenault	05b617f	2015-03-23 18:45:23 +0000	[diff] [blame]	173	defm V_CMPSX_GT_F64 : VOPCX_F64 <vopc<0x74>, "v_cmpsx_gt_f64">;
				174	defm V_CMPSX_LG_F64 : VOPCX_F64 <vopc<0x75>, "v_cmpsx_lg_f64">;
				175	defm V_CMPSX_GE_F64 : VOPCX_F64 <vopc<0x76>, "v_cmpsx_ge_f64">;
				176	defm V_CMPSX_O_F64 : VOPCX_F64 <vopc<0x77>, "v_cmpsx_o_f64">;
				177	defm V_CMPSX_U_F64 : VOPCX_F64 <vopc<0x78>, "v_cmpsx_u_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	178	defm V_CMPSX_NGE_F64 : VOPCX_F64 <vopc<0x79>, "v_cmpsx_nge_f64", "v_cmpsx_nle_f64">;
Matt Arsenault	05b617f	2015-03-23 18:45:23 +0000	[diff] [blame]	179	defm V_CMPSX_NLG_F64 : VOPCX_F64 <vopc<0x7a>, "v_cmpsx_nlg_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	180	defm V_CMPSX_NGT_F64 : VOPCX_F64 <vopc<0x7b>, "v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">;
Matt Arsenault	05b617f	2015-03-23 18:45:23 +0000	[diff] [blame]	181	defm V_CMPSX_NLE_F64 : VOPCX_F64 <vopc<0x7c>, "v_cmpsx_nle_f64">;
				182	defm V_CMPSX_NEQ_F64 : VOPCX_F64 <vopc<0x7d>, "v_cmpsx_neq_f64">;
				183	defm V_CMPSX_NLT_F64 : VOPCX_F64 <vopc<0x7e>, "v_cmpsx_nlt_f64">;
				184	defm V_CMPSX_TRU_F64 : VOPCX_F64 <vopc<0x7f>, "v_cmpsx_tru_f64">;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	185
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	186	} // End SubtargetPredicate = isSICI
				187
				188	defm V_CMP_F_I32 : VOPC_I32 <vopc<0x80, 0xc0>, "v_cmp_f_i32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	189	defm V_CMP_LT_I32 : VOPC_I32 <vopc<0x81, 0xc1>, "v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	190	defm V_CMP_EQ_I32 : VOPC_I32 <vopc<0x82, 0xc2>, "v_cmp_eq_i32", COND_EQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	191	defm V_CMP_LE_I32 : VOPC_I32 <vopc<0x83, 0xc3>, "v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	192	defm V_CMP_GT_I32 : VOPC_I32 <vopc<0x84, 0xc4>, "v_cmp_gt_i32", COND_SGT>;
				193	defm V_CMP_NE_I32 : VOPC_I32 <vopc<0x85, 0xc5>, "v_cmp_ne_i32", COND_NE>;
				194	defm V_CMP_GE_I32 : VOPC_I32 <vopc<0x86, 0xc6>, "v_cmp_ge_i32", COND_SGE>;
				195	defm V_CMP_T_I32 : VOPC_I32 <vopc<0x87, 0xc7>, "v_cmp_t_i32">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	196
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	197
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	198	defm V_CMPX_F_I32 : VOPCX_I32 <vopc<0x90, 0xd0>, "v_cmpx_f_i32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	199	defm V_CMPX_LT_I32 : VOPCX_I32 <vopc<0x91, 0xd1>, "v_cmpx_lt_i32", "v_cmpx_gt_i32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	200	defm V_CMPX_EQ_I32 : VOPCX_I32 <vopc<0x92, 0xd2>, "v_cmpx_eq_i32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	201	defm V_CMPX_LE_I32 : VOPCX_I32 <vopc<0x93, 0xd3>, "v_cmpx_le_i32", "v_cmpx_ge_i32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	202	defm V_CMPX_GT_I32 : VOPCX_I32 <vopc<0x94, 0xd4>, "v_cmpx_gt_i32">;
				203	defm V_CMPX_NE_I32 : VOPCX_I32 <vopc<0x95, 0xd5>, "v_cmpx_ne_i32">;
				204	defm V_CMPX_GE_I32 : VOPCX_I32 <vopc<0x96, 0xd6>, "v_cmpx_ge_i32">;
				205	defm V_CMPX_T_I32 : VOPCX_I32 <vopc<0x97, 0xd7>, "v_cmpx_t_i32">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	206
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	207
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	208	defm V_CMP_F_I64 : VOPC_I64 <vopc<0xa0, 0xe0>, "v_cmp_f_i64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	209	defm V_CMP_LT_I64 : VOPC_I64 <vopc<0xa1, 0xe1>, "v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	210	defm V_CMP_EQ_I64 : VOPC_I64 <vopc<0xa2, 0xe2>, "v_cmp_eq_i64", COND_EQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	211	defm V_CMP_LE_I64 : VOPC_I64 <vopc<0xa3, 0xe3>, "v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	212	defm V_CMP_GT_I64 : VOPC_I64 <vopc<0xa4, 0xe4>, "v_cmp_gt_i64", COND_SGT>;
				213	defm V_CMP_NE_I64 : VOPC_I64 <vopc<0xa5, 0xe5>, "v_cmp_ne_i64", COND_NE>;
				214	defm V_CMP_GE_I64 : VOPC_I64 <vopc<0xa6, 0xe6>, "v_cmp_ge_i64", COND_SGE>;
				215	defm V_CMP_T_I64 : VOPC_I64 <vopc<0xa7, 0xe7>, "v_cmp_t_i64">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	216
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	217
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	218	defm V_CMPX_F_I64 : VOPCX_I64 <vopc<0xb0, 0xf0>, "v_cmpx_f_i64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	219	defm V_CMPX_LT_I64 : VOPCX_I64 <vopc<0xb1, 0xf1>, "v_cmpx_lt_i64", "v_cmpx_gt_i64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	220	defm V_CMPX_EQ_I64 : VOPCX_I64 <vopc<0xb2, 0xf2>, "v_cmpx_eq_i64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	221	defm V_CMPX_LE_I64 : VOPCX_I64 <vopc<0xb3, 0xf3>, "v_cmpx_le_i64", "v_cmpx_ge_i64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	222	defm V_CMPX_GT_I64 : VOPCX_I64 <vopc<0xb4, 0xf4>, "v_cmpx_gt_i64">;
				223	defm V_CMPX_NE_I64 : VOPCX_I64 <vopc<0xb5, 0xf5>, "v_cmpx_ne_i64">;
				224	defm V_CMPX_GE_I64 : VOPCX_I64 <vopc<0xb6, 0xf6>, "v_cmpx_ge_i64">;
				225	defm V_CMPX_T_I64 : VOPCX_I64 <vopc<0xb7, 0xf7>, "v_cmpx_t_i64">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	226
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	227
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	228	defm V_CMP_F_U32 : VOPC_I32 <vopc<0xc0, 0xc8>, "v_cmp_f_u32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	229	defm V_CMP_LT_U32 : VOPC_I32 <vopc<0xc1, 0xc9>, "v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	230	defm V_CMP_EQ_U32 : VOPC_I32 <vopc<0xc2, 0xca>, "v_cmp_eq_u32", COND_EQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	231	defm V_CMP_LE_U32 : VOPC_I32 <vopc<0xc3, 0xcb>, "v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	232	defm V_CMP_GT_U32 : VOPC_I32 <vopc<0xc4, 0xcc>, "v_cmp_gt_u32", COND_UGT>;
				233	defm V_CMP_NE_U32 : VOPC_I32 <vopc<0xc5, 0xcd>, "v_cmp_ne_u32", COND_NE>;
				234	defm V_CMP_GE_U32 : VOPC_I32 <vopc<0xc6, 0xce>, "v_cmp_ge_u32", COND_UGE>;
				235	defm V_CMP_T_U32 : VOPC_I32 <vopc<0xc7, 0xcf>, "v_cmp_t_u32">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	236
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	237
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	238	defm V_CMPX_F_U32 : VOPCX_I32 <vopc<0xd0, 0xd8>, "v_cmpx_f_u32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	239	defm V_CMPX_LT_U32 : VOPCX_I32 <vopc<0xd1, 0xd9>, "v_cmpx_lt_u32", "v_cmpx_gt_u32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	240	defm V_CMPX_EQ_U32 : VOPCX_I32 <vopc<0xd2, 0xda>, "v_cmpx_eq_u32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	241	defm V_CMPX_LE_U32 : VOPCX_I32 <vopc<0xd3, 0xdb>, "v_cmpx_le_u32", "v_cmpx_le_u32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	242	defm V_CMPX_GT_U32 : VOPCX_I32 <vopc<0xd4, 0xdc>, "v_cmpx_gt_u32">;
				243	defm V_CMPX_NE_U32 : VOPCX_I32 <vopc<0xd5, 0xdd>, "v_cmpx_ne_u32">;
				244	defm V_CMPX_GE_U32 : VOPCX_I32 <vopc<0xd6, 0xde>, "v_cmpx_ge_u32">;
				245	defm V_CMPX_T_U32 : VOPCX_I32 <vopc<0xd7, 0xdf>, "v_cmpx_t_u32">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	246
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	247
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	248	defm V_CMP_F_U64 : VOPC_I64 <vopc<0xe0, 0xe8>, "v_cmp_f_u64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	249	defm V_CMP_LT_U64 : VOPC_I64 <vopc<0xe1, 0xe9>, "v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	250	defm V_CMP_EQ_U64 : VOPC_I64 <vopc<0xe2, 0xea>, "v_cmp_eq_u64", COND_EQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	251	defm V_CMP_LE_U64 : VOPC_I64 <vopc<0xe3, 0xeb>, "v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	252	defm V_CMP_GT_U64 : VOPC_I64 <vopc<0xe4, 0xec>, "v_cmp_gt_u64", COND_UGT>;
				253	defm V_CMP_NE_U64 : VOPC_I64 <vopc<0xe5, 0xed>, "v_cmp_ne_u64", COND_NE>;
				254	defm V_CMP_GE_U64 : VOPC_I64 <vopc<0xe6, 0xee>, "v_cmp_ge_u64", COND_UGE>;
				255	defm V_CMP_T_U64 : VOPC_I64 <vopc<0xe7, 0xef>, "v_cmp_t_u64">;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	256
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	257	defm V_CMPX_F_U64 : VOPCX_I64 <vopc<0xf0, 0xf8>, "v_cmpx_f_u64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	258	defm V_CMPX_LT_U64 : VOPCX_I64 <vopc<0xf1, 0xf9>, "v_cmpx_lt_u64", "v_cmpx_gt_u64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	259	defm V_CMPX_EQ_U64 : VOPCX_I64 <vopc<0xf2, 0xfa>, "v_cmpx_eq_u64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	260	defm V_CMPX_LE_U64 : VOPCX_I64 <vopc<0xf3, 0xfb>, "v_cmpx_le_u64", "v_cmpx_ge_u64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	261	defm V_CMPX_GT_U64 : VOPCX_I64 <vopc<0xf4, 0xfc>, "v_cmpx_gt_u64">;
				262	defm V_CMPX_NE_U64 : VOPCX_I64 <vopc<0xf5, 0xfd>, "v_cmpx_ne_u64">;
				263	defm V_CMPX_GE_U64 : VOPCX_I64 <vopc<0xf6, 0xfe>, "v_cmpx_ge_u64">;
				264	defm V_CMPX_T_U64 : VOPCX_I64 <vopc<0xf7, 0xff>, "v_cmpx_t_u64">;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	265
Matt Arsenault	0943b0e	2015-03-23 18:45:38 +0000	[diff] [blame]	266	} // End isCompare = 1, isCommutable = 1
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	267
Matt Arsenault	4831ce5	2015-01-06 23:00:37 +0000	[diff] [blame]	268	defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <vopc<0x88, 0x10>, "v_cmp_class_f32">;
Matt Arsenault	4831ce5	2015-01-06 23:00:37 +0000	[diff] [blame]	269	defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <vopc<0x98, 0x11>, "v_cmpx_class_f32">;
Matt Arsenault	4831ce5	2015-01-06 23:00:37 +0000	[diff] [blame]	270	defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <vopc<0xa8, 0x12>, "v_cmp_class_f64">;
Matt Arsenault	4831ce5	2015-01-06 23:00:37 +0000	[diff] [blame]	271	defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <vopc<0xb8, 0x13>, "v_cmpx_class_f64">;
Matt Arsenault	42f39e1	2015-03-23 18:45:35 +0000	[diff] [blame]	272
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	273	//===----------------------------------------------------------------------===//
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	274	// MUBUF Instructions
				275	//===----------------------------------------------------------------------===//
Matt Arsenault	dd78b80	2014-03-19 22:19:56 +0000	[diff] [blame]	276
Tom Stellard	aec94b3	2015-02-27 14:59:46 +0000	[diff] [blame]	277	defm BUFFER_LOAD_FORMAT_X : MUBUF_Load_Helper <
				278	mubuf<0x00>, "buffer_load_format_x", VGPR_32
				279	>;
				280	defm BUFFER_LOAD_FORMAT_XY : MUBUF_Load_Helper <
				281	mubuf<0x01>, "buffer_load_format_xy", VReg_64
				282	>;
				283	defm BUFFER_LOAD_FORMAT_XYZ : MUBUF_Load_Helper <
				284	mubuf<0x02>, "buffer_load_format_xyz", VReg_96
				285	>;
				286	defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <
				287	mubuf<0x03>, "buffer_load_format_xyzw", VReg_128
				288	>;
Nicolai Haehnle	b48275f	2016-04-19 21:58:33 +0000	[diff] [blame]	289	defm BUFFER_STORE_FORMAT_X : MUBUF_Store_Helper <
				290	mubuf<0x04>, "buffer_store_format_x", VGPR_32
				291	>;
				292	defm BUFFER_STORE_FORMAT_XY : MUBUF_Store_Helper <
				293	mubuf<0x05>, "buffer_store_format_xy", VReg_64
				294	>;
				295	defm BUFFER_STORE_FORMAT_XYZ : MUBUF_Store_Helper <
				296	mubuf<0x06>, "buffer_store_format_xyz", VReg_96
				297	>;
				298	defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Store_Helper <
				299	mubuf<0x07>, "buffer_store_format_xyzw", VReg_128
				300	>;
Tom Stellard	7c1838d	2014-07-02 20:53:56 +0000	[diff] [blame]	301	defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <
Tom Stellard	17a0ec54	2016-07-04 20:41:48 +0000	[diff] [blame]	302	mubuf<0x08, 0x10>, "buffer_load_ubyte", VGPR_32, i32, mubuf_az_extloadi8
Tom Stellard	7c1838d	2014-07-02 20:53:56 +0000	[diff] [blame]	303	>;
				304	defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <
Tom Stellard	17a0ec54	2016-07-04 20:41:48 +0000	[diff] [blame]	305	mubuf<0x09, 0x11>, "buffer_load_sbyte", VGPR_32, i32, mubuf_sextloadi8
Tom Stellard	7c1838d	2014-07-02 20:53:56 +0000	[diff] [blame]	306	>;
				307	defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <
Tom Stellard	17a0ec54	2016-07-04 20:41:48 +0000	[diff] [blame]	308	mubuf<0x0a, 0x12>, "buffer_load_ushort", VGPR_32, i32, mubuf_az_extloadi16
Tom Stellard	7c1838d	2014-07-02 20:53:56 +0000	[diff] [blame]	309	>;
				310	defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <
Tom Stellard	17a0ec54	2016-07-04 20:41:48 +0000	[diff] [blame]	311	mubuf<0x0b, 0x13>, "buffer_load_sshort", VGPR_32, i32, mubuf_sextloadi16
Tom Stellard	7c1838d	2014-07-02 20:53:56 +0000	[diff] [blame]	312	>;
				313	defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <
Tom Stellard	a6f24c6	2015-12-15 20:55:55 +0000	[diff] [blame]	314	mubuf<0x0c, 0x14>, "buffer_load_dword", VGPR_32, i32, mubuf_load
Tom Stellard	7c1838d	2014-07-02 20:53:56 +0000	[diff] [blame]	315	>;
				316	defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <
Tom Stellard	a6f24c6	2015-12-15 20:55:55 +0000	[diff] [blame]	317	mubuf<0x0d, 0x15>, "buffer_load_dwordx2", VReg_64, v2i32, mubuf_load
Tom Stellard	7c1838d	2014-07-02 20:53:56 +0000	[diff] [blame]	318	>;
				319	defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <
Tom Stellard	a6f24c6	2015-12-15 20:55:55 +0000	[diff] [blame]	320	mubuf<0x0e, 0x17>, "buffer_load_dwordx4", VReg_128, v4i32, mubuf_load
Tom Stellard	7c1838d	2014-07-02 20:53:56 +0000	[diff] [blame]	321	>;
Tom Stellard	d3ee8c1	2013-08-16 01:12:06 +0000	[diff] [blame]	322
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	323	defm BUFFER_STORE_BYTE : MUBUF_Store_Helper <
Marek Olsak	ee98b11	2015-01-27 17:24:58 +0000	[diff] [blame]	324	mubuf<0x18>, "buffer_store_byte", VGPR_32, i32, truncstorei8_global
Tom Stellard	d3ee8c1	2013-08-16 01:12:06 +0000	[diff] [blame]	325	>;
				326
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	327	defm BUFFER_STORE_SHORT : MUBUF_Store_Helper <
Marek Olsak	ee98b11	2015-01-27 17:24:58 +0000	[diff] [blame]	328	mubuf<0x1a>, "buffer_store_short", VGPR_32, i32, truncstorei16_global
Tom Stellard	d3ee8c1	2013-08-16 01:12:06 +0000	[diff] [blame]	329	>;
Tom Stellard	754f80f	2013-04-05 23:31:51 +0000	[diff] [blame]	330
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	331	defm BUFFER_STORE_DWORD : MUBUF_Store_Helper <
Marek Olsak	ee98b11	2015-01-27 17:24:58 +0000	[diff] [blame]	332	mubuf<0x1c>, "buffer_store_dword", VGPR_32, i32, global_store
Tom Stellard	754f80f	2013-04-05 23:31:51 +0000	[diff] [blame]	333	>;
				334
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	335	defm BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
Marek Olsak	ee98b11	2015-01-27 17:24:58 +0000	[diff] [blame]	336	mubuf<0x1d>, "buffer_store_dwordx2", VReg_64, v2i32, global_store
Tom Stellard	754f80f	2013-04-05 23:31:51 +0000	[diff] [blame]	337	>;
Tom Stellard	556d9aa	2013-06-03 17:39:37 +0000	[diff] [blame]	338
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	339	defm BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
Marek Olsak	ee98b11	2015-01-27 17:24:58 +0000	[diff] [blame]	340	mubuf<0x1e, 0x1f>, "buffer_store_dwordx4", VReg_128, v4i32, global_store
Tom Stellard	556d9aa	2013-06-03 17:39:37 +0000	[diff] [blame]	341	>;
Marek Olsak	ee98b11	2015-01-27 17:24:58 +0000	[diff] [blame]	342
Aaron Watry	8114437	2014-10-17 23:33:03 +0000	[diff] [blame]	343	defm BUFFER_ATOMIC_SWAP : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	344	mubuf<0x30, 0x40>, "buffer_atomic_swap", VGPR_32, i32, atomic_swap_global
Aaron Watry	8114437	2014-10-17 23:33:03 +0000	[diff] [blame]	345	>;
Nicolai Haehnle	ad63638	2016-03-18 16:24:31 +0000	[diff] [blame]	346	defm BUFFER_ATOMIC_CMPSWAP : MUBUF_Atomic <
				347	mubuf<0x31, 0x41>, "buffer_atomic_cmpswap", VReg_64, v2i32, null_frag
				348	>;
Tom Stellard	7980fc8	2014-09-25 18:30:26 +0000	[diff] [blame]	349	defm BUFFER_ATOMIC_ADD : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	350	mubuf<0x32, 0x42>, "buffer_atomic_add", VGPR_32, i32, atomic_add_global
Tom Stellard	7980fc8	2014-09-25 18:30:26 +0000	[diff] [blame]	351	>;
Aaron Watry	328f1ba	2014-10-17 23:32:52 +0000	[diff] [blame]	352	defm BUFFER_ATOMIC_SUB : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	353	mubuf<0x33, 0x43>, "buffer_atomic_sub", VGPR_32, i32, atomic_sub_global
Aaron Watry	328f1ba	2014-10-17 23:32:52 +0000	[diff] [blame]	354	>;
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	355	//def BUFFER_ATOMIC_RSUB : MUBUF_ <mubuf<0x34>, "buffer_atomic_rsub", []>; // isn't on CI & VI
Aaron Watry	58c9992	2014-10-17 23:32:57 +0000	[diff] [blame]	356	defm BUFFER_ATOMIC_SMIN : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	357	mubuf<0x35, 0x44>, "buffer_atomic_smin", VGPR_32, i32, atomic_min_global
Aaron Watry	58c9992	2014-10-17 23:32:57 +0000	[diff] [blame]	358	>;
				359	defm BUFFER_ATOMIC_UMIN : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	360	mubuf<0x36, 0x45>, "buffer_atomic_umin", VGPR_32, i32, atomic_umin_global
Aaron Watry	58c9992	2014-10-17 23:32:57 +0000	[diff] [blame]	361	>;
Aaron Watry	29f295d	2014-10-17 23:32:56 +0000	[diff] [blame]	362	defm BUFFER_ATOMIC_SMAX : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	363	mubuf<0x37, 0x46>, "buffer_atomic_smax", VGPR_32, i32, atomic_max_global
Aaron Watry	29f295d	2014-10-17 23:32:56 +0000	[diff] [blame]	364	>;
				365	defm BUFFER_ATOMIC_UMAX : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	366	mubuf<0x38, 0x47>, "buffer_atomic_umax", VGPR_32, i32, atomic_umax_global
Aaron Watry	29f295d	2014-10-17 23:32:56 +0000	[diff] [blame]	367	>;
Aaron Watry	6212780	2014-10-17 23:32:54 +0000	[diff] [blame]	368	defm BUFFER_ATOMIC_AND : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	369	mubuf<0x39, 0x48>, "buffer_atomic_and", VGPR_32, i32, atomic_and_global
Aaron Watry	6212780	2014-10-17 23:32:54 +0000	[diff] [blame]	370	>;
Aaron Watry	8a911e6	2014-10-17 23:32:59 +0000	[diff] [blame]	371	defm BUFFER_ATOMIC_OR : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	372	mubuf<0x3a, 0x49>, "buffer_atomic_or", VGPR_32, i32, atomic_or_global
Aaron Watry	8a911e6	2014-10-17 23:32:59 +0000	[diff] [blame]	373	>;
Aaron Watry	d672ee2	2014-10-17 23:33:01 +0000	[diff] [blame]	374	defm BUFFER_ATOMIC_XOR : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	375	mubuf<0x3b, 0x4a>, "buffer_atomic_xor", VGPR_32, i32, atomic_xor_global
Aaron Watry	d672ee2	2014-10-17 23:33:01 +0000	[diff] [blame]	376	>;
Matt Arsenault	a9dbdca	2016-04-12 14:05:04 +0000	[diff] [blame]	377	defm BUFFER_ATOMIC_INC : MUBUF_Atomic <
				378	mubuf<0x3c, 0x4b>, "buffer_atomic_inc", VGPR_32, i32, atomic_inc_global
				379	>;
				380	defm BUFFER_ATOMIC_DEC : MUBUF_Atomic <
				381	mubuf<0x3d, 0x4c>, "buffer_atomic_dec", VGPR_32, i32, atomic_dec_global
				382	>;
				383
Matt Arsenault	64fa2f4	2016-04-12 14:05:11 +0000	[diff] [blame]	384	//def BUFFER_ATOMIC_FCMPSWAP : MUBUF_Atomic <mubuf<0x3e>, "buffer_atomic_fcmpswap", []>; // isn't on VI
				385	//def BUFFER_ATOMIC_FMIN : MUBUF_Atomic <mubuf<0x3f>, "buffer_atomic_fmin", []>; // isn't on VI
				386	//def BUFFER_ATOMIC_FMAX : MUBUF_Atomic <mubuf<0x40>, "buffer_atomic_fmax", []>; // isn't on VI
				387	defm BUFFER_ATOMIC_SWAP_X2 : MUBUF_Atomic <
				388	mubuf<0x50, 0x60>, "buffer_atomic_swap_x2", VReg_64, i64, atomic_swap_global
				389	>;
Tom Stellard	354a43c	2016-04-01 18:27:37 +0000	[diff] [blame]	390	defm BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_Atomic <
				391	mubuf<0x51, 0x61>, "buffer_atomic_cmpswap_x2", VReg_128, v2i64, null_frag
				392	>;
Matt Arsenault	64fa2f4	2016-04-12 14:05:11 +0000	[diff] [blame]	393	defm BUFFER_ATOMIC_ADD_X2 : MUBUF_Atomic <
				394	mubuf<0x52, 0x62>, "buffer_atomic_add_x2", VReg_64, i64, atomic_add_global
				395	>;
				396	defm BUFFER_ATOMIC_SUB_X2 : MUBUF_Atomic <
				397	mubuf<0x53, 0x63>, "buffer_atomic_sub_x2", VReg_64, i64, atomic_sub_global
				398	>;
				399	//defm BUFFER_ATOMIC_RSUB_X2 : MUBUF_Atomic <mubuf<0x54>, "buffer_atomic_rsub_x2", []>; // isn't on CI & VI
				400	defm BUFFER_ATOMIC_SMIN_X2 : MUBUF_Atomic <
				401	mubuf<0x55, 0x64>, "buffer_atomic_smin_x2", VReg_64, i64, atomic_min_global
				402	>;
				403	defm BUFFER_ATOMIC_UMIN_X2 : MUBUF_Atomic <
				404	mubuf<0x56, 0x65>, "buffer_atomic_umin_x2", VReg_64, i64, atomic_umin_global
				405	>;
				406	defm BUFFER_ATOMIC_SMAX_X2 : MUBUF_Atomic <
				407	mubuf<0x57, 0x66>, "buffer_atomic_smax_x2", VReg_64, i64, atomic_max_global
				408	>;
				409	defm BUFFER_ATOMIC_UMAX_X2 : MUBUF_Atomic <
				410	mubuf<0x58, 0x67>, "buffer_atomic_umax_x2", VReg_64, i64, atomic_umax_global
				411	>;
				412	defm BUFFER_ATOMIC_AND_X2 : MUBUF_Atomic <
				413	mubuf<0x59, 0x68>, "buffer_atomic_and_x2", VReg_64, i64, atomic_and_global
				414	>;
				415	defm BUFFER_ATOMIC_OR_X2 : MUBUF_Atomic <
				416	mubuf<0x5a, 0x69>, "buffer_atomic_or_x2", VReg_64, i64, atomic_or_global
				417	>;
				418	defm BUFFER_ATOMIC_XOR_X2 : MUBUF_Atomic <
				419	mubuf<0x5b, 0x6a>, "buffer_atomic_xor_x2", VReg_64, i64, atomic_xor_global
				420	>;
Matt Arsenault	a9dbdca	2016-04-12 14:05:04 +0000	[diff] [blame]	421	defm BUFFER_ATOMIC_INC_X2 : MUBUF_Atomic <
				422	mubuf<0x5c, 0x6b>, "buffer_atomic_inc_x2", VReg_64, i64, atomic_inc_global
				423	>;
				424	defm BUFFER_ATOMIC_DEC_X2 : MUBUF_Atomic <
				425	mubuf<0x5d, 0x6c>, "buffer_atomic_dec_x2", VReg_64, i64, atomic_dec_global
				426	>;
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	427	//def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <mubuf<0x5e>, "buffer_atomic_fcmpswap_x2", []>; // isn't on VI
				428	//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <mubuf<0x5f>, "buffer_atomic_fmin_x2", []>; // isn't on VI
				429	//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <mubuf<0x60>, "buffer_atomic_fmax_x2", []>; // isn't on VI
Matt Arsenault	d6adfb4	2015-09-24 19:52:21 +0000	[diff] [blame]	430
Tom Stellard	e1818af	2016-02-18 03:42:32 +0000	[diff] [blame]	431	let SubtargetPredicate = isSI, DisableVIDecoder = 1 in {
Matt Arsenault	d6adfb4	2015-09-24 19:52:21 +0000	[diff] [blame]	432	defm BUFFER_WBINVL1_SC : MUBUF_Invalidate <mubuf<0x70>, "buffer_wbinvl1_sc", int_amdgcn_buffer_wbinvl1_sc>; // isn't on CI & VI
				433	}
				434
				435	defm BUFFER_WBINVL1 : MUBUF_Invalidate <mubuf<0x71, 0x3e>, "buffer_wbinvl1", int_amdgcn_buffer_wbinvl1>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	436
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	437	//===----------------------------------------------------------------------===//
				438	// MTBUF Instructions
				439	//===----------------------------------------------------------------------===//
				440
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	441	//def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "tbuffer_load_format_x", []>;
				442	//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "tbuffer_load_format_xy", []>;
				443	//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "tbuffer_load_format_xyz", []>;
				444	defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "tbuffer_load_format_xyzw", VReg_128>;
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	445	defm TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "tbuffer_store_format_x", VGPR_32>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	446	defm TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "tbuffer_store_format_xy", VReg_64>;
				447	defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "tbuffer_store_format_xyz", VReg_128>;
				448	defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "tbuffer_store_format_xyzw", VReg_128>;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	449
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	450	//===----------------------------------------------------------------------===//
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	451	// VOP1 Instructions
				452	//===----------------------------------------------------------------------===//
				453
Tom Stellard	88e0b25	2015-10-06 15:57:53 +0000	[diff] [blame]	454	let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in {
				455	defm V_NOP : VOP1Inst <vop1<0x0>, "v_nop", VOP_NONE>;
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	456	}
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	457
Matthias Braun	e1a6741	2015-04-24 00:25:50 +0000	[diff] [blame]	458	let isMoveImm = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in {
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	459	defm V_MOV_B32 : VOP1Inst <vop1<0x1>, "v_mov_b32", VOP_I32_I32>;
Matt Arsenault	f273370	2014-07-30 03:18:57 +0000	[diff] [blame]	460	} // End isMoveImm = 1
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	461
Tom Stellard	fbe435d	2014-03-17 17:03:51 +0000	[diff] [blame]	462	let Uses = [EXEC] in {
				463
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	464	// FIXME: Specify SchedRW for READFIRSTLANE_B32
				465
Tom Stellard	fbe435d	2014-03-17 17:03:51 +0000	[diff] [blame]	466	def V_READFIRSTLANE_B32 : VOP1 <
				467	0x00000002,
				468	(outs SReg_32:$vdst),
Changpeng Fang	75f0968	2016-08-24 20:35:23 +0000	[diff] [blame]	469	(ins VGPR_32:$src0),
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	470	"v_readfirstlane_b32 $vdst, $src0",
Changpeng Fang	75f0968	2016-08-24 20:35:23 +0000	[diff] [blame]	471	[(set i32:$vdst, (int_amdgcn_readfirstlane i32:$src0))]
Matt Arsenault	4234542	2016-05-11 00:32:31 +0000	[diff] [blame]	472	> {
				473	let isConvergent = 1;
				474	}
Tom Stellard	fbe435d	2014-03-17 17:03:51 +0000	[diff] [blame]	475
				476	}
				477
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	478	let SchedRW = [WriteQuarterRate32] in {
				479
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	480	defm V_CVT_I32_F64 : VOP1Inst <vop1<0x3>, "v_cvt_i32_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	481	VOP_I32_F64, fp_to_sint
Niels Ole Salscheider	4715d88	2013-08-08 16:06:08 +0000	[diff] [blame]	482	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	483	defm V_CVT_F64_I32 : VOP1Inst <vop1<0x4>, "v_cvt_f64_i32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	484	VOP_F64_I32, sint_to_fp
Niels Ole Salscheider	4715d88	2013-08-08 16:06:08 +0000	[diff] [blame]	485	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	486	defm V_CVT_F32_I32 : VOP1Inst <vop1<0x5>, "v_cvt_f32_i32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	487	VOP_F32_I32, sint_to_fp
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	488	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	489	defm V_CVT_F32_U32 : VOP1Inst <vop1<0x6>, "v_cvt_f32_u32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	490	VOP_F32_I32, uint_to_fp
Tom Stellard	c932d73	2013-05-06 23:02:07 +0000	[diff] [blame]	491	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	492	defm V_CVT_U32_F32 : VOP1Inst <vop1<0x7>, "v_cvt_u32_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	493	VOP_I32_F32, fp_to_uint
Tom Stellard	73c31d5	2013-08-14 22:21:57 +0000	[diff] [blame]	494	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	495	defm V_CVT_I32_F32 : VOP1Inst <vop1<0x8>, "v_cvt_i32_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	496	VOP_I32_F32, fp_to_sint
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	497	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	498	defm V_CVT_F16_F32 : VOP1Inst <vop1<0xa>, "v_cvt_f16_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	499	VOP_I32_F32, fp_to_f16
Matt Arsenault	b0df925	2014-07-10 03:22:20 +0000	[diff] [blame]	500	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	501	defm V_CVT_F32_F16 : VOP1Inst <vop1<0xb>, "v_cvt_f32_f16",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	502	VOP_F32_I32, f16_to_fp
Matt Arsenault	b0df925	2014-07-10 03:22:20 +0000	[diff] [blame]	503	>;
Matt Arsenault	eeb2a7e	2015-01-15 23:58:35 +0000	[diff] [blame]	504	defm V_CVT_RPI_I32_F32 : VOP1Inst <vop1<0xc>, "v_cvt_rpi_i32_f32",
				505	VOP_I32_F32, cvt_rpi_i32_f32>;
				506	defm V_CVT_FLR_I32_F32 : VOP1Inst <vop1<0xd>, "v_cvt_flr_i32_f32",
				507	VOP_I32_F32, cvt_flr_i32_f32>;
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	508	defm V_CVT_OFF_F32_I4 : VOP1Inst <vop1<0x0e>, "v_cvt_off_f32_i4", VOP_F32_I32>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	509	defm V_CVT_F32_F64 : VOP1Inst <vop1<0xf>, "v_cvt_f32_f64",
Michael Kuperstein	2bc3d4d	2016-08-18 20:08:15 +0000	[diff] [blame]	510	VOP_F32_F64, fpround
Niels Ole Salscheider	719fbc9	2013-08-08 16:06:15 +0000	[diff] [blame]	511	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	512	defm V_CVT_F64_F32 : VOP1Inst <vop1<0x10>, "v_cvt_f64_f32",
Michael Kuperstein	2bc3d4d	2016-08-18 20:08:15 +0000	[diff] [blame]	513	VOP_F64_F32, fpextend
Niels Ole Salscheider	719fbc9	2013-08-08 16:06:15 +0000	[diff] [blame]	514	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	515	defm V_CVT_F32_UBYTE0 : VOP1Inst <vop1<0x11>, "v_cvt_f32_ubyte0",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	516	VOP_F32_I32, AMDGPUcvt_f32_ubyte0
Matt Arsenault	364a674	2014-06-11 17:50:44 +0000	[diff] [blame]	517	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	518	defm V_CVT_F32_UBYTE1 : VOP1Inst <vop1<0x12>, "v_cvt_f32_ubyte1",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	519	VOP_F32_I32, AMDGPUcvt_f32_ubyte1
Matt Arsenault	364a674	2014-06-11 17:50:44 +0000	[diff] [blame]	520	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	521	defm V_CVT_F32_UBYTE2 : VOP1Inst <vop1<0x13>, "v_cvt_f32_ubyte2",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	522	VOP_F32_I32, AMDGPUcvt_f32_ubyte2
Matt Arsenault	364a674	2014-06-11 17:50:44 +0000	[diff] [blame]	523	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	524	defm V_CVT_F32_UBYTE3 : VOP1Inst <vop1<0x14>, "v_cvt_f32_ubyte3",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	525	VOP_F32_I32, AMDGPUcvt_f32_ubyte3
Matt Arsenault	364a674	2014-06-11 17:50:44 +0000	[diff] [blame]	526	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	527	defm V_CVT_U32_F64 : VOP1Inst <vop1<0x15>, "v_cvt_u32_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	528	VOP_I32_F64, fp_to_uint
Matt Arsenault	c3a73c3	2014-05-22 03:20:30 +0000	[diff] [blame]	529	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	530	defm V_CVT_F64_U32 : VOP1Inst <vop1<0x16>, "v_cvt_f64_u32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	531	VOP_F64_I32, uint_to_fp
Matt Arsenault	c3a73c3	2014-05-22 03:20:30 +0000	[diff] [blame]	532	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	533
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	534	} // End SchedRW = [WriteQuarterRate32]
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	535
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	536	defm V_FRACT_F32 : VOP1Inst <vop1<0x20, 0x1b>, "v_fract_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	537	VOP_F32_F32, AMDGPUfract
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	538	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	539	defm V_TRUNC_F32 : VOP1Inst <vop1<0x21, 0x1c>, "v_trunc_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	540	VOP_F32_F32, ftrunc
Tom Stellard	9b3d253	2013-05-06 23:02:00 +0000	[diff] [blame]	541	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	542	defm V_CEIL_F32 : VOP1Inst <vop1<0x22, 0x1d>, "v_ceil_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	543	VOP_F32_F32, fceil
Michel Danzer	c3ea404	2013-02-22 11:22:49 +0000	[diff] [blame]	544	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	545	defm V_RNDNE_F32 : VOP1Inst <vop1<0x23, 0x1e>, "v_rndne_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	546	VOP_F32_F32, frint
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	547	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	548	defm V_FLOOR_F32 : VOP1Inst <vop1<0x24, 0x1f>, "v_floor_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	549	VOP_F32_F32, ffloor
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	550	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	551	defm V_EXP_F32 : VOP1Inst <vop1<0x25, 0x20>, "v_exp_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	552	VOP_F32_F32, fexp2
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	553	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	554
				555	let SchedRW = [WriteQuarterRate32] in {
				556
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	557	defm V_LOG_F32 : VOP1Inst <vop1<0x27, 0x21>, "v_log_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	558	VOP_F32_F32, flog2
Michel Danzer	349cabe	2013-02-07 14:55:16 +0000	[diff] [blame]	559	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	560	defm V_RCP_F32 : VOP1Inst <vop1<0x2a, 0x22>, "v_rcp_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	561	VOP_F32_F32, AMDGPUrcp
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	562	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	563	defm V_RCP_IFLAG_F32 : VOP1Inst <vop1<0x2b, 0x23>, "v_rcp_iflag_f32",
				564	VOP_F32_F32
Matt Arsenault	257d48d	2014-06-24 22:13:39 +0000	[diff] [blame]	565	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	566	defm V_RSQ_F32 : VOP1Inst <vop1<0x2e, 0x24>, "v_rsq_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	567	VOP_F32_F32, AMDGPUrsq
Matt Arsenault	1513046	2014-06-05 00:15:55 +0000	[diff] [blame]	568	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	569
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	570	} // End SchedRW = [WriteQuarterRate32]
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	571
				572	let SchedRW = [WriteDouble] in {
				573
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	574	defm V_RCP_F64 : VOP1Inst <vop1<0x2f, 0x25>, "v_rcp_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	575	VOP_F64_F64, AMDGPUrcp
Tom Stellard	7512c08	2013-07-12 18:14:56 +0000	[diff] [blame]	576	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	577	defm V_RSQ_F64 : VOP1Inst <vop1<0x31, 0x26>, "v_rsq_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	578	VOP_F64_F64, AMDGPUrsq
Matt Arsenault	1513046	2014-06-05 00:15:55 +0000	[diff] [blame]	579	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	580
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	581	} // End SchedRW = [WriteDouble];
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	582
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	583	defm V_SQRT_F32 : VOP1Inst <vop1<0x33, 0x27>, "v_sqrt_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	584	VOP_F32_F32, fsqrt
Tom Stellard	8ed7b45	2013-07-12 18:15:13 +0000	[diff] [blame]	585	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	586
				587	let SchedRW = [WriteDouble] in {
				588
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	589	defm V_SQRT_F64 : VOP1Inst <vop1<0x34, 0x28>, "v_sqrt_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	590	VOP_F64_F64, fsqrt
Tom Stellard	8ed7b45	2013-07-12 18:15:13 +0000	[diff] [blame]	591	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	592
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	593	} // End SchedRW = [WriteDouble]
				594
				595	let SchedRW = [WriteQuarterRate32] in {
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	596
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	597	defm V_SIN_F32 : VOP1Inst <vop1<0x35, 0x29>, "v_sin_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	598	VOP_F32_F32, AMDGPUsin
Matt Arsenault	ad14ce8	2014-07-19 18:44:39 +0000	[diff] [blame]	599	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	600	defm V_COS_F32 : VOP1Inst <vop1<0x36, 0x2a>, "v_cos_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	601	VOP_F32_F32, AMDGPUcos
Matt Arsenault	ad14ce8	2014-07-19 18:44:39 +0000	[diff] [blame]	602	>;
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	603
				604	} // End SchedRW = [WriteQuarterRate32]
				605
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	606	defm V_NOT_B32 : VOP1Inst <vop1<0x37, 0x2b>, "v_not_b32", VOP_I32_I32>;
				607	defm V_BFREV_B32 : VOP1Inst <vop1<0x38, 0x2c>, "v_bfrev_b32", VOP_I32_I32>;
				608	defm V_FFBH_U32 : VOP1Inst <vop1<0x39, 0x2d>, "v_ffbh_u32", VOP_I32_I32>;
				609	defm V_FFBL_B32 : VOP1Inst <vop1<0x3a, 0x2e>, "v_ffbl_b32", VOP_I32_I32>;
				610	defm V_FFBH_I32 : VOP1Inst <vop1<0x3b, 0x2f>, "v_ffbh_i32", VOP_I32_I32>;
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	611	defm V_FREXP_EXP_I32_F64 : VOP1Inst <vop1<0x3c,0x30>, "v_frexp_exp_i32_f64",
Matt Arsenault	2fe4fbc	2016-03-30 22:28:52 +0000	[diff] [blame]	612	VOP_I32_F64, int_amdgcn_frexp_exp
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	613	>;
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	614
				615	let SchedRW = [WriteDoubleAdd] in {
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	616	defm V_FREXP_MANT_F64 : VOP1Inst <vop1<0x3d, 0x31>, "v_frexp_mant_f64",
Matt Arsenault	b96b573	2016-03-21 16:11:05 +0000	[diff] [blame]	617	VOP_F64_F64, int_amdgcn_frexp_mant
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	618	>;
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	619
				620	defm V_FRACT_F64 : VOP1Inst <vop1<0x3e, 0x32>, "v_fract_f64",
Matt Arsenault	7401516	2016-05-28 00:19:52 +0000	[diff] [blame]	621	VOP_F64_F64, AMDGPUfract
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	622	>;
				623	} // End SchedRW = [WriteDoubleAdd]
				624
				625
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	626	defm V_FREXP_EXP_I32_F32 : VOP1Inst <vop1<0x3f, 0x33>, "v_frexp_exp_i32_f32",
Matt Arsenault	2fe4fbc	2016-03-30 22:28:52 +0000	[diff] [blame]	627	VOP_I32_F32, int_amdgcn_frexp_exp
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	628	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	629	defm V_FREXP_MANT_F32 : VOP1Inst <vop1<0x40, 0x34>, "v_frexp_mant_f32",
Matt Arsenault	b96b573	2016-03-21 16:11:05 +0000	[diff] [blame]	630	VOP_F32_F32, int_amdgcn_frexp_mant
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	631	>;
Tom Stellard	88e0b25	2015-10-06 15:57:53 +0000	[diff] [blame]	632	let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in {
Sam Kolton	3025e7f	2016-04-26 13:33:56 +0000	[diff] [blame]	633	defm V_CLREXCP : VOP1Inst <vop1<0x41,0x35>, "v_clrexcp", VOP_NO_EXT<VOP_NONE>>;
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	634	}
Matt Arsenault	fc0ad42	2015-10-07 17:46:32 +0000	[diff] [blame]	635
				636	let Uses = [M0, EXEC] in {
Matt Arsenault	cb540bc	2016-07-19 00:35:03 +0000	[diff] [blame]	637	// v_movreld_b32 is a special case because the destination output
				638	// register is really a source. It isn't actually read (but may be
				639	// written), and is only to provide the base register to start
				640	// indexing from. Tablegen seems to not let you define an implicit
				641	// virtual register output for the super register being written into,
				642	// so this must have an implicit def of the register added to it.
				643	defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42, 0x36>, "v_movreld_b32", VOP_MOVRELD>;
				644	defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43, 0x37>, "v_movrels_b32", VOP_I32_VI32_NO_EXT>;
Sam Kolton	3025e7f	2016-04-26 13:33:56 +0000	[diff] [blame]	645	defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44, 0x38>, "v_movrelsd_b32", VOP_NO_EXT<VOP_I32_I32>>;
Matt Arsenault	cb540bc	2016-07-19 00:35:03 +0000	[diff] [blame]	646
Matt Arsenault	fc0ad42	2015-10-07 17:46:32 +0000	[diff] [blame]	647	} // End Uses = [M0, EXEC]
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	648
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	649	// These instruction only exist on SI and CI
				650	let SubtargetPredicate = isSICI in {
				651
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	652	let SchedRW = [WriteQuarterRate32] in {
				653
Tom Stellard	4b3e755	2015-04-23 19:33:52 +0000	[diff] [blame]	654	defm V_MOV_FED_B32 : VOP1InstSI <vop1<0x9>, "v_mov_fed_b32", VOP_I32_I32>;
Matt Arsenault	ce56a0e	2016-02-13 01:19:56 +0000	[diff] [blame]	655	defm V_LOG_CLAMP_F32 : VOP1InstSI <vop1<0x26>, "v_log_clamp_f32",
				656	VOP_F32_F32, int_amdgcn_log_clamp>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	657	defm V_RCP_CLAMP_F32 : VOP1InstSI <vop1<0x28>, "v_rcp_clamp_f32", VOP_F32_F32>;
Matt Arsenault	32fc527	2016-07-26 16:45:45 +0000	[diff] [blame]	658	defm V_RCP_LEGACY_F32 : VOP1InstSI <vop1<0x29>, "v_rcp_legacy_f32",
				659	VOP_F32_F32, AMDGPUrcp_legacy>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	660	defm V_RSQ_CLAMP_F32 : VOP1InstSI <vop1<0x2c>, "v_rsq_clamp_f32",
Matt Arsenault	79963e8	2016-02-13 01:03:00 +0000	[diff] [blame]	661	VOP_F32_F32, AMDGPUrsq_clamp
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	662	>;
				663	defm V_RSQ_LEGACY_F32 : VOP1InstSI <vop1<0x2d>, "v_rsq_legacy_f32",
				664	VOP_F32_F32, AMDGPUrsq_legacy
				665	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	666
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	667	} // End SchedRW = [WriteQuarterRate32]
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	668
				669	let SchedRW = [WriteDouble] in {
				670
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	671	defm V_RCP_CLAMP_F64 : VOP1InstSI <vop1<0x30>, "v_rcp_clamp_f64", VOP_F64_F64>;
				672	defm V_RSQ_CLAMP_F64 : VOP1InstSI <vop1<0x32>, "v_rsq_clamp_f64",
Matt Arsenault	79963e8	2016-02-13 01:03:00 +0000	[diff] [blame]	673	VOP_F64_F64, AMDGPUrsq_clamp
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	674	>;
				675
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	676	} // End SchedRW = [WriteDouble]
				677
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	678	} // End SubtargetPredicate = isSICI
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	679
				680	//===----------------------------------------------------------------------===//
				681	// VINTRP Instructions
				682	//===----------------------------------------------------------------------===//
				683
Matt Arsenault	80f766a	2015-09-10 01:23:28 +0000	[diff] [blame]	684	let Uses = [M0, EXEC] in {
Tom Stellard	2a9d947	2015-05-12 15:00:46 +0000	[diff] [blame]	685
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	686	// FIXME: Specify SchedRW for VINTRP insturctions.
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	687
				688	multiclass V_INTERP_P1_F32_m : VINTRP_m <
				689	0x00000000,
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	690	(outs VGPR_32:$dst),
Tom Stellard	2a9d947	2015-05-12 15:00:46 +0000	[diff] [blame]	691	(ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr),
				692	"v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [m0]",
				693	[(set f32:$dst, (AMDGPUinterp_p1 i32:$i, (i32 imm:$attr_chan),
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	694	(i32 imm:$attr)))]
				695	>;
				696
				697	let OtherPredicates = [has32BankLDS] in {
				698
				699	defm V_INTERP_P1_F32 : V_INTERP_P1_F32_m;
				700
				701	} // End OtherPredicates = [has32BankLDS]
				702
Tom Stellard	e1818af	2016-02-18 03:42:32 +0000	[diff] [blame]	703	let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1 in {
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	704
				705	defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m;
				706
Tom Stellard	e1818af	2016-02-18 03:42:32 +0000	[diff] [blame]	707	} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	708
Tom Stellard	5082816	2015-05-25 16:15:56 +0000	[diff] [blame]	709	let DisableEncoding = "$src0", Constraints = "$src0 = $dst" in {
				710
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	711	defm V_INTERP_P2_F32 : VINTRP_m <
Tom Stellard	c70cf90	2015-05-25 16:15:50 +0000	[diff] [blame]	712	0x00000001,
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	713	(outs VGPR_32:$dst),
Tom Stellard	2a9d947	2015-05-12 15:00:46 +0000	[diff] [blame]	714	(ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr),
				715	"v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [m0]",
				716	[(set f32:$dst, (AMDGPUinterp_p2 f32:$src0, i32:$j, (i32 imm:$attr_chan),
Tom Stellard	5082816	2015-05-25 16:15:56 +0000	[diff] [blame]	717	(i32 imm:$attr)))]>;
				718
				719	} // End DisableEncoding = "$src0", Constraints = "$src0 = $dst"
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	720
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	721	defm V_INTERP_MOV_F32 : VINTRP_m <
Tom Stellard	c70cf90	2015-05-25 16:15:50 +0000	[diff] [blame]	722	0x00000002,
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	723	(outs VGPR_32:$dst),
Tom Stellard	2a9d947	2015-05-12 15:00:46 +0000	[diff] [blame]	724	(ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr),
				725	"v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [m0]",
				726	[(set f32:$dst, (AMDGPUinterp_mov (i32 imm:$src0), (i32 imm:$attr_chan),
				727	(i32 imm:$attr)))]>;
				728
Matt Arsenault	80f766a	2015-09-10 01:23:28 +0000	[diff] [blame]	729	} // End Uses = [M0, EXEC]
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	730
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	731	//===----------------------------------------------------------------------===//
				732	// VOP2 Instructions
				733	//===----------------------------------------------------------------------===//
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	734
Artem Tamazov	1354877	2016-06-06 15:23:43 +0000	[diff] [blame]	735	defm V_CNDMASK_B32 : VOP2eInst <vop2<0x0, 0x0>, "v_cndmask_b32",
				736	VOP2e_I32_I32_I32_I1
				737	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	738
				739	let isCommutable = 1 in {
				740	defm V_ADD_F32 : VOP2Inst <vop2<0x3, 0x1>, "v_add_f32",
				741	VOP_F32_F32_F32, fadd
				742	>;
				743
				744	defm V_SUB_F32 : VOP2Inst <vop2<0x4, 0x2>, "v_sub_f32", VOP_F32_F32_F32, fsub>;
				745	defm V_SUBREV_F32 : VOP2Inst <vop2<0x5, 0x3>, "v_subrev_f32",
				746	VOP_F32_F32_F32, null_frag, "v_sub_f32"
				747	>;
				748	} // End isCommutable = 1
				749
				750	let isCommutable = 1 in {
				751
				752	defm V_MUL_LEGACY_F32 : VOP2Inst <vop2<0x7, 0x4>, "v_mul_legacy_f32",
Matt Arsenault	32fc527	2016-07-26 16:45:45 +0000	[diff] [blame]	753	VOP_F32_F32_F32, AMDGPUfmul_legacy
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	754	>;
				755
				756	defm V_MUL_F32 : VOP2Inst <vop2<0x8, 0x5>, "v_mul_f32",
				757	VOP_F32_F32_F32, fmul
				758	>;
				759
				760	defm V_MUL_I32_I24 : VOP2Inst <vop2<0x9, 0x6>, "v_mul_i32_i24",
				761	VOP_I32_I32_I32, AMDGPUmul_i24
				762	>;
Tom Stellard	894b988	2015-02-18 16:08:14 +0000	[diff] [blame]	763
				764	defm V_MUL_HI_I32_I24 : VOP2Inst <vop2<0xa,0x7>, "v_mul_hi_i32_i24",
Matt Arsenault	2712d4a	2016-08-27 01:32:27 +0000	[diff] [blame]	765	VOP_I32_I32_I32, AMDGPUmulhi_i24
Tom Stellard	894b988	2015-02-18 16:08:14 +0000	[diff] [blame]	766	>;
				767
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	768	defm V_MUL_U32_U24 : VOP2Inst <vop2<0xb, 0x8>, "v_mul_u32_u24",
				769	VOP_I32_I32_I32, AMDGPUmul_u24
				770	>;
Tom Stellard	894b988	2015-02-18 16:08:14 +0000	[diff] [blame]	771
				772	defm V_MUL_HI_U32_U24 : VOP2Inst <vop2<0xc,0x9>, "v_mul_hi_u32_u24",
Matt Arsenault	2712d4a	2016-08-27 01:32:27 +0000	[diff] [blame]	773	VOP_I32_I32_I32, AMDGPUmulhi_u24
Tom Stellard	894b988	2015-02-18 16:08:14 +0000	[diff] [blame]	774	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	775
				776	defm V_MIN_F32 : VOP2Inst <vop2<0xf, 0xa>, "v_min_f32", VOP_F32_F32_F32,
				777	fminnum>;
				778	defm V_MAX_F32 : VOP2Inst <vop2<0x10, 0xb>, "v_max_f32", VOP_F32_F32_F32,
				779	fmaxnum>;
Marek Olsak	24ae2cd	2015-02-03 21:53:08 +0000	[diff] [blame]	780	defm V_MIN_I32 : VOP2Inst <vop2<0x11, 0xc>, "v_min_i32", VOP_I32_I32_I32>;
				781	defm V_MAX_I32 : VOP2Inst <vop2<0x12, 0xd>, "v_max_i32", VOP_I32_I32_I32>;
				782	defm V_MIN_U32 : VOP2Inst <vop2<0x13, 0xe>, "v_min_u32", VOP_I32_I32_I32>;
				783	defm V_MAX_U32 : VOP2Inst <vop2<0x14, 0xf>, "v_max_u32", VOP_I32_I32_I32>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	784
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	785	defm V_LSHRREV_B32 : VOP2Inst <
				786	vop2<0x16, 0x10>, "v_lshrrev_b32", VOP_I32_I32_I32, null_frag,
Marek Olsak	7585a29	2015-02-03 17:38:05 +0000	[diff] [blame]	787	"v_lshr_b32"
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	788	>;
				789
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	790	defm V_ASHRREV_I32 : VOP2Inst <
				791	vop2<0x18, 0x11>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag,
Marek Olsak	7585a29	2015-02-03 17:38:05 +0000	[diff] [blame]	792	"v_ashr_i32"
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	793	>;
				794
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	795	defm V_LSHLREV_B32 : VOP2Inst <
				796	vop2<0x1a, 0x12>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag,
Marek Olsak	7585a29	2015-02-03 17:38:05 +0000	[diff] [blame]	797	"v_lshl_b32"
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	798	>;
				799
Marek Olsak	24ae2cd	2015-02-03 21:53:08 +0000	[diff] [blame]	800	defm V_AND_B32 : VOP2Inst <vop2<0x1b, 0x13>, "v_and_b32", VOP_I32_I32_I32>;
				801	defm V_OR_B32 : VOP2Inst <vop2<0x1c, 0x14>, "v_or_b32", VOP_I32_I32_I32>;
				802	defm V_XOR_B32 : VOP2Inst <vop2<0x1d, 0x15>, "v_xor_b32", VOP_I32_I32_I32>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	803
Tom Stellard	cc4c871	2016-02-16 18:14:56 +0000	[diff] [blame]	804	let Constraints = "$vdst = $src2", DisableEncoding="$src2",
Tom Stellard	db5a11f	2015-07-13 15:47:57 +0000	[diff] [blame]	805	isConvertibleToThreeAddress = 1 in {
				806	defm V_MAC_F32 : VOP2Inst <vop2<0x1f, 0x16>, "v_mac_f32", VOP_MAC>;
				807	}
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	808	} // End isCommutable = 1
				809
Nikolay Haustov	6560781	2016-03-11 09:27:25 +0000	[diff] [blame]	810	defm V_MADMK_F32 : VOP2MADK <vop2<0x20, 0x17>, "v_madmk_f32", VOP_MADMK>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	811
				812	let isCommutable = 1 in {
Nikolay Haustov	6560781	2016-03-11 09:27:25 +0000	[diff] [blame]	813	defm V_MADAK_F32 : VOP2MADK <vop2<0x21, 0x18>, "v_madak_f32", VOP_MADAK>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	814	} // End isCommutable = 1
				815
Matt Arsenault	86d336e	2015-09-08 21:15:00 +0000	[diff] [blame]	816	let isCommutable = 1 in {
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	817	// No patterns so that the scalar instructions are always selected.
				818	// The scalar versions will be replaced with vector when needed later.
				819
				820	// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in VI,
				821	// but the VI instructions behave the same as the SI versions.
				822	defm V_ADD_I32 : VOP2bInst <vop2<0x25, 0x19>, "v_add_i32",
Matt Arsenault	e4d0c14	2015-08-29 07:16:50 +0000	[diff] [blame]	823	VOP2b_I32_I1_I32_I32
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	824	>;
Matt Arsenault	e4d0c14	2015-08-29 07:16:50 +0000	[diff] [blame]	825	defm V_SUB_I32 : VOP2bInst <vop2<0x26, 0x1a>, "v_sub_i32", VOP2b_I32_I1_I32_I32>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	826
				827	defm V_SUBREV_I32 : VOP2bInst <vop2<0x27, 0x1b>, "v_subrev_i32",
Matt Arsenault	e4d0c14	2015-08-29 07:16:50 +0000	[diff] [blame]	828	VOP2b_I32_I1_I32_I32, null_frag, "v_sub_i32"
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	829	>;
				830
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	831	defm V_ADDC_U32 : VOP2bInst <vop2<0x28, 0x1c>, "v_addc_u32",
Matt Arsenault	86d336e	2015-09-08 21:15:00 +0000	[diff] [blame]	832	VOP2b_I32_I1_I32_I32_I1
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	833	>;
				834	defm V_SUBB_U32 : VOP2bInst <vop2<0x29, 0x1d>, "v_subb_u32",
Matt Arsenault	86d336e	2015-09-08 21:15:00 +0000	[diff] [blame]	835	VOP2b_I32_I1_I32_I32_I1
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	836	>;
				837	defm V_SUBBREV_U32 : VOP2bInst <vop2<0x2a, 0x1e>, "v_subbrev_u32",
Matt Arsenault	86d336e	2015-09-08 21:15:00 +0000	[diff] [blame]	838	VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32"
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	839	>;
				840
Matt Arsenault	86d336e	2015-09-08 21:15:00 +0000	[diff] [blame]	841	} // End isCommutable = 1
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	842
Matt Arsenault	529cf25	2016-06-23 01:26:16 +0000	[diff] [blame]	843	// These are special and do not read the exec mask.
				844	let isConvergent = 1, Uses = []<Register> in {
Matt Arsenault	4234542	2016-05-11 00:32:31 +0000	[diff] [blame]	845
Marek Olsak	15e4a59	2015-01-15 18:42:55 +0000	[diff] [blame]	846	defm V_READLANE_B32 : VOP2SI_3VI_m <
				847	vop3 <0x001, 0x289>,
				848	"v_readlane_b32",
Tom Stellard	c149dc0	2013-11-27 21:23:35 +0000	[diff] [blame]	849	(outs SReg_32:$vdst),
Changpeng Fang	75f0968	2016-08-24 20:35:23 +0000	[diff] [blame]	850	(ins VGPR_32:$src0, SCSrc_32:$src1),
				851	"v_readlane_b32 $vdst, $src0, $src1",
				852	[(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))]
Tom Stellard	c149dc0	2013-11-27 21:23:35 +0000	[diff] [blame]	853	>;
				854
Marek Olsak	15e4a59	2015-01-15 18:42:55 +0000	[diff] [blame]	855	defm V_WRITELANE_B32 : VOP2SI_3VI_m <
				856	vop3 <0x002, 0x28a>,
				857	"v_writelane_b32",
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	858	(outs VGPR_32:$vdst),
Marek Olsak	9b8f32e	2015-02-18 22:12:45 +0000	[diff] [blame]	859	(ins SReg_32:$src0, SCSrc_32:$src1),
				860	"v_writelane_b32 $vdst, $src0, $src1"
Tom Stellard	c149dc0	2013-11-27 21:23:35 +0000	[diff] [blame]	861	>;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	862
Matt Arsenault	4234542	2016-05-11 00:32:31 +0000	[diff] [blame]	863	} // End isConvergent = 1
				864
Marek Olsak	15e4a59	2015-01-15 18:42:55 +0000	[diff] [blame]	865	// These instructions only exist on SI and CI
				866	let SubtargetPredicate = isSICI in {
				867
Tom Stellard	85656ca	2015-08-07 15:34:30 +0000	[diff] [blame]	868	let isCommutable = 1 in {
				869	defm V_MAC_LEGACY_F32 : VOP2InstSI <vop2<0x6>, "v_mac_legacy_f32",
				870	VOP_F32_F32_F32
				871	>;
				872	} // End isCommutable = 1
				873
Marek Olsak	191507e	2015-02-03 17:38:12 +0000	[diff] [blame]	874	defm V_MIN_LEGACY_F32 : VOP2InstSI <vop2<0xd>, "v_min_legacy_f32",
Matt Arsenault	da59f3d	2014-11-13 23:03:09 +0000	[diff] [blame]	875	VOP_F32_F32_F32, AMDGPUfmin_legacy
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	876	>;
Marek Olsak	191507e	2015-02-03 17:38:12 +0000	[diff] [blame]	877	defm V_MAX_LEGACY_F32 : VOP2InstSI <vop2<0xe>, "v_max_legacy_f32",
Matt Arsenault	da59f3d	2014-11-13 23:03:09 +0000	[diff] [blame]	878	VOP_F32_F32_F32, AMDGPUfmax_legacy
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	879	>;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	880
Matt Arsenault	1e3a4eb	2014-12-12 02:30:37 +0000	[diff] [blame]	881	let isCommutable = 1 in {
Marek Olsak	24ae2cd	2015-02-03 21:53:08 +0000	[diff] [blame]	882	defm V_LSHR_B32 : VOP2InstSI <vop2<0x15>, "v_lshr_b32", VOP_I32_I32_I32>;
				883	defm V_ASHR_I32 : VOP2InstSI <vop2<0x17>, "v_ashr_i32", VOP_I32_I32_I32>;
				884	defm V_LSHL_B32 : VOP2InstSI <vop2<0x19>, "v_lshl_b32", VOP_I32_I32_I32>;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	885	} // End isCommutable = 1
Marek Olsak	f0b130a	2015-01-15 18:43:06 +0000	[diff] [blame]	886	} // End let SubtargetPredicate = SICI
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	887
Marek Olsak	63a7b08	2015-03-24 13:40:21 +0000	[diff] [blame]	888	defm V_BFM_B32 : VOP2_VI3_Inst <vop23<0x1e, 0x293>, "v_bfm_b32",
				889	VOP_I32_I32_I32
Marek Olsak	f0b130a	2015-01-15 18:43:06 +0000	[diff] [blame]	890	>;
				891	defm V_BCNT_U32_B32 : VOP2_VI3_Inst <vop23<0x22, 0x28b>, "v_bcnt_u32_b32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	892	VOP_I32_I32_I32
				893	>;
Marek Olsak	f0b130a	2015-01-15 18:43:06 +0000	[diff] [blame]	894	defm V_MBCNT_LO_U32_B32 : VOP2_VI3_Inst <vop23<0x23, 0x28c>, "v_mbcnt_lo_u32_b32",
Tom Stellard	43f52df	2015-12-15 17:02:52 +0000	[diff] [blame]	895	VOP_I32_I32_I32, int_amdgcn_mbcnt_lo
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	896	>;
Marek Olsak	f0b130a	2015-01-15 18:43:06 +0000	[diff] [blame]	897	defm V_MBCNT_HI_U32_B32 : VOP2_VI3_Inst <vop23<0x24, 0x28d>, "v_mbcnt_hi_u32_b32",
Tom Stellard	43f52df	2015-12-15 17:02:52 +0000	[diff] [blame]	898	VOP_I32_I32_I32, int_amdgcn_mbcnt_hi
Marek Olsak	f0b130a	2015-01-15 18:43:06 +0000	[diff] [blame]	899	>;
				900	defm V_LDEXP_F32 : VOP2_VI3_Inst <vop23<0x2b, 0x288>, "v_ldexp_f32",
Matt Arsenault	2e7cc48	2014-08-15 17:30:25 +0000	[diff] [blame]	901	VOP_F32_F32_I32, AMDGPUldexp
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	902	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	903
Marek Olsak	11057ee	2015-02-03 17:38:01 +0000	[diff] [blame]	904	defm V_CVT_PKACCUM_U8_F32 : VOP2_VI3_Inst <vop23<0x2c, 0x1f0>, "v_cvt_pkaccum_u8_f32",
				905	VOP_I32_F32_I32>; // TODO: set "Uses = dst"
				906
				907	defm V_CVT_PKNORM_I16_F32 : VOP2_VI3_Inst <vop23<0x2d, 0x294>, "v_cvt_pknorm_i16_f32",
				908	VOP_I32_F32_F32
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	909	>;
Marek Olsak	11057ee	2015-02-03 17:38:01 +0000	[diff] [blame]	910	defm V_CVT_PKNORM_U16_F32 : VOP2_VI3_Inst <vop23<0x2e, 0x295>, "v_cvt_pknorm_u16_f32",
				911	VOP_I32_F32_F32
				912	>;
				913	defm V_CVT_PKRTZ_F16_F32 : VOP2_VI3_Inst <vop23<0x2f, 0x296>, "v_cvt_pkrtz_f16_f32",
				914	VOP_I32_F32_F32, int_SI_packf16
				915	>;
				916	defm V_CVT_PK_U16_U32 : VOP2_VI3_Inst <vop23<0x30, 0x297>, "v_cvt_pk_u16_u32",
				917	VOP_I32_I32_I32
				918	>;
				919	defm V_CVT_PK_I16_I32 : VOP2_VI3_Inst <vop23<0x31, 0x298>, "v_cvt_pk_i16_i32",
				920	VOP_I32_I32_I32
				921	>;
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	922
				923	//===----------------------------------------------------------------------===//
				924	// VOP3 Instructions
				925	//===----------------------------------------------------------------------===//
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	926
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	927	let isCommutable = 1 in {
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	928	defm V_MAD_LEGACY_F32 : VOP3Inst <vop3<0x140, 0x1c0>, "v_mad_legacy_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	929	VOP_F32_F32_F32_F32
Matt Arsenault	f37abc7	2014-05-22 17:45:20 +0000	[diff] [blame]	930	>;
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	931
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	932	defm V_MAD_F32 : VOP3Inst <vop3<0x141, 0x1c1>, "v_mad_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	933	VOP_F32_F32_F32_F32, fmad
Tom Stellard	5263948	2013-07-23 01:48:49 +0000	[diff] [blame]	934	>;
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	935
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	936	defm V_MAD_I32_I24 : VOP3Inst <vop3<0x142, 0x1c2>, "v_mad_i32_i24",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	937	VOP_I32_I32_I32_I32, AMDGPUmad_i24
				938	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	939	defm V_MAD_U32_U24 : VOP3Inst <vop3<0x143, 0x1c3>, "v_mad_u32_u24",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	940	VOP_I32_I32_I32_I32, AMDGPUmad_u24
Tom Stellard	5263948	2013-07-23 01:48:49 +0000	[diff] [blame]	941	>;
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	942	} // End isCommutable = 1
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	943
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	944	defm V_CUBEID_F32 : VOP3Inst <vop3<0x144, 0x1c4>, "v_cubeid_f32",
Matt Arsenault	051d6f9	2016-01-26 04:29:56 +0000	[diff] [blame]	945	VOP_F32_F32_F32_F32, int_amdgcn_cubeid
Niels Ole Salscheider	6509ac6	2013-08-10 10:38:47 +0000	[diff] [blame]	946	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	947	defm V_CUBESC_F32 : VOP3Inst <vop3<0x145, 0x1c5>, "v_cubesc_f32",
Matt Arsenault	051d6f9	2016-01-26 04:29:56 +0000	[diff] [blame]	948	VOP_F32_F32_F32_F32, int_amdgcn_cubesc
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	949	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	950	defm V_CUBETC_F32 : VOP3Inst <vop3<0x146, 0x1c6>, "v_cubetc_f32",
Matt Arsenault	051d6f9	2016-01-26 04:29:56 +0000	[diff] [blame]	951	VOP_F32_F32_F32_F32, int_amdgcn_cubetc
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	952	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	953	defm V_CUBEMA_F32 : VOP3Inst <vop3<0x147, 0x1c7>, "v_cubema_f32",
Matt Arsenault	051d6f9	2016-01-26 04:29:56 +0000	[diff] [blame]	954	VOP_F32_F32_F32_F32, int_amdgcn_cubema
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	955	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	956
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	957	defm V_BFE_U32 : VOP3Inst <vop3<0x148, 0x1c8>, "v_bfe_u32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	958	VOP_I32_I32_I32_I32, AMDGPUbfe_u32
				959	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	960	defm V_BFE_I32 : VOP3Inst <vop3<0x149, 0x1c9>, "v_bfe_i32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	961	VOP_I32_I32_I32_I32, AMDGPUbfe_i32
				962	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	963
				964	defm V_BFI_B32 : VOP3Inst <vop3<0x14a, 0x1ca>, "v_bfi_b32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	965	VOP_I32_I32_I32_I32, AMDGPUbfi
				966	>;
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	967
				968	let isCommutable = 1 in {
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	969	defm V_FMA_F32 : VOP3Inst <vop3<0x14b, 0x1cb>, "v_fma_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	970	VOP_F32_F32_F32_F32, fma
				971	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	972	defm V_FMA_F64 : VOP3Inst <vop3<0x14c, 0x1cc>, "v_fma_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	973	VOP_F64_F64_F64_F64, fma
Niels Ole Salscheider	6509ac6	2013-08-10 10:38:47 +0000	[diff] [blame]	974	>;
Wei Ding	5b2636a	2016-07-12 18:02:14 +0000	[diff] [blame]	975
				976	defm V_LERP_U8 : VOP3Inst <vop3<0x14d, 0x1cd>, "v_lerp_u8",
				977	VOP_I32_I32_I32_I32, int_amdgcn_lerp
				978	>;
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	979	} // End isCommutable = 1
				980
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	981	//def V_LERP_U8 : VOP3_U8 <0x0000014d, "v_lerp_u8", []>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	982	defm V_ALIGNBIT_B32 : VOP3Inst <vop3<0x14e, 0x1ce>, "v_alignbit_b32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	983	VOP_I32_I32_I32_I32
				984	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	985	defm V_ALIGNBYTE_B32 : VOP3Inst <vop3<0x14f, 0x1cf>, "v_alignbyte_b32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	986	VOP_I32_I32_I32_I32
				987	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	988
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	989	defm V_MIN3_F32 : VOP3Inst <vop3<0x151, 0x1d0>, "v_min3_f32",
Matt Arsenault	cc3c2b3	2014-11-14 20:08:52 +0000	[diff] [blame]	990	VOP_F32_F32_F32_F32, AMDGPUfmin3>;
				991
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	992	defm V_MIN3_I32 : VOP3Inst <vop3<0x152, 0x1d1>, "v_min3_i32",
Matt Arsenault	cc3c2b3	2014-11-14 20:08:52 +0000	[diff] [blame]	993	VOP_I32_I32_I32_I32, AMDGPUsmin3
				994	>;
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	995	defm V_MIN3_U32 : VOP3Inst <vop3<0x153, 0x1d2>, "v_min3_u32",
Matt Arsenault	cc3c2b3	2014-11-14 20:08:52 +0000	[diff] [blame]	996	VOP_I32_I32_I32_I32, AMDGPUumin3
				997	>;
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	998	defm V_MAX3_F32 : VOP3Inst <vop3<0x154, 0x1d3>, "v_max3_f32",
Matt Arsenault	cc3c2b3	2014-11-14 20:08:52 +0000	[diff] [blame]	999	VOP_F32_F32_F32_F32, AMDGPUfmax3
				1000	>;
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	1001	defm V_MAX3_I32 : VOP3Inst <vop3<0x155, 0x1d4>, "v_max3_i32",
Matt Arsenault	cc3c2b3	2014-11-14 20:08:52 +0000	[diff] [blame]	1002	VOP_I32_I32_I32_I32, AMDGPUsmax3
				1003	>;
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	1004	defm V_MAX3_U32 : VOP3Inst <vop3<0x156, 0x1d5>, "v_max3_u32",
Matt Arsenault	cc3c2b3	2014-11-14 20:08:52 +0000	[diff] [blame]	1005	VOP_I32_I32_I32_I32, AMDGPUumax3
				1006	>;
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	1007	defm V_MED3_F32 : VOP3Inst <vop3<0x157, 0x1d6>, "v_med3_f32",
Matt Arsenault	f639c32	2016-01-28 20:53:42 +0000	[diff] [blame]	1008	VOP_F32_F32_F32_F32, AMDGPUfmed3
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	1009	>;
				1010	defm V_MED3_I32 : VOP3Inst <vop3<0x158, 0x1d7>, "v_med3_i32",
Matt Arsenault	f639c32	2016-01-28 20:53:42 +0000	[diff] [blame]	1011	VOP_I32_I32_I32_I32, AMDGPUsmed3
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	1012	>;
				1013	defm V_MED3_U32 : VOP3Inst <vop3<0x159, 0x1d8>, "v_med3_u32",
Matt Arsenault	f639c32	2016-01-28 20:53:42 +0000	[diff] [blame]	1014	VOP_I32_I32_I32_I32, AMDGPUumed3
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	1015	>;
				1016
Wei Ding	34e1753	2016-08-11 16:33:53 +0000	[diff] [blame]	1017	defm V_SAD_U8 : VOP3Inst <vop3 <0x15a, 0x1d9>, "v_sad_u8",
				1018	VOP_I32_I32_I32_I32, int_amdgcn_sad_u8>;
				1019
				1020	defm V_SAD_HI_U8 : VOP3Inst <vop3 <0x15b, 0x1da>, "v_sad_hi_u8",
				1021	VOP_I32_I32_I32_I32, int_amdgcn_sad_hi_u8>;
				1022
				1023	defm V_SAD_U16 : VOP3Inst <vop3<0x15c, 0x1db>, "v_sad_u16",
				1024	VOP_I32_I32_I32_I32, int_amdgcn_sad_u16>;
				1025
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1026	defm V_SAD_U32 : VOP3Inst <vop3<0x15d, 0x1dc>, "v_sad_u32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1027	VOP_I32_I32_I32_I32
				1028	>;
Wei Ding	70cda07	2016-08-11 20:34:48 +0000	[diff] [blame]	1029
				1030	defm V_CVT_PK_U8_F32 : VOP3Inst<vop3<0x15e, 0x1dd>, "v_cvt_pk_u8_f32",
				1031	VOP_I32_F32_I32_I32, int_amdgcn_cvt_pk_u8_f32
				1032	>;
				1033
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1034	//def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "v_cvt_pk_u8_f32", []>;
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1035	defm V_DIV_FIXUP_F32 : VOP3Inst <
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1036	vop3<0x15f, 0x1de>, "v_div_fixup_f32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	1037	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	1038
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	1039	let SchedRW = [WriteDoubleAdd] in {
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	1040
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1041	defm V_DIV_FIXUP_F64 : VOP3Inst <
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1042	vop3<0x160, 0x1df>, "v_div_fixup_f64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	1043	>;
Tom Stellard	1cfd7a5	2013-05-20 15:02:12 +0000	[diff] [blame]	1044
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	1045	} // End SchedRW = [WriteDouble]
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	1046
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	1047	let SchedRW = [WriteDoubleAdd] in {
Tom Stellard	7512c08	2013-07-12 18:14:56 +0000	[diff] [blame]	1048	let isCommutable = 1 in {
				1049
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1050	defm V_ADD_F64 : VOP3Inst <vop3<0x164, 0x280>, "v_add_f64",
Tom Stellard	a90b952	2016-02-11 03:28:15 +0000	[diff] [blame]	1051	VOP_F64_F64_F64, fadd, 1
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1052	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1053	defm V_MUL_F64 : VOP3Inst <vop3<0x165, 0x281>, "v_mul_f64",
Tom Stellard	a90b952	2016-02-11 03:28:15 +0000	[diff] [blame]	1054	VOP_F64_F64_F64, fmul, 1
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1055	>;
Matt Arsenault	7c93690	2014-10-21 23:01:01 +0000	[diff] [blame]	1056
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1057	defm V_MIN_F64 : VOP3Inst <vop3<0x166, 0x282>, "v_min_f64",
Tom Stellard	a90b952	2016-02-11 03:28:15 +0000	[diff] [blame]	1058	VOP_F64_F64_F64, fminnum, 1
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1059	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1060	defm V_MAX_F64 : VOP3Inst <vop3<0x167, 0x283>, "v_max_f64",
Tom Stellard	a90b952	2016-02-11 03:28:15 +0000	[diff] [blame]	1061	VOP_F64_F64_F64, fmaxnum, 1
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1062	>;
Tom Stellard	7512c08	2013-07-12 18:14:56 +0000	[diff] [blame]	1063
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1064	} // End isCommutable = 1
Tom Stellard	7512c08	2013-07-12 18:14:56 +0000	[diff] [blame]	1065
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1066	defm V_LDEXP_F64 : VOP3Inst <vop3<0x168, 0x284>, "v_ldexp_f64",
Tom Stellard	a90b952	2016-02-11 03:28:15 +0000	[diff] [blame]	1067	VOP_F64_F64_I32, AMDGPUldexp, 1
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1068	>;
Christian Konig	70a5032	2013-03-27 09:12:51 +0000	[diff] [blame]	1069
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1070	} // End let SchedRW = [WriteDoubleAdd]
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	1071
				1072	let isCommutable = 1, SchedRW = [WriteQuarterRate32] in {
Christian Konig	70a5032	2013-03-27 09:12:51 +0000	[diff] [blame]	1073
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1074	defm V_MUL_LO_U32 : VOP3Inst <vop3<0x169, 0x285>, "v_mul_lo_u32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1075	VOP_I32_I32_I32
				1076	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1077	defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a, 0x286>, "v_mul_hi_u32",
Matt Arsenault	8d90302	2016-01-22 18:42:49 +0000	[diff] [blame]	1078	VOP_I32_I32_I32, mulhu
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1079	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1080
Tom Stellard	e1818af	2016-02-18 03:42:32 +0000	[diff] [blame]	1081	let DisableVIDecoder=1 in { // removed from VI as identical to V_MUL_LO_U32
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1082	defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b, 0x285>, "v_mul_lo_i32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1083	VOP_I32_I32_I32
				1084	>;
Tom Stellard	e1818af	2016-02-18 03:42:32 +0000	[diff] [blame]	1085	}
				1086
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1087	defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32",
Matt Arsenault	8d90302	2016-01-22 18:42:49 +0000	[diff] [blame]	1088	VOP_I32_I32_I32, mulhs
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1089	>;
Christian Konig	70a5032	2013-03-27 09:12:51 +0000	[diff] [blame]	1090
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1091	} // End isCommutable = 1, SchedRW = [WriteQuarterRate32]
Christian Konig	70a5032	2013-03-27 09:12:51 +0000	[diff] [blame]	1092
Matt Arsenault	6e26b8d	2015-02-14 04:03:18 +0000	[diff] [blame]	1093	let SchedRW = [WriteFloatFMA, WriteSALU] in {
Matt Arsenault	e98a074	2015-09-26 02:25:48 +0000	[diff] [blame]	1094	defm V_DIV_SCALE_F32 : VOP3bInst <vop3<0x16d, 0x1e0>, "v_div_scale_f32",
Tom Stellard	e993451	2016-02-11 18:25:26 +0000	[diff] [blame]	1095	VOP3b_F32_I1_F32_F32_F32, [], 1
Matt Arsenault	e98a074	2015-09-26 02:25:48 +0000	[diff] [blame]	1096	>;
Matt Arsenault	6e26b8d	2015-02-14 04:03:18 +0000	[diff] [blame]	1097	}
Matt Arsenault	f2b0aeb	2014-06-23 18:28:28 +0000	[diff] [blame]	1098
Matt Arsenault	6e26b8d	2015-02-14 04:03:18 +0000	[diff] [blame]	1099	let SchedRW = [WriteDouble, WriteSALU] in {
Matt Arsenault	f2b0aeb	2014-06-23 18:28:28 +0000	[diff] [blame]	1100	// Double precision division pre-scale.
Matt Arsenault	e98a074	2015-09-26 02:25:48 +0000	[diff] [blame]	1101	defm V_DIV_SCALE_F64 : VOP3bInst <vop3<0x16e, 0x1e1>, "v_div_scale_f64",
Tom Stellard	e993451	2016-02-11 18:25:26 +0000	[diff] [blame]	1102	VOP3b_F64_I1_F64_F64_F64, [], 1
Matt Arsenault	e98a074	2015-09-26 02:25:48 +0000	[diff] [blame]	1103	>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1104	} // End SchedRW = [WriteDouble]
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	1105
Matt Arsenault	80f766a	2015-09-10 01:23:28 +0000	[diff] [blame]	1106	let isCommutable = 1, Uses = [VCC, EXEC] in {
Matt Arsenault	1bc9d95	2015-02-14 04:22:00 +0000	[diff] [blame]	1107
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	1108	let SchedRW = [WriteFloatFMA] in {
Matt Arsenault	1bc9d95	2015-02-14 04:22:00 +0000	[diff] [blame]	1109	// v_div_fmas_f32:
				1110	// result = src0 * src1 + src2
				1111	// if (vcc)
				1112	// result *= 2^32
				1113	//
				1114	defm V_DIV_FMAS_F32 : VOP3_VCC_Inst <vop3<0x16f, 0x1e2>, "v_div_fmas_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1115	VOP_F32_F32_F32_F32, AMDGPUdiv_fmas
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	1116	>;
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	1117	}
Matt Arsenault	1bc9d95	2015-02-14 04:22:00 +0000	[diff] [blame]	1118
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	1119	let SchedRW = [WriteDouble] in {
Matt Arsenault	1bc9d95	2015-02-14 04:22:00 +0000	[diff] [blame]	1120	// v_div_fmas_f64:
				1121	// result = src0 * src1 + src2
				1122	// if (vcc)
				1123	// result *= 2^64
				1124	//
				1125	defm V_DIV_FMAS_F64 : VOP3_VCC_Inst <vop3<0x170, 0x1e3>, "v_div_fmas_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1126	VOP_F64_F64_F64_F64, AMDGPUdiv_fmas
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	1127	>;
Matt Arsenault	1bc9d95	2015-02-14 04:22:00 +0000	[diff] [blame]	1128
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	1129	} // End SchedRW = [WriteDouble]
Matt Arsenault	80f766a	2015-09-10 01:23:28 +0000	[diff] [blame]	1130	} // End isCommutable = 1, Uses = [VCC, EXEC]
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	1131
Wei Ding	34e1753	2016-08-11 16:33:53 +0000	[diff] [blame]	1132	defm V_MSAD_U8 : VOP3Inst <vop3<0x171, 0x1e4>, "v_msad_u8",
				1133	VOP_I32_I32_I32_I32, int_amdgcn_msad_u8>;
				1134
				1135	defm V_MQSAD_PK_U16_U8 : VOP3Inst <vop3<0x173, 0x1e6>, "v_mqsad_pk_u16_u8",
Wei Ding	52bb661	2016-08-18 19:51:14 +0000	[diff] [blame]	1136	VOP_I64_I64_I32_I64, int_amdgcn_mqsad_pk_u16_u8>;
Wei Ding	34e1753	2016-08-11 16:33:53 +0000	[diff] [blame]	1137
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	1138	//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "v_mqsad_u8", []>;
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	1139
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	1140	let SchedRW = [WriteDouble] in {
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1141	defm V_TRIG_PREOP_F64 : VOP3Inst <
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1142	vop3<0x174, 0x292>, "v_trig_preop_f64", VOP_F64_F64_I32, AMDGPUtrig_preop
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	1143	>;
Matt Arsenault	e27a41b	2013-11-18 20:09:32 +0000	[diff] [blame]	1144
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1145	} // End SchedRW = [WriteDouble]
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	1146
Marek Olsak	eae20ab	2015-01-15 18:42:40 +0000	[diff] [blame]	1147	// These instructions only exist on SI and CI
				1148	let SubtargetPredicate = isSICI in {
				1149
Marek Olsak	24ae2cd	2015-02-03 21:53:08 +0000	[diff] [blame]	1150	defm V_LSHL_B64 : VOP3Inst <vop3<0x161>, "v_lshl_b64", VOP_I64_I64_I32>;
				1151	defm V_LSHR_B64 : VOP3Inst <vop3<0x162>, "v_lshr_b64", VOP_I64_I64_I32>;
				1152	defm V_ASHR_I64 : VOP3Inst <vop3<0x163>, "v_ashr_i64", VOP_I64_I64_I32>;
Marek Olsak	eae20ab	2015-01-15 18:42:40 +0000	[diff] [blame]	1153
				1154	defm V_MULLIT_F32 : VOP3Inst <vop3<0x150>, "v_mullit_f32",
				1155	VOP_F32_F32_F32_F32>;
				1156
				1157	} // End SubtargetPredicate = isSICI
				1158
Tom Stellard	e1818af	2016-02-18 03:42:32 +0000	[diff] [blame]	1159	let SubtargetPredicate = isVI, DisableSIDecoder = 1 in {
Marek Olsak	707a6d0	2015-02-03 21:53:01 +0000	[diff] [blame]	1160
				1161	defm V_LSHLREV_B64 : VOP3Inst <vop3<0, 0x28f>, "v_lshlrev_b64",
				1162	VOP_I64_I32_I64
				1163	>;
				1164	defm V_LSHRREV_B64 : VOP3Inst <vop3<0, 0x290>, "v_lshrrev_b64",
				1165	VOP_I64_I32_I64
				1166	>;
				1167	defm V_ASHRREV_I64 : VOP3Inst <vop3<0, 0x291>, "v_ashrrev_i64",
				1168	VOP_I64_I32_I64
				1169	>;
				1170
				1171	} // End SubtargetPredicate = isVI
				1172
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	1173	//===----------------------------------------------------------------------===//
				1174	// Pseudo Instructions
				1175	//===----------------------------------------------------------------------===//
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1176
				1177	let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in {
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1178
Marek Olsak	7d77728	2015-03-24 13:40:15 +0000	[diff] [blame]	1179	// For use in patterns
Tom Stellard	cc4c871	2016-02-16 18:14:56 +0000	[diff] [blame]	1180	def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$vdst),
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1181	(ins VSrc_64:$src0, VSrc_64:$src1, SSrc_64:$src2), "", []> {
				1182	let isPseudo = 1;
				1183	let isCodeGenOnly = 1;
Matt Arsenault	22e4179	2016-08-27 01:00:37 +0000	[diff] [blame]	1184	let usesCustomInserter = 1;
Tom Stellard	60024a0	2014-09-24 01:33:24 +0000	[diff] [blame]	1185	}
				1186
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1187	// 64-bit vector move instruction. This is mainly used by the SIFoldOperands
				1188	// pass to enable folding of inline immediates.
				1189	def V_MOV_B64_PSEUDO : PseudoInstSI <(outs VReg_64:$vdst), (ins VSrc_64:$src0)> {
				1190	let VALU = 1;
				1191	}
				1192	} // End let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC]
				1193
Changpeng Fang	01f6062	2016-03-15 17:28:44 +0000	[diff] [blame]	1194	let usesCustomInserter = 1, SALU = 1 in {
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1195	def GET_GROUPSTATICSIZE : PseudoInstSI <(outs SReg_32:$sdst), (ins),
Changpeng Fang	01f6062	2016-03-15 17:28:44 +0000	[diff] [blame]	1196	[(set SReg_32:$sdst, (int_amdgcn_groupstaticsize))]>;
				1197	} // End let usesCustomInserter = 1, SALU = 1
				1198
Matt Arsenault	8fb3738	2013-10-11 21:03:36 +0000	[diff] [blame]	1199	// SI pseudo instructions. These are used by the CFG structurizer pass
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1200	// and should be lowered to ISA instructions prior to codegen.
				1201
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1202	let hasSideEffects = 1 in {
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1203
				1204	// Dummy terminator instruction to use after control flow instructions
				1205	// replaced with exec mask operations.
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1206	def SI_MASK_BRANCH : PseudoInstSI <
Matt Arsenault	f98a596	2016-08-27 00:42:21 +0000	[diff] [blame]	1207	(outs), (ins brtarget:$target)> {
Matt Arsenault	57431c9	2016-08-10 19:11:42 +0000	[diff] [blame]	1208	let isBranch = 0;
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1209	let isTerminator = 1;
Matt Arsenault	57431c9	2016-08-10 19:11:42 +0000	[diff] [blame]	1210	let isBarrier = 0;
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1211	let SALU = 1;
Matt Arsenault	78fc9da	2016-08-22 19:33:16 +0000	[diff] [blame]	1212	let Uses = [EXEC];
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1213	}
				1214
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1215	let isTerminator = 1 in {
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1216
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1217	def SI_IF: CFPseudoInstSI <
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1218	(outs SReg_64:$dst), (ins SReg_64:$vcc, brtarget:$target),
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1219	[(set i64:$dst, (int_amdgcn_if i1:$vcc, bb:$target))], 1, 1> {
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1220	let Constraints = "";
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1221	let Size = 8;
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1222	}
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1223
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1224	def SI_ELSE : CFPseudoInstSI <
				1225	(outs SReg_64:$dst), (ins SReg_64:$src, brtarget:$target, i1imm:$execfix), [], 1, 1> {
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1226	let Constraints = "$src = $dst";
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1227	let Size = 12;
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1228	}
				1229
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1230	def SI_LOOP : CFPseudoInstSI <
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1231	(outs), (ins SReg_64:$saved, brtarget:$target),
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1232	[(int_amdgcn_loop i64:$saved, bb:$target)], 1, 1> {
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1233	let Size = 8;
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1234	let isBranch = 1;
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1235	}
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1236
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1237	} // End isBranch = 1, isTerminator = 1
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1238
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1239	def SI_END_CF : CFPseudoInstSI <
				1240	(outs), (ins SReg_64:$saved),
				1241	[(int_amdgcn_end_cf i64:$saved)], 1, 1> {
				1242	let Size = 4;
				1243	}
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1244
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1245	def SI_BREAK : CFPseudoInstSI <
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1246	(outs SReg_64:$dst), (ins SReg_64:$src),
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1247	[(set i64:$dst, (int_amdgcn_break i64:$src))], 1> {
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1248	let Size = 4;
				1249	}
Matt Arsenault	48d70cb	2016-07-09 17:18:39 +0000	[diff] [blame]	1250
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1251	def SI_IF_BREAK : CFPseudoInstSI <
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1252	(outs SReg_64:$dst), (ins SReg_64:$vcc, SReg_64:$src),
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1253	[(set i64:$dst, (int_amdgcn_if_break i1:$vcc, i64:$src))]> {
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1254	let Size = 4;
				1255	}
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1256
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1257	def SI_ELSE_BREAK : CFPseudoInstSI <
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1258	(outs SReg_64:$dst), (ins SReg_64:$src0, SReg_64:$src1),
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1259	[(set i64:$dst, (int_amdgcn_else_break i64:$src0, i64:$src1))]> {
				1260	let Size = 4;
				1261	}
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1262
Tom Stellard	aa79834	2015-05-01 03:44:09 +0000	[diff] [blame]	1263	let Uses = [EXEC], Defs = [EXEC,VCC] in {
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1264	def SI_KILL : PseudoInstSI <
				1265	(outs), (ins VSrc_32:$src),
Matt Arsenault	03006fd	2016-07-19 16:27:56 +0000	[diff] [blame]	1266	[(AMDGPUkill i32:$src)]> {
Matt Arsenault	786724a	2016-07-12 21:41:32 +0000	[diff] [blame]	1267	let isConvergent = 1;
				1268	let usesCustomInserter = 1;
				1269	}
				1270
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1271	def SI_KILL_TERMINATOR : SPseudoInstSI <
Matt Arsenault	786724a	2016-07-12 21:41:32 +0000	[diff] [blame]	1272	(outs), (ins VSrc_32:$src)> {
				1273	let isTerminator = 1;
				1274	}
				1275
Tom Stellard	aa79834	2015-05-01 03:44:09 +0000	[diff] [blame]	1276	} // End Uses = [EXEC], Defs = [EXEC,VCC]
Tom Stellard	be8ebee	2013-01-18 21:15:50 +0000	[diff] [blame]	1277
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1278	} // End mayLoad = 1, mayStore = 1, hasSideEffects = 1
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1279
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1280	def SI_PS_LIVE : PseudoInstSI <
				1281	(outs SReg_64:$dst), (ins),
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1282	[(set i1:$dst, (int_amdgcn_ps_live))]> {
				1283	let SALU = 1;
				1284	}
Nicolai Haehnle	b0c9748	2016-04-22 04:04:08 +0000	[diff] [blame]	1285
Matt Arsenault	4ac341c	2016-04-14 21:58:15 +0000	[diff] [blame]	1286	// Used as an isel pseudo to directly emit initialization with an
				1287	// s_mov_b32 rather than a copy of another initialized
				1288	// register. MachineCSE skips copies, and we don't want to have to
				1289	// fold operands before it runs.
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1290	def SI_INIT_M0 : SPseudoInstSI <(outs), (ins SSrc_32:$src)> {
Matt Arsenault	4ac341c	2016-04-14 21:58:15 +0000	[diff] [blame]	1291	let Defs = [M0];
				1292	let usesCustomInserter = 1;
Matt Arsenault	4ac341c	2016-04-14 21:58:15 +0000	[diff] [blame]	1293	let isAsCheapAsAMove = 1;
Matt Arsenault	4ac341c	2016-04-14 21:58:15 +0000	[diff] [blame]	1294	let isReMaterializable = 1;
				1295	}
				1296
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1297	def SI_RETURN : SPseudoInstSI <
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1298	(outs), (ins variable_ops), [(AMDGPUreturn)]> {
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1299	let isTerminator = 1;
				1300	let isBarrier = 1;
				1301	let isReturn = 1;
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1302	let hasSideEffects = 1;
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1303	let hasNoSchedulingInfo = 1;
Nicolai Haehnle	a246dcc	2016-09-03 12:26:32 +0000	[diff] [blame]	1304	let DisableWQM = 1;
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1305	}
				1306
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1307	let Defs = [M0, EXEC],
Matt Arsenault	3cb4dde	2016-06-22 23:40:57 +0000	[diff] [blame]	1308	UseNamedOperandTable = 1 in {
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1309
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1310	class SI_INDIRECT_SRC<RegisterClass rc> : VPseudoInstSI <
Matt Arsenault	cb540bc	2016-07-19 00:35:03 +0000	[diff] [blame]	1311	(outs VGPR_32:$vdst),
				1312	(ins rc:$src, VS_32:$idx, i32imm:$offset)> {
				1313	let usesCustomInserter = 1;
				1314	}
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1315
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1316	class SI_INDIRECT_DST<RegisterClass rc> : VPseudoInstSI <
Matt Arsenault	cb540bc	2016-07-19 00:35:03 +0000	[diff] [blame]	1317	(outs rc:$vdst),
				1318	(ins rc:$src, VS_32:$idx, i32imm:$offset, VGPR_32:$val)> {
Matt Arsenault	3cb4dde	2016-06-22 23:40:57 +0000	[diff] [blame]	1319	let Constraints = "$src = $vdst";
Matt Arsenault	cb540bc	2016-07-19 00:35:03 +0000	[diff] [blame]	1320	let usesCustomInserter = 1;
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1321	}
				1322
Matt Arsenault	2841927	2015-10-07 00:42:51 +0000	[diff] [blame]	1323	// TODO: We can support indirect SGPR access.
				1324	def SI_INDIRECT_SRC_V1 : SI_INDIRECT_SRC<VGPR_32>;
				1325	def SI_INDIRECT_SRC_V2 : SI_INDIRECT_SRC<VReg_64>;
				1326	def SI_INDIRECT_SRC_V4 : SI_INDIRECT_SRC<VReg_128>;
				1327	def SI_INDIRECT_SRC_V8 : SI_INDIRECT_SRC<VReg_256>;
				1328	def SI_INDIRECT_SRC_V16 : SI_INDIRECT_SRC<VReg_512>;
				1329
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	1330	def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VGPR_32>;
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1331	def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
				1332	def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
				1333	def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
				1334	def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
				1335
Matt Arsenault	cb540bc	2016-07-19 00:35:03 +0000	[diff] [blame]	1336	} // End Uses = [EXEC], Defs = [M0, EXEC]
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1337
Tom Stellard	eba6107	2014-05-02 15:41:42 +0000	[diff] [blame]	1338	multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
Matt Arsenault	80f766a	2015-09-10 01:23:28 +0000	[diff] [blame]	1339	let UseNamedOperandTable = 1, Uses = [EXEC] in {
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1340	def _SAVE : PseudoInstSI <
Tom Stellard	42fb60e	2015-01-14 15:42:31 +0000	[diff] [blame]	1341	(outs),
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1342	(ins sgpr_class:$src, i32imm:$frame_idx)> {
Matt Arsenault	9a32cd3	2015-08-29 06:48:57 +0000	[diff] [blame]	1343	let mayStore = 1;
				1344	let mayLoad = 0;
				1345	}
Tom Stellard	eba6107	2014-05-02 15:41:42 +0000	[diff] [blame]	1346
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1347	def _RESTORE : PseudoInstSI <
Tom Stellard	42fb60e	2015-01-14 15:42:31 +0000	[diff] [blame]	1348	(outs sgpr_class:$dst),
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1349	(ins i32imm:$frame_idx)> {
Matt Arsenault	9a32cd3	2015-08-29 06:48:57 +0000	[diff] [blame]	1350	let mayStore = 0;
				1351	let mayLoad = 1;
				1352	}
Tom Stellard	42fb60e	2015-01-14 15:42:31 +0000	[diff] [blame]	1353	} // End UseNamedOperandTable = 1
Tom Stellard	eba6107	2014-05-02 15:41:42 +0000	[diff] [blame]	1354	}
				1355
Matt Arsenault	2510a31	2016-09-03 06:57:55 +0000	[diff] [blame]	1356	// You cannot use M0 as the output of v_readlane_b32 instructions or
				1357	// use it in the sdata operand of SMEM instructions. We still need to
				1358	// be able to spill the physical register m0, so allow it for
				1359	// SI_SPILL_32_* instructions.
				1360	defm SI_SPILL_S32 : SI_SPILL_SGPR <SReg_32>;
Tom Stellard	eba6107	2014-05-02 15:41:42 +0000	[diff] [blame]	1361	defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
				1362	defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
				1363	defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;
				1364	defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
				1365
Tom Stellard	9646890	2014-09-24 01:33:17 +0000	[diff] [blame]	1366	multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> {
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1367	let UseNamedOperandTable = 1, VGPRSpill = 1 in {
				1368	def _SAVE : VPseudoInstSI <
Tom Stellard	42fb60e	2015-01-14 15:42:31 +0000	[diff] [blame]	1369	(outs),
Tom Stellard	95292bb	2015-01-20 17:49:47 +0000	[diff] [blame]	1370	(ins vgpr_class:$src, i32imm:$frame_idx, SReg_128:$scratch_rsrc,
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1371	SReg_32:$scratch_offset, i32imm:$offset)> {
Matt Arsenault	9a32cd3	2015-08-29 06:48:57 +0000	[diff] [blame]	1372	let mayStore = 1;
				1373	let mayLoad = 0;
Matt Arsenault	ac42ba8	2016-09-03 17:25:44 +0000	[diff] [blame^]	1374	// (2 * 4) + (8 * num_subregs) bytes maximum
				1375	let Size = !add(!shl(!srl(vgpr_class.Size, 5), 3), 8);
Matt Arsenault	9a32cd3	2015-08-29 06:48:57 +0000	[diff] [blame]	1376	}
Tom Stellard	9646890	2014-09-24 01:33:17 +0000	[diff] [blame]	1377
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1378	def _RESTORE : VPseudoInstSI <
Tom Stellard	42fb60e	2015-01-14 15:42:31 +0000	[diff] [blame]	1379	(outs vgpr_class:$dst),
Tom Stellard	649b5db	2016-03-04 18:31:18 +0000	[diff] [blame]	1380	(ins i32imm:$frame_idx, SReg_128:$scratch_rsrc, SReg_32:$scratch_offset,
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1381	i32imm:$offset)> {
Matt Arsenault	9a32cd3	2015-08-29 06:48:57 +0000	[diff] [blame]	1382	let mayStore = 0;
				1383	let mayLoad = 1;
Matt Arsenault	ac42ba8	2016-09-03 17:25:44 +0000	[diff] [blame^]	1384
				1385	// (2 * 4) + (8 * num_subregs) bytes maximum
				1386	let Size = !add(!shl(!srl(vgpr_class.Size, 5), 3), 8);
Matt Arsenault	9a32cd3	2015-08-29 06:48:57 +0000	[diff] [blame]	1387	}
Tom Stellard	a77c3f7	2015-05-12 18:59:17 +0000	[diff] [blame]	1388	} // End UseNamedOperandTable = 1, VGPRSpill = 1
Tom Stellard	9646890	2014-09-24 01:33:17 +0000	[diff] [blame]	1389	}
				1390
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	1391	defm SI_SPILL_V32 : SI_SPILL_VGPR <VGPR_32>;
Tom Stellard	9646890	2014-09-24 01:33:17 +0000	[diff] [blame]	1392	defm SI_SPILL_V64 : SI_SPILL_VGPR <VReg_64>;
				1393	defm SI_SPILL_V96 : SI_SPILL_VGPR <VReg_96>;
				1394	defm SI_SPILL_V128 : SI_SPILL_VGPR <VReg_128>;
				1395	defm SI_SPILL_V256 : SI_SPILL_VGPR <VReg_256>;
				1396	defm SI_SPILL_V512 : SI_SPILL_VGPR <VReg_512>;
				1397
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1398	def SI_PC_ADD_REL_OFFSET : SPseudoInstSI <
Tom Stellard	067c815	2014-07-21 14:01:14 +0000	[diff] [blame]	1399	(outs SReg_64:$dst),
Tom Stellard	bf3e6e5	2016-06-14 20:29:59 +0000	[diff] [blame]	1400	(ins si_ga:$ptr),
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1401	[(set SReg_64:$dst, (i64 (SIpc_add_rel_offset (tglobaladdr:$ptr))))]> {
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1402	let Defs = [SCC];
Matt Arsenault	d092a06	2015-10-02 18:58:37 +0000	[diff] [blame]	1403	}
Tom Stellard	067c815	2014-07-21 14:01:14 +0000	[diff] [blame]	1404
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1405	} // End SubtargetPredicate = isGCN
Tom Stellard	0e70de5	2014-05-16 20:56:45 +0000	[diff] [blame]	1406
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1407	let Predicates = [isGCN] in {
Tom Stellard	0e70de5	2014-05-16 20:56:45 +0000	[diff] [blame]	1408
Nicolai Haehnle	3b57200	2016-07-28 11:39:24 +0000	[diff] [blame]	1409	def : Pat<
				1410	(int_amdgcn_else i64:$src, bb:$target),
				1411	(SI_ELSE $src, $target, 0)
				1412	>;
				1413
Tom Stellard	be8ebee	2013-01-18 21:15:50 +0000	[diff] [blame]	1414	def : Pat <
				1415	(int_AMDGPU_kilp),
Michel Danzer	9e61c4b	2014-02-27 01:47:09 +0000	[diff] [blame]	1416	(SI_KILL 0xbf800000)
Tom Stellard	be8ebee	2013-01-18 21:15:50 +0000	[diff] [blame]	1417	>;
				1418
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1419	/* int_SI_vs_load_input */
				1420	def : Pat<
Tom Stellard	bc5b537	2014-06-13 16:38:59 +0000	[diff] [blame]	1421	(SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr),
Tom Stellard	c229baa	2015-03-10 16:16:49 +0000	[diff] [blame]	1422	(BUFFER_LOAD_FORMAT_XYZW_IDXEN $buf_idx_vgpr, $tlst, 0, imm:$attr_offset, 0, 0, 0)
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1423	>;
				1424
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1425	def : Pat <
				1426	(int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1427	f32:$src0, f32:$src1, f32:$src2, f32:$src3),
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1428	(EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1429	$src0, $src1, $src2, $src3)
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1430	>;
				1431
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	1432	//===----------------------------------------------------------------------===//
Nicolai Haehnle	b142770	2016-03-10 18:43:50 +0000	[diff] [blame]	1433	// buffer_load/store_format patterns
				1434	//===----------------------------------------------------------------------===//
Nicolai Haehnle	b142770	2016-03-10 18:43:50 +0000	[diff] [blame]	1435
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1436	multiclass MUBUF_LoadIntrinsicPat<SDPatternOperator name, ValueType vt,
				1437	string opcode> {
Nicolai Haehnle	95e8ffd	2016-03-18 16:24:40 +0000	[diff] [blame]	1438	def : Pat<
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1439	(vt (name v4i32:$rsrc, 0,
				1440	(MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
				1441	imm:$glc, imm:$slc)),
Nicolai Haehnle	95e8ffd	2016-03-18 16:24:40 +0000	[diff] [blame]	1442	(!cast<MUBUF>(opcode # _OFFSET) $rsrc, $soffset, (as_i16imm $offset),
				1443	(as_i1imm $glc), (as_i1imm $slc), 0)
				1444	>;
Nicolai Haehnle	b142770	2016-03-10 18:43:50 +0000	[diff] [blame]	1445
Nicolai Haehnle	95e8ffd	2016-03-18 16:24:40 +0000	[diff] [blame]	1446	def : Pat<
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1447	(vt (name v4i32:$rsrc, i32:$vindex,
				1448	(MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
				1449	imm:$glc, imm:$slc)),
Nicolai Haehnle	95e8ffd	2016-03-18 16:24:40 +0000	[diff] [blame]	1450	(!cast<MUBUF>(opcode # _IDXEN) $vindex, $rsrc, $soffset, (as_i16imm $offset),
				1451	(as_i1imm $glc), (as_i1imm $slc), 0)
				1452	>;
Nicolai Haehnle	b142770	2016-03-10 18:43:50 +0000	[diff] [blame]	1453
Nicolai Haehnle	95e8ffd	2016-03-18 16:24:40 +0000	[diff] [blame]	1454	def : Pat<
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1455	(vt (name v4i32:$rsrc, 0,
				1456	(MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
				1457	imm:$glc, imm:$slc)),
Nicolai Haehnle	95e8ffd	2016-03-18 16:24:40 +0000	[diff] [blame]	1458	(!cast<MUBUF>(opcode # _OFFEN) $voffset, $rsrc, $soffset, (as_i16imm $offset),
				1459	(as_i1imm $glc), (as_i1imm $slc), 0)
				1460	>;
				1461
				1462	def : Pat<
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1463	(vt (name v4i32:$rsrc, i32:$vindex,
				1464	(MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
				1465	imm:$glc, imm:$slc)),
Nicolai Haehnle	95e8ffd	2016-03-18 16:24:40 +0000	[diff] [blame]	1466	(!cast<MUBUF>(opcode # _BOTHEN)
				1467	(REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
				1468	$rsrc, $soffset, (as_i16imm $offset),
				1469	(as_i1imm $glc), (as_i1imm $slc), 0)
				1470	>;
				1471	}
				1472
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1473	defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load_format, f32, "BUFFER_LOAD_FORMAT_X">;
				1474	defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load_format, v2f32, "BUFFER_LOAD_FORMAT_XY">;
				1475	defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load_format, v4f32, "BUFFER_LOAD_FORMAT_XYZW">;
				1476	defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load, f32, "BUFFER_LOAD_DWORD">;
				1477	defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load, v2f32, "BUFFER_LOAD_DWORDX2">;
				1478	defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load, v4f32, "BUFFER_LOAD_DWORDX4">;
Nicolai Haehnle	b142770	2016-03-10 18:43:50 +0000	[diff] [blame]	1479
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1480	multiclass MUBUF_StoreIntrinsicPat<SDPatternOperator name, ValueType vt,
				1481	string opcode> {
				1482	def : Pat<
				1483	(name vt:$vdata, v4i32:$rsrc, 0,
				1484	(MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
				1485	imm:$glc, imm:$slc),
Nicolai Haehnle	8a482b3	2016-08-02 19:31:14 +0000	[diff] [blame]	1486	(!cast<MUBUF>(opcode # _OFFSET_exact) $vdata, $rsrc, $soffset, (as_i16imm $offset),
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1487	(as_i1imm $glc), (as_i1imm $slc), 0)
				1488	>;
Nicolai Haehnle	b142770	2016-03-10 18:43:50 +0000	[diff] [blame]	1489
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1490	def : Pat<
				1491	(name vt:$vdata, v4i32:$rsrc, i32:$vindex,
				1492	(MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
				1493	imm:$glc, imm:$slc),
Nicolai Haehnle	8a482b3	2016-08-02 19:31:14 +0000	[diff] [blame]	1494	(!cast<MUBUF>(opcode # _IDXEN_exact) $vdata, $vindex, $rsrc, $soffset,
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1495	(as_i16imm $offset), (as_i1imm $glc),
				1496	(as_i1imm $slc), 0)
				1497	>;
Nicolai Haehnle	b142770	2016-03-10 18:43:50 +0000	[diff] [blame]	1498
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1499	def : Pat<
				1500	(name vt:$vdata, v4i32:$rsrc, 0,
				1501	(MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
				1502	imm:$glc, imm:$slc),
Nicolai Haehnle	8a482b3	2016-08-02 19:31:14 +0000	[diff] [blame]	1503	(!cast<MUBUF>(opcode # _OFFEN_exact) $vdata, $voffset, $rsrc, $soffset,
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1504	(as_i16imm $offset), (as_i1imm $glc),
				1505	(as_i1imm $slc), 0)
				1506	>;
Nicolai Haehnle	b142770	2016-03-10 18:43:50 +0000	[diff] [blame]	1507
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1508	def : Pat<
				1509	(name vt:$vdata, v4i32:$rsrc, i32:$vindex,
				1510	(MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
				1511	imm:$glc, imm:$slc),
Nicolai Haehnle	8a482b3	2016-08-02 19:31:14 +0000	[diff] [blame]	1512	(!cast<MUBUF>(opcode # _BOTHEN_exact)
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1513	$vdata,
				1514	(REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
				1515	$rsrc, $soffset, (as_i16imm $offset),
				1516	(as_i1imm $glc), (as_i1imm $slc), 0)
				1517	>;
				1518	}
				1519
				1520	defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store_format, f32, "BUFFER_STORE_FORMAT_X">;
				1521	defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store_format, v2f32, "BUFFER_STORE_FORMAT_XY">;
				1522	defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store_format, v4f32, "BUFFER_STORE_FORMAT_XYZW">;
				1523	defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store, f32, "BUFFER_STORE_DWORD">;
				1524	defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store, v2f32, "BUFFER_STORE_DWORDX2">;
				1525	defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store, v4f32, "BUFFER_STORE_DWORDX4">;
Nicolai Haehnle	b142770	2016-03-10 18:43:50 +0000	[diff] [blame]	1526
				1527	//===----------------------------------------------------------------------===//
Nicolai Haehnle	ad63638	2016-03-18 16:24:31 +0000	[diff] [blame]	1528	// buffer_atomic patterns
				1529	//===----------------------------------------------------------------------===//
				1530	multiclass BufferAtomicPatterns<SDPatternOperator name, string opcode> {
				1531	def : Pat<
				1532	(name i32:$vdata_in, v4i32:$rsrc, 0,
				1533	(MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
				1534	imm:$slc),
				1535	(!cast<MUBUF>(opcode # _RTN_OFFSET) $vdata_in, $rsrc, $soffset,
				1536	(as_i16imm $offset), (as_i1imm $slc))
				1537	>;
				1538
				1539	def : Pat<
				1540	(name i32:$vdata_in, v4i32:$rsrc, i32:$vindex,
				1541	(MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
				1542	imm:$slc),
				1543	(!cast<MUBUF>(opcode # _RTN_IDXEN) $vdata_in, $vindex, $rsrc, $soffset,
				1544	(as_i16imm $offset), (as_i1imm $slc))
				1545	>;
				1546
				1547	def : Pat<
				1548	(name i32:$vdata_in, v4i32:$rsrc, 0,
				1549	(MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
				1550	imm:$slc),
				1551	(!cast<MUBUF>(opcode # _RTN_OFFEN) $vdata_in, $voffset, $rsrc, $soffset,
				1552	(as_i16imm $offset), (as_i1imm $slc))
				1553	>;
				1554
				1555	def : Pat<
				1556	(name i32:$vdata_in, v4i32:$rsrc, i32:$vindex,
				1557	(MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
				1558	imm:$slc),
				1559	(!cast<MUBUF>(opcode # _RTN_BOTHEN)
				1560	$vdata_in,
				1561	(REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
				1562	$rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc))
				1563	>;
				1564	}
				1565
				1566	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_swap, "BUFFER_ATOMIC_SWAP">;
				1567	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_add, "BUFFER_ATOMIC_ADD">;
				1568	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_sub, "BUFFER_ATOMIC_SUB">;
				1569	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_smin, "BUFFER_ATOMIC_SMIN">;
				1570	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_umin, "BUFFER_ATOMIC_UMIN">;
				1571	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_smax, "BUFFER_ATOMIC_SMAX">;
				1572	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_umax, "BUFFER_ATOMIC_UMAX">;
				1573	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_and, "BUFFER_ATOMIC_AND">;
				1574	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_or, "BUFFER_ATOMIC_OR">;
				1575	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_xor, "BUFFER_ATOMIC_XOR">;
				1576
				1577	def : Pat<
				1578	(int_amdgcn_buffer_atomic_cmpswap
				1579	i32:$data, i32:$cmp, v4i32:$rsrc, 0,
				1580	(MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
				1581	imm:$slc),
				1582	(EXTRACT_SUBREG
				1583	(BUFFER_ATOMIC_CMPSWAP_RTN_OFFSET
				1584	(REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
				1585	$rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
				1586	sub0)
				1587	>;
				1588
				1589	def : Pat<
				1590	(int_amdgcn_buffer_atomic_cmpswap
				1591	i32:$data, i32:$cmp, v4i32:$rsrc, i32:$vindex,
				1592	(MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
				1593	imm:$slc),
				1594	(EXTRACT_SUBREG
				1595	(BUFFER_ATOMIC_CMPSWAP_RTN_IDXEN
				1596	(REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
				1597	$vindex, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
				1598	sub0)
				1599	>;
				1600
				1601	def : Pat<
				1602	(int_amdgcn_buffer_atomic_cmpswap
				1603	i32:$data, i32:$cmp, v4i32:$rsrc, 0,
				1604	(MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
				1605	imm:$slc),
				1606	(EXTRACT_SUBREG
				1607	(BUFFER_ATOMIC_CMPSWAP_RTN_OFFEN
				1608	(REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
				1609	$voffset, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
				1610	sub0)
				1611	>;
				1612
				1613	def : Pat<
				1614	(int_amdgcn_buffer_atomic_cmpswap
				1615	i32:$data, i32:$cmp, v4i32:$rsrc, i32:$vindex,
				1616	(MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
				1617	imm:$slc),
				1618	(EXTRACT_SUBREG
				1619	(BUFFER_ATOMIC_CMPSWAP_RTN_BOTHEN
				1620	(REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
				1621	(REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
				1622	$rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
				1623	sub0)
				1624	>;
				1625
Changpeng Fang	278a5b3	2016-03-10 16:47:15 +0000	[diff] [blame]	1626	//===----------------------------------------------------------------------===//
Wei Ding	07e0371	2016-07-28 16:42:13 +0000	[diff] [blame]	1627	// V_ICMPIntrinsic Pattern.
				1628	//===----------------------------------------------------------------------===//
				1629	class ICMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> : Pat <
				1630	(AMDGPUsetcc vt:$src0, vt:$src1, cond),
				1631	(inst $src0, $src1)
				1632	>;
				1633
				1634	def : ICMP_Pattern <COND_EQ, V_CMP_EQ_I32_e64, i32>;
				1635	def : ICMP_Pattern <COND_NE, V_CMP_NE_I32_e64, i32>;
				1636	def : ICMP_Pattern <COND_UGT, V_CMP_GT_U32_e64, i32>;
				1637	def : ICMP_Pattern <COND_UGE, V_CMP_GE_U32_e64, i32>;
				1638	def : ICMP_Pattern <COND_ULT, V_CMP_LT_U32_e64, i32>;
				1639	def : ICMP_Pattern <COND_ULE, V_CMP_LE_U32_e64, i32>;
				1640	def : ICMP_Pattern <COND_SGT, V_CMP_GT_I32_e64, i32>;
				1641	def : ICMP_Pattern <COND_SGE, V_CMP_GE_I32_e64, i32>;
				1642	def : ICMP_Pattern <COND_SLT, V_CMP_LT_I32_e64, i32>;
				1643	def : ICMP_Pattern <COND_SLE, V_CMP_LE_I32_e64, i32>;
				1644
				1645	def : ICMP_Pattern <COND_EQ, V_CMP_EQ_I64_e64, i64>;
				1646	def : ICMP_Pattern <COND_NE, V_CMP_NE_I64_e64, i64>;
				1647	def : ICMP_Pattern <COND_UGT, V_CMP_GT_U64_e64, i64>;
				1648	def : ICMP_Pattern <COND_UGE, V_CMP_GE_U64_e64, i64>;
				1649	def : ICMP_Pattern <COND_ULT, V_CMP_LT_U64_e64, i64>;
				1650	def : ICMP_Pattern <COND_ULE, V_CMP_LE_U64_e64, i64>;
				1651	def : ICMP_Pattern <COND_SGT, V_CMP_GT_I64_e64, i64>;
				1652	def : ICMP_Pattern <COND_SGE, V_CMP_GE_I64_e64, i64>;
				1653	def : ICMP_Pattern <COND_SLT, V_CMP_LT_I64_e64, i64>;
				1654	def : ICMP_Pattern <COND_SLE, V_CMP_LE_I64_e64, i64>;
				1655
				1656	class FCMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> : Pat <
				1657	(i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
				1658	(vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),
				1659	(inst $src0_modifiers, $src0, $src1_modifiers, $src1,
				1660	DSTCLAMP.NONE, DSTOMOD.NONE)
				1661	>;
				1662
				1663	def : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F32_e64, f32>;
				1664	def : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F32_e64, f32>;
				1665	def : FCMP_Pattern <COND_OGT, V_CMP_GT_F32_e64, f32>;
				1666	def : FCMP_Pattern <COND_OGE, V_CMP_GE_F32_e64, f32>;
				1667	def : FCMP_Pattern <COND_OLT, V_CMP_LT_F32_e64, f32>;
				1668	def : FCMP_Pattern <COND_OLE, V_CMP_LE_F32_e64, f32>;
				1669
				1670	def : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F64_e64, f64>;
				1671	def : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F64_e64, f64>;
				1672	def : FCMP_Pattern <COND_OGT, V_CMP_GT_F64_e64, f64>;
				1673	def : FCMP_Pattern <COND_OGE, V_CMP_GE_F64_e64, f64>;
				1674	def : FCMP_Pattern <COND_OLT, V_CMP_LT_F64_e64, f64>;
				1675	def : FCMP_Pattern <COND_OLE, V_CMP_LE_F64_e64, f64>;
				1676
				1677	def : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F32_e64, f32>;
				1678	def : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F32_e64, f32>;
				1679	def : FCMP_Pattern <COND_UGT, V_CMP_NLE_F32_e64, f32>;
				1680	def : FCMP_Pattern <COND_UGE, V_CMP_NLT_F32_e64, f32>;
				1681	def : FCMP_Pattern <COND_ULT, V_CMP_NGE_F32_e64, f32>;
				1682	def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F32_e64, f32>;
				1683
				1684	def : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F64_e64, f64>;
				1685	def : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F64_e64, f64>;
				1686	def : FCMP_Pattern <COND_UGT, V_CMP_NLE_F64_e64, f64>;
				1687	def : FCMP_Pattern <COND_UGE, V_CMP_NLT_F64_e64, f64>;
				1688	def : FCMP_Pattern <COND_ULT, V_CMP_NGE_F64_e64, f64>;
				1689	def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F64_e64, f64>;
Tom Stellard	a6f24c6	2015-12-15 20:55:55 +0000	[diff] [blame]	1690
Tom Stellard	ae4c9e7	2014-06-20 17:06:11 +0000	[diff] [blame]	1691	//===----------------------------------------------------------------------===//
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	1692	// VOP1 Patterns
				1693	//===----------------------------------------------------------------------===//
				1694
Matt Arsenault	22ca3f8	2014-07-15 23:50:10 +0000	[diff] [blame]	1695	let Predicates = [UnsafeFPMath] in {
Matt Arsenault	0bbcd8b	2015-02-14 04:30:08 +0000	[diff] [blame]	1696
				1697	//def : RcpPat<V_RCP_F64_e32, f64>;
				1698	//defm : RsqPat<V_RSQ_F64_e32, f64>;
				1699	//defm : RsqPat<V_RSQ_F32_e32, f32>;
				1700
				1701	def : RsqPat<V_RSQ_F32_e32, f32>;
				1702	def : RsqPat<V_RSQ_F64_e32, f64>;
Matt Arsenault	7401516	2016-05-28 00:19:52 +0000	[diff] [blame]	1703
				1704	// Convert (x - floor(x)) to fract(x)
				1705	def : Pat <
				1706	(f32 (fsub (f32 (VOP3Mods f32:$x, i32:$mods)),
				1707	(f32 (ffloor (f32 (VOP3Mods f32:$x, i32:$mods)))))),
				1708	(V_FRACT_F32_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)
				1709	>;
				1710
				1711	// Convert (x + (-floor(x))) to fract(x)
				1712	def : Pat <
				1713	(f64 (fadd (f64 (VOP3Mods f64:$x, i32:$mods)),
				1714	(f64 (fneg (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))))))),
				1715	(V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)
				1716	>;
				1717
				1718	} // End Predicates = [UnsafeFPMath]
Matt Arsenault	e9fa3b8	2014-07-15 20:18:31 +0000	[diff] [blame]	1719
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	1720	//===----------------------------------------------------------------------===//
Tom Stellard	58ac744	2014-04-29 23:12:48 +0000	[diff] [blame]	1721	// VOP2 Patterns
				1722	//===----------------------------------------------------------------------===//
				1723
Tom Stellard	ae4c9e7	2014-06-20 17:06:11 +0000	[diff] [blame]	1724	def : Pat <
				1725	(i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)),
Matt Arsenault	49dd428	2014-09-15 17:15:02 +0000	[diff] [blame]	1726	(V_BCNT_U32_B32_e64 $popcnt, $val)
Tom Stellard	ae4c9e7	2014-06-20 17:06:11 +0000	[diff] [blame]	1727	>;
				1728
Tom Stellard	5224df3	2015-03-10 16:16:44 +0000	[diff] [blame]	1729	def : Pat <
				1730	(i32 (select i1:$src0, i32:$src1, i32:$src2)),
				1731	(V_CNDMASK_B32_e64 $src2, $src1, $src0)
				1732	>;
				1733
Tom Stellard	db5a11f	2015-07-13 15:47:57 +0000	[diff] [blame]	1734	// Pattern for V_MAC_F32
				1735	def : Pat <
				1736	(fmad (VOP3NoMods0 f32:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
				1737	(VOP3NoMods f32:$src1, i32:$src1_modifiers),
				1738	(VOP3NoMods f32:$src2, i32:$src2_modifiers)),
				1739	(V_MAC_F32_e64 $src0_modifiers, $src0, $src1_modifiers, $src1,
				1740	$src2_modifiers, $src2, $clamp, $omod)
				1741	>;
				1742
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1743	/******** ============================================ ********/
				1744	/******** Extraction, Insertion, Building and Casting ********/
				1745	/******** ============================================ ********/
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1746
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1747	foreach Index = 0-2 in {
				1748	def Extract_Element_v2i32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1749	i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1750	>;
				1751	def Insert_Element_v2i32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1752	i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1753	>;
				1754
				1755	def Extract_Element_v2f32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1756	f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1757	>;
				1758	def Insert_Element_v2f32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1759	f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1760	>;
				1761	}
				1762
				1763	foreach Index = 0-3 in {
				1764	def Extract_Element_v4i32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1765	i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1766	>;
				1767	def Insert_Element_v4i32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1768	i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1769	>;
				1770
				1771	def Extract_Element_v4f32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1772	f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1773	>;
				1774	def Insert_Element_v4f32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1775	f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1776	>;
				1777	}
				1778
				1779	foreach Index = 0-7 in {
				1780	def Extract_Element_v8i32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1781	i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1782	>;
				1783	def Insert_Element_v8i32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1784	i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1785	>;
				1786
				1787	def Extract_Element_v8f32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1788	f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1789	>;
				1790	def Insert_Element_v8f32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1791	f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1792	>;
				1793	}
				1794
				1795	foreach Index = 0-15 in {
				1796	def Extract_Element_v16i32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1797	i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1798	>;
				1799	def Insert_Element_v16i32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1800	i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1801	>;
				1802
				1803	def Extract_Element_v16f32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1804	f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1805	>;
				1806	def Insert_Element_v16f32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1807	f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	1808	>;
				1809	}
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1810
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1811	// FIXME: Why do only some of these type combinations for SReg and
				1812	// VReg?
				1813	// 32-bit bitcast
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	1814	def : BitConvert <i32, f32, VGPR_32>;
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	1815	def : BitConvert <f32, i32, VGPR_32>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1816	def : BitConvert <i32, f32, SReg_32>;
				1817	def : BitConvert <f32, i32, SReg_32>;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1818
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1819	// 64-bit bitcast
Tom Stellard	7512c08	2013-07-12 18:14:56 +0000	[diff] [blame]	1820	def : BitConvert <i64, f64, VReg_64>;
Tom Stellard	7512c08	2013-07-12 18:14:56 +0000	[diff] [blame]	1821	def : BitConvert <f64, i64, VReg_64>;
Tom Stellard	ed2f614	2013-07-18 21:43:42 +0000	[diff] [blame]	1822	def : BitConvert <v2i32, v2f32, VReg_64>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1823	def : BitConvert <v2f32, v2i32, VReg_64>;
Tom Stellard	7ea3d6d	2014-03-31 14:01:55 +0000	[diff] [blame]	1824	def : BitConvert <i64, v2i32, VReg_64>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1825	def : BitConvert <v2i32, i64, VReg_64>;
Matt Arsenault	064c206	2014-06-11 17:40:32 +0000	[diff] [blame]	1826	def : BitConvert <i64, v2f32, VReg_64>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1827	def : BitConvert <v2f32, i64, VReg_64>;
Tom Stellard	8f30721	2015-12-15 17:11:17 +0000	[diff] [blame]	1828	def : BitConvert <f64, v2f32, VReg_64>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1829	def : BitConvert <v2f32, f64, VReg_64>;
Matt Arsenault	2acc7a4	2014-06-11 19:31:13 +0000	[diff] [blame]	1830	def : BitConvert <f64, v2i32, VReg_64>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1831	def : BitConvert <v2i32, f64, VReg_64>;
Tom Stellard	8374720	2013-07-18 21:43:53 +0000	[diff] [blame]	1832	def : BitConvert <v4i32, v4f32, VReg_128>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1833	def : BitConvert <v4f32, v4i32, VReg_128>;
Tom Stellard	8374720	2013-07-18 21:43:53 +0000	[diff] [blame]	1834
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1835	// 128-bit bitcast
Matt Arsenault	61001bb	2015-11-25 19:58:34 +0000	[diff] [blame]	1836	def : BitConvert <v2i64, v4i32, SReg_128>;
				1837	def : BitConvert <v4i32, v2i64, SReg_128>;
Tom Stellard	8f30721	2015-12-15 17:11:17 +0000	[diff] [blame]	1838	def : BitConvert <v2f64, v4f32, VReg_128>;
Matt Arsenault	61001bb	2015-11-25 19:58:34 +0000	[diff] [blame]	1839	def : BitConvert <v2f64, v4i32, VReg_128>;
Tom Stellard	8f30721	2015-12-15 17:11:17 +0000	[diff] [blame]	1840	def : BitConvert <v4f32, v2f64, VReg_128>;
Matt Arsenault	61001bb	2015-11-25 19:58:34 +0000	[diff] [blame]	1841	def : BitConvert <v4i32, v2f64, VReg_128>;
Matt Arsenault	e57206d	2016-05-25 18:07:36 +0000	[diff] [blame]	1842	def : BitConvert <v2i64, v2f64, VReg_128>;
				1843	def : BitConvert <v2f64, v2i64, VReg_128>;
Matt Arsenault	61001bb	2015-11-25 19:58:34 +0000	[diff] [blame]	1844
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1845	// 256-bit bitcast
Tom Stellard	967bf58	2014-02-13 23:34:15 +0000	[diff] [blame]	1846	def : BitConvert <v8i32, v8f32, SReg_256>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1847	def : BitConvert <v8f32, v8i32, SReg_256>;
Matt Arsenault	f5958dd	2014-02-02 00:05:35 +0000	[diff] [blame]	1848	def : BitConvert <v8i32, v8f32, VReg_256>;
				1849	def : BitConvert <v8f32, v8i32, VReg_256>;
Tom Stellard	20ee94f	2013-08-14 22:22:09 +0000	[diff] [blame]	1850
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1851	// 512-bit bitcast
Matt Arsenault	f5958dd	2014-02-02 00:05:35 +0000	[diff] [blame]	1852	def : BitConvert <v16i32, v16f32, VReg_512>;
				1853	def : BitConvert <v16f32, v16i32, VReg_512>;
				1854
Christian Konig	8dbe6f6	2013-02-21 15:17:27 +0000	[diff] [blame]	1855	/******** =================== ********/
				1856	/******** Src & Dst modifiers ********/
				1857	/******** =================== ********/
				1858
				1859	def : Pat <
Matt Arsenault	1cffa4c	2014-11-13 19:49:04 +0000	[diff] [blame]	1860	(AMDGPUclamp (VOP3Mods0Clamp f32:$src0, i32:$src0_modifiers, i32:$omod),
				1861	(f32 FP_ZERO), (f32 FP_ONE)),
				1862	(V_ADD_F32_e64 $src0_modifiers, $src0, 0, 0, 1, $omod)
Christian Konig	8dbe6f6	2013-02-21 15:17:27 +0000	[diff] [blame]	1863	>;
				1864
Michel Danzer	624b02a	2014-02-04 07:12:38 +0000	[diff] [blame]	1865	/******** ================================ ********/
				1866	/******** Floating point absolute/negative ********/
				1867	/******** ================================ ********/
				1868
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1869	// Prevent expanding both fneg and fabs.
Michel Danzer	624b02a	2014-02-04 07:12:38 +0000	[diff] [blame]	1870
Michel Danzer	624b02a	2014-02-04 07:12:38 +0000	[diff] [blame]	1871	def : Pat <
				1872	(fneg (fabs f32:$src)),
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1873	(S_OR_B32 $src, 0x80000000) // Set sign bit
Michel Danzer	624b02a	2014-02-04 07:12:38 +0000	[diff] [blame]	1874	>;
				1875
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1876	// FIXME: Should use S_OR_B32
Matt Arsenault	13623d0	2014-08-15 18:42:18 +0000	[diff] [blame]	1877	def : Pat <
				1878	(fneg (fabs f64:$src)),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1879	(REG_SEQUENCE VReg_64,
				1880	(i32 (EXTRACT_SUBREG f64:$src, sub0)),
				1881	sub0,
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1882	(V_OR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1883	(V_MOV_B32_e32 0x80000000)), // Set sign bit.
				1884	sub1)
Matt Arsenault	13623d0	2014-08-15 18:42:18 +0000	[diff] [blame]	1885	>;
				1886
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1887	def : Pat <
				1888	(fabs f32:$src),
				1889	(V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff))
				1890	>;
Vincent Lejeune	79a5834	2014-05-10 19:18:25 +0000	[diff] [blame]	1891
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1892	def : Pat <
				1893	(fneg f32:$src),
				1894	(V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000))
				1895	>;
Christian Konig	8dbe6f6	2013-02-21 15:17:27 +0000	[diff] [blame]	1896
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1897	def : Pat <
				1898	(fabs f64:$src),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1899	(REG_SEQUENCE VReg_64,
				1900	(i32 (EXTRACT_SUBREG f64:$src, sub0)),
				1901	sub0,
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1902	(V_AND_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1903	(V_MOV_B32_e32 0x7fffffff)), // Set sign bit.
				1904	sub1)
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1905	>;
Vincent Lejeune	79a5834	2014-05-10 19:18:25 +0000	[diff] [blame]	1906
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1907	def : Pat <
				1908	(fneg f64:$src),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1909	(REG_SEQUENCE VReg_64,
				1910	(i32 (EXTRACT_SUBREG f64:$src, sub0)),
				1911	sub0,
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1912	(V_XOR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1913	(V_MOV_B32_e32 0x80000000)),
				1914	sub1)
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	1915	>;
Christian Konig	8dbe6f6	2013-02-21 15:17:27 +0000	[diff] [blame]	1916
Christian Konig	c756cb99	2013-02-16 11:28:22 +0000	[diff] [blame]	1917	/******** ================== ********/
				1918	/******** Immediate Patterns ********/
				1919	/******** ================== ********/
				1920
				1921	def : Pat <
Tom Stellard	df94dc3	2013-08-14 23:24:24 +0000	[diff] [blame]	1922	(SGPRImm<(i32 imm)>:$imm),
				1923	(S_MOV_B32 imm:$imm)
				1924	>;
				1925
				1926	def : Pat <
				1927	(SGPRImm<(f32 fpimm)>:$imm),
Tom Stellard	fb77f00	2015-01-13 22:59:41 +0000	[diff] [blame]	1928	(S_MOV_B32 (f32 (bitcast_fpimm_to_i32 $imm)))
Tom Stellard	df94dc3	2013-08-14 23:24:24 +0000	[diff] [blame]	1929	>;
				1930
				1931	def : Pat <
Christian Konig	c756cb99	2013-02-16 11:28:22 +0000	[diff] [blame]	1932	(i32 imm:$imm),
				1933	(V_MOV_B32_e32 imm:$imm)
				1934	>;
				1935
				1936	def : Pat <
				1937	(f32 fpimm:$imm),
Tom Stellard	fb77f00	2015-01-13 22:59:41 +0000	[diff] [blame]	1938	(V_MOV_B32_e32 (f32 (bitcast_fpimm_to_i32 $imm)))
Christian Konig	c756cb99	2013-02-16 11:28:22 +0000	[diff] [blame]	1939	>;
				1940
				1941	def : Pat <
Christian Konig	b559b07	2013-02-16 11:28:36 +0000	[diff] [blame]	1942	(i64 InlineImm<i64>:$imm),
				1943	(S_MOV_B64 InlineImm<i64>:$imm)
				1944	>;
				1945
Matt Arsenault	becd656	2014-12-03 05:22:35 +0000	[diff] [blame]	1946	// XXX - Should this use a s_cmp to set SCC?
				1947
				1948	// Set to sign-extended 64-bit value (true = -1, false = 0)
				1949	def : Pat <
				1950	(i1 imm:$imm),
				1951	(S_MOV_B64 (i64 (as_i64imm $imm)))
				1952	>;
				1953
Matt Arsenault	303011a	2014-12-17 21:04:08 +0000	[diff] [blame]	1954	def : Pat <
				1955	(f64 InlineFPImm<f64>:$imm),
Tom Stellard	fb77f00	2015-01-13 22:59:41 +0000	[diff] [blame]	1956	(S_MOV_B64 (f64 (bitcast_fpimm_to_i64 InlineFPImm<f64>:$imm)))
Matt Arsenault	303011a	2014-12-17 21:04:08 +0000	[diff] [blame]	1957	>;
				1958
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1959	/******** ================== ********/
				1960	/******** Intrinsic Patterns ********/
				1961	/******** ================== ********/
				1962
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1963	def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1964
				1965	def : Pat <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1966	(int_AMDGPU_cube v4f32:$src),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1967	(REG_SEQUENCE VReg_128,
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1968	(V_CUBETC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
				1969	0 /* src1_modifiers */, (EXTRACT_SUBREG $src, sub1),
				1970	0 /* src2_modifiers */, (EXTRACT_SUBREG $src, sub2),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1971	0 /* clamp /, 0 / omod */), sub0,
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1972	(V_CUBESC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
				1973	0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
				1974	0 /* src2_modifiers */,(EXTRACT_SUBREG $src, sub2),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1975	0 /* clamp /, 0 / omod */), sub1,
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1976	(V_CUBEMA_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
				1977	0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
				1978	0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1979	0 /* clamp /, 0 / omod */), sub2,
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1980	(V_CUBEID_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
				1981	0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
				1982	0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	1983	0 /* clamp /, 0 / omod */), sub3)
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1984	>;
				1985
Michel Danzer	0cc991e	2013-02-22 11:22:58 +0000	[diff] [blame]	1986	def : Pat <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1987	(i32 (sext i1:$src0)),
				1988	(V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
Michel Danzer	0cc991e	2013-02-22 11:22:58 +0000	[diff] [blame]	1989	>;
				1990
Tom Stellard	f16d38c	2014-02-13 23:34:13 +0000	[diff] [blame]	1991	class Ext32Pat <SDNode ext> : Pat <
				1992	(i32 (ext i1:$src0)),
Michel Danzer	5d26fdf	2014-02-05 09:48:05 +0000	[diff] [blame]	1993	(V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
				1994	>;
				1995
Tom Stellard	f16d38c	2014-02-13 23:34:13 +0000	[diff] [blame]	1996	def : Ext32Pat <zext>;
				1997	def : Ext32Pat <anyext>;
				1998
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1999	// Offset in an 32-bit VGPR
Christian Konig	7a14a47	2013-03-18 11:34:00 +0000	[diff] [blame]	2000	def : Pat <
Tom Stellard	868fd92	2014-04-17 21:00:11 +0000	[diff] [blame]	2001	(SIload_constant v4i32:$sbase, i32:$voff),
Tom Stellard	c229baa	2015-03-10 16:16:49 +0000	[diff] [blame]	2002	(BUFFER_LOAD_DWORD_OFFEN $voff, $sbase, 0, 0, 0, 0, 0)
Christian Konig	7a14a47	2013-03-18 11:34:00 +0000	[diff] [blame]	2003	>;
				2004
Michel Danzer	8caa904	2013-04-10 17:17:56 +0000	[diff] [blame]	2005	// The multiplication scales from [0,1] to the unsigned integer range
				2006	def : Pat <
				2007	(AMDGPUurecip i32:$src0),
				2008	(V_CVT_U32_F32_e32
				2009	(V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
				2010	(V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
				2011	>;
				2012
Tom Stellard	0289ff4	2014-05-16 20:56:44 +0000	[diff] [blame]	2013	//===----------------------------------------------------------------------===//
				2014	// VOP3 Patterns
				2015	//===----------------------------------------------------------------------===//
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	2016
Matt Arsenault	eb26020	2014-05-22 18:00:15 +0000	[diff] [blame]	2017	def : IMad24Pat<V_MAD_I32_I24>;
				2018	def : UMad24Pat<V_MAD_U32_U24>;
				2019
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2020	defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>;
Tom Stellard	0289ff4	2014-05-16 20:56:44 +0000	[diff] [blame]	2021	def : ROTRPattern <V_ALIGNBIT_B32>;
				2022
Tom Stellard	556d9aa	2013-06-03 17:39:37 +0000	[diff] [blame]	2023	//===----------------------------------------------------------------------===//
				2024	// MUBUF Patterns
				2025	//===----------------------------------------------------------------------===//
				2026
Jan Vesely	43b7b5b	2016-04-07 19:23:11 +0000	[diff] [blame]	2027	class MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
				2028	PatFrag constant_ld> : Pat <
Tom Stellard	1f9939f	2015-02-27 14:59:41 +0000	[diff] [blame]	2029	(vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
				2030	i16:$offset, i1:$glc, i1:$slc, i1:$tfe))),
Tom Stellard	c229baa	2015-03-10 16:16:49 +0000	[diff] [blame]	2031	(Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, $glc, $slc, $tfe)
Tom Stellard	07a10a3	2013-06-03 17:39:43 +0000	[diff] [blame]	2032	>;
Jan Vesely	43b7b5b	2016-04-07 19:23:11 +0000	[diff] [blame]	2033
				2034	multiclass MUBUFLoad_Atomic_Pattern <MUBUF Instr_ADDR64, MUBUF Instr_OFFSET,
				2035	ValueType vt, PatFrag atomic_ld> {
				2036	def : Pat <
				2037	(vt (atomic_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
				2038	i16:$offset, i1:$slc))),
				2039	(Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, 1, $slc, 0)
				2040	>;
				2041
				2042	def : Pat <
				2043	(vt (atomic_ld (MUBUFOffsetNoGLC v4i32:$rsrc, i32:$soffset, i16:$offset))),
				2044	(Instr_OFFSET $rsrc, $soffset, (as_i16imm $offset), 1, 0, 0)
				2045	>;
Tom Stellard	07a10a3	2013-06-03 17:39:43 +0000	[diff] [blame]	2046	}
				2047
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	2048	let Predicates = [isSICI] in {
Jan Vesely	43b7b5b	2016-04-07 19:23:11 +0000	[diff] [blame]	2049	def : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>;
				2050	def : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>;
				2051	def : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>;
				2052	def : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>;
				2053
				2054	defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORD_ADDR64, BUFFER_LOAD_DWORD_OFFSET, i32, mubuf_load_atomic>;
				2055	defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, BUFFER_LOAD_DWORDX2_OFFSET, i64, mubuf_load_atomic>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	2056	} // End Predicates = [isSICI]
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	2057
				2058	class MUBUFScratchLoadPat <MUBUF Instr, ValueType vt, PatFrag ld> : Pat <
				2059	(vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr,
				2060	i32:$soffset, u16imm:$offset))),
Tom Stellard	c229baa	2015-03-10 16:16:49 +0000	[diff] [blame]	2061	(Instr $vaddr, $srsrc, $soffset, $offset, 0, 0, 0)
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	2062	>;
				2063
				2064	def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i32, sextloadi8_private>;
				2065	def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i32, extloadi8_private>;
				2066	def : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, i32, sextloadi16_private>;
				2067	def : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, i32, extloadi16_private>;
				2068	def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORD_OFFEN, i32, load_private>;
				2069	def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, v2i32, load_private>;
				2070	def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, v4i32, load_private>;
Tom Stellard	07a10a3	2013-06-03 17:39:43 +0000	[diff] [blame]	2071
Michel Danzer	1373622	2014-01-27 07:20:51 +0000	[diff] [blame]	2072	// BUFFER_LOAD_DWORD*, addr64=0
				2073	multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
				2074	MUBUF bothen> {
				2075
				2076	def : Pat <
Tom Stellard	8e44d94	2014-07-21 15:44:55 +0000	[diff] [blame]	2077	(vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset,
Michel Danzer	1373622	2014-01-27 07:20:51 +0000	[diff] [blame]	2078	imm:$offset, 0, 0, imm:$glc, imm:$slc,
				2079	imm:$tfe)),
Tom Stellard	49282c9	2015-02-27 14:59:44 +0000	[diff] [blame]	2080	(offset $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc),
Michel Danzer	1373622	2014-01-27 07:20:51 +0000	[diff] [blame]	2081	(as_i1imm $slc), (as_i1imm $tfe))
				2082	>;
				2083
				2084	def : Pat <
Tom Stellard	868fd92	2014-04-17 21:00:11 +0000	[diff] [blame]	2085	(vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	2086	imm:$offset, 1, 0, imm:$glc, imm:$slc,
Michel Danzer	1373622	2014-01-27 07:20:51 +0000	[diff] [blame]	2087	imm:$tfe)),
Tom Stellard	c229baa	2015-03-10 16:16:49 +0000	[diff] [blame]	2088	(offen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
Michel Danzer	1373622	2014-01-27 07:20:51 +0000	[diff] [blame]	2089	(as_i1imm $tfe))
				2090	>;
				2091
				2092	def : Pat <
Tom Stellard	868fd92	2014-04-17 21:00:11 +0000	[diff] [blame]	2093	(vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
Michel Danzer	1373622	2014-01-27 07:20:51 +0000	[diff] [blame]	2094	imm:$offset, 0, 1, imm:$glc, imm:$slc,
				2095	imm:$tfe)),
Tom Stellard	c229baa	2015-03-10 16:16:49 +0000	[diff] [blame]	2096	(idxen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc),
Michel Danzer	1373622	2014-01-27 07:20:51 +0000	[diff] [blame]	2097	(as_i1imm $slc), (as_i1imm $tfe))
				2098	>;
				2099
				2100	def : Pat <
Tom Stellard	868fd92	2014-04-17 21:00:11 +0000	[diff] [blame]	2101	(vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset,
Matt Arsenault	caa1288	2015-02-18 02:04:38 +0000	[diff] [blame]	2102	imm:$offset, 1, 1, imm:$glc, imm:$slc,
Michel Danzer	1373622	2014-01-27 07:20:51 +0000	[diff] [blame]	2103	imm:$tfe)),
Tom Stellard	c229baa	2015-03-10 16:16:49 +0000	[diff] [blame]	2104	(bothen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
Michel Danzer	1373622	2014-01-27 07:20:51 +0000	[diff] [blame]	2105	(as_i1imm $tfe))
				2106	>;
				2107	}
				2108
				2109	defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
				2110	BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
				2111	defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
				2112	BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
				2113	defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
				2114	BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
				2115
Jan Vesely	43b7b5b	2016-04-07 19:23:11 +0000	[diff] [blame]	2116	multiclass MUBUFStore_Atomic_Pattern <MUBUF Instr_ADDR64, MUBUF Instr_OFFSET,
				2117	ValueType vt, PatFrag atomic_st> {
				2118	// Store follows atomic op convention so address is forst
				2119	def : Pat <
				2120	(atomic_st (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
				2121	i16:$offset, i1:$slc), vt:$val),
				2122	(Instr_ADDR64 $val, $vaddr, $srsrc, $soffset, $offset, 1, $slc, 0)
				2123	>;
				2124
				2125	def : Pat <
				2126	(atomic_st (MUBUFOffsetNoGLC v4i32:$rsrc, i32:$soffset, i16:$offset), vt:$val),
				2127	(Instr_OFFSET $val, $rsrc, $soffset, (as_i16imm $offset), 1, 0, 0)
				2128	>;
				2129	}
				2130	let Predicates = [isSICI] in {
				2131	defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORD_ADDR64, BUFFER_STORE_DWORD_OFFSET, i32, global_store_atomic>;
				2132	defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORDX2_ADDR64, BUFFER_STORE_DWORDX2_OFFSET, i64, global_store_atomic>;
				2133	} // End Predicates = [isSICI]
				2134
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	2135	class MUBUFScratchStorePat <MUBUF Instr, ValueType vt, PatFrag st> : Pat <
Tom Stellard	ddea486	2014-08-11 22:18:14 +0000	[diff] [blame]	2136	(st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset,
				2137	u16imm:$offset)),
Tom Stellard	c229baa	2015-03-10 16:16:49 +0000	[diff] [blame]	2138	(Instr $value, $vaddr, $srsrc, $soffset, $offset, 0, 0, 0)
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	2139	>;
				2140
Tom Stellard	ddea486	2014-08-11 22:18:14 +0000	[diff] [blame]	2141	def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i32, truncstorei8_private>;
				2142	def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i32, truncstorei16_private>;
				2143	def : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, i32, store_private>;
				2144	def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, v2i32, store_private>;
				2145	def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, v4i32, store_private>;
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	2146
Tom Stellard	afcf12f	2013-09-12 02:55:14 +0000	[diff] [blame]	2147	//===----------------------------------------------------------------------===//
				2148	// MTBUF Patterns
				2149	//===----------------------------------------------------------------------===//
				2150
				2151	// TBUFFER_STORE_FORMAT_*, addr64=0
				2152	class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
Tom Stellard	868fd92	2014-04-17 21:00:11 +0000	[diff] [blame]	2153	(SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
Tom Stellard	afcf12f	2013-09-12 02:55:14 +0000	[diff] [blame]	2154	i32:$soffset, imm:$inst_offset, imm:$dfmt,
				2155	imm:$nfmt, imm:$offen, imm:$idxen,
				2156	imm:$glc, imm:$slc, imm:$tfe),
				2157	(opcode
				2158	$vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
				2159	(as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
				2160	(as_i1imm $slc), (as_i1imm $tfe), $soffset)
				2161	>;
				2162
				2163	def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
				2164	def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
				2165	def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
				2166	def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
				2167
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	2168	/******** ====================== ********/
				2169	/******** Indirect adressing ********/
				2170	/******** ====================== ********/
				2171
Matt Arsenault	2841927	2015-10-07 00:42:51 +0000	[diff] [blame]	2172	multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, string VecSize> {
Matt Arsenault	1322b6f	2016-07-09 01:13:56 +0000	[diff] [blame]	2173	// Extract with offset
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	2174	def : Pat<
Nicolai Haehnle	7968c34	2016-07-12 08:12:16 +0000	[diff] [blame]	2175	(eltvt (extractelt vt:$src, (MOVRELOffset i32:$idx, (i32 imm:$offset)))),
Matt Arsenault	1322b6f	2016-07-09 01:13:56 +0000	[diff] [blame]	2176	(!cast<Instruction>("SI_INDIRECT_SRC_"#VecSize) $src, $idx, imm:$offset)
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	2177	>;
				2178
Matt Arsenault	1322b6f	2016-07-09 01:13:56 +0000	[diff] [blame]	2179	// Insert with offset
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	2180	def : Pat<
Nicolai Haehnle	7968c34	2016-07-12 08:12:16 +0000	[diff] [blame]	2181	(insertelt vt:$src, eltvt:$val, (MOVRELOffset i32:$idx, (i32 imm:$offset))),
Matt Arsenault	1322b6f	2016-07-09 01:13:56 +0000	[diff] [blame]	2182	(!cast<Instruction>("SI_INDIRECT_DST_"#VecSize) $src, $idx, imm:$offset, $val)
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	2183	>;
				2184	}
				2185
Matt Arsenault	2841927	2015-10-07 00:42:51 +0000	[diff] [blame]	2186	defm : SI_INDIRECT_Pattern <v2f32, f32, "V2">;
				2187	defm : SI_INDIRECT_Pattern <v4f32, f32, "V4">;
				2188	defm : SI_INDIRECT_Pattern <v8f32, f32, "V8">;
				2189	defm : SI_INDIRECT_Pattern <v16f32, f32, "V16">;
Matt Arsenault	f5958dd	2014-02-02 00:05:35 +0000	[diff] [blame]	2190
Matt Arsenault	2841927	2015-10-07 00:42:51 +0000	[diff] [blame]	2191	defm : SI_INDIRECT_Pattern <v2i32, i32, "V2">;
				2192	defm : SI_INDIRECT_Pattern <v4i32, i32, "V4">;
				2193	defm : SI_INDIRECT_Pattern <v8i32, i32, "V8">;
				2194	defm : SI_INDIRECT_Pattern <v16i32, i32, "V16">;
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	2195
Tom Stellard	81d871d	2013-11-13 23:36:50 +0000	[diff] [blame]	2196	//===----------------------------------------------------------------------===//
Wei Ding	1041a64	2016-08-24 14:59:47 +0000	[diff] [blame]	2197	// SAD Patterns
				2198	//===----------------------------------------------------------------------===//
				2199
				2200	def : Pat <
				2201	(add (sub_oneuse (umax i32:$src0, i32:$src1),
				2202	(umin i32:$src0, i32:$src1)),
				2203	i32:$src2),
				2204	(V_SAD_U32 $src0, $src1, $src2)
				2205	>;
				2206
				2207	def : Pat <
				2208	(add (select_oneuse (i1 (setugt i32:$src0, i32:$src1)),
				2209	(sub i32:$src0, i32:$src1),
				2210	(sub i32:$src1, i32:$src0)),
				2211	i32:$src2),
				2212	(V_SAD_U32 $src0, $src1, $src2)
				2213	>;
				2214
				2215	//===----------------------------------------------------------------------===//
Matt Arsenault	5dbd5db	2014-04-22 03:49:30 +0000	[diff] [blame]	2216	// Conversion Patterns
				2217	//===----------------------------------------------------------------------===//
				2218
				2219	def : Pat<(i32 (sext_inreg i32:$src, i1)),
				2220	(S_BFE_I32 i32:$src, 65536)>; // 0 \| 1 << 16
				2221
Matt Arsenault	5dbd5db	2014-04-22 03:49:30 +0000	[diff] [blame]	2222	// Handle sext_inreg in i64
				2223	def : Pat <
				2224	(i64 (sext_inreg i64:$src, i1)),
Matt Arsenault	9481221	2014-11-14 18:18:16 +0000	[diff] [blame]	2225	(S_BFE_I64 i64:$src, 0x10000) // 0 \| 1 << 16
Matt Arsenault	5dbd5db	2014-04-22 03:49:30 +0000	[diff] [blame]	2226	>;
				2227
				2228	def : Pat <
				2229	(i64 (sext_inreg i64:$src, i8)),
Matt Arsenault	9481221	2014-11-14 18:18:16 +0000	[diff] [blame]	2230	(S_BFE_I64 i64:$src, 0x80000) // 0 \| 8 << 16
Matt Arsenault	5dbd5db	2014-04-22 03:49:30 +0000	[diff] [blame]	2231	>;
				2232
				2233	def : Pat <
				2234	(i64 (sext_inreg i64:$src, i16)),
Matt Arsenault	9481221	2014-11-14 18:18:16 +0000	[diff] [blame]	2235	(S_BFE_I64 i64:$src, 0x100000) // 0 \| 16 << 16
				2236	>;
				2237
				2238	def : Pat <
				2239	(i64 (sext_inreg i64:$src, i32)),
				2240	(S_BFE_I64 i64:$src, 0x200000) // 0 \| 32 << 16
Matt Arsenault	5dbd5db	2014-04-22 03:49:30 +0000	[diff] [blame]	2241	>;
				2242
Matt Arsenault	c6b69a9	2016-07-26 23:06:33 +0000	[diff] [blame]	2243	def : Pat <
				2244	(i64 (zext i32:$src)),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2245	(REG_SEQUENCE SReg_64, $src, sub0, (S_MOV_B32 0), sub1)
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	2246	>;
				2247
Matt Arsenault	c6b69a9	2016-07-26 23:06:33 +0000	[diff] [blame]	2248	def : Pat <
				2249	(i64 (anyext i32:$src)),
				2250	(REG_SEQUENCE SReg_64, $src, sub0, (i32 (IMPLICIT_DEF)), sub1)
				2251	>;
				2252
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	2253	class ZExt_i64_i1_Pat <SDNode ext> : Pat <
				2254	(i64 (ext i1:$src)),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2255	(REG_SEQUENCE VReg_64,
				2256	(V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0,
				2257	(S_MOV_B32 0), sub1)
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	2258	>;
				2259
				2260
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	2261	def : ZExt_i64_i1_Pat<zext>;
				2262	def : ZExt_i64_i1_Pat<anyext>;
				2263
Tom Stellard	bc4497b	2016-02-12 23:45:29 +0000	[diff] [blame]	2264	// FIXME: We need to use COPY_TO_REGCLASS to work-around the fact that
				2265	// REG_SEQUENCE patterns don't support instructions with multiple outputs.
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	2266	def : Pat <
				2267	(i64 (sext i32:$src)),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2268	(REG_SEQUENCE SReg_64, $src, sub0,
Artem Tamazov	38e496b	2016-04-29 17:04:50 +0000	[diff] [blame]	2269	(i32 (COPY_TO_REGCLASS (S_ASHR_I32 $src, 31), SReg_32_XM0)), sub1)
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	2270	>;
				2271
				2272	def : Pat <
				2273	(i64 (sext i1:$src)),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2274	(REG_SEQUENCE VReg_64,
				2275	(V_CNDMASK_B32_e64 0, -1, $src), sub0,
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	2276	(V_CNDMASK_B32_e64 0, -1, $src), sub1)
				2277	>;
				2278
Matt Arsenault	7fb961f	2016-07-22 17:01:21 +0000	[diff] [blame]	2279	class FPToI1Pat<Instruction Inst, int KOne, ValueType vt, SDPatternOperator fp_to_int> : Pat <
				2280	(i1 (fp_to_int (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)))),
				2281	(i1 (Inst 0, KOne, $src0_modifiers, $src0, DSTCLAMP.NONE, DSTOMOD.NONE))
				2282	>;
				2283
				2284	def : FPToI1Pat<V_CMP_EQ_F32_e64, CONST.FP32_ONE, f32, fp_to_uint>;
				2285	def : FPToI1Pat<V_CMP_EQ_F32_e64, CONST.FP32_NEG_ONE, f32, fp_to_sint>;
				2286	def : FPToI1Pat<V_CMP_EQ_F64_e64, CONST.FP64_ONE, f64, fp_to_uint>;
				2287	def : FPToI1Pat<V_CMP_EQ_F64_e64, CONST.FP64_NEG_ONE, f64, fp_to_sint>;
				2288
Matt Arsenault	becd656	2014-12-03 05:22:35 +0000	[diff] [blame]	2289	// If we need to perform a logical operation on i1 values, we need to
				2290	// use vector comparisons since there is only one SCC register. Vector
				2291	// comparisions still write to a pair of SGPRs, so treat these as
				2292	// 64-bit comparisons. When legalizing SGPR copies, instructions
				2293	// resulting in the copies from SCC to these instructions will be
				2294	// moved to the VALU.
				2295	def : Pat <
				2296	(i1 (and i1:$src0, i1:$src1)),
				2297	(S_AND_B64 $src0, $src1)
				2298	>;
				2299
				2300	def : Pat <
				2301	(i1 (or i1:$src0, i1:$src1)),
				2302	(S_OR_B64 $src0, $src1)
				2303	>;
				2304
				2305	def : Pat <
				2306	(i1 (xor i1:$src0, i1:$src1)),
				2307	(S_XOR_B64 $src0, $src1)
				2308	>;
				2309
Matt Arsenault	aeca2fa	2014-05-31 06:47:42 +0000	[diff] [blame]	2310	def : Pat <
				2311	(f32 (sint_to_fp i1:$src)),
				2312	(V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src)
				2313	>;
				2314
				2315	def : Pat <
				2316	(f32 (uint_to_fp i1:$src)),
				2317	(V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src)
				2318	>;
				2319
				2320	def : Pat <
				2321	(f64 (sint_to_fp i1:$src)),
Matt Arsenault	becd656	2014-12-03 05:22:35 +0000	[diff] [blame]	2322	(V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src))
Matt Arsenault	aeca2fa	2014-05-31 06:47:42 +0000	[diff] [blame]	2323	>;
				2324
				2325	def : Pat <
				2326	(f64 (uint_to_fp i1:$src)),
				2327	(V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src))
				2328	>;
				2329
Matt Arsenault	5dbd5db	2014-04-22 03:49:30 +0000	[diff] [blame]	2330	//===----------------------------------------------------------------------===//
Tom Stellard	fb96169	2013-10-23 00:44:19 +0000	[diff] [blame]	2331	// Miscellaneous Patterns
				2332	//===----------------------------------------------------------------------===//
				2333
				2334	def : Pat <
Tom Stellard	81d871d	2013-11-13 23:36:50 +0000	[diff] [blame]	2335	(i32 (trunc i64:$a)),
				2336	(EXTRACT_SUBREG $a, sub0)
				2337	>;
				2338
Michel Danzer	bf1a641	2014-01-28 03:01:16 +0000	[diff] [blame]	2339	def : Pat <
				2340	(i1 (trunc i32:$a)),
Marek Olsak	f924dd6	2015-10-29 15:05:03 +0000	[diff] [blame]	2341	(V_CMP_EQ_I32_e64 (S_AND_B32 (i32 1), $a), 1)
Michel Danzer	bf1a641	2014-01-28 03:01:16 +0000	[diff] [blame]	2342	>;
				2343
Matt Arsenault	e306a32	2014-10-21 16:25:08 +0000	[diff] [blame]	2344	def : Pat <
Matt Arsenault	abd271b	2015-02-05 06:05:13 +0000	[diff] [blame]	2345	(i1 (trunc i64:$a)),
Marek Olsak	f924dd6	2015-10-29 15:05:03 +0000	[diff] [blame]	2346	(V_CMP_EQ_I32_e64 (S_AND_B32 (i32 1),
Matt Arsenault	abd271b	2015-02-05 06:05:13 +0000	[diff] [blame]	2347	(EXTRACT_SUBREG $a, sub0)), 1)
				2348	>;
				2349
				2350	def : Pat <
Matt Arsenault	e306a32	2014-10-21 16:25:08 +0000	[diff] [blame]	2351	(i32 (bswap i32:$a)),
				2352	(V_BFI_B32 (S_MOV_B32 0x00ff00ff),
				2353	(V_ALIGNBIT_B32 $a, $a, 24),
				2354	(V_ALIGNBIT_B32 $a, $a, 8))
				2355	>;
				2356
Matt Arsenault	477b1782	2014-12-12 02:30:29 +0000	[diff] [blame]	2357	def : Pat <
				2358	(f32 (select i1:$src2, f32:$src1, f32:$src0)),
				2359	(V_CNDMASK_B32_e64 $src0, $src1, $src2)
				2360	>;
				2361
Marek Olsak	63a7b08	2015-03-24 13:40:21 +0000	[diff] [blame]	2362	multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> {
				2363	def : Pat <
				2364	(vt (shl (vt (add (vt (shl 1, vt:$a)), -1)), vt:$b)),
				2365	(BFM $a, $b)
				2366	>;
				2367
				2368	def : Pat <
				2369	(vt (add (vt (shl 1, vt:$a)), -1)),
				2370	(BFM $a, (MOV 0))
				2371	>;
				2372	}
				2373
				2374	defm : BFMPatterns <i32, S_BFM_B32, S_MOV_B32>;
				2375	// FIXME: defm : BFMPatterns <i64, S_BFM_B64, S_MOV_B64>;
				2376
Marek Olsak	949f5da	2015-03-24 13:40:34 +0000	[diff] [blame]	2377	def : BFEPattern <V_BFE_U32, S_MOV_B32>;
				2378
Matt Arsenault	9cd9071	2016-04-14 01:42:16 +0000	[diff] [blame]	2379	def : Pat<
				2380	(fcanonicalize f32:$src),
				2381	(V_MUL_F32_e64 0, CONST.FP32_ONE, 0, $src, 0, 0)
				2382	>;
				2383
				2384	def : Pat<
				2385	(fcanonicalize f64:$src),
				2386	(V_MUL_F64 0, CONST.FP64_ONE, 0, $src, 0, 0)
				2387	>;
				2388
Marek Olsak	43650e4	2015-03-24 13:40:08 +0000	[diff] [blame]	2389	//===----------------------------------------------------------------------===//
				2390	// Fract Patterns
				2391	//===----------------------------------------------------------------------===//
				2392
Marek Olsak	7d77728	2015-03-24 13:40:15 +0000	[diff] [blame]	2393	let Predicates = [isSI] in {
				2394
				2395	// V_FRACT is buggy on SI, so the F32 version is never used and (x-floor(x)) is
				2396	// used instead. However, SI doesn't have V_FLOOR_F64, so the most efficient
				2397	// way to implement it is using V_FRACT_F64.
				2398	// The workaround for the V_FRACT bug is:
				2399	// fract(x) = isnan(x) ? x : min(V_FRACT(x), 0.99999999999999999)
				2400
Marek Olsak	7d77728	2015-03-24 13:40:15 +0000	[diff] [blame]	2401	// Convert floor(x) to (x - fract(x))
				2402	def : Pat <
				2403	(f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))),
				2404	(V_ADD_F64
				2405	$mods,
				2406	$x,
				2407	SRCMODS.NEG,
				2408	(V_CNDMASK_B64_PSEUDO
Marek Olsak	7d77728	2015-03-24 13:40:15 +0000	[diff] [blame]	2409	(V_MIN_F64
				2410	SRCMODS.NONE,
				2411	(V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE),
				2412	SRCMODS.NONE,
				2413	(V_MOV_B64_PSEUDO 0x3fefffffffffffff),
				2414	DSTCLAMP.NONE, DSTOMOD.NONE),
Marek Olsak	1354b87	2015-07-27 11:37:42 +0000	[diff] [blame]	2415	$x,
Marek Olsak	7d77728	2015-03-24 13:40:15 +0000	[diff] [blame]	2416	(V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, 3/NaN/)),
				2417	DSTCLAMP.NONE, DSTOMOD.NONE)
				2418	>;
				2419
				2420	} // End Predicates = [isSI]
				2421
Tom Stellard	fb96169	2013-10-23 00:44:19 +0000	[diff] [blame]	2422	//============================================================================//
Tom Stellard	eac65dd	2013-05-03 17:21:20 +0000	[diff] [blame]	2423	// Miscellaneous Optimization Patterns
				2424	//============================================================================//
				2425
Matt Arsenault	49dd428	2014-09-15 17:15:02 +0000	[diff] [blame]	2426	def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64>;
Tom Stellard	eac65dd	2013-05-03 17:21:20 +0000	[diff] [blame]	2427
Matt Arsenault	c89f291	2016-03-07 21:54:48 +0000	[diff] [blame]	2428	def : IntMed3Pat<V_MED3_I32, smax, smax_oneuse, smin_oneuse>;
				2429	def : IntMed3Pat<V_MED3_U32, umax, umax_oneuse, umin_oneuse>;
				2430
Tom Stellard	245c15f	2015-05-26 15:55:52 +0000	[diff] [blame]	2431	//============================================================================//
				2432	// Assembler aliases
				2433	//============================================================================//
				2434
				2435	def : MnemonicAlias<"v_add_u32", "v_add_i32">;
				2436	def : MnemonicAlias<"v_sub_u32", "v_sub_i32">;
				2437	def : MnemonicAlias<"v_subrev_u32", "v_subrev_i32">;
				2438
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	2439	} // End isGCN predicate