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gerrit-public.fairphone.software / toolchain / llvm-project / 1b13886b5f626a65e5242f22d93650c3a1f6ef8f / . / llvm / lib / Target / AMDGPU / SIInstructions.td
blob: 52eae16930e38979606d3719b3196ad5829e3d17 [file] [log] [blame]
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]1//===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This file was originally auto-generated from a GPU register header file and
10// all the instruction definitions were originally commented out. Instructions
11// that are not yet supported remain commented out.
12//===----------------------------------------------------------------------===//
13
Eric Christopher7792e322015-01-30 23:24:40 +0000[diff] [blame]14def isGCN : Predicate<"Subtarget->getGeneration() "
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000[diff] [blame]15 ">= SISubtarget::SOUTHERN_ISLANDS">,
Tom Stellardd7e6f132015-04-08 01:09:26 +0000[diff] [blame]16 AssemblerPredicate<"FeatureGCN">;
Marek Olsak7d777282015-03-24 13:40:15 +0000[diff] [blame]17def isSI : Predicate<"Subtarget->getGeneration() "
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000[diff] [blame]18 "== SISubtarget::SOUTHERN_ISLANDS">,
Matt Arsenaultd6adfb42015-09-24 19:52:21 +0000[diff] [blame]19 AssemblerPredicate<"FeatureSouthernIslands">;
20
Tom Stellardec87f842015-05-25 16:15:54 +0000[diff] [blame]21def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
22def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
23
Valery Pykhtina34fb492016-08-30 15:20:31 +0000[diff] [blame]24include "SOPInstructions.td"
Valery Pykhtin1b138862016-09-01 09:56:47 +0000[diff] [blame^]25include "SMInstructions.td"
Valery Pykhtina34fb492016-08-30 15:20:31 +0000[diff] [blame]26
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]27let SubtargetPredicate = isGCN in {
Tom Stellard0e70de52014-05-16 20:56:45 +0000[diff] [blame]28
Tom Stellard8d6d4492014-04-22 16:33:57 +0000[diff] [blame]29//===----------------------------------------------------------------------===//
Tom Stellard3a35d8f2014-10-01 14:44:45 +0000[diff] [blame]30// EXP Instructions
31//===----------------------------------------------------------------------===//
32
33defm EXP : EXP_m;
34
35//===----------------------------------------------------------------------===//
Tom Stellard8d6d4492014-04-22 16:33:57 +0000[diff] [blame]36// VOPC Instructions
37//===----------------------------------------------------------------------===//
38
Matt Arsenault0943b0e2015-03-23 18:45:38 +0000[diff] [blame]39let isCompare = 1, isCommutable = 1 in {
Christian Konig76edd4f2013-02-26 17:52:29 +0000[diff] [blame]40
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]41defm V_CMP_F_F32 : VOPC_F32 <vopc<0x0, 0x40>, "v_cmp_f_f32">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]42defm V_CMP_LT_F32 : VOPC_F32 <vopc<0x1, 0x41>, "v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]43defm V_CMP_EQ_F32 : VOPC_F32 <vopc<0x2, 0x42>, "v_cmp_eq_f32", COND_OEQ>;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]44defm V_CMP_LE_F32 : VOPC_F32 <vopc<0x3, 0x43>, "v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]45defm V_CMP_GT_F32 : VOPC_F32 <vopc<0x4, 0x44>, "v_cmp_gt_f32", COND_OGT>;
Matt Arsenault9cded7a2014-12-11 22:15:35 +0000[diff] [blame]46defm V_CMP_LG_F32 : VOPC_F32 <vopc<0x5, 0x45>, "v_cmp_lg_f32", COND_ONE>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]47defm V_CMP_GE_F32 : VOPC_F32 <vopc<0x6, 0x46>, "v_cmp_ge_f32", COND_OGE>;
48defm V_CMP_O_F32 : VOPC_F32 <vopc<0x7, 0x47>, "v_cmp_o_f32", COND_O>;
49defm V_CMP_U_F32 : VOPC_F32 <vopc<0x8, 0x48>, "v_cmp_u_f32", COND_UO>;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]50defm V_CMP_NGE_F32 : VOPC_F32 <vopc<0x9, 0x49>, "v_cmp_nge_f32", COND_ULT, "v_cmp_nle_f32">;
Matt Arsenault58d502f2014-12-11 22:15:43 +0000[diff] [blame]51defm V_CMP_NLG_F32 : VOPC_F32 <vopc<0xa, 0x4a>, "v_cmp_nlg_f32", COND_UEQ>;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]52defm V_CMP_NGT_F32 : VOPC_F32 <vopc<0xb, 0x4b>, "v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">;
Matt Arsenault8b989ef2014-12-11 22:15:39 +0000[diff] [blame]53defm V_CMP_NLE_F32 : VOPC_F32 <vopc<0xc, 0x4c>, "v_cmp_nle_f32", COND_UGT>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]54defm V_CMP_NEQ_F32 : VOPC_F32 <vopc<0xd, 0x4d>, "v_cmp_neq_f32", COND_UNE>;
Matt Arsenault8b989ef2014-12-11 22:15:39 +0000[diff] [blame]55defm V_CMP_NLT_F32 : VOPC_F32 <vopc<0xe, 0x4e>, "v_cmp_nlt_f32", COND_UGE>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]56defm V_CMP_TRU_F32 : VOPC_F32 <vopc<0xf, 0x4f>, "v_cmp_tru_f32">;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]57
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]58
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]59defm V_CMPX_F_F32 : VOPCX_F32 <vopc<0x10, 0x50>, "v_cmpx_f_f32">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]60defm V_CMPX_LT_F32 : VOPCX_F32 <vopc<0x11, 0x51>, "v_cmpx_lt_f32", "v_cmpx_gt_f32">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]61defm V_CMPX_EQ_F32 : VOPCX_F32 <vopc<0x12, 0x52>, "v_cmpx_eq_f32">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]62defm V_CMPX_LE_F32 : VOPCX_F32 <vopc<0x13, 0x53>, "v_cmpx_le_f32", "v_cmpx_ge_f32">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]63defm V_CMPX_GT_F32 : VOPCX_F32 <vopc<0x14, 0x54>, "v_cmpx_gt_f32">;
64defm V_CMPX_LG_F32 : VOPCX_F32 <vopc<0x15, 0x55>, "v_cmpx_lg_f32">;
65defm V_CMPX_GE_F32 : VOPCX_F32 <vopc<0x16, 0x56>, "v_cmpx_ge_f32">;
66defm V_CMPX_O_F32 : VOPCX_F32 <vopc<0x17, 0x57>, "v_cmpx_o_f32">;
67defm V_CMPX_U_F32 : VOPCX_F32 <vopc<0x18, 0x58>, "v_cmpx_u_f32">;
68defm V_CMPX_NGE_F32 : VOPCX_F32 <vopc<0x19, 0x59>, "v_cmpx_nge_f32">;
69defm V_CMPX_NLG_F32 : VOPCX_F32 <vopc<0x1a, 0x5a>, "v_cmpx_nlg_f32">;
70defm V_CMPX_NGT_F32 : VOPCX_F32 <vopc<0x1b, 0x5b>, "v_cmpx_ngt_f32">;
71defm V_CMPX_NLE_F32 : VOPCX_F32 <vopc<0x1c, 0x5c>, "v_cmpx_nle_f32">;
72defm V_CMPX_NEQ_F32 : VOPCX_F32 <vopc<0x1d, 0x5d>, "v_cmpx_neq_f32">;
73defm V_CMPX_NLT_F32 : VOPCX_F32 <vopc<0x1e, 0x5e>, "v_cmpx_nlt_f32">;
74defm V_CMPX_TRU_F32 : VOPCX_F32 <vopc<0x1f, 0x5f>, "v_cmpx_tru_f32">;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]75
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]76
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]77defm V_CMP_F_F64 : VOPC_F64 <vopc<0x20, 0x60>, "v_cmp_f_f64">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]78defm V_CMP_LT_F64 : VOPC_F64 <vopc<0x21, 0x61>, "v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]79defm V_CMP_EQ_F64 : VOPC_F64 <vopc<0x22, 0x62>, "v_cmp_eq_f64", COND_OEQ>;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]80defm V_CMP_LE_F64 : VOPC_F64 <vopc<0x23, 0x63>, "v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]81defm V_CMP_GT_F64 : VOPC_F64 <vopc<0x24, 0x64>, "v_cmp_gt_f64", COND_OGT>;
Matt Arsenault9cded7a2014-12-11 22:15:35 +0000[diff] [blame]82defm V_CMP_LG_F64 : VOPC_F64 <vopc<0x25, 0x65>, "v_cmp_lg_f64", COND_ONE>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]83defm V_CMP_GE_F64 : VOPC_F64 <vopc<0x26, 0x66>, "v_cmp_ge_f64", COND_OGE>;
84defm V_CMP_O_F64 : VOPC_F64 <vopc<0x27, 0x67>, "v_cmp_o_f64", COND_O>;
85defm V_CMP_U_F64 : VOPC_F64 <vopc<0x28, 0x68>, "v_cmp_u_f64", COND_UO>;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]86defm V_CMP_NGE_F64 : VOPC_F64 <vopc<0x29, 0x69>, "v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">;
Matt Arsenault58d502f2014-12-11 22:15:43 +0000[diff] [blame]87defm V_CMP_NLG_F64 : VOPC_F64 <vopc<0x2a, 0x6a>, "v_cmp_nlg_f64", COND_UEQ>;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]88defm V_CMP_NGT_F64 : VOPC_F64 <vopc<0x2b, 0x6b>, "v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">;
Matt Arsenault8b989ef2014-12-11 22:15:39 +0000[diff] [blame]89defm V_CMP_NLE_F64 : VOPC_F64 <vopc<0x2c, 0x6c>, "v_cmp_nle_f64", COND_UGT>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]90defm V_CMP_NEQ_F64 : VOPC_F64 <vopc<0x2d, 0x6d>, "v_cmp_neq_f64", COND_UNE>;
Matt Arsenault8b989ef2014-12-11 22:15:39 +0000[diff] [blame]91defm V_CMP_NLT_F64 : VOPC_F64 <vopc<0x2e, 0x6e>, "v_cmp_nlt_f64", COND_UGE>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]92defm V_CMP_TRU_F64 : VOPC_F64 <vopc<0x2f, 0x6f>, "v_cmp_tru_f64">;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]93
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]94
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]95defm V_CMPX_F_F64 : VOPCX_F64 <vopc<0x30, 0x70>, "v_cmpx_f_f64">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]96defm V_CMPX_LT_F64 : VOPCX_F64 <vopc<0x31, 0x71>, "v_cmpx_lt_f64", "v_cmpx_gt_f64">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]97defm V_CMPX_EQ_F64 : VOPCX_F64 <vopc<0x32, 0x72>, "v_cmpx_eq_f64">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]98defm V_CMPX_LE_F64 : VOPCX_F64 <vopc<0x33, 0x73>, "v_cmpx_le_f64", "v_cmpx_ge_f64">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]99defm V_CMPX_GT_F64 : VOPCX_F64 <vopc<0x34, 0x74>, "v_cmpx_gt_f64">;
100defm V_CMPX_LG_F64 : VOPCX_F64 <vopc<0x35, 0x75>, "v_cmpx_lg_f64">;
101defm V_CMPX_GE_F64 : VOPCX_F64 <vopc<0x36, 0x76>, "v_cmpx_ge_f64">;
102defm V_CMPX_O_F64 : VOPCX_F64 <vopc<0x37, 0x77>, "v_cmpx_o_f64">;
103defm V_CMPX_U_F64 : VOPCX_F64 <vopc<0x38, 0x78>, "v_cmpx_u_f64">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]104defm V_CMPX_NGE_F64 : VOPCX_F64 <vopc<0x39, 0x79>, "v_cmpx_nge_f64", "v_cmpx_nle_f64">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]105defm V_CMPX_NLG_F64 : VOPCX_F64 <vopc<0x3a, 0x7a>, "v_cmpx_nlg_f64">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]106defm V_CMPX_NGT_F64 : VOPCX_F64 <vopc<0x3b, 0x7b>, "v_cmpx_ngt_f64", "v_cmpx_nlt_f64">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]107defm V_CMPX_NLE_F64 : VOPCX_F64 <vopc<0x3c, 0x7c>, "v_cmpx_nle_f64">;
108defm V_CMPX_NEQ_F64 : VOPCX_F64 <vopc<0x3d, 0x7d>, "v_cmpx_neq_f64">;
109defm V_CMPX_NLT_F64 : VOPCX_F64 <vopc<0x3e, 0x7e>, "v_cmpx_nlt_f64">;
110defm V_CMPX_TRU_F64 : VOPCX_F64 <vopc<0x3f, 0x7f>, "v_cmpx_tru_f64">;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]111
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]112
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]113let SubtargetPredicate = isSICI in {
114
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]115defm V_CMPS_F_F32 : VOPC_F32 <vopc<0x40>, "v_cmps_f_f32">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]116defm V_CMPS_LT_F32 : VOPC_F32 <vopc<0x41>, "v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]117defm V_CMPS_EQ_F32 : VOPC_F32 <vopc<0x42>, "v_cmps_eq_f32">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]118defm V_CMPS_LE_F32 : VOPC_F32 <vopc<0x43>, "v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]119defm V_CMPS_GT_F32 : VOPC_F32 <vopc<0x44>, "v_cmps_gt_f32">;
120defm V_CMPS_LG_F32 : VOPC_F32 <vopc<0x45>, "v_cmps_lg_f32">;
121defm V_CMPS_GE_F32 : VOPC_F32 <vopc<0x46>, "v_cmps_ge_f32">;
122defm V_CMPS_O_F32 : VOPC_F32 <vopc<0x47>, "v_cmps_o_f32">;
123defm V_CMPS_U_F32 : VOPC_F32 <vopc<0x48>, "v_cmps_u_f32">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]124defm V_CMPS_NGE_F32 : VOPC_F32 <vopc<0x49>, "v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]125defm V_CMPS_NLG_F32 : VOPC_F32 <vopc<0x4a>, "v_cmps_nlg_f32">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]126defm V_CMPS_NGT_F32 : VOPC_F32 <vopc<0x4b>, "v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]127defm V_CMPS_NLE_F32 : VOPC_F32 <vopc<0x4c>, "v_cmps_nle_f32">;
128defm V_CMPS_NEQ_F32 : VOPC_F32 <vopc<0x4d>, "v_cmps_neq_f32">;
129defm V_CMPS_NLT_F32 : VOPC_F32 <vopc<0x4e>, "v_cmps_nlt_f32">;
130defm V_CMPS_TRU_F32 : VOPC_F32 <vopc<0x4f>, "v_cmps_tru_f32">;
Christian Konig76edd4f2013-02-26 17:52:29 +0000[diff] [blame]131
Christian Konig76edd4f2013-02-26 17:52:29 +0000[diff] [blame]132
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]133defm V_CMPSX_F_F32 : VOPCX_F32 <vopc<0x50>, "v_cmpsx_f_f32">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]134defm V_CMPSX_LT_F32 : VOPCX_F32 <vopc<0x51>, "v_cmpsx_lt_f32", "v_cmpsx_gt_f32">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]135defm V_CMPSX_EQ_F32 : VOPCX_F32 <vopc<0x52>, "v_cmpsx_eq_f32">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]136defm V_CMPSX_LE_F32 : VOPCX_F32 <vopc<0x53>, "v_cmpsx_le_f32", "v_cmpsx_ge_f32">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]137defm V_CMPSX_GT_F32 : VOPCX_F32 <vopc<0x54>, "v_cmpsx_gt_f32">;
138defm V_CMPSX_LG_F32 : VOPCX_F32 <vopc<0x55>, "v_cmpsx_lg_f32">;
139defm V_CMPSX_GE_F32 : VOPCX_F32 <vopc<0x56>, "v_cmpsx_ge_f32">;
140defm V_CMPSX_O_F32 : VOPCX_F32 <vopc<0x57>, "v_cmpsx_o_f32">;
141defm V_CMPSX_U_F32 : VOPCX_F32 <vopc<0x58>, "v_cmpsx_u_f32">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]142defm V_CMPSX_NGE_F32 : VOPCX_F32 <vopc<0x59>, "v_cmpsx_nge_f32", "v_cmpsx_nle_f32">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]143defm V_CMPSX_NLG_F32 : VOPCX_F32 <vopc<0x5a>, "v_cmpsx_nlg_f32">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]144defm V_CMPSX_NGT_F32 : VOPCX_F32 <vopc<0x5b>, "v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]145defm V_CMPSX_NLE_F32 : VOPCX_F32 <vopc<0x5c>, "v_cmpsx_nle_f32">;
146defm V_CMPSX_NEQ_F32 : VOPCX_F32 <vopc<0x5d>, "v_cmpsx_neq_f32">;
147defm V_CMPSX_NLT_F32 : VOPCX_F32 <vopc<0x5e>, "v_cmpsx_nlt_f32">;
148defm V_CMPSX_TRU_F32 : VOPCX_F32 <vopc<0x5f>, "v_cmpsx_tru_f32">;
Christian Konig76edd4f2013-02-26 17:52:29 +0000[diff] [blame]149
Christian Konig76edd4f2013-02-26 17:52:29 +0000[diff] [blame]150
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]151defm V_CMPS_F_F64 : VOPC_F64 <vopc<0x60>, "v_cmps_f_f64">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]152defm V_CMPS_LT_F64 : VOPC_F64 <vopc<0x61>, "v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]153defm V_CMPS_EQ_F64 : VOPC_F64 <vopc<0x62>, "v_cmps_eq_f64">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]154defm V_CMPS_LE_F64 : VOPC_F64 <vopc<0x63>, "v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]155defm V_CMPS_GT_F64 : VOPC_F64 <vopc<0x64>, "v_cmps_gt_f64">;
156defm V_CMPS_LG_F64 : VOPC_F64 <vopc<0x65>, "v_cmps_lg_f64">;
157defm V_CMPS_GE_F64 : VOPC_F64 <vopc<0x66>, "v_cmps_ge_f64">;
158defm V_CMPS_O_F64 : VOPC_F64 <vopc<0x67>, "v_cmps_o_f64">;
159defm V_CMPS_U_F64 : VOPC_F64 <vopc<0x68>, "v_cmps_u_f64">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]160defm V_CMPS_NGE_F64 : VOPC_F64 <vopc<0x69>, "v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]161defm V_CMPS_NLG_F64 : VOPC_F64 <vopc<0x6a>, "v_cmps_nlg_f64">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]162defm V_CMPS_NGT_F64 : VOPC_F64 <vopc<0x6b>, "v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]163defm V_CMPS_NLE_F64 : VOPC_F64 <vopc<0x6c>, "v_cmps_nle_f64">;
164defm V_CMPS_NEQ_F64 : VOPC_F64 <vopc<0x6d>, "v_cmps_neq_f64">;
165defm V_CMPS_NLT_F64 : VOPC_F64 <vopc<0x6e>, "v_cmps_nlt_f64">;
166defm V_CMPS_TRU_F64 : VOPC_F64 <vopc<0x6f>, "v_cmps_tru_f64">;
Christian Konig76edd4f2013-02-26 17:52:29 +0000[diff] [blame]167
Christian Konig76edd4f2013-02-26 17:52:29 +0000[diff] [blame]168
Matt Arsenault05b617f2015-03-23 18:45:23 +0000[diff] [blame]169defm V_CMPSX_F_F64 : VOPCX_F64 <vopc<0x70>, "v_cmpsx_f_f64">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]170defm V_CMPSX_LT_F64 : VOPCX_F64 <vopc<0x71>, "v_cmpsx_lt_f64", "v_cmpsx_gt_f64">;
Matt Arsenault05b617f2015-03-23 18:45:23 +0000[diff] [blame]171defm V_CMPSX_EQ_F64 : VOPCX_F64 <vopc<0x72>, "v_cmpsx_eq_f64">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]172defm V_CMPSX_LE_F64 : VOPCX_F64 <vopc<0x73>, "v_cmpsx_le_f64", "v_cmpsx_ge_f64">;
Matt Arsenault05b617f2015-03-23 18:45:23 +0000[diff] [blame]173defm V_CMPSX_GT_F64 : VOPCX_F64 <vopc<0x74>, "v_cmpsx_gt_f64">;
174defm V_CMPSX_LG_F64 : VOPCX_F64 <vopc<0x75>, "v_cmpsx_lg_f64">;
175defm V_CMPSX_GE_F64 : VOPCX_F64 <vopc<0x76>, "v_cmpsx_ge_f64">;
176defm V_CMPSX_O_F64 : VOPCX_F64 <vopc<0x77>, "v_cmpsx_o_f64">;
177defm V_CMPSX_U_F64 : VOPCX_F64 <vopc<0x78>, "v_cmpsx_u_f64">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]178defm V_CMPSX_NGE_F64 : VOPCX_F64 <vopc<0x79>, "v_cmpsx_nge_f64", "v_cmpsx_nle_f64">;
Matt Arsenault05b617f2015-03-23 18:45:23 +0000[diff] [blame]179defm V_CMPSX_NLG_F64 : VOPCX_F64 <vopc<0x7a>, "v_cmpsx_nlg_f64">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]180defm V_CMPSX_NGT_F64 : VOPCX_F64 <vopc<0x7b>, "v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">;
Matt Arsenault05b617f2015-03-23 18:45:23 +0000[diff] [blame]181defm V_CMPSX_NLE_F64 : VOPCX_F64 <vopc<0x7c>, "v_cmpsx_nle_f64">;
182defm V_CMPSX_NEQ_F64 : VOPCX_F64 <vopc<0x7d>, "v_cmpsx_neq_f64">;
183defm V_CMPSX_NLT_F64 : VOPCX_F64 <vopc<0x7e>, "v_cmpsx_nlt_f64">;
184defm V_CMPSX_TRU_F64 : VOPCX_F64 <vopc<0x7f>, "v_cmpsx_tru_f64">;
Christian Konig76edd4f2013-02-26 17:52:29 +0000[diff] [blame]185
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]186} // End SubtargetPredicate = isSICI
187
188defm V_CMP_F_I32 : VOPC_I32 <vopc<0x80, 0xc0>, "v_cmp_f_i32">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]189defm V_CMP_LT_I32 : VOPC_I32 <vopc<0x81, 0xc1>, "v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]190defm V_CMP_EQ_I32 : VOPC_I32 <vopc<0x82, 0xc2>, "v_cmp_eq_i32", COND_EQ>;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]191defm V_CMP_LE_I32 : VOPC_I32 <vopc<0x83, 0xc3>, "v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]192defm V_CMP_GT_I32 : VOPC_I32 <vopc<0x84, 0xc4>, "v_cmp_gt_i32", COND_SGT>;
193defm V_CMP_NE_I32 : VOPC_I32 <vopc<0x85, 0xc5>, "v_cmp_ne_i32", COND_NE>;
194defm V_CMP_GE_I32 : VOPC_I32 <vopc<0x86, 0xc6>, "v_cmp_ge_i32", COND_SGE>;
195defm V_CMP_T_I32 : VOPC_I32 <vopc<0x87, 0xc7>, "v_cmp_t_i32">;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]196
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]197
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]198defm V_CMPX_F_I32 : VOPCX_I32 <vopc<0x90, 0xd0>, "v_cmpx_f_i32">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]199defm V_CMPX_LT_I32 : VOPCX_I32 <vopc<0x91, 0xd1>, "v_cmpx_lt_i32", "v_cmpx_gt_i32">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]200defm V_CMPX_EQ_I32 : VOPCX_I32 <vopc<0x92, 0xd2>, "v_cmpx_eq_i32">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]201defm V_CMPX_LE_I32 : VOPCX_I32 <vopc<0x93, 0xd3>, "v_cmpx_le_i32", "v_cmpx_ge_i32">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]202defm V_CMPX_GT_I32 : VOPCX_I32 <vopc<0x94, 0xd4>, "v_cmpx_gt_i32">;
203defm V_CMPX_NE_I32 : VOPCX_I32 <vopc<0x95, 0xd5>, "v_cmpx_ne_i32">;
204defm V_CMPX_GE_I32 : VOPCX_I32 <vopc<0x96, 0xd6>, "v_cmpx_ge_i32">;
205defm V_CMPX_T_I32 : VOPCX_I32 <vopc<0x97, 0xd7>, "v_cmpx_t_i32">;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]206
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]207
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]208defm V_CMP_F_I64 : VOPC_I64 <vopc<0xa0, 0xe0>, "v_cmp_f_i64">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]209defm V_CMP_LT_I64 : VOPC_I64 <vopc<0xa1, 0xe1>, "v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]210defm V_CMP_EQ_I64 : VOPC_I64 <vopc<0xa2, 0xe2>, "v_cmp_eq_i64", COND_EQ>;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]211defm V_CMP_LE_I64 : VOPC_I64 <vopc<0xa3, 0xe3>, "v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]212defm V_CMP_GT_I64 : VOPC_I64 <vopc<0xa4, 0xe4>, "v_cmp_gt_i64", COND_SGT>;
213defm V_CMP_NE_I64 : VOPC_I64 <vopc<0xa5, 0xe5>, "v_cmp_ne_i64", COND_NE>;
214defm V_CMP_GE_I64 : VOPC_I64 <vopc<0xa6, 0xe6>, "v_cmp_ge_i64", COND_SGE>;
215defm V_CMP_T_I64 : VOPC_I64 <vopc<0xa7, 0xe7>, "v_cmp_t_i64">;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]216
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]217
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]218defm V_CMPX_F_I64 : VOPCX_I64 <vopc<0xb0, 0xf0>, "v_cmpx_f_i64">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]219defm V_CMPX_LT_I64 : VOPCX_I64 <vopc<0xb1, 0xf1>, "v_cmpx_lt_i64", "v_cmpx_gt_i64">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]220defm V_CMPX_EQ_I64 : VOPCX_I64 <vopc<0xb2, 0xf2>, "v_cmpx_eq_i64">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]221defm V_CMPX_LE_I64 : VOPCX_I64 <vopc<0xb3, 0xf3>, "v_cmpx_le_i64", "v_cmpx_ge_i64">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]222defm V_CMPX_GT_I64 : VOPCX_I64 <vopc<0xb4, 0xf4>, "v_cmpx_gt_i64">;
223defm V_CMPX_NE_I64 : VOPCX_I64 <vopc<0xb5, 0xf5>, "v_cmpx_ne_i64">;
224defm V_CMPX_GE_I64 : VOPCX_I64 <vopc<0xb6, 0xf6>, "v_cmpx_ge_i64">;
225defm V_CMPX_T_I64 : VOPCX_I64 <vopc<0xb7, 0xf7>, "v_cmpx_t_i64">;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]226
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]227
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]228defm V_CMP_F_U32 : VOPC_I32 <vopc<0xc0, 0xc8>, "v_cmp_f_u32">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]229defm V_CMP_LT_U32 : VOPC_I32 <vopc<0xc1, 0xc9>, "v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]230defm V_CMP_EQ_U32 : VOPC_I32 <vopc<0xc2, 0xca>, "v_cmp_eq_u32", COND_EQ>;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]231defm V_CMP_LE_U32 : VOPC_I32 <vopc<0xc3, 0xcb>, "v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]232defm V_CMP_GT_U32 : VOPC_I32 <vopc<0xc4, 0xcc>, "v_cmp_gt_u32", COND_UGT>;
233defm V_CMP_NE_U32 : VOPC_I32 <vopc<0xc5, 0xcd>, "v_cmp_ne_u32", COND_NE>;
234defm V_CMP_GE_U32 : VOPC_I32 <vopc<0xc6, 0xce>, "v_cmp_ge_u32", COND_UGE>;
235defm V_CMP_T_U32 : VOPC_I32 <vopc<0xc7, 0xcf>, "v_cmp_t_u32">;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]236
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]237
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]238defm V_CMPX_F_U32 : VOPCX_I32 <vopc<0xd0, 0xd8>, "v_cmpx_f_u32">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]239defm V_CMPX_LT_U32 : VOPCX_I32 <vopc<0xd1, 0xd9>, "v_cmpx_lt_u32", "v_cmpx_gt_u32">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]240defm V_CMPX_EQ_U32 : VOPCX_I32 <vopc<0xd2, 0xda>, "v_cmpx_eq_u32">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]241defm V_CMPX_LE_U32 : VOPCX_I32 <vopc<0xd3, 0xdb>, "v_cmpx_le_u32", "v_cmpx_le_u32">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]242defm V_CMPX_GT_U32 : VOPCX_I32 <vopc<0xd4, 0xdc>, "v_cmpx_gt_u32">;
243defm V_CMPX_NE_U32 : VOPCX_I32 <vopc<0xd5, 0xdd>, "v_cmpx_ne_u32">;
244defm V_CMPX_GE_U32 : VOPCX_I32 <vopc<0xd6, 0xde>, "v_cmpx_ge_u32">;
245defm V_CMPX_T_U32 : VOPCX_I32 <vopc<0xd7, 0xdf>, "v_cmpx_t_u32">;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]246
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]247
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]248defm V_CMP_F_U64 : VOPC_I64 <vopc<0xe0, 0xe8>, "v_cmp_f_u64">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]249defm V_CMP_LT_U64 : VOPC_I64 <vopc<0xe1, 0xe9>, "v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]250defm V_CMP_EQ_U64 : VOPC_I64 <vopc<0xe2, 0xea>, "v_cmp_eq_u64", COND_EQ>;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]251defm V_CMP_LE_U64 : VOPC_I64 <vopc<0xe3, 0xeb>, "v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]252defm V_CMP_GT_U64 : VOPC_I64 <vopc<0xe4, 0xec>, "v_cmp_gt_u64", COND_UGT>;
253defm V_CMP_NE_U64 : VOPC_I64 <vopc<0xe5, 0xed>, "v_cmp_ne_u64", COND_NE>;
254defm V_CMP_GE_U64 : VOPC_I64 <vopc<0xe6, 0xee>, "v_cmp_ge_u64", COND_UGE>;
255defm V_CMP_T_U64 : VOPC_I64 <vopc<0xe7, 0xef>, "v_cmp_t_u64">;
Christian Konig76edd4f2013-02-26 17:52:29 +0000[diff] [blame]256
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]257defm V_CMPX_F_U64 : VOPCX_I64 <vopc<0xf0, 0xf8>, "v_cmpx_f_u64">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]258defm V_CMPX_LT_U64 : VOPCX_I64 <vopc<0xf1, 0xf9>, "v_cmpx_lt_u64", "v_cmpx_gt_u64">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]259defm V_CMPX_EQ_U64 : VOPCX_I64 <vopc<0xf2, 0xfa>, "v_cmpx_eq_u64">;
Matt Arsenaultf5b2cd82015-03-23 18:45:30 +0000[diff] [blame]260defm V_CMPX_LE_U64 : VOPCX_I64 <vopc<0xf3, 0xfb>, "v_cmpx_le_u64", "v_cmpx_ge_u64">;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]261defm V_CMPX_GT_U64 : VOPCX_I64 <vopc<0xf4, 0xfc>, "v_cmpx_gt_u64">;
262defm V_CMPX_NE_U64 : VOPCX_I64 <vopc<0xf5, 0xfd>, "v_cmpx_ne_u64">;
263defm V_CMPX_GE_U64 : VOPCX_I64 <vopc<0xf6, 0xfe>, "v_cmpx_ge_u64">;
264defm V_CMPX_T_U64 : VOPCX_I64 <vopc<0xf7, 0xff>, "v_cmpx_t_u64">;
Christian Konig76edd4f2013-02-26 17:52:29 +0000[diff] [blame]265
Matt Arsenault0943b0e2015-03-23 18:45:38 +0000[diff] [blame]266} // End isCompare = 1, isCommutable = 1
Christian Konig76edd4f2013-02-26 17:52:29 +0000[diff] [blame]267
Matt Arsenault4831ce52015-01-06 23:00:37 +0000[diff] [blame]268defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <vopc<0x88, 0x10>, "v_cmp_class_f32">;
Matt Arsenault4831ce52015-01-06 23:00:37 +0000[diff] [blame]269defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <vopc<0x98, 0x11>, "v_cmpx_class_f32">;
Matt Arsenault4831ce52015-01-06 23:00:37 +0000[diff] [blame]270defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <vopc<0xa8, 0x12>, "v_cmp_class_f64">;
Matt Arsenault4831ce52015-01-06 23:00:37 +0000[diff] [blame]271defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <vopc<0xb8, 0x13>, "v_cmpx_class_f64">;
Matt Arsenault42f39e12015-03-23 18:45:35 +0000[diff] [blame]272
Tom Stellard8d6d4492014-04-22 16:33:57 +0000[diff] [blame]273//===----------------------------------------------------------------------===//
Tom Stellard8d6d4492014-04-22 16:33:57 +0000[diff] [blame]274// MUBUF Instructions
275//===----------------------------------------------------------------------===//
Matt Arsenaultdd78b802014-03-19 22:19:56 +0000[diff] [blame]276
Tom Stellardaec94b32015-02-27 14:59:46 +0000[diff] [blame]277defm BUFFER_LOAD_FORMAT_X : MUBUF_Load_Helper <
278 mubuf<0x00>, "buffer_load_format_x", VGPR_32
279>;
280defm BUFFER_LOAD_FORMAT_XY : MUBUF_Load_Helper <
281 mubuf<0x01>, "buffer_load_format_xy", VReg_64
282>;
283defm BUFFER_LOAD_FORMAT_XYZ : MUBUF_Load_Helper <
284 mubuf<0x02>, "buffer_load_format_xyz", VReg_96
285>;
286defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <
287 mubuf<0x03>, "buffer_load_format_xyzw", VReg_128
288>;
Nicolai Haehnleb48275f2016-04-19 21:58:33 +0000[diff] [blame]289defm BUFFER_STORE_FORMAT_X : MUBUF_Store_Helper <
290 mubuf<0x04>, "buffer_store_format_x", VGPR_32
291>;
292defm BUFFER_STORE_FORMAT_XY : MUBUF_Store_Helper <
293 mubuf<0x05>, "buffer_store_format_xy", VReg_64
294>;
295defm BUFFER_STORE_FORMAT_XYZ : MUBUF_Store_Helper <
296 mubuf<0x06>, "buffer_store_format_xyz", VReg_96
297>;
298defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Store_Helper <
299 mubuf<0x07>, "buffer_store_format_xyzw", VReg_128
300>;
Tom Stellard7c1838d2014-07-02 20:53:56 +0000[diff] [blame]301defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <
Tom Stellard17a0ec542016-07-04 20:41:48 +0000[diff] [blame]302 mubuf<0x08, 0x10>, "buffer_load_ubyte", VGPR_32, i32, mubuf_az_extloadi8
Tom Stellard7c1838d2014-07-02 20:53:56 +0000[diff] [blame]303>;
304defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <
Tom Stellard17a0ec542016-07-04 20:41:48 +0000[diff] [blame]305 mubuf<0x09, 0x11>, "buffer_load_sbyte", VGPR_32, i32, mubuf_sextloadi8
Tom Stellard7c1838d2014-07-02 20:53:56 +0000[diff] [blame]306>;
307defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <
Tom Stellard17a0ec542016-07-04 20:41:48 +0000[diff] [blame]308 mubuf<0x0a, 0x12>, "buffer_load_ushort", VGPR_32, i32, mubuf_az_extloadi16
Tom Stellard7c1838d2014-07-02 20:53:56 +0000[diff] [blame]309>;
310defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <
Tom Stellard17a0ec542016-07-04 20:41:48 +0000[diff] [blame]311 mubuf<0x0b, 0x13>, "buffer_load_sshort", VGPR_32, i32, mubuf_sextloadi16
Tom Stellard7c1838d2014-07-02 20:53:56 +0000[diff] [blame]312>;
313defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <
Tom Stellarda6f24c62015-12-15 20:55:55 +0000[diff] [blame]314 mubuf<0x0c, 0x14>, "buffer_load_dword", VGPR_32, i32, mubuf_load
Tom Stellard7c1838d2014-07-02 20:53:56 +0000[diff] [blame]315>;
316defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <
Tom Stellarda6f24c62015-12-15 20:55:55 +0000[diff] [blame]317 mubuf<0x0d, 0x15>, "buffer_load_dwordx2", VReg_64, v2i32, mubuf_load
Tom Stellard7c1838d2014-07-02 20:53:56 +0000[diff] [blame]318>;
319defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <
Tom Stellarda6f24c62015-12-15 20:55:55 +0000[diff] [blame]320 mubuf<0x0e, 0x17>, "buffer_load_dwordx4", VReg_128, v4i32, mubuf_load
Tom Stellard7c1838d2014-07-02 20:53:56 +0000[diff] [blame]321>;
Tom Stellardd3ee8c12013-08-16 01:12:06 +0000[diff] [blame]322
Tom Stellardb02094e2014-07-21 15:45:01 +0000[diff] [blame]323defm BUFFER_STORE_BYTE : MUBUF_Store_Helper <
Marek Olsakee98b112015-01-27 17:24:58 +0000[diff] [blame]324 mubuf<0x18>, "buffer_store_byte", VGPR_32, i32, truncstorei8_global
Tom Stellardd3ee8c12013-08-16 01:12:06 +0000[diff] [blame]325>;
326
Tom Stellardb02094e2014-07-21 15:45:01 +0000[diff] [blame]327defm BUFFER_STORE_SHORT : MUBUF_Store_Helper <
Marek Olsakee98b112015-01-27 17:24:58 +0000[diff] [blame]328 mubuf<0x1a>, "buffer_store_short", VGPR_32, i32, truncstorei16_global
Tom Stellardd3ee8c12013-08-16 01:12:06 +0000[diff] [blame]329>;
Tom Stellard754f80f2013-04-05 23:31:51 +0000[diff] [blame]330
Tom Stellardb02094e2014-07-21 15:45:01 +0000[diff] [blame]331defm BUFFER_STORE_DWORD : MUBUF_Store_Helper <
Marek Olsakee98b112015-01-27 17:24:58 +0000[diff] [blame]332 mubuf<0x1c>, "buffer_store_dword", VGPR_32, i32, global_store
Tom Stellard754f80f2013-04-05 23:31:51 +0000[diff] [blame]333>;
334
Tom Stellardb02094e2014-07-21 15:45:01 +0000[diff] [blame]335defm BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
Marek Olsakee98b112015-01-27 17:24:58 +0000[diff] [blame]336 mubuf<0x1d>, "buffer_store_dwordx2", VReg_64, v2i32, global_store
Tom Stellard754f80f2013-04-05 23:31:51 +0000[diff] [blame]337>;
Tom Stellard556d9aa2013-06-03 17:39:37 +0000[diff] [blame]338
Tom Stellardb02094e2014-07-21 15:45:01 +0000[diff] [blame]339defm BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
Marek Olsakee98b112015-01-27 17:24:58 +0000[diff] [blame]340 mubuf<0x1e, 0x1f>, "buffer_store_dwordx4", VReg_128, v4i32, global_store
Tom Stellard556d9aa2013-06-03 17:39:37 +0000[diff] [blame]341>;
Marek Olsakee98b112015-01-27 17:24:58 +0000[diff] [blame]342
Aaron Watry81144372014-10-17 23:33:03 +0000[diff] [blame]343defm BUFFER_ATOMIC_SWAP : MUBUF_Atomic <
Marek Olsak19d9e1f2015-01-27 17:25:02 +0000[diff] [blame]344 mubuf<0x30, 0x40>, "buffer_atomic_swap", VGPR_32, i32, atomic_swap_global
Aaron Watry81144372014-10-17 23:33:03 +0000[diff] [blame]345>;
Nicolai Haehnlead636382016-03-18 16:24:31 +0000[diff] [blame]346defm BUFFER_ATOMIC_CMPSWAP : MUBUF_Atomic <
347 mubuf<0x31, 0x41>, "buffer_atomic_cmpswap", VReg_64, v2i32, null_frag
348>;
Tom Stellard7980fc82014-09-25 18:30:26 +0000[diff] [blame]349defm BUFFER_ATOMIC_ADD : MUBUF_Atomic <
Marek Olsak19d9e1f2015-01-27 17:25:02 +0000[diff] [blame]350 mubuf<0x32, 0x42>, "buffer_atomic_add", VGPR_32, i32, atomic_add_global
Tom Stellard7980fc82014-09-25 18:30:26 +0000[diff] [blame]351>;
Aaron Watry328f1ba2014-10-17 23:32:52 +0000[diff] [blame]352defm BUFFER_ATOMIC_SUB : MUBUF_Atomic <
Marek Olsak19d9e1f2015-01-27 17:25:02 +0000[diff] [blame]353 mubuf<0x33, 0x43>, "buffer_atomic_sub", VGPR_32, i32, atomic_sub_global
Aaron Watry328f1ba2014-10-17 23:32:52 +0000[diff] [blame]354>;
Marek Olsak19d9e1f2015-01-27 17:25:02 +0000[diff] [blame]355//def BUFFER_ATOMIC_RSUB : MUBUF_ <mubuf<0x34>, "buffer_atomic_rsub", []>; // isn't on CI & VI
Aaron Watry58c99922014-10-17 23:32:57 +0000[diff] [blame]356defm BUFFER_ATOMIC_SMIN : MUBUF_Atomic <
Marek Olsak19d9e1f2015-01-27 17:25:02 +0000[diff] [blame]357 mubuf<0x35, 0x44>, "buffer_atomic_smin", VGPR_32, i32, atomic_min_global
Aaron Watry58c99922014-10-17 23:32:57 +0000[diff] [blame]358>;
359defm BUFFER_ATOMIC_UMIN : MUBUF_Atomic <
Marek Olsak19d9e1f2015-01-27 17:25:02 +0000[diff] [blame]360 mubuf<0x36, 0x45>, "buffer_atomic_umin", VGPR_32, i32, atomic_umin_global
Aaron Watry58c99922014-10-17 23:32:57 +0000[diff] [blame]361>;
Aaron Watry29f295d2014-10-17 23:32:56 +0000[diff] [blame]362defm BUFFER_ATOMIC_SMAX : MUBUF_Atomic <
Marek Olsak19d9e1f2015-01-27 17:25:02 +0000[diff] [blame]363 mubuf<0x37, 0x46>, "buffer_atomic_smax", VGPR_32, i32, atomic_max_global
Aaron Watry29f295d2014-10-17 23:32:56 +0000[diff] [blame]364>;
365defm BUFFER_ATOMIC_UMAX : MUBUF_Atomic <
Marek Olsak19d9e1f2015-01-27 17:25:02 +0000[diff] [blame]366 mubuf<0x38, 0x47>, "buffer_atomic_umax", VGPR_32, i32, atomic_umax_global
Aaron Watry29f295d2014-10-17 23:32:56 +0000[diff] [blame]367>;
Aaron Watry62127802014-10-17 23:32:54 +0000[diff] [blame]368defm BUFFER_ATOMIC_AND : MUBUF_Atomic <
Marek Olsak19d9e1f2015-01-27 17:25:02 +0000[diff] [blame]369 mubuf<0x39, 0x48>, "buffer_atomic_and", VGPR_32, i32, atomic_and_global
Aaron Watry62127802014-10-17 23:32:54 +0000[diff] [blame]370>;
Aaron Watry8a911e62014-10-17 23:32:59 +0000[diff] [blame]371defm BUFFER_ATOMIC_OR : MUBUF_Atomic <
Marek Olsak19d9e1f2015-01-27 17:25:02 +0000[diff] [blame]372 mubuf<0x3a, 0x49>, "buffer_atomic_or", VGPR_32, i32, atomic_or_global
Aaron Watry8a911e62014-10-17 23:32:59 +0000[diff] [blame]373>;
Aaron Watryd672ee22014-10-17 23:33:01 +0000[diff] [blame]374defm BUFFER_ATOMIC_XOR : MUBUF_Atomic <
Marek Olsak19d9e1f2015-01-27 17:25:02 +0000[diff] [blame]375 mubuf<0x3b, 0x4a>, "buffer_atomic_xor", VGPR_32, i32, atomic_xor_global
Aaron Watryd672ee22014-10-17 23:33:01 +0000[diff] [blame]376>;
Matt Arsenaulta9dbdca2016-04-12 14:05:04 +0000[diff] [blame]377defm BUFFER_ATOMIC_INC : MUBUF_Atomic <
378 mubuf<0x3c, 0x4b>, "buffer_atomic_inc", VGPR_32, i32, atomic_inc_global
379>;
380defm BUFFER_ATOMIC_DEC : MUBUF_Atomic <
381 mubuf<0x3d, 0x4c>, "buffer_atomic_dec", VGPR_32, i32, atomic_dec_global
382>;
383
Matt Arsenault64fa2f42016-04-12 14:05:11 +0000[diff] [blame]384//def BUFFER_ATOMIC_FCMPSWAP : MUBUF_Atomic <mubuf<0x3e>, "buffer_atomic_fcmpswap", []>; // isn't on VI
385//def BUFFER_ATOMIC_FMIN : MUBUF_Atomic <mubuf<0x3f>, "buffer_atomic_fmin", []>; // isn't on VI
386//def BUFFER_ATOMIC_FMAX : MUBUF_Atomic <mubuf<0x40>, "buffer_atomic_fmax", []>; // isn't on VI
387defm BUFFER_ATOMIC_SWAP_X2 : MUBUF_Atomic <
388 mubuf<0x50, 0x60>, "buffer_atomic_swap_x2", VReg_64, i64, atomic_swap_global
389>;
Tom Stellard354a43c2016-04-01 18:27:37 +0000[diff] [blame]390defm BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_Atomic <
391 mubuf<0x51, 0x61>, "buffer_atomic_cmpswap_x2", VReg_128, v2i64, null_frag
392>;
Matt Arsenault64fa2f42016-04-12 14:05:11 +0000[diff] [blame]393defm BUFFER_ATOMIC_ADD_X2 : MUBUF_Atomic <
394 mubuf<0x52, 0x62>, "buffer_atomic_add_x2", VReg_64, i64, atomic_add_global
395>;
396defm BUFFER_ATOMIC_SUB_X2 : MUBUF_Atomic <
397 mubuf<0x53, 0x63>, "buffer_atomic_sub_x2", VReg_64, i64, atomic_sub_global
398>;
399//defm BUFFER_ATOMIC_RSUB_X2 : MUBUF_Atomic <mubuf<0x54>, "buffer_atomic_rsub_x2", []>; // isn't on CI & VI
400defm BUFFER_ATOMIC_SMIN_X2 : MUBUF_Atomic <
401 mubuf<0x55, 0x64>, "buffer_atomic_smin_x2", VReg_64, i64, atomic_min_global
402>;
403defm BUFFER_ATOMIC_UMIN_X2 : MUBUF_Atomic <
404 mubuf<0x56, 0x65>, "buffer_atomic_umin_x2", VReg_64, i64, atomic_umin_global
405>;
406defm BUFFER_ATOMIC_SMAX_X2 : MUBUF_Atomic <
407 mubuf<0x57, 0x66>, "buffer_atomic_smax_x2", VReg_64, i64, atomic_max_global
408>;
409defm BUFFER_ATOMIC_UMAX_X2 : MUBUF_Atomic <
410 mubuf<0x58, 0x67>, "buffer_atomic_umax_x2", VReg_64, i64, atomic_umax_global
411>;
412defm BUFFER_ATOMIC_AND_X2 : MUBUF_Atomic <
413 mubuf<0x59, 0x68>, "buffer_atomic_and_x2", VReg_64, i64, atomic_and_global
414>;
415defm BUFFER_ATOMIC_OR_X2 : MUBUF_Atomic <
416 mubuf<0x5a, 0x69>, "buffer_atomic_or_x2", VReg_64, i64, atomic_or_global
417>;
418defm BUFFER_ATOMIC_XOR_X2 : MUBUF_Atomic <
419 mubuf<0x5b, 0x6a>, "buffer_atomic_xor_x2", VReg_64, i64, atomic_xor_global
420>;
Matt Arsenaulta9dbdca2016-04-12 14:05:04 +0000[diff] [blame]421defm BUFFER_ATOMIC_INC_X2 : MUBUF_Atomic <
422 mubuf<0x5c, 0x6b>, "buffer_atomic_inc_x2", VReg_64, i64, atomic_inc_global
423>;
424defm BUFFER_ATOMIC_DEC_X2 : MUBUF_Atomic <
425 mubuf<0x5d, 0x6c>, "buffer_atomic_dec_x2", VReg_64, i64, atomic_dec_global
426>;
Marek Olsak19d9e1f2015-01-27 17:25:02 +0000[diff] [blame]427//def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <mubuf<0x5e>, "buffer_atomic_fcmpswap_x2", []>; // isn't on VI
428//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <mubuf<0x5f>, "buffer_atomic_fmin_x2", []>; // isn't on VI
429//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <mubuf<0x60>, "buffer_atomic_fmax_x2", []>; // isn't on VI
Matt Arsenaultd6adfb42015-09-24 19:52:21 +0000[diff] [blame]430
Tom Stellarde1818af2016-02-18 03:42:32 +0000[diff] [blame]431let SubtargetPredicate = isSI, DisableVIDecoder = 1 in {
Matt Arsenaultd6adfb42015-09-24 19:52:21 +0000[diff] [blame]432defm BUFFER_WBINVL1_SC : MUBUF_Invalidate <mubuf<0x70>, "buffer_wbinvl1_sc", int_amdgcn_buffer_wbinvl1_sc>; // isn't on CI & VI
433}
434
435defm BUFFER_WBINVL1 : MUBUF_Invalidate <mubuf<0x71, 0x3e>, "buffer_wbinvl1", int_amdgcn_buffer_wbinvl1>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]436
Tom Stellard8d6d4492014-04-22 16:33:57 +0000[diff] [blame]437//===----------------------------------------------------------------------===//
438// MTBUF Instructions
439//===----------------------------------------------------------------------===//
440
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]441//def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "tbuffer_load_format_x", []>;
442//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "tbuffer_load_format_xy", []>;
443//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "tbuffer_load_format_xyz", []>;
444defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "tbuffer_load_format_xyzw", VReg_128>;
Tom Stellard45c0b3a2015-01-07 20:59:25 +0000[diff] [blame]445defm TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "tbuffer_store_format_x", VGPR_32>;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]446defm TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "tbuffer_store_format_xy", VReg_64>;
447defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "tbuffer_store_format_xyz", VReg_128>;
448defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "tbuffer_store_format_xyzw", VReg_128>;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]449
Tom Stellard8d6d4492014-04-22 16:33:57 +0000[diff] [blame]450//===----------------------------------------------------------------------===//
451// MIMG Instructions
452//===----------------------------------------------------------------------===//
Tom Stellard89093802013-02-07 19:39:40 +0000[diff] [blame]453
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]454defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load">;
455defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip">;
456//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"image_load_pck", 0x00000002>;
457//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"image_load_pck_sgn", 0x00000003>;
458//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"image_load_mip_pck", 0x00000004>;
459//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"image_load_mip_pck_sgn", 0x00000005>;
Nicolai Haehnlef2c64db2016-02-18 16:44:18 +0000[diff] [blame]460defm IMAGE_STORE : MIMG_Store <0x00000008, "image_store">;
461defm IMAGE_STORE_MIP : MIMG_Store <0x00000009, "image_store_mip">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]462//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"image_store_pck", 0x0000000a>;
463//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"image_store_mip_pck", 0x0000000b>;
464defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo">;
Nikolay Haustov5bf46ac12016-03-04 10:39:50 +0000[diff] [blame]465defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimg<0x0f, 0x10>, "image_atomic_swap">;
466defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimg<0x10, 0x11>, "image_atomic_cmpswap", VReg_64>;
467defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimg<0x11, 0x12>, "image_atomic_add">;
468defm IMAGE_ATOMIC_SUB : MIMG_Atomic <mimg<0x12, 0x13>, "image_atomic_sub">;
469//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>; -- not on VI
470defm IMAGE_ATOMIC_SMIN : MIMG_Atomic <mimg<0x14>, "image_atomic_smin">;
471defm IMAGE_ATOMIC_UMIN : MIMG_Atomic <mimg<0x15>, "image_atomic_umin">;
472defm IMAGE_ATOMIC_SMAX : MIMG_Atomic <mimg<0x16>, "image_atomic_smax">;
473defm IMAGE_ATOMIC_UMAX : MIMG_Atomic <mimg<0x17>, "image_atomic_umax">;
474defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimg<0x18>, "image_atomic_and">;
475defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimg<0x19>, "image_atomic_or">;
476defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimg<0x1a>, "image_atomic_xor">;
477defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimg<0x1b>, "image_atomic_inc">;
478defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimg<0x1c>, "image_atomic_dec">;
479//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d>; -- not on VI
480//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>; -- not on VI
481//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>; -- not on VI
Michel Danzer494391b2015-02-06 02:51:20 +0000[diff] [blame]482defm IMAGE_SAMPLE : MIMG_Sampler_WQM <0x00000020, "image_sample">;
483defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <0x00000021, "image_sample_cl">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]484defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "image_sample_d">;
485defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "image_sample_d_cl">;
486defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "image_sample_l">;
Michel Danzer494391b2015-02-06 02:51:20 +0000[diff] [blame]487defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <0x00000025, "image_sample_b">;
488defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <0x00000026, "image_sample_b_cl">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]489defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "image_sample_lz">;
Michel Danzer494391b2015-02-06 02:51:20 +0000[diff] [blame]490defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <0x00000028, "image_sample_c">;
491defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <0x00000029, "image_sample_c_cl">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]492defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "image_sample_c_d">;
493defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "image_sample_c_d_cl">;
494defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "image_sample_c_l">;
Michel Danzer494391b2015-02-06 02:51:20 +0000[diff] [blame]495defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <0x0000002d, "image_sample_c_b">;
496defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <0x0000002e, "image_sample_c_b_cl">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]497defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "image_sample_c_lz">;
Michel Danzer494391b2015-02-06 02:51:20 +0000[diff] [blame]498defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <0x00000030, "image_sample_o">;
499defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <0x00000031, "image_sample_cl_o">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]500defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "image_sample_d_o">;
501defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "image_sample_d_cl_o">;
502defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "image_sample_l_o">;
Michel Danzer494391b2015-02-06 02:51:20 +0000[diff] [blame]503defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <0x00000035, "image_sample_b_o">;
504defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <0x00000036, "image_sample_b_cl_o">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]505defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "image_sample_lz_o">;
Michel Danzer494391b2015-02-06 02:51:20 +0000[diff] [blame]506defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <0x00000038, "image_sample_c_o">;
507defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <0x00000039, "image_sample_c_cl_o">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]508defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "image_sample_c_d_o">;
509defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "image_sample_c_d_cl_o">;
510defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "image_sample_c_l_o">;
Michel Danzer494391b2015-02-06 02:51:20 +0000[diff] [blame]511defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <0x0000003d, "image_sample_c_b_o">;
512defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <0x0000003e, "image_sample_c_b_cl_o">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]513defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "image_sample_c_lz_o">;
Michel Danzer494391b2015-02-06 02:51:20 +0000[diff] [blame]514defm IMAGE_GATHER4 : MIMG_Gather_WQM <0x00000040, "image_gather4">;
515defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <0x00000041, "image_gather4_cl">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]516defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "image_gather4_l">;
Michel Danzer494391b2015-02-06 02:51:20 +0000[diff] [blame]517defm IMAGE_GATHER4_B : MIMG_Gather_WQM <0x00000045, "image_gather4_b">;
518defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <0x00000046, "image_gather4_b_cl">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]519defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "image_gather4_lz">;
Michel Danzer494391b2015-02-06 02:51:20 +0000[diff] [blame]520defm IMAGE_GATHER4_C : MIMG_Gather_WQM <0x00000048, "image_gather4_c">;
521defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <0x00000049, "image_gather4_c_cl">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]522defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "image_gather4_c_l">;
Michel Danzer494391b2015-02-06 02:51:20 +0000[diff] [blame]523defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <0x0000004d, "image_gather4_c_b">;
524defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <0x0000004e, "image_gather4_c_b_cl">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]525defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "image_gather4_c_lz">;
Michel Danzer494391b2015-02-06 02:51:20 +0000[diff] [blame]526defm IMAGE_GATHER4_O : MIMG_Gather_WQM <0x00000050, "image_gather4_o">;
527defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <0x00000051, "image_gather4_cl_o">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]528defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "image_gather4_l_o">;
Michel Danzer494391b2015-02-06 02:51:20 +0000[diff] [blame]529defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <0x00000055, "image_gather4_b_o">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]530defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "image_gather4_b_cl_o">;
531defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "image_gather4_lz_o">;
Michel Danzer494391b2015-02-06 02:51:20 +0000[diff] [blame]532defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <0x00000058, "image_gather4_c_o">;
533defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <0x00000059, "image_gather4_c_cl_o">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]534defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "image_gather4_c_l_o">;
Michel Danzer494391b2015-02-06 02:51:20 +0000[diff] [blame]535defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <0x0000005d, "image_gather4_c_b_o">;
536defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <0x0000005e, "image_gather4_c_b_cl_o">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]537defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "image_gather4_c_lz_o">;
Michel Danzer494391b2015-02-06 02:51:20 +0000[diff] [blame]538defm IMAGE_GET_LOD : MIMG_Sampler_WQM <0x00000060, "image_get_lod">;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]539defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "image_sample_cd">;
540defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "image_sample_cd_cl">;
541defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "image_sample_c_cd">;
542defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "image_sample_c_cd_cl">;
543defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "image_sample_cd_o">;
544defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "image_sample_cd_cl_o">;
545defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "image_sample_c_cd_o">;
546defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "image_sample_c_cd_cl_o">;
547//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>;
548//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]549
Tom Stellard8d6d4492014-04-22 16:33:57 +0000[diff] [blame]550//===----------------------------------------------------------------------===//
551// VOP1 Instructions
552//===----------------------------------------------------------------------===//
553
Tom Stellard88e0b252015-10-06 15:57:53 +0000[diff] [blame]554let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in {
555defm V_NOP : VOP1Inst <vop1<0x0>, "v_nop", VOP_NONE>;
Tom Stellardc34c37a2015-02-18 16:08:15 +0000[diff] [blame]556}
Christian Konig76edd4f2013-02-26 17:52:29 +0000[diff] [blame]557
Matthias Braune1a67412015-04-24 00:25:50 +0000[diff] [blame]558let isMoveImm = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in {
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]559defm V_MOV_B32 : VOP1Inst <vop1<0x1>, "v_mov_b32", VOP_I32_I32>;
Matt Arsenaultf2733702014-07-30 03:18:57 +0000[diff] [blame]560} // End isMoveImm = 1
Christian Konig76edd4f2013-02-26 17:52:29 +0000[diff] [blame]561
Tom Stellardfbe435d2014-03-17 17:03:51 +0000[diff] [blame]562let Uses = [EXEC] in {
563
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]564// FIXME: Specify SchedRW for READFIRSTLANE_B32
565
Tom Stellardfbe435d2014-03-17 17:03:51 +0000[diff] [blame]566def V_READFIRSTLANE_B32 : VOP1 <
567 0x00000002,
568 (outs SReg_32:$vdst),
Changpeng Fang75f09682016-08-24 20:35:23 +0000[diff] [blame]569 (ins VGPR_32:$src0),
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]570 "v_readfirstlane_b32 $vdst, $src0",
Changpeng Fang75f09682016-08-24 20:35:23 +0000[diff] [blame]571 [(set i32:$vdst, (int_amdgcn_readfirstlane i32:$src0))]
Matt Arsenault42345422016-05-11 00:32:31 +0000[diff] [blame]572> {
573 let isConvergent = 1;
574}
Tom Stellardfbe435d2014-03-17 17:03:51 +0000[diff] [blame]575
576}
577
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]578let SchedRW = [WriteQuarterRate32] in {
579
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]580defm V_CVT_I32_F64 : VOP1Inst <vop1<0x3>, "v_cvt_i32_f64",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]581 VOP_I32_F64, fp_to_sint
Niels Ole Salscheider4715d882013-08-08 16:06:08 +0000[diff] [blame]582>;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]583defm V_CVT_F64_I32 : VOP1Inst <vop1<0x4>, "v_cvt_f64_i32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]584 VOP_F64_I32, sint_to_fp
Niels Ole Salscheider4715d882013-08-08 16:06:08 +0000[diff] [blame]585>;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]586defm V_CVT_F32_I32 : VOP1Inst <vop1<0x5>, "v_cvt_f32_i32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]587 VOP_F32_I32, sint_to_fp
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]588>;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]589defm V_CVT_F32_U32 : VOP1Inst <vop1<0x6>, "v_cvt_f32_u32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]590 VOP_F32_I32, uint_to_fp
Tom Stellardc932d732013-05-06 23:02:07 +0000[diff] [blame]591>;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]592defm V_CVT_U32_F32 : VOP1Inst <vop1<0x7>, "v_cvt_u32_f32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]593 VOP_I32_F32, fp_to_uint
Tom Stellard73c31d52013-08-14 22:21:57 +0000[diff] [blame]594>;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]595defm V_CVT_I32_F32 : VOP1Inst <vop1<0x8>, "v_cvt_i32_f32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]596 VOP_I32_F32, fp_to_sint
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]597>;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]598defm V_CVT_F16_F32 : VOP1Inst <vop1<0xa>, "v_cvt_f16_f32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]599 VOP_I32_F32, fp_to_f16
Matt Arsenaultb0df9252014-07-10 03:22:20 +0000[diff] [blame]600>;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]601defm V_CVT_F32_F16 : VOP1Inst <vop1<0xb>, "v_cvt_f32_f16",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]602 VOP_F32_I32, f16_to_fp
Matt Arsenaultb0df9252014-07-10 03:22:20 +0000[diff] [blame]603>;
Matt Arsenaulteeb2a7e2015-01-15 23:58:35 +0000[diff] [blame]604defm V_CVT_RPI_I32_F32 : VOP1Inst <vop1<0xc>, "v_cvt_rpi_i32_f32",
605 VOP_I32_F32, cvt_rpi_i32_f32>;
606defm V_CVT_FLR_I32_F32 : VOP1Inst <vop1<0xd>, "v_cvt_flr_i32_f32",
607 VOP_I32_F32, cvt_flr_i32_f32>;
Tom Stellardc34c37a2015-02-18 16:08:15 +0000[diff] [blame]608defm V_CVT_OFF_F32_I4 : VOP1Inst <vop1<0x0e>, "v_cvt_off_f32_i4", VOP_F32_I32>;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]609defm V_CVT_F32_F64 : VOP1Inst <vop1<0xf>, "v_cvt_f32_f64",
Michael Kuperstein2bc3d4d2016-08-18 20:08:15 +0000[diff] [blame]610 VOP_F32_F64, fpround
Niels Ole Salscheider719fbc92013-08-08 16:06:15 +0000[diff] [blame]611>;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]612defm V_CVT_F64_F32 : VOP1Inst <vop1<0x10>, "v_cvt_f64_f32",
Michael Kuperstein2bc3d4d2016-08-18 20:08:15 +0000[diff] [blame]613 VOP_F64_F32, fpextend
Niels Ole Salscheider719fbc92013-08-08 16:06:15 +0000[diff] [blame]614>;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]615defm V_CVT_F32_UBYTE0 : VOP1Inst <vop1<0x11>, "v_cvt_f32_ubyte0",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]616 VOP_F32_I32, AMDGPUcvt_f32_ubyte0
Matt Arsenault364a6742014-06-11 17:50:44 +0000[diff] [blame]617>;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]618defm V_CVT_F32_UBYTE1 : VOP1Inst <vop1<0x12>, "v_cvt_f32_ubyte1",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]619 VOP_F32_I32, AMDGPUcvt_f32_ubyte1
Matt Arsenault364a6742014-06-11 17:50:44 +0000[diff] [blame]620>;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]621defm V_CVT_F32_UBYTE2 : VOP1Inst <vop1<0x13>, "v_cvt_f32_ubyte2",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]622 VOP_F32_I32, AMDGPUcvt_f32_ubyte2
Matt Arsenault364a6742014-06-11 17:50:44 +0000[diff] [blame]623>;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]624defm V_CVT_F32_UBYTE3 : VOP1Inst <vop1<0x14>, "v_cvt_f32_ubyte3",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]625 VOP_F32_I32, AMDGPUcvt_f32_ubyte3
Matt Arsenault364a6742014-06-11 17:50:44 +0000[diff] [blame]626>;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]627defm V_CVT_U32_F64 : VOP1Inst <vop1<0x15>, "v_cvt_u32_f64",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]628 VOP_I32_F64, fp_to_uint
Matt Arsenaultc3a73c32014-05-22 03:20:30 +0000[diff] [blame]629>;
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]630defm V_CVT_F64_U32 : VOP1Inst <vop1<0x16>, "v_cvt_f64_u32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]631 VOP_F64_I32, uint_to_fp
Matt Arsenaultc3a73c32014-05-22 03:20:30 +0000[diff] [blame]632>;
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]633
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]634} // End SchedRW = [WriteQuarterRate32]
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]635
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]636defm V_FRACT_F32 : VOP1Inst <vop1<0x20, 0x1b>, "v_fract_f32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]637 VOP_F32_F32, AMDGPUfract
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]638>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]639defm V_TRUNC_F32 : VOP1Inst <vop1<0x21, 0x1c>, "v_trunc_f32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]640 VOP_F32_F32, ftrunc
Tom Stellard9b3d2532013-05-06 23:02:00 +0000[diff] [blame]641>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]642defm V_CEIL_F32 : VOP1Inst <vop1<0x22, 0x1d>, "v_ceil_f32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]643 VOP_F32_F32, fceil
Michel Danzerc3ea4042013-02-22 11:22:49 +0000[diff] [blame]644>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]645defm V_RNDNE_F32 : VOP1Inst <vop1<0x23, 0x1e>, "v_rndne_f32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]646 VOP_F32_F32, frint
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]647>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]648defm V_FLOOR_F32 : VOP1Inst <vop1<0x24, 0x1f>, "v_floor_f32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]649 VOP_F32_F32, ffloor
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]650>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]651defm V_EXP_F32 : VOP1Inst <vop1<0x25, 0x20>, "v_exp_f32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]652 VOP_F32_F32, fexp2
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]653>;
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]654
655let SchedRW = [WriteQuarterRate32] in {
656
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]657defm V_LOG_F32 : VOP1Inst <vop1<0x27, 0x21>, "v_log_f32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]658 VOP_F32_F32, flog2
Michel Danzer349cabe2013-02-07 14:55:16 +0000[diff] [blame]659>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]660defm V_RCP_F32 : VOP1Inst <vop1<0x2a, 0x22>, "v_rcp_f32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]661 VOP_F32_F32, AMDGPUrcp
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]662>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]663defm V_RCP_IFLAG_F32 : VOP1Inst <vop1<0x2b, 0x23>, "v_rcp_iflag_f32",
664 VOP_F32_F32
Matt Arsenault257d48d2014-06-24 22:13:39 +0000[diff] [blame]665>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]666defm V_RSQ_F32 : VOP1Inst <vop1<0x2e, 0x24>, "v_rsq_f32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]667 VOP_F32_F32, AMDGPUrsq
Matt Arsenault15130462014-06-05 00:15:55 +0000[diff] [blame]668>;
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]669
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]670} // End SchedRW = [WriteQuarterRate32]
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]671
672let SchedRW = [WriteDouble] in {
673
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]674defm V_RCP_F64 : VOP1Inst <vop1<0x2f, 0x25>, "v_rcp_f64",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]675 VOP_F64_F64, AMDGPUrcp
Tom Stellard7512c082013-07-12 18:14:56 +0000[diff] [blame]676>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]677defm V_RSQ_F64 : VOP1Inst <vop1<0x31, 0x26>, "v_rsq_f64",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]678 VOP_F64_F64, AMDGPUrsq
Matt Arsenault15130462014-06-05 00:15:55 +0000[diff] [blame]679>;
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]680
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]681} // End SchedRW = [WriteDouble];
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]682
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]683defm V_SQRT_F32 : VOP1Inst <vop1<0x33, 0x27>, "v_sqrt_f32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]684 VOP_F32_F32, fsqrt
Tom Stellard8ed7b452013-07-12 18:15:13 +0000[diff] [blame]685>;
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]686
687let SchedRW = [WriteDouble] in {
688
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]689defm V_SQRT_F64 : VOP1Inst <vop1<0x34, 0x28>, "v_sqrt_f64",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]690 VOP_F64_F64, fsqrt
Tom Stellard8ed7b452013-07-12 18:15:13 +0000[diff] [blame]691>;
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]692
Matt Arsenaulte8df8792015-08-22 00:50:41 +0000[diff] [blame]693} // End SchedRW = [WriteDouble]
694
695let SchedRW = [WriteQuarterRate32] in {
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]696
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]697defm V_SIN_F32 : VOP1Inst <vop1<0x35, 0x29>, "v_sin_f32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]698 VOP_F32_F32, AMDGPUsin
Matt Arsenaultad14ce82014-07-19 18:44:39 +0000[diff] [blame]699>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]700defm V_COS_F32 : VOP1Inst <vop1<0x36, 0x2a>, "v_cos_f32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]701 VOP_F32_F32, AMDGPUcos
Matt Arsenaultad14ce82014-07-19 18:44:39 +0000[diff] [blame]702>;
Matt Arsenaulte8df8792015-08-22 00:50:41 +0000[diff] [blame]703
704} // End SchedRW = [WriteQuarterRate32]
705
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]706defm V_NOT_B32 : VOP1Inst <vop1<0x37, 0x2b>, "v_not_b32", VOP_I32_I32>;
707defm V_BFREV_B32 : VOP1Inst <vop1<0x38, 0x2c>, "v_bfrev_b32", VOP_I32_I32>;
708defm V_FFBH_U32 : VOP1Inst <vop1<0x39, 0x2d>, "v_ffbh_u32", VOP_I32_I32>;
709defm V_FFBL_B32 : VOP1Inst <vop1<0x3a, 0x2e>, "v_ffbl_b32", VOP_I32_I32>;
710defm V_FFBH_I32 : VOP1Inst <vop1<0x3b, 0x2f>, "v_ffbh_i32", VOP_I32_I32>;
Tom Stellardc34c37a2015-02-18 16:08:15 +0000[diff] [blame]711defm V_FREXP_EXP_I32_F64 : VOP1Inst <vop1<0x3c,0x30>, "v_frexp_exp_i32_f64",
Matt Arsenault2fe4fbc2016-03-30 22:28:52 +0000[diff] [blame]712 VOP_I32_F64, int_amdgcn_frexp_exp
Tom Stellardc34c37a2015-02-18 16:08:15 +0000[diff] [blame]713>;
Matt Arsenaulte8df8792015-08-22 00:50:41 +0000[diff] [blame]714
715let SchedRW = [WriteDoubleAdd] in {
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]716defm V_FREXP_MANT_F64 : VOP1Inst <vop1<0x3d, 0x31>, "v_frexp_mant_f64",
Matt Arsenaultb96b5732016-03-21 16:11:05 +0000[diff] [blame]717 VOP_F64_F64, int_amdgcn_frexp_mant
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]718>;
Matt Arsenaulte8df8792015-08-22 00:50:41 +0000[diff] [blame]719
720defm V_FRACT_F64 : VOP1Inst <vop1<0x3e, 0x32>, "v_fract_f64",
Matt Arsenault74015162016-05-28 00:19:52 +0000[diff] [blame]721 VOP_F64_F64, AMDGPUfract
Matt Arsenaulte8df8792015-08-22 00:50:41 +0000[diff] [blame]722>;
723} // End SchedRW = [WriteDoubleAdd]
724
725
Tom Stellardc34c37a2015-02-18 16:08:15 +0000[diff] [blame]726defm V_FREXP_EXP_I32_F32 : VOP1Inst <vop1<0x3f, 0x33>, "v_frexp_exp_i32_f32",
Matt Arsenault2fe4fbc2016-03-30 22:28:52 +0000[diff] [blame]727 VOP_I32_F32, int_amdgcn_frexp_exp
Tom Stellardc34c37a2015-02-18 16:08:15 +0000[diff] [blame]728>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]729defm V_FREXP_MANT_F32 : VOP1Inst <vop1<0x40, 0x34>, "v_frexp_mant_f32",
Matt Arsenaultb96b5732016-03-21 16:11:05 +0000[diff] [blame]730 VOP_F32_F32, int_amdgcn_frexp_mant
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]731>;
Tom Stellard88e0b252015-10-06 15:57:53 +0000[diff] [blame]732let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in {
Sam Kolton3025e7f2016-04-26 13:33:56 +0000[diff] [blame]733defm V_CLREXCP : VOP1Inst <vop1<0x41,0x35>, "v_clrexcp", VOP_NO_EXT<VOP_NONE>>;
Tom Stellardc34c37a2015-02-18 16:08:15 +0000[diff] [blame]734}
Matt Arsenaultfc0ad422015-10-07 17:46:32 +0000[diff] [blame]735
736let Uses = [M0, EXEC] in {
Matt Arsenaultcb540bc2016-07-19 00:35:03 +0000[diff] [blame]737// v_movreld_b32 is a special case because the destination output
738 // register is really a source. It isn't actually read (but may be
739 // written), and is only to provide the base register to start
740 // indexing from. Tablegen seems to not let you define an implicit
741 // virtual register output for the super register being written into,
742 // so this must have an implicit def of the register added to it.
743defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42, 0x36>, "v_movreld_b32", VOP_MOVRELD>;
744defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43, 0x37>, "v_movrels_b32", VOP_I32_VI32_NO_EXT>;
Sam Kolton3025e7f2016-04-26 13:33:56 +0000[diff] [blame]745defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44, 0x38>, "v_movrelsd_b32", VOP_NO_EXT<VOP_I32_I32>>;
Matt Arsenaultcb540bc2016-07-19 00:35:03 +0000[diff] [blame]746
Matt Arsenaultfc0ad422015-10-07 17:46:32 +0000[diff] [blame]747} // End Uses = [M0, EXEC]
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]748
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]749// These instruction only exist on SI and CI
750let SubtargetPredicate = isSICI in {
751
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]752let SchedRW = [WriteQuarterRate32] in {
753
Tom Stellard4b3e7552015-04-23 19:33:52 +0000[diff] [blame]754defm V_MOV_FED_B32 : VOP1InstSI <vop1<0x9>, "v_mov_fed_b32", VOP_I32_I32>;
Matt Arsenaultce56a0e2016-02-13 01:19:56 +0000[diff] [blame]755defm V_LOG_CLAMP_F32 : VOP1InstSI <vop1<0x26>, "v_log_clamp_f32",
756 VOP_F32_F32, int_amdgcn_log_clamp>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]757defm V_RCP_CLAMP_F32 : VOP1InstSI <vop1<0x28>, "v_rcp_clamp_f32", VOP_F32_F32>;
Matt Arsenault32fc5272016-07-26 16:45:45 +0000[diff] [blame]758defm V_RCP_LEGACY_F32 : VOP1InstSI <vop1<0x29>, "v_rcp_legacy_f32",
759 VOP_F32_F32, AMDGPUrcp_legacy>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]760defm V_RSQ_CLAMP_F32 : VOP1InstSI <vop1<0x2c>, "v_rsq_clamp_f32",
Matt Arsenault79963e82016-02-13 01:03:00 +0000[diff] [blame]761 VOP_F32_F32, AMDGPUrsq_clamp
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]762>;
763defm V_RSQ_LEGACY_F32 : VOP1InstSI <vop1<0x2d>, "v_rsq_legacy_f32",
764 VOP_F32_F32, AMDGPUrsq_legacy
765>;
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]766
Matt Arsenaulte8df8792015-08-22 00:50:41 +0000[diff] [blame]767} // End SchedRW = [WriteQuarterRate32]
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]768
769let SchedRW = [WriteDouble] in {
770
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]771defm V_RCP_CLAMP_F64 : VOP1InstSI <vop1<0x30>, "v_rcp_clamp_f64", VOP_F64_F64>;
772defm V_RSQ_CLAMP_F64 : VOP1InstSI <vop1<0x32>, "v_rsq_clamp_f64",
Matt Arsenault79963e82016-02-13 01:03:00 +0000[diff] [blame]773 VOP_F64_F64, AMDGPUrsq_clamp
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]774>;
775
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]776} // End SchedRW = [WriteDouble]
777
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]778} // End SubtargetPredicate = isSICI
Tom Stellard8d6d4492014-04-22 16:33:57 +0000[diff] [blame]779
780//===----------------------------------------------------------------------===//
781// VINTRP Instructions
782//===----------------------------------------------------------------------===//
783
Matt Arsenault80f766a2015-09-10 01:23:28 +0000[diff] [blame]784let Uses = [M0, EXEC] in {
Tom Stellard2a9d9472015-05-12 15:00:46 +0000[diff] [blame]785
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]786// FIXME: Specify SchedRW for VINTRP insturctions.
Tom Stellardec87f842015-05-25 16:15:54 +0000[diff] [blame]787
788multiclass V_INTERP_P1_F32_m : VINTRP_m <
789 0x00000000,
Tom Stellard45c0b3a2015-01-07 20:59:25 +0000[diff] [blame]790 (outs VGPR_32:$dst),
Tom Stellard2a9d9472015-05-12 15:00:46 +0000[diff] [blame]791 (ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr),
792 "v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [m0]",
793 [(set f32:$dst, (AMDGPUinterp_p1 i32:$i, (i32 imm:$attr_chan),
Tom Stellardec87f842015-05-25 16:15:54 +0000[diff] [blame]794 (i32 imm:$attr)))]
795>;
796
797let OtherPredicates = [has32BankLDS] in {
798
799defm V_INTERP_P1_F32 : V_INTERP_P1_F32_m;
800
801} // End OtherPredicates = [has32BankLDS]
802
Tom Stellarde1818af2016-02-18 03:42:32 +0000[diff] [blame]803let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1 in {
Tom Stellardec87f842015-05-25 16:15:54 +0000[diff] [blame]804
805defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m;
806
Tom Stellarde1818af2016-02-18 03:42:32 +0000[diff] [blame]807} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]808
Tom Stellard50828162015-05-25 16:15:56 +0000[diff] [blame]809let DisableEncoding = "$src0", Constraints = "$src0 = $dst" in {
810
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]811defm V_INTERP_P2_F32 : VINTRP_m <
Tom Stellardc70cf902015-05-25 16:15:50 +0000[diff] [blame]812 0x00000001,
Tom Stellard45c0b3a2015-01-07 20:59:25 +0000[diff] [blame]813 (outs VGPR_32:$dst),
Tom Stellard2a9d9472015-05-12 15:00:46 +0000[diff] [blame]814 (ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr),
815 "v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [m0]",
816 [(set f32:$dst, (AMDGPUinterp_p2 f32:$src0, i32:$j, (i32 imm:$attr_chan),
Tom Stellard50828162015-05-25 16:15:56 +0000[diff] [blame]817 (i32 imm:$attr)))]>;
818
819} // End DisableEncoding = "$src0", Constraints = "$src0 = $dst"
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]820
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]821defm V_INTERP_MOV_F32 : VINTRP_m <
Tom Stellardc70cf902015-05-25 16:15:50 +0000[diff] [blame]822 0x00000002,
Tom Stellard45c0b3a2015-01-07 20:59:25 +0000[diff] [blame]823 (outs VGPR_32:$dst),
Tom Stellard2a9d9472015-05-12 15:00:46 +0000[diff] [blame]824 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr),
825 "v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [m0]",
826 [(set f32:$dst, (AMDGPUinterp_mov (i32 imm:$src0), (i32 imm:$attr_chan),
827 (i32 imm:$attr)))]>;
828
Matt Arsenault80f766a2015-09-10 01:23:28 +0000[diff] [blame]829} // End Uses = [M0, EXEC]
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]830
Tom Stellard8d6d4492014-04-22 16:33:57 +0000[diff] [blame]831//===----------------------------------------------------------------------===//
832// VOP2 Instructions
833//===----------------------------------------------------------------------===//
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]834
Artem Tamazov13548772016-06-06 15:23:43 +0000[diff] [blame]835defm V_CNDMASK_B32 : VOP2eInst <vop2<0x0, 0x0>, "v_cndmask_b32",
836 VOP2e_I32_I32_I32_I1
837>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]838
839let isCommutable = 1 in {
840defm V_ADD_F32 : VOP2Inst <vop2<0x3, 0x1>, "v_add_f32",
841 VOP_F32_F32_F32, fadd
842>;
843
844defm V_SUB_F32 : VOP2Inst <vop2<0x4, 0x2>, "v_sub_f32", VOP_F32_F32_F32, fsub>;
845defm V_SUBREV_F32 : VOP2Inst <vop2<0x5, 0x3>, "v_subrev_f32",
846 VOP_F32_F32_F32, null_frag, "v_sub_f32"
847>;
848} // End isCommutable = 1
849
850let isCommutable = 1 in {
851
852defm V_MUL_LEGACY_F32 : VOP2Inst <vop2<0x7, 0x4>, "v_mul_legacy_f32",
Matt Arsenault32fc5272016-07-26 16:45:45 +0000[diff] [blame]853 VOP_F32_F32_F32, AMDGPUfmul_legacy
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]854>;
855
856defm V_MUL_F32 : VOP2Inst <vop2<0x8, 0x5>, "v_mul_f32",
857 VOP_F32_F32_F32, fmul
858>;
859
860defm V_MUL_I32_I24 : VOP2Inst <vop2<0x9, 0x6>, "v_mul_i32_i24",
861 VOP_I32_I32_I32, AMDGPUmul_i24
862>;
Tom Stellard894b9882015-02-18 16:08:14 +0000[diff] [blame]863
864defm V_MUL_HI_I32_I24 : VOP2Inst <vop2<0xa,0x7>, "v_mul_hi_i32_i24",
Matt Arsenault2712d4a2016-08-27 01:32:27 +0000[diff] [blame]865 VOP_I32_I32_I32, AMDGPUmulhi_i24
Tom Stellard894b9882015-02-18 16:08:14 +0000[diff] [blame]866>;
867
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]868defm V_MUL_U32_U24 : VOP2Inst <vop2<0xb, 0x8>, "v_mul_u32_u24",
869 VOP_I32_I32_I32, AMDGPUmul_u24
870>;
Tom Stellard894b9882015-02-18 16:08:14 +0000[diff] [blame]871
872defm V_MUL_HI_U32_U24 : VOP2Inst <vop2<0xc,0x9>, "v_mul_hi_u32_u24",
Matt Arsenault2712d4a2016-08-27 01:32:27 +0000[diff] [blame]873 VOP_I32_I32_I32, AMDGPUmulhi_u24
Tom Stellard894b9882015-02-18 16:08:14 +0000[diff] [blame]874>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]875
876defm V_MIN_F32 : VOP2Inst <vop2<0xf, 0xa>, "v_min_f32", VOP_F32_F32_F32,
877 fminnum>;
878defm V_MAX_F32 : VOP2Inst <vop2<0x10, 0xb>, "v_max_f32", VOP_F32_F32_F32,
879 fmaxnum>;
Marek Olsak24ae2cd2015-02-03 21:53:08 +0000[diff] [blame]880defm V_MIN_I32 : VOP2Inst <vop2<0x11, 0xc>, "v_min_i32", VOP_I32_I32_I32>;
881defm V_MAX_I32 : VOP2Inst <vop2<0x12, 0xd>, "v_max_i32", VOP_I32_I32_I32>;
882defm V_MIN_U32 : VOP2Inst <vop2<0x13, 0xe>, "v_min_u32", VOP_I32_I32_I32>;
883defm V_MAX_U32 : VOP2Inst <vop2<0x14, 0xf>, "v_max_u32", VOP_I32_I32_I32>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]884
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]885defm V_LSHRREV_B32 : VOP2Inst <
886 vop2<0x16, 0x10>, "v_lshrrev_b32", VOP_I32_I32_I32, null_frag,
Marek Olsak7585a292015-02-03 17:38:05 +0000[diff] [blame]887 "v_lshr_b32"
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]888>;
889
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]890defm V_ASHRREV_I32 : VOP2Inst <
891 vop2<0x18, 0x11>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag,
Marek Olsak7585a292015-02-03 17:38:05 +0000[diff] [blame]892 "v_ashr_i32"
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]893>;
894
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]895defm V_LSHLREV_B32 : VOP2Inst <
896 vop2<0x1a, 0x12>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag,
Marek Olsak7585a292015-02-03 17:38:05 +0000[diff] [blame]897 "v_lshl_b32"
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]898>;
899
Marek Olsak24ae2cd2015-02-03 21:53:08 +0000[diff] [blame]900defm V_AND_B32 : VOP2Inst <vop2<0x1b, 0x13>, "v_and_b32", VOP_I32_I32_I32>;
901defm V_OR_B32 : VOP2Inst <vop2<0x1c, 0x14>, "v_or_b32", VOP_I32_I32_I32>;
902defm V_XOR_B32 : VOP2Inst <vop2<0x1d, 0x15>, "v_xor_b32", VOP_I32_I32_I32>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]903
Tom Stellardcc4c8712016-02-16 18:14:56 +0000[diff] [blame]904let Constraints = "$vdst = $src2", DisableEncoding="$src2",
Tom Stellarddb5a11f2015-07-13 15:47:57 +0000[diff] [blame]905 isConvertibleToThreeAddress = 1 in {
906defm V_MAC_F32 : VOP2Inst <vop2<0x1f, 0x16>, "v_mac_f32", VOP_MAC>;
907}
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]908} // End isCommutable = 1
909
Nikolay Haustov65607812016-03-11 09:27:25 +0000[diff] [blame]910defm V_MADMK_F32 : VOP2MADK <vop2<0x20, 0x17>, "v_madmk_f32", VOP_MADMK>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]911
912let isCommutable = 1 in {
Nikolay Haustov65607812016-03-11 09:27:25 +0000[diff] [blame]913defm V_MADAK_F32 : VOP2MADK <vop2<0x21, 0x18>, "v_madak_f32", VOP_MADAK>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]914} // End isCommutable = 1
915
Matt Arsenault86d336e2015-09-08 21:15:00 +0000[diff] [blame]916let isCommutable = 1 in {
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]917// No patterns so that the scalar instructions are always selected.
918// The scalar versions will be replaced with vector when needed later.
919
920// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in VI,
921// but the VI instructions behave the same as the SI versions.
922defm V_ADD_I32 : VOP2bInst <vop2<0x25, 0x19>, "v_add_i32",
Matt Arsenaulte4d0c142015-08-29 07:16:50 +0000[diff] [blame]923 VOP2b_I32_I1_I32_I32
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]924>;
Matt Arsenaulte4d0c142015-08-29 07:16:50 +0000[diff] [blame]925defm V_SUB_I32 : VOP2bInst <vop2<0x26, 0x1a>, "v_sub_i32", VOP2b_I32_I1_I32_I32>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]926
927defm V_SUBREV_I32 : VOP2bInst <vop2<0x27, 0x1b>, "v_subrev_i32",
Matt Arsenaulte4d0c142015-08-29 07:16:50 +0000[diff] [blame]928 VOP2b_I32_I1_I32_I32, null_frag, "v_sub_i32"
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]929>;
930
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]931defm V_ADDC_U32 : VOP2bInst <vop2<0x28, 0x1c>, "v_addc_u32",
Matt Arsenault86d336e2015-09-08 21:15:00 +0000[diff] [blame]932 VOP2b_I32_I1_I32_I32_I1
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]933>;
934defm V_SUBB_U32 : VOP2bInst <vop2<0x29, 0x1d>, "v_subb_u32",
Matt Arsenault86d336e2015-09-08 21:15:00 +0000[diff] [blame]935 VOP2b_I32_I1_I32_I32_I1
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]936>;
937defm V_SUBBREV_U32 : VOP2bInst <vop2<0x2a, 0x1e>, "v_subbrev_u32",
Matt Arsenault86d336e2015-09-08 21:15:00 +0000[diff] [blame]938 VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32"
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]939>;
940
Matt Arsenault86d336e2015-09-08 21:15:00 +0000[diff] [blame]941} // End isCommutable = 1
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]942
Matt Arsenault529cf252016-06-23 01:26:16 +0000[diff] [blame]943// These are special and do not read the exec mask.
944let isConvergent = 1, Uses = []<Register> in {
Matt Arsenault42345422016-05-11 00:32:31 +0000[diff] [blame]945
Marek Olsak15e4a592015-01-15 18:42:55 +0000[diff] [blame]946defm V_READLANE_B32 : VOP2SI_3VI_m <
947 vop3 <0x001, 0x289>,
948 "v_readlane_b32",
Tom Stellardc149dc02013-11-27 21:23:35 +0000[diff] [blame]949 (outs SReg_32:$vdst),
Changpeng Fang75f09682016-08-24 20:35:23 +0000[diff] [blame]950 (ins VGPR_32:$src0, SCSrc_32:$src1),
951 "v_readlane_b32 $vdst, $src0, $src1",
952 [(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))]
Tom Stellardc149dc02013-11-27 21:23:35 +0000[diff] [blame]953>;
954
Marek Olsak15e4a592015-01-15 18:42:55 +0000[diff] [blame]955defm V_WRITELANE_B32 : VOP2SI_3VI_m <
956 vop3 <0x002, 0x28a>,
957 "v_writelane_b32",
Tom Stellard45c0b3a2015-01-07 20:59:25 +0000[diff] [blame]958 (outs VGPR_32:$vdst),
Marek Olsak9b8f32e2015-02-18 22:12:45 +0000[diff] [blame]959 (ins SReg_32:$src0, SCSrc_32:$src1),
960 "v_writelane_b32 $vdst, $src0, $src1"
Tom Stellardc149dc02013-11-27 21:23:35 +0000[diff] [blame]961>;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]962
Matt Arsenault42345422016-05-11 00:32:31 +0000[diff] [blame]963} // End isConvergent = 1
964
Marek Olsak15e4a592015-01-15 18:42:55 +0000[diff] [blame]965// These instructions only exist on SI and CI
966let SubtargetPredicate = isSICI in {
967
Tom Stellard85656ca2015-08-07 15:34:30 +0000[diff] [blame]968let isCommutable = 1 in {
969defm V_MAC_LEGACY_F32 : VOP2InstSI <vop2<0x6>, "v_mac_legacy_f32",
970 VOP_F32_F32_F32
971>;
972} // End isCommutable = 1
973
Marek Olsak191507e2015-02-03 17:38:12 +0000[diff] [blame]974defm V_MIN_LEGACY_F32 : VOP2InstSI <vop2<0xd>, "v_min_legacy_f32",
Matt Arsenaultda59f3d2014-11-13 23:03:09 +0000[diff] [blame]975 VOP_F32_F32_F32, AMDGPUfmin_legacy
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]976>;
Marek Olsak191507e2015-02-03 17:38:12 +0000[diff] [blame]977defm V_MAX_LEGACY_F32 : VOP2InstSI <vop2<0xe>, "v_max_legacy_f32",
Matt Arsenaultda59f3d2014-11-13 23:03:09 +0000[diff] [blame]978 VOP_F32_F32_F32, AMDGPUfmax_legacy
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]979>;
Christian Konig76edd4f2013-02-26 17:52:29 +0000[diff] [blame]980
Matt Arsenault1e3a4eb2014-12-12 02:30:37 +0000[diff] [blame]981let isCommutable = 1 in {
Marek Olsak24ae2cd2015-02-03 21:53:08 +0000[diff] [blame]982defm V_LSHR_B32 : VOP2InstSI <vop2<0x15>, "v_lshr_b32", VOP_I32_I32_I32>;
983defm V_ASHR_I32 : VOP2InstSI <vop2<0x17>, "v_ashr_i32", VOP_I32_I32_I32>;
984defm V_LSHL_B32 : VOP2InstSI <vop2<0x19>, "v_lshl_b32", VOP_I32_I32_I32>;
Christian Konig76edd4f2013-02-26 17:52:29 +0000[diff] [blame]985} // End isCommutable = 1
Marek Olsakf0b130a2015-01-15 18:43:06 +0000[diff] [blame]986} // End let SubtargetPredicate = SICI
Christian Konig76edd4f2013-02-26 17:52:29 +0000[diff] [blame]987
Marek Olsak63a7b082015-03-24 13:40:21 +0000[diff] [blame]988defm V_BFM_B32 : VOP2_VI3_Inst <vop23<0x1e, 0x293>, "v_bfm_b32",
989 VOP_I32_I32_I32
Marek Olsakf0b130a2015-01-15 18:43:06 +0000[diff] [blame]990>;
991defm V_BCNT_U32_B32 : VOP2_VI3_Inst <vop23<0x22, 0x28b>, "v_bcnt_u32_b32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]992 VOP_I32_I32_I32
993>;
Marek Olsakf0b130a2015-01-15 18:43:06 +0000[diff] [blame]994defm V_MBCNT_LO_U32_B32 : VOP2_VI3_Inst <vop23<0x23, 0x28c>, "v_mbcnt_lo_u32_b32",
Tom Stellard43f52df2015-12-15 17:02:52 +0000[diff] [blame]995 VOP_I32_I32_I32, int_amdgcn_mbcnt_lo
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]996>;
Marek Olsakf0b130a2015-01-15 18:43:06 +0000[diff] [blame]997defm V_MBCNT_HI_U32_B32 : VOP2_VI3_Inst <vop23<0x24, 0x28d>, "v_mbcnt_hi_u32_b32",
Tom Stellard43f52df2015-12-15 17:02:52 +0000[diff] [blame]998 VOP_I32_I32_I32, int_amdgcn_mbcnt_hi
Marek Olsakf0b130a2015-01-15 18:43:06 +0000[diff] [blame]999>;
1000defm V_LDEXP_F32 : VOP2_VI3_Inst <vop23<0x2b, 0x288>, "v_ldexp_f32",
Matt Arsenault2e7cc482014-08-15 17:30:25 +0000[diff] [blame]1001 VOP_F32_F32_I32, AMDGPUldexp
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1002>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1003
Marek Olsak11057ee2015-02-03 17:38:01 +0000[diff] [blame]1004defm V_CVT_PKACCUM_U8_F32 : VOP2_VI3_Inst <vop23<0x2c, 0x1f0>, "v_cvt_pkaccum_u8_f32",
1005 VOP_I32_F32_I32>; // TODO: set "Uses = dst"
1006
1007defm V_CVT_PKNORM_I16_F32 : VOP2_VI3_Inst <vop23<0x2d, 0x294>, "v_cvt_pknorm_i16_f32",
1008 VOP_I32_F32_F32
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]1009>;
Marek Olsak11057ee2015-02-03 17:38:01 +0000[diff] [blame]1010defm V_CVT_PKNORM_U16_F32 : VOP2_VI3_Inst <vop23<0x2e, 0x295>, "v_cvt_pknorm_u16_f32",
1011 VOP_I32_F32_F32
1012>;
1013defm V_CVT_PKRTZ_F16_F32 : VOP2_VI3_Inst <vop23<0x2f, 0x296>, "v_cvt_pkrtz_f16_f32",
1014 VOP_I32_F32_F32, int_SI_packf16
1015>;
1016defm V_CVT_PK_U16_U32 : VOP2_VI3_Inst <vop23<0x30, 0x297>, "v_cvt_pk_u16_u32",
1017 VOP_I32_I32_I32
1018>;
1019defm V_CVT_PK_I16_I32 : VOP2_VI3_Inst <vop23<0x31, 0x298>, "v_cvt_pk_i16_i32",
1020 VOP_I32_I32_I32
1021>;
Tom Stellard8d6d4492014-04-22 16:33:57 +0000[diff] [blame]1022
1023//===----------------------------------------------------------------------===//
1024// VOP3 Instructions
1025//===----------------------------------------------------------------------===//
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]1026
Matt Arsenault95e48662014-11-13 19:26:47 +0000[diff] [blame]1027let isCommutable = 1 in {
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1028defm V_MAD_LEGACY_F32 : VOP3Inst <vop3<0x140, 0x1c0>, "v_mad_legacy_f32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1029 VOP_F32_F32_F32_F32
Matt Arsenaultf37abc72014-05-22 17:45:20 +0000[diff] [blame]1030>;
Matt Arsenault95e48662014-11-13 19:26:47 +0000[diff] [blame]1031
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1032defm V_MAD_F32 : VOP3Inst <vop3<0x141, 0x1c1>, "v_mad_f32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1033 VOP_F32_F32_F32_F32, fmad
Tom Stellard52639482013-07-23 01:48:49 +0000[diff] [blame]1034>;
Matt Arsenault95e48662014-11-13 19:26:47 +0000[diff] [blame]1035
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1036defm V_MAD_I32_I24 : VOP3Inst <vop3<0x142, 0x1c2>, "v_mad_i32_i24",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1037 VOP_I32_I32_I32_I32, AMDGPUmad_i24
1038>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1039defm V_MAD_U32_U24 : VOP3Inst <vop3<0x143, 0x1c3>, "v_mad_u32_u24",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1040 VOP_I32_I32_I32_I32, AMDGPUmad_u24
Tom Stellard52639482013-07-23 01:48:49 +0000[diff] [blame]1041>;
Matt Arsenault95e48662014-11-13 19:26:47 +0000[diff] [blame]1042} // End isCommutable = 1
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]1043
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1044defm V_CUBEID_F32 : VOP3Inst <vop3<0x144, 0x1c4>, "v_cubeid_f32",
Matt Arsenault051d6f92016-01-26 04:29:56 +0000[diff] [blame]1045 VOP_F32_F32_F32_F32, int_amdgcn_cubeid
Niels Ole Salscheider6509ac62013-08-10 10:38:47 +0000[diff] [blame]1046>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1047defm V_CUBESC_F32 : VOP3Inst <vop3<0x145, 0x1c5>, "v_cubesc_f32",
Matt Arsenault051d6f92016-01-26 04:29:56 +0000[diff] [blame]1048 VOP_F32_F32_F32_F32, int_amdgcn_cubesc
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1049>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1050defm V_CUBETC_F32 : VOP3Inst <vop3<0x146, 0x1c6>, "v_cubetc_f32",
Matt Arsenault051d6f92016-01-26 04:29:56 +0000[diff] [blame]1051 VOP_F32_F32_F32_F32, int_amdgcn_cubetc
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1052>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1053defm V_CUBEMA_F32 : VOP3Inst <vop3<0x147, 0x1c7>, "v_cubema_f32",
Matt Arsenault051d6f92016-01-26 04:29:56 +0000[diff] [blame]1054 VOP_F32_F32_F32_F32, int_amdgcn_cubema
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1055>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1056
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1057defm V_BFE_U32 : VOP3Inst <vop3<0x148, 0x1c8>, "v_bfe_u32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1058 VOP_I32_I32_I32_I32, AMDGPUbfe_u32
1059>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1060defm V_BFE_I32 : VOP3Inst <vop3<0x149, 0x1c9>, "v_bfe_i32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1061 VOP_I32_I32_I32_I32, AMDGPUbfe_i32
1062>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1063
1064defm V_BFI_B32 : VOP3Inst <vop3<0x14a, 0x1ca>, "v_bfi_b32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1065 VOP_I32_I32_I32_I32, AMDGPUbfi
1066>;
Matt Arsenault95e48662014-11-13 19:26:47 +0000[diff] [blame]1067
1068let isCommutable = 1 in {
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1069defm V_FMA_F32 : VOP3Inst <vop3<0x14b, 0x1cb>, "v_fma_f32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1070 VOP_F32_F32_F32_F32, fma
1071>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1072defm V_FMA_F64 : VOP3Inst <vop3<0x14c, 0x1cc>, "v_fma_f64",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1073 VOP_F64_F64_F64_F64, fma
Niels Ole Salscheider6509ac62013-08-10 10:38:47 +0000[diff] [blame]1074>;
Wei Ding5b2636a2016-07-12 18:02:14 +0000[diff] [blame]1075
1076defm V_LERP_U8 : VOP3Inst <vop3<0x14d, 0x1cd>, "v_lerp_u8",
1077 VOP_I32_I32_I32_I32, int_amdgcn_lerp
1078>;
Matt Arsenault95e48662014-11-13 19:26:47 +0000[diff] [blame]1079} // End isCommutable = 1
1080
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]1081//def V_LERP_U8 : VOP3_U8 <0x0000014d, "v_lerp_u8", []>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1082defm V_ALIGNBIT_B32 : VOP3Inst <vop3<0x14e, 0x1ce>, "v_alignbit_b32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1083 VOP_I32_I32_I32_I32
1084>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1085defm V_ALIGNBYTE_B32 : VOP3Inst <vop3<0x14f, 0x1cf>, "v_alignbyte_b32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1086 VOP_I32_I32_I32_I32
1087>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1088
Marek Olsak794ff832015-01-27 17:25:15 +0000[diff] [blame]1089defm V_MIN3_F32 : VOP3Inst <vop3<0x151, 0x1d0>, "v_min3_f32",
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +0000[diff] [blame]1090 VOP_F32_F32_F32_F32, AMDGPUfmin3>;
1091
Marek Olsak794ff832015-01-27 17:25:15 +0000[diff] [blame]1092defm V_MIN3_I32 : VOP3Inst <vop3<0x152, 0x1d1>, "v_min3_i32",
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +0000[diff] [blame]1093 VOP_I32_I32_I32_I32, AMDGPUsmin3
1094>;
Marek Olsak794ff832015-01-27 17:25:15 +0000[diff] [blame]1095defm V_MIN3_U32 : VOP3Inst <vop3<0x153, 0x1d2>, "v_min3_u32",
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +0000[diff] [blame]1096 VOP_I32_I32_I32_I32, AMDGPUumin3
1097>;
Marek Olsak794ff832015-01-27 17:25:15 +0000[diff] [blame]1098defm V_MAX3_F32 : VOP3Inst <vop3<0x154, 0x1d3>, "v_max3_f32",
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +0000[diff] [blame]1099 VOP_F32_F32_F32_F32, AMDGPUfmax3
1100>;
Marek Olsak794ff832015-01-27 17:25:15 +0000[diff] [blame]1101defm V_MAX3_I32 : VOP3Inst <vop3<0x155, 0x1d4>, "v_max3_i32",
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +0000[diff] [blame]1102 VOP_I32_I32_I32_I32, AMDGPUsmax3
1103>;
Marek Olsak794ff832015-01-27 17:25:15 +0000[diff] [blame]1104defm V_MAX3_U32 : VOP3Inst <vop3<0x156, 0x1d5>, "v_max3_u32",
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +0000[diff] [blame]1105 VOP_I32_I32_I32_I32, AMDGPUumax3
1106>;
Marek Olsak794ff832015-01-27 17:25:15 +0000[diff] [blame]1107defm V_MED3_F32 : VOP3Inst <vop3<0x157, 0x1d6>, "v_med3_f32",
Matt Arsenaultf639c322016-01-28 20:53:42 +0000[diff] [blame]1108 VOP_F32_F32_F32_F32, AMDGPUfmed3
Marek Olsak794ff832015-01-27 17:25:15 +0000[diff] [blame]1109>;
1110defm V_MED3_I32 : VOP3Inst <vop3<0x158, 0x1d7>, "v_med3_i32",
Matt Arsenaultf639c322016-01-28 20:53:42 +0000[diff] [blame]1111 VOP_I32_I32_I32_I32, AMDGPUsmed3
Marek Olsak794ff832015-01-27 17:25:15 +0000[diff] [blame]1112>;
1113defm V_MED3_U32 : VOP3Inst <vop3<0x159, 0x1d8>, "v_med3_u32",
Matt Arsenaultf639c322016-01-28 20:53:42 +0000[diff] [blame]1114 VOP_I32_I32_I32_I32, AMDGPUumed3
Marek Olsak794ff832015-01-27 17:25:15 +0000[diff] [blame]1115>;
1116
Wei Ding34e17532016-08-11 16:33:53 +0000[diff] [blame]1117defm V_SAD_U8 : VOP3Inst <vop3 <0x15a, 0x1d9>, "v_sad_u8",
1118 VOP_I32_I32_I32_I32, int_amdgcn_sad_u8>;
1119
1120defm V_SAD_HI_U8 : VOP3Inst <vop3 <0x15b, 0x1da>, "v_sad_hi_u8",
1121 VOP_I32_I32_I32_I32, int_amdgcn_sad_hi_u8>;
1122
1123defm V_SAD_U16 : VOP3Inst <vop3<0x15c, 0x1db>, "v_sad_u16",
1124 VOP_I32_I32_I32_I32, int_amdgcn_sad_u16>;
1125
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1126defm V_SAD_U32 : VOP3Inst <vop3<0x15d, 0x1dc>, "v_sad_u32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1127 VOP_I32_I32_I32_I32
1128>;
Wei Ding70cda072016-08-11 20:34:48 +0000[diff] [blame]1129
1130defm V_CVT_PK_U8_F32 : VOP3Inst<vop3<0x15e, 0x1dd>, "v_cvt_pk_u8_f32",
1131 VOP_I32_F32_I32_I32, int_amdgcn_cvt_pk_u8_f32
1132>;
1133
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]1134//def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "v_cvt_pk_u8_f32", []>;
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1135defm V_DIV_FIXUP_F32 : VOP3Inst <
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1136 vop3<0x15f, 0x1de>, "v_div_fixup_f32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup
Matt Arsenaulta0050b02014-06-19 01:19:19 +0000[diff] [blame]1137>;
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]1138
Matt Arsenaulte8df8792015-08-22 00:50:41 +0000[diff] [blame]1139let SchedRW = [WriteDoubleAdd] in {
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]1140
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1141defm V_DIV_FIXUP_F64 : VOP3Inst <
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1142 vop3<0x160, 0x1df>, "v_div_fixup_f64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup
Matt Arsenaulta0050b02014-06-19 01:19:19 +0000[diff] [blame]1143>;
Tom Stellard1cfd7a52013-05-20 15:02:12 +0000[diff] [blame]1144
Matt Arsenaulte8df8792015-08-22 00:50:41 +0000[diff] [blame]1145} // End SchedRW = [WriteDouble]
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]1146
Matt Arsenaulte8df8792015-08-22 00:50:41 +0000[diff] [blame]1147let SchedRW = [WriteDoubleAdd] in {
Tom Stellard7512c082013-07-12 18:14:56 +0000[diff] [blame]1148let isCommutable = 1 in {
1149
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1150defm V_ADD_F64 : VOP3Inst <vop3<0x164, 0x280>, "v_add_f64",
Tom Stellarda90b9522016-02-11 03:28:15 +0000[diff] [blame]1151 VOP_F64_F64_F64, fadd, 1
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1152>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1153defm V_MUL_F64 : VOP3Inst <vop3<0x165, 0x281>, "v_mul_f64",
Tom Stellarda90b9522016-02-11 03:28:15 +0000[diff] [blame]1154 VOP_F64_F64_F64, fmul, 1
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1155>;
Matt Arsenault7c936902014-10-21 23:01:01 +0000[diff] [blame]1156
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1157defm V_MIN_F64 : VOP3Inst <vop3<0x166, 0x282>, "v_min_f64",
Tom Stellarda90b9522016-02-11 03:28:15 +0000[diff] [blame]1158 VOP_F64_F64_F64, fminnum, 1
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1159>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1160defm V_MAX_F64 : VOP3Inst <vop3<0x167, 0x283>, "v_max_f64",
Tom Stellarda90b9522016-02-11 03:28:15 +0000[diff] [blame]1161 VOP_F64_F64_F64, fmaxnum, 1
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1162>;
Tom Stellard7512c082013-07-12 18:14:56 +0000[diff] [blame]1163
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]1164} // End isCommutable = 1
Tom Stellard7512c082013-07-12 18:14:56 +0000[diff] [blame]1165
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1166defm V_LDEXP_F64 : VOP3Inst <vop3<0x168, 0x284>, "v_ldexp_f64",
Tom Stellarda90b9522016-02-11 03:28:15 +0000[diff] [blame]1167 VOP_F64_F64_I32, AMDGPUldexp, 1
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1168>;
Christian Konig70a50322013-03-27 09:12:51 +0000[diff] [blame]1169
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]1170} // End let SchedRW = [WriteDoubleAdd]
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]1171
1172let isCommutable = 1, SchedRW = [WriteQuarterRate32] in {
Christian Konig70a50322013-03-27 09:12:51 +0000[diff] [blame]1173
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1174defm V_MUL_LO_U32 : VOP3Inst <vop3<0x169, 0x285>, "v_mul_lo_u32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1175 VOP_I32_I32_I32
1176>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1177defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a, 0x286>, "v_mul_hi_u32",
Matt Arsenault8d903022016-01-22 18:42:49 +0000[diff] [blame]1178 VOP_I32_I32_I32, mulhu
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1179>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1180
Tom Stellarde1818af2016-02-18 03:42:32 +0000[diff] [blame]1181let DisableVIDecoder=1 in { // removed from VI as identical to V_MUL_LO_U32
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1182defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b, 0x285>, "v_mul_lo_i32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1183 VOP_I32_I32_I32
1184>;
Tom Stellarde1818af2016-02-18 03:42:32 +0000[diff] [blame]1185}
1186
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1187defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32",
Matt Arsenault8d903022016-01-22 18:42:49 +0000[diff] [blame]1188 VOP_I32_I32_I32, mulhs
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1189>;
Christian Konig70a50322013-03-27 09:12:51 +0000[diff] [blame]1190
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]1191} // End isCommutable = 1, SchedRW = [WriteQuarterRate32]
Christian Konig70a50322013-03-27 09:12:51 +0000[diff] [blame]1192
Matt Arsenault6e26b8d2015-02-14 04:03:18 +0000[diff] [blame]1193let SchedRW = [WriteFloatFMA, WriteSALU] in {
Matt Arsenaulte98a0742015-09-26 02:25:48 +0000[diff] [blame]1194defm V_DIV_SCALE_F32 : VOP3bInst <vop3<0x16d, 0x1e0>, "v_div_scale_f32",
Tom Stellarde9934512016-02-11 18:25:26 +0000[diff] [blame]1195 VOP3b_F32_I1_F32_F32_F32, [], 1
Matt Arsenaulte98a0742015-09-26 02:25:48 +0000[diff] [blame]1196>;
Matt Arsenault6e26b8d2015-02-14 04:03:18 +0000[diff] [blame]1197}
Matt Arsenaultf2b0aeb2014-06-23 18:28:28 +0000[diff] [blame]1198
Matt Arsenault6e26b8d2015-02-14 04:03:18 +0000[diff] [blame]1199let SchedRW = [WriteDouble, WriteSALU] in {
Matt Arsenaultf2b0aeb2014-06-23 18:28:28 +0000[diff] [blame]1200// Double precision division pre-scale.
Matt Arsenaulte98a0742015-09-26 02:25:48 +0000[diff] [blame]1201defm V_DIV_SCALE_F64 : VOP3bInst <vop3<0x16e, 0x1e1>, "v_div_scale_f64",
Tom Stellarde9934512016-02-11 18:25:26 +0000[diff] [blame]1202 VOP3b_F64_I1_F64_F64_F64, [], 1
Matt Arsenaulte98a0742015-09-26 02:25:48 +0000[diff] [blame]1203>;
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]1204} // End SchedRW = [WriteDouble]
Matt Arsenaulta0050b02014-06-19 01:19:19 +0000[diff] [blame]1205
Matt Arsenault80f766a2015-09-10 01:23:28 +0000[diff] [blame]1206let isCommutable = 1, Uses = [VCC, EXEC] in {
Matt Arsenault1bc9d952015-02-14 04:22:00 +0000[diff] [blame]1207
Matt Arsenaulte8df8792015-08-22 00:50:41 +0000[diff] [blame]1208let SchedRW = [WriteFloatFMA] in {
Matt Arsenault1bc9d952015-02-14 04:22:00 +0000[diff] [blame]1209// v_div_fmas_f32:
1210// result = src0 * src1 + src2
1211// if (vcc)
1212// result *= 2^32
1213//
1214defm V_DIV_FMAS_F32 : VOP3_VCC_Inst <vop3<0x16f, 0x1e2>, "v_div_fmas_f32",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1215 VOP_F32_F32_F32_F32, AMDGPUdiv_fmas
Matt Arsenaulta0050b02014-06-19 01:19:19 +0000[diff] [blame]1216>;
Matt Arsenaulte8df8792015-08-22 00:50:41 +0000[diff] [blame]1217}
Matt Arsenault1bc9d952015-02-14 04:22:00 +0000[diff] [blame]1218
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]1219let SchedRW = [WriteDouble] in {
Matt Arsenault1bc9d952015-02-14 04:22:00 +0000[diff] [blame]1220// v_div_fmas_f64:
1221// result = src0 * src1 + src2
1222// if (vcc)
1223// result *= 2^64
1224//
1225defm V_DIV_FMAS_F64 : VOP3_VCC_Inst <vop3<0x170, 0x1e3>, "v_div_fmas_f64",
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1226 VOP_F64_F64_F64_F64, AMDGPUdiv_fmas
Matt Arsenaulta0050b02014-06-19 01:19:19 +0000[diff] [blame]1227>;
Matt Arsenault1bc9d952015-02-14 04:22:00 +0000[diff] [blame]1228
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]1229} // End SchedRW = [WriteDouble]
Matt Arsenault80f766a2015-09-10 01:23:28 +0000[diff] [blame]1230} // End isCommutable = 1, Uses = [VCC, EXEC]
Matt Arsenault95e48662014-11-13 19:26:47 +0000[diff] [blame]1231
Wei Ding34e17532016-08-11 16:33:53 +0000[diff] [blame]1232defm V_MSAD_U8 : VOP3Inst <vop3<0x171, 0x1e4>, "v_msad_u8",
1233 VOP_I32_I32_I32_I32, int_amdgcn_msad_u8>;
1234
1235defm V_MQSAD_PK_U16_U8 : VOP3Inst <vop3<0x173, 0x1e6>, "v_mqsad_pk_u16_u8",
Wei Ding52bb6612016-08-18 19:51:14 +0000[diff] [blame]1236 VOP_I64_I64_I32_I64, int_amdgcn_mqsad_pk_u16_u8>;
Wei Ding34e17532016-08-11 16:33:53 +0000[diff] [blame]1237
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]1238//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "v_mqsad_u8", []>;
Matt Arsenault95e48662014-11-13 19:26:47 +0000[diff] [blame]1239
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]1240let SchedRW = [WriteDouble] in {
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]1241defm V_TRIG_PREOP_F64 : VOP3Inst <
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1242 vop3<0x174, 0x292>, "v_trig_preop_f64", VOP_F64_F64_I32, AMDGPUtrig_preop
Matt Arsenaulta0050b02014-06-19 01:19:19 +0000[diff] [blame]1243>;
Matt Arsenaulte27a41b2013-11-18 20:09:32 +0000[diff] [blame]1244
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]1245} // End SchedRW = [WriteDouble]
Tom Stellardae38f302015-01-14 01:13:19 +0000[diff] [blame]1246
Marek Olsakeae20ab2015-01-15 18:42:40 +0000[diff] [blame]1247// These instructions only exist on SI and CI
1248let SubtargetPredicate = isSICI in {
1249
Marek Olsak24ae2cd2015-02-03 21:53:08 +0000[diff] [blame]1250defm V_LSHL_B64 : VOP3Inst <vop3<0x161>, "v_lshl_b64", VOP_I64_I64_I32>;
1251defm V_LSHR_B64 : VOP3Inst <vop3<0x162>, "v_lshr_b64", VOP_I64_I64_I32>;
1252defm V_ASHR_I64 : VOP3Inst <vop3<0x163>, "v_ashr_i64", VOP_I64_I64_I32>;
Marek Olsakeae20ab2015-01-15 18:42:40 +0000[diff] [blame]1253
1254defm V_MULLIT_F32 : VOP3Inst <vop3<0x150>, "v_mullit_f32",
1255 VOP_F32_F32_F32_F32>;
1256
1257} // End SubtargetPredicate = isSICI
1258
Tom Stellarde1818af2016-02-18 03:42:32 +0000[diff] [blame]1259let SubtargetPredicate = isVI, DisableSIDecoder = 1 in {
Marek Olsak707a6d02015-02-03 21:53:01 +0000[diff] [blame]1260
1261defm V_LSHLREV_B64 : VOP3Inst <vop3<0, 0x28f>, "v_lshlrev_b64",
1262 VOP_I64_I32_I64
1263>;
1264defm V_LSHRREV_B64 : VOP3Inst <vop3<0, 0x290>, "v_lshrrev_b64",
1265 VOP_I64_I32_I64
1266>;
1267defm V_ASHRREV_I64 : VOP3Inst <vop3<0, 0x291>, "v_ashrrev_i64",
1268 VOP_I64_I32_I64
1269>;
1270
1271} // End SubtargetPredicate = isVI
1272
Tom Stellard8d6d4492014-04-22 16:33:57 +0000[diff] [blame]1273//===----------------------------------------------------------------------===//
1274// Pseudo Instructions
1275//===----------------------------------------------------------------------===//
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1276
1277let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in {
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]1278
Marek Olsak7d777282015-03-24 13:40:15 +0000[diff] [blame]1279// For use in patterns
Tom Stellardcc4c8712016-02-16 18:14:56 +0000[diff] [blame]1280def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$vdst),
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1281 (ins VSrc_64:$src0, VSrc_64:$src1, SSrc_64:$src2), "", []> {
1282 let isPseudo = 1;
1283 let isCodeGenOnly = 1;
Matt Arsenault22e41792016-08-27 01:00:37 +0000[diff] [blame]1284 let usesCustomInserter = 1;
Tom Stellard60024a02014-09-24 01:33:24 +0000[diff] [blame]1285}
1286
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1287// 64-bit vector move instruction. This is mainly used by the SIFoldOperands
1288// pass to enable folding of inline immediates.
1289def V_MOV_B64_PSEUDO : PseudoInstSI <(outs VReg_64:$vdst), (ins VSrc_64:$src0)> {
1290 let VALU = 1;
1291}
1292} // End let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC]
1293
Changpeng Fang01f60622016-03-15 17:28:44 +0000[diff] [blame]1294let usesCustomInserter = 1, SALU = 1 in {
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1295def GET_GROUPSTATICSIZE : PseudoInstSI <(outs SReg_32:$sdst), (ins),
Changpeng Fang01f60622016-03-15 17:28:44 +0000[diff] [blame]1296 [(set SReg_32:$sdst, (int_amdgcn_groupstaticsize))]>;
1297} // End let usesCustomInserter = 1, SALU = 1
1298
Matt Arsenault8fb37382013-10-11 21:03:36 +0000[diff] [blame]1299// SI pseudo instructions. These are used by the CFG structurizer pass
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]1300// and should be lowered to ISA instructions prior to codegen.
1301
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1302let hasSideEffects = 1 in {
Matt Arsenault9babdf42016-06-22 20:15:28 +0000[diff] [blame]1303
1304// Dummy terminator instruction to use after control flow instructions
1305// replaced with exec mask operations.
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1306def SI_MASK_BRANCH : PseudoInstSI <
Matt Arsenaultf98a5962016-08-27 00:42:21 +0000[diff] [blame]1307 (outs), (ins brtarget:$target)> {
Matt Arsenault57431c92016-08-10 19:11:42 +0000[diff] [blame]1308 let isBranch = 0;
Matt Arsenault9babdf42016-06-22 20:15:28 +0000[diff] [blame]1309 let isTerminator = 1;
Matt Arsenault57431c92016-08-10 19:11:42 +0000[diff] [blame]1310 let isBarrier = 0;
Matt Arsenault9babdf42016-06-22 20:15:28 +0000[diff] [blame]1311 let SALU = 1;
Matt Arsenault78fc9da2016-08-22 19:33:16 +0000[diff] [blame]1312 let Uses = [EXEC];
Matt Arsenault9babdf42016-06-22 20:15:28 +0000[diff] [blame]1313}
1314
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1315let isTerminator = 1 in {
Tom Stellardf8794352012-12-19 22:10:31 +0000[diff] [blame]1316
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1317def SI_IF: CFPseudoInstSI <
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1318 (outs SReg_64:$dst), (ins SReg_64:$vcc, brtarget:$target),
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1319 [(set i64:$dst, (int_amdgcn_if i1:$vcc, bb:$target))], 1, 1> {
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1320 let Constraints = "";
Matt Arsenaultc6b13502016-08-10 19:11:51 +0000[diff] [blame]1321 let Size = 8;
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1322}
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]1323
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1324def SI_ELSE : CFPseudoInstSI <
1325 (outs SReg_64:$dst), (ins SReg_64:$src, brtarget:$target, i1imm:$execfix), [], 1, 1> {
Tom Stellardf8794352012-12-19 22:10:31 +0000[diff] [blame]1326 let Constraints = "$src = $dst";
Matt Arsenaultc6b13502016-08-10 19:11:51 +0000[diff] [blame]1327 let Size = 12;
Tom Stellardf8794352012-12-19 22:10:31 +0000[diff] [blame]1328}
1329
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1330def SI_LOOP : CFPseudoInstSI <
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1331 (outs), (ins SReg_64:$saved, brtarget:$target),
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1332 [(int_amdgcn_loop i64:$saved, bb:$target)], 1, 1> {
Matt Arsenaultc6b13502016-08-10 19:11:51 +0000[diff] [blame]1333 let Size = 8;
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1334 let isBranch = 1;
Matt Arsenaultc6b13502016-08-10 19:11:51 +0000[diff] [blame]1335}
Tom Stellardf8794352012-12-19 22:10:31 +0000[diff] [blame]1336
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]1337} // End isBranch = 1, isTerminator = 1
Tom Stellardf8794352012-12-19 22:10:31 +0000[diff] [blame]1338
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1339def SI_END_CF : CFPseudoInstSI <
1340 (outs), (ins SReg_64:$saved),
1341 [(int_amdgcn_end_cf i64:$saved)], 1, 1> {
1342 let Size = 4;
1343}
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1344
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1345def SI_BREAK : CFPseudoInstSI <
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1346 (outs SReg_64:$dst), (ins SReg_64:$src),
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1347 [(set i64:$dst, (int_amdgcn_break i64:$src))], 1> {
Matt Arsenaultc6b13502016-08-10 19:11:51 +0000[diff] [blame]1348 let Size = 4;
1349}
Matt Arsenault48d70cb2016-07-09 17:18:39 +0000[diff] [blame]1350
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1351def SI_IF_BREAK : CFPseudoInstSI <
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1352 (outs SReg_64:$dst), (ins SReg_64:$vcc, SReg_64:$src),
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1353 [(set i64:$dst, (int_amdgcn_if_break i1:$vcc, i64:$src))]> {
Matt Arsenaultc6b13502016-08-10 19:11:51 +0000[diff] [blame]1354 let Size = 4;
1355}
Tom Stellardf8794352012-12-19 22:10:31 +0000[diff] [blame]1356
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1357def SI_ELSE_BREAK : CFPseudoInstSI <
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1358 (outs SReg_64:$dst), (ins SReg_64:$src0, SReg_64:$src1),
Matt Arsenaultc6b13502016-08-10 19:11:51 +0000[diff] [blame]1359 [(set i64:$dst, (int_amdgcn_else_break i64:$src0, i64:$src1))]> {
1360 let Size = 4;
1361}
Tom Stellardf8794352012-12-19 22:10:31 +0000[diff] [blame]1362
Tom Stellardaa798342015-05-01 03:44:09 +0000[diff] [blame]1363let Uses = [EXEC], Defs = [EXEC,VCC] in {
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1364def SI_KILL : PseudoInstSI <
1365 (outs), (ins VSrc_32:$src),
Matt Arsenault03006fd2016-07-19 16:27:56 +0000[diff] [blame]1366 [(AMDGPUkill i32:$src)]> {
Matt Arsenault786724a2016-07-12 21:41:32 +0000[diff] [blame]1367 let isConvergent = 1;
1368 let usesCustomInserter = 1;
1369}
1370
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1371def SI_KILL_TERMINATOR : SPseudoInstSI <
Matt Arsenault786724a2016-07-12 21:41:32 +0000[diff] [blame]1372 (outs), (ins VSrc_32:$src)> {
1373 let isTerminator = 1;
1374}
1375
Tom Stellardaa798342015-05-01 03:44:09 +0000[diff] [blame]1376} // End Uses = [EXEC], Defs = [EXEC,VCC]
Tom Stellardbe8ebee2013-01-18 21:15:50 +0000[diff] [blame]1377
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]1378} // End mayLoad = 1, mayStore = 1, hasSideEffects = 1
Tom Stellardf8794352012-12-19 22:10:31 +0000[diff] [blame]1379
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1380def SI_PS_LIVE : PseudoInstSI <
1381 (outs SReg_64:$dst), (ins),
Matt Arsenault9babdf42016-06-22 20:15:28 +0000[diff] [blame]1382 [(set i1:$dst, (int_amdgcn_ps_live))]> {
1383 let SALU = 1;
1384}
Nicolai Haehnleb0c97482016-04-22 04:04:08 +0000[diff] [blame]1385
Matt Arsenault4ac341c2016-04-14 21:58:15 +0000[diff] [blame]1386// Used as an isel pseudo to directly emit initialization with an
1387// s_mov_b32 rather than a copy of another initialized
1388// register. MachineCSE skips copies, and we don't want to have to
1389// fold operands before it runs.
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1390def SI_INIT_M0 : SPseudoInstSI <(outs), (ins SSrc_32:$src)> {
Matt Arsenault4ac341c2016-04-14 21:58:15 +0000[diff] [blame]1391 let Defs = [M0];
1392 let usesCustomInserter = 1;
Matt Arsenault4ac341c2016-04-14 21:58:15 +0000[diff] [blame]1393 let isAsCheapAsAMove = 1;
Matt Arsenault4ac341c2016-04-14 21:58:15 +0000[diff] [blame]1394 let isReMaterializable = 1;
1395}
1396
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1397def SI_RETURN : SPseudoInstSI <
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1398 (outs), (ins variable_ops), [(AMDGPUreturn)]> {
Matt Arsenault9babdf42016-06-22 20:15:28 +0000[diff] [blame]1399 let isTerminator = 1;
1400 let isBarrier = 1;
1401 let isReturn = 1;
Matt Arsenault9babdf42016-06-22 20:15:28 +0000[diff] [blame]1402 let hasSideEffects = 1;
Matt Arsenault9babdf42016-06-22 20:15:28 +0000[diff] [blame]1403 let hasNoSchedulingInfo = 1;
1404}
1405
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1406let Defs = [M0, EXEC],
Matt Arsenault3cb4dde2016-06-22 23:40:57 +0000[diff] [blame]1407 UseNamedOperandTable = 1 in {
Christian Konig2989ffc2013-03-18 11:34:16 +0000[diff] [blame]1408
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1409class SI_INDIRECT_SRC<RegisterClass rc> : VPseudoInstSI <
Matt Arsenaultcb540bc2016-07-19 00:35:03 +0000[diff] [blame]1410 (outs VGPR_32:$vdst),
1411 (ins rc:$src, VS_32:$idx, i32imm:$offset)> {
1412 let usesCustomInserter = 1;
1413}
Christian Konig2989ffc2013-03-18 11:34:16 +0000[diff] [blame]1414
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1415class SI_INDIRECT_DST<RegisterClass rc> : VPseudoInstSI <
Matt Arsenaultcb540bc2016-07-19 00:35:03 +0000[diff] [blame]1416 (outs rc:$vdst),
1417 (ins rc:$src, VS_32:$idx, i32imm:$offset, VGPR_32:$val)> {
Matt Arsenault3cb4dde2016-06-22 23:40:57 +0000[diff] [blame]1418 let Constraints = "$src = $vdst";
Matt Arsenaultcb540bc2016-07-19 00:35:03 +0000[diff] [blame]1419 let usesCustomInserter = 1;
Christian Konig2989ffc2013-03-18 11:34:16 +0000[diff] [blame]1420}
1421
Matt Arsenault28419272015-10-07 00:42:51 +0000[diff] [blame]1422// TODO: We can support indirect SGPR access.
1423def SI_INDIRECT_SRC_V1 : SI_INDIRECT_SRC<VGPR_32>;
1424def SI_INDIRECT_SRC_V2 : SI_INDIRECT_SRC<VReg_64>;
1425def SI_INDIRECT_SRC_V4 : SI_INDIRECT_SRC<VReg_128>;
1426def SI_INDIRECT_SRC_V8 : SI_INDIRECT_SRC<VReg_256>;
1427def SI_INDIRECT_SRC_V16 : SI_INDIRECT_SRC<VReg_512>;
1428
Tom Stellard45c0b3a2015-01-07 20:59:25 +0000[diff] [blame]1429def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VGPR_32>;
Christian Konig2989ffc2013-03-18 11:34:16 +0000[diff] [blame]1430def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
1431def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
1432def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
1433def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
1434
Matt Arsenaultcb540bc2016-07-19 00:35:03 +0000[diff] [blame]1435} // End Uses = [EXEC], Defs = [M0, EXEC]
Christian Konig2989ffc2013-03-18 11:34:16 +0000[diff] [blame]1436
Tom Stellardeba61072014-05-02 15:41:42 +0000[diff] [blame]1437multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
Matt Arsenault80f766a2015-09-10 01:23:28 +0000[diff] [blame]1438 let UseNamedOperandTable = 1, Uses = [EXEC] in {
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1439 def _SAVE : PseudoInstSI <
Tom Stellard42fb60e2015-01-14 15:42:31 +0000[diff] [blame]1440 (outs),
Matt Arsenault9babdf42016-06-22 20:15:28 +0000[diff] [blame]1441 (ins sgpr_class:$src, i32imm:$frame_idx)> {
Matt Arsenault9a32cd32015-08-29 06:48:57 +0000[diff] [blame]1442 let mayStore = 1;
1443 let mayLoad = 0;
1444 }
Tom Stellardeba61072014-05-02 15:41:42 +0000[diff] [blame]1445
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1446 def _RESTORE : PseudoInstSI <
Tom Stellard42fb60e2015-01-14 15:42:31 +0000[diff] [blame]1447 (outs sgpr_class:$dst),
Matt Arsenault9babdf42016-06-22 20:15:28 +0000[diff] [blame]1448 (ins i32imm:$frame_idx)> {
Matt Arsenault9a32cd32015-08-29 06:48:57 +0000[diff] [blame]1449 let mayStore = 0;
1450 let mayLoad = 1;
1451 }
Tom Stellard42fb60e2015-01-14 15:42:31 +0000[diff] [blame]1452 } // End UseNamedOperandTable = 1
Tom Stellardeba61072014-05-02 15:41:42 +0000[diff] [blame]1453}
1454
Tom Stellardc2743492015-05-12 15:00:53 +0000[diff] [blame]1455// It's unclear whether you can use M0 as the output of v_readlane_b32
Artem Tamazov38e496b2016-04-29 17:04:50 +0000[diff] [blame]1456// instructions, so use SReg_32_XM0 register class for spills to prevent
Tom Stellardc2743492015-05-12 15:00:53 +0000[diff] [blame]1457// this from happening.
Artem Tamazov38e496b2016-04-29 17:04:50 +0000[diff] [blame]1458defm SI_SPILL_S32 : SI_SPILL_SGPR <SReg_32_XM0>;
Tom Stellardeba61072014-05-02 15:41:42 +0000[diff] [blame]1459defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
1460defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
1461defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;
1462defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
1463
Tom Stellard96468902014-09-24 01:33:17 +0000[diff] [blame]1464multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> {
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1465 let UseNamedOperandTable = 1, VGPRSpill = 1 in {
1466 def _SAVE : VPseudoInstSI <
Tom Stellard42fb60e2015-01-14 15:42:31 +0000[diff] [blame]1467 (outs),
Tom Stellard95292bb2015-01-20 17:49:47 +0000[diff] [blame]1468 (ins vgpr_class:$src, i32imm:$frame_idx, SReg_128:$scratch_rsrc,
Matt Arsenault9babdf42016-06-22 20:15:28 +0000[diff] [blame]1469 SReg_32:$scratch_offset, i32imm:$offset)> {
Matt Arsenault9a32cd32015-08-29 06:48:57 +0000[diff] [blame]1470 let mayStore = 1;
1471 let mayLoad = 0;
1472 }
Tom Stellard96468902014-09-24 01:33:17 +0000[diff] [blame]1473
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1474 def _RESTORE : VPseudoInstSI <
Tom Stellard42fb60e2015-01-14 15:42:31 +0000[diff] [blame]1475 (outs vgpr_class:$dst),
Tom Stellard649b5db2016-03-04 18:31:18 +0000[diff] [blame]1476 (ins i32imm:$frame_idx, SReg_128:$scratch_rsrc, SReg_32:$scratch_offset,
Matt Arsenault9babdf42016-06-22 20:15:28 +0000[diff] [blame]1477 i32imm:$offset)> {
Matt Arsenault9a32cd32015-08-29 06:48:57 +0000[diff] [blame]1478 let mayStore = 0;
1479 let mayLoad = 1;
1480 }
Tom Stellarda77c3f72015-05-12 18:59:17 +0000[diff] [blame]1481 } // End UseNamedOperandTable = 1, VGPRSpill = 1
Tom Stellard96468902014-09-24 01:33:17 +0000[diff] [blame]1482}
1483
Tom Stellard45c0b3a2015-01-07 20:59:25 +0000[diff] [blame]1484defm SI_SPILL_V32 : SI_SPILL_VGPR <VGPR_32>;
Tom Stellard96468902014-09-24 01:33:17 +0000[diff] [blame]1485defm SI_SPILL_V64 : SI_SPILL_VGPR <VReg_64>;
1486defm SI_SPILL_V96 : SI_SPILL_VGPR <VReg_96>;
1487defm SI_SPILL_V128 : SI_SPILL_VGPR <VReg_128>;
1488defm SI_SPILL_V256 : SI_SPILL_VGPR <VReg_256>;
1489defm SI_SPILL_V512 : SI_SPILL_VGPR <VReg_512>;
1490
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1491def SI_PC_ADD_REL_OFFSET : SPseudoInstSI <
Tom Stellard067c8152014-07-21 14:01:14 +0000[diff] [blame]1492 (outs SReg_64:$dst),
Tom Stellardbf3e6e52016-06-14 20:29:59 +0000[diff] [blame]1493 (ins si_ga:$ptr),
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000[diff] [blame]1494 [(set SReg_64:$dst, (i64 (SIpc_add_rel_offset (tglobaladdr:$ptr))))]> {
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000[diff] [blame]1495 let Defs = [SCC];
Matt Arsenaultd092a062015-10-02 18:58:37 +0000[diff] [blame]1496}
Tom Stellard067c8152014-07-21 14:01:14 +0000[diff] [blame]1497
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]1498} // End SubtargetPredicate = isGCN
Tom Stellard0e70de52014-05-16 20:56:45 +0000[diff] [blame]1499
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]1500let Predicates = [isGCN] in {
Tom Stellard0e70de52014-05-16 20:56:45 +0000[diff] [blame]1501
Nicolai Haehnle3b572002016-07-28 11:39:24 +0000[diff] [blame]1502def : Pat<
1503 (int_amdgcn_else i64:$src, bb:$target),
1504 (SI_ELSE $src, $target, 0)
1505>;
1506
Tom Stellardbe8ebee2013-01-18 21:15:50 +0000[diff] [blame]1507def : Pat <
1508 (int_AMDGPU_kilp),
Michel Danzer9e61c4b2014-02-27 01:47:09 +0000[diff] [blame]1509 (SI_KILL 0xbf800000)
Tom Stellardbe8ebee2013-01-18 21:15:50 +0000[diff] [blame]1510>;
1511
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]1512/* int_SI_vs_load_input */
1513def : Pat<
Tom Stellardbc5b5372014-06-13 16:38:59 +0000[diff] [blame]1514 (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr),
Tom Stellardc229baa2015-03-10 16:16:49 +0000[diff] [blame]1515 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $buf_idx_vgpr, $tlst, 0, imm:$attr_offset, 0, 0, 0)
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]1516>;
1517
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]1518def : Pat <
1519 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]1520 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]1521 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]1522 $src0, $src1, $src2, $src3)
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]1523>;
1524
Tom Stellard8d6d4492014-04-22 16:33:57 +0000[diff] [blame]1525//===----------------------------------------------------------------------===//
Nicolai Haehnleb1427702016-03-10 18:43:50 +0000[diff] [blame]1526// buffer_load/store_format patterns
1527//===----------------------------------------------------------------------===//
Nicolai Haehnleb1427702016-03-10 18:43:50 +0000[diff] [blame]1528
Nicolai Haehnledf77c9a2016-04-12 21:18:10 +0000[diff] [blame]1529multiclass MUBUF_LoadIntrinsicPat<SDPatternOperator name, ValueType vt,
1530 string opcode> {
Nicolai Haehnle95e8ffd2016-03-18 16:24:40 +0000[diff] [blame]1531 def : Pat<
Nicolai Haehnledf77c9a2016-04-12 21:18:10 +0000[diff] [blame]1532 (vt (name v4i32:$rsrc, 0,
1533 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
1534 imm:$glc, imm:$slc)),
Nicolai Haehnle95e8ffd2016-03-18 16:24:40 +0000[diff] [blame]1535 (!cast<MUBUF>(opcode # _OFFSET) $rsrc, $soffset, (as_i16imm $offset),
1536 (as_i1imm $glc), (as_i1imm $slc), 0)
1537 >;
Nicolai Haehnleb1427702016-03-10 18:43:50 +0000[diff] [blame]1538
Nicolai Haehnle95e8ffd2016-03-18 16:24:40 +0000[diff] [blame]1539 def : Pat<
Nicolai Haehnledf77c9a2016-04-12 21:18:10 +0000[diff] [blame]1540 (vt (name v4i32:$rsrc, i32:$vindex,
1541 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
1542 imm:$glc, imm:$slc)),
Nicolai Haehnle95e8ffd2016-03-18 16:24:40 +0000[diff] [blame]1543 (!cast<MUBUF>(opcode # _IDXEN) $vindex, $rsrc, $soffset, (as_i16imm $offset),
1544 (as_i1imm $glc), (as_i1imm $slc), 0)
1545 >;
Nicolai Haehnleb1427702016-03-10 18:43:50 +0000[diff] [blame]1546
Nicolai Haehnle95e8ffd2016-03-18 16:24:40 +0000[diff] [blame]1547 def : Pat<
Nicolai Haehnledf77c9a2016-04-12 21:18:10 +0000[diff] [blame]1548 (vt (name v4i32:$rsrc, 0,
1549 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
1550 imm:$glc, imm:$slc)),
Nicolai Haehnle95e8ffd2016-03-18 16:24:40 +0000[diff] [blame]1551 (!cast<MUBUF>(opcode # _OFFEN) $voffset, $rsrc, $soffset, (as_i16imm $offset),
1552 (as_i1imm $glc), (as_i1imm $slc), 0)
1553 >;
1554
1555 def : Pat<
Nicolai Haehnledf77c9a2016-04-12 21:18:10 +0000[diff] [blame]1556 (vt (name v4i32:$rsrc, i32:$vindex,
1557 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
1558 imm:$glc, imm:$slc)),
Nicolai Haehnle95e8ffd2016-03-18 16:24:40 +0000[diff] [blame]1559 (!cast<MUBUF>(opcode # _BOTHEN)
1560 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
1561 $rsrc, $soffset, (as_i16imm $offset),
1562 (as_i1imm $glc), (as_i1imm $slc), 0)
1563 >;
1564}
1565
Nicolai Haehnledf77c9a2016-04-12 21:18:10 +0000[diff] [blame]1566defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load_format, f32, "BUFFER_LOAD_FORMAT_X">;
1567defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load_format, v2f32, "BUFFER_LOAD_FORMAT_XY">;
1568defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load_format, v4f32, "BUFFER_LOAD_FORMAT_XYZW">;
1569defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load, f32, "BUFFER_LOAD_DWORD">;
1570defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load, v2f32, "BUFFER_LOAD_DWORDX2">;
1571defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load, v4f32, "BUFFER_LOAD_DWORDX4">;
Nicolai Haehnleb1427702016-03-10 18:43:50 +0000[diff] [blame]1572
Nicolai Haehnledf77c9a2016-04-12 21:18:10 +0000[diff] [blame]1573multiclass MUBUF_StoreIntrinsicPat<SDPatternOperator name, ValueType vt,
1574 string opcode> {
1575 def : Pat<
1576 (name vt:$vdata, v4i32:$rsrc, 0,
1577 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
1578 imm:$glc, imm:$slc),
Nicolai Haehnle8a482b32016-08-02 19:31:14 +0000[diff] [blame]1579 (!cast<MUBUF>(opcode # _OFFSET_exact) $vdata, $rsrc, $soffset, (as_i16imm $offset),
Nicolai Haehnledf77c9a2016-04-12 21:18:10 +0000[diff] [blame]1580 (as_i1imm $glc), (as_i1imm $slc), 0)
1581 >;
Nicolai Haehnleb1427702016-03-10 18:43:50 +0000[diff] [blame]1582
Nicolai Haehnledf77c9a2016-04-12 21:18:10 +0000[diff] [blame]1583 def : Pat<
1584 (name vt:$vdata, v4i32:$rsrc, i32:$vindex,
1585 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
1586 imm:$glc, imm:$slc),
Nicolai Haehnle8a482b32016-08-02 19:31:14 +0000[diff] [blame]1587 (!cast<MUBUF>(opcode # _IDXEN_exact) $vdata, $vindex, $rsrc, $soffset,
Nicolai Haehnledf77c9a2016-04-12 21:18:10 +0000[diff] [blame]1588 (as_i16imm $offset), (as_i1imm $glc),
1589 (as_i1imm $slc), 0)
1590 >;
Nicolai Haehnleb1427702016-03-10 18:43:50 +0000[diff] [blame]1591
Nicolai Haehnledf77c9a2016-04-12 21:18:10 +0000[diff] [blame]1592 def : Pat<
1593 (name vt:$vdata, v4i32:$rsrc, 0,
1594 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
1595 imm:$glc, imm:$slc),
Nicolai Haehnle8a482b32016-08-02 19:31:14 +0000[diff] [blame]1596 (!cast<MUBUF>(opcode # _OFFEN_exact) $vdata, $voffset, $rsrc, $soffset,
Nicolai Haehnledf77c9a2016-04-12 21:18:10 +0000[diff] [blame]1597 (as_i16imm $offset), (as_i1imm $glc),
1598 (as_i1imm $slc), 0)
1599 >;
Nicolai Haehnleb1427702016-03-10 18:43:50 +0000[diff] [blame]1600
Nicolai Haehnledf77c9a2016-04-12 21:18:10 +0000[diff] [blame]1601 def : Pat<
1602 (name vt:$vdata, v4i32:$rsrc, i32:$vindex,
1603 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
1604 imm:$glc, imm:$slc),
Nicolai Haehnle8a482b32016-08-02 19:31:14 +0000[diff] [blame]1605 (!cast<MUBUF>(opcode # _BOTHEN_exact)
Nicolai Haehnledf77c9a2016-04-12 21:18:10 +0000[diff] [blame]1606 $vdata,
1607 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
1608 $rsrc, $soffset, (as_i16imm $offset),
1609 (as_i1imm $glc), (as_i1imm $slc), 0)
1610 >;
1611}
1612
1613defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store_format, f32, "BUFFER_STORE_FORMAT_X">;
1614defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store_format, v2f32, "BUFFER_STORE_FORMAT_XY">;
1615defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store_format, v4f32, "BUFFER_STORE_FORMAT_XYZW">;
1616defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store, f32, "BUFFER_STORE_DWORD">;
1617defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store, v2f32, "BUFFER_STORE_DWORDX2">;
1618defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store, v4f32, "BUFFER_STORE_DWORDX4">;
Nicolai Haehnleb1427702016-03-10 18:43:50 +0000[diff] [blame]1619
1620//===----------------------------------------------------------------------===//
Nicolai Haehnlead636382016-03-18 16:24:31 +0000[diff] [blame]1621// buffer_atomic patterns
1622//===----------------------------------------------------------------------===//
1623multiclass BufferAtomicPatterns<SDPatternOperator name, string opcode> {
1624 def : Pat<
1625 (name i32:$vdata_in, v4i32:$rsrc, 0,
1626 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
1627 imm:$slc),
1628 (!cast<MUBUF>(opcode # _RTN_OFFSET) $vdata_in, $rsrc, $soffset,
1629 (as_i16imm $offset), (as_i1imm $slc))
1630 >;
1631
1632 def : Pat<
1633 (name i32:$vdata_in, v4i32:$rsrc, i32:$vindex,
1634 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
1635 imm:$slc),
1636 (!cast<MUBUF>(opcode # _RTN_IDXEN) $vdata_in, $vindex, $rsrc, $soffset,
1637 (as_i16imm $offset), (as_i1imm $slc))
1638 >;
1639
1640 def : Pat<
1641 (name i32:$vdata_in, v4i32:$rsrc, 0,
1642 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
1643 imm:$slc),
1644 (!cast<MUBUF>(opcode # _RTN_OFFEN) $vdata_in, $voffset, $rsrc, $soffset,
1645 (as_i16imm $offset), (as_i1imm $slc))
1646 >;
1647
1648 def : Pat<
1649 (name i32:$vdata_in, v4i32:$rsrc, i32:$vindex,
1650 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
1651 imm:$slc),
1652 (!cast<MUBUF>(opcode # _RTN_BOTHEN)
1653 $vdata_in,
1654 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
1655 $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc))
1656 >;
1657}
1658
1659defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_swap, "BUFFER_ATOMIC_SWAP">;
1660defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_add, "BUFFER_ATOMIC_ADD">;
1661defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_sub, "BUFFER_ATOMIC_SUB">;
1662defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_smin, "BUFFER_ATOMIC_SMIN">;
1663defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_umin, "BUFFER_ATOMIC_UMIN">;
1664defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_smax, "BUFFER_ATOMIC_SMAX">;
1665defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_umax, "BUFFER_ATOMIC_UMAX">;
1666defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_and, "BUFFER_ATOMIC_AND">;
1667defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_or, "BUFFER_ATOMIC_OR">;
1668defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_xor, "BUFFER_ATOMIC_XOR">;
1669
1670def : Pat<
1671 (int_amdgcn_buffer_atomic_cmpswap
1672 i32:$data, i32:$cmp, v4i32:$rsrc, 0,
1673 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
1674 imm:$slc),
1675 (EXTRACT_SUBREG
1676 (BUFFER_ATOMIC_CMPSWAP_RTN_OFFSET
1677 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
1678 $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
1679 sub0)
1680>;
1681
1682def : Pat<
1683 (int_amdgcn_buffer_atomic_cmpswap
1684 i32:$data, i32:$cmp, v4i32:$rsrc, i32:$vindex,
1685 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
1686 imm:$slc),
1687 (EXTRACT_SUBREG
1688 (BUFFER_ATOMIC_CMPSWAP_RTN_IDXEN
1689 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
1690 $vindex, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
1691 sub0)
1692>;
1693
1694def : Pat<
1695 (int_amdgcn_buffer_atomic_cmpswap
1696 i32:$data, i32:$cmp, v4i32:$rsrc, 0,
1697 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
1698 imm:$slc),
1699 (EXTRACT_SUBREG
1700 (BUFFER_ATOMIC_CMPSWAP_RTN_OFFEN
1701 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
1702 $voffset, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
1703 sub0)
1704>;
1705
1706def : Pat<
1707 (int_amdgcn_buffer_atomic_cmpswap
1708 i32:$data, i32:$cmp, v4i32:$rsrc, i32:$vindex,
1709 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
1710 imm:$slc),
1711 (EXTRACT_SUBREG
1712 (BUFFER_ATOMIC_CMPSWAP_RTN_BOTHEN
1713 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
1714 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
1715 $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
1716 sub0)
1717>;
1718
Changpeng Fang278a5b32016-03-10 16:47:15 +0000[diff] [blame]1719//===----------------------------------------------------------------------===//
Wei Ding07e03712016-07-28 16:42:13 +0000[diff] [blame]1720// V_ICMPIntrinsic Pattern.
1721//===----------------------------------------------------------------------===//
1722class ICMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> : Pat <
1723 (AMDGPUsetcc vt:$src0, vt:$src1, cond),
1724 (inst $src0, $src1)
1725>;
1726
1727def : ICMP_Pattern <COND_EQ, V_CMP_EQ_I32_e64, i32>;
1728def : ICMP_Pattern <COND_NE, V_CMP_NE_I32_e64, i32>;
1729def : ICMP_Pattern <COND_UGT, V_CMP_GT_U32_e64, i32>;
1730def : ICMP_Pattern <COND_UGE, V_CMP_GE_U32_e64, i32>;
1731def : ICMP_Pattern <COND_ULT, V_CMP_LT_U32_e64, i32>;
1732def : ICMP_Pattern <COND_ULE, V_CMP_LE_U32_e64, i32>;
1733def : ICMP_Pattern <COND_SGT, V_CMP_GT_I32_e64, i32>;
1734def : ICMP_Pattern <COND_SGE, V_CMP_GE_I32_e64, i32>;
1735def : ICMP_Pattern <COND_SLT, V_CMP_LT_I32_e64, i32>;
1736def : ICMP_Pattern <COND_SLE, V_CMP_LE_I32_e64, i32>;
1737
1738def : ICMP_Pattern <COND_EQ, V_CMP_EQ_I64_e64, i64>;
1739def : ICMP_Pattern <COND_NE, V_CMP_NE_I64_e64, i64>;
1740def : ICMP_Pattern <COND_UGT, V_CMP_GT_U64_e64, i64>;
1741def : ICMP_Pattern <COND_UGE, V_CMP_GE_U64_e64, i64>;
1742def : ICMP_Pattern <COND_ULT, V_CMP_LT_U64_e64, i64>;
1743def : ICMP_Pattern <COND_ULE, V_CMP_LE_U64_e64, i64>;
1744def : ICMP_Pattern <COND_SGT, V_CMP_GT_I64_e64, i64>;
1745def : ICMP_Pattern <COND_SGE, V_CMP_GE_I64_e64, i64>;
1746def : ICMP_Pattern <COND_SLT, V_CMP_LT_I64_e64, i64>;
1747def : ICMP_Pattern <COND_SLE, V_CMP_LE_I64_e64, i64>;
1748
1749class FCMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> : Pat <
1750 (i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
1751 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),
1752 (inst $src0_modifiers, $src0, $src1_modifiers, $src1,
1753 DSTCLAMP.NONE, DSTOMOD.NONE)
1754>;
1755
1756def : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F32_e64, f32>;
1757def : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F32_e64, f32>;
1758def : FCMP_Pattern <COND_OGT, V_CMP_GT_F32_e64, f32>;
1759def : FCMP_Pattern <COND_OGE, V_CMP_GE_F32_e64, f32>;
1760def : FCMP_Pattern <COND_OLT, V_CMP_LT_F32_e64, f32>;
1761def : FCMP_Pattern <COND_OLE, V_CMP_LE_F32_e64, f32>;
1762
1763def : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F64_e64, f64>;
1764def : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F64_e64, f64>;
1765def : FCMP_Pattern <COND_OGT, V_CMP_GT_F64_e64, f64>;
1766def : FCMP_Pattern <COND_OGE, V_CMP_GE_F64_e64, f64>;
1767def : FCMP_Pattern <COND_OLT, V_CMP_LT_F64_e64, f64>;
1768def : FCMP_Pattern <COND_OLE, V_CMP_LE_F64_e64, f64>;
1769
1770def : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F32_e64, f32>;
1771def : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F32_e64, f32>;
1772def : FCMP_Pattern <COND_UGT, V_CMP_NLE_F32_e64, f32>;
1773def : FCMP_Pattern <COND_UGE, V_CMP_NLT_F32_e64, f32>;
1774def : FCMP_Pattern <COND_ULT, V_CMP_NGE_F32_e64, f32>;
1775def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F32_e64, f32>;
1776
1777def : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F64_e64, f64>;
1778def : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F64_e64, f64>;
1779def : FCMP_Pattern <COND_UGT, V_CMP_NLE_F64_e64, f64>;
1780def : FCMP_Pattern <COND_UGE, V_CMP_NLT_F64_e64, f64>;
1781def : FCMP_Pattern <COND_ULT, V_CMP_NGE_F64_e64, f64>;
1782def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F64_e64, f64>;
Tom Stellarda6f24c62015-12-15 20:55:55 +0000[diff] [blame]1783
Tom Stellardae4c9e72014-06-20 17:06:11 +0000[diff] [blame]1784//===----------------------------------------------------------------------===//
Matt Arsenaulta0050b02014-06-19 01:19:19 +0000[diff] [blame]1785// VOP1 Patterns
1786//===----------------------------------------------------------------------===//
1787
Matt Arsenault22ca3f82014-07-15 23:50:10 +0000[diff] [blame]1788let Predicates = [UnsafeFPMath] in {
Matt Arsenault0bbcd8b2015-02-14 04:30:08 +0000[diff] [blame]1789
1790//def : RcpPat<V_RCP_F64_e32, f64>;
1791//defm : RsqPat<V_RSQ_F64_e32, f64>;
1792//defm : RsqPat<V_RSQ_F32_e32, f32>;
1793
1794def : RsqPat<V_RSQ_F32_e32, f32>;
1795def : RsqPat<V_RSQ_F64_e32, f64>;
Matt Arsenault74015162016-05-28 00:19:52 +0000[diff] [blame]1796
1797// Convert (x - floor(x)) to fract(x)
1798def : Pat <
1799 (f32 (fsub (f32 (VOP3Mods f32:$x, i32:$mods)),
1800 (f32 (ffloor (f32 (VOP3Mods f32:$x, i32:$mods)))))),
1801 (V_FRACT_F32_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)
1802>;
1803
1804// Convert (x + (-floor(x))) to fract(x)
1805def : Pat <
1806 (f64 (fadd (f64 (VOP3Mods f64:$x, i32:$mods)),
1807 (f64 (fneg (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))))))),
1808 (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)
1809>;
1810
1811} // End Predicates = [UnsafeFPMath]
Matt Arsenaulte9fa3b82014-07-15 20:18:31 +0000[diff] [blame]1812
Matt Arsenaulta0050b02014-06-19 01:19:19 +0000[diff] [blame]1813//===----------------------------------------------------------------------===//
Tom Stellard58ac7442014-04-29 23:12:48 +0000[diff] [blame]1814// VOP2 Patterns
1815//===----------------------------------------------------------------------===//
1816
Tom Stellardae4c9e72014-06-20 17:06:11 +0000[diff] [blame]1817def : Pat <
1818 (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)),
Matt Arsenault49dd4282014-09-15 17:15:02 +0000[diff] [blame]1819 (V_BCNT_U32_B32_e64 $popcnt, $val)
Tom Stellardae4c9e72014-06-20 17:06:11 +0000[diff] [blame]1820>;
1821
Tom Stellard5224df32015-03-10 16:16:44 +0000[diff] [blame]1822def : Pat <
1823 (i32 (select i1:$src0, i32:$src1, i32:$src2)),
1824 (V_CNDMASK_B32_e64 $src2, $src1, $src0)
1825>;
1826
Tom Stellarddb5a11f2015-07-13 15:47:57 +0000[diff] [blame]1827// Pattern for V_MAC_F32
1828def : Pat <
1829 (fmad (VOP3NoMods0 f32:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
1830 (VOP3NoMods f32:$src1, i32:$src1_modifiers),
1831 (VOP3NoMods f32:$src2, i32:$src2_modifiers)),
1832 (V_MAC_F32_e64 $src0_modifiers, $src0, $src1_modifiers, $src1,
1833 $src2_modifiers, $src2, $clamp, $omod)
1834>;
1835
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]1836/********** ======================= **********/
1837/********** Image sampling patterns **********/
1838/********** ======================= **********/
Tom Stellardae6c06e2013-02-07 17:02:13 +0000[diff] [blame]1839
Marek Olsakd8ecaee2014-07-11 17:11:46 +0000[diff] [blame]1840// Image + sampler
Marek Olsak51b8e7b2014-06-18 22:00:29 +0000[diff] [blame]1841class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
Marek Olsakeac50622014-07-11 17:11:52 +0000[diff] [blame]1842 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm,
Marek Olsak51b8e7b2014-06-18 22:00:29 +0000[diff] [blame]1843 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
Nikolay Haustov2f684f12016-02-26 09:51:05 +0000[diff] [blame]1844 (opcode $addr, $rsrc, $sampler,
1845 (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc),
1846 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da))
Marek Olsak51b8e7b2014-06-18 22:00:29 +0000[diff] [blame]1847>;
1848
Marek Olsakd8ecaee2014-07-11 17:11:46 +0000[diff] [blame]1849multiclass SampleRawPatterns<SDPatternOperator name, string opcode> {
1850 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
1851 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
1852 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
1853 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>;
1854 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>;
1855}
1856
Changpeng Fangfb9c3812016-08-10 21:15:30 +0000[diff] [blame]1857
1858// Image + sampler for amdgcn
1859// TODO:
1860// 1. Handle half data type like v4f16, and add D16 bit support;
1861// 2. Handle v4i32 rsrc type (Register Class for the instruction to be SReg_128).
1862// 3. Add A16 support when we pass address of half type.
1863multiclass AMDGCNSamplePattern<SDPatternOperator name, MIMG opcode, ValueType vt> {
1864 def : Pat<
1865 (v4f32 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i1:$unorm, i1:$glc,
1866 i1:$slc, i1:$lwe, i1:$da)),
1867 (opcode $addr, $rsrc, $sampler,
1868 (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc),
1869 0, 0, (as_i1imm $lwe), (as_i1imm $da))
1870 >;
1871}
1872
1873multiclass AMDGCNSamplePatterns<SDPatternOperator name, string opcode> {
1874 defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V4_V1), f32>;
1875 defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V4_V2), v2f32>;
1876 defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V4_V4), v4f32>;
1877 defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V4_V8), v8f32>;
1878 defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V4_V16), v16f32>;
1879}
1880
1881
Marek Olsakd8ecaee2014-07-11 17:11:46 +0000[diff] [blame]1882// Image only
1883class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
Nicolai Haehnlef2c64db2016-02-18 16:44:18 +0000[diff] [blame]1884 (name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$unorm,
1885 imm:$r128, imm:$da, imm:$glc, imm:$slc, imm:$tfe, imm:$lwe),
Nikolay Haustov2f684f12016-02-26 09:51:05 +0000[diff] [blame]1886 (opcode $addr, $rsrc,
1887 (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc),
1888 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da))
Marek Olsakd8ecaee2014-07-11 17:11:46 +0000[diff] [blame]1889>;
1890
1891multiclass ImagePatterns<SDPatternOperator name, string opcode> {
1892 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
1893 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
1894 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
1895}
1896
Nicolai Haehnlef2c64db2016-02-18 16:44:18 +0000[diff] [blame]1897class ImageLoadPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
1898 (name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$r128, imm:$da, imm:$glc,
1899 imm:$slc),
Nikolay Haustov2f684f12016-02-26 09:51:05 +0000[diff] [blame]1900 (opcode $addr, $rsrc,
1901 (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc),
1902 (as_i1imm $r128), 0, 0, (as_i1imm $da))
Nicolai Haehnlef2c64db2016-02-18 16:44:18 +0000[diff] [blame]1903>;
1904
1905multiclass ImageLoadPatterns<SDPatternOperator name, string opcode> {
1906 def : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
1907 def : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
1908 def : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
1909}
1910
1911class ImageStorePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
1912 (name v4f32:$data, vt:$addr, v8i32:$rsrc, i32:$dmask, imm:$r128, imm:$da,
1913 imm:$glc, imm:$slc),
Nikolay Haustov2f684f12016-02-26 09:51:05 +0000[diff] [blame]1914 (opcode $data, $addr, $rsrc,
1915 (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc),
1916 (as_i1imm $r128), 0, 0, (as_i1imm $da))
Nicolai Haehnlef2c64db2016-02-18 16:44:18 +0000[diff] [blame]1917>;
1918
1919multiclass ImageStorePatterns<SDPatternOperator name, string opcode> {
1920 def : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
1921 def : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
1922 def : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
1923}
1924
Nikolay Haustov5bf46ac12016-03-04 10:39:50 +0000[diff] [blame]1925class ImageAtomicPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
1926 (name i32:$vdata, vt:$addr, v8i32:$rsrc, imm:$r128, imm:$da, imm:$slc),
1927 (opcode $vdata, $addr, $rsrc, 1, 1, 1, (as_i1imm $slc), (as_i1imm $r128), 0, 0, (as_i1imm $da))
1928>;
1929
1930multiclass ImageAtomicPatterns<SDPatternOperator name, string opcode> {
1931 def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V1), i32>;
1932 def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V2), v2i32>;
1933 def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V4), v4i32>;
1934}
1935
1936class ImageAtomicCmpSwapPattern<MIMG opcode, ValueType vt> : Pat <
1937 (int_amdgcn_image_atomic_cmpswap i32:$vsrc, i32:$vcmp, vt:$addr, v8i32:$rsrc,
1938 imm:$r128, imm:$da, imm:$slc),
1939 (EXTRACT_SUBREG
1940 (opcode (REG_SEQUENCE VReg_64, $vsrc, sub0, $vcmp, sub1),
1941 $addr, $rsrc, 3, 1, 1, (as_i1imm $slc), (as_i1imm $r128), 0, 0, (as_i1imm $da)),
1942 sub0)
1943>;
1944
Changpeng Fangfb9c3812016-08-10 21:15:30 +0000[diff] [blame]1945// ======= SI Image Intrinsics ================
1946
1947// Image load
1948defm : ImagePatterns<int_SI_image_load, "IMAGE_LOAD">;
1949defm : ImagePatterns<int_SI_image_load_mip, "IMAGE_LOAD_MIP">;
1950def : ImagePattern<int_SI_getresinfo, IMAGE_GET_RESINFO_V4_V1, i32>;
1951
Marek Olsakd8ecaee2014-07-11 17:11:46 +0000[diff] [blame]1952// Basic sample
1953defm : SampleRawPatterns<int_SI_image_sample, "IMAGE_SAMPLE">;
1954defm : SampleRawPatterns<int_SI_image_sample_cl, "IMAGE_SAMPLE_CL">;
1955defm : SampleRawPatterns<int_SI_image_sample_d, "IMAGE_SAMPLE_D">;
1956defm : SampleRawPatterns<int_SI_image_sample_d_cl, "IMAGE_SAMPLE_D_CL">;
1957defm : SampleRawPatterns<int_SI_image_sample_l, "IMAGE_SAMPLE_L">;
1958defm : SampleRawPatterns<int_SI_image_sample_b, "IMAGE_SAMPLE_B">;
1959defm : SampleRawPatterns<int_SI_image_sample_b_cl, "IMAGE_SAMPLE_B_CL">;
1960defm : SampleRawPatterns<int_SI_image_sample_lz, "IMAGE_SAMPLE_LZ">;
1961defm : SampleRawPatterns<int_SI_image_sample_cd, "IMAGE_SAMPLE_CD">;
1962defm : SampleRawPatterns<int_SI_image_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">;
1963
1964// Sample with comparison
1965defm : SampleRawPatterns<int_SI_image_sample_c, "IMAGE_SAMPLE_C">;
1966defm : SampleRawPatterns<int_SI_image_sample_c_cl, "IMAGE_SAMPLE_C_CL">;
1967defm : SampleRawPatterns<int_SI_image_sample_c_d, "IMAGE_SAMPLE_C_D">;
1968defm : SampleRawPatterns<int_SI_image_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">;
1969defm : SampleRawPatterns<int_SI_image_sample_c_l, "IMAGE_SAMPLE_C_L">;
1970defm : SampleRawPatterns<int_SI_image_sample_c_b, "IMAGE_SAMPLE_C_B">;
1971defm : SampleRawPatterns<int_SI_image_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">;
1972defm : SampleRawPatterns<int_SI_image_sample_c_lz, "IMAGE_SAMPLE_C_LZ">;
1973defm : SampleRawPatterns<int_SI_image_sample_c_cd, "IMAGE_SAMPLE_C_CD">;
1974defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">;
1975
1976// Sample with offsets
1977defm : SampleRawPatterns<int_SI_image_sample_o, "IMAGE_SAMPLE_O">;
1978defm : SampleRawPatterns<int_SI_image_sample_cl_o, "IMAGE_SAMPLE_CL_O">;
1979defm : SampleRawPatterns<int_SI_image_sample_d_o, "IMAGE_SAMPLE_D_O">;
1980defm : SampleRawPatterns<int_SI_image_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">;
1981defm : SampleRawPatterns<int_SI_image_sample_l_o, "IMAGE_SAMPLE_L_O">;
1982defm : SampleRawPatterns<int_SI_image_sample_b_o, "IMAGE_SAMPLE_B_O">;
1983defm : SampleRawPatterns<int_SI_image_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">;
1984defm : SampleRawPatterns<int_SI_image_sample_lz_o, "IMAGE_SAMPLE_LZ_O">;
1985defm : SampleRawPatterns<int_SI_image_sample_cd_o, "IMAGE_SAMPLE_CD_O">;
1986defm : SampleRawPatterns<int_SI_image_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">;
1987
1988// Sample with comparison and offsets
1989defm : SampleRawPatterns<int_SI_image_sample_c_o, "IMAGE_SAMPLE_C_O">;
1990defm : SampleRawPatterns<int_SI_image_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">;
1991defm : SampleRawPatterns<int_SI_image_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">;
1992defm : SampleRawPatterns<int_SI_image_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">;
1993defm : SampleRawPatterns<int_SI_image_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">;
1994defm : SampleRawPatterns<int_SI_image_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">;
1995defm : SampleRawPatterns<int_SI_image_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">;
1996defm : SampleRawPatterns<int_SI_image_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">;
1997defm : SampleRawPatterns<int_SI_image_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">;
1998defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">;
1999
2000// Gather opcodes
Marek Olsak51b8e7b2014-06-18 22:00:29 +0000[diff] [blame]2001// Only the variants which make sense are defined.
2002def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V2, v2i32>;
2003def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V4, v4i32>;
2004def : SampleRawPattern<int_SI_gather4_cl, IMAGE_GATHER4_CL_V4_V4, v4i32>;
2005def : SampleRawPattern<int_SI_gather4_l, IMAGE_GATHER4_L_V4_V4, v4i32>;
2006def : SampleRawPattern<int_SI_gather4_b, IMAGE_GATHER4_B_V4_V4, v4i32>;
2007def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V4, v4i32>;
2008def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8i32>;
2009def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V2, v2i32>;
2010def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V4, v4i32>;
2011
2012def : SampleRawPattern<int_SI_gather4_c, IMAGE_GATHER4_C_V4_V4, v4i32>;
2013def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V4, v4i32>;
2014def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8i32>;
2015def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V4, v4i32>;
2016def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8i32>;
2017def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V4, v4i32>;
2018def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8i32>;
2019def : SampleRawPattern<int_SI_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8i32>;
2020def : SampleRawPattern<int_SI_gather4_c_lz, IMAGE_GATHER4_C_LZ_V4_V4, v4i32>;
2021
2022def : SampleRawPattern<int_SI_gather4_o, IMAGE_GATHER4_O_V4_V4, v4i32>;
2023def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V4, v4i32>;
2024def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8i32>;
2025def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V4, v4i32>;
2026def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V8, v8i32>;
2027def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V4, v4i32>;
2028def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V8, v8i32>;
2029def : SampleRawPattern<int_SI_gather4_b_cl_o, IMAGE_GATHER4_B_CL_O_V4_V8, v8i32>;
2030def : SampleRawPattern<int_SI_gather4_lz_o, IMAGE_GATHER4_LZ_O_V4_V4, v4i32>;
2031
2032def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V4, v4i32>;
2033def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V8, v8i32>;
2034def : SampleRawPattern<int_SI_gather4_c_cl_o, IMAGE_GATHER4_C_CL_O_V4_V8, v8i32>;
2035def : SampleRawPattern<int_SI_gather4_c_l_o, IMAGE_GATHER4_C_L_O_V4_V8, v8i32>;
2036def : SampleRawPattern<int_SI_gather4_c_b_o, IMAGE_GATHER4_C_B_O_V4_V8, v8i32>;
2037def : SampleRawPattern<int_SI_gather4_c_b_cl_o, IMAGE_GATHER4_C_B_CL_O_V4_V8, v8i32>;
2038def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V4, v4i32>;
2039def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V8, v8i32>;
2040
2041def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V1, i32>;
2042def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V2, v2i32>;
2043def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V4, v4i32>;
2044
Changpeng Fangfb9c3812016-08-10 21:15:30 +0000[diff] [blame]2045
2046// ======= amdgcn Image Intrinsics ==============
2047
2048// Image load
Nicolai Haehnlef2c64db2016-02-18 16:44:18 +0000[diff] [blame]2049defm : ImageLoadPatterns<int_amdgcn_image_load, "IMAGE_LOAD">;
2050defm : ImageLoadPatterns<int_amdgcn_image_load_mip, "IMAGE_LOAD_MIP">;
Changpeng Fangfb9c3812016-08-10 21:15:30 +0000[diff] [blame]2051
2052// Image store
Nicolai Haehnlef2c64db2016-02-18 16:44:18 +0000[diff] [blame]2053defm : ImageStorePatterns<int_amdgcn_image_store, "IMAGE_STORE">;
2054defm : ImageStorePatterns<int_amdgcn_image_store_mip, "IMAGE_STORE_MIP">;
Changpeng Fangfb9c3812016-08-10 21:15:30 +0000[diff] [blame]2055
2056// Basic sample
2057defm : AMDGCNSamplePatterns<int_amdgcn_image_sample, "IMAGE_SAMPLE">;
2058defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cl, "IMAGE_SAMPLE_CL">;
2059defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_d, "IMAGE_SAMPLE_D">;
2060defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_d_cl, "IMAGE_SAMPLE_D_CL">;
2061defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_l, "IMAGE_SAMPLE_L">;
2062defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_b, "IMAGE_SAMPLE_B">;
2063defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_b_cl, "IMAGE_SAMPLE_B_CL">;
2064defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_lz, "IMAGE_SAMPLE_LZ">;
2065defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cd, "IMAGE_SAMPLE_CD">;
2066defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">;
2067
2068// Sample with comparison
2069defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c, "IMAGE_SAMPLE_C">;
2070defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cl, "IMAGE_SAMPLE_C_CL">;
2071defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_d, "IMAGE_SAMPLE_C_D">;
2072defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">;
2073defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_l, "IMAGE_SAMPLE_C_L">;
2074defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_b, "IMAGE_SAMPLE_C_B">;
2075defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">;
2076defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_lz, "IMAGE_SAMPLE_C_LZ">;
2077defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cd, "IMAGE_SAMPLE_C_CD">;
2078defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">;
2079
2080// Sample with offsets
2081defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_o, "IMAGE_SAMPLE_O">;
2082defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cl_o, "IMAGE_SAMPLE_CL_O">;
2083defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_d_o, "IMAGE_SAMPLE_D_O">;
2084defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">;
2085defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_l_o, "IMAGE_SAMPLE_L_O">;
2086defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_b_o, "IMAGE_SAMPLE_B_O">;
2087defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">;
2088defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_lz_o, "IMAGE_SAMPLE_LZ_O">;
2089defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cd_o, "IMAGE_SAMPLE_CD_O">;
2090defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">;
2091
2092// Sample with comparison and offsets
2093defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_o, "IMAGE_SAMPLE_C_O">;
2094defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">;
2095defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">;
2096defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">;
2097defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">;
2098defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">;
2099defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">;
2100defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">;
2101defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">;
2102defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">;
2103
2104// Gather opcodes
2105// Only the variants which make sense are defined.
2106defm : AMDGCNSamplePattern<int_amdgcn_image_gather4, IMAGE_GATHER4_V4_V2, v2f32>;
2107defm : AMDGCNSamplePattern<int_amdgcn_image_gather4, IMAGE_GATHER4_V4_V4, v4f32>;
2108defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_cl, IMAGE_GATHER4_CL_V4_V4, v4f32>;
2109defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_l, IMAGE_GATHER4_L_V4_V4, v4f32>;
2110defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_b, IMAGE_GATHER4_B_V4_V4, v4f32>;
2111defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V4, v4f32>;
2112defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8f32>;
2113defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_lz, IMAGE_GATHER4_LZ_V4_V2, v2f32>;
2114defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_lz, IMAGE_GATHER4_LZ_V4_V4, v4f32>;
2115
2116defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c, IMAGE_GATHER4_C_V4_V4, v4f32>;
2117defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V4, v4f32>;
2118defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8f32>;
2119defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_l, IMAGE_GATHER4_C_L_V4_V4, v4f32>;
2120defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8f32>;
2121defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_b, IMAGE_GATHER4_C_B_V4_V4, v4f32>;
2122defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8f32>;
2123defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8f32>;
2124defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_lz, IMAGE_GATHER4_C_LZ_V4_V4, v4f32>;
2125
2126defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_o, IMAGE_GATHER4_O_V4_V4, v4f32>;
2127defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V4, v4f32>;
2128defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8f32>;
2129defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_l_o, IMAGE_GATHER4_L_O_V4_V4, v4f32>;
2130defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_l_o, IMAGE_GATHER4_L_O_V4_V8, v8f32>;
2131defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_b_o, IMAGE_GATHER4_B_O_V4_V4, v4f32>;
2132defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_b_o, IMAGE_GATHER4_B_O_V4_V8, v8f32>;
2133defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_b_cl_o, IMAGE_GATHER4_B_CL_O_V4_V8, v8f32>;
2134defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_lz_o, IMAGE_GATHER4_LZ_O_V4_V4, v4f32>;
2135
2136defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_o, IMAGE_GATHER4_C_O_V4_V4, v4f32>;
2137defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_o, IMAGE_GATHER4_C_O_V4_V8, v8f32>;
2138defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_cl_o, IMAGE_GATHER4_C_CL_O_V4_V8, v8f32>;
2139defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_l_o, IMAGE_GATHER4_C_L_O_V4_V8, v8f32>;
2140defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_b_o, IMAGE_GATHER4_C_B_O_V4_V8, v8f32>;
2141defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_b_cl_o, IMAGE_GATHER4_C_B_CL_O_V4_V8, v8f32>;
2142defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V4, v4f32>;
2143defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V8, v8f32>;
2144
2145defm : AMDGCNSamplePattern<int_amdgcn_image_getlod, IMAGE_GET_LOD_V4_V1, f32>;
2146defm : AMDGCNSamplePattern<int_amdgcn_image_getlod, IMAGE_GET_LOD_V4_V2, v2f32>;
2147defm : AMDGCNSamplePattern<int_amdgcn_image_getlod, IMAGE_GET_LOD_V4_V4, v4f32>;
2148
2149// Image atomics
Nikolay Haustov5bf46ac12016-03-04 10:39:50 +0000[diff] [blame]2150defm : ImageAtomicPatterns<int_amdgcn_image_atomic_swap, "IMAGE_ATOMIC_SWAP">;
2151def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V1, i32>;
2152def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V2, v2i32>;
2153def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V4, v4i32>;
2154defm : ImageAtomicPatterns<int_amdgcn_image_atomic_add, "IMAGE_ATOMIC_ADD">;
2155defm : ImageAtomicPatterns<int_amdgcn_image_atomic_sub, "IMAGE_ATOMIC_SUB">;
2156defm : ImageAtomicPatterns<int_amdgcn_image_atomic_smin, "IMAGE_ATOMIC_SMIN">;
2157defm : ImageAtomicPatterns<int_amdgcn_image_atomic_umin, "IMAGE_ATOMIC_UMIN">;
2158defm : ImageAtomicPatterns<int_amdgcn_image_atomic_smax, "IMAGE_ATOMIC_SMAX">;
2159defm : ImageAtomicPatterns<int_amdgcn_image_atomic_umax, "IMAGE_ATOMIC_UMAX">;
2160defm : ImageAtomicPatterns<int_amdgcn_image_atomic_and, "IMAGE_ATOMIC_AND">;
2161defm : ImageAtomicPatterns<int_amdgcn_image_atomic_or, "IMAGE_ATOMIC_OR">;
2162defm : ImageAtomicPatterns<int_amdgcn_image_atomic_xor, "IMAGE_ATOMIC_XOR">;
2163defm : ImageAtomicPatterns<int_amdgcn_image_atomic_inc, "IMAGE_ATOMIC_INC">;
2164defm : ImageAtomicPatterns<int_amdgcn_image_atomic_dec, "IMAGE_ATOMIC_DEC">;
Marek Olsakd8ecaee2014-07-11 17:11:46 +0000[diff] [blame]2165
Tom Stellard9fa17912013-08-14 23:24:45 +0000[diff] [blame]2166/* SIsample for simple 1D texture lookup */
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]2167def : Pat <
Matt Arsenaultc5f61522016-01-26 04:43:48 +0000[diff] [blame]2168 (SIsample i32:$addr, v8i32:$rsrc, v4i32:$sampler, imm),
Nikolay Haustov2f684f12016-02-26 09:51:05 +0000[diff] [blame]2169 (IMAGE_SAMPLE_V4_V1 $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0)
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]2170>;
2171
Tom Stellard9fa17912013-08-14 23:24:45 +0000[diff] [blame]2172class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
Matt Arsenaultc5f61522016-01-26 04:43:48 +0000[diff] [blame]2173 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, imm),
Nikolay Haustov2f684f12016-02-26 09:51:05 +0000[diff] [blame]2174 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0)
Tom Stellardc9b90312013-01-21 15:40:48 +0000[diff] [blame]2175>;
2176
Tom Stellard9fa17912013-08-14 23:24:45 +0000[diff] [blame]2177class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
Matt Arsenaultc5f61522016-01-26 04:43:48 +0000[diff] [blame]2178 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_RECT),
Nikolay Haustov2f684f12016-02-26 09:51:05 +0000[diff] [blame]2179 (opcode $addr, $rsrc, $sampler, 0xf, 1, 0, 0, 0, 0, 0, 0)
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]2180>;
2181
Tom Stellard9fa17912013-08-14 23:24:45 +0000[diff] [blame]2182class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
Matt Arsenaultc5f61522016-01-26 04:43:48 +0000[diff] [blame]2183 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_ARRAY),
Nikolay Haustov2f684f12016-02-26 09:51:05 +0000[diff] [blame]2184 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1)
Tom Stellard462516b2013-02-07 17:02:14 +0000[diff] [blame]2185>;
2186
Tom Stellard9fa17912013-08-14 23:24:45 +0000[diff] [blame]2187class SampleShadowPattern<SDNode name, MIMG opcode,
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2188 ValueType vt> : Pat <
Matt Arsenaultc5f61522016-01-26 04:43:48 +0000[diff] [blame]2189 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW),
Nikolay Haustov2f684f12016-02-26 09:51:05 +0000[diff] [blame]2190 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0)
Tom Stellard462516b2013-02-07 17:02:14 +0000[diff] [blame]2191>;
2192
Tom Stellard9fa17912013-08-14 23:24:45 +0000[diff] [blame]2193class SampleShadowArrayPattern<SDNode name, MIMG opcode,
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2194 ValueType vt> : Pat <
Matt Arsenaultc5f61522016-01-26 04:43:48 +0000[diff] [blame]2195 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
Nikolay Haustov2f684f12016-02-26 09:51:05 +0000[diff] [blame]2196 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1)
Tom Stellard462516b2013-02-07 17:02:14 +0000[diff] [blame]2197>;
2198
Tom Stellard9fa17912013-08-14 23:24:45 +0000[diff] [blame]2199/* SIsample* for texture lookups consuming more address parameters */
Tom Stellard16a9a202013-08-14 23:24:17 +0000[diff] [blame]2200multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
2201 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
2202MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
Tom Stellard9fa17912013-08-14 23:24:45 +0000[diff] [blame]2203 def : SamplePattern <SIsample, sample, addr_type>;
2204 def : SampleRectPattern <SIsample, sample, addr_type>;
2205 def : SampleArrayPattern <SIsample, sample, addr_type>;
2206 def : SampleShadowPattern <SIsample, sample_c, addr_type>;
2207 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
Tom Stellardae6c06e2013-02-07 17:02:13 +0000[diff] [blame]2208
Tom Stellard9fa17912013-08-14 23:24:45 +0000[diff] [blame]2209 def : SamplePattern <SIsamplel, sample_l, addr_type>;
2210 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
2211 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
2212 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
Tom Stellardae6c06e2013-02-07 17:02:13 +0000[diff] [blame]2213
Tom Stellard9fa17912013-08-14 23:24:45 +0000[diff] [blame]2214 def : SamplePattern <SIsampleb, sample_b, addr_type>;
2215 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
2216 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
2217 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
Michel Danzer83f87c42013-07-10 16:36:36 +0000[diff] [blame]2218
Tom Stellard9fa17912013-08-14 23:24:45 +0000[diff] [blame]2219 def : SamplePattern <SIsampled, sample_d, addr_type>;
2220 def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
2221 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
2222 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
Tom Stellardae6c06e2013-02-07 17:02:13 +0000[diff] [blame]2223}
2224
Tom Stellard682bfbc2013-10-10 17:11:24 +0000[diff] [blame]2225defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2,
2226 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2,
2227 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2,
2228 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2,
Tom Stellard16a9a202013-08-14 23:24:17 +0000[diff] [blame]2229 v2i32>;
Tom Stellard682bfbc2013-10-10 17:11:24 +0000[diff] [blame]2230defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4,
2231 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4,
2232 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4,
2233 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4,
Tom Stellard16a9a202013-08-14 23:24:17 +0000[diff] [blame]2234 v4i32>;
Tom Stellard682bfbc2013-10-10 17:11:24 +0000[diff] [blame]2235defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8,
2236 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8,
2237 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8,
2238 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8,
Tom Stellard16a9a202013-08-14 23:24:17 +0000[diff] [blame]2239 v8i32>;
Tom Stellard682bfbc2013-10-10 17:11:24 +0000[diff] [blame]2240defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
2241 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16,
2242 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16,
2243 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
Tom Stellard16a9a202013-08-14 23:24:17 +0000[diff] [blame]2244 v16i32>;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]2245
Christian Konig4a1b9c32013-03-18 11:34:10 +0000[diff] [blame]2246/********** ============================================ **********/
2247/********** Extraction, Insertion, Building and Casting **********/
2248/********** ============================================ **********/
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]2249
Christian Konig4a1b9c32013-03-18 11:34:10 +0000[diff] [blame]2250foreach Index = 0-2 in {
2251 def Extract_Element_v2i32_#Index : Extract_Element <
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2252 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig4a1b9c32013-03-18 11:34:10 +0000[diff] [blame]2253 >;
2254 def Insert_Element_v2i32_#Index : Insert_Element <
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2255 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig4a1b9c32013-03-18 11:34:10 +0000[diff] [blame]2256 >;
2257
2258 def Extract_Element_v2f32_#Index : Extract_Element <
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2259 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig4a1b9c32013-03-18 11:34:10 +0000[diff] [blame]2260 >;
2261 def Insert_Element_v2f32_#Index : Insert_Element <
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2262 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig4a1b9c32013-03-18 11:34:10 +0000[diff] [blame]2263 >;
2264}
2265
2266foreach Index = 0-3 in {
2267 def Extract_Element_v4i32_#Index : Extract_Element <
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2268 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig4a1b9c32013-03-18 11:34:10 +0000[diff] [blame]2269 >;
2270 def Insert_Element_v4i32_#Index : Insert_Element <
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2271 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig4a1b9c32013-03-18 11:34:10 +0000[diff] [blame]2272 >;
2273
2274 def Extract_Element_v4f32_#Index : Extract_Element <
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2275 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig4a1b9c32013-03-18 11:34:10 +0000[diff] [blame]2276 >;
2277 def Insert_Element_v4f32_#Index : Insert_Element <
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2278 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig4a1b9c32013-03-18 11:34:10 +0000[diff] [blame]2279 >;
2280}
2281
2282foreach Index = 0-7 in {
2283 def Extract_Element_v8i32_#Index : Extract_Element <
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2284 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig4a1b9c32013-03-18 11:34:10 +0000[diff] [blame]2285 >;
2286 def Insert_Element_v8i32_#Index : Insert_Element <
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2287 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig4a1b9c32013-03-18 11:34:10 +0000[diff] [blame]2288 >;
2289
2290 def Extract_Element_v8f32_#Index : Extract_Element <
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2291 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig4a1b9c32013-03-18 11:34:10 +0000[diff] [blame]2292 >;
2293 def Insert_Element_v8f32_#Index : Insert_Element <
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2294 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig4a1b9c32013-03-18 11:34:10 +0000[diff] [blame]2295 >;
2296}
2297
2298foreach Index = 0-15 in {
2299 def Extract_Element_v16i32_#Index : Extract_Element <
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2300 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig4a1b9c32013-03-18 11:34:10 +0000[diff] [blame]2301 >;
2302 def Insert_Element_v16i32_#Index : Insert_Element <
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2303 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig4a1b9c32013-03-18 11:34:10 +0000[diff] [blame]2304 >;
2305
2306 def Extract_Element_v16f32_#Index : Extract_Element <
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2307 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig4a1b9c32013-03-18 11:34:10 +0000[diff] [blame]2308 >;
2309 def Insert_Element_v16f32_#Index : Insert_Element <
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2310 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig4a1b9c32013-03-18 11:34:10 +0000[diff] [blame]2311 >;
2312}
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]2313
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]2314// FIXME: Why do only some of these type combinations for SReg and
2315// VReg?
2316// 32-bit bitcast
Tom Stellard45c0b3a2015-01-07 20:59:25 +0000[diff] [blame]2317def : BitConvert <i32, f32, VGPR_32>;
Tom Stellard45c0b3a2015-01-07 20:59:25 +0000[diff] [blame]2318def : BitConvert <f32, i32, VGPR_32>;
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]2319def : BitConvert <i32, f32, SReg_32>;
2320def : BitConvert <f32, i32, SReg_32>;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]2321
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]2322// 64-bit bitcast
Tom Stellard7512c082013-07-12 18:14:56 +0000[diff] [blame]2323def : BitConvert <i64, f64, VReg_64>;
Tom Stellard7512c082013-07-12 18:14:56 +0000[diff] [blame]2324def : BitConvert <f64, i64, VReg_64>;
Tom Stellarded2f6142013-07-18 21:43:42 +0000[diff] [blame]2325def : BitConvert <v2i32, v2f32, VReg_64>;
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]2326def : BitConvert <v2f32, v2i32, VReg_64>;
Tom Stellard7ea3d6d2014-03-31 14:01:55 +0000[diff] [blame]2327def : BitConvert <i64, v2i32, VReg_64>;
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]2328def : BitConvert <v2i32, i64, VReg_64>;
Matt Arsenault064c2062014-06-11 17:40:32 +0000[diff] [blame]2329def : BitConvert <i64, v2f32, VReg_64>;
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]2330def : BitConvert <v2f32, i64, VReg_64>;
Tom Stellard8f307212015-12-15 17:11:17 +0000[diff] [blame]2331def : BitConvert <f64, v2f32, VReg_64>;
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]2332def : BitConvert <v2f32, f64, VReg_64>;
Matt Arsenault2acc7a42014-06-11 19:31:13 +0000[diff] [blame]2333def : BitConvert <f64, v2i32, VReg_64>;
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]2334def : BitConvert <v2i32, f64, VReg_64>;
Tom Stellard83747202013-07-18 21:43:53 +0000[diff] [blame]2335def : BitConvert <v4i32, v4f32, VReg_128>;
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]2336def : BitConvert <v4f32, v4i32, VReg_128>;
Tom Stellard83747202013-07-18 21:43:53 +0000[diff] [blame]2337
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]2338// 128-bit bitcast
Matt Arsenault61001bb2015-11-25 19:58:34 +0000[diff] [blame]2339def : BitConvert <v2i64, v4i32, SReg_128>;
2340def : BitConvert <v4i32, v2i64, SReg_128>;
Tom Stellard8f307212015-12-15 17:11:17 +0000[diff] [blame]2341def : BitConvert <v2f64, v4f32, VReg_128>;
Matt Arsenault61001bb2015-11-25 19:58:34 +0000[diff] [blame]2342def : BitConvert <v2f64, v4i32, VReg_128>;
Tom Stellard8f307212015-12-15 17:11:17 +0000[diff] [blame]2343def : BitConvert <v4f32, v2f64, VReg_128>;
Matt Arsenault61001bb2015-11-25 19:58:34 +0000[diff] [blame]2344def : BitConvert <v4i32, v2f64, VReg_128>;
Matt Arsenaulte57206d2016-05-25 18:07:36 +0000[diff] [blame]2345def : BitConvert <v2i64, v2f64, VReg_128>;
2346def : BitConvert <v2f64, v2i64, VReg_128>;
Matt Arsenault61001bb2015-11-25 19:58:34 +0000[diff] [blame]2347
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]2348// 256-bit bitcast
Tom Stellard967bf582014-02-13 23:34:15 +0000[diff] [blame]2349def : BitConvert <v8i32, v8f32, SReg_256>;
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]2350def : BitConvert <v8f32, v8i32, SReg_256>;
Matt Arsenaultf5958dd2014-02-02 00:05:35 +0000[diff] [blame]2351def : BitConvert <v8i32, v8f32, VReg_256>;
2352def : BitConvert <v8f32, v8i32, VReg_256>;
Tom Stellard20ee94f2013-08-14 22:22:09 +0000[diff] [blame]2353
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]2354// 512-bit bitcast
Matt Arsenaultf5958dd2014-02-02 00:05:35 +0000[diff] [blame]2355def : BitConvert <v16i32, v16f32, VReg_512>;
2356def : BitConvert <v16f32, v16i32, VReg_512>;
2357
Christian Konig8dbe6f62013-02-21 15:17:27 +0000[diff] [blame]2358/********** =================== **********/
2359/********** Src & Dst modifiers **********/
2360/********** =================== **********/
2361
2362def : Pat <
Matt Arsenault1cffa4c2014-11-13 19:49:04 +0000[diff] [blame]2363 (AMDGPUclamp (VOP3Mods0Clamp f32:$src0, i32:$src0_modifiers, i32:$omod),
2364 (f32 FP_ZERO), (f32 FP_ONE)),
2365 (V_ADD_F32_e64 $src0_modifiers, $src0, 0, 0, 1, $omod)
Christian Konig8dbe6f62013-02-21 15:17:27 +0000[diff] [blame]2366>;
2367
Michel Danzer624b02a2014-02-04 07:12:38 +0000[diff] [blame]2368/********** ================================ **********/
2369/********** Floating point absolute/negative **********/
2370/********** ================================ **********/
2371
Matt Arsenaultfabf5452014-08-15 18:42:22 +0000[diff] [blame]2372// Prevent expanding both fneg and fabs.
Michel Danzer624b02a2014-02-04 07:12:38 +0000[diff] [blame]2373
Michel Danzer624b02a2014-02-04 07:12:38 +0000[diff] [blame]2374def : Pat <
2375 (fneg (fabs f32:$src)),
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]2376 (S_OR_B32 $src, 0x80000000) // Set sign bit
Michel Danzer624b02a2014-02-04 07:12:38 +0000[diff] [blame]2377>;
2378
Matt Arsenaultfabf5452014-08-15 18:42:22 +0000[diff] [blame]2379// FIXME: Should use S_OR_B32
Matt Arsenault13623d02014-08-15 18:42:18 +0000[diff] [blame]2380def : Pat <
2381 (fneg (fabs f64:$src)),
Matt Arsenault7d858d82014-11-02 23:46:54 +0000[diff] [blame]2382 (REG_SEQUENCE VReg_64,
2383 (i32 (EXTRACT_SUBREG f64:$src, sub0)),
2384 sub0,
Matt Arsenaultfabf5452014-08-15 18:42:22 +0000[diff] [blame]2385 (V_OR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
Matt Arsenault7d858d82014-11-02 23:46:54 +0000[diff] [blame]2386 (V_MOV_B32_e32 0x80000000)), // Set sign bit.
2387 sub1)
Matt Arsenault13623d02014-08-15 18:42:18 +0000[diff] [blame]2388>;
2389
Matt Arsenaultfabf5452014-08-15 18:42:22 +0000[diff] [blame]2390def : Pat <
2391 (fabs f32:$src),
2392 (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff))
2393>;
Vincent Lejeune79a58342014-05-10 19:18:25 +0000[diff] [blame]2394
Matt Arsenaultfabf5452014-08-15 18:42:22 +0000[diff] [blame]2395def : Pat <
2396 (fneg f32:$src),
2397 (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000))
2398>;
Christian Konig8dbe6f62013-02-21 15:17:27 +0000[diff] [blame]2399
Matt Arsenaultfabf5452014-08-15 18:42:22 +0000[diff] [blame]2400def : Pat <
2401 (fabs f64:$src),
Matt Arsenault7d858d82014-11-02 23:46:54 +0000[diff] [blame]2402 (REG_SEQUENCE VReg_64,
2403 (i32 (EXTRACT_SUBREG f64:$src, sub0)),
2404 sub0,
Matt Arsenaultfabf5452014-08-15 18:42:22 +0000[diff] [blame]2405 (V_AND_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
Matt Arsenault7d858d82014-11-02 23:46:54 +0000[diff] [blame]2406 (V_MOV_B32_e32 0x7fffffff)), // Set sign bit.
2407 sub1)
Matt Arsenaultfabf5452014-08-15 18:42:22 +0000[diff] [blame]2408>;
Vincent Lejeune79a58342014-05-10 19:18:25 +0000[diff] [blame]2409
Matt Arsenaultfabf5452014-08-15 18:42:22 +0000[diff] [blame]2410def : Pat <
2411 (fneg f64:$src),
Matt Arsenault7d858d82014-11-02 23:46:54 +0000[diff] [blame]2412 (REG_SEQUENCE VReg_64,
2413 (i32 (EXTRACT_SUBREG f64:$src, sub0)),
2414 sub0,
Matt Arsenaultfabf5452014-08-15 18:42:22 +0000[diff] [blame]2415 (V_XOR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
Matt Arsenault7d858d82014-11-02 23:46:54 +0000[diff] [blame]2416 (V_MOV_B32_e32 0x80000000)),
2417 sub1)
Matt Arsenaultfabf5452014-08-15 18:42:22 +0000[diff] [blame]2418>;
Christian Konig8dbe6f62013-02-21 15:17:27 +0000[diff] [blame]2419
Christian Konigc756cb992013-02-16 11:28:22 +0000[diff] [blame]2420/********** ================== **********/
2421/********** Immediate Patterns **********/
2422/********** ================== **********/
2423
2424def : Pat <
Tom Stellarddf94dc32013-08-14 23:24:24 +0000[diff] [blame]2425 (SGPRImm<(i32 imm)>:$imm),
2426 (S_MOV_B32 imm:$imm)
2427>;
2428
2429def : Pat <
2430 (SGPRImm<(f32 fpimm)>:$imm),
Tom Stellardfb77f002015-01-13 22:59:41 +0000[diff] [blame]2431 (S_MOV_B32 (f32 (bitcast_fpimm_to_i32 $imm)))
Tom Stellarddf94dc32013-08-14 23:24:24 +0000[diff] [blame]2432>;
2433
2434def : Pat <
Christian Konigc756cb992013-02-16 11:28:22 +0000[diff] [blame]2435 (i32 imm:$imm),
2436 (V_MOV_B32_e32 imm:$imm)
2437>;
2438
2439def : Pat <
2440 (f32 fpimm:$imm),
Tom Stellardfb77f002015-01-13 22:59:41 +0000[diff] [blame]2441 (V_MOV_B32_e32 (f32 (bitcast_fpimm_to_i32 $imm)))
Christian Konigc756cb992013-02-16 11:28:22 +0000[diff] [blame]2442>;
2443
2444def : Pat <
Christian Konigb559b072013-02-16 11:28:36 +0000[diff] [blame]2445 (i64 InlineImm<i64>:$imm),
2446 (S_MOV_B64 InlineImm<i64>:$imm)
2447>;
2448
Matt Arsenaultbecd6562014-12-03 05:22:35 +0000[diff] [blame]2449// XXX - Should this use a s_cmp to set SCC?
2450
2451// Set to sign-extended 64-bit value (true = -1, false = 0)
2452def : Pat <
2453 (i1 imm:$imm),
2454 (S_MOV_B64 (i64 (as_i64imm $imm)))
2455>;
2456
Matt Arsenault303011a2014-12-17 21:04:08 +0000[diff] [blame]2457def : Pat <
2458 (f64 InlineFPImm<f64>:$imm),
Tom Stellardfb77f002015-01-13 22:59:41 +0000[diff] [blame]2459 (S_MOV_B64 (f64 (bitcast_fpimm_to_i64 InlineFPImm<f64>:$imm)))
Matt Arsenault303011a2014-12-17 21:04:08 +0000[diff] [blame]2460>;
2461
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]2462/********** ================== **********/
2463/********** Intrinsic Patterns **********/
2464/********** ================== **********/
2465
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2466def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]2467
2468def : Pat <
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2469 (int_AMDGPU_cube v4f32:$src),
Matt Arsenault7d858d82014-11-02 23:46:54 +0000[diff] [blame]2470 (REG_SEQUENCE VReg_128,
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]2471 (V_CUBETC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
2472 0 /* src1_modifiers */, (EXTRACT_SUBREG $src, sub1),
2473 0 /* src2_modifiers */, (EXTRACT_SUBREG $src, sub2),
Matt Arsenault7d858d82014-11-02 23:46:54 +0000[diff] [blame]2474 0 /* clamp */, 0 /* omod */), sub0,
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]2475 (V_CUBESC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
2476 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2477 0 /* src2_modifiers */,(EXTRACT_SUBREG $src, sub2),
Matt Arsenault7d858d82014-11-02 23:46:54 +0000[diff] [blame]2478 0 /* clamp */, 0 /* omod */), sub1,
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]2479 (V_CUBEMA_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
2480 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2481 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
Matt Arsenault7d858d82014-11-02 23:46:54 +0000[diff] [blame]2482 0 /* clamp */, 0 /* omod */), sub2,
Tom Stellardb4a313a2014-08-01 00:32:39 +0000[diff] [blame]2483 (V_CUBEID_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
2484 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2485 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
Matt Arsenault7d858d82014-11-02 23:46:54 +0000[diff] [blame]2486 0 /* clamp */, 0 /* omod */), sub3)
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]2487>;
2488
Michel Danzer0cc991e2013-02-22 11:22:58 +0000[diff] [blame]2489def : Pat <
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000[diff] [blame]2490 (i32 (sext i1:$src0)),
2491 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
Michel Danzer0cc991e2013-02-22 11:22:58 +0000[diff] [blame]2492>;
2493
Tom Stellardf16d38c2014-02-13 23:34:13 +0000[diff] [blame]2494class Ext32Pat <SDNode ext> : Pat <
2495 (i32 (ext i1:$src0)),
Michel Danzer5d26fdf2014-02-05 09:48:05 +0000[diff] [blame]2496 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
2497>;
2498
Tom Stellardf16d38c2014-02-13 23:34:13 +0000[diff] [blame]2499def : Ext32Pat <zext>;
2500def : Ext32Pat <anyext>;
2501
Matt Arsenault382d9452016-01-26 04:49:22 +0000[diff] [blame]2502// Offset in an 32-bit VGPR
Christian Konig7a14a472013-03-18 11:34:00 +0000[diff] [blame]2503def : Pat <
Tom Stellard868fd922014-04-17 21:00:11 +0000[diff] [blame]2504 (SIload_constant v4i32:$sbase, i32:$voff),
Tom Stellardc229baa2015-03-10 16:16:49 +0000[diff] [blame]2505 (BUFFER_LOAD_DWORD_OFFEN $voff, $sbase, 0, 0, 0, 0, 0)
Christian Konig7a14a472013-03-18 11:34:00 +0000[diff] [blame]2506>;
2507
Michel Danzer8caa9042013-04-10 17:17:56 +0000[diff] [blame]2508// The multiplication scales from [0,1] to the unsigned integer range
2509def : Pat <
2510 (AMDGPUurecip i32:$src0),
2511 (V_CVT_U32_F32_e32
2512 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
2513 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
2514>;
2515
Tom Stellard0289ff42014-05-16 20:56:44 +0000[diff] [blame]2516//===----------------------------------------------------------------------===//
2517// VOP3 Patterns
2518//===----------------------------------------------------------------------===//
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]2519
Matt Arsenaulteb260202014-05-22 18:00:15 +0000[diff] [blame]2520def : IMad24Pat<V_MAD_I32_I24>;
2521def : UMad24Pat<V_MAD_U32_U24>;
2522
Matt Arsenault7d858d82014-11-02 23:46:54 +0000[diff] [blame]2523defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>;
Tom Stellard0289ff42014-05-16 20:56:44 +0000[diff] [blame]2524def : ROTRPattern <V_ALIGNBIT_B32>;
2525
Tom Stellard556d9aa2013-06-03 17:39:37 +0000[diff] [blame]2526//===----------------------------------------------------------------------===//
2527// MUBUF Patterns
2528//===----------------------------------------------------------------------===//
2529
Jan Vesely43b7b5b2016-04-07 19:23:11 +0000[diff] [blame]2530class MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
2531 PatFrag constant_ld> : Pat <
Tom Stellard1f9939f2015-02-27 14:59:41 +0000[diff] [blame]2532 (vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
2533 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))),
Tom Stellardc229baa2015-03-10 16:16:49 +0000[diff] [blame]2534 (Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, $glc, $slc, $tfe)
Tom Stellard07a10a32013-06-03 17:39:43 +0000[diff] [blame]2535 >;
Jan Vesely43b7b5b2016-04-07 19:23:11 +0000[diff] [blame]2536
2537multiclass MUBUFLoad_Atomic_Pattern <MUBUF Instr_ADDR64, MUBUF Instr_OFFSET,
2538 ValueType vt, PatFrag atomic_ld> {
2539 def : Pat <
2540 (vt (atomic_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
2541 i16:$offset, i1:$slc))),
2542 (Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, 1, $slc, 0)
2543 >;
2544
2545 def : Pat <
2546 (vt (atomic_ld (MUBUFOffsetNoGLC v4i32:$rsrc, i32:$soffset, i16:$offset))),
2547 (Instr_OFFSET $rsrc, $soffset, (as_i16imm $offset), 1, 0, 0)
2548 >;
Tom Stellard07a10a32013-06-03 17:39:43 +0000[diff] [blame]2549}
2550
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]2551let Predicates = [isSICI] in {
Jan Vesely43b7b5b2016-04-07 19:23:11 +0000[diff] [blame]2552def : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>;
2553def : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>;
2554def : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>;
2555def : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>;
2556
2557defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORD_ADDR64, BUFFER_LOAD_DWORD_OFFSET, i32, mubuf_load_atomic>;
2558defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, BUFFER_LOAD_DWORDX2_OFFSET, i64, mubuf_load_atomic>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]2559} // End Predicates = [isSICI]
Tom Stellardb02094e2014-07-21 15:45:01 +0000[diff] [blame]2560
2561class MUBUFScratchLoadPat <MUBUF Instr, ValueType vt, PatFrag ld> : Pat <
2562 (vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr,
2563 i32:$soffset, u16imm:$offset))),
Tom Stellardc229baa2015-03-10 16:16:49 +0000[diff] [blame]2564 (Instr $vaddr, $srsrc, $soffset, $offset, 0, 0, 0)
Tom Stellardb02094e2014-07-21 15:45:01 +0000[diff] [blame]2565>;
2566
2567def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i32, sextloadi8_private>;
2568def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i32, extloadi8_private>;
2569def : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, i32, sextloadi16_private>;
2570def : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, i32, extloadi16_private>;
2571def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORD_OFFEN, i32, load_private>;
2572def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, v2i32, load_private>;
2573def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, v4i32, load_private>;
Tom Stellard07a10a32013-06-03 17:39:43 +0000[diff] [blame]2574
Michel Danzer13736222014-01-27 07:20:51 +0000[diff] [blame]2575// BUFFER_LOAD_DWORD*, addr64=0
2576multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
2577 MUBUF bothen> {
2578
2579 def : Pat <
Tom Stellard8e44d942014-07-21 15:44:55 +0000[diff] [blame]2580 (vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset,
Michel Danzer13736222014-01-27 07:20:51 +0000[diff] [blame]2581 imm:$offset, 0, 0, imm:$glc, imm:$slc,
2582 imm:$tfe)),
Tom Stellard49282c92015-02-27 14:59:44 +0000[diff] [blame]2583 (offset $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc),
Michel Danzer13736222014-01-27 07:20:51 +0000[diff] [blame]2584 (as_i1imm $slc), (as_i1imm $tfe))
2585 >;
2586
2587 def : Pat <
Tom Stellard868fd922014-04-17 21:00:11 +0000[diff] [blame]2588 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
Tom Stellardb02094e2014-07-21 15:45:01 +0000[diff] [blame]2589 imm:$offset, 1, 0, imm:$glc, imm:$slc,
Michel Danzer13736222014-01-27 07:20:51 +0000[diff] [blame]2590 imm:$tfe)),
Tom Stellardc229baa2015-03-10 16:16:49 +0000[diff] [blame]2591 (offen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
Michel Danzer13736222014-01-27 07:20:51 +0000[diff] [blame]2592 (as_i1imm $tfe))
2593 >;
2594
2595 def : Pat <
Tom Stellard868fd922014-04-17 21:00:11 +0000[diff] [blame]2596 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
Michel Danzer13736222014-01-27 07:20:51 +0000[diff] [blame]2597 imm:$offset, 0, 1, imm:$glc, imm:$slc,
2598 imm:$tfe)),
Tom Stellardc229baa2015-03-10 16:16:49 +0000[diff] [blame]2599 (idxen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc),
Michel Danzer13736222014-01-27 07:20:51 +0000[diff] [blame]2600 (as_i1imm $slc), (as_i1imm $tfe))
2601 >;
2602
2603 def : Pat <
Tom Stellard868fd922014-04-17 21:00:11 +0000[diff] [blame]2604 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset,
Matt Arsenaultcaa12882015-02-18 02:04:38 +0000[diff] [blame]2605 imm:$offset, 1, 1, imm:$glc, imm:$slc,
Michel Danzer13736222014-01-27 07:20:51 +0000[diff] [blame]2606 imm:$tfe)),
Tom Stellardc229baa2015-03-10 16:16:49 +0000[diff] [blame]2607 (bothen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
Michel Danzer13736222014-01-27 07:20:51 +0000[diff] [blame]2608 (as_i1imm $tfe))
2609 >;
2610}
2611
2612defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
2613 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
2614defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
2615 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
2616defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
2617 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
2618
Jan Vesely43b7b5b2016-04-07 19:23:11 +0000[diff] [blame]2619multiclass MUBUFStore_Atomic_Pattern <MUBUF Instr_ADDR64, MUBUF Instr_OFFSET,
2620 ValueType vt, PatFrag atomic_st> {
2621 // Store follows atomic op convention so address is forst
2622 def : Pat <
2623 (atomic_st (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
2624 i16:$offset, i1:$slc), vt:$val),
2625 (Instr_ADDR64 $val, $vaddr, $srsrc, $soffset, $offset, 1, $slc, 0)
2626 >;
2627
2628 def : Pat <
2629 (atomic_st (MUBUFOffsetNoGLC v4i32:$rsrc, i32:$soffset, i16:$offset), vt:$val),
2630 (Instr_OFFSET $val, $rsrc, $soffset, (as_i16imm $offset), 1, 0, 0)
2631 >;
2632}
2633let Predicates = [isSICI] in {
2634defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORD_ADDR64, BUFFER_STORE_DWORD_OFFSET, i32, global_store_atomic>;
2635defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORDX2_ADDR64, BUFFER_STORE_DWORDX2_OFFSET, i64, global_store_atomic>;
2636} // End Predicates = [isSICI]
2637
Tom Stellardb02094e2014-07-21 15:45:01 +0000[diff] [blame]2638class MUBUFScratchStorePat <MUBUF Instr, ValueType vt, PatFrag st> : Pat <
Tom Stellardddea4862014-08-11 22:18:14 +0000[diff] [blame]2639 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset,
2640 u16imm:$offset)),
Tom Stellardc229baa2015-03-10 16:16:49 +0000[diff] [blame]2641 (Instr $value, $vaddr, $srsrc, $soffset, $offset, 0, 0, 0)
Tom Stellardb02094e2014-07-21 15:45:01 +0000[diff] [blame]2642>;
2643
Tom Stellardddea4862014-08-11 22:18:14 +0000[diff] [blame]2644def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i32, truncstorei8_private>;
2645def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i32, truncstorei16_private>;
2646def : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, i32, store_private>;
2647def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, v2i32, store_private>;
2648def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, v4i32, store_private>;
Tom Stellardb02094e2014-07-21 15:45:01 +0000[diff] [blame]2649
Tom Stellardafcf12f2013-09-12 02:55:14 +0000[diff] [blame]2650//===----------------------------------------------------------------------===//
2651// MTBUF Patterns
2652//===----------------------------------------------------------------------===//
2653
2654// TBUFFER_STORE_FORMAT_*, addr64=0
2655class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
Tom Stellard868fd922014-04-17 21:00:11 +0000[diff] [blame]2656 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
Tom Stellardafcf12f2013-09-12 02:55:14 +0000[diff] [blame]2657 i32:$soffset, imm:$inst_offset, imm:$dfmt,
2658 imm:$nfmt, imm:$offen, imm:$idxen,
2659 imm:$glc, imm:$slc, imm:$tfe),
2660 (opcode
2661 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
2662 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
2663 (as_i1imm $slc), (as_i1imm $tfe), $soffset)
2664>;
2665
2666def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
2667def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
2668def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
2669def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
2670
Christian Konig2989ffc2013-03-18 11:34:16 +0000[diff] [blame]2671/********** ====================== **********/
2672/********** Indirect adressing **********/
2673/********** ====================== **********/
2674
Matt Arsenault28419272015-10-07 00:42:51 +0000[diff] [blame]2675multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, string VecSize> {
Matt Arsenault1322b6f2016-07-09 01:13:56 +0000[diff] [blame]2676 // Extract with offset
Christian Konig2989ffc2013-03-18 11:34:16 +0000[diff] [blame]2677 def : Pat<
Nicolai Haehnle7968c342016-07-12 08:12:16 +0000[diff] [blame]2678 (eltvt (extractelt vt:$src, (MOVRELOffset i32:$idx, (i32 imm:$offset)))),
Matt Arsenault1322b6f2016-07-09 01:13:56 +0000[diff] [blame]2679 (!cast<Instruction>("SI_INDIRECT_SRC_"#VecSize) $src, $idx, imm:$offset)
Christian Konig2989ffc2013-03-18 11:34:16 +0000[diff] [blame]2680 >;
2681
Matt Arsenault1322b6f2016-07-09 01:13:56 +0000[diff] [blame]2682 // Insert with offset
Christian Konig2989ffc2013-03-18 11:34:16 +0000[diff] [blame]2683 def : Pat<
Nicolai Haehnle7968c342016-07-12 08:12:16 +0000[diff] [blame]2684 (insertelt vt:$src, eltvt:$val, (MOVRELOffset i32:$idx, (i32 imm:$offset))),
Matt Arsenault1322b6f2016-07-09 01:13:56 +0000[diff] [blame]2685 (!cast<Instruction>("SI_INDIRECT_DST_"#VecSize) $src, $idx, imm:$offset, $val)
Christian Konig2989ffc2013-03-18 11:34:16 +0000[diff] [blame]2686 >;
2687}
2688
Matt Arsenault28419272015-10-07 00:42:51 +0000[diff] [blame]2689defm : SI_INDIRECT_Pattern <v2f32, f32, "V2">;
2690defm : SI_INDIRECT_Pattern <v4f32, f32, "V4">;
2691defm : SI_INDIRECT_Pattern <v8f32, f32, "V8">;
2692defm : SI_INDIRECT_Pattern <v16f32, f32, "V16">;
Matt Arsenaultf5958dd2014-02-02 00:05:35 +0000[diff] [blame]2693
Matt Arsenault28419272015-10-07 00:42:51 +0000[diff] [blame]2694defm : SI_INDIRECT_Pattern <v2i32, i32, "V2">;
2695defm : SI_INDIRECT_Pattern <v4i32, i32, "V4">;
2696defm : SI_INDIRECT_Pattern <v8i32, i32, "V8">;
2697defm : SI_INDIRECT_Pattern <v16i32, i32, "V16">;
Christian Konig2989ffc2013-03-18 11:34:16 +0000[diff] [blame]2698
Tom Stellard81d871d2013-11-13 23:36:50 +0000[diff] [blame]2699//===----------------------------------------------------------------------===//
Wei Ding1041a642016-08-24 14:59:47 +0000[diff] [blame]2700// SAD Patterns
2701//===----------------------------------------------------------------------===//
2702
2703def : Pat <
2704 (add (sub_oneuse (umax i32:$src0, i32:$src1),
2705 (umin i32:$src0, i32:$src1)),
2706 i32:$src2),
2707 (V_SAD_U32 $src0, $src1, $src2)
2708>;
2709
2710def : Pat <
2711 (add (select_oneuse (i1 (setugt i32:$src0, i32:$src1)),
2712 (sub i32:$src0, i32:$src1),
2713 (sub i32:$src1, i32:$src0)),
2714 i32:$src2),
2715 (V_SAD_U32 $src0, $src1, $src2)
2716>;
2717
2718//===----------------------------------------------------------------------===//
Matt Arsenault5dbd5db2014-04-22 03:49:30 +0000[diff] [blame]2719// Conversion Patterns
2720//===----------------------------------------------------------------------===//
2721
2722def : Pat<(i32 (sext_inreg i32:$src, i1)),
2723 (S_BFE_I32 i32:$src, 65536)>; // 0 | 1 << 16
2724
Matt Arsenault5dbd5db2014-04-22 03:49:30 +0000[diff] [blame]2725// Handle sext_inreg in i64
2726def : Pat <
2727 (i64 (sext_inreg i64:$src, i1)),
Matt Arsenault94812212014-11-14 18:18:16 +0000[diff] [blame]2728 (S_BFE_I64 i64:$src, 0x10000) // 0 | 1 << 16
Matt Arsenault5dbd5db2014-04-22 03:49:30 +0000[diff] [blame]2729>;
2730
2731def : Pat <
2732 (i64 (sext_inreg i64:$src, i8)),
Matt Arsenault94812212014-11-14 18:18:16 +0000[diff] [blame]2733 (S_BFE_I64 i64:$src, 0x80000) // 0 | 8 << 16
Matt Arsenault5dbd5db2014-04-22 03:49:30 +0000[diff] [blame]2734>;
2735
2736def : Pat <
2737 (i64 (sext_inreg i64:$src, i16)),
Matt Arsenault94812212014-11-14 18:18:16 +0000[diff] [blame]2738 (S_BFE_I64 i64:$src, 0x100000) // 0 | 16 << 16
2739>;
2740
2741def : Pat <
2742 (i64 (sext_inreg i64:$src, i32)),
2743 (S_BFE_I64 i64:$src, 0x200000) // 0 | 32 << 16
Matt Arsenault5dbd5db2014-04-22 03:49:30 +0000[diff] [blame]2744>;
2745
Matt Arsenaultc6b69a92016-07-26 23:06:33 +0000[diff] [blame]2746def : Pat <
2747 (i64 (zext i32:$src)),
Matt Arsenault7d858d82014-11-02 23:46:54 +0000[diff] [blame]2748 (REG_SEQUENCE SReg_64, $src, sub0, (S_MOV_B32 0), sub1)
Matt Arsenaultb2cbf792014-06-10 18:54:59 +0000[diff] [blame]2749>;
2750
Matt Arsenaultc6b69a92016-07-26 23:06:33 +0000[diff] [blame]2751def : Pat <
2752 (i64 (anyext i32:$src)),
2753 (REG_SEQUENCE SReg_64, $src, sub0, (i32 (IMPLICIT_DEF)), sub1)
2754>;
2755
Matt Arsenaultb2cbf792014-06-10 18:54:59 +0000[diff] [blame]2756class ZExt_i64_i1_Pat <SDNode ext> : Pat <
2757 (i64 (ext i1:$src)),
Matt Arsenault7d858d82014-11-02 23:46:54 +0000[diff] [blame]2758 (REG_SEQUENCE VReg_64,
2759 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0,
2760 (S_MOV_B32 0), sub1)
Matt Arsenaultb2cbf792014-06-10 18:54:59 +0000[diff] [blame]2761>;
2762
2763
Matt Arsenaultb2cbf792014-06-10 18:54:59 +0000[diff] [blame]2764def : ZExt_i64_i1_Pat<zext>;
2765def : ZExt_i64_i1_Pat<anyext>;
2766
Tom Stellardbc4497b2016-02-12 23:45:29 +0000[diff] [blame]2767// FIXME: We need to use COPY_TO_REGCLASS to work-around the fact that
2768// REG_SEQUENCE patterns don't support instructions with multiple outputs.
Matt Arsenaultb2cbf792014-06-10 18:54:59 +0000[diff] [blame]2769def : Pat <
2770 (i64 (sext i32:$src)),
Matt Arsenault7d858d82014-11-02 23:46:54 +0000[diff] [blame]2771 (REG_SEQUENCE SReg_64, $src, sub0,
Artem Tamazov38e496b2016-04-29 17:04:50 +0000[diff] [blame]2772 (i32 (COPY_TO_REGCLASS (S_ASHR_I32 $src, 31), SReg_32_XM0)), sub1)
Matt Arsenaultb2cbf792014-06-10 18:54:59 +0000[diff] [blame]2773>;
2774
2775def : Pat <
2776 (i64 (sext i1:$src)),
Matt Arsenault7d858d82014-11-02 23:46:54 +0000[diff] [blame]2777 (REG_SEQUENCE VReg_64,
2778 (V_CNDMASK_B32_e64 0, -1, $src), sub0,
Matt Arsenaultb2cbf792014-06-10 18:54:59 +0000[diff] [blame]2779 (V_CNDMASK_B32_e64 0, -1, $src), sub1)
2780>;
2781
Matt Arsenault7fb961f2016-07-22 17:01:21 +0000[diff] [blame]2782class FPToI1Pat<Instruction Inst, int KOne, ValueType vt, SDPatternOperator fp_to_int> : Pat <
2783 (i1 (fp_to_int (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)))),
2784 (i1 (Inst 0, KOne, $src0_modifiers, $src0, DSTCLAMP.NONE, DSTOMOD.NONE))
2785>;
2786
2787def : FPToI1Pat<V_CMP_EQ_F32_e64, CONST.FP32_ONE, f32, fp_to_uint>;
2788def : FPToI1Pat<V_CMP_EQ_F32_e64, CONST.FP32_NEG_ONE, f32, fp_to_sint>;
2789def : FPToI1Pat<V_CMP_EQ_F64_e64, CONST.FP64_ONE, f64, fp_to_uint>;
2790def : FPToI1Pat<V_CMP_EQ_F64_e64, CONST.FP64_NEG_ONE, f64, fp_to_sint>;
2791
Matt Arsenaultbecd6562014-12-03 05:22:35 +0000[diff] [blame]2792// If we need to perform a logical operation on i1 values, we need to
2793// use vector comparisons since there is only one SCC register. Vector
2794// comparisions still write to a pair of SGPRs, so treat these as
2795// 64-bit comparisons. When legalizing SGPR copies, instructions
2796// resulting in the copies from SCC to these instructions will be
2797// moved to the VALU.
2798def : Pat <
2799 (i1 (and i1:$src0, i1:$src1)),
2800 (S_AND_B64 $src0, $src1)
2801>;
2802
2803def : Pat <
2804 (i1 (or i1:$src0, i1:$src1)),
2805 (S_OR_B64 $src0, $src1)
2806>;
2807
2808def : Pat <
2809 (i1 (xor i1:$src0, i1:$src1)),
2810 (S_XOR_B64 $src0, $src1)
2811>;
2812
Matt Arsenaultaeca2fa2014-05-31 06:47:42 +0000[diff] [blame]2813def : Pat <
2814 (f32 (sint_to_fp i1:$src)),
2815 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src)
2816>;
2817
2818def : Pat <
2819 (f32 (uint_to_fp i1:$src)),
2820 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src)
2821>;
2822
2823def : Pat <
2824 (f64 (sint_to_fp i1:$src)),
Matt Arsenaultbecd6562014-12-03 05:22:35 +0000[diff] [blame]2825 (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src))
Matt Arsenaultaeca2fa2014-05-31 06:47:42 +0000[diff] [blame]2826>;
2827
2828def : Pat <
2829 (f64 (uint_to_fp i1:$src)),
2830 (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src))
2831>;
2832
Matt Arsenault5dbd5db2014-04-22 03:49:30 +0000[diff] [blame]2833//===----------------------------------------------------------------------===//
Tom Stellardfb961692013-10-23 00:44:19 +0000[diff] [blame]2834// Miscellaneous Patterns
2835//===----------------------------------------------------------------------===//
2836
2837def : Pat <
Tom Stellard81d871d2013-11-13 23:36:50 +0000[diff] [blame]2838 (i32 (trunc i64:$a)),
2839 (EXTRACT_SUBREG $a, sub0)
2840>;
2841
Michel Danzerbf1a6412014-01-28 03:01:16 +0000[diff] [blame]2842def : Pat <
2843 (i1 (trunc i32:$a)),
Marek Olsakf924dd62015-10-29 15:05:03 +0000[diff] [blame]2844 (V_CMP_EQ_I32_e64 (S_AND_B32 (i32 1), $a), 1)
Michel Danzerbf1a6412014-01-28 03:01:16 +0000[diff] [blame]2845>;
2846
Matt Arsenaulte306a322014-10-21 16:25:08 +0000[diff] [blame]2847def : Pat <
Matt Arsenaultabd271b2015-02-05 06:05:13 +0000[diff] [blame]2848 (i1 (trunc i64:$a)),
Marek Olsakf924dd62015-10-29 15:05:03 +0000[diff] [blame]2849 (V_CMP_EQ_I32_e64 (S_AND_B32 (i32 1),
Matt Arsenaultabd271b2015-02-05 06:05:13 +0000[diff] [blame]2850 (EXTRACT_SUBREG $a, sub0)), 1)
2851>;
2852
2853def : Pat <
Matt Arsenaulte306a322014-10-21 16:25:08 +0000[diff] [blame]2854 (i32 (bswap i32:$a)),
2855 (V_BFI_B32 (S_MOV_B32 0x00ff00ff),
2856 (V_ALIGNBIT_B32 $a, $a, 24),
2857 (V_ALIGNBIT_B32 $a, $a, 8))
2858>;
2859
Matt Arsenault477b17822014-12-12 02:30:29 +0000[diff] [blame]2860def : Pat <
2861 (f32 (select i1:$src2, f32:$src1, f32:$src0)),
2862 (V_CNDMASK_B32_e64 $src0, $src1, $src2)
2863>;
2864
Marek Olsak63a7b082015-03-24 13:40:21 +0000[diff] [blame]2865multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> {
2866 def : Pat <
2867 (vt (shl (vt (add (vt (shl 1, vt:$a)), -1)), vt:$b)),
2868 (BFM $a, $b)
2869 >;
2870
2871 def : Pat <
2872 (vt (add (vt (shl 1, vt:$a)), -1)),
2873 (BFM $a, (MOV 0))
2874 >;
2875}
2876
2877defm : BFMPatterns <i32, S_BFM_B32, S_MOV_B32>;
2878// FIXME: defm : BFMPatterns <i64, S_BFM_B64, S_MOV_B64>;
2879
Marek Olsak949f5da2015-03-24 13:40:34 +0000[diff] [blame]2880def : BFEPattern <V_BFE_U32, S_MOV_B32>;
2881
Matt Arsenault9cd90712016-04-14 01:42:16 +0000[diff] [blame]2882def : Pat<
2883 (fcanonicalize f32:$src),
2884 (V_MUL_F32_e64 0, CONST.FP32_ONE, 0, $src, 0, 0)
2885>;
2886
2887def : Pat<
2888 (fcanonicalize f64:$src),
2889 (V_MUL_F64 0, CONST.FP64_ONE, 0, $src, 0, 0)
2890>;
2891
Marek Olsak43650e42015-03-24 13:40:08 +0000[diff] [blame]2892//===----------------------------------------------------------------------===//
2893// Fract Patterns
2894//===----------------------------------------------------------------------===//
2895
Marek Olsak7d777282015-03-24 13:40:15 +0000[diff] [blame]2896let Predicates = [isSI] in {
2897
2898// V_FRACT is buggy on SI, so the F32 version is never used and (x-floor(x)) is
2899// used instead. However, SI doesn't have V_FLOOR_F64, so the most efficient
2900// way to implement it is using V_FRACT_F64.
2901// The workaround for the V_FRACT bug is:
2902// fract(x) = isnan(x) ? x : min(V_FRACT(x), 0.99999999999999999)
2903
Marek Olsak7d777282015-03-24 13:40:15 +0000[diff] [blame]2904// Convert floor(x) to (x - fract(x))
2905def : Pat <
2906 (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))),
2907 (V_ADD_F64
2908 $mods,
2909 $x,
2910 SRCMODS.NEG,
2911 (V_CNDMASK_B64_PSEUDO
Marek Olsak7d777282015-03-24 13:40:15 +0000[diff] [blame]2912 (V_MIN_F64
2913 SRCMODS.NONE,
2914 (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE),
2915 SRCMODS.NONE,
2916 (V_MOV_B64_PSEUDO 0x3fefffffffffffff),
2917 DSTCLAMP.NONE, DSTOMOD.NONE),
Marek Olsak1354b872015-07-27 11:37:42 +0000[diff] [blame]2918 $x,
Marek Olsak7d777282015-03-24 13:40:15 +0000[diff] [blame]2919 (V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, 3/*NaN*/)),
2920 DSTCLAMP.NONE, DSTOMOD.NONE)
2921>;
2922
2923} // End Predicates = [isSI]
2924
Tom Stellardfb961692013-10-23 00:44:19 +0000[diff] [blame]2925//============================================================================//
Tom Stellardeac65dd2013-05-03 17:21:20 +0000[diff] [blame]2926// Miscellaneous Optimization Patterns
2927//============================================================================//
2928
Matt Arsenault49dd4282014-09-15 17:15:02 +0000[diff] [blame]2929def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64>;
Tom Stellardeac65dd2013-05-03 17:21:20 +0000[diff] [blame]2930
Matt Arsenaultc89f2912016-03-07 21:54:48 +0000[diff] [blame]2931def : IntMed3Pat<V_MED3_I32, smax, smax_oneuse, smin_oneuse>;
2932def : IntMed3Pat<V_MED3_U32, umax, umax_oneuse, umin_oneuse>;
2933
Tom Stellard245c15f2015-05-26 15:55:52 +0000[diff] [blame]2934//============================================================================//
2935// Assembler aliases
2936//============================================================================//
2937
2938def : MnemonicAlias<"v_add_u32", "v_add_i32">;
2939def : MnemonicAlias<"v_sub_u32", "v_sub_i32">;
2940def : MnemonicAlias<"v_subrev_u32", "v_subrev_i32">;
2941
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]2942} // End isGCN predicate