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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04004 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020042#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050043#include <linux/device.h>
Tejun Heoedc93052007-10-25 14:59:16 +090044#include <linux/dmi.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090045#include <linux/gfp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050047#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048#include <linux/libata.h>
Anton Vorontsov365cfa12010-03-28 00:22:14 -040049#include "ahci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070050
51#define DRV_NAME "ahci"
Tejun Heo7d50b602007-09-23 13:19:54 +090052#define DRV_VERSION "3.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
Linus Torvalds1da177e2005-04-16 15:20:36 -070054enum {
Alessandro Rubini318893e2012-01-06 13:33:39 +010055 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_STANDARD = 5,
Tejun Heo441577e2010-03-29 10:32:39 +090057};
Linus Torvalds1da177e2005-04-16 15:20:36 -070058
Tejun Heo441577e2010-03-29 10:32:39 +090059enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
63 board_ahci_nosntf,
Tejun Heo5f173102010-07-24 16:53:48 +020064 board_ahci_yes_fbs,
Tejun Heo441577e2010-03-29 10:32:39 +090065
66 /* board IDs for specific chipsets in alphabetical order */
67 board_ahci_mcp65,
Tejun Heo83f2b962010-03-30 10:28:32 +090068 board_ahci_mcp77,
69 board_ahci_mcp89,
Tejun Heo441577e2010-03-29 10:32:39 +090070 board_ahci_mv,
71 board_ahci_sb600,
72 board_ahci_sb700, /* for SB700 and SB800 */
73 board_ahci_vt8251,
74
75 /* aliases */
76 board_ahci_mcp_linux = board_ahci_mcp65,
77 board_ahci_mcp67 = board_ahci_mcp65,
78 board_ahci_mcp73 = board_ahci_mcp65,
Tejun Heo83f2b962010-03-30 10:28:32 +090079 board_ahci_mcp79 = board_ahci_mcp77,
Linus Torvalds1da177e2005-04-16 15:20:36 -070080};
81
Jeff Garzik2dcb4072007-10-19 06:42:56 -040082static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heoa1efdab2008-03-25 12:22:50 +090083static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
Tejun Heo438ac6d2007-03-02 17:31:26 +090087#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +090088static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
89static int ahci_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +090090#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070091
Tejun Heofad16e72010-09-21 09:25:48 +020092static struct scsi_host_template ahci_sht = {
93 AHCI_SHT("ahci"),
94};
95
Tejun Heo029cfd62008-03-25 12:22:49 +090096static struct ata_port_operations ahci_vt8251_ops = {
97 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +090098 .hardreset = ahci_vt8251_hardreset,
Tejun Heoad616ff2006-11-01 18:00:24 +090099};
100
Tejun Heo029cfd62008-03-25 12:22:49 +0900101static struct ata_port_operations ahci_p5wdh_ops = {
102 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900103 .hardreset = ahci_p5wdh_hardreset,
Tejun Heoedc93052007-10-25 14:59:16 +0900104};
105
Tejun Heo417a1a62007-09-23 13:19:55 +0900106#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
107
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100108static const struct ata_port_info ahci_port_info[] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900109 /* by features */
Jeff Garzik4da646b2009-04-08 02:00:13 -0400110 [board_ahci] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900112 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100113 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400114 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115 .port_ops = &ahci_ops,
116 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400117 [board_ahci_ign_iferr] =
Tejun Heo41669552006-11-29 11:33:14 +0900118 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900119 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
120 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100121 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400122 .udma_mask = ATA_UDMA6,
Tejun Heo41669552006-11-29 11:33:14 +0900123 .port_ops = &ahci_ops,
124 },
Tejun Heo441577e2010-03-29 10:32:39 +0900125 [board_ahci_nosntf] =
126 {
127 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
128 .flags = AHCI_FLAG_COMMON,
129 .pio_mask = ATA_PIO4,
130 .udma_mask = ATA_UDMA6,
131 .port_ops = &ahci_ops,
132 },
Tejun Heo5f173102010-07-24 16:53:48 +0200133 [board_ahci_yes_fbs] =
134 {
135 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
136 .flags = AHCI_FLAG_COMMON,
137 .pio_mask = ATA_PIO4,
138 .udma_mask = ATA_UDMA6,
139 .port_ops = &ahci_ops,
140 },
Tejun Heo441577e2010-03-29 10:32:39 +0900141 /* by chipsets */
142 [board_ahci_mcp65] =
143 {
Tejun Heo83f2b962010-03-30 10:28:32 +0900144 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
145 AHCI_HFLAG_YES_NCQ),
Tejun Heoae01b242011-03-16 11:14:55 +0100146 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
Tejun Heo83f2b962010-03-30 10:28:32 +0900147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
150 },
151 [board_ahci_mcp77] =
152 {
153 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
154 .flags = AHCI_FLAG_COMMON,
155 .pio_mask = ATA_PIO4,
156 .udma_mask = ATA_UDMA6,
157 .port_ops = &ahci_ops,
158 },
159 [board_ahci_mcp89] =
160 {
161 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
Tejun Heo441577e2010-03-29 10:32:39 +0900162 .flags = AHCI_FLAG_COMMON,
163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
166 },
167 [board_ahci_mv] =
168 {
169 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
170 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300171 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
Tejun Heo441577e2010-03-29 10:32:39 +0900172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
175 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400176 [board_ahci_sb600] =
Conke Hu55a61602007-03-27 18:33:05 +0800177 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900178 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900179 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
180 AHCI_HFLAG_32BIT_ONLY),
Tejun Heo417a1a62007-09-23 13:19:55 +0900181 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100182 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400183 .udma_mask = ATA_UDMA6,
Yuan-Hsin Chen345347c2011-06-21 17:17:38 +0800184 .port_ops = &ahci_pmp_retry_srst_ops,
Conke Hu55a61602007-03-27 18:33:05 +0800185 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400186 [board_ahci_sb700] = /* for SB700 and SB800 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800187 {
Shane Huangbd172432008-06-10 15:52:04 +0800188 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
Shane Huange39fc8c2008-02-22 05:00:31 -0800189 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100190 .pio_mask = ATA_PIO4,
Shane Huange39fc8c2008-02-22 05:00:31 -0800191 .udma_mask = ATA_UDMA6,
Yuan-Hsin Chen345347c2011-06-21 17:17:38 +0800192 .port_ops = &ahci_pmp_retry_srst_ops,
Shane Huange39fc8c2008-02-22 05:00:31 -0800193 },
Tejun Heo441577e2010-03-29 10:32:39 +0900194 [board_ahci_vt8251] =
Tejun Heoe297d992008-06-10 00:13:04 +0900195 {
Tejun Heo441577e2010-03-29 10:32:39 +0900196 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
Tejun Heoe297d992008-06-10 00:13:04 +0900197 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100198 .pio_mask = ATA_PIO4,
Tejun Heoe297d992008-06-10 00:13:04 +0900199 .udma_mask = ATA_UDMA6,
Tejun Heo441577e2010-03-29 10:32:39 +0900200 .port_ops = &ahci_vt8251_ops,
Shaohua Li1b677af2009-11-16 09:56:05 +0800201 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202};
203
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500204static const struct pci_device_id ahci_pci_tbl[] = {
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400205 /* Intel */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400206 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
207 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
208 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
209 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
210 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
Tejun Heo82490c02007-01-23 15:13:39 +0900211 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400212 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
213 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
214 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
215 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
Tejun Heo7a234af2007-09-03 12:44:57 +0900216 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
Shaohua Li1b677af2009-11-16 09:56:05 +0800217 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
Tejun Heo7a234af2007-09-03 12:44:57 +0900218 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
219 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
220 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
221 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
225 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
226 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
230 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
232 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
Jason Gastond4155e62007-09-20 17:35:00 -0400233 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
234 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800235 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
Mark Goodwinb2dde6a2009-06-26 10:44:11 -0500236 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800237 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
David Milburnc1f57d92009-07-22 15:15:56 -0500238 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
239 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700240 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700241 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500242 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700243 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700244 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500245 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
Seth Heasley5623cab2010-01-12 17:00:18 -0800246 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
247 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
248 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
251 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
Seth Heasley992b3fb2010-09-09 09:44:56 -0700252 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
253 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
254 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
Seth Heasley64a39032011-03-11 11:57:42 -0800255 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
Seth Heasleya4a461a2011-01-10 12:57:17 -0800256 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
Seth Heasley181e3ce2011-04-20 08:45:20 -0700257 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
258 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
259 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
262 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
Seth Heasley2cab7a42011-07-14 16:50:49 -0700263 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400264
Tejun Heoe34bb372007-02-26 20:24:03 +0900265 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
266 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
267 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400268
269 /* ATI */
Conke Huc65ec1c2007-04-11 18:23:14 +0800270 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800271 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
272 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
273 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
274 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
275 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
276 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400277
Shane Huange2dd90b2009-07-29 11:34:49 +0800278 /* AMD */
Shane Huang5deab532009-10-13 11:14:00 +0800279 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
Shane Huange2dd90b2009-07-29 11:34:49 +0800280 /* AMD is using RAID class only for ahci controllers */
281 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
282 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
283
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400284 /* VIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400285 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
Tejun Heobf335542007-04-11 17:27:14 +0900286 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400287
288 /* NVIDIA */
Tejun Heoe297d992008-06-10 00:13:04 +0900289 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
290 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
291 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
292 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
293 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
294 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
295 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
Tejun Heo441577e2010-03-29 10:32:39 +0900297 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400373
Jeff Garzik95916ed2006-07-29 04:10:14 -0400374 /* SiS */
Tejun Heo20e2de42008-08-01 12:51:43 +0900375 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
376 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
377 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
Jeff Garzik95916ed2006-07-29 04:10:14 -0400378
Alessandro Rubini318893e2012-01-06 13:33:39 +0100379 /* ST Microelectronics */
380 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
381
Jeff Garzikcd70c262007-07-08 02:29:42 -0400382 /* Marvell */
383 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100384 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
Tejun Heo5f173102010-07-24 16:53:48 +0200385 { PCI_DEVICE(0x1b4b, 0x9123),
Anssi Hannula10aca062011-01-18 20:03:26 -0500386 .class = PCI_CLASS_STORAGE_SATA_AHCI,
387 .class_mask = 0xffffff,
Tejun Heo5f173102010-07-24 16:53:48 +0200388 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
Per Jessen467b41c2011-02-08 13:54:32 +0100389 { PCI_DEVICE(0x1b4b, 0x9125),
390 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
Tejun Heo50be5e32010-11-29 15:57:14 +0100391 { PCI_DEVICE(0x1b4b, 0x91a3),
392 .driver_data = board_ahci_yes_fbs },
Jeff Garzikcd70c262007-07-08 02:29:42 -0400393
Mark Nelsonc77a0362008-10-23 14:08:16 +1100394 /* Promise */
395 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
396
Keng-Yu Linc9703762011-11-09 01:47:36 -0500397 /* Asmedia */
398 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1061 */
399
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500400 /* Generic, PCI class code for AHCI */
401 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Conke Huc9f89472007-01-09 05:32:51 -0500402 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500403
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404 { } /* terminate list */
405};
406
407
408static struct pci_driver ahci_pci_driver = {
409 .name = DRV_NAME,
410 .id_table = ahci_pci_tbl,
411 .probe = ahci_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900412 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900413#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900414 .suspend = ahci_pci_device_suspend,
415 .resume = ahci_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900416#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417};
418
Alan Cox5b66c822008-09-03 14:48:34 +0100419#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
420static int marvell_enable;
421#else
422static int marvell_enable = 1;
423#endif
424module_param(marvell_enable, int, 0644);
425MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
426
427
Anton Vorontsov394d6e52010-03-03 20:17:36 +0300428static void ahci_pci_save_initial_config(struct pci_dev *pdev,
429 struct ahci_host_priv *hpriv)
430{
431 unsigned int force_port_map = 0;
432 unsigned int mask_port_map = 0;
433
434 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
435 dev_info(&pdev->dev, "JMB361 has only one port\n");
436 force_port_map = 1;
437 }
438
439 /*
440 * Temporary Marvell 6145 hack: PATA port presence
441 * is asserted through the standard AHCI port
442 * presence register, as bit 4 (counting from 0)
443 */
444 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
445 if (pdev->device == 0x6121)
446 mask_port_map = 0x3;
447 else
448 mask_port_map = 0xf;
449 dev_info(&pdev->dev,
450 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
451 }
452
Anton Vorontsov1d513352010-03-03 20:17:37 +0300453 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
454 mask_port_map);
Anton Vorontsov394d6e52010-03-03 20:17:36 +0300455}
456
Anton Vorontsov33030402010-03-03 20:17:39 +0300457static int ahci_pci_reset_controller(struct ata_host *host)
458{
459 struct pci_dev *pdev = to_pci_dev(host->dev);
460
461 ahci_reset_controller(host);
462
Tejun Heod91542c2006-07-26 15:59:26 +0900463 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
Anton Vorontsov33030402010-03-03 20:17:39 +0300464 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heod91542c2006-07-26 15:59:26 +0900465 u16 tmp16;
466
467 /* configure PCS */
468 pci_read_config_word(pdev, 0x92, &tmp16);
Tejun Heo49f29092007-11-19 16:03:44 +0900469 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
470 tmp16 |= hpriv->port_map;
471 pci_write_config_word(pdev, 0x92, tmp16);
472 }
Tejun Heod91542c2006-07-26 15:59:26 +0900473 }
474
475 return 0;
476}
477
Anton Vorontsov781d6552010-03-03 20:17:42 +0300478static void ahci_pci_init_controller(struct ata_host *host)
479{
480 struct ahci_host_priv *hpriv = host->private_data;
481 struct pci_dev *pdev = to_pci_dev(host->dev);
482 void __iomem *port_mmio;
483 u32 tmp;
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100484 int mv;
Tejun Heod91542c2006-07-26 15:59:26 +0900485
Tejun Heo417a1a62007-09-23 13:19:55 +0900486 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100487 if (pdev->device == 0x6121)
488 mv = 2;
489 else
490 mv = 4;
491 port_mmio = __ahci_port_base(host, mv);
Jeff Garzikcd70c262007-07-08 02:29:42 -0400492
493 writel(0, port_mmio + PORT_IRQ_MASK);
494
495 /* clear port IRQ */
496 tmp = readl(port_mmio + PORT_IRQ_STAT);
497 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
498 if (tmp)
499 writel(tmp, port_mmio + PORT_IRQ_STAT);
500 }
501
Anton Vorontsov781d6552010-03-03 20:17:42 +0300502 ahci_init_controller(host);
Tejun Heod91542c2006-07-26 15:59:26 +0900503}
504
Tejun Heocc0680a2007-08-06 18:36:23 +0900505static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +0900506 unsigned long deadline)
Tejun Heoad616ff2006-11-01 18:00:24 +0900507{
Tejun Heocc0680a2007-08-06 18:36:23 +0900508 struct ata_port *ap = link->ap;
Tejun Heo9dadd452008-04-07 22:47:19 +0900509 bool online;
Tejun Heoad616ff2006-11-01 18:00:24 +0900510 int rc;
511
512 DPRINTK("ENTER\n");
513
Tejun Heo4447d352007-04-17 23:44:08 +0900514 ahci_stop_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900515
Tejun Heocc0680a2007-08-06 18:36:23 +0900516 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +0900517 deadline, &online, NULL);
Tejun Heoad616ff2006-11-01 18:00:24 +0900518
Tejun Heo4447d352007-04-17 23:44:08 +0900519 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900520
521 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
522
523 /* vt8251 doesn't clear BSY on signature FIS reception,
524 * request follow-up softreset.
525 */
Tejun Heo9dadd452008-04-07 22:47:19 +0900526 return online ? -EAGAIN : rc;
Tejun Heoad616ff2006-11-01 18:00:24 +0900527}
528
Tejun Heoedc93052007-10-25 14:59:16 +0900529static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
530 unsigned long deadline)
531{
532 struct ata_port *ap = link->ap;
533 struct ahci_port_priv *pp = ap->private_data;
534 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
535 struct ata_taskfile tf;
Tejun Heo9dadd452008-04-07 22:47:19 +0900536 bool online;
Tejun Heoedc93052007-10-25 14:59:16 +0900537 int rc;
538
539 ahci_stop_engine(ap);
540
541 /* clear D2H reception area to properly wait for D2H FIS */
542 ata_tf_init(link->device, &tf);
543 tf.command = 0x80;
544 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
545
546 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +0900547 deadline, &online, NULL);
Tejun Heoedc93052007-10-25 14:59:16 +0900548
549 ahci_start_engine(ap);
550
Tejun Heoedc93052007-10-25 14:59:16 +0900551 /* The pseudo configuration device on SIMG4726 attached to
552 * ASUS P5W-DH Deluxe doesn't send signature FIS after
553 * hardreset if no device is attached to the first downstream
554 * port && the pseudo device locks up on SRST w/ PMP==0. To
555 * work around this, wait for !BSY only briefly. If BSY isn't
556 * cleared, perform CLO and proceed to IDENTIFY (achieved by
557 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
558 *
559 * Wait for two seconds. Devices attached to downstream port
560 * which can't process the following IDENTIFY after this will
561 * have to be reset again. For most cases, this should
562 * suffice while making probing snappish enough.
563 */
Tejun Heo9dadd452008-04-07 22:47:19 +0900564 if (online) {
565 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
566 ahci_check_ready);
567 if (rc)
Shane Huang78d5ae32009-08-07 15:05:52 +0800568 ahci_kick_engine(ap);
Tejun Heo9dadd452008-04-07 22:47:19 +0900569 }
Tejun Heo9dadd452008-04-07 22:47:19 +0900570 return rc;
Tejun Heoedc93052007-10-25 14:59:16 +0900571}
572
Tejun Heo438ac6d2007-03-02 17:31:26 +0900573#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900574static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
575{
Jeff Garzikcca39742006-08-24 03:19:22 -0400576 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo9b10ae82009-05-30 20:50:12 +0900577 struct ahci_host_priv *hpriv = host->private_data;
Anton Vorontsovd8993342010-03-03 20:17:34 +0300578 void __iomem *mmio = hpriv->mmio;
Tejun Heoc1332872006-07-26 15:59:26 +0900579 u32 ctl;
580
Tejun Heo9b10ae82009-05-30 20:50:12 +0900581 if (mesg.event & PM_EVENT_SUSPEND &&
582 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700583 dev_err(&pdev->dev,
584 "BIOS update required for suspend/resume\n");
Tejun Heo9b10ae82009-05-30 20:50:12 +0900585 return -EIO;
586 }
587
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +0100588 if (mesg.event & PM_EVENT_SLEEP) {
Tejun Heoc1332872006-07-26 15:59:26 +0900589 /* AHCI spec rev1.1 section 8.3.3:
590 * Software must disable interrupts prior to requesting a
591 * transition of the HBA to D3 state.
592 */
593 ctl = readl(mmio + HOST_CTL);
594 ctl &= ~HOST_IRQ_EN;
595 writel(ctl, mmio + HOST_CTL);
596 readl(mmio + HOST_CTL); /* flush */
597 }
598
599 return ata_pci_device_suspend(pdev, mesg);
600}
601
602static int ahci_pci_device_resume(struct pci_dev *pdev)
603{
Jeff Garzikcca39742006-08-24 03:19:22 -0400604 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heoc1332872006-07-26 15:59:26 +0900605 int rc;
606
Tejun Heo553c4aa2006-12-26 19:39:50 +0900607 rc = ata_pci_device_do_resume(pdev);
608 if (rc)
609 return rc;
Tejun Heoc1332872006-07-26 15:59:26 +0900610
611 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Anton Vorontsov33030402010-03-03 20:17:39 +0300612 rc = ahci_pci_reset_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900613 if (rc)
614 return rc;
615
Anton Vorontsov781d6552010-03-03 20:17:42 +0300616 ahci_pci_init_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900617 }
618
Jeff Garzikcca39742006-08-24 03:19:22 -0400619 ata_host_resume(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900620
621 return 0;
622}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900623#endif
Tejun Heoc1332872006-07-26 15:59:26 +0900624
Tejun Heo4447d352007-04-17 23:44:08 +0900625static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700626{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700628
Alessandro Rubini318893e2012-01-06 13:33:39 +0100629 /*
630 * If the device fixup already set the dma_mask to some non-standard
631 * value, don't extend it here. This happens on STA2X11, for example.
632 */
633 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
634 return 0;
635
Linus Torvalds1da177e2005-04-16 15:20:36 -0700636 if (using_dac &&
Yang Hongyang6a355282009-04-06 19:01:13 -0700637 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
638 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639 if (rc) {
Yang Hongyang284901a2009-04-06 19:01:15 -0700640 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700642 dev_err(&pdev->dev,
643 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700644 return rc;
645 }
646 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647 } else {
Yang Hongyang284901a2009-04-06 19:01:15 -0700648 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700650 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651 return rc;
652 }
Yang Hongyang284901a2009-04-06 19:01:15 -0700653 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700654 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700655 dev_err(&pdev->dev,
656 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657 return rc;
658 }
659 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660 return 0;
661}
662
Anton Vorontsov439fcae2010-03-03 20:17:43 +0300663static void ahci_pci_print_info(struct ata_host *host)
664{
665 struct pci_dev *pdev = to_pci_dev(host->dev);
666 u16 cc;
667 const char *scc_s;
668
669 pci_read_config_word(pdev, 0x0a, &cc);
670 if (cc == PCI_CLASS_STORAGE_IDE)
671 scc_s = "IDE";
672 else if (cc == PCI_CLASS_STORAGE_SATA)
673 scc_s = "SATA";
674 else if (cc == PCI_CLASS_STORAGE_RAID)
675 scc_s = "RAID";
676 else
677 scc_s = "unknown";
678
679 ahci_print_info(host, scc_s);
680}
681
Tejun Heoedc93052007-10-25 14:59:16 +0900682/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
683 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
684 * support PMP and the 4726 either directly exports the device
685 * attached to the first downstream port or acts as a hardware storage
686 * controller and emulate a single ATA device (can be RAID 0/1 or some
687 * other configuration).
688 *
689 * When there's no device attached to the first downstream port of the
690 * 4726, "Config Disk" appears, which is a pseudo ATA device to
691 * configure the 4726. However, ATA emulation of the device is very
692 * lame. It doesn't send signature D2H Reg FIS after the initial
693 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
694 *
695 * The following function works around the problem by always using
696 * hardreset on the port and not depending on receiving signature FIS
697 * afterward. If signature FIS isn't received soon, ATA class is
698 * assumed without follow-up softreset.
699 */
700static void ahci_p5wdh_workaround(struct ata_host *host)
701{
702 static struct dmi_system_id sysids[] = {
703 {
704 .ident = "P5W DH Deluxe",
705 .matches = {
706 DMI_MATCH(DMI_SYS_VENDOR,
707 "ASUSTEK COMPUTER INC"),
708 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
709 },
710 },
711 { }
712 };
713 struct pci_dev *pdev = to_pci_dev(host->dev);
714
715 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
716 dmi_check_system(sysids)) {
717 struct ata_port *ap = host->ports[1];
718
Joe Perchesa44fec12011-04-15 15:51:58 -0700719 dev_info(&pdev->dev,
720 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
Tejun Heoedc93052007-10-25 14:59:16 +0900721
722 ap->ops = &ahci_p5wdh_ops;
723 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
724 }
725}
726
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900727/* only some SB600 ahci controllers can do 64bit DMA */
728static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
Shane Huang58a09b32009-05-27 15:04:43 +0800729{
730 static const struct dmi_system_id sysids[] = {
Tejun Heo03d783b2009-08-16 21:04:02 +0900731 /*
732 * The oldest version known to be broken is 0901 and
733 * working is 1501 which was released on 2007-10-26.
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900734 * Enable 64bit DMA on 1501 and anything newer.
735 *
Tejun Heo03d783b2009-08-16 21:04:02 +0900736 * Please read bko#9412 for more info.
737 */
Shane Huang58a09b32009-05-27 15:04:43 +0800738 {
739 .ident = "ASUS M2A-VM",
740 .matches = {
741 DMI_MATCH(DMI_BOARD_VENDOR,
742 "ASUSTeK Computer INC."),
743 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
744 },
Tejun Heo03d783b2009-08-16 21:04:02 +0900745 .driver_data = "20071026", /* yyyymmdd */
Shane Huang58a09b32009-05-27 15:04:43 +0800746 },
Mark Nelsone65cc192009-11-03 20:06:48 +1100747 /*
748 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
749 * support 64bit DMA.
750 *
751 * BIOS versions earlier than 1.5 had the Manufacturer DMI
752 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
753 * This spelling mistake was fixed in BIOS version 1.5, so
754 * 1.5 and later have the Manufacturer as
755 * "MICRO-STAR INTERNATIONAL CO.,LTD".
756 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
757 *
758 * BIOS versions earlier than 1.9 had a Board Product Name
759 * DMI field of "MS-7376". This was changed to be
760 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
761 * match on DMI_BOARD_NAME of "MS-7376".
762 */
763 {
764 .ident = "MSI K9A2 Platinum",
765 .matches = {
766 DMI_MATCH(DMI_BOARD_VENDOR,
767 "MICRO-STAR INTER"),
768 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
769 },
770 },
Mark Nelson3c4aa912011-06-27 16:33:44 +1000771 /*
772 * All BIOS versions for the Asus M3A support 64bit DMA.
773 * (all release versions from 0301 to 1206 were tested)
774 */
775 {
776 .ident = "ASUS M3A",
777 .matches = {
778 DMI_MATCH(DMI_BOARD_VENDOR,
779 "ASUSTeK Computer INC."),
780 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
781 },
782 },
Shane Huang58a09b32009-05-27 15:04:43 +0800783 { }
784 };
Tejun Heo03d783b2009-08-16 21:04:02 +0900785 const struct dmi_system_id *match;
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900786 int year, month, date;
787 char buf[9];
Shane Huang58a09b32009-05-27 15:04:43 +0800788
Tejun Heo03d783b2009-08-16 21:04:02 +0900789 match = dmi_first_match(sysids);
Shane Huang58a09b32009-05-27 15:04:43 +0800790 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
Tejun Heo03d783b2009-08-16 21:04:02 +0900791 !match)
Shane Huang58a09b32009-05-27 15:04:43 +0800792 return false;
793
Mark Nelsone65cc192009-11-03 20:06:48 +1100794 if (!match->driver_data)
795 goto enable_64bit;
796
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900797 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
798 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
Shane Huang58a09b32009-05-27 15:04:43 +0800799
Mark Nelsone65cc192009-11-03 20:06:48 +1100800 if (strcmp(buf, match->driver_data) >= 0)
801 goto enable_64bit;
802 else {
Joe Perchesa44fec12011-04-15 15:51:58 -0700803 dev_warn(&pdev->dev,
804 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
805 match->ident);
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900806 return false;
807 }
Mark Nelsone65cc192009-11-03 20:06:48 +1100808
809enable_64bit:
Joe Perchesa44fec12011-04-15 15:51:58 -0700810 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
Mark Nelsone65cc192009-11-03 20:06:48 +1100811 return true;
Shane Huang58a09b32009-05-27 15:04:43 +0800812}
813
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +0100814static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
815{
816 static const struct dmi_system_id broken_systems[] = {
817 {
818 .ident = "HP Compaq nx6310",
819 .matches = {
820 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
821 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
822 },
823 /* PCI slot number of the controller */
824 .driver_data = (void *)0x1FUL,
825 },
Maciej Ruteckid2f9c062009-03-20 00:06:46 +0100826 {
827 .ident = "HP Compaq 6720s",
828 .matches = {
829 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
830 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
831 },
832 /* PCI slot number of the controller */
833 .driver_data = (void *)0x1FUL,
834 },
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +0100835
836 { } /* terminate list */
837 };
838 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
839
840 if (dmi) {
841 unsigned long slot = (unsigned long)dmi->driver_data;
842 /* apply the quirk only to on-board controllers */
843 return slot == PCI_SLOT(pdev->devfn);
844 }
845
846 return false;
847}
848
Tejun Heo9b10ae82009-05-30 20:50:12 +0900849static bool ahci_broken_suspend(struct pci_dev *pdev)
850{
851 static const struct dmi_system_id sysids[] = {
852 /*
853 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
854 * to the harddisk doesn't become online after
855 * resuming from STR. Warn and fail suspend.
Tejun Heo9deb3432010-03-16 09:50:26 +0900856 *
857 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
858 *
859 * Use dates instead of versions to match as HP is
860 * apparently recycling both product and version
861 * strings.
862 *
863 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
Tejun Heo9b10ae82009-05-30 20:50:12 +0900864 */
865 {
866 .ident = "dv4",
867 .matches = {
868 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
869 DMI_MATCH(DMI_PRODUCT_NAME,
870 "HP Pavilion dv4 Notebook PC"),
871 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900872 .driver_data = "20090105", /* F.30 */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900873 },
874 {
875 .ident = "dv5",
876 .matches = {
877 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
878 DMI_MATCH(DMI_PRODUCT_NAME,
879 "HP Pavilion dv5 Notebook PC"),
880 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900881 .driver_data = "20090506", /* F.16 */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900882 },
883 {
884 .ident = "dv6",
885 .matches = {
886 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
887 DMI_MATCH(DMI_PRODUCT_NAME,
888 "HP Pavilion dv6 Notebook PC"),
889 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900890 .driver_data = "20090423", /* F.21 */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900891 },
892 {
893 .ident = "HDX18",
894 .matches = {
895 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
896 DMI_MATCH(DMI_PRODUCT_NAME,
897 "HP HDX18 Notebook PC"),
898 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900899 .driver_data = "20090430", /* F.23 */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900900 },
Tejun Heocedc9bf2010-01-28 16:04:15 +0900901 /*
902 * Acer eMachines G725 has the same problem. BIOS
903 * V1.03 is known to be broken. V3.04 is known to
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300904 * work. Between, there are V1.06, V2.06 and V3.03
Tejun Heocedc9bf2010-01-28 16:04:15 +0900905 * that we don't have much idea about. For now,
906 * blacklist anything older than V3.04.
Tejun Heo9deb3432010-03-16 09:50:26 +0900907 *
908 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
Tejun Heocedc9bf2010-01-28 16:04:15 +0900909 */
910 {
911 .ident = "G725",
912 .matches = {
913 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
914 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
915 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900916 .driver_data = "20091216", /* V3.04 */
Tejun Heocedc9bf2010-01-28 16:04:15 +0900917 },
Tejun Heo9b10ae82009-05-30 20:50:12 +0900918 { } /* terminate list */
919 };
920 const struct dmi_system_id *dmi = dmi_first_match(sysids);
Tejun Heo9deb3432010-03-16 09:50:26 +0900921 int year, month, date;
922 char buf[9];
Tejun Heo9b10ae82009-05-30 20:50:12 +0900923
924 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
925 return false;
926
Tejun Heo9deb3432010-03-16 09:50:26 +0900927 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
928 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
Tejun Heo9b10ae82009-05-30 20:50:12 +0900929
Tejun Heo9deb3432010-03-16 09:50:26 +0900930 return strcmp(buf, dmi->driver_data) < 0;
Tejun Heo9b10ae82009-05-30 20:50:12 +0900931}
932
Tejun Heo55946392009-08-04 14:30:08 +0900933static bool ahci_broken_online(struct pci_dev *pdev)
934{
935#define ENCODE_BUSDEVFN(bus, slot, func) \
936 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
937 static const struct dmi_system_id sysids[] = {
938 /*
939 * There are several gigabyte boards which use
940 * SIMG5723s configured as hardware RAID. Certain
941 * 5723 firmware revisions shipped there keep the link
942 * online but fail to answer properly to SRST or
943 * IDENTIFY when no device is attached downstream
944 * causing libata to retry quite a few times leading
945 * to excessive detection delay.
946 *
947 * As these firmwares respond to the second reset try
948 * with invalid device signature, considering unknown
949 * sig as offline works around the problem acceptably.
950 */
951 {
952 .ident = "EP45-DQ6",
953 .matches = {
954 DMI_MATCH(DMI_BOARD_VENDOR,
955 "Gigabyte Technology Co., Ltd."),
956 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
957 },
958 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
959 },
960 {
961 .ident = "EP45-DS5",
962 .matches = {
963 DMI_MATCH(DMI_BOARD_VENDOR,
964 "Gigabyte Technology Co., Ltd."),
965 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
966 },
967 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
968 },
969 { } /* terminate list */
970 };
971#undef ENCODE_BUSDEVFN
972 const struct dmi_system_id *dmi = dmi_first_match(sysids);
973 unsigned int val;
974
975 if (!dmi)
976 return false;
977
978 val = (unsigned long)dmi->driver_data;
979
980 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
981}
982
Markus Trippelsdorf8e513212009-10-09 05:41:47 +0200983#ifdef CONFIG_ATA_ACPI
Tejun Heof80ae7e2009-09-16 04:18:03 +0900984static void ahci_gtf_filter_workaround(struct ata_host *host)
985{
986 static const struct dmi_system_id sysids[] = {
987 /*
988 * Aspire 3810T issues a bunch of SATA enable commands
989 * via _GTF including an invalid one and one which is
990 * rejected by the device. Among the successful ones
991 * is FPDMA non-zero offset enable which when enabled
992 * only on the drive side leads to NCQ command
993 * failures. Filter it out.
994 */
995 {
996 .ident = "Aspire 3810T",
997 .matches = {
998 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
999 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1000 },
1001 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1002 },
1003 { }
1004 };
1005 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1006 unsigned int filter;
1007 int i;
1008
1009 if (!dmi)
1010 return;
1011
1012 filter = (unsigned long)dmi->driver_data;
Joe Perchesa44fec12011-04-15 15:51:58 -07001013 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1014 filter, dmi->ident);
Tejun Heof80ae7e2009-09-16 04:18:03 +09001015
1016 for (i = 0; i < host->n_ports; i++) {
1017 struct ata_port *ap = host->ports[i];
1018 struct ata_link *link;
1019 struct ata_device *dev;
1020
1021 ata_for_each_link(link, ap, EDGE)
1022 ata_for_each_dev(dev, link, ALL)
1023 dev->gtf_filter |= filter;
1024 }
1025}
Markus Trippelsdorf8e513212009-10-09 05:41:47 +02001026#else
1027static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1028{}
1029#endif
Tejun Heof80ae7e2009-09-16 04:18:03 +09001030
Tejun Heo24dc5f32007-01-20 16:00:28 +09001031static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001032{
Tejun Heoe297d992008-06-10 00:13:04 +09001033 unsigned int board_id = ent->driver_data;
1034 struct ata_port_info pi = ahci_port_info[board_id];
Tejun Heo4447d352007-04-17 23:44:08 +09001035 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo24dc5f32007-01-20 16:00:28 +09001036 struct device *dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001037 struct ahci_host_priv *hpriv;
Tejun Heo4447d352007-04-17 23:44:08 +09001038 struct ata_host *host;
Tejun Heo837f5f82008-02-06 15:13:51 +09001039 int n_ports, i, rc;
Alessandro Rubini318893e2012-01-06 13:33:39 +01001040 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001041
1042 VPRINTK("ENTER\n");
1043
Justin P. Mattockb429dd52010-07-03 07:29:25 -07001044 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001045
Joe Perches06296a12011-04-15 15:52:00 -07001046 ata_print_version_once(&pdev->dev, DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001047
Alan Cox5b66c822008-09-03 14:48:34 +01001048 /* The AHCI driver can only drive the SATA ports, the PATA driver
1049 can drive them all so if both drivers are selected make sure
1050 AHCI stays out of the way */
1051 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1052 return -ENODEV;
1053
Tejun Heoc6353b42010-06-17 11:42:22 +02001054 /*
1055 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1056 * ahci, use ata_generic instead.
1057 */
1058 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1059 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1060 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1061 pdev->subsystem_device == 0xcb89)
1062 return -ENODEV;
1063
Mark Nelson7a022672009-11-22 12:07:41 +11001064 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1065 * At the moment, we can only use the AHCI mode. Let the users know
1066 * that for SAS drives they're out of luck.
1067 */
1068 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
Joe Perchesa44fec12011-04-15 15:51:58 -07001069 dev_info(&pdev->dev,
1070 "PDC42819 can only drive SATA devices with this driver\n");
Mark Nelson7a022672009-11-22 12:07:41 +11001071
Alessandro Rubini318893e2012-01-06 13:33:39 +01001072 /* The Connext uses non-standard BAR */
1073 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1074 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1075
Tejun Heo4447d352007-04-17 23:44:08 +09001076 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09001077 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001078 if (rc)
1079 return rc;
1080
Tejun Heodea55132008-03-11 19:52:31 +09001081 /* AHCI controllers often implement SFF compatible interface.
1082 * Grab all PCI BARs just in case.
1083 */
Alessandro Rubini318893e2012-01-06 13:33:39 +01001084 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001085 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001086 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001087 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001088 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001089
Tejun Heoc4f77922007-12-06 15:09:43 +09001090 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1091 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1092 u8 map;
1093
1094 /* ICH6s share the same PCI ID for both piix and ahci
1095 * modes. Enabling ahci mode while MAP indicates
1096 * combined mode is a bad idea. Yield to ata_piix.
1097 */
1098 pci_read_config_byte(pdev, ICH_MAP, &map);
1099 if (map & 0x3) {
Joe Perchesa44fec12011-04-15 15:51:58 -07001100 dev_info(&pdev->dev,
1101 "controller is in combined mode, can't enable AHCI mode\n");
Tejun Heoc4f77922007-12-06 15:09:43 +09001102 return -ENODEV;
1103 }
1104 }
1105
Tejun Heo24dc5f32007-01-20 16:00:28 +09001106 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1107 if (!hpriv)
1108 return -ENOMEM;
Tejun Heo417a1a62007-09-23 13:19:55 +09001109 hpriv->flags |= (unsigned long)pi.private_data;
1110
Tejun Heoe297d992008-06-10 00:13:04 +09001111 /* MCP65 revision A1 and A2 can't do MSI */
1112 if (board_id == board_ahci_mcp65 &&
1113 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1114 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1115
Shane Huange427fe02008-12-30 10:53:41 +08001116 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1117 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1118 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1119
Tejun Heo2fcad9d2009-10-03 18:27:29 +09001120 /* only some SB600s can do 64bit DMA */
1121 if (ahci_sb600_enable_64bit(pdev))
1122 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
Shane Huang58a09b32009-05-27 15:04:43 +08001123
Tejun Heo31b239a2009-09-17 00:34:39 +09001124 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1125 pci_intx(pdev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001126
Alessandro Rubini318893e2012-01-06 13:33:39 +01001127 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
Anton Vorontsovd8993342010-03-03 20:17:34 +03001128
Tejun Heo4447d352007-04-17 23:44:08 +09001129 /* save initial config */
Anton Vorontsov394d6e52010-03-03 20:17:36 +03001130 ahci_pci_save_initial_config(pdev, hpriv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001131
Tejun Heo4447d352007-04-17 23:44:08 +09001132 /* prepare host */
Robert Hancock453d3132010-01-26 22:33:23 -06001133 if (hpriv->cap & HOST_CAP_NCQ) {
1134 pi.flags |= ATA_FLAG_NCQ;
Tejun Heo83f2b962010-03-30 10:28:32 +09001135 /*
1136 * Auto-activate optimization is supposed to be
1137 * supported on all AHCI controllers indicating NCQ
1138 * capability, but it seems to be broken on some
1139 * chipsets including NVIDIAs.
1140 */
1141 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
Robert Hancock453d3132010-01-26 22:33:23 -06001142 pi.flags |= ATA_FLAG_FPDMA_AA;
1143 }
Tejun Heo4447d352007-04-17 23:44:08 +09001144
Tejun Heo7d50b602007-09-23 13:19:54 +09001145 if (hpriv->cap & HOST_CAP_PMP)
1146 pi.flags |= ATA_FLAG_PMP;
1147
Anton Vorontsov0cbb0e72010-03-03 20:17:45 +03001148 ahci_set_em_messages(hpriv, &pi);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001149
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01001150 if (ahci_broken_system_poweroff(pdev)) {
1151 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1152 dev_info(&pdev->dev,
1153 "quirky BIOS, skipping spindown on poweroff\n");
1154 }
1155
Tejun Heo9b10ae82009-05-30 20:50:12 +09001156 if (ahci_broken_suspend(pdev)) {
1157 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
Joe Perchesa44fec12011-04-15 15:51:58 -07001158 dev_warn(&pdev->dev,
1159 "BIOS update required for suspend/resume\n");
Tejun Heo9b10ae82009-05-30 20:50:12 +09001160 }
1161
Tejun Heo55946392009-08-04 14:30:08 +09001162 if (ahci_broken_online(pdev)) {
1163 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1164 dev_info(&pdev->dev,
1165 "online status unreliable, applying workaround\n");
1166 }
1167
Tejun Heo837f5f82008-02-06 15:13:51 +09001168 /* CAP.NP sometimes indicate the index of the last enabled
1169 * port, at other times, that of the last possible port, so
1170 * determining the maximum port number requires looking at
1171 * both CAP.NP and port_map.
1172 */
1173 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1174
1175 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
Tejun Heo4447d352007-04-17 23:44:08 +09001176 if (!host)
1177 return -ENOMEM;
Tejun Heo4447d352007-04-17 23:44:08 +09001178 host->private_data = hpriv;
1179
Arjan van de Venf3d7f232009-01-26 02:05:44 -08001180 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
Arjan van de Ven886ad092009-01-09 15:54:07 -08001181 host->flags |= ATA_HOST_PARALLEL_SCAN;
Arjan van de Venf3d7f232009-01-26 02:05:44 -08001182 else
1183 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
Arjan van de Ven886ad092009-01-09 15:54:07 -08001184
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001185 if (pi.flags & ATA_FLAG_EM)
1186 ahci_reset_em(host);
1187
Tejun Heo4447d352007-04-17 23:44:08 +09001188 for (i = 0; i < host->n_ports; i++) {
Jeff Garzikdab632e2007-05-28 08:33:01 -04001189 struct ata_port *ap = host->ports[i];
Tejun Heo4447d352007-04-17 23:44:08 +09001190
Alessandro Rubini318893e2012-01-06 13:33:39 +01001191 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1192 ata_port_pbar_desc(ap, ahci_pci_bar,
Tejun Heocbcdd872007-08-18 13:14:55 +09001193 0x100 + ap->port_no * 0x80, "port");
1194
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001195 /* set enclosure management message type */
1196 if (ap->flags & ATA_FLAG_EM)
Harry Zhang008dbd62010-04-23 17:27:19 +08001197 ap->em_message_type = hpriv->em_msg_type;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001198
1199
Jeff Garzikdab632e2007-05-28 08:33:01 -04001200 /* disabled/not-implemented port */
Tejun Heo350756f2008-04-07 22:47:21 +09001201 if (!(hpriv->port_map & (1 << i)))
Jeff Garzikdab632e2007-05-28 08:33:01 -04001202 ap->ops = &ata_dummy_port_ops;
Tejun Heo4447d352007-04-17 23:44:08 +09001203 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001204
Tejun Heoedc93052007-10-25 14:59:16 +09001205 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1206 ahci_p5wdh_workaround(host);
1207
Tejun Heof80ae7e2009-09-16 04:18:03 +09001208 /* apply gtf filter quirk */
1209 ahci_gtf_filter_workaround(host);
1210
Linus Torvalds1da177e2005-04-16 15:20:36 -07001211 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09001212 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001213 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001214 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001215
Anton Vorontsov33030402010-03-03 20:17:39 +03001216 rc = ahci_pci_reset_controller(host);
Tejun Heo4447d352007-04-17 23:44:08 +09001217 if (rc)
1218 return rc;
Tejun Heo12fad3f2006-05-15 21:03:55 +09001219
Anton Vorontsov781d6552010-03-03 20:17:42 +03001220 ahci_pci_init_controller(host);
Anton Vorontsov439fcae2010-03-03 20:17:43 +03001221 ahci_pci_print_info(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001222
Tejun Heo4447d352007-04-17 23:44:08 +09001223 pci_set_master(pdev);
1224 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1225 &ahci_sht);
Jeff Garzik907f4672005-05-12 15:03:42 -04001226}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001227
1228static int __init ahci_init(void)
1229{
Pavel Roskinb7887192006-08-10 18:13:18 +09001230 return pci_register_driver(&ahci_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001231}
1232
Linus Torvalds1da177e2005-04-16 15:20:36 -07001233static void __exit ahci_exit(void)
1234{
1235 pci_unregister_driver(&ahci_pci_driver);
1236}
1237
1238
1239MODULE_AUTHOR("Jeff Garzik");
1240MODULE_DESCRIPTION("AHCI SATA low-level driver");
1241MODULE_LICENSE("GPL");
1242MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04001243MODULE_VERSION(DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001244
1245module_init(ahci_init);
1246module_exit(ahci_exit);