Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 5 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the |
| 9 | * "Software"), to deal in the Software without restriction, including |
| 10 | * without limitation the rights to use, copy, modify, merge, publish, |
| 11 | * distribute, sub license, and/or sell copies of the Software, and to |
| 12 | * permit persons to whom the Software is furnished to do so, subject to |
| 13 | * the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the |
| 16 | * next paragraph) shall be included in all copies or substantial portions |
| 17 | * of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 26 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 27 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 30 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 31 | #include <linux/sysrq.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 32 | #include <linux/slab.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | #include "drmP.h" |
| 34 | #include "drm.h" |
| 35 | #include "i915_drm.h" |
| 36 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 37 | #include "i915_trace.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 38 | #include "intel_drv.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | #define MAX_NOPID ((u32)~0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 42 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
| 43 | PIPE_VBLANK_INTERRUPT_STATUS) |
| 44 | |
| 45 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ |
| 46 | PIPE_VBLANK_INTERRUPT_ENABLE) |
| 47 | |
| 48 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ |
| 49 | DRM_I915_VBLANK_PIPE_B) |
| 50 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 51 | /* For display hotplug interrupt */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 52 | static void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 53 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 54 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 55 | if ((dev_priv->irq_mask & mask) != 0) { |
| 56 | dev_priv->irq_mask &= ~mask; |
| 57 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 58 | POSTING_READ(DEIMR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 59 | } |
| 60 | } |
| 61 | |
| 62 | static inline void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 63 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 64 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 65 | if ((dev_priv->irq_mask & mask) != mask) { |
| 66 | dev_priv->irq_mask |= mask; |
| 67 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 68 | POSTING_READ(DEIMR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 69 | } |
| 70 | } |
| 71 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 72 | void |
| 73 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 74 | { |
| 75 | if ((dev_priv->pipestat[pipe] & mask) != mask) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 76 | u32 reg = PIPESTAT(pipe); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 77 | |
| 78 | dev_priv->pipestat[pipe] |= mask; |
| 79 | /* Enable the interrupt, clear any pending status */ |
| 80 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 81 | POSTING_READ(reg); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 82 | } |
| 83 | } |
| 84 | |
| 85 | void |
| 86 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 87 | { |
| 88 | if ((dev_priv->pipestat[pipe] & mask) != 0) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 89 | u32 reg = PIPESTAT(pipe); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 90 | |
| 91 | dev_priv->pipestat[pipe] &= ~mask; |
| 92 | I915_WRITE(reg, dev_priv->pipestat[pipe]); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 93 | POSTING_READ(reg); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 94 | } |
| 95 | } |
| 96 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 97 | /** |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 98 | * intel_enable_asle - enable ASLE interrupt for OpRegion |
| 99 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 100 | void intel_enable_asle(struct drm_device *dev) |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 101 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 102 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 103 | unsigned long irqflags; |
| 104 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 105 | /* FIXME: opregion/asle for VLV */ |
| 106 | if (IS_VALLEYVIEW(dev)) |
| 107 | return; |
| 108 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 109 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 110 | |
Eric Anholt | c619eed | 2010-01-28 16:45:52 -0800 | [diff] [blame] | 111 | if (HAS_PCH_SPLIT(dev)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 112 | ironlake_enable_display_irq(dev_priv, DE_GSE); |
Zhao Yakui | edcb49c | 2010-04-07 17:11:21 +0800 | [diff] [blame] | 113 | else { |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 114 | i915_enable_pipestat(dev_priv, 1, |
Jesse Barnes | d874bcf | 2010-06-30 13:16:00 -0700 | [diff] [blame] | 115 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 116 | if (INTEL_INFO(dev)->gen >= 4) |
Zhao Yakui | edcb49c | 2010-04-07 17:11:21 +0800 | [diff] [blame] | 117 | i915_enable_pipestat(dev_priv, 0, |
Jesse Barnes | d874bcf | 2010-06-30 13:16:00 -0700 | [diff] [blame] | 118 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
Zhao Yakui | edcb49c | 2010-04-07 17:11:21 +0800 | [diff] [blame] | 119 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 120 | |
| 121 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | /** |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 125 | * i915_pipe_enabled - check if a pipe is enabled |
| 126 | * @dev: DRM device |
| 127 | * @pipe: pipe to check |
| 128 | * |
| 129 | * Reading certain registers when the pipe is disabled can hang the chip. |
| 130 | * Use this routine to make sure the PLL is running and the pipe is active |
| 131 | * before reading such registers if unsure. |
| 132 | */ |
| 133 | static int |
| 134 | i915_pipe_enabled(struct drm_device *dev, int pipe) |
| 135 | { |
| 136 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 137 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 138 | } |
| 139 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 140 | /* Called from drm generic code, passed a 'crtc', which |
| 141 | * we use as a pipe index |
| 142 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 143 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 144 | { |
| 145 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 146 | unsigned long high_frame; |
| 147 | unsigned long low_frame; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 148 | u32 high1, high2, low; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 149 | |
| 150 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 151 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 152 | "pipe %c\n", pipe_name(pipe)); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 153 | return 0; |
| 154 | } |
| 155 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 156 | high_frame = PIPEFRAME(pipe); |
| 157 | low_frame = PIPEFRAMEPIXEL(pipe); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 158 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 159 | /* |
| 160 | * High & low register fields aren't synchronized, so make sure |
| 161 | * we get a low value that's stable across two reads of the high |
| 162 | * register. |
| 163 | */ |
| 164 | do { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 165 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
| 166 | low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; |
| 167 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 168 | } while (high1 != high2); |
| 169 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 170 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
| 171 | low >>= PIPE_FRAME_LOW_SHIFT; |
| 172 | return (high1 << 8) | low; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 173 | } |
| 174 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 175 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 176 | { |
| 177 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 178 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 179 | |
| 180 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 181 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 182 | "pipe %c\n", pipe_name(pipe)); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 183 | return 0; |
| 184 | } |
| 185 | |
| 186 | return I915_READ(reg); |
| 187 | } |
| 188 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 189 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 190 | int *vpos, int *hpos) |
| 191 | { |
| 192 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 193 | u32 vbl = 0, position = 0; |
| 194 | int vbl_start, vbl_end, htotal, vtotal; |
| 195 | bool in_vbl = true; |
| 196 | int ret = 0; |
| 197 | |
| 198 | if (!i915_pipe_enabled(dev, pipe)) { |
| 199 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 200 | "pipe %c\n", pipe_name(pipe)); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 201 | return 0; |
| 202 | } |
| 203 | |
| 204 | /* Get vtotal. */ |
| 205 | vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff); |
| 206 | |
| 207 | if (INTEL_INFO(dev)->gen >= 4) { |
| 208 | /* No obvious pixelcount register. Only query vertical |
| 209 | * scanout position from Display scan line register. |
| 210 | */ |
| 211 | position = I915_READ(PIPEDSL(pipe)); |
| 212 | |
| 213 | /* Decode into vertical scanout position. Don't have |
| 214 | * horizontal scanout position. |
| 215 | */ |
| 216 | *vpos = position & 0x1fff; |
| 217 | *hpos = 0; |
| 218 | } else { |
| 219 | /* Have access to pixelcount since start of frame. |
| 220 | * We can split this into vertical and horizontal |
| 221 | * scanout position. |
| 222 | */ |
| 223 | position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
| 224 | |
| 225 | htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff); |
| 226 | *vpos = position / htotal; |
| 227 | *hpos = position - (*vpos * htotal); |
| 228 | } |
| 229 | |
| 230 | /* Query vblank area. */ |
| 231 | vbl = I915_READ(VBLANK(pipe)); |
| 232 | |
| 233 | /* Test position against vblank region. */ |
| 234 | vbl_start = vbl & 0x1fff; |
| 235 | vbl_end = (vbl >> 16) & 0x1fff; |
| 236 | |
| 237 | if ((*vpos < vbl_start) || (*vpos > vbl_end)) |
| 238 | in_vbl = false; |
| 239 | |
| 240 | /* Inside "upper part" of vblank area? Apply corrective offset: */ |
| 241 | if (in_vbl && (*vpos >= vbl_start)) |
| 242 | *vpos = *vpos - vtotal; |
| 243 | |
| 244 | /* Readouts valid? */ |
| 245 | if (vbl > 0) |
| 246 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
| 247 | |
| 248 | /* In vblank? */ |
| 249 | if (in_vbl) |
| 250 | ret |= DRM_SCANOUTPOS_INVBL; |
| 251 | |
| 252 | return ret; |
| 253 | } |
| 254 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 255 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 256 | int *max_error, |
| 257 | struct timeval *vblank_time, |
| 258 | unsigned flags) |
| 259 | { |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 260 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 261 | struct drm_crtc *crtc; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 262 | |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 263 | if (pipe < 0 || pipe >= dev_priv->num_pipe) { |
| 264 | DRM_ERROR("Invalid crtc %d\n", pipe); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 265 | return -EINVAL; |
| 266 | } |
| 267 | |
| 268 | /* Get drm_crtc to timestamp: */ |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 269 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
| 270 | if (crtc == NULL) { |
| 271 | DRM_ERROR("Invalid crtc %d\n", pipe); |
| 272 | return -EINVAL; |
| 273 | } |
| 274 | |
| 275 | if (!crtc->enabled) { |
| 276 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); |
| 277 | return -EBUSY; |
| 278 | } |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 279 | |
| 280 | /* Helper routine in DRM core does all the work: */ |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 281 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
| 282 | vblank_time, flags, |
| 283 | crtc); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 284 | } |
| 285 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 286 | /* |
| 287 | * Handle hotplug events outside the interrupt handler proper. |
| 288 | */ |
| 289 | static void i915_hotplug_work_func(struct work_struct *work) |
| 290 | { |
| 291 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 292 | hotplug_work); |
| 293 | struct drm_device *dev = dev_priv->dev; |
Keith Packard | c31c4ba | 2009-05-06 11:48:58 -0700 | [diff] [blame] | 294 | struct drm_mode_config *mode_config = &dev->mode_config; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 295 | struct intel_encoder *encoder; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 296 | |
Keith Packard | a65e34c | 2011-07-25 10:04:56 -0700 | [diff] [blame] | 297 | mutex_lock(&mode_config->mutex); |
Jesse Barnes | e67189ab | 2011-02-11 14:44:51 -0800 | [diff] [blame] | 298 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
| 299 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 300 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) |
| 301 | if (encoder->hot_plug) |
| 302 | encoder->hot_plug(encoder); |
| 303 | |
Keith Packard | 40ee338 | 2011-07-28 15:31:19 -0700 | [diff] [blame] | 304 | mutex_unlock(&mode_config->mutex); |
| 305 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 306 | /* Just fire off a uevent and let userspace tell us what to do */ |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 307 | drm_helper_hpd_irq_event(dev); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 308 | } |
| 309 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 310 | static void i915_handle_rps_change(struct drm_device *dev) |
| 311 | { |
| 312 | drm_i915_private_t *dev_priv = dev->dev_private; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 313 | u32 busy_up, busy_down, max_avg, min_avg; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 314 | u8 new_delay = dev_priv->cur_delay; |
| 315 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 316 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 317 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
| 318 | busy_down = I915_READ(RCPREVBSYTDNAVG); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 319 | max_avg = I915_READ(RCBMAXAVG); |
| 320 | min_avg = I915_READ(RCBMINAVG); |
| 321 | |
| 322 | /* Handle RCS change request from hw */ |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 323 | if (busy_up > max_avg) { |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 324 | if (dev_priv->cur_delay != dev_priv->max_delay) |
| 325 | new_delay = dev_priv->cur_delay - 1; |
| 326 | if (new_delay < dev_priv->max_delay) |
| 327 | new_delay = dev_priv->max_delay; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 328 | } else if (busy_down < min_avg) { |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 329 | if (dev_priv->cur_delay != dev_priv->min_delay) |
| 330 | new_delay = dev_priv->cur_delay + 1; |
| 331 | if (new_delay > dev_priv->min_delay) |
| 332 | new_delay = dev_priv->min_delay; |
| 333 | } |
| 334 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 335 | if (ironlake_set_drps(dev, new_delay)) |
| 336 | dev_priv->cur_delay = new_delay; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 337 | |
| 338 | return; |
| 339 | } |
| 340 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 341 | static void notify_ring(struct drm_device *dev, |
| 342 | struct intel_ring_buffer *ring) |
| 343 | { |
| 344 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 475553d | 2011-01-20 09:52:56 +0000 | [diff] [blame] | 345 | u32 seqno; |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 346 | |
Chris Wilson | 475553d | 2011-01-20 09:52:56 +0000 | [diff] [blame] | 347 | if (ring->obj == NULL) |
| 348 | return; |
| 349 | |
| 350 | seqno = ring->get_seqno(ring); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 351 | trace_i915_gem_request_complete(ring, seqno); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 352 | |
| 353 | ring->irq_seqno = seqno; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 354 | wake_up_all(&ring->irq_queue); |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 355 | if (i915_enable_hangcheck) { |
| 356 | dev_priv->hangcheck_count = 0; |
| 357 | mod_timer(&dev_priv->hangcheck_timer, |
| 358 | jiffies + |
| 359 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
| 360 | } |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 361 | } |
| 362 | |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 363 | static void gen6_pm_rps_work(struct work_struct *work) |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 364 | { |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 365 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 366 | rps_work); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 367 | u8 new_delay = dev_priv->cur_delay; |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 368 | u32 pm_iir, pm_imr; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 369 | |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 370 | spin_lock_irq(&dev_priv->rps_lock); |
| 371 | pm_iir = dev_priv->pm_iir; |
| 372 | dev_priv->pm_iir = 0; |
| 373 | pm_imr = I915_READ(GEN6_PMIMR); |
Daniel Vetter | a9e2641 | 2011-09-08 14:00:21 +0200 | [diff] [blame] | 374 | I915_WRITE(GEN6_PMIMR, 0); |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 375 | spin_unlock_irq(&dev_priv->rps_lock); |
| 376 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 377 | if (!pm_iir) |
| 378 | return; |
| 379 | |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 380 | mutex_lock(&dev_priv->dev->struct_mutex); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 381 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
| 382 | if (dev_priv->cur_delay != dev_priv->max_delay) |
| 383 | new_delay = dev_priv->cur_delay + 1; |
| 384 | if (new_delay > dev_priv->max_delay) |
| 385 | new_delay = dev_priv->max_delay; |
| 386 | } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) { |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 387 | gen6_gt_force_wake_get(dev_priv); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 388 | if (dev_priv->cur_delay != dev_priv->min_delay) |
| 389 | new_delay = dev_priv->cur_delay - 1; |
| 390 | if (new_delay < dev_priv->min_delay) { |
| 391 | new_delay = dev_priv->min_delay; |
| 392 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, |
| 393 | I915_READ(GEN6_RP_INTERRUPT_LIMITS) | |
| 394 | ((new_delay << 16) & 0x3f0000)); |
| 395 | } else { |
| 396 | /* Make sure we continue to get down interrupts |
| 397 | * until we hit the minimum frequency */ |
| 398 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, |
| 399 | I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000); |
| 400 | } |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 401 | gen6_gt_force_wake_put(dev_priv); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 402 | } |
| 403 | |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 404 | gen6_set_rps(dev_priv->dev, new_delay); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 405 | dev_priv->cur_delay = new_delay; |
| 406 | |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 407 | /* |
| 408 | * rps_lock not held here because clearing is non-destructive. There is |
| 409 | * an *extremely* unlikely race with gen6_rps_enable() that is prevented |
| 410 | * by holding struct_mutex for the duration of the write. |
| 411 | */ |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 412 | mutex_unlock(&dev_priv->dev->struct_mutex); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 413 | } |
| 414 | |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 415 | static void snb_gt_irq_handler(struct drm_device *dev, |
| 416 | struct drm_i915_private *dev_priv, |
| 417 | u32 gt_iir) |
| 418 | { |
| 419 | |
| 420 | if (gt_iir & (GEN6_RENDER_USER_INTERRUPT | |
| 421 | GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT)) |
| 422 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 423 | if (gt_iir & GEN6_BSD_USER_INTERRUPT) |
| 424 | notify_ring(dev, &dev_priv->ring[VCS]); |
| 425 | if (gt_iir & GEN6_BLITTER_USER_INTERRUPT) |
| 426 | notify_ring(dev, &dev_priv->ring[BCS]); |
| 427 | |
| 428 | if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT | |
| 429 | GT_GEN6_BSD_CS_ERROR_INTERRUPT | |
| 430 | GT_RENDER_CS_ERROR_INTERRUPT)) { |
| 431 | DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); |
| 432 | i915_handle_error(dev, false); |
| 433 | } |
| 434 | } |
| 435 | |
Chris Wilson | fc6826d | 2012-04-15 11:56:03 +0100 | [diff] [blame] | 436 | static void gen6_queue_rps_work(struct drm_i915_private *dev_priv, |
| 437 | u32 pm_iir) |
| 438 | { |
| 439 | unsigned long flags; |
| 440 | |
| 441 | /* |
| 442 | * IIR bits should never already be set because IMR should |
| 443 | * prevent an interrupt from being shown in IIR. The warning |
| 444 | * displays a case where we've unsafely cleared |
| 445 | * dev_priv->pm_iir. Although missing an interrupt of the same |
| 446 | * type is not a problem, it displays a problem in the logic. |
| 447 | * |
| 448 | * The mask bit in IMR is cleared by rps_work. |
| 449 | */ |
| 450 | |
| 451 | spin_lock_irqsave(&dev_priv->rps_lock, flags); |
| 452 | WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); |
| 453 | dev_priv->pm_iir |= pm_iir; |
| 454 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); |
| 455 | POSTING_READ(GEN6_PMIMR); |
| 456 | spin_unlock_irqrestore(&dev_priv->rps_lock, flags); |
| 457 | |
| 458 | queue_work(dev_priv->wq, &dev_priv->rps_work); |
| 459 | } |
| 460 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 461 | static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS) |
| 462 | { |
| 463 | struct drm_device *dev = (struct drm_device *) arg; |
| 464 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 465 | u32 iir, gt_iir, pm_iir; |
| 466 | irqreturn_t ret = IRQ_NONE; |
| 467 | unsigned long irqflags; |
| 468 | int pipe; |
| 469 | u32 pipe_stats[I915_MAX_PIPES]; |
| 470 | u32 vblank_status; |
| 471 | int vblank = 0; |
| 472 | bool blc_event; |
| 473 | |
| 474 | atomic_inc(&dev_priv->irq_received); |
| 475 | |
| 476 | vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS | |
| 477 | PIPE_VBLANK_INTERRUPT_STATUS; |
| 478 | |
| 479 | while (true) { |
| 480 | iir = I915_READ(VLV_IIR); |
| 481 | gt_iir = I915_READ(GTIIR); |
| 482 | pm_iir = I915_READ(GEN6_PMIIR); |
| 483 | |
| 484 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) |
| 485 | goto out; |
| 486 | |
| 487 | ret = IRQ_HANDLED; |
| 488 | |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 489 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 490 | |
| 491 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 492 | for_each_pipe(pipe) { |
| 493 | int reg = PIPESTAT(pipe); |
| 494 | pipe_stats[pipe] = I915_READ(reg); |
| 495 | |
| 496 | /* |
| 497 | * Clear the PIPE*STAT regs before the IIR |
| 498 | */ |
| 499 | if (pipe_stats[pipe] & 0x8000ffff) { |
| 500 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 501 | DRM_DEBUG_DRIVER("pipe %c underrun\n", |
| 502 | pipe_name(pipe)); |
| 503 | I915_WRITE(reg, pipe_stats[pipe]); |
| 504 | } |
| 505 | } |
| 506 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 507 | |
| 508 | /* Consume port. Then clear IIR or we'll miss events */ |
| 509 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
| 510 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
| 511 | |
| 512 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
| 513 | hotplug_status); |
| 514 | if (hotplug_status & dev_priv->hotplug_supported_mask) |
| 515 | queue_work(dev_priv->wq, |
| 516 | &dev_priv->hotplug_work); |
| 517 | |
| 518 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
| 519 | I915_READ(PORT_HOTPLUG_STAT); |
| 520 | } |
| 521 | |
| 522 | |
| 523 | if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) { |
| 524 | drm_handle_vblank(dev, 0); |
| 525 | vblank++; |
Chris Wilson | e0f608d | 2012-04-24 22:59:43 +0100 | [diff] [blame] | 526 | intel_finish_page_flip(dev, 0); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 527 | } |
| 528 | |
| 529 | if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) { |
| 530 | drm_handle_vblank(dev, 1); |
| 531 | vblank++; |
Chris Wilson | e0f608d | 2012-04-24 22:59:43 +0100 | [diff] [blame] | 532 | intel_finish_page_flip(dev, 0); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 533 | } |
| 534 | |
| 535 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
| 536 | blc_event = true; |
| 537 | |
Chris Wilson | fc6826d | 2012-04-15 11:56:03 +0100 | [diff] [blame] | 538 | if (pm_iir & GEN6_PM_DEFERRED_EVENTS) |
| 539 | gen6_queue_rps_work(dev_priv, pm_iir); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 540 | |
| 541 | I915_WRITE(GTIIR, gt_iir); |
| 542 | I915_WRITE(GEN6_PMIIR, pm_iir); |
| 543 | I915_WRITE(VLV_IIR, iir); |
| 544 | } |
| 545 | |
| 546 | out: |
| 547 | return ret; |
| 548 | } |
| 549 | |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 550 | static void pch_irq_handler(struct drm_device *dev) |
| 551 | { |
| 552 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 553 | u32 pch_iir; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 554 | int pipe; |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 555 | |
| 556 | pch_iir = I915_READ(SDEIIR); |
| 557 | |
| 558 | if (pch_iir & SDE_AUDIO_POWER_MASK) |
| 559 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
| 560 | (pch_iir & SDE_AUDIO_POWER_MASK) >> |
| 561 | SDE_AUDIO_POWER_SHIFT); |
| 562 | |
| 563 | if (pch_iir & SDE_GMBUS) |
| 564 | DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); |
| 565 | |
| 566 | if (pch_iir & SDE_AUDIO_HDCP_MASK) |
| 567 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); |
| 568 | |
| 569 | if (pch_iir & SDE_AUDIO_TRANS_MASK) |
| 570 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); |
| 571 | |
| 572 | if (pch_iir & SDE_POISON) |
| 573 | DRM_ERROR("PCH poison interrupt\n"); |
| 574 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 575 | if (pch_iir & SDE_FDI_MASK) |
| 576 | for_each_pipe(pipe) |
| 577 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
| 578 | pipe_name(pipe), |
| 579 | I915_READ(FDI_RX_IIR(pipe))); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 580 | |
| 581 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) |
| 582 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); |
| 583 | |
| 584 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) |
| 585 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); |
| 586 | |
| 587 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) |
| 588 | DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n"); |
| 589 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
| 590 | DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); |
| 591 | } |
| 592 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 593 | static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS) |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 594 | { |
| 595 | struct drm_device *dev = (struct drm_device *) arg; |
| 596 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 597 | int ret = IRQ_NONE; |
| 598 | u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; |
| 599 | struct drm_i915_master_private *master_priv; |
| 600 | |
| 601 | atomic_inc(&dev_priv->irq_received); |
| 602 | |
| 603 | /* disable master interrupt before clearing iir */ |
| 604 | de_ier = I915_READ(DEIER); |
| 605 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); |
| 606 | POSTING_READ(DEIER); |
| 607 | |
| 608 | de_iir = I915_READ(DEIIR); |
| 609 | gt_iir = I915_READ(GTIIR); |
| 610 | pch_iir = I915_READ(SDEIIR); |
| 611 | pm_iir = I915_READ(GEN6_PMIIR); |
| 612 | |
| 613 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0) |
| 614 | goto done; |
| 615 | |
| 616 | ret = IRQ_HANDLED; |
| 617 | |
| 618 | if (dev->primary->master) { |
| 619 | master_priv = dev->primary->master->driver_priv; |
| 620 | if (master_priv->sarea_priv) |
| 621 | master_priv->sarea_priv->last_dispatch = |
| 622 | READ_BREADCRUMB(dev_priv); |
| 623 | } |
| 624 | |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 625 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 626 | |
| 627 | if (de_iir & DE_GSE_IVB) |
| 628 | intel_opregion_gse_intr(dev); |
| 629 | |
| 630 | if (de_iir & DE_PLANEA_FLIP_DONE_IVB) { |
| 631 | intel_prepare_page_flip(dev, 0); |
| 632 | intel_finish_page_flip_plane(dev, 0); |
| 633 | } |
| 634 | |
| 635 | if (de_iir & DE_PLANEB_FLIP_DONE_IVB) { |
| 636 | intel_prepare_page_flip(dev, 1); |
| 637 | intel_finish_page_flip_plane(dev, 1); |
| 638 | } |
| 639 | |
| 640 | if (de_iir & DE_PIPEA_VBLANK_IVB) |
| 641 | drm_handle_vblank(dev, 0); |
| 642 | |
Dan Carpenter | f6b07f4 | 2011-05-25 12:56:56 +0300 | [diff] [blame] | 643 | if (de_iir & DE_PIPEB_VBLANK_IVB) |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 644 | drm_handle_vblank(dev, 1); |
| 645 | |
| 646 | /* check event from PCH */ |
| 647 | if (de_iir & DE_PCH_EVENT_IVB) { |
| 648 | if (pch_iir & SDE_HOTPLUG_MASK_CPT) |
| 649 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); |
| 650 | pch_irq_handler(dev); |
| 651 | } |
| 652 | |
Chris Wilson | fc6826d | 2012-04-15 11:56:03 +0100 | [diff] [blame] | 653 | if (pm_iir & GEN6_PM_DEFERRED_EVENTS) |
| 654 | gen6_queue_rps_work(dev_priv, pm_iir); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 655 | |
| 656 | /* should clear PCH hotplug event before clear CPU irq */ |
| 657 | I915_WRITE(SDEIIR, pch_iir); |
| 658 | I915_WRITE(GTIIR, gt_iir); |
| 659 | I915_WRITE(DEIIR, de_iir); |
| 660 | I915_WRITE(GEN6_PMIIR, pm_iir); |
| 661 | |
| 662 | done: |
| 663 | I915_WRITE(DEIER, de_ier); |
| 664 | POSTING_READ(DEIER); |
| 665 | |
| 666 | return ret; |
| 667 | } |
| 668 | |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 669 | static void ilk_gt_irq_handler(struct drm_device *dev, |
| 670 | struct drm_i915_private *dev_priv, |
| 671 | u32 gt_iir) |
| 672 | { |
| 673 | if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) |
| 674 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 675 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
| 676 | notify_ring(dev, &dev_priv->ring[VCS]); |
| 677 | } |
| 678 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 679 | static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 680 | { |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 681 | struct drm_device *dev = (struct drm_device *) arg; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 682 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 683 | int ret = IRQ_NONE; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 684 | u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 685 | u32 hotplug_mask; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 686 | struct drm_i915_master_private *master_priv; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 687 | |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 688 | atomic_inc(&dev_priv->irq_received); |
| 689 | |
Zou, Nanhai | 2d109a8 | 2009-11-06 02:13:01 +0000 | [diff] [blame] | 690 | /* disable master interrupt before clearing iir */ |
| 691 | de_ier = I915_READ(DEIER); |
| 692 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 693 | POSTING_READ(DEIER); |
Zou, Nanhai | 2d109a8 | 2009-11-06 02:13:01 +0000 | [diff] [blame] | 694 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 695 | de_iir = I915_READ(DEIIR); |
| 696 | gt_iir = I915_READ(GTIIR); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 697 | pch_iir = I915_READ(SDEIIR); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 698 | pm_iir = I915_READ(GEN6_PMIIR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 699 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 700 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && |
| 701 | (!IS_GEN6(dev) || pm_iir == 0)) |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 702 | goto done; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 703 | |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 704 | if (HAS_PCH_CPT(dev)) |
| 705 | hotplug_mask = SDE_HOTPLUG_MASK_CPT; |
| 706 | else |
| 707 | hotplug_mask = SDE_HOTPLUG_MASK; |
| 708 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 709 | ret = IRQ_HANDLED; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 710 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 711 | if (dev->primary->master) { |
| 712 | master_priv = dev->primary->master->driver_priv; |
| 713 | if (master_priv->sarea_priv) |
| 714 | master_priv->sarea_priv->last_dispatch = |
| 715 | READ_BREADCRUMB(dev_priv); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 716 | } |
| 717 | |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 718 | if (IS_GEN5(dev)) |
| 719 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); |
| 720 | else |
| 721 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 722 | |
| 723 | if (de_iir & DE_GSE) |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 724 | intel_opregion_gse_intr(dev); |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 725 | |
Zhenyu Wang | f072d2e | 2010-02-09 09:46:19 +0800 | [diff] [blame] | 726 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 727 | intel_prepare_page_flip(dev, 0); |
Chris Wilson | 2bbda38 | 2010-09-02 17:59:39 +0100 | [diff] [blame] | 728 | intel_finish_page_flip_plane(dev, 0); |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 729 | } |
| 730 | |
Zhenyu Wang | f072d2e | 2010-02-09 09:46:19 +0800 | [diff] [blame] | 731 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
| 732 | intel_prepare_page_flip(dev, 1); |
Chris Wilson | 2bbda38 | 2010-09-02 17:59:39 +0100 | [diff] [blame] | 733 | intel_finish_page_flip_plane(dev, 1); |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 734 | } |
Li Peng | c062df6 | 2010-01-23 00:12:58 +0800 | [diff] [blame] | 735 | |
Zhenyu Wang | f072d2e | 2010-02-09 09:46:19 +0800 | [diff] [blame] | 736 | if (de_iir & DE_PIPEA_VBLANK) |
| 737 | drm_handle_vblank(dev, 0); |
| 738 | |
| 739 | if (de_iir & DE_PIPEB_VBLANK) |
| 740 | drm_handle_vblank(dev, 1); |
| 741 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 742 | /* check event from PCH */ |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 743 | if (de_iir & DE_PCH_EVENT) { |
| 744 | if (pch_iir & hotplug_mask) |
| 745 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); |
| 746 | pch_irq_handler(dev); |
| 747 | } |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 748 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 749 | if (de_iir & DE_PCU_EVENT) { |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 750 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 751 | i915_handle_rps_change(dev); |
| 752 | } |
| 753 | |
Chris Wilson | fc6826d | 2012-04-15 11:56:03 +0100 | [diff] [blame] | 754 | if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) |
| 755 | gen6_queue_rps_work(dev_priv, pm_iir); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 756 | |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 757 | /* should clear PCH hotplug event before clear CPU irq */ |
| 758 | I915_WRITE(SDEIIR, pch_iir); |
| 759 | I915_WRITE(GTIIR, gt_iir); |
| 760 | I915_WRITE(DEIIR, de_iir); |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 761 | I915_WRITE(GEN6_PMIIR, pm_iir); |
Zou Nan hai | c7c8510 | 2010-01-15 10:29:06 +0800 | [diff] [blame] | 762 | |
| 763 | done: |
Zou, Nanhai | 2d109a8 | 2009-11-06 02:13:01 +0000 | [diff] [blame] | 764 | I915_WRITE(DEIER, de_ier); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 765 | POSTING_READ(DEIER); |
Zou, Nanhai | 2d109a8 | 2009-11-06 02:13:01 +0000 | [diff] [blame] | 766 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 767 | return ret; |
| 768 | } |
| 769 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 770 | /** |
| 771 | * i915_error_work_func - do process context error handling work |
| 772 | * @work: work struct |
| 773 | * |
| 774 | * Fire an error uevent so userspace can see that a hang or error |
| 775 | * was detected. |
| 776 | */ |
| 777 | static void i915_error_work_func(struct work_struct *work) |
| 778 | { |
| 779 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 780 | error_work); |
| 781 | struct drm_device *dev = dev_priv->dev; |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 782 | char *error_event[] = { "ERROR=1", NULL }; |
| 783 | char *reset_event[] = { "RESET=1", NULL }; |
| 784 | char *reset_done_event[] = { "ERROR=0", NULL }; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 785 | |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 786 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 787 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 788 | if (atomic_read(&dev_priv->mm.wedged)) { |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 789 | DRM_DEBUG_DRIVER("resetting chip\n"); |
| 790 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); |
| 791 | if (!i915_reset(dev, GRDOM_RENDER)) { |
| 792 | atomic_set(&dev_priv->mm.wedged, 0); |
| 793 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 794 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 795 | complete_all(&dev_priv->error_completion); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 796 | } |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 797 | } |
| 798 | |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 799 | #ifdef CONFIG_DEBUG_FS |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 800 | static struct drm_i915_error_object * |
Chris Wilson | bcfb2e2 | 2011-01-07 21:06:07 +0000 | [diff] [blame] | 801 | i915_error_object_create(struct drm_i915_private *dev_priv, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 802 | struct drm_i915_gem_object *src) |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 803 | { |
| 804 | struct drm_i915_error_object *dst; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 805 | int page, page_count; |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 806 | u32 reloc_offset; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 807 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 808 | if (src == NULL || src->pages == NULL) |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 809 | return NULL; |
| 810 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 811 | page_count = src->base.size / PAGE_SIZE; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 812 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 813 | dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 814 | if (dst == NULL) |
| 815 | return NULL; |
| 816 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 817 | reloc_offset = src->gtt_offset; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 818 | for (page = 0; page < page_count; page++) { |
Andrew Morton | 788885a | 2010-05-11 14:07:05 -0700 | [diff] [blame] | 819 | unsigned long flags; |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 820 | void *d; |
Andrew Morton | 788885a | 2010-05-11 14:07:05 -0700 | [diff] [blame] | 821 | |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 822 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 823 | if (d == NULL) |
| 824 | goto unwind; |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 825 | |
Andrew Morton | 788885a | 2010-05-11 14:07:05 -0700 | [diff] [blame] | 826 | local_irq_save(flags); |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 827 | if (reloc_offset < dev_priv->mm.gtt_mappable_end && |
| 828 | src->has_global_gtt_mapping) { |
Chris Wilson | 172975aa | 2011-12-14 13:57:25 +0100 | [diff] [blame] | 829 | void __iomem *s; |
| 830 | |
| 831 | /* Simply ignore tiling or any overlapping fence. |
| 832 | * It's part of the error state, and this hopefully |
| 833 | * captures what the GPU read. |
| 834 | */ |
| 835 | |
| 836 | s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
| 837 | reloc_offset); |
| 838 | memcpy_fromio(d, s, PAGE_SIZE); |
| 839 | io_mapping_unmap_atomic(s); |
| 840 | } else { |
| 841 | void *s; |
| 842 | |
| 843 | drm_clflush_pages(&src->pages[page], 1); |
| 844 | |
| 845 | s = kmap_atomic(src->pages[page]); |
| 846 | memcpy(d, s, PAGE_SIZE); |
| 847 | kunmap_atomic(s); |
| 848 | |
| 849 | drm_clflush_pages(&src->pages[page], 1); |
| 850 | } |
Andrew Morton | 788885a | 2010-05-11 14:07:05 -0700 | [diff] [blame] | 851 | local_irq_restore(flags); |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 852 | |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 853 | dst->pages[page] = d; |
Chris Wilson | e56660d | 2010-08-07 11:01:26 +0100 | [diff] [blame] | 854 | |
| 855 | reloc_offset += PAGE_SIZE; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 856 | } |
| 857 | dst->page_count = page_count; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 858 | dst->gtt_offset = src->gtt_offset; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 859 | |
| 860 | return dst; |
| 861 | |
| 862 | unwind: |
| 863 | while (page--) |
| 864 | kfree(dst->pages[page]); |
| 865 | kfree(dst); |
| 866 | return NULL; |
| 867 | } |
| 868 | |
| 869 | static void |
| 870 | i915_error_object_free(struct drm_i915_error_object *obj) |
| 871 | { |
| 872 | int page; |
| 873 | |
| 874 | if (obj == NULL) |
| 875 | return; |
| 876 | |
| 877 | for (page = 0; page < obj->page_count; page++) |
| 878 | kfree(obj->pages[page]); |
| 879 | |
| 880 | kfree(obj); |
| 881 | } |
| 882 | |
| 883 | static void |
| 884 | i915_error_state_free(struct drm_device *dev, |
| 885 | struct drm_i915_error_state *error) |
| 886 | { |
Chris Wilson | e2f973d | 2011-01-27 19:15:11 +0000 | [diff] [blame] | 887 | int i; |
| 888 | |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 889 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { |
| 890 | i915_error_object_free(error->ring[i].batchbuffer); |
| 891 | i915_error_object_free(error->ring[i].ringbuffer); |
| 892 | kfree(error->ring[i].requests); |
| 893 | } |
Chris Wilson | e2f973d | 2011-01-27 19:15:11 +0000 | [diff] [blame] | 894 | |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 895 | kfree(error->active_bo); |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 896 | kfree(error->overlay); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 897 | kfree(error); |
| 898 | } |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 899 | static void capture_bo(struct drm_i915_error_buffer *err, |
| 900 | struct drm_i915_gem_object *obj) |
| 901 | { |
| 902 | err->size = obj->base.size; |
| 903 | err->name = obj->base.name; |
| 904 | err->seqno = obj->last_rendering_seqno; |
| 905 | err->gtt_offset = obj->gtt_offset; |
| 906 | err->read_domains = obj->base.read_domains; |
| 907 | err->write_domain = obj->base.write_domain; |
| 908 | err->fence_reg = obj->fence_reg; |
| 909 | err->pinned = 0; |
| 910 | if (obj->pin_count > 0) |
| 911 | err->pinned = 1; |
| 912 | if (obj->user_pin_count > 0) |
| 913 | err->pinned = -1; |
| 914 | err->tiling = obj->tiling_mode; |
| 915 | err->dirty = obj->dirty; |
| 916 | err->purgeable = obj->madv != I915_MADV_WILLNEED; |
| 917 | err->ring = obj->ring ? obj->ring->id : -1; |
| 918 | err->cache_level = obj->cache_level; |
| 919 | } |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 920 | |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 921 | static u32 capture_active_bo(struct drm_i915_error_buffer *err, |
| 922 | int count, struct list_head *head) |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 923 | { |
| 924 | struct drm_i915_gem_object *obj; |
| 925 | int i = 0; |
| 926 | |
| 927 | list_for_each_entry(obj, head, mm_list) { |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 928 | capture_bo(err++, obj); |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 929 | if (++i == count) |
| 930 | break; |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 931 | } |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 932 | |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 933 | return i; |
| 934 | } |
| 935 | |
| 936 | static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, |
| 937 | int count, struct list_head *head) |
| 938 | { |
| 939 | struct drm_i915_gem_object *obj; |
| 940 | int i = 0; |
| 941 | |
| 942 | list_for_each_entry(obj, head, gtt_list) { |
| 943 | if (obj->pin_count == 0) |
| 944 | continue; |
| 945 | |
| 946 | capture_bo(err++, obj); |
| 947 | if (++i == count) |
| 948 | break; |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 949 | } |
| 950 | |
| 951 | return i; |
| 952 | } |
| 953 | |
Chris Wilson | 748ebc6 | 2010-10-24 10:28:47 +0100 | [diff] [blame] | 954 | static void i915_gem_record_fences(struct drm_device *dev, |
| 955 | struct drm_i915_error_state *error) |
| 956 | { |
| 957 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 958 | int i; |
| 959 | |
| 960 | /* Fences */ |
| 961 | switch (INTEL_INFO(dev)->gen) { |
Daniel Vetter | 775d17b | 2011-10-09 21:52:01 +0200 | [diff] [blame] | 962 | case 7: |
Chris Wilson | 748ebc6 | 2010-10-24 10:28:47 +0100 | [diff] [blame] | 963 | case 6: |
| 964 | for (i = 0; i < 16; i++) |
| 965 | error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); |
| 966 | break; |
| 967 | case 5: |
| 968 | case 4: |
| 969 | for (i = 0; i < 16; i++) |
| 970 | error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); |
| 971 | break; |
| 972 | case 3: |
| 973 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 974 | for (i = 0; i < 8; i++) |
| 975 | error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); |
| 976 | case 2: |
| 977 | for (i = 0; i < 8; i++) |
| 978 | error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); |
| 979 | break; |
| 980 | |
| 981 | } |
| 982 | } |
| 983 | |
Chris Wilson | bcfb2e2 | 2011-01-07 21:06:07 +0000 | [diff] [blame] | 984 | static struct drm_i915_error_object * |
| 985 | i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, |
| 986 | struct intel_ring_buffer *ring) |
| 987 | { |
| 988 | struct drm_i915_gem_object *obj; |
| 989 | u32 seqno; |
| 990 | |
| 991 | if (!ring->get_seqno) |
| 992 | return NULL; |
| 993 | |
| 994 | seqno = ring->get_seqno(ring); |
| 995 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { |
| 996 | if (obj->ring != ring) |
| 997 | continue; |
| 998 | |
Chris Wilson | c37d9a5 | 2011-01-12 20:33:01 +0000 | [diff] [blame] | 999 | if (i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
Chris Wilson | bcfb2e2 | 2011-01-07 21:06:07 +0000 | [diff] [blame] | 1000 | continue; |
| 1001 | |
| 1002 | if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) |
| 1003 | continue; |
| 1004 | |
| 1005 | /* We need to copy these to an anonymous buffer as the simplest |
| 1006 | * method to avoid being overwritten by userspace. |
| 1007 | */ |
| 1008 | return i915_error_object_create(dev_priv, obj); |
| 1009 | } |
| 1010 | |
| 1011 | return NULL; |
| 1012 | } |
| 1013 | |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 1014 | static void i915_record_ring_state(struct drm_device *dev, |
| 1015 | struct drm_i915_error_state *error, |
| 1016 | struct intel_ring_buffer *ring) |
| 1017 | { |
| 1018 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1019 | |
Daniel Vetter | 33f3f51 | 2011-12-14 13:57:39 +0100 | [diff] [blame] | 1020 | if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | 33f3f51 | 2011-12-14 13:57:39 +0100 | [diff] [blame] | 1021 | error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring)); |
Daniel Vetter | 7e3b873 | 2012-02-01 22:26:45 +0100 | [diff] [blame] | 1022 | error->semaphore_mboxes[ring->id][0] |
| 1023 | = I915_READ(RING_SYNC_0(ring->mmio_base)); |
| 1024 | error->semaphore_mboxes[ring->id][1] |
| 1025 | = I915_READ(RING_SYNC_1(ring->mmio_base)); |
Daniel Vetter | 33f3f51 | 2011-12-14 13:57:39 +0100 | [diff] [blame] | 1026 | } |
Daniel Vetter | c1cd90e | 2011-12-14 13:57:02 +0100 | [diff] [blame] | 1027 | |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 1028 | if (INTEL_INFO(dev)->gen >= 4) { |
Daniel Vetter | 9d2f41f | 2012-04-02 21:41:45 +0200 | [diff] [blame] | 1029 | error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base)); |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 1030 | error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base)); |
| 1031 | error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base)); |
| 1032 | error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base)); |
Daniel Vetter | c1cd90e | 2011-12-14 13:57:02 +0100 | [diff] [blame] | 1033 | error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base)); |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 1034 | if (ring->id == RCS) { |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 1035 | error->instdone1 = I915_READ(INSTDONE1); |
| 1036 | error->bbaddr = I915_READ64(BB_ADDR); |
| 1037 | } |
| 1038 | } else { |
Daniel Vetter | 9d2f41f | 2012-04-02 21:41:45 +0200 | [diff] [blame] | 1039 | error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX); |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 1040 | error->ipeir[ring->id] = I915_READ(IPEIR); |
| 1041 | error->ipehr[ring->id] = I915_READ(IPEHR); |
| 1042 | error->instdone[ring->id] = I915_READ(INSTDONE); |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 1043 | } |
| 1044 | |
Daniel Vetter | c1cd90e | 2011-12-14 13:57:02 +0100 | [diff] [blame] | 1045 | error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base)); |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 1046 | error->seqno[ring->id] = ring->get_seqno(ring); |
| 1047 | error->acthd[ring->id] = intel_ring_get_active_head(ring); |
Daniel Vetter | c1cd90e | 2011-12-14 13:57:02 +0100 | [diff] [blame] | 1048 | error->head[ring->id] = I915_READ_HEAD(ring); |
| 1049 | error->tail[ring->id] = I915_READ_TAIL(ring); |
Daniel Vetter | 7e3b873 | 2012-02-01 22:26:45 +0100 | [diff] [blame] | 1050 | |
| 1051 | error->cpu_ring_head[ring->id] = ring->head; |
| 1052 | error->cpu_ring_tail[ring->id] = ring->tail; |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 1053 | } |
| 1054 | |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 1055 | static void i915_gem_record_rings(struct drm_device *dev, |
| 1056 | struct drm_i915_error_state *error) |
| 1057 | { |
| 1058 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1059 | struct drm_i915_gem_request *request; |
| 1060 | int i, count; |
| 1061 | |
| 1062 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 1063 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; |
| 1064 | |
| 1065 | if (ring->obj == NULL) |
| 1066 | continue; |
| 1067 | |
| 1068 | i915_record_ring_state(dev, error, ring); |
| 1069 | |
| 1070 | error->ring[i].batchbuffer = |
| 1071 | i915_error_first_batchbuffer(dev_priv, ring); |
| 1072 | |
| 1073 | error->ring[i].ringbuffer = |
| 1074 | i915_error_object_create(dev_priv, ring->obj); |
| 1075 | |
| 1076 | count = 0; |
| 1077 | list_for_each_entry(request, &ring->request_list, list) |
| 1078 | count++; |
| 1079 | |
| 1080 | error->ring[i].num_requests = count; |
| 1081 | error->ring[i].requests = |
| 1082 | kmalloc(count*sizeof(struct drm_i915_error_request), |
| 1083 | GFP_ATOMIC); |
| 1084 | if (error->ring[i].requests == NULL) { |
| 1085 | error->ring[i].num_requests = 0; |
| 1086 | continue; |
| 1087 | } |
| 1088 | |
| 1089 | count = 0; |
| 1090 | list_for_each_entry(request, &ring->request_list, list) { |
| 1091 | struct drm_i915_error_request *erq; |
| 1092 | |
| 1093 | erq = &error->ring[i].requests[count++]; |
| 1094 | erq->seqno = request->seqno; |
| 1095 | erq->jiffies = request->emitted_jiffies; |
Chris Wilson | ee4f42b | 2012-02-15 11:25:38 +0000 | [diff] [blame] | 1096 | erq->tail = request->tail; |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 1097 | } |
| 1098 | } |
| 1099 | } |
| 1100 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1101 | /** |
| 1102 | * i915_capture_error_state - capture an error record for later analysis |
| 1103 | * @dev: drm device |
| 1104 | * |
| 1105 | * Should be called when an error is detected (either a hang or an error |
| 1106 | * interrupt) to capture error state from the time of the error. Fills |
| 1107 | * out a structure which becomes available in debugfs for user level tools |
| 1108 | * to pick up. |
| 1109 | */ |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1110 | static void i915_capture_error_state(struct drm_device *dev) |
| 1111 | { |
| 1112 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1113 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1114 | struct drm_i915_error_state *error; |
| 1115 | unsigned long flags; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1116 | int i, pipe; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1117 | |
| 1118 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1119 | error = dev_priv->first_error; |
| 1120 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
| 1121 | if (error) |
| 1122 | return; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1123 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1124 | /* Account for pipe specific data like PIPE*STAT */ |
Daniel Vetter | 33f3f51 | 2011-12-14 13:57:39 +0100 | [diff] [blame] | 1125 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1126 | if (!error) { |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1127 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); |
| 1128 | return; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1129 | } |
| 1130 | |
Chris Wilson | b6f7833 | 2011-02-01 14:15:55 +0000 | [diff] [blame] | 1131 | DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n", |
| 1132 | dev->primary->index); |
Chris Wilson | 2fa772f | 2010-10-01 13:23:27 +0100 | [diff] [blame] | 1133 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1134 | error->eir = I915_READ(EIR); |
| 1135 | error->pgtbl_er = I915_READ(PGTBL_ER); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1136 | for_each_pipe(pipe) |
| 1137 | error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 1138 | |
Daniel Vetter | 33f3f51 | 2011-12-14 13:57:39 +0100 | [diff] [blame] | 1139 | if (INTEL_INFO(dev)->gen >= 6) { |
Chris Wilson | f406839 | 2010-10-27 20:36:41 +0100 | [diff] [blame] | 1140 | error->error = I915_READ(ERROR_GEN6); |
Daniel Vetter | 33f3f51 | 2011-12-14 13:57:39 +0100 | [diff] [blame] | 1141 | error->done_reg = I915_READ(DONE_REG); |
| 1142 | } |
Chris Wilson | add354d | 2010-10-29 19:00:51 +0100 | [diff] [blame] | 1143 | |
Chris Wilson | 748ebc6 | 2010-10-24 10:28:47 +0100 | [diff] [blame] | 1144 | i915_gem_record_fences(dev, error); |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 1145 | i915_gem_record_rings(dev, error); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1146 | |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 1147 | /* Record buffers on the active and pinned lists. */ |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1148 | error->active_bo = NULL; |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 1149 | error->pinned_bo = NULL; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1150 | |
Chris Wilson | bcfb2e2 | 2011-01-07 21:06:07 +0000 | [diff] [blame] | 1151 | i = 0; |
| 1152 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) |
| 1153 | i++; |
| 1154 | error->active_bo_count = i; |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 1155 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) |
| 1156 | if (obj->pin_count) |
| 1157 | i++; |
Chris Wilson | bcfb2e2 | 2011-01-07 21:06:07 +0000 | [diff] [blame] | 1158 | error->pinned_bo_count = i - error->active_bo_count; |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 1159 | |
Chris Wilson | 8e934db | 2011-01-24 12:34:00 +0000 | [diff] [blame] | 1160 | error->active_bo = NULL; |
| 1161 | error->pinned_bo = NULL; |
Chris Wilson | bcfb2e2 | 2011-01-07 21:06:07 +0000 | [diff] [blame] | 1162 | if (i) { |
| 1163 | error->active_bo = kmalloc(sizeof(*error->active_bo)*i, |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1164 | GFP_ATOMIC); |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 1165 | if (error->active_bo) |
| 1166 | error->pinned_bo = |
| 1167 | error->active_bo + error->active_bo_count; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1168 | } |
| 1169 | |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 1170 | if (error->active_bo) |
| 1171 | error->active_bo_count = |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 1172 | capture_active_bo(error->active_bo, |
| 1173 | error->active_bo_count, |
| 1174 | &dev_priv->mm.active_list); |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 1175 | |
| 1176 | if (error->pinned_bo) |
| 1177 | error->pinned_bo_count = |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 1178 | capture_pinned_bo(error->pinned_bo, |
| 1179 | error->pinned_bo_count, |
| 1180 | &dev_priv->mm.gtt_list); |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 1181 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1182 | do_gettimeofday(&error->time); |
| 1183 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1184 | error->overlay = intel_overlay_capture_error_state(dev); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 1185 | error->display = intel_display_capture_error_state(dev); |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1186 | |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1187 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
| 1188 | if (dev_priv->first_error == NULL) { |
| 1189 | dev_priv->first_error = error; |
| 1190 | error = NULL; |
| 1191 | } |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1192 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1193 | |
| 1194 | if (error) |
| 1195 | i915_error_state_free(dev, error); |
| 1196 | } |
| 1197 | |
| 1198 | void i915_destroy_error_state(struct drm_device *dev) |
| 1199 | { |
| 1200 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1201 | struct drm_i915_error_state *error; |
Ben Widawsky | 6dc0e81 | 2012-01-23 15:30:02 -0800 | [diff] [blame] | 1202 | unsigned long flags; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1203 | |
Ben Widawsky | 6dc0e81 | 2012-01-23 15:30:02 -0800 | [diff] [blame] | 1204 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1205 | error = dev_priv->first_error; |
| 1206 | dev_priv->first_error = NULL; |
Ben Widawsky | 6dc0e81 | 2012-01-23 15:30:02 -0800 | [diff] [blame] | 1207 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 1208 | |
| 1209 | if (error) |
| 1210 | i915_error_state_free(dev, error); |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1211 | } |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 1212 | #else |
| 1213 | #define i915_capture_error_state(x) |
| 1214 | #endif |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1215 | |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 1216 | static void i915_report_and_clear_eir(struct drm_device *dev) |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1217 | { |
| 1218 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1219 | u32 eir = I915_READ(EIR); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1220 | int pipe; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1221 | |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 1222 | if (!eir) |
| 1223 | return; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1224 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1225 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1226 | |
| 1227 | if (IS_G4X(dev)) { |
| 1228 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { |
| 1229 | u32 ipeir = I915_READ(IPEIR_I965); |
| 1230 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1231 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
| 1232 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); |
| 1233 | pr_err(" INSTDONE: 0x%08x\n", |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1234 | I915_READ(INSTDONE_I965)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1235 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
| 1236 | pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1)); |
| 1237 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1238 | I915_WRITE(IPEIR_I965, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1239 | POSTING_READ(IPEIR_I965); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1240 | } |
| 1241 | if (eir & GM45_ERROR_PAGE_TABLE) { |
| 1242 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1243 | pr_err("page table error\n"); |
| 1244 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1245 | I915_WRITE(PGTBL_ER, pgtbl_err); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1246 | POSTING_READ(PGTBL_ER); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1247 | } |
| 1248 | } |
| 1249 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1250 | if (!IS_GEN2(dev)) { |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1251 | if (eir & I915_ERROR_PAGE_TABLE) { |
| 1252 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1253 | pr_err("page table error\n"); |
| 1254 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1255 | I915_WRITE(PGTBL_ER, pgtbl_err); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1256 | POSTING_READ(PGTBL_ER); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1257 | } |
| 1258 | } |
| 1259 | |
| 1260 | if (eir & I915_ERROR_MEMORY_REFRESH) { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1261 | pr_err("memory refresh error:\n"); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1262 | for_each_pipe(pipe) |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1263 | pr_err("pipe %c stat: 0x%08x\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1264 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1265 | /* pipestat has already been acked */ |
| 1266 | } |
| 1267 | if (eir & I915_ERROR_INSTRUCTION) { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1268 | pr_err("instruction error\n"); |
| 1269 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1270 | if (INTEL_INFO(dev)->gen < 4) { |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1271 | u32 ipeir = I915_READ(IPEIR); |
| 1272 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1273 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
| 1274 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); |
| 1275 | pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE)); |
| 1276 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1277 | I915_WRITE(IPEIR, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1278 | POSTING_READ(IPEIR); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1279 | } else { |
| 1280 | u32 ipeir = I915_READ(IPEIR_I965); |
| 1281 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1282 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
| 1283 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); |
| 1284 | pr_err(" INSTDONE: 0x%08x\n", |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1285 | I915_READ(INSTDONE_I965)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1286 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
| 1287 | pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1)); |
| 1288 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1289 | I915_WRITE(IPEIR_I965, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1290 | POSTING_READ(IPEIR_I965); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1291 | } |
| 1292 | } |
| 1293 | |
| 1294 | I915_WRITE(EIR, eir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1295 | POSTING_READ(EIR); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1296 | eir = I915_READ(EIR); |
| 1297 | if (eir) { |
| 1298 | /* |
| 1299 | * some errors might have become stuck, |
| 1300 | * mask them. |
| 1301 | */ |
| 1302 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); |
| 1303 | I915_WRITE(EMR, I915_READ(EMR) | eir); |
| 1304 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 1305 | } |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 1306 | } |
| 1307 | |
| 1308 | /** |
| 1309 | * i915_handle_error - handle an error interrupt |
| 1310 | * @dev: drm device |
| 1311 | * |
| 1312 | * Do some basic checking of regsiter state at error interrupt time and |
| 1313 | * dump it to the syslog. Also call i915_capture_error_state() to make |
| 1314 | * sure we get a record and make it available in debugfs. Fire a uevent |
| 1315 | * so userspace knows something bad happened (should trigger collection |
| 1316 | * of a ring dump etc.). |
| 1317 | */ |
Chris Wilson | 527f9e9 | 2010-11-11 01:16:58 +0000 | [diff] [blame] | 1318 | void i915_handle_error(struct drm_device *dev, bool wedged) |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 1319 | { |
| 1320 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1321 | |
| 1322 | i915_capture_error_state(dev); |
| 1323 | i915_report_and_clear_eir(dev); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1324 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1325 | if (wedged) { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 1326 | INIT_COMPLETION(dev_priv->error_completion); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1327 | atomic_set(&dev_priv->mm.wedged, 1); |
| 1328 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 1329 | /* |
| 1330 | * Wakeup waiting processes so they don't hang |
| 1331 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1332 | wake_up_all(&dev_priv->ring[RCS].irq_queue); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1333 | if (HAS_BSD(dev)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1334 | wake_up_all(&dev_priv->ring[VCS].irq_queue); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1335 | if (HAS_BLT(dev)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1336 | wake_up_all(&dev_priv->ring[BCS].irq_queue); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 1337 | } |
| 1338 | |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1339 | queue_work(dev_priv->wq, &dev_priv->error_work); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1340 | } |
| 1341 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1342 | static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
| 1343 | { |
| 1344 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1345 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 1346 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1347 | struct drm_i915_gem_object *obj; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1348 | struct intel_unpin_work *work; |
| 1349 | unsigned long flags; |
| 1350 | bool stall_detected; |
| 1351 | |
| 1352 | /* Ignore early vblank irqs */ |
| 1353 | if (intel_crtc == NULL) |
| 1354 | return; |
| 1355 | |
| 1356 | spin_lock_irqsave(&dev->event_lock, flags); |
| 1357 | work = intel_crtc->unpin_work; |
| 1358 | |
| 1359 | if (work == NULL || work->pending || !work->enable_stall_check) { |
| 1360 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ |
| 1361 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 1362 | return; |
| 1363 | } |
| 1364 | |
| 1365 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1366 | obj = work->pending_flip_obj; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1367 | if (INTEL_INFO(dev)->gen >= 4) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1368 | int dspsurf = DSPSURF(intel_crtc->plane); |
Armin Reese | 446f254 | 2012-03-30 16:20:16 -0700 | [diff] [blame] | 1369 | stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == |
| 1370 | obj->gtt_offset; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1371 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1372 | int dspaddr = DSPADDR(intel_crtc->plane); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1373 | stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 1374 | crtc->y * crtc->fb->pitches[0] + |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1375 | crtc->x * crtc->fb->bits_per_pixel/8); |
| 1376 | } |
| 1377 | |
| 1378 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 1379 | |
| 1380 | if (stall_detected) { |
| 1381 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); |
| 1382 | intel_prepare_page_flip(dev, intel_crtc->plane); |
| 1383 | } |
| 1384 | } |
| 1385 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 1386 | static int i915_emit_irq(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1387 | { |
| 1388 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1389 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1390 | |
| 1391 | i915_kernel_lost_context(dev); |
| 1392 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 1393 | DRM_DEBUG_DRIVER("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1394 | |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 1395 | dev_priv->counter++; |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 1396 | if (dev_priv->counter > 0x7FFFFFFFUL) |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 1397 | dev_priv->counter = 1; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1398 | if (master_priv->sarea_priv) |
| 1399 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 1400 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1401 | if (BEGIN_LP_RING(4) == 0) { |
| 1402 | OUT_RING(MI_STORE_DWORD_INDEX); |
| 1403 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 1404 | OUT_RING(dev_priv->counter); |
| 1405 | OUT_RING(MI_USER_INTERRUPT); |
| 1406 | ADVANCE_LP_RING(); |
| 1407 | } |
Dave Airlie | bc5f452 | 2007-11-05 12:50:58 +1000 | [diff] [blame] | 1408 | |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 1409 | return dev_priv->counter; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1410 | } |
| 1411 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1412 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1413 | { |
| 1414 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1415 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1416 | int ret = 0; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1417 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1418 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 1419 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1420 | READ_BREADCRUMB(dev_priv)); |
| 1421 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1422 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1423 | if (master_priv->sarea_priv) |
| 1424 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1425 | return 0; |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1426 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1427 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1428 | if (master_priv->sarea_priv) |
| 1429 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1430 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1431 | if (ring->irq_get(ring)) { |
| 1432 | DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ, |
| 1433 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
| 1434 | ring->irq_put(ring); |
Chris Wilson | 5a9a8d1 | 2011-01-23 13:03:24 +0000 | [diff] [blame] | 1435 | } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) |
| 1436 | ret = -EBUSY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1437 | |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1438 | if (ret == -EBUSY) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1439 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1440 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
| 1441 | } |
| 1442 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 1443 | return ret; |
| 1444 | } |
| 1445 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1446 | /* Needs the lock as it touches the ring. |
| 1447 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1448 | int i915_irq_emit(struct drm_device *dev, void *data, |
| 1449 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1450 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1451 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1452 | drm_i915_irq_emit_t *emit = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1453 | int result; |
| 1454 | |
Daniel Vetter | cd9d4e9 | 2012-04-24 08:29:42 +0200 | [diff] [blame] | 1455 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 1456 | return -ENODEV; |
| 1457 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1458 | if (!dev_priv || !LP_RING(dev_priv)->virtual_start) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1459 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1460 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1461 | } |
Eric Anholt | 299eb93 | 2009-02-24 22:14:12 -0800 | [diff] [blame] | 1462 | |
| 1463 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
| 1464 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 1465 | mutex_lock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1466 | result = i915_emit_irq(dev); |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 1467 | mutex_unlock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1468 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1469 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1470 | DRM_ERROR("copy_to_user\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1471 | return -EFAULT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1472 | } |
| 1473 | |
| 1474 | return 0; |
| 1475 | } |
| 1476 | |
| 1477 | /* Doesn't need the hardware lock. |
| 1478 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1479 | int i915_irq_wait(struct drm_device *dev, void *data, |
| 1480 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1481 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1482 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1483 | drm_i915_irq_wait_t *irqwait = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1484 | |
Daniel Vetter | cd9d4e9 | 2012-04-24 08:29:42 +0200 | [diff] [blame] | 1485 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 1486 | return -ENODEV; |
| 1487 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1488 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1489 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1490 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1491 | } |
| 1492 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1493 | return i915_wait_irq(dev, irqwait->irq_seq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1494 | } |
| 1495 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 1496 | /* Called from drm generic code, passed 'crtc' which |
| 1497 | * we use as a pipe index |
| 1498 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1499 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1500 | { |
| 1501 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1502 | unsigned long irqflags; |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 1503 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1504 | if (!i915_pipe_enabled(dev, pipe)) |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 1505 | return -EINVAL; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1506 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1507 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1508 | if (INTEL_INFO(dev)->gen >= 4) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1509 | i915_enable_pipestat(dev_priv, pipe, |
| 1510 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1511 | else |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1512 | i915_enable_pipestat(dev_priv, pipe, |
| 1513 | PIPE_VBLANK_INTERRUPT_ENABLE); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 1514 | |
| 1515 | /* maintain vblank delivery even in deep C-states */ |
| 1516 | if (dev_priv->info->gen == 3) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 1517 | I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1518 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 1519 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1520 | return 0; |
| 1521 | } |
| 1522 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1523 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1524 | { |
| 1525 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1526 | unsigned long irqflags; |
| 1527 | |
| 1528 | if (!i915_pipe_enabled(dev, pipe)) |
| 1529 | return -EINVAL; |
| 1530 | |
| 1531 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 1532 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1533 | DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1534 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1535 | |
| 1536 | return 0; |
| 1537 | } |
| 1538 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1539 | static int ivybridge_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1540 | { |
| 1541 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1542 | unsigned long irqflags; |
| 1543 | |
| 1544 | if (!i915_pipe_enabled(dev, pipe)) |
| 1545 | return -EINVAL; |
| 1546 | |
| 1547 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 1548 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? |
| 1549 | DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); |
| 1550 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1551 | |
| 1552 | return 0; |
| 1553 | } |
| 1554 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1555 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
| 1556 | { |
| 1557 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1558 | unsigned long irqflags; |
| 1559 | u32 dpfl, imr; |
| 1560 | |
| 1561 | if (!i915_pipe_enabled(dev, pipe)) |
| 1562 | return -EINVAL; |
| 1563 | |
| 1564 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 1565 | dpfl = I915_READ(VLV_DPFLIPSTAT); |
| 1566 | imr = I915_READ(VLV_IMR); |
| 1567 | if (pipe == 0) { |
| 1568 | dpfl |= PIPEA_VBLANK_INT_EN; |
| 1569 | imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
| 1570 | } else { |
| 1571 | dpfl |= PIPEA_VBLANK_INT_EN; |
| 1572 | imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
| 1573 | } |
| 1574 | I915_WRITE(VLV_DPFLIPSTAT, dpfl); |
| 1575 | I915_WRITE(VLV_IMR, imr); |
| 1576 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1577 | |
| 1578 | return 0; |
| 1579 | } |
| 1580 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 1581 | /* Called from drm generic code, passed 'crtc' which |
| 1582 | * we use as a pipe index |
| 1583 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1584 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1585 | { |
| 1586 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1587 | unsigned long irqflags; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1588 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1589 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 1590 | if (dev_priv->info->gen == 3) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 1591 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 1592 | |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1593 | i915_disable_pipestat(dev_priv, pipe, |
| 1594 | PIPE_VBLANK_INTERRUPT_ENABLE | |
| 1595 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
| 1596 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1597 | } |
| 1598 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1599 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1600 | { |
| 1601 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1602 | unsigned long irqflags; |
| 1603 | |
| 1604 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 1605 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1606 | DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1607 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1608 | } |
| 1609 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1610 | static void ivybridge_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1611 | { |
| 1612 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1613 | unsigned long irqflags; |
| 1614 | |
| 1615 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 1616 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? |
| 1617 | DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); |
| 1618 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1619 | } |
| 1620 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1621 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
| 1622 | { |
| 1623 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1624 | unsigned long irqflags; |
| 1625 | u32 dpfl, imr; |
| 1626 | |
| 1627 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 1628 | dpfl = I915_READ(VLV_DPFLIPSTAT); |
| 1629 | imr = I915_READ(VLV_IMR); |
| 1630 | if (pipe == 0) { |
| 1631 | dpfl &= ~PIPEA_VBLANK_INT_EN; |
| 1632 | imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
| 1633 | } else { |
| 1634 | dpfl &= ~PIPEB_VBLANK_INT_EN; |
| 1635 | imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
| 1636 | } |
| 1637 | I915_WRITE(VLV_IMR, imr); |
| 1638 | I915_WRITE(VLV_DPFLIPSTAT, dpfl); |
| 1639 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1640 | } |
| 1641 | |
| 1642 | |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1643 | /* Set the vblank monitor pipe |
| 1644 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1645 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
| 1646 | struct drm_file *file_priv) |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1647 | { |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1648 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1649 | |
Daniel Vetter | cd9d4e9 | 2012-04-24 08:29:42 +0200 | [diff] [blame] | 1650 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 1651 | return -ENODEV; |
| 1652 | |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1653 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1654 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1655 | return -EINVAL; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1656 | } |
| 1657 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | 5b51694 | 2006-10-25 00:08:23 +1000 | [diff] [blame] | 1658 | return 0; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1659 | } |
| 1660 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1661 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
| 1662 | struct drm_file *file_priv) |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1663 | { |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1664 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1665 | drm_i915_vblank_pipe_t *pipe = data; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1666 | |
Daniel Vetter | cd9d4e9 | 2012-04-24 08:29:42 +0200 | [diff] [blame] | 1667 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 1668 | return -ENODEV; |
| 1669 | |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1670 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1671 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1672 | return -EINVAL; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1673 | } |
| 1674 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1675 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1676 | |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 1677 | return 0; |
| 1678 | } |
| 1679 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 1680 | /** |
| 1681 | * Schedule buffer swap at given vertical blank. |
| 1682 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1683 | int i915_vblank_swap(struct drm_device *dev, void *data, |
| 1684 | struct drm_file *file_priv) |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 1685 | { |
Eric Anholt | bd95e0a | 2008-11-04 12:01:24 -0800 | [diff] [blame] | 1686 | /* The delayed swap mechanism was fundamentally racy, and has been |
| 1687 | * removed. The model was that the client requested a delayed flip/swap |
| 1688 | * from the kernel, then waited for vblank before continuing to perform |
| 1689 | * rendering. The problem was that the kernel might wake the client |
| 1690 | * up before it dispatched the vblank swap (since the lock has to be |
| 1691 | * held while touching the ringbuffer), in which case the client would |
| 1692 | * clear and start the next frame before the swap occurred, and |
| 1693 | * flicker would occur in addition to likely missing the vblank. |
| 1694 | * |
| 1695 | * In the absence of this ioctl, userland falls back to a correct path |
| 1696 | * of waiting for a vblank, then dispatching the swap on its own. |
| 1697 | * Context switching to userland and back is plenty fast enough for |
| 1698 | * meeting the requirements of vblank swapping. |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1699 | */ |
Eric Anholt | bd95e0a | 2008-11-04 12:01:24 -0800 | [diff] [blame] | 1700 | return -EINVAL; |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 1701 | } |
| 1702 | |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1703 | static u32 |
| 1704 | ring_last_seqno(struct intel_ring_buffer *ring) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1705 | { |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1706 | return list_entry(ring->request_list.prev, |
| 1707 | struct drm_i915_gem_request, list)->seqno; |
| 1708 | } |
| 1709 | |
| 1710 | static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) |
| 1711 | { |
| 1712 | if (list_empty(&ring->request_list) || |
| 1713 | i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) { |
| 1714 | /* Issue a wake-up to catch stuck h/w. */ |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 1715 | if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) { |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1716 | DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n", |
| 1717 | ring->name, |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 1718 | ring->waiting_seqno, |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1719 | ring->get_seqno(ring)); |
| 1720 | wake_up_all(&ring->irq_queue); |
| 1721 | *err = true; |
| 1722 | } |
| 1723 | return true; |
| 1724 | } |
| 1725 | return false; |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1726 | } |
| 1727 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1728 | static bool kick_ring(struct intel_ring_buffer *ring) |
| 1729 | { |
| 1730 | struct drm_device *dev = ring->dev; |
| 1731 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1732 | u32 tmp = I915_READ_CTL(ring); |
| 1733 | if (tmp & RING_WAIT) { |
| 1734 | DRM_ERROR("Kicking stuck wait on %s\n", |
| 1735 | ring->name); |
| 1736 | I915_WRITE_CTL(ring, tmp); |
| 1737 | return true; |
| 1738 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1739 | return false; |
| 1740 | } |
| 1741 | |
Chris Wilson | d1e61e7 | 2012-04-10 17:00:41 +0100 | [diff] [blame] | 1742 | static bool i915_hangcheck_hung(struct drm_device *dev) |
| 1743 | { |
| 1744 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1745 | |
| 1746 | if (dev_priv->hangcheck_count++ > 1) { |
| 1747 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); |
| 1748 | i915_handle_error(dev, true); |
| 1749 | |
| 1750 | if (!IS_GEN2(dev)) { |
| 1751 | /* Is the chip hanging on a WAIT_FOR_EVENT? |
| 1752 | * If so we can simply poke the RB_WAIT bit |
| 1753 | * and break the hang. This should work on |
| 1754 | * all but the second generation chipsets. |
| 1755 | */ |
| 1756 | if (kick_ring(&dev_priv->ring[RCS])) |
| 1757 | return false; |
| 1758 | |
| 1759 | if (HAS_BSD(dev) && kick_ring(&dev_priv->ring[VCS])) |
| 1760 | return false; |
| 1761 | |
| 1762 | if (HAS_BLT(dev) && kick_ring(&dev_priv->ring[BCS])) |
| 1763 | return false; |
| 1764 | } |
| 1765 | |
| 1766 | return true; |
| 1767 | } |
| 1768 | |
| 1769 | return false; |
| 1770 | } |
| 1771 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1772 | /** |
| 1773 | * This is called when the chip hasn't reported back with completed |
| 1774 | * batchbuffers in a long time. The first time this is called we simply record |
| 1775 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses |
| 1776 | * again, we assume the chip is wedged and try to fix it. |
| 1777 | */ |
| 1778 | void i915_hangcheck_elapsed(unsigned long data) |
| 1779 | { |
| 1780 | struct drm_device *dev = (struct drm_device *)data; |
| 1781 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 097354e | 2011-11-27 18:58:17 +0100 | [diff] [blame] | 1782 | uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt; |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1783 | bool err = false; |
| 1784 | |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 1785 | if (!i915_enable_hangcheck) |
| 1786 | return; |
| 1787 | |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1788 | /* If all work is done then ACTHD clearly hasn't advanced. */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1789 | if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) && |
| 1790 | i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) && |
| 1791 | i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) { |
Chris Wilson | d1e61e7 | 2012-04-10 17:00:41 +0100 | [diff] [blame] | 1792 | if (err) { |
| 1793 | if (i915_hangcheck_hung(dev)) |
| 1794 | return; |
| 1795 | |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1796 | goto repeat; |
Chris Wilson | d1e61e7 | 2012-04-10 17:00:41 +0100 | [diff] [blame] | 1797 | } |
| 1798 | |
| 1799 | dev_priv->hangcheck_count = 0; |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1800 | return; |
| 1801 | } |
Eric Anholt | b9201c1 | 2010-01-08 14:25:16 -0800 | [diff] [blame] | 1802 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1803 | if (INTEL_INFO(dev)->gen < 4) { |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1804 | instdone = I915_READ(INSTDONE); |
| 1805 | instdone1 = 0; |
| 1806 | } else { |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1807 | instdone = I915_READ(INSTDONE_I965); |
| 1808 | instdone1 = I915_READ(INSTDONE1); |
| 1809 | } |
Daniel Vetter | 097354e | 2011-11-27 18:58:17 +0100 | [diff] [blame] | 1810 | acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]); |
| 1811 | acthd_bsd = HAS_BSD(dev) ? |
| 1812 | intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0; |
| 1813 | acthd_blt = HAS_BLT(dev) ? |
| 1814 | intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0; |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1815 | |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1816 | if (dev_priv->last_acthd == acthd && |
Daniel Vetter | 097354e | 2011-11-27 18:58:17 +0100 | [diff] [blame] | 1817 | dev_priv->last_acthd_bsd == acthd_bsd && |
| 1818 | dev_priv->last_acthd_blt == acthd_blt && |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1819 | dev_priv->last_instdone == instdone && |
| 1820 | dev_priv->last_instdone1 == instdone1) { |
Chris Wilson | d1e61e7 | 2012-04-10 17:00:41 +0100 | [diff] [blame] | 1821 | if (i915_hangcheck_hung(dev)) |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1822 | return; |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1823 | } else { |
| 1824 | dev_priv->hangcheck_count = 0; |
| 1825 | |
| 1826 | dev_priv->last_acthd = acthd; |
Daniel Vetter | 097354e | 2011-11-27 18:58:17 +0100 | [diff] [blame] | 1827 | dev_priv->last_acthd_bsd = acthd_bsd; |
| 1828 | dev_priv->last_acthd_blt = acthd_blt; |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 1829 | dev_priv->last_instdone = instdone; |
| 1830 | dev_priv->last_instdone1 = instdone1; |
| 1831 | } |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1832 | |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1833 | repeat: |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1834 | /* Reset timer case chip hangs without another request being added */ |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1835 | mod_timer(&dev_priv->hangcheck_timer, |
| 1836 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1837 | } |
| 1838 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1839 | /* drm_dma.h hooks |
| 1840 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1841 | static void ironlake_irq_preinstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1842 | { |
| 1843 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1844 | |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 1845 | atomic_set(&dev_priv->irq_received, 0); |
| 1846 | |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 1847 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1848 | I915_WRITE(HWSTAM, 0xeffe); |
Daniel Vetter | bdfcdb6 | 2012-01-05 01:05:26 +0100 | [diff] [blame] | 1849 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1850 | /* XXX hotplug from PCH */ |
| 1851 | |
| 1852 | I915_WRITE(DEIMR, 0xffffffff); |
| 1853 | I915_WRITE(DEIER, 0x0); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1854 | POSTING_READ(DEIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1855 | |
| 1856 | /* and GT */ |
| 1857 | I915_WRITE(GTIMR, 0xffffffff); |
| 1858 | I915_WRITE(GTIER, 0x0); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1859 | POSTING_READ(GTIER); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 1860 | |
| 1861 | /* south display irq */ |
| 1862 | I915_WRITE(SDEIMR, 0xffffffff); |
| 1863 | I915_WRITE(SDEIER, 0x0); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1864 | POSTING_READ(SDEIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1865 | } |
| 1866 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1867 | static void valleyview_irq_preinstall(struct drm_device *dev) |
| 1868 | { |
| 1869 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1870 | int pipe; |
| 1871 | |
| 1872 | atomic_set(&dev_priv->irq_received, 0); |
| 1873 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1874 | /* VLV magic */ |
| 1875 | I915_WRITE(VLV_IMR, 0); |
| 1876 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); |
| 1877 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); |
| 1878 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); |
| 1879 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1880 | /* and GT */ |
| 1881 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 1882 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 1883 | I915_WRITE(GTIMR, 0xffffffff); |
| 1884 | I915_WRITE(GTIER, 0x0); |
| 1885 | POSTING_READ(GTIER); |
| 1886 | |
| 1887 | I915_WRITE(DPINVGTT, 0xff); |
| 1888 | |
| 1889 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 1890 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 1891 | for_each_pipe(pipe) |
| 1892 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
| 1893 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 1894 | I915_WRITE(VLV_IMR, 0xffffffff); |
| 1895 | I915_WRITE(VLV_IER, 0x0); |
| 1896 | POSTING_READ(VLV_IER); |
| 1897 | } |
| 1898 | |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 1899 | /* |
| 1900 | * Enable digital hotplug on the PCH, and configure the DP short pulse |
| 1901 | * duration to 2ms (which is the minimum in the Display Port spec) |
| 1902 | * |
| 1903 | * This register is the same on all known PCH chips. |
| 1904 | */ |
| 1905 | |
| 1906 | static void ironlake_enable_pch_hotplug(struct drm_device *dev) |
| 1907 | { |
| 1908 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1909 | u32 hotplug; |
| 1910 | |
| 1911 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
| 1912 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); |
| 1913 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; |
| 1914 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; |
| 1915 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; |
| 1916 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
| 1917 | } |
| 1918 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1919 | static int ironlake_irq_postinstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1920 | { |
| 1921 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1922 | /* enable kind of interrupts always enabled */ |
Jesse Barnes | 013d5aa | 2010-01-29 11:18:31 -0800 | [diff] [blame] | 1923 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
| 1924 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1925 | u32 render_irqs; |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 1926 | u32 hotplug_mask; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1927 | |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 1928 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1929 | dev_priv->irq_mask = ~display_mask; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1930 | |
| 1931 | /* should always can generate irq */ |
| 1932 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1933 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
| 1934 | I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1935 | POSTING_READ(DEIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1936 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1937 | dev_priv->gt_irq_mask = ~0; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1938 | |
| 1939 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1940 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1941 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1942 | if (IS_GEN6(dev)) |
| 1943 | render_irqs = |
| 1944 | GT_USER_INTERRUPT | |
Ben Widawsky | e2a1e2f | 2012-03-29 19:11:26 -0700 | [diff] [blame] | 1945 | GEN6_BSD_USER_INTERRUPT | |
| 1946 | GEN6_BLITTER_USER_INTERRUPT; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1947 | else |
| 1948 | render_irqs = |
Chris Wilson | 88f23b8 | 2010-12-05 15:08:31 +0000 | [diff] [blame] | 1949 | GT_USER_INTERRUPT | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1950 | GT_PIPE_NOTIFY | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1951 | GT_BSD_USER_INTERRUPT; |
| 1952 | I915_WRITE(GTIER, render_irqs); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1953 | POSTING_READ(GTIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1954 | |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 1955 | if (HAS_PCH_CPT(dev)) { |
Chris Wilson | 9035a97 | 2011-02-16 09:36:05 +0000 | [diff] [blame] | 1956 | hotplug_mask = (SDE_CRT_HOTPLUG_CPT | |
| 1957 | SDE_PORTB_HOTPLUG_CPT | |
| 1958 | SDE_PORTC_HOTPLUG_CPT | |
| 1959 | SDE_PORTD_HOTPLUG_CPT); |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 1960 | } else { |
Chris Wilson | 9035a97 | 2011-02-16 09:36:05 +0000 | [diff] [blame] | 1961 | hotplug_mask = (SDE_CRT_HOTPLUG | |
| 1962 | SDE_PORTB_HOTPLUG | |
| 1963 | SDE_PORTC_HOTPLUG | |
| 1964 | SDE_PORTD_HOTPLUG | |
| 1965 | SDE_AUX_MASK); |
Yuanhan Liu | 2d7b836 | 2010-10-08 10:21:06 +0100 | [diff] [blame] | 1966 | } |
| 1967 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1968 | dev_priv->pch_irq_mask = ~hotplug_mask; |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 1969 | |
| 1970 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1971 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); |
| 1972 | I915_WRITE(SDEIER, hotplug_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1973 | POSTING_READ(SDEIER); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 1974 | |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 1975 | ironlake_enable_pch_hotplug(dev); |
| 1976 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1977 | if (IS_IRONLAKE_M(dev)) { |
| 1978 | /* Clear & enable PCU event interrupts */ |
| 1979 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
| 1980 | I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); |
| 1981 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
| 1982 | } |
| 1983 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1984 | return 0; |
| 1985 | } |
| 1986 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1987 | static int ivybridge_irq_postinstall(struct drm_device *dev) |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1988 | { |
| 1989 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1990 | /* enable kind of interrupts always enabled */ |
| 1991 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | |
| 1992 | DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB | |
| 1993 | DE_PLANEB_FLIP_DONE_IVB; |
| 1994 | u32 render_irqs; |
| 1995 | u32 hotplug_mask; |
| 1996 | |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1997 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
| 1998 | dev_priv->irq_mask = ~display_mask; |
| 1999 | |
| 2000 | /* should always can generate irq */ |
| 2001 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
| 2002 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
| 2003 | I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB | |
| 2004 | DE_PIPEB_VBLANK_IVB); |
| 2005 | POSTING_READ(DEIER); |
| 2006 | |
| 2007 | dev_priv->gt_irq_mask = ~0; |
| 2008 | |
| 2009 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 2010 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 2011 | |
Ben Widawsky | e2a1e2f | 2012-03-29 19:11:26 -0700 | [diff] [blame] | 2012 | render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT | |
| 2013 | GEN6_BLITTER_USER_INTERRUPT; |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2014 | I915_WRITE(GTIER, render_irqs); |
| 2015 | POSTING_READ(GTIER); |
| 2016 | |
| 2017 | hotplug_mask = (SDE_CRT_HOTPLUG_CPT | |
| 2018 | SDE_PORTB_HOTPLUG_CPT | |
| 2019 | SDE_PORTC_HOTPLUG_CPT | |
| 2020 | SDE_PORTD_HOTPLUG_CPT); |
| 2021 | dev_priv->pch_irq_mask = ~hotplug_mask; |
| 2022 | |
| 2023 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
| 2024 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); |
| 2025 | I915_WRITE(SDEIER, hotplug_mask); |
| 2026 | POSTING_READ(SDEIER); |
| 2027 | |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 2028 | ironlake_enable_pch_hotplug(dev); |
| 2029 | |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2030 | return 0; |
| 2031 | } |
| 2032 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2033 | static int valleyview_irq_postinstall(struct drm_device *dev) |
| 2034 | { |
| 2035 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2036 | u32 render_irqs; |
| 2037 | u32 enable_mask; |
| 2038 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
| 2039 | u16 msid; |
| 2040 | |
| 2041 | enable_mask = I915_DISPLAY_PORT_INTERRUPT; |
| 2042 | enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | |
| 2043 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
| 2044 | |
| 2045 | dev_priv->irq_mask = ~enable_mask; |
| 2046 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2047 | dev_priv->pipestat[0] = 0; |
| 2048 | dev_priv->pipestat[1] = 0; |
| 2049 | |
| 2050 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
| 2051 | |
| 2052 | /* Hack for broken MSIs on VLV */ |
| 2053 | pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000); |
| 2054 | pci_read_config_word(dev->pdev, 0x98, &msid); |
| 2055 | msid &= 0xff; /* mask out delivery bits */ |
| 2056 | msid |= (1<<14); |
| 2057 | pci_write_config_word(dev_priv->dev->pdev, 0x98, msid); |
| 2058 | |
| 2059 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
| 2060 | I915_WRITE(VLV_IER, enable_mask); |
| 2061 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 2062 | I915_WRITE(PIPESTAT(0), 0xffff); |
| 2063 | I915_WRITE(PIPESTAT(1), 0xffff); |
| 2064 | POSTING_READ(VLV_IER); |
| 2065 | |
| 2066 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 2067 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 2068 | |
| 2069 | render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT | |
| 2070 | GT_GEN6_BLT_CS_ERROR_INTERRUPT | |
Ben Widawsky | e2a1e2f | 2012-03-29 19:11:26 -0700 | [diff] [blame] | 2071 | GT_GEN6_BLT_USER_INTERRUPT | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2072 | GT_GEN6_BSD_USER_INTERRUPT | |
| 2073 | GT_GEN6_BSD_CS_ERROR_INTERRUPT | |
| 2074 | GT_GEN7_L3_PARITY_ERROR_INTERRUPT | |
| 2075 | GT_PIPE_NOTIFY | |
| 2076 | GT_RENDER_CS_ERROR_INTERRUPT | |
| 2077 | GT_SYNC_STATUS | |
| 2078 | GT_USER_INTERRUPT; |
| 2079 | |
| 2080 | dev_priv->gt_irq_mask = ~render_irqs; |
| 2081 | |
| 2082 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 2083 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 2084 | I915_WRITE(GTIMR, 0); |
| 2085 | I915_WRITE(GTIER, render_irqs); |
| 2086 | POSTING_READ(GTIER); |
| 2087 | |
| 2088 | /* ack & enable invalid PTE error interrupts */ |
| 2089 | #if 0 /* FIXME: add support to irq handler for checking these bits */ |
| 2090 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); |
| 2091 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); |
| 2092 | #endif |
| 2093 | |
| 2094 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
| 2095 | #if 0 /* FIXME: check register definitions; some have moved */ |
| 2096 | /* Note HDMI and DP share bits */ |
| 2097 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) |
| 2098 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; |
| 2099 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) |
| 2100 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; |
| 2101 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) |
| 2102 | hotplug_en |= HDMID_HOTPLUG_INT_EN; |
| 2103 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) |
| 2104 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; |
| 2105 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) |
| 2106 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; |
| 2107 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { |
| 2108 | hotplug_en |= CRT_HOTPLUG_INT_EN; |
| 2109 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
| 2110 | } |
| 2111 | #endif |
| 2112 | |
| 2113 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
| 2114 | |
| 2115 | return 0; |
| 2116 | } |
| 2117 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2118 | static void valleyview_irq_uninstall(struct drm_device *dev) |
| 2119 | { |
| 2120 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2121 | int pipe; |
| 2122 | |
| 2123 | if (!dev_priv) |
| 2124 | return; |
| 2125 | |
| 2126 | dev_priv->vblank_pipe = 0; |
| 2127 | |
| 2128 | for_each_pipe(pipe) |
| 2129 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
| 2130 | |
| 2131 | I915_WRITE(HWSTAM, 0xffffffff); |
| 2132 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2133 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 2134 | for_each_pipe(pipe) |
| 2135 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
| 2136 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 2137 | I915_WRITE(VLV_IMR, 0xffffffff); |
| 2138 | I915_WRITE(VLV_IER, 0x0); |
| 2139 | POSTING_READ(VLV_IER); |
| 2140 | } |
| 2141 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2142 | static void ironlake_irq_uninstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2143 | { |
| 2144 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 2145 | |
| 2146 | if (!dev_priv) |
| 2147 | return; |
| 2148 | |
| 2149 | dev_priv->vblank_pipe = 0; |
| 2150 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2151 | I915_WRITE(HWSTAM, 0xffffffff); |
| 2152 | |
| 2153 | I915_WRITE(DEIMR, 0xffffffff); |
| 2154 | I915_WRITE(DEIER, 0x0); |
| 2155 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
| 2156 | |
| 2157 | I915_WRITE(GTIMR, 0xffffffff); |
| 2158 | I915_WRITE(GTIER, 0x0); |
| 2159 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
Keith Packard | 192aac1f | 2011-09-20 10:12:44 -0700 | [diff] [blame] | 2160 | |
| 2161 | I915_WRITE(SDEIMR, 0xffffffff); |
| 2162 | I915_WRITE(SDEIER, 0x0); |
| 2163 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2164 | } |
| 2165 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2166 | static void i8xx_irq_preinstall(struct drm_device * dev) |
| 2167 | { |
| 2168 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2169 | int pipe; |
| 2170 | |
| 2171 | atomic_set(&dev_priv->irq_received, 0); |
| 2172 | |
| 2173 | for_each_pipe(pipe) |
| 2174 | I915_WRITE(PIPESTAT(pipe), 0); |
| 2175 | I915_WRITE16(IMR, 0xffff); |
| 2176 | I915_WRITE16(IER, 0x0); |
| 2177 | POSTING_READ16(IER); |
| 2178 | } |
| 2179 | |
| 2180 | static int i8xx_irq_postinstall(struct drm_device *dev) |
| 2181 | { |
| 2182 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2183 | |
| 2184 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
| 2185 | |
| 2186 | dev_priv->pipestat[0] = 0; |
| 2187 | dev_priv->pipestat[1] = 0; |
| 2188 | |
| 2189 | I915_WRITE16(EMR, |
| 2190 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
| 2191 | |
| 2192 | /* Unmask the interrupts that we always want on. */ |
| 2193 | dev_priv->irq_mask = |
| 2194 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 2195 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 2196 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 2197 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | |
| 2198 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 2199 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 2200 | |
| 2201 | I915_WRITE16(IER, |
| 2202 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 2203 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 2204 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | |
| 2205 | I915_USER_INTERRUPT); |
| 2206 | POSTING_READ16(IER); |
| 2207 | |
| 2208 | return 0; |
| 2209 | } |
| 2210 | |
| 2211 | static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS) |
| 2212 | { |
| 2213 | struct drm_device *dev = (struct drm_device *) arg; |
| 2214 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2215 | struct drm_i915_master_private *master_priv; |
| 2216 | u16 iir, new_iir; |
| 2217 | u32 pipe_stats[2]; |
| 2218 | unsigned long irqflags; |
| 2219 | int irq_received; |
| 2220 | int pipe; |
| 2221 | u16 flip_mask = |
| 2222 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 2223 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; |
| 2224 | |
| 2225 | atomic_inc(&dev_priv->irq_received); |
| 2226 | |
| 2227 | iir = I915_READ16(IIR); |
| 2228 | if (iir == 0) |
| 2229 | return IRQ_NONE; |
| 2230 | |
| 2231 | while (iir & ~flip_mask) { |
| 2232 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 2233 | * have been cleared after the pipestat interrupt was received. |
| 2234 | * It doesn't set the bit in iir again, but it still produces |
| 2235 | * interrupts (for non-MSI). |
| 2236 | */ |
| 2237 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 2238 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
| 2239 | i915_handle_error(dev, false); |
| 2240 | |
| 2241 | for_each_pipe(pipe) { |
| 2242 | int reg = PIPESTAT(pipe); |
| 2243 | pipe_stats[pipe] = I915_READ(reg); |
| 2244 | |
| 2245 | /* |
| 2246 | * Clear the PIPE*STAT regs before the IIR |
| 2247 | */ |
| 2248 | if (pipe_stats[pipe] & 0x8000ffff) { |
| 2249 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 2250 | DRM_DEBUG_DRIVER("pipe %c underrun\n", |
| 2251 | pipe_name(pipe)); |
| 2252 | I915_WRITE(reg, pipe_stats[pipe]); |
| 2253 | irq_received = 1; |
| 2254 | } |
| 2255 | } |
| 2256 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2257 | |
| 2258 | I915_WRITE16(IIR, iir & ~flip_mask); |
| 2259 | new_iir = I915_READ16(IIR); /* Flush posted writes */ |
| 2260 | |
| 2261 | if (dev->primary->master) { |
| 2262 | master_priv = dev->primary->master->driver_priv; |
| 2263 | if (master_priv->sarea_priv) |
| 2264 | master_priv->sarea_priv->last_dispatch = |
| 2265 | READ_BREADCRUMB(dev_priv); |
| 2266 | } |
| 2267 | |
| 2268 | if (iir & I915_USER_INTERRUPT) |
| 2269 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 2270 | |
| 2271 | if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS && |
| 2272 | drm_handle_vblank(dev, 0)) { |
| 2273 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { |
| 2274 | intel_prepare_page_flip(dev, 0); |
| 2275 | intel_finish_page_flip(dev, 0); |
| 2276 | flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT; |
| 2277 | } |
| 2278 | } |
| 2279 | |
| 2280 | if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS && |
| 2281 | drm_handle_vblank(dev, 1)) { |
| 2282 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { |
| 2283 | intel_prepare_page_flip(dev, 1); |
| 2284 | intel_finish_page_flip(dev, 1); |
| 2285 | flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; |
| 2286 | } |
| 2287 | } |
| 2288 | |
| 2289 | iir = new_iir; |
| 2290 | } |
| 2291 | |
| 2292 | return IRQ_HANDLED; |
| 2293 | } |
| 2294 | |
| 2295 | static void i8xx_irq_uninstall(struct drm_device * dev) |
| 2296 | { |
| 2297 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2298 | int pipe; |
| 2299 | |
| 2300 | dev_priv->vblank_pipe = 0; |
| 2301 | |
| 2302 | for_each_pipe(pipe) { |
| 2303 | /* Clear enable bits; then clear status bits */ |
| 2304 | I915_WRITE(PIPESTAT(pipe), 0); |
| 2305 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
| 2306 | } |
| 2307 | I915_WRITE16(IMR, 0xffff); |
| 2308 | I915_WRITE16(IER, 0x0); |
| 2309 | I915_WRITE16(IIR, I915_READ16(IIR)); |
| 2310 | } |
| 2311 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2312 | static void i915_irq_preinstall(struct drm_device * dev) |
| 2313 | { |
| 2314 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2315 | int pipe; |
| 2316 | |
| 2317 | atomic_set(&dev_priv->irq_received, 0); |
| 2318 | |
| 2319 | if (I915_HAS_HOTPLUG(dev)) { |
| 2320 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2321 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 2322 | } |
| 2323 | |
Chris Wilson | 00d98eb | 2012-04-24 22:59:48 +0100 | [diff] [blame] | 2324 | I915_WRITE16(HWSTAM, 0xeffe); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2325 | for_each_pipe(pipe) |
| 2326 | I915_WRITE(PIPESTAT(pipe), 0); |
| 2327 | I915_WRITE(IMR, 0xffffffff); |
| 2328 | I915_WRITE(IER, 0x0); |
| 2329 | POSTING_READ(IER); |
| 2330 | } |
| 2331 | |
| 2332 | static int i915_irq_postinstall(struct drm_device *dev) |
| 2333 | { |
| 2334 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2335 | u32 enable_mask; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2336 | |
| 2337 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
| 2338 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2339 | dev_priv->pipestat[0] = 0; |
| 2340 | dev_priv->pipestat[1] = 0; |
| 2341 | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2342 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
| 2343 | |
| 2344 | /* Unmask the interrupts that we always want on. */ |
| 2345 | dev_priv->irq_mask = |
| 2346 | ~(I915_ASLE_INTERRUPT | |
| 2347 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 2348 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 2349 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 2350 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | |
| 2351 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 2352 | |
| 2353 | enable_mask = |
| 2354 | I915_ASLE_INTERRUPT | |
| 2355 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 2356 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 2357 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | |
| 2358 | I915_USER_INTERRUPT; |
| 2359 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2360 | if (I915_HAS_HOTPLUG(dev)) { |
| 2361 | /* Enable in IER... */ |
| 2362 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; |
| 2363 | /* and unmask in IMR */ |
| 2364 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; |
| 2365 | } |
| 2366 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2367 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 2368 | I915_WRITE(IER, enable_mask); |
| 2369 | POSTING_READ(IER); |
| 2370 | |
| 2371 | if (I915_HAS_HOTPLUG(dev)) { |
| 2372 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
| 2373 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2374 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) |
| 2375 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; |
| 2376 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) |
| 2377 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; |
| 2378 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) |
| 2379 | hotplug_en |= HDMID_HOTPLUG_INT_EN; |
| 2380 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) |
| 2381 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; |
| 2382 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) |
| 2383 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; |
| 2384 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { |
| 2385 | hotplug_en |= CRT_HOTPLUG_INT_EN; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2386 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
| 2387 | } |
| 2388 | |
| 2389 | /* Ignore TV since it's buggy */ |
| 2390 | |
| 2391 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
| 2392 | } |
| 2393 | |
| 2394 | intel_opregion_enable_asle(dev); |
| 2395 | |
| 2396 | return 0; |
| 2397 | } |
| 2398 | |
| 2399 | static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS) |
| 2400 | { |
| 2401 | struct drm_device *dev = (struct drm_device *) arg; |
| 2402 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2403 | struct drm_i915_master_private *master_priv; |
Chris Wilson | 8291ee9 | 2012-04-24 22:59:47 +0100 | [diff] [blame] | 2404 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2405 | unsigned long irqflags; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2406 | u32 flip_mask = |
| 2407 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 2408 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; |
| 2409 | u32 flip[2] = { |
| 2410 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT, |
| 2411 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
| 2412 | }; |
| 2413 | int pipe, ret = IRQ_NONE; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2414 | |
| 2415 | atomic_inc(&dev_priv->irq_received); |
| 2416 | |
| 2417 | iir = I915_READ(IIR); |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2418 | do { |
| 2419 | bool irq_received = (iir & ~flip_mask) != 0; |
Chris Wilson | 8291ee9 | 2012-04-24 22:59:47 +0100 | [diff] [blame] | 2420 | bool blc_event = false; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2421 | |
| 2422 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 2423 | * have been cleared after the pipestat interrupt was received. |
| 2424 | * It doesn't set the bit in iir again, but it still produces |
| 2425 | * interrupts (for non-MSI). |
| 2426 | */ |
| 2427 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 2428 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
| 2429 | i915_handle_error(dev, false); |
| 2430 | |
| 2431 | for_each_pipe(pipe) { |
| 2432 | int reg = PIPESTAT(pipe); |
| 2433 | pipe_stats[pipe] = I915_READ(reg); |
| 2434 | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2435 | /* Clear the PIPE*STAT regs before the IIR */ |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2436 | if (pipe_stats[pipe] & 0x8000ffff) { |
| 2437 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 2438 | DRM_DEBUG_DRIVER("pipe %c underrun\n", |
| 2439 | pipe_name(pipe)); |
| 2440 | I915_WRITE(reg, pipe_stats[pipe]); |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2441 | irq_received = true; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2442 | } |
| 2443 | } |
| 2444 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2445 | |
| 2446 | if (!irq_received) |
| 2447 | break; |
| 2448 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2449 | /* Consume port. Then clear IIR or we'll miss events */ |
| 2450 | if ((I915_HAS_HOTPLUG(dev)) && |
| 2451 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { |
| 2452 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
| 2453 | |
| 2454 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
| 2455 | hotplug_status); |
| 2456 | if (hotplug_status & dev_priv->hotplug_supported_mask) |
| 2457 | queue_work(dev_priv->wq, |
| 2458 | &dev_priv->hotplug_work); |
| 2459 | |
| 2460 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2461 | POSTING_READ(PORT_HOTPLUG_STAT); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2462 | } |
| 2463 | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2464 | I915_WRITE(IIR, iir & ~flip_mask); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2465 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
| 2466 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2467 | if (iir & I915_USER_INTERRUPT) |
| 2468 | notify_ring(dev, &dev_priv->ring[RCS]); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2469 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2470 | for_each_pipe(pipe) { |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2471 | int plane = pipe; |
| 2472 | if (IS_MOBILE(dev)) |
| 2473 | plane = !plane; |
Chris Wilson | 8291ee9 | 2012-04-24 22:59:47 +0100 | [diff] [blame] | 2474 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2475 | drm_handle_vblank(dev, pipe)) { |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2476 | if (iir & flip[plane]) { |
| 2477 | intel_prepare_page_flip(dev, plane); |
| 2478 | intel_finish_page_flip(dev, pipe); |
| 2479 | flip_mask &= ~flip[plane]; |
| 2480 | } |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2481 | } |
| 2482 | |
| 2483 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
| 2484 | blc_event = true; |
| 2485 | } |
| 2486 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2487 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
| 2488 | intel_opregion_asle_intr(dev); |
| 2489 | |
| 2490 | /* With MSI, interrupts are only generated when iir |
| 2491 | * transitions from zero to nonzero. If another bit got |
| 2492 | * set while we were handling the existing iir bits, then |
| 2493 | * we would never get another interrupt. |
| 2494 | * |
| 2495 | * This is fine on non-MSI as well, as if we hit this path |
| 2496 | * we avoid exiting the interrupt handler only to generate |
| 2497 | * another one. |
| 2498 | * |
| 2499 | * Note that for MSI this could cause a stray interrupt report |
| 2500 | * if an interrupt landed in the time between writing IIR and |
| 2501 | * the posting read. This should be rare enough to never |
| 2502 | * trigger the 99% of 100,000 interrupts test for disabling |
| 2503 | * stray interrupts. |
| 2504 | */ |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2505 | ret = IRQ_HANDLED; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2506 | iir = new_iir; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2507 | } while (iir & ~flip_mask); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2508 | |
Chris Wilson | 8291ee9 | 2012-04-24 22:59:47 +0100 | [diff] [blame] | 2509 | if (dev->primary->master) { |
| 2510 | master_priv = dev->primary->master->driver_priv; |
| 2511 | if (master_priv->sarea_priv) |
| 2512 | master_priv->sarea_priv->last_dispatch = |
| 2513 | READ_BREADCRUMB(dev_priv); |
| 2514 | } |
| 2515 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2516 | return ret; |
| 2517 | } |
| 2518 | |
| 2519 | static void i915_irq_uninstall(struct drm_device * dev) |
| 2520 | { |
| 2521 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2522 | int pipe; |
| 2523 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2524 | dev_priv->vblank_pipe = 0; |
| 2525 | |
| 2526 | if (I915_HAS_HOTPLUG(dev)) { |
| 2527 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2528 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 2529 | } |
| 2530 | |
Chris Wilson | 00d98eb | 2012-04-24 22:59:48 +0100 | [diff] [blame] | 2531 | I915_WRITE16(HWSTAM, 0xffff); |
Chris Wilson | 55b3975 | 2012-04-24 22:59:49 +0100 | [diff] [blame] | 2532 | for_each_pipe(pipe) { |
| 2533 | /* Clear enable bits; then clear status bits */ |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2534 | I915_WRITE(PIPESTAT(pipe), 0); |
Chris Wilson | 55b3975 | 2012-04-24 22:59:49 +0100 | [diff] [blame] | 2535 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
| 2536 | } |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2537 | I915_WRITE(IMR, 0xffffffff); |
| 2538 | I915_WRITE(IER, 0x0); |
| 2539 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2540 | I915_WRITE(IIR, I915_READ(IIR)); |
| 2541 | } |
| 2542 | |
| 2543 | static void i965_irq_preinstall(struct drm_device * dev) |
| 2544 | { |
| 2545 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2546 | int pipe; |
| 2547 | |
| 2548 | atomic_set(&dev_priv->irq_received, 0); |
| 2549 | |
| 2550 | if (I915_HAS_HOTPLUG(dev)) { |
| 2551 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2552 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 2553 | } |
| 2554 | |
| 2555 | I915_WRITE(HWSTAM, 0xeffe); |
| 2556 | for_each_pipe(pipe) |
| 2557 | I915_WRITE(PIPESTAT(pipe), 0); |
| 2558 | I915_WRITE(IMR, 0xffffffff); |
| 2559 | I915_WRITE(IER, 0x0); |
| 2560 | POSTING_READ(IER); |
| 2561 | } |
| 2562 | |
| 2563 | static int i965_irq_postinstall(struct drm_device *dev) |
| 2564 | { |
| 2565 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame^] | 2566 | u32 enable_mask; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2567 | u32 error_mask; |
| 2568 | |
| 2569 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
| 2570 | |
| 2571 | /* Unmask the interrupts that we always want on. */ |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame^] | 2572 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
| 2573 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 2574 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 2575 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 2576 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | |
| 2577 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 2578 | |
| 2579 | enable_mask = ~dev_priv->irq_mask; |
| 2580 | enable_mask |= I915_USER_INTERRUPT; |
| 2581 | |
| 2582 | if (IS_G4X(dev)) |
| 2583 | enable_mask |= I915_BSD_USER_INTERRUPT; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2584 | |
| 2585 | dev_priv->pipestat[0] = 0; |
| 2586 | dev_priv->pipestat[1] = 0; |
| 2587 | |
| 2588 | if (I915_HAS_HOTPLUG(dev)) { |
| 2589 | /* Enable in IER... */ |
| 2590 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; |
| 2591 | /* and unmask in IMR */ |
| 2592 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; |
| 2593 | } |
| 2594 | |
| 2595 | /* |
| 2596 | * Enable some error detection, note the instruction error mask |
| 2597 | * bit is reserved, so we leave it masked. |
| 2598 | */ |
| 2599 | if (IS_G4X(dev)) { |
| 2600 | error_mask = ~(GM45_ERROR_PAGE_TABLE | |
| 2601 | GM45_ERROR_MEM_PRIV | |
| 2602 | GM45_ERROR_CP_PRIV | |
| 2603 | I915_ERROR_MEMORY_REFRESH); |
| 2604 | } else { |
| 2605 | error_mask = ~(I915_ERROR_PAGE_TABLE | |
| 2606 | I915_ERROR_MEMORY_REFRESH); |
| 2607 | } |
| 2608 | I915_WRITE(EMR, error_mask); |
| 2609 | |
| 2610 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 2611 | I915_WRITE(IER, enable_mask); |
| 2612 | POSTING_READ(IER); |
| 2613 | |
| 2614 | if (I915_HAS_HOTPLUG(dev)) { |
| 2615 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
| 2616 | |
| 2617 | /* Note HDMI and DP share bits */ |
| 2618 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) |
| 2619 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; |
| 2620 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) |
| 2621 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; |
| 2622 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) |
| 2623 | hotplug_en |= HDMID_HOTPLUG_INT_EN; |
| 2624 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) |
| 2625 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; |
| 2626 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) |
| 2627 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; |
| 2628 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { |
| 2629 | hotplug_en |= CRT_HOTPLUG_INT_EN; |
| 2630 | |
| 2631 | /* Programming the CRT detection parameters tends |
| 2632 | to generate a spurious hotplug event about three |
| 2633 | seconds later. So just do it once. |
| 2634 | */ |
| 2635 | if (IS_G4X(dev)) |
| 2636 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; |
| 2637 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
| 2638 | } |
| 2639 | |
| 2640 | /* Ignore TV since it's buggy */ |
| 2641 | |
| 2642 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
| 2643 | } |
| 2644 | |
| 2645 | intel_opregion_enable_asle(dev); |
| 2646 | |
| 2647 | return 0; |
| 2648 | } |
| 2649 | |
| 2650 | static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS) |
| 2651 | { |
| 2652 | struct drm_device *dev = (struct drm_device *) arg; |
| 2653 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2654 | struct drm_i915_master_private *master_priv; |
| 2655 | u32 iir, new_iir; |
| 2656 | u32 pipe_stats[I915_MAX_PIPES]; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2657 | unsigned long irqflags; |
| 2658 | int irq_received; |
| 2659 | int ret = IRQ_NONE, pipe; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2660 | |
| 2661 | atomic_inc(&dev_priv->irq_received); |
| 2662 | |
| 2663 | iir = I915_READ(IIR); |
| 2664 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2665 | for (;;) { |
Chris Wilson | 2c8ba29 | 2012-04-24 22:59:46 +0100 | [diff] [blame] | 2666 | bool blc_event = false; |
| 2667 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2668 | irq_received = iir != 0; |
| 2669 | |
| 2670 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 2671 | * have been cleared after the pipestat interrupt was received. |
| 2672 | * It doesn't set the bit in iir again, but it still produces |
| 2673 | * interrupts (for non-MSI). |
| 2674 | */ |
| 2675 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 2676 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
| 2677 | i915_handle_error(dev, false); |
| 2678 | |
| 2679 | for_each_pipe(pipe) { |
| 2680 | int reg = PIPESTAT(pipe); |
| 2681 | pipe_stats[pipe] = I915_READ(reg); |
| 2682 | |
| 2683 | /* |
| 2684 | * Clear the PIPE*STAT regs before the IIR |
| 2685 | */ |
| 2686 | if (pipe_stats[pipe] & 0x8000ffff) { |
| 2687 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 2688 | DRM_DEBUG_DRIVER("pipe %c underrun\n", |
| 2689 | pipe_name(pipe)); |
| 2690 | I915_WRITE(reg, pipe_stats[pipe]); |
| 2691 | irq_received = 1; |
| 2692 | } |
| 2693 | } |
| 2694 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2695 | |
| 2696 | if (!irq_received) |
| 2697 | break; |
| 2698 | |
| 2699 | ret = IRQ_HANDLED; |
| 2700 | |
| 2701 | /* Consume port. Then clear IIR or we'll miss events */ |
| 2702 | if ((I915_HAS_HOTPLUG(dev)) && |
| 2703 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { |
| 2704 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
| 2705 | |
| 2706 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
| 2707 | hotplug_status); |
| 2708 | if (hotplug_status & dev_priv->hotplug_supported_mask) |
| 2709 | queue_work(dev_priv->wq, |
| 2710 | &dev_priv->hotplug_work); |
| 2711 | |
| 2712 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
| 2713 | I915_READ(PORT_HOTPLUG_STAT); |
| 2714 | } |
| 2715 | |
| 2716 | I915_WRITE(IIR, iir); |
| 2717 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
| 2718 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2719 | if (iir & I915_USER_INTERRUPT) |
| 2720 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 2721 | if (iir & I915_BSD_USER_INTERRUPT) |
| 2722 | notify_ring(dev, &dev_priv->ring[VCS]); |
| 2723 | |
Chris Wilson | 4f7d1e7 | 2012-04-24 22:59:45 +0100 | [diff] [blame] | 2724 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2725 | intel_prepare_page_flip(dev, 0); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2726 | |
Chris Wilson | 4f7d1e7 | 2012-04-24 22:59:45 +0100 | [diff] [blame] | 2727 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2728 | intel_prepare_page_flip(dev, 1); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2729 | |
| 2730 | for_each_pipe(pipe) { |
Chris Wilson | 2c8ba29 | 2012-04-24 22:59:46 +0100 | [diff] [blame] | 2731 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2732 | drm_handle_vblank(dev, pipe)) { |
Chris Wilson | 4f7d1e7 | 2012-04-24 22:59:45 +0100 | [diff] [blame] | 2733 | i915_pageflip_stall_check(dev, pipe); |
| 2734 | intel_finish_page_flip(dev, pipe); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2735 | } |
| 2736 | |
| 2737 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
| 2738 | blc_event = true; |
| 2739 | } |
| 2740 | |
| 2741 | |
| 2742 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
| 2743 | intel_opregion_asle_intr(dev); |
| 2744 | |
| 2745 | /* With MSI, interrupts are only generated when iir |
| 2746 | * transitions from zero to nonzero. If another bit got |
| 2747 | * set while we were handling the existing iir bits, then |
| 2748 | * we would never get another interrupt. |
| 2749 | * |
| 2750 | * This is fine on non-MSI as well, as if we hit this path |
| 2751 | * we avoid exiting the interrupt handler only to generate |
| 2752 | * another one. |
| 2753 | * |
| 2754 | * Note that for MSI this could cause a stray interrupt report |
| 2755 | * if an interrupt landed in the time between writing IIR and |
| 2756 | * the posting read. This should be rare enough to never |
| 2757 | * trigger the 99% of 100,000 interrupts test for disabling |
| 2758 | * stray interrupts. |
| 2759 | */ |
| 2760 | iir = new_iir; |
| 2761 | } |
| 2762 | |
Chris Wilson | 2c8ba29 | 2012-04-24 22:59:46 +0100 | [diff] [blame] | 2763 | if (dev->primary->master) { |
| 2764 | master_priv = dev->primary->master->driver_priv; |
| 2765 | if (master_priv->sarea_priv) |
| 2766 | master_priv->sarea_priv->last_dispatch = |
| 2767 | READ_BREADCRUMB(dev_priv); |
| 2768 | } |
| 2769 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2770 | return ret; |
| 2771 | } |
| 2772 | |
| 2773 | static void i965_irq_uninstall(struct drm_device * dev) |
| 2774 | { |
| 2775 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2776 | int pipe; |
| 2777 | |
| 2778 | if (!dev_priv) |
| 2779 | return; |
| 2780 | |
| 2781 | dev_priv->vblank_pipe = 0; |
| 2782 | |
| 2783 | if (I915_HAS_HOTPLUG(dev)) { |
| 2784 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2785 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 2786 | } |
| 2787 | |
| 2788 | I915_WRITE(HWSTAM, 0xffffffff); |
| 2789 | for_each_pipe(pipe) |
| 2790 | I915_WRITE(PIPESTAT(pipe), 0); |
| 2791 | I915_WRITE(IMR, 0xffffffff); |
| 2792 | I915_WRITE(IER, 0x0); |
| 2793 | |
| 2794 | for_each_pipe(pipe) |
| 2795 | I915_WRITE(PIPESTAT(pipe), |
| 2796 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); |
| 2797 | I915_WRITE(IIR, I915_READ(IIR)); |
| 2798 | } |
| 2799 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2800 | void intel_irq_init(struct drm_device *dev) |
| 2801 | { |
Chris Wilson | 8b2e326 | 2012-04-24 22:59:41 +0100 | [diff] [blame] | 2802 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2803 | |
| 2804 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
| 2805 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
| 2806 | INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work); |
| 2807 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2808 | dev->driver->get_vblank_counter = i915_get_vblank_counter; |
| 2809 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2810 | if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) || |
| 2811 | IS_VALLEYVIEW(dev)) { |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2812 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
| 2813 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; |
| 2814 | } |
| 2815 | |
Keith Packard | c3613de | 2011-08-12 17:05:54 -0700 | [diff] [blame] | 2816 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 2817 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
| 2818 | else |
| 2819 | dev->driver->get_vblank_timestamp = NULL; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2820 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
| 2821 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2822 | if (IS_VALLEYVIEW(dev)) { |
| 2823 | dev->driver->irq_handler = valleyview_irq_handler; |
| 2824 | dev->driver->irq_preinstall = valleyview_irq_preinstall; |
| 2825 | dev->driver->irq_postinstall = valleyview_irq_postinstall; |
| 2826 | dev->driver->irq_uninstall = valleyview_irq_uninstall; |
| 2827 | dev->driver->enable_vblank = valleyview_enable_vblank; |
| 2828 | dev->driver->disable_vblank = valleyview_disable_vblank; |
| 2829 | } else if (IS_IVYBRIDGE(dev)) { |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2830 | /* Share pre & uninstall handlers with ILK/SNB */ |
| 2831 | dev->driver->irq_handler = ivybridge_irq_handler; |
| 2832 | dev->driver->irq_preinstall = ironlake_irq_preinstall; |
| 2833 | dev->driver->irq_postinstall = ivybridge_irq_postinstall; |
| 2834 | dev->driver->irq_uninstall = ironlake_irq_uninstall; |
| 2835 | dev->driver->enable_vblank = ivybridge_enable_vblank; |
| 2836 | dev->driver->disable_vblank = ivybridge_disable_vblank; |
| 2837 | } else if (HAS_PCH_SPLIT(dev)) { |
| 2838 | dev->driver->irq_handler = ironlake_irq_handler; |
| 2839 | dev->driver->irq_preinstall = ironlake_irq_preinstall; |
| 2840 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
| 2841 | dev->driver->irq_uninstall = ironlake_irq_uninstall; |
| 2842 | dev->driver->enable_vblank = ironlake_enable_vblank; |
| 2843 | dev->driver->disable_vblank = ironlake_disable_vblank; |
| 2844 | } else { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2845 | if (INTEL_INFO(dev)->gen == 2) { |
| 2846 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
| 2847 | dev->driver->irq_postinstall = i8xx_irq_postinstall; |
| 2848 | dev->driver->irq_handler = i8xx_irq_handler; |
| 2849 | dev->driver->irq_uninstall = i8xx_irq_uninstall; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2850 | } else if (INTEL_INFO(dev)->gen == 3) { |
Chris Wilson | 4f7d1e7 | 2012-04-24 22:59:45 +0100 | [diff] [blame] | 2851 | /* IIR "flip pending" means done if this bit is set */ |
| 2852 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); |
| 2853 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2854 | dev->driver->irq_preinstall = i915_irq_preinstall; |
| 2855 | dev->driver->irq_postinstall = i915_irq_postinstall; |
| 2856 | dev->driver->irq_uninstall = i915_irq_uninstall; |
| 2857 | dev->driver->irq_handler = i915_irq_handler; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2858 | } else { |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2859 | dev->driver->irq_preinstall = i965_irq_preinstall; |
| 2860 | dev->driver->irq_postinstall = i965_irq_postinstall; |
| 2861 | dev->driver->irq_uninstall = i965_irq_uninstall; |
| 2862 | dev->driver->irq_handler = i965_irq_handler; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2863 | } |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2864 | dev->driver->enable_vblank = i915_enable_vblank; |
| 2865 | dev->driver->disable_vblank = i915_disable_vblank; |
| 2866 | } |
| 2867 | } |