blob: 968b88af2ef5ea93077186ff72d41d95aae60803 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Petr Machata803335a2018-02-27 14:53:46 +01003 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
Jiri Pirko22a67762017-02-03 10:29:07 +01004 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +020056#include <linux/netlink.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020057#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020058#include <net/pkt_cls.h>
59#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020060#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010061#include <net/tc_act/tc_sample.h>
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +020062#include <net/addrconf.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020063
64#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020065#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020066#include "core.h"
67#include "reg.h"
68#include "port.h"
69#include "trap.h"
70#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010071#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020072#include "spectrum_dpipe.h"
Yotam Gigid3b939b2017-09-19 10:00:09 +020073#include "spectrum_acl_flex_actions.h"
Petr Machataa629ef22018-02-13 11:27:48 +010074#include "spectrum_span.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020075#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020076
Yotam Gigi6b742192017-05-23 21:56:29 +020077#define MLXSW_FWREV_MAJOR 13
Tal Bar1c6e1032018-03-21 09:34:05 +020078#define MLXSW_FWREV_MINOR 1620
79#define MLXSW_FWREV_SUBMINOR 192
Yuval Mintzfd5204c2018-01-18 12:55:23 +010080#define MLXSW_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
Yotam Gigi6b742192017-05-23 21:56:29 +020081
82#define MLXSW_SP_FW_FILENAME \
Yotam Gigia4e1ce22017-06-04 16:49:58 +020083 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
Yotam Gigi6b742192017-05-23 21:56:29 +020084 "." __stringify(MLXSW_FWREV_MINOR) \
85 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
86
Jiri Pirko56ade8f2015-10-16 14:01:37 +020087static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
88static const char mlxsw_sp_driver_version[] = "1.0";
89
90/* tx_hdr_version
91 * Tx header version.
92 * Must be set to 1.
93 */
94MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
95
96/* tx_hdr_ctl
97 * Packet control type.
98 * 0 - Ethernet control (e.g. EMADs, LACP)
99 * 1 - Ethernet data
100 */
101MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
102
103/* tx_hdr_proto
104 * Packet protocol type. Must be set to 1 (Ethernet).
105 */
106MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
107
108/* tx_hdr_rx_is_router
109 * Packet is sent from the router. Valid for data packets only.
110 */
111MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
112
113/* tx_hdr_fid_valid
114 * Indicates if the 'fid' field is valid and should be used for
115 * forwarding lookup. Valid for data packets only.
116 */
117MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
118
119/* tx_hdr_swid
120 * Switch partition ID. Must be set to 0.
121 */
122MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
123
124/* tx_hdr_control_tclass
125 * Indicates if the packet should use the control TClass and not one
126 * of the data TClasses.
127 */
128MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
129
130/* tx_hdr_etclass
131 * Egress TClass to be used on the egress device on the egress port.
132 */
133MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
134
135/* tx_hdr_port_mid
136 * Destination local port for unicast packets.
137 * Destination multicast ID for multicast packets.
138 *
139 * Control packets are directed to a specific egress port, while data
140 * packets are transmitted through the CPU port (0) into the switch partition,
141 * where forwarding rules are applied.
142 */
143MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
144
145/* tx_hdr_fid
146 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
147 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
148 * Valid for data packets only.
149 */
150MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
151
152/* tx_hdr_type
153 * 0 - Data packets
154 * 6 - Control packets
155 */
156MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
157
Yotam Gigie5e5c882017-05-23 21:56:27 +0200158struct mlxsw_sp_mlxfw_dev {
159 struct mlxfw_dev mlxfw_dev;
160 struct mlxsw_sp *mlxsw_sp;
161};
162
163static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
164 u16 component_index, u32 *p_max_size,
165 u8 *p_align_bits, u16 *p_max_write_size)
166{
167 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
168 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
169 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
170 char mcqi_pl[MLXSW_REG_MCQI_LEN];
171 int err;
172
173 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
174 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
175 if (err)
176 return err;
177 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
178 p_max_write_size);
179
180 *p_align_bits = max_t(u8, *p_align_bits, 2);
181 *p_max_write_size = min_t(u16, *p_max_write_size,
182 MLXSW_REG_MCDA_MAX_DATA_LEN);
183 return 0;
184}
185
186static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
187{
188 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
189 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
190 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
191 char mcc_pl[MLXSW_REG_MCC_LEN];
192 u8 control_state;
193 int err;
194
195 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
196 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
197 if (err)
198 return err;
199
200 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
201 if (control_state != MLXFW_FSM_STATE_IDLE)
202 return -EBUSY;
203
204 mlxsw_reg_mcc_pack(mcc_pl,
205 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
206 0, *fwhandle, 0);
207 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
208}
209
210static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
211 u32 fwhandle, u16 component_index,
212 u32 component_size)
213{
214 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
215 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
217 char mcc_pl[MLXSW_REG_MCC_LEN];
218
219 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
220 component_index, fwhandle, component_size);
221 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
222}
223
224static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
225 u32 fwhandle, u8 *data, u16 size,
226 u32 offset)
227{
228 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
229 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
230 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
231 char mcda_pl[MLXSW_REG_MCDA_LEN];
232
233 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
234 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
235}
236
237static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
238 u32 fwhandle, u16 component_index)
239{
240 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
241 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
242 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
243 char mcc_pl[MLXSW_REG_MCC_LEN];
244
245 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
246 component_index, fwhandle, 0);
247 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
248}
249
250static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
251{
252 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
253 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
254 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
255 char mcc_pl[MLXSW_REG_MCC_LEN];
256
257 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
258 fwhandle, 0);
259 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
260}
261
262static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
263 enum mlxfw_fsm_state *fsm_state,
264 enum mlxfw_fsm_state_err *fsm_state_err)
265{
266 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
267 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
268 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
269 char mcc_pl[MLXSW_REG_MCC_LEN];
270 u8 control_state;
271 u8 error_code;
272 int err;
273
274 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
275 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
276 if (err)
277 return err;
278
279 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
280 *fsm_state = control_state;
281 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
282 MLXFW_FSM_STATE_ERR_MAX);
283 return 0;
284}
285
286static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
287{
288 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
289 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
290 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
291 char mcc_pl[MLXSW_REG_MCC_LEN];
292
293 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
294 fwhandle, 0);
295 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
296}
297
298static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
299{
300 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
301 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
302 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
303 char mcc_pl[MLXSW_REG_MCC_LEN];
304
305 mlxsw_reg_mcc_pack(mcc_pl,
306 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
307 fwhandle, 0);
308 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
309}
310
311static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
312 .component_query = mlxsw_sp_component_query,
313 .fsm_lock = mlxsw_sp_fsm_lock,
314 .fsm_component_update = mlxsw_sp_fsm_component_update,
315 .fsm_block_download = mlxsw_sp_fsm_block_download,
316 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
317 .fsm_activate = mlxsw_sp_fsm_activate,
318 .fsm_query_state = mlxsw_sp_fsm_query_state,
319 .fsm_cancel = mlxsw_sp_fsm_cancel,
320 .fsm_release = mlxsw_sp_fsm_release
321};
322
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300323static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
324 const struct firmware *firmware)
325{
326 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
327 .mlxfw_dev = {
328 .ops = &mlxsw_sp_mlxfw_dev_ops,
329 .psid = mlxsw_sp->bus_info->psid,
330 .psid_size = strlen(mlxsw_sp->bus_info->psid),
331 },
332 .mlxsw_sp = mlxsw_sp
333 };
334
335 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
336}
337
Yotam Gigi6b742192017-05-23 21:56:29 +0200338static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
339{
340 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
Yotam Gigi6b742192017-05-23 21:56:29 +0200341 const struct firmware *firmware;
342 int err;
343
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100344 /* Validate driver & FW are compatible */
345 if (rev->major != MLXSW_FWREV_MAJOR) {
346 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
347 rev->major, MLXSW_FWREV_MAJOR);
348 return -EINVAL;
349 }
350 if (MLXSW_FWREV_MINOR_TO_BRANCH(rev->minor) ==
351 MLXSW_FWREV_MINOR_TO_BRANCH(MLXSW_FWREV_MINOR))
Yotam Gigi6b742192017-05-23 21:56:29 +0200352 return 0;
353
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100354 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200355 rev->major, rev->minor, rev->subminor);
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100356 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200357 MLXSW_SP_FW_FILENAME);
358
359 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
360 mlxsw_sp->bus_info->dev);
361 if (err) {
362 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
363 MLXSW_SP_FW_FILENAME);
364 return err;
365 }
366
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300367 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
Yotam Gigi6b742192017-05-23 21:56:29 +0200368 release_firmware(firmware);
369 return err;
370}
371
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100372int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
373 unsigned int counter_index, u64 *packets,
374 u64 *bytes)
375{
376 char mgpc_pl[MLXSW_REG_MGPC_LEN];
377 int err;
378
379 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200380 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100381 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
382 if (err)
383 return err;
Arkadi Sharshevsky7cfcbc72017-08-24 08:40:08 +0200384 if (packets)
385 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
386 if (bytes)
387 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100388 return 0;
389}
390
391static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
392 unsigned int counter_index)
393{
394 char mgpc_pl[MLXSW_REG_MGPC_LEN];
395
396 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200397 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100398 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
399}
400
401int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
402 unsigned int *p_counter_index)
403{
404 int err;
405
406 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
407 p_counter_index);
408 if (err)
409 return err;
410 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
411 if (err)
412 goto err_counter_clear;
413 return 0;
414
415err_counter_clear:
416 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
417 *p_counter_index);
418 return err;
419}
420
421void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
422 unsigned int counter_index)
423{
424 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
425 counter_index);
426}
427
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200428static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
429 const struct mlxsw_tx_info *tx_info)
430{
431 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
432
433 memset(txhdr, 0, MLXSW_TXHDR_LEN);
434
435 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
436 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
437 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
438 mlxsw_tx_hdr_swid_set(txhdr, 0);
439 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
440 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
441 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
442}
443
Petr Machata541e1152018-04-29 10:56:09 +0300444enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200445{
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200446 switch (state) {
447 case BR_STATE_FORWARDING:
Petr Machata541e1152018-04-29 10:56:09 +0300448 return MLXSW_REG_SPMS_STATE_FORWARDING;
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200449 case BR_STATE_LEARNING:
Petr Machata541e1152018-04-29 10:56:09 +0300450 return MLXSW_REG_SPMS_STATE_LEARNING;
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200451 case BR_STATE_LISTENING: /* fall-through */
452 case BR_STATE_DISABLED: /* fall-through */
453 case BR_STATE_BLOCKING:
Petr Machata541e1152018-04-29 10:56:09 +0300454 return MLXSW_REG_SPMS_STATE_DISCARDING;
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200455 default:
456 BUG();
457 }
Petr Machata541e1152018-04-29 10:56:09 +0300458}
459
460int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
461 u8 state)
462{
463 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
464 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
465 char *spms_pl;
466 int err;
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200467
468 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
469 if (!spms_pl)
470 return -ENOMEM;
471 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
472 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
473
474 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
475 kfree(spms_pl);
476 return err;
477}
478
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200479static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
480{
Elad Raz5b090742016-10-28 21:35:46 +0200481 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200482 int err;
483
484 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
485 if (err)
486 return err;
487 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
488 return 0;
489}
490
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100491static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
492 bool enable, u32 rate)
493{
494 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
495 char mpsc_pl[MLXSW_REG_MPSC_LEN];
496
497 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
498 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
499}
500
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200501static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
502 bool is_up)
503{
504 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
505 char paos_pl[MLXSW_REG_PAOS_LEN];
506
507 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
508 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
509 MLXSW_PORT_ADMIN_STATUS_DOWN);
510 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
511}
512
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200513static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
514 unsigned char *addr)
515{
516 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
517 char ppad_pl[MLXSW_REG_PPAD_LEN];
518
519 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
520 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
521 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
522}
523
524static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
525{
526 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
527 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
528
529 ether_addr_copy(addr, mlxsw_sp->base_mac);
530 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
531 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
532}
533
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200534static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
535{
536 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
537 char pmtu_pl[MLXSW_REG_PMTU_LEN];
538 int max_mtu;
539 int err;
540
541 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
542 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
543 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
544 if (err)
545 return err;
546 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
547
548 if (mtu > max_mtu)
549 return -EINVAL;
550
551 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
552 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
553}
554
555static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
556{
557 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel5b153852017-06-08 08:47:44 +0200558 char pspa_pl[MLXSW_REG_PSPA_LEN];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200559
Ido Schimmel5b153852017-06-08 08:47:44 +0200560 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
561 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200562}
563
Ido Schimmela1107482017-05-26 08:37:39 +0200564int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200565{
566 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
567 char svpe_pl[MLXSW_REG_SVPE_LEN];
568
569 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
570 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
571}
572
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200573int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
574 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200575{
576 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
577 char *spvmlr_pl;
578 int err;
579
580 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
581 if (!spvmlr_pl)
582 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200583 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
584 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200585 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
586 kfree(spvmlr_pl);
587 return err;
588}
589
Ido Schimmelb02eae92017-05-16 19:38:34 +0200590static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
591 u16 vid)
592{
593 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
594 char spvid_pl[MLXSW_REG_SPVID_LEN];
595
596 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
597 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
598}
599
600static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
601 bool allow)
602{
603 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
604 char spaft_pl[MLXSW_REG_SPAFT_LEN];
605
606 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
607 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
608}
609
610int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
611{
612 int err;
613
614 if (!vid) {
615 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
616 if (err)
617 return err;
618 } else {
619 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
620 if (err)
621 return err;
622 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
623 if (err)
624 goto err_port_allow_untagged_set;
625 }
626
627 mlxsw_sp_port->pvid = vid;
628 return 0;
629
630err_port_allow_untagged_set:
631 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
632 return err;
633}
634
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200635static int
636mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
637{
638 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
639 char sspr_pl[MLXSW_REG_SSPR_LEN];
640
641 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
642 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
643}
644
Ido Schimmeld664b412016-06-09 09:51:40 +0200645static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
646 u8 local_port, u8 *p_module,
647 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200648{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200649 char pmlp_pl[MLXSW_REG_PMLP_LEN];
650 int err;
651
Ido Schimmel558c2d52016-02-26 17:32:29 +0100652 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200653 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
654 if (err)
655 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100656 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
657 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200658 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200659 return 0;
660}
661
Ido Schimmel2e915e02017-06-08 08:47:45 +0200662static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100663 u8 module, u8 width, u8 lane)
664{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200665 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel18f1e702016-02-26 17:32:31 +0100666 char pmlp_pl[MLXSW_REG_PMLP_LEN];
667 int i;
668
Ido Schimmel2e915e02017-06-08 08:47:45 +0200669 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel18f1e702016-02-26 17:32:31 +0100670 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
671 for (i = 0; i < width; i++) {
672 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
673 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
674 }
675
676 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
677}
678
Ido Schimmel2e915e02017-06-08 08:47:45 +0200679static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100680{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200681 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100682 char pmlp_pl[MLXSW_REG_PMLP_LEN];
683
Ido Schimmel2e915e02017-06-08 08:47:45 +0200684 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100685 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
686 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
687}
688
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200689static int mlxsw_sp_port_open(struct net_device *dev)
690{
691 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
692 int err;
693
694 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
695 if (err)
696 return err;
697 netif_start_queue(dev);
698 return 0;
699}
700
701static int mlxsw_sp_port_stop(struct net_device *dev)
702{
703 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
704
705 netif_stop_queue(dev);
706 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
707}
708
709static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
710 struct net_device *dev)
711{
712 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
713 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
714 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
715 const struct mlxsw_tx_info tx_info = {
716 .local_port = mlxsw_sp_port->local_port,
717 .is_emad = false,
718 };
719 u64 len;
720 int err;
721
Jiri Pirko307c2432016-04-08 19:11:22 +0200722 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200723 return NETDEV_TX_BUSY;
724
725 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
726 struct sk_buff *skb_orig = skb;
727
728 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
729 if (!skb) {
730 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
731 dev_kfree_skb_any(skb_orig);
732 return NETDEV_TX_OK;
733 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +0100734 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200735 }
736
737 if (eth_skb_pad(skb)) {
738 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
739 return NETDEV_TX_OK;
740 }
741
742 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +0200743 /* TX header is consumed by HW on the way so we shouldn't count its
744 * bytes as being sent.
745 */
746 len = skb->len - MLXSW_TXHDR_LEN;
747
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200748 /* Due to a race we might fail here because of a full queue. In that
749 * unlikely case we simply drop the packet.
750 */
Jiri Pirko307c2432016-04-08 19:11:22 +0200751 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200752
753 if (!err) {
754 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
755 u64_stats_update_begin(&pcpu_stats->syncp);
756 pcpu_stats->tx_packets++;
757 pcpu_stats->tx_bytes += len;
758 u64_stats_update_end(&pcpu_stats->syncp);
759 } else {
760 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
761 dev_kfree_skb_any(skb);
762 }
763 return NETDEV_TX_OK;
764}
765
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100766static void mlxsw_sp_set_rx_mode(struct net_device *dev)
767{
768}
769
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200770static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
771{
772 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
773 struct sockaddr *addr = p;
774 int err;
775
776 if (!is_valid_ether_addr(addr->sa_data))
777 return -EADDRNOTAVAIL;
778
779 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
780 if (err)
781 return err;
782 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
783 return 0;
784}
785
Ido Schimmel18281f22017-03-24 08:02:51 +0100786static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
787 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200788{
Ido Schimmel18281f22017-03-24 08:02:51 +0100789 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100790}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200791
Ido Schimmelf417f042017-03-24 08:02:50 +0100792#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +0100793
794static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
795 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +0100796{
Ido Schimmel18281f22017-03-24 08:02:51 +0100797 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
798 BITS_PER_BYTE));
799 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
800 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100801}
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200802
Ido Schimmel18281f22017-03-24 08:02:51 +0100803/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +0100804 * Assumes 100m cable and maximum MTU.
805 */
Ido Schimmel18281f22017-03-24 08:02:51 +0100806#define MLXSW_SP_PAUSE_DELAY 58752
807
808static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
809 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +0100810{
811 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +0100812 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +0100813 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +0100814 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200815 else
Ido Schimmelf417f042017-03-24 08:02:50 +0100816 return 0;
817}
818
819static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
820 bool lossy)
821{
822 if (lossy)
823 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
824 else
825 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
826 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200827}
828
829int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200830 u8 *prio_tc, bool pause_en,
831 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +0200832{
833 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200834 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
835 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200836 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200837 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200838
839 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
840 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
841 if (err)
842 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200843
844 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
845 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200846 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +0100847 bool lossy;
848 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200849
850 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
851 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200852 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200853 configure = true;
854 break;
855 }
856 }
857
858 if (!configure)
859 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +0100860
861 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +0100862 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
863 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
864 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +0100865 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200866 }
867
Ido Schimmelff6551e2016-04-06 17:10:03 +0200868 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
869}
870
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200871static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200872 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200873{
874 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
875 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200876 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200877 u8 *prio_tc;
878
879 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200880 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200881
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200882 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200883 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200884}
885
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200886static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
887{
888 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200889 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200890 int err;
891
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200892 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200893 if (err)
894 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200895 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
896 if (err)
897 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200898 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
899 if (err)
900 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200901 dev->mtu = mtu;
902 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200903
904err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +0200905 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
906err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200907 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +0200908 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200909}
910
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +0300911static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200912mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
913 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200914{
915 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
916 struct mlxsw_sp_port_pcpu_stats *p;
917 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
918 u32 tx_dropped = 0;
919 unsigned int start;
920 int i;
921
922 for_each_possible_cpu(i) {
923 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
924 do {
925 start = u64_stats_fetch_begin_irq(&p->syncp);
926 rx_packets = p->rx_packets;
927 rx_bytes = p->rx_bytes;
928 tx_packets = p->tx_packets;
929 tx_bytes = p->tx_bytes;
930 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
931
932 stats->rx_packets += rx_packets;
933 stats->rx_bytes += rx_bytes;
934 stats->tx_packets += tx_packets;
935 stats->tx_bytes += tx_bytes;
936 /* tx_dropped is u32, updated without syncp protection. */
937 tx_dropped += p->tx_dropped;
938 }
939 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200940 return 0;
941}
942
Or Gerlitz3df5b3c2016-11-22 23:09:54 +0200943static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200944{
945 switch (attr_id) {
946 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
947 return true;
948 }
949
950 return false;
951}
952
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +0300953static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
954 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200955{
956 switch (attr_id) {
957 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
958 return mlxsw_sp_port_get_sw_stats64(dev, sp);
959 }
960
961 return -EINVAL;
962}
963
964static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
965 int prio, char *ppcnt_pl)
966{
967 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
968 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
969
970 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
971 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
972}
973
974static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
975 struct rtnl_link_stats64 *stats)
976{
977 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
978 int err;
979
980 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
981 0, ppcnt_pl);
982 if (err)
983 goto out;
984
985 stats->tx_packets =
986 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
987 stats->rx_packets =
988 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
989 stats->tx_bytes =
990 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
991 stats->rx_bytes =
992 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
993 stats->multicast =
994 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
995
996 stats->rx_crc_errors =
997 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
998 stats->rx_frame_errors =
999 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1000
1001 stats->rx_length_errors = (
1002 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1003 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1004 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1005
1006 stats->rx_errors = (stats->rx_crc_errors +
1007 stats->rx_frame_errors + stats->rx_length_errors);
1008
1009out:
1010 return err;
1011}
1012
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001013static void
1014mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1015 struct mlxsw_sp_port_xstats *xstats)
1016{
1017 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1018 int err, i;
1019
1020 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1021 ppcnt_pl);
1022 if (!err)
1023 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1024
1025 for (i = 0; i < TC_MAX_QUEUE; i++) {
1026 err = mlxsw_sp_port_get_stats_raw(dev,
1027 MLXSW_REG_PPCNT_TC_CONG_TC,
1028 i, ppcnt_pl);
1029 if (!err)
1030 xstats->wred_drop[i] =
1031 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1032
1033 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1034 i, ppcnt_pl);
1035 if (err)
1036 continue;
1037
1038 xstats->backlog[i] =
1039 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1040 xstats->tail_drop[i] =
1041 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1042 }
Nogah Frankel2f880472018-02-28 10:44:59 +01001043
1044 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1045 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
1046 i, ppcnt_pl);
1047 if (err)
1048 continue;
1049
1050 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
1051 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
1052 }
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001053}
1054
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001055static void update_stats_cache(struct work_struct *work)
1056{
1057 struct mlxsw_sp_port *mlxsw_sp_port =
1058 container_of(work, struct mlxsw_sp_port,
Nogah Frankel9deef432017-10-26 10:55:32 +02001059 periodic_hw_stats.update_dw.work);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001060
1061 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1062 goto out;
1063
1064 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
Nogah Frankel9deef432017-10-26 10:55:32 +02001065 &mlxsw_sp_port->periodic_hw_stats.stats);
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001066 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1067 &mlxsw_sp_port->periodic_hw_stats.xstats);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001068
1069out:
Nogah Frankel9deef432017-10-26 10:55:32 +02001070 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001071 MLXSW_HW_STATS_UPDATE_TIME);
1072}
1073
1074/* Return the stats from a cache that is updated periodically,
1075 * as this function might get called in an atomic context.
1076 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001077static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001078mlxsw_sp_port_get_stats64(struct net_device *dev,
1079 struct rtnl_link_stats64 *stats)
1080{
1081 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1082
Nogah Frankel9deef432017-10-26 10:55:32 +02001083 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001084}
1085
Jiri Pirko93cd0812017-04-18 16:55:35 +02001086static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1087 u16 vid_begin, u16 vid_end,
1088 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001089{
1090 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1091 char *spvm_pl;
1092 int err;
1093
1094 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1095 if (!spvm_pl)
1096 return -ENOMEM;
1097
1098 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1099 vid_end, is_member, untagged);
1100 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1101 kfree(spvm_pl);
1102 return err;
1103}
1104
Jiri Pirko93cd0812017-04-18 16:55:35 +02001105int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1106 u16 vid_end, bool is_member, bool untagged)
1107{
1108 u16 vid, vid_e;
1109 int err;
1110
1111 for (vid = vid_begin; vid <= vid_end;
1112 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1113 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1114 vid_end);
1115
1116 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1117 is_member, untagged);
1118 if (err)
1119 return err;
1120 }
1121
1122 return 0;
1123}
1124
Ido Schimmelc57529e2017-05-26 08:37:31 +02001125static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001126{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001127 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001128
Ido Schimmelc57529e2017-05-26 08:37:31 +02001129 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1130 &mlxsw_sp_port->vlans_list, list)
1131 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001132}
1133
Ido Schimmel31a08a52017-05-26 08:37:26 +02001134static struct mlxsw_sp_port_vlan *
1135mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1136{
1137 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001138 bool untagged = vid == 1;
1139 int err;
1140
1141 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1142 if (err)
1143 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001144
1145 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001146 if (!mlxsw_sp_port_vlan) {
1147 err = -ENOMEM;
1148 goto err_port_vlan_alloc;
1149 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02001150
1151 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
Ido Schimmelb3529af2018-02-28 13:12:11 +01001152 mlxsw_sp_port_vlan->ref_count = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02001153 mlxsw_sp_port_vlan->vid = vid;
1154 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1155
1156 return mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001157
1158err_port_vlan_alloc:
1159 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1160 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001161}
1162
1163static void
1164mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1165{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001166 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1167 u16 vid = mlxsw_sp_port_vlan->vid;
Ido Schimmel7cbecf22017-05-26 08:37:28 +02001168
Ido Schimmel31a08a52017-05-26 08:37:26 +02001169 list_del(&mlxsw_sp_port_vlan->list);
1170 kfree(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001171 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1172}
1173
1174struct mlxsw_sp_port_vlan *
1175mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1176{
1177 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1178
1179 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelb3529af2018-02-28 13:12:11 +01001180 if (mlxsw_sp_port_vlan) {
1181 mlxsw_sp_port_vlan->ref_count++;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001182 return mlxsw_sp_port_vlan;
Ido Schimmelb3529af2018-02-28 13:12:11 +01001183 }
Ido Schimmelc57529e2017-05-26 08:37:31 +02001184
1185 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1186}
1187
1188void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1189{
Ido Schimmela1107482017-05-26 08:37:39 +02001190 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1191
Ido Schimmelb3529af2018-02-28 13:12:11 +01001192 if (--mlxsw_sp_port_vlan->ref_count != 0)
1193 return;
1194
Ido Schimmelc57529e2017-05-26 08:37:31 +02001195 if (mlxsw_sp_port_vlan->bridge_port)
1196 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
Ido Schimmela1107482017-05-26 08:37:39 +02001197 else if (fid)
1198 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001199
1200 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001201}
1202
Ido Schimmel05978482016-08-17 16:39:30 +02001203static int mlxsw_sp_port_add_vid(struct net_device *dev,
1204 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001205{
1206 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001207
1208 /* VLAN 0 is added to HW filter when device goes up, but it is
1209 * reserved in our case, so simply return.
1210 */
1211 if (!vid)
1212 return 0;
1213
Ido Schimmelc57529e2017-05-26 08:37:31 +02001214 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001215}
1216
Ido Schimmel32d863f2016-07-02 11:00:10 +02001217static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1218 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001219{
1220 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001221 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001222
1223 /* VLAN 0 is removed from HW filter when device goes down, but
1224 * it is reserved in our case, so simply return.
1225 */
1226 if (!vid)
1227 return 0;
1228
Ido Schimmel31a08a52017-05-26 08:37:26 +02001229 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001230 if (!mlxsw_sp_port_vlan)
Ido Schimmel31a08a52017-05-26 08:37:26 +02001231 return 0;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001232 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001233
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001234 return 0;
1235}
1236
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001237static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1238 size_t len)
1239{
1240 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001241
Jiri Pirkoec932fb2018-05-18 09:29:04 +02001242 return mlxsw_core_port_get_phys_port_name(mlxsw_sp_port->mlxsw_sp->core,
1243 mlxsw_sp_port->local_port,
1244 name, len);
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001245}
1246
Yotam Gigi763b4b72016-07-21 12:03:17 +02001247static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001248mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1249 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001250 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1251
1252 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1253 if (mall_tc_entry->cookie == cookie)
1254 return mall_tc_entry;
1255
1256 return NULL;
1257}
1258
1259static int
1260mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001261 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001262 const struct tc_action *a,
1263 bool ingress)
1264{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001265 enum mlxsw_sp_span_type span_type;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001266 struct net_device *to_dev;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001267
Cong Wang9f8a7392017-12-05 16:17:26 -08001268 to_dev = tcf_mirred_dev(a);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001269 if (!to_dev) {
1270 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1271 return -EINVAL;
1272 }
1273
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001274 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001275 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Petr Machata079c9f32018-02-27 14:53:44 +01001276 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type,
Petr Machata98977082018-02-27 14:53:41 +01001277 true, &mirror->span_id);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001278}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001279
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001280static void
1281mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1282 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1283{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001284 enum mlxsw_sp_span_type span_type;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001285
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001286 span_type = mirror->ingress ?
1287 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Petr Machata98977082018-02-27 14:53:41 +01001288 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +01001289 span_type, true);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001290}
1291
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001292static int
1293mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1294 struct tc_cls_matchall_offload *cls,
1295 const struct tc_action *a,
1296 bool ingress)
1297{
1298 int err;
1299
1300 if (!mlxsw_sp_port->sample)
1301 return -EOPNOTSUPP;
1302 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1303 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1304 return -EEXIST;
1305 }
1306 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1307 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1308 return -EOPNOTSUPP;
1309 }
1310
1311 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1312 tcf_sample_psample_group(a));
1313 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1314 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1315 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1316
1317 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1318 if (err)
1319 goto err_port_sample_set;
1320 return 0;
1321
1322err_port_sample_set:
1323 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1324 return err;
1325}
1326
1327static void
1328mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1329{
1330 if (!mlxsw_sp_port->sample)
1331 return;
1332
1333 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1334 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1335}
1336
Yotam Gigi763b4b72016-07-21 12:03:17 +02001337static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001338 struct tc_cls_matchall_offload *f,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001339 bool ingress)
1340{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001341 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001342 __be16 protocol = f->common.protocol;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001343 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001344 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001345 int err;
1346
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001347 if (!tcf_exts_has_one_action(f->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001348 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001349 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001350 }
1351
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001352 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1353 if (!mall_tc_entry)
1354 return -ENOMEM;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001355 mall_tc_entry->cookie = f->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001356
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001357 tcf_exts_to_list(f->exts, &actions);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001358 a = list_first_entry(&actions, struct tc_action, list);
1359
1360 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1361 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1362
1363 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1364 mirror = &mall_tc_entry->mirror;
1365 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1366 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001367 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1368 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001369 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001370 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001371 } else {
1372 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001373 }
1374
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001375 if (err)
1376 goto err_add_action;
1377
1378 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001379 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001380
1381err_add_action:
1382 kfree(mall_tc_entry);
1383 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001384}
1385
1386static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001387 struct tc_cls_matchall_offload *f)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001388{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001389 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001390
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001391 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001392 f->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001393 if (!mall_tc_entry) {
1394 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1395 return;
1396 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001397 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001398
1399 switch (mall_tc_entry->type) {
1400 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001401 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1402 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001403 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001404 case MLXSW_SP_PORT_MALL_SAMPLE:
1405 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1406 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001407 default:
1408 WARN_ON(1);
1409 }
1410
Yotam Gigi763b4b72016-07-21 12:03:17 +02001411 kfree(mall_tc_entry);
1412}
1413
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001414static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001415 struct tc_cls_matchall_offload *f,
1416 bool ingress)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001417{
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001418 switch (f->command) {
1419 case TC_CLSMATCHALL_REPLACE:
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001420 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001421 ingress);
1422 case TC_CLSMATCHALL_DESTROY:
1423 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1424 return 0;
1425 default:
1426 return -EOPNOTSUPP;
1427 }
1428}
1429
1430static int
Jiri Pirko3aaff322018-01-17 11:46:56 +01001431mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1432 struct tc_cls_flower_offload *f)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001433{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001434 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1435
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001436 switch (f->command) {
1437 case TC_CLSFLOWER_REPLACE:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001438 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001439 case TC_CLSFLOWER_DESTROY:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001440 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001441 return 0;
1442 case TC_CLSFLOWER_STATS:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001443 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001444 default:
1445 return -EOPNOTSUPP;
1446 }
1447}
1448
Jiri Pirko3aaff322018-01-17 11:46:56 +01001449static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1450 void *type_data,
1451 void *cb_priv, bool ingress)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001452{
1453 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1454
1455 switch (type) {
1456 case TC_SETUP_CLSMATCHALL:
Jakub Kicinski15f4edb2018-01-25 14:00:51 -08001457 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1458 type_data))
Jiri Pirko3aaff322018-01-17 11:46:56 +01001459 return -EOPNOTSUPP;
1460
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001461 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1462 ingress);
1463 case TC_SETUP_CLSFLOWER:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001464 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001465 default:
1466 return -EOPNOTSUPP;
1467 }
1468}
1469
Jiri Pirko3aaff322018-01-17 11:46:56 +01001470static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1471 void *type_data,
1472 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001473{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001474 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1475 cb_priv, true);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001476}
1477
Jiri Pirko3aaff322018-01-17 11:46:56 +01001478static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1479 void *type_data,
1480 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001481{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001482 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1483 cb_priv, false);
1484}
1485
1486static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1487 void *type_data, void *cb_priv)
1488{
1489 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1490
1491 switch (type) {
1492 case TC_SETUP_CLSMATCHALL:
1493 return 0;
1494 case TC_SETUP_CLSFLOWER:
1495 if (mlxsw_sp_acl_block_disabled(acl_block))
1496 return -EOPNOTSUPP;
1497
1498 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1499 default:
1500 return -EOPNOTSUPP;
1501 }
1502}
1503
1504static int
1505mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1506 struct tcf_block *block, bool ingress)
1507{
1508 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1509 struct mlxsw_sp_acl_block *acl_block;
1510 struct tcf_block_cb *block_cb;
1511 int err;
1512
1513 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1514 mlxsw_sp);
1515 if (!block_cb) {
1516 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1517 if (!acl_block)
1518 return -ENOMEM;
1519 block_cb = __tcf_block_cb_register(block,
1520 mlxsw_sp_setup_tc_block_cb_flower,
1521 mlxsw_sp, acl_block);
1522 if (IS_ERR(block_cb)) {
1523 err = PTR_ERR(block_cb);
1524 goto err_cb_register;
1525 }
1526 } else {
1527 acl_block = tcf_block_cb_priv(block_cb);
1528 }
1529 tcf_block_cb_incref(block_cb);
1530 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1531 mlxsw_sp_port, ingress);
1532 if (err)
1533 goto err_block_bind;
1534
1535 if (ingress)
1536 mlxsw_sp_port->ing_acl_block = acl_block;
1537 else
1538 mlxsw_sp_port->eg_acl_block = acl_block;
1539
1540 return 0;
1541
1542err_block_bind:
1543 if (!tcf_block_cb_decref(block_cb)) {
1544 __tcf_block_cb_unregister(block_cb);
1545err_cb_register:
1546 mlxsw_sp_acl_block_destroy(acl_block);
1547 }
1548 return err;
1549}
1550
1551static void
1552mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1553 struct tcf_block *block, bool ingress)
1554{
1555 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1556 struct mlxsw_sp_acl_block *acl_block;
1557 struct tcf_block_cb *block_cb;
1558 int err;
1559
1560 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1561 mlxsw_sp);
1562 if (!block_cb)
1563 return;
1564
1565 if (ingress)
1566 mlxsw_sp_port->ing_acl_block = NULL;
1567 else
1568 mlxsw_sp_port->eg_acl_block = NULL;
1569
1570 acl_block = tcf_block_cb_priv(block_cb);
1571 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1572 mlxsw_sp_port, ingress);
1573 if (!err && !tcf_block_cb_decref(block_cb)) {
1574 __tcf_block_cb_unregister(block_cb);
1575 mlxsw_sp_acl_block_destroy(acl_block);
1576 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001577}
1578
1579static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1580 struct tc_block_offload *f)
1581{
1582 tc_setup_cb_t *cb;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001583 bool ingress;
1584 int err;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001585
Jiri Pirko3aaff322018-01-17 11:46:56 +01001586 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1587 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1588 ingress = true;
1589 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1590 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1591 ingress = false;
1592 } else {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001593 return -EOPNOTSUPP;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001594 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001595
1596 switch (f->command) {
1597 case TC_BLOCK_BIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001598 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1599 mlxsw_sp_port);
1600 if (err)
1601 return err;
1602 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
1603 f->block, ingress);
1604 if (err) {
1605 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1606 return err;
1607 }
1608 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001609 case TC_BLOCK_UNBIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001610 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1611 f->block, ingress);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001612 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1613 return 0;
1614 default:
1615 return -EOPNOTSUPP;
1616 }
1617}
1618
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001619static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
Jiri Pirkode4784c2017-08-07 10:15:32 +02001620 void *type_data)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001621{
1622 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1623
Jiri Pirko2572ac52017-08-07 10:15:17 +02001624 switch (type) {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001625 case TC_SETUP_BLOCK:
1626 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
Nogah Frankel96f17e02017-11-06 07:23:45 +01001627 case TC_SETUP_QDISC_RED:
1628 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
Nogah Frankel46a36152018-01-14 12:33:16 +01001629 case TC_SETUP_QDISC_PRIO:
1630 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
Jiri Pirko2572ac52017-08-07 10:15:17 +02001631 default:
1632 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001633 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001634}
1635
Jiri Pirko9454d932017-12-06 09:41:12 +01001636
1637static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1638{
1639 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1640
Jiri Pirko3aaff322018-01-17 11:46:56 +01001641 if (!enable) {
1642 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1643 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1644 !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1645 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1646 return -EINVAL;
1647 }
1648 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1649 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1650 } else {
1651 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1652 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
Jiri Pirko9454d932017-12-06 09:41:12 +01001653 }
1654 return 0;
1655}
1656
1657typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1658
1659static int mlxsw_sp_handle_feature(struct net_device *dev,
1660 netdev_features_t wanted_features,
1661 netdev_features_t feature,
1662 mlxsw_sp_feature_handler feature_handler)
1663{
1664 netdev_features_t changes = wanted_features ^ dev->features;
1665 bool enable = !!(wanted_features & feature);
1666 int err;
1667
1668 if (!(changes & feature))
1669 return 0;
1670
1671 err = feature_handler(dev, enable);
1672 if (err) {
1673 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1674 enable ? "Enable" : "Disable", &feature, err);
1675 return err;
1676 }
1677
1678 if (enable)
1679 dev->features |= feature;
1680 else
1681 dev->features &= ~feature;
1682
1683 return 0;
1684}
1685static int mlxsw_sp_set_features(struct net_device *dev,
1686 netdev_features_t features)
1687{
1688 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1689 mlxsw_sp_feature_hw_tc);
1690}
1691
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001692static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1693 .ndo_open = mlxsw_sp_port_open,
1694 .ndo_stop = mlxsw_sp_port_stop,
1695 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001696 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001697 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001698 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1699 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1700 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001701 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1702 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001703 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1704 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001705 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko9454d932017-12-06 09:41:12 +01001706 .ndo_set_features = mlxsw_sp_set_features,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001707};
1708
1709static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1710 struct ethtool_drvinfo *drvinfo)
1711{
1712 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1713 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1714
1715 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1716 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1717 sizeof(drvinfo->version));
1718 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1719 "%d.%d.%d",
1720 mlxsw_sp->bus_info->fw_rev.major,
1721 mlxsw_sp->bus_info->fw_rev.minor,
1722 mlxsw_sp->bus_info->fw_rev.subminor);
1723 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1724 sizeof(drvinfo->bus_info));
1725}
1726
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001727static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1728 struct ethtool_pauseparam *pause)
1729{
1730 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1731
1732 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1733 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1734}
1735
1736static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1737 struct ethtool_pauseparam *pause)
1738{
1739 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1740
1741 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1742 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1743 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1744
1745 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1746 pfcc_pl);
1747}
1748
1749static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1750 struct ethtool_pauseparam *pause)
1751{
1752 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1753 bool pause_en = pause->tx_pause || pause->rx_pause;
1754 int err;
1755
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001756 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1757 netdev_err(dev, "PFC already enabled on port\n");
1758 return -EINVAL;
1759 }
1760
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001761 if (pause->autoneg) {
1762 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1763 return -EINVAL;
1764 }
1765
1766 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1767 if (err) {
1768 netdev_err(dev, "Failed to configure port's headroom\n");
1769 return err;
1770 }
1771
1772 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1773 if (err) {
1774 netdev_err(dev, "Failed to set PAUSE parameters\n");
1775 goto err_port_pause_configure;
1776 }
1777
1778 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1779 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1780
1781 return 0;
1782
1783err_port_pause_configure:
1784 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1785 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1786 return err;
1787}
1788
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001789struct mlxsw_sp_port_hw_stats {
1790 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02001791 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01001792 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001793};
1794
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001795static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001796 {
1797 .str = "a_frames_transmitted_ok",
1798 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1799 },
1800 {
1801 .str = "a_frames_received_ok",
1802 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1803 },
1804 {
1805 .str = "a_frame_check_sequence_errors",
1806 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1807 },
1808 {
1809 .str = "a_alignment_errors",
1810 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1811 },
1812 {
1813 .str = "a_octets_transmitted_ok",
1814 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1815 },
1816 {
1817 .str = "a_octets_received_ok",
1818 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1819 },
1820 {
1821 .str = "a_multicast_frames_xmitted_ok",
1822 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1823 },
1824 {
1825 .str = "a_broadcast_frames_xmitted_ok",
1826 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1827 },
1828 {
1829 .str = "a_multicast_frames_received_ok",
1830 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1831 },
1832 {
1833 .str = "a_broadcast_frames_received_ok",
1834 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1835 },
1836 {
1837 .str = "a_in_range_length_errors",
1838 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1839 },
1840 {
1841 .str = "a_out_of_range_length_field",
1842 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1843 },
1844 {
1845 .str = "a_frame_too_long_errors",
1846 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1847 },
1848 {
1849 .str = "a_symbol_error_during_carrier",
1850 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1851 },
1852 {
1853 .str = "a_mac_control_frames_transmitted",
1854 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1855 },
1856 {
1857 .str = "a_mac_control_frames_received",
1858 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1859 },
1860 {
1861 .str = "a_unsupported_opcodes_received",
1862 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1863 },
1864 {
1865 .str = "a_pause_mac_ctrl_frames_received",
1866 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1867 },
1868 {
1869 .str = "a_pause_mac_ctrl_frames_xmitted",
1870 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1871 },
1872};
1873
1874#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1875
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001876static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1877 {
1878 .str = "rx_octets_prio",
1879 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1880 },
1881 {
1882 .str = "rx_frames_prio",
1883 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1884 },
1885 {
1886 .str = "tx_octets_prio",
1887 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1888 },
1889 {
1890 .str = "tx_frames_prio",
1891 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1892 },
1893 {
1894 .str = "rx_pause_prio",
1895 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1896 },
1897 {
1898 .str = "rx_pause_duration_prio",
1899 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1900 },
1901 {
1902 .str = "tx_pause_prio",
1903 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1904 },
1905 {
1906 .str = "tx_pause_duration_prio",
1907 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1908 },
1909};
1910
1911#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1912
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001913static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1914 {
1915 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01001916 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1917 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001918 },
1919 {
1920 .str = "tc_no_buffer_discard_uc_tc",
1921 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1922 },
1923};
1924
1925#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1926
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001927#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001928 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1929 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001930 IEEE_8021QAZ_MAX_TCS)
1931
1932static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1933{
1934 int i;
1935
1936 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1937 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1938 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1939 *p += ETH_GSTRING_LEN;
1940 }
1941}
1942
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001943static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1944{
1945 int i;
1946
1947 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1948 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1949 mlxsw_sp_port_hw_tc_stats[i].str, tc);
1950 *p += ETH_GSTRING_LEN;
1951 }
1952}
1953
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001954static void mlxsw_sp_port_get_strings(struct net_device *dev,
1955 u32 stringset, u8 *data)
1956{
1957 u8 *p = data;
1958 int i;
1959
1960 switch (stringset) {
1961 case ETH_SS_STATS:
1962 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1963 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1964 ETH_GSTRING_LEN);
1965 p += ETH_GSTRING_LEN;
1966 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001967
1968 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1969 mlxsw_sp_port_get_prio_strings(&p, i);
1970
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001971 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1972 mlxsw_sp_port_get_tc_strings(&p, i);
1973
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001974 break;
1975 }
1976}
1977
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001978static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1979 enum ethtool_phys_id_state state)
1980{
1981 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1982 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1983 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1984 bool active;
1985
1986 switch (state) {
1987 case ETHTOOL_ID_ACTIVE:
1988 active = true;
1989 break;
1990 case ETHTOOL_ID_INACTIVE:
1991 active = false;
1992 break;
1993 default:
1994 return -EOPNOTSUPP;
1995 }
1996
1997 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1998 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1999}
2000
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002001static int
2002mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2003 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2004{
2005 switch (grp) {
2006 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2007 *p_hw_stats = mlxsw_sp_port_hw_stats;
2008 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2009 break;
2010 case MLXSW_REG_PPCNT_PRIO_CNT:
2011 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2012 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2013 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002014 case MLXSW_REG_PPCNT_TC_CNT:
2015 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2016 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2017 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002018 default:
2019 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002020 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002021 }
2022 return 0;
2023}
2024
2025static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2026 enum mlxsw_reg_ppcnt_grp grp, int prio,
2027 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002028{
Ido Schimmel18281f22017-03-24 08:02:51 +01002029 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2030 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002031 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002032 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002033 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002034 int err;
2035
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002036 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2037 if (err)
2038 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002039 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002040 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002041 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002042 if (!hw_stats[i].cells_bytes)
2043 continue;
2044 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2045 data[data_index + i]);
2046 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002047}
2048
2049static void mlxsw_sp_port_get_stats(struct net_device *dev,
2050 struct ethtool_stats *stats, u64 *data)
2051{
2052 int i, data_index = 0;
2053
2054 /* IEEE 802.3 Counters */
2055 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2056 data, data_index);
2057 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2058
2059 /* Per-Priority Counters */
2060 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2061 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2062 data, data_index);
2063 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2064 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002065
2066 /* Per-TC Counters */
2067 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2068 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2069 data, data_index);
2070 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2071 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002072}
2073
2074static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2075{
2076 switch (sset) {
2077 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002078 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002079 default:
2080 return -EOPNOTSUPP;
2081 }
2082}
2083
2084struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002085 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002086 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002087 u32 speed;
2088};
2089
2090static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2091 {
2092 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002093 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2094 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002095 },
2096 {
2097 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2098 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002099 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2100 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002101 },
2102 {
2103 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002104 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2105 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002106 },
2107 {
2108 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2109 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002110 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2111 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002112 },
2113 {
2114 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2115 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2116 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2117 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002118 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2119 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002120 },
2121 {
2122 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002123 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2124 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002125 },
2126 {
2127 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002128 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2129 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002130 },
2131 {
2132 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002133 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2134 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002135 },
2136 {
2137 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002138 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2139 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002140 },
2141 {
2142 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002143 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2144 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002145 },
2146 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002147 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2148 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2149 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002150 },
2151 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002152 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2153 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2154 .speed = SPEED_25000,
2155 },
2156 {
2157 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2158 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2159 .speed = SPEED_25000,
2160 },
2161 {
2162 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2163 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2164 .speed = SPEED_25000,
2165 },
2166 {
2167 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2168 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2169 .speed = SPEED_50000,
2170 },
2171 {
2172 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2173 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2174 .speed = SPEED_50000,
2175 },
2176 {
2177 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2178 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2179 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002180 },
2181 {
2182 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002183 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2184 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002185 },
2186 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002187 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2188 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2189 .speed = SPEED_56000,
2190 },
2191 {
2192 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2193 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2194 .speed = SPEED_56000,
2195 },
2196 {
2197 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2198 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2199 .speed = SPEED_56000,
2200 },
2201 {
2202 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2203 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2204 .speed = SPEED_100000,
2205 },
2206 {
2207 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2208 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2209 .speed = SPEED_100000,
2210 },
2211 {
2212 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2213 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2214 .speed = SPEED_100000,
2215 },
2216 {
2217 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2218 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2219 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002220 },
2221};
2222
2223#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2224
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002225static void
2226mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2227 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002228{
2229 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2230 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2231 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2232 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2233 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2234 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002235 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002236
2237 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2238 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2239 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2240 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2241 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002242 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002243}
2244
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002245static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002246{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002247 int i;
2248
2249 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2250 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002251 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2252 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002253 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002254}
2255
2256static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002257 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002258{
2259 u32 speed = SPEED_UNKNOWN;
2260 u8 duplex = DUPLEX_UNKNOWN;
2261 int i;
2262
2263 if (!carrier_ok)
2264 goto out;
2265
2266 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2267 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2268 speed = mlxsw_sp_port_link_mode[i].speed;
2269 duplex = DUPLEX_FULL;
2270 break;
2271 }
2272 }
2273out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002274 cmd->base.speed = speed;
2275 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002276}
2277
2278static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2279{
2280 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2281 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2282 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2283 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2284 return PORT_FIBRE;
2285
2286 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2287 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2288 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2289 return PORT_DA;
2290
2291 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2292 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2293 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2294 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2295 return PORT_NONE;
2296
2297 return PORT_OTHER;
2298}
2299
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002300static u32
2301mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002302{
2303 u32 ptys_proto = 0;
2304 int i;
2305
2306 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002307 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2308 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002309 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2310 }
2311 return ptys_proto;
2312}
2313
2314static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2315{
2316 u32 ptys_proto = 0;
2317 int i;
2318
2319 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2320 if (speed == mlxsw_sp_port_link_mode[i].speed)
2321 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2322 }
2323 return ptys_proto;
2324}
2325
Ido Schimmel18f1e702016-02-26 17:32:31 +01002326static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2327{
2328 u32 ptys_proto = 0;
2329 int i;
2330
2331 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2332 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2333 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2334 }
2335 return ptys_proto;
2336}
2337
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002338static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2339 struct ethtool_link_ksettings *cmd)
2340{
2341 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2342 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2343 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2344
2345 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2346 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2347}
2348
2349static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2350 struct ethtool_link_ksettings *cmd)
2351{
2352 if (!autoneg)
2353 return;
2354
2355 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2356 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2357}
2358
2359static void
2360mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2361 struct ethtool_link_ksettings *cmd)
2362{
2363 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2364 return;
2365
2366 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2367 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2368}
2369
2370static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2371 struct ethtool_link_ksettings *cmd)
2372{
2373 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2374 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2375 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2376 char ptys_pl[MLXSW_REG_PTYS_LEN];
2377 u8 autoneg_status;
2378 bool autoneg;
2379 int err;
2380
2381 autoneg = mlxsw_sp_port->link.autoneg;
Tal Bar8e1ed732018-03-21 09:34:06 +02002382 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002383 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2384 if (err)
2385 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002386 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2387 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002388
2389 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2390
2391 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2392
2393 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2394 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2395 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2396
2397 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2398 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2399 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2400 cmd);
2401
2402 return 0;
2403}
2404
2405static int
2406mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2407 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002408{
2409 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2410 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2411 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002412 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002413 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002414 int err;
2415
Tal Bar8e1ed732018-03-21 09:34:06 +02002416 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002417 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002418 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002419 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002420 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002421
2422 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2423 eth_proto_new = autoneg ?
2424 mlxsw_sp_to_ptys_advert_link(cmd) :
2425 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002426
2427 eth_proto_new = eth_proto_new & eth_proto_cap;
2428 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002429 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002430 return -EINVAL;
2431 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002432
Elad Raz401c8b42016-10-28 21:35:52 +02002433 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
Tal Bar8e1ed732018-03-21 09:34:06 +02002434 eth_proto_new, autoneg);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002435 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002436 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002437 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002438
Ido Schimmel6277d462016-07-15 11:14:58 +02002439 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002440 return 0;
2441
Ido Schimmel0c83f882016-09-12 13:26:23 +02002442 mlxsw_sp_port->link.autoneg = autoneg;
2443
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002444 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2445 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002446
2447 return 0;
2448}
2449
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002450static int mlxsw_sp_flash_device(struct net_device *dev,
2451 struct ethtool_flash *flash)
2452{
2453 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2454 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2455 const struct firmware *firmware;
2456 int err;
2457
2458 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2459 return -EOPNOTSUPP;
2460
2461 dev_hold(dev);
2462 rtnl_unlock();
2463
2464 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2465 if (err)
2466 goto out;
2467 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2468 release_firmware(firmware);
2469out:
2470 rtnl_lock();
2471 dev_put(dev);
2472 return err;
2473}
2474
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002475#define MLXSW_SP_I2C_ADDR_LOW 0x50
2476#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2477#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002478
2479static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2480 u16 offset, u16 size, void *data,
2481 unsigned int *p_read_size)
2482{
2483 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2484 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2485 char mcia_pl[MLXSW_REG_MCIA_LEN];
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002486 u16 i2c_addr;
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002487 int status;
2488 int err;
2489
2490 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002491
2492 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2493 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2494 /* Cross pages read, read until offset 256 in low page */
2495 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2496
2497 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2498 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2499 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2500 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2501 }
2502
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002503 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002504 0, 0, offset, size, i2c_addr);
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002505
2506 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2507 if (err)
2508 return err;
2509
2510 status = mlxsw_reg_mcia_status_get(mcia_pl);
2511 if (status)
2512 return -EIO;
2513
2514 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2515 memcpy(data, eeprom_tmp, size);
2516 *p_read_size = size;
2517
2518 return 0;
2519}
2520
2521enum mlxsw_sp_eeprom_module_info_rev_id {
2522 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2523 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2524 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2525};
2526
2527enum mlxsw_sp_eeprom_module_info_id {
2528 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2529 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2530 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2531 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2532};
2533
2534enum mlxsw_sp_eeprom_module_info {
2535 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2536 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2537 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2538};
2539
2540static int mlxsw_sp_get_module_info(struct net_device *netdev,
2541 struct ethtool_modinfo *modinfo)
2542{
2543 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2544 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2545 u8 module_rev_id, module_id;
2546 unsigned int read_size;
2547 int err;
2548
2549 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2550 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2551 module_info, &read_size);
2552 if (err)
2553 return err;
2554
2555 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2556 return -EIO;
2557
2558 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2559 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2560
2561 switch (module_id) {
2562 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2563 modinfo->type = ETH_MODULE_SFF_8436;
2564 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2565 break;
2566 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2567 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2568 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2569 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2570 modinfo->type = ETH_MODULE_SFF_8636;
2571 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2572 } else {
2573 modinfo->type = ETH_MODULE_SFF_8436;
2574 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2575 }
2576 break;
2577 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2578 modinfo->type = ETH_MODULE_SFF_8472;
2579 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2580 break;
2581 default:
2582 return -EINVAL;
2583 }
2584
2585 return 0;
2586}
2587
2588static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2589 struct ethtool_eeprom *ee,
2590 u8 *data)
2591{
2592 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2593 int offset = ee->offset;
2594 unsigned int read_size;
2595 int i = 0;
2596 int err;
2597
2598 if (!ee->len)
2599 return -EINVAL;
2600
2601 memset(data, 0, ee->len);
2602
2603 while (i < ee->len) {
2604 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2605 ee->len - i, data + i,
2606 &read_size);
2607 if (err) {
2608 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2609 return err;
2610 }
2611
2612 i += read_size;
2613 offset += read_size;
2614 }
2615
2616 return 0;
2617}
2618
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002619static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2620 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2621 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002622 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2623 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002624 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002625 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002626 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2627 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002628 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2629 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002630 .flash_device = mlxsw_sp_flash_device,
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002631 .get_module_info = mlxsw_sp_get_module_info,
2632 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002633};
2634
Ido Schimmel18f1e702016-02-26 17:32:31 +01002635static int
2636mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2637{
2638 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2639 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2640 char ptys_pl[MLXSW_REG_PTYS_LEN];
2641 u32 eth_proto_admin;
2642
2643 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002644 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
Tal Bar8e1ed732018-03-21 09:34:06 +02002645 eth_proto_admin, mlxsw_sp_port->link.autoneg);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002646 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2647}
2648
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002649int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2650 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2651 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002652{
2653 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2654 char qeec_pl[MLXSW_REG_QEEC_LEN];
2655
2656 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2657 next_index);
2658 mlxsw_reg_qeec_de_set(qeec_pl, true);
2659 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2660 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2661 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2662}
2663
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002664int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2665 enum mlxsw_reg_qeec_hr hr, u8 index,
2666 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002667{
2668 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2669 char qeec_pl[MLXSW_REG_QEEC_LEN];
2670
2671 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2672 next_index);
2673 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2674 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2675 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2676}
2677
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002678int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2679 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002680{
2681 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2682 char qtct_pl[MLXSW_REG_QTCT_LEN];
2683
2684 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2685 tclass);
2686 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2687}
2688
2689static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2690{
2691 int err, i;
2692
2693 /* Setup the elements hierarcy, so that each TC is linked to
2694 * one subgroup, which are all member in the same group.
2695 */
2696 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2697 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2698 0);
2699 if (err)
2700 return err;
2701 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2702 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2703 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2704 0, false, 0);
2705 if (err)
2706 return err;
2707 }
2708 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2709 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2710 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2711 false, 0);
2712 if (err)
2713 return err;
2714 }
2715
2716 /* Make sure the max shaper is disabled in all hierarcies that
2717 * support it.
2718 */
2719 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2720 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2721 MLXSW_REG_QEEC_MAS_DIS);
2722 if (err)
2723 return err;
2724 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2725 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2726 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2727 i, 0,
2728 MLXSW_REG_QEEC_MAS_DIS);
2729 if (err)
2730 return err;
2731 }
2732 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2733 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2734 MLXSW_REG_QEEC_HIERARCY_TC,
2735 i, i,
2736 MLXSW_REG_QEEC_MAS_DIS);
2737 if (err)
2738 return err;
2739 }
2740
2741 /* Map all priorities to traffic class 0. */
2742 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2743 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2744 if (err)
2745 return err;
2746 }
2747
2748 return 0;
2749}
2750
Ido Schimmel5b153852017-06-08 08:47:44 +02002751static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2752 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002753{
Ido Schimmelc57529e2017-05-26 08:37:31 +02002754 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002755 struct mlxsw_sp_port *mlxsw_sp_port;
2756 struct net_device *dev;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002757 int err;
2758
Ido Schimmel5b153852017-06-08 08:47:44 +02002759 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2760 if (err) {
2761 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2762 local_port);
2763 return err;
2764 }
2765
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002766 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
Ido Schimmel5b153852017-06-08 08:47:44 +02002767 if (!dev) {
2768 err = -ENOMEM;
2769 goto err_alloc_etherdev;
2770 }
Jiri Pirkof20a91f2016-10-27 15:13:00 +02002771 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002772 mlxsw_sp_port = netdev_priv(dev);
2773 mlxsw_sp_port->dev = dev;
2774 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2775 mlxsw_sp_port->local_port = local_port;
Ido Schimmelc57529e2017-05-26 08:37:31 +02002776 mlxsw_sp_port->pvid = 1;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002777 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02002778 mlxsw_sp_port->mapping.module = module;
2779 mlxsw_sp_port->mapping.width = width;
2780 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002781 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02002782 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02002783 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002784
2785 mlxsw_sp_port->pcpu_stats =
2786 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2787 if (!mlxsw_sp_port->pcpu_stats) {
2788 err = -ENOMEM;
2789 goto err_alloc_stats;
2790 }
2791
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002792 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2793 GFP_KERNEL);
2794 if (!mlxsw_sp_port->sample) {
2795 err = -ENOMEM;
2796 goto err_alloc_sample;
2797 }
2798
Nogah Frankel9deef432017-10-26 10:55:32 +02002799 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002800 &update_stats_cache);
2801
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002802 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2803 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2804
Ido Schimmel2e915e02017-06-08 08:47:45 +02002805 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
Ido Schimmel5b153852017-06-08 08:47:44 +02002806 if (err) {
2807 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2808 mlxsw_sp_port->local_port);
2809 goto err_port_module_map;
2810 }
2811
Ido Schimmel3247ff22016-09-08 08:16:02 +02002812 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2813 if (err) {
2814 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2815 mlxsw_sp_port->local_port);
2816 goto err_port_swid_set;
2817 }
2818
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002819 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2820 if (err) {
2821 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2822 mlxsw_sp_port->local_port);
2823 goto err_dev_addr_init;
2824 }
2825
2826 netif_carrier_off(dev);
2827
2828 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02002829 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2830 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002831
Jarod Wilsond894be52016-10-20 13:55:16 -04002832 dev->min_mtu = 0;
2833 dev->max_mtu = ETH_MAX_MTU;
2834
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002835 /* Each packet needs to have a Tx header (metadata) on top all other
2836 * headers.
2837 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02002838 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002839
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002840 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2841 if (err) {
2842 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2843 mlxsw_sp_port->local_port);
2844 goto err_port_system_port_mapping_set;
2845 }
2846
Ido Schimmel18f1e702016-02-26 17:32:31 +01002847 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2848 if (err) {
2849 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2850 mlxsw_sp_port->local_port);
2851 goto err_port_speed_by_width_set;
2852 }
2853
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002854 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2855 if (err) {
2856 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2857 mlxsw_sp_port->local_port);
2858 goto err_port_mtu_set;
2859 }
2860
2861 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2862 if (err)
2863 goto err_port_admin_status_set;
2864
2865 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2866 if (err) {
2867 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2868 mlxsw_sp_port->local_port);
2869 goto err_port_buffers_init;
2870 }
2871
Ido Schimmel90183b92016-04-06 17:10:08 +02002872 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2873 if (err) {
2874 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2875 mlxsw_sp_port->local_port);
2876 goto err_port_ets_init;
2877 }
2878
Ido Schimmelf00817d2016-04-06 17:10:09 +02002879 /* ETS and buffers must be initialized before DCB. */
2880 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2881 if (err) {
2882 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2883 mlxsw_sp_port->local_port);
2884 goto err_port_dcb_init;
2885 }
2886
Ido Schimmela1107482017-05-26 08:37:39 +02002887 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
Ido Schimmel45a4a162017-05-16 19:38:35 +02002888 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02002889 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
Ido Schimmel45a4a162017-05-16 19:38:35 +02002890 mlxsw_sp_port->local_port);
Ido Schimmela1107482017-05-26 08:37:39 +02002891 goto err_port_fids_init;
Ido Schimmel45a4a162017-05-16 19:38:35 +02002892 }
2893
Nogah Frankel371b4372018-01-10 14:59:57 +01002894 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
2895 if (err) {
2896 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
2897 mlxsw_sp_port->local_port);
2898 goto err_port_qdiscs_init;
2899 }
2900
Ido Schimmelc57529e2017-05-26 08:37:31 +02002901 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
2902 if (IS_ERR(mlxsw_sp_port_vlan)) {
2903 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
Ido Schimmel05978482016-08-17 16:39:30 +02002904 mlxsw_sp_port->local_port);
Wei Yongjund86fd112017-11-06 11:11:28 +00002905 err = PTR_ERR(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002906 goto err_port_vlan_get;
Ido Schimmel05978482016-08-17 16:39:30 +02002907 }
2908
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002909 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02002910 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002911 err = register_netdev(dev);
2912 if (err) {
2913 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2914 mlxsw_sp_port->local_port);
2915 goto err_register_netdev;
2916 }
2917
Elad Razd808c7e2016-10-28 21:35:57 +02002918 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
Jiri Pirkob9ffcba2018-05-18 09:29:00 +02002919 mlxsw_sp_port, dev, module + 1,
2920 mlxsw_sp_port->split, lane / width);
Nogah Frankel9deef432017-10-26 10:55:32 +02002921 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002922 return 0;
2923
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002924err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02002925 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002926 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002927 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
2928err_port_vlan_get:
Nogah Frankel371b4372018-01-10 14:59:57 +01002929 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
2930err_port_qdiscs_init:
Ido Schimmela1107482017-05-26 08:37:39 +02002931 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
2932err_port_fids_init:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03002933 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002934err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02002935err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002936err_port_buffers_init:
2937err_port_admin_status_set:
2938err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01002939err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002940err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002941err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02002942 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2943err_port_swid_set:
Ido Schimmel2e915e02017-06-08 08:47:45 +02002944 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Ido Schimmel5b153852017-06-08 08:47:44 +02002945err_port_module_map:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002946 kfree(mlxsw_sp_port->sample);
2947err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002948 free_percpu(mlxsw_sp_port->pcpu_stats);
2949err_alloc_stats:
2950 free_netdev(dev);
Ido Schimmel5b153852017-06-08 08:47:44 +02002951err_alloc_etherdev:
Jiri Pirko67963a32016-10-28 21:35:55 +02002952 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2953 return err;
2954}
2955
Ido Schimmel5b153852017-06-08 08:47:44 +02002956static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002957{
2958 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2959
Nogah Frankel9deef432017-10-26 10:55:32 +02002960 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02002961 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002962 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02002963 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002964 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002965 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Nogah Frankel371b4372018-01-10 14:59:57 +01002966 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
Ido Schimmela1107482017-05-26 08:37:39 +02002967 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002968 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01002969 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
Ido Schimmel2e915e02017-06-08 08:47:45 +02002970 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002971 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01002972 free_percpu(mlxsw_sp_port->pcpu_stats);
Ido Schimmel31a08a52017-05-26 08:37:26 +02002973 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002974 free_netdev(mlxsw_sp_port->dev);
Jiri Pirko67963a32016-10-28 21:35:55 +02002975 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2976}
2977
Jiri Pirkof83e2102016-10-28 21:35:49 +02002978static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2979{
2980 return mlxsw_sp->ports[local_port] != NULL;
2981}
2982
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002983static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2984{
2985 int i;
2986
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002987 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002988 if (mlxsw_sp_port_created(mlxsw_sp, i))
2989 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002990 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002991 kfree(mlxsw_sp->ports);
2992}
2993
2994static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2995{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002996 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02002997 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002998 size_t alloc_size;
2999 int i;
3000 int err;
3001
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003002 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003003 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3004 if (!mlxsw_sp->ports)
3005 return -ENOMEM;
3006
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003007 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3008 GFP_KERNEL);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003009 if (!mlxsw_sp->port_to_module) {
3010 err = -ENOMEM;
3011 goto err_port_to_module_alloc;
3012 }
3013
3014 for (i = 1; i < max_ports; i++) {
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003015 /* Mark as invalid */
3016 mlxsw_sp->port_to_module[i] = -1;
3017
Ido Schimmel558c2d52016-02-26 17:32:29 +01003018 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003019 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01003020 if (err)
3021 goto err_port_module_info_get;
3022 if (!width)
3023 continue;
3024 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02003025 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3026 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003027 if (err)
3028 goto err_port_create;
3029 }
3030 return 0;
3031
3032err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01003033err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003034 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003035 if (mlxsw_sp_port_created(mlxsw_sp, i))
3036 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003037 kfree(mlxsw_sp->port_to_module);
3038err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003039 kfree(mlxsw_sp->ports);
3040 return err;
3041}
3042
Ido Schimmel18f1e702016-02-26 17:32:31 +01003043static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3044{
3045 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3046
3047 return local_port - offset;
3048}
3049
Ido Schimmelbe945352016-06-09 09:51:39 +02003050static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3051 u8 module, unsigned int count)
3052{
3053 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3054 int err, i;
3055
3056 for (i = 0; i < count; i++) {
Ido Schimmelbe945352016-06-09 09:51:39 +02003057 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02003058 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02003059 if (err)
3060 goto err_port_create;
3061 }
3062
3063 return 0;
3064
3065err_port_create:
3066 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003067 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3068 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02003069 return err;
3070}
3071
3072static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3073 u8 base_port, unsigned int count)
3074{
3075 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3076 int i;
3077
3078 /* Split by four means we need to re-create two ports, otherwise
3079 * only one.
3080 */
3081 count = count / 2;
3082
3083 for (i = 0; i < count; i++) {
3084 local_port = base_port + i * 2;
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003085 if (mlxsw_sp->port_to_module[local_port] < 0)
3086 continue;
Ido Schimmelbe945352016-06-09 09:51:39 +02003087 module = mlxsw_sp->port_to_module[local_port];
3088
Ido Schimmelbe945352016-06-09 09:51:39 +02003089 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003090 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003091 }
3092}
3093
Jiri Pirkob2f10572016-04-08 19:11:23 +02003094static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
David Ahern3fcc7732018-06-05 08:14:11 -07003095 unsigned int count,
3096 struct netlink_ext_ack *extack)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003097{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003098 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003099 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003100 u8 module, cur_width, base_port;
3101 int i;
3102 int err;
3103
3104 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3105 if (!mlxsw_sp_port) {
3106 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3107 local_port);
David Ahern3fcc7732018-06-05 08:14:11 -07003108 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003109 return -EINVAL;
3110 }
3111
Ido Schimmeld664b412016-06-09 09:51:40 +02003112 module = mlxsw_sp_port->mapping.module;
3113 cur_width = mlxsw_sp_port->mapping.width;
3114
Ido Schimmel18f1e702016-02-26 17:32:31 +01003115 if (count != 2 && count != 4) {
3116 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
David Ahern3fcc7732018-06-05 08:14:11 -07003117 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003118 return -EINVAL;
3119 }
3120
Ido Schimmel18f1e702016-02-26 17:32:31 +01003121 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3122 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
David Ahern3fcc7732018-06-05 08:14:11 -07003123 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003124 return -EINVAL;
3125 }
3126
3127 /* Make sure we have enough slave (even) ports for the split. */
3128 if (count == 2) {
3129 base_port = local_port;
3130 if (mlxsw_sp->ports[base_port + 1]) {
3131 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
David Ahern3fcc7732018-06-05 08:14:11 -07003132 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003133 return -EINVAL;
3134 }
3135 } else {
3136 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3137 if (mlxsw_sp->ports[base_port + 1] ||
3138 mlxsw_sp->ports[base_port + 3]) {
3139 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
David Ahern3fcc7732018-06-05 08:14:11 -07003140 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003141 return -EINVAL;
3142 }
3143 }
3144
3145 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003146 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3147 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003148
Ido Schimmelbe945352016-06-09 09:51:39 +02003149 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3150 if (err) {
3151 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3152 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003153 }
3154
3155 return 0;
3156
Ido Schimmelbe945352016-06-09 09:51:39 +02003157err_port_split_create:
3158 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003159 return err;
3160}
3161
David Ahern3fcc7732018-06-05 08:14:11 -07003162static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port,
3163 struct netlink_ext_ack *extack)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003164{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003165 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003166 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003167 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003168 unsigned int count;
3169 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003170
3171 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3172 if (!mlxsw_sp_port) {
3173 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3174 local_port);
David Ahern3fcc7732018-06-05 08:14:11 -07003175 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003176 return -EINVAL;
3177 }
3178
3179 if (!mlxsw_sp_port->split) {
David Ahern3fcc7732018-06-05 08:14:11 -07003180 netdev_err(mlxsw_sp_port->dev, "Port was not split\n");
3181 NL_SET_ERR_MSG_MOD(extack, "Port was not split");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003182 return -EINVAL;
3183 }
3184
Ido Schimmeld664b412016-06-09 09:51:40 +02003185 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003186 count = cur_width == 1 ? 4 : 2;
3187
3188 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3189
3190 /* Determine which ports to remove. */
3191 if (count == 2 && local_port >= base_port + 2)
3192 base_port = base_port + 2;
3193
3194 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003195 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3196 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003197
Ido Schimmelbe945352016-06-09 09:51:39 +02003198 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003199
3200 return 0;
3201}
3202
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003203static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3204 char *pude_pl, void *priv)
3205{
3206 struct mlxsw_sp *mlxsw_sp = priv;
3207 struct mlxsw_sp_port *mlxsw_sp_port;
3208 enum mlxsw_reg_pude_oper_status status;
3209 u8 local_port;
3210
3211 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3212 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003213 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003214 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003215
3216 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3217 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3218 netdev_info(mlxsw_sp_port->dev, "link up\n");
3219 netif_carrier_on(mlxsw_sp_port->dev);
3220 } else {
3221 netdev_info(mlxsw_sp_port->dev, "link down\n");
3222 netif_carrier_off(mlxsw_sp_port->dev);
3223 }
3224}
3225
Nogah Frankel14eeda92016-11-25 10:33:32 +01003226static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3227 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003228{
3229 struct mlxsw_sp *mlxsw_sp = priv;
3230 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3231 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3232
3233 if (unlikely(!mlxsw_sp_port)) {
3234 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3235 local_port);
3236 return;
3237 }
3238
3239 skb->dev = mlxsw_sp_port->dev;
3240
3241 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3242 u64_stats_update_begin(&pcpu_stats->syncp);
3243 pcpu_stats->rx_packets++;
3244 pcpu_stats->rx_bytes += skb->len;
3245 u64_stats_update_end(&pcpu_stats->syncp);
3246
3247 skb->protocol = eth_type_trans(skb, skb->dev);
3248 netif_receive_skb(skb);
3249}
3250
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003251static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3252 void *priv)
3253{
3254 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003255 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003256}
3257
Yotam Gigia0040c82017-10-03 09:58:10 +02003258static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3259 u8 local_port, void *priv)
3260{
3261 skb->offload_mr_fwd_mark = 1;
3262 skb->offload_fwd_mark = 1;
3263 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3264}
3265
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003266static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3267 void *priv)
3268{
3269 struct mlxsw_sp *mlxsw_sp = priv;
3270 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3271 struct psample_group *psample_group;
3272 u32 size;
3273
3274 if (unlikely(!mlxsw_sp_port)) {
3275 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3276 local_port);
3277 goto out;
3278 }
3279 if (unlikely(!mlxsw_sp_port->sample)) {
3280 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3281 local_port);
3282 goto out;
3283 }
3284
3285 size = mlxsw_sp_port->sample->truncate ?
3286 mlxsw_sp_port->sample->trunc_size : skb->len;
3287
3288 rcu_read_lock();
3289 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3290 if (!psample_group)
3291 goto out_unlock;
3292 psample_sample_packet(psample_group, skb, size,
3293 mlxsw_sp_port->dev->ifindex, 0,
3294 mlxsw_sp_port->sample->rate);
3295out_unlock:
3296 rcu_read_unlock();
3297out:
3298 consume_skb(skb);
3299}
3300
Nogah Frankel117b0da2016-11-25 10:33:44 +01003301#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003302 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003303 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003304
Nogah Frankel117b0da2016-11-25 10:33:44 +01003305#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003306 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003307 _is_ctrl, SP_##_trap_group, DISCARD)
3308
Yotam Gigia0040c82017-10-03 09:58:10 +02003309#define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3310 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3311 _is_ctrl, SP_##_trap_group, DISCARD)
3312
Nogah Frankel117b0da2016-11-25 10:33:44 +01003313#define MLXSW_SP_EVENTL(_func, _trap_id) \
3314 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003315
Nogah Frankel45449132016-11-25 10:33:35 +01003316static const struct mlxsw_listener mlxsw_sp_listener[] = {
3317 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003318 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003319 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003320 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3321 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3322 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3323 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3324 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3325 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3326 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3327 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3328 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3329 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3330 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003331 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003332 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3333 false),
3334 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3335 false),
3336 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3337 false),
3338 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3339 false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003340 /* L3 traps */
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003341 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3342 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3343 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003344 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003345 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3346 false),
3347 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3348 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3349 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3350 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3351 false),
3352 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3353 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3354 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003355 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003356 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3357 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3358 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3359 false),
3360 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3361 false),
3362 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3363 false),
3364 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3365 false),
3366 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3367 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3368 false),
3369 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3370 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
Ido Schimmel7607dd32017-07-17 14:15:30 +02003371 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003372 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
Petr Machata86484de2017-09-02 23:49:27 +02003373 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003374 /* PKT Sample trap */
3375 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
Jiri Pirko0db7b382017-06-06 14:12:05 +02003376 false, SP_IP2ME, DISCARD),
3377 /* ACL trap */
3378 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
Yotam Gigib48cfc82017-09-19 10:00:20 +02003379 /* Multicast Router Traps */
3380 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
Yuval Mintz6a170d32018-03-26 15:01:45 +03003381 MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false),
Yotam Gigib48cfc82017-09-19 10:00:20 +02003382 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3383 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
Yotam Gigia0040c82017-10-03 09:58:10 +02003384 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003385};
3386
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003387static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3388{
3389 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3390 enum mlxsw_reg_qpcr_ir_units ir_units;
3391 int max_cpu_policers;
3392 bool is_bytes;
3393 u8 burst_size;
3394 u32 rate;
3395 int i, err;
3396
3397 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3398 return -EIO;
3399
3400 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3401
3402 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3403 for (i = 0; i < max_cpu_policers; i++) {
3404 is_bytes = false;
3405 switch (i) {
3406 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3407 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3408 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3409 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003410 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3411 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003412 rate = 128;
3413 burst_size = 7;
3414 break;
3415 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003416 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003417 rate = 16 * 1024;
3418 burst_size = 10;
3419 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003420 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003421 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3422 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003423 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003424 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3425 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003426 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003427 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003428 rate = 1024;
3429 burst_size = 7;
3430 break;
3431 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3432 is_bytes = true;
3433 rate = 4 * 1024;
3434 burst_size = 4;
3435 break;
3436 default:
3437 continue;
3438 }
3439
3440 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3441 burst_size);
3442 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3443 if (err)
3444 return err;
3445 }
3446
3447 return 0;
3448}
3449
Nogah Frankel579c82e2016-11-25 10:33:42 +01003450static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003451{
3452 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003453 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003454 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003455 int max_trap_groups;
3456 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003457 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003458 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003459
3460 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3461 return -EIO;
3462
3463 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003464 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003465
3466 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003467 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003468 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003469 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3470 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3471 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3472 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003473 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003474 priority = 5;
3475 tc = 5;
3476 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003477 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003478 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3479 priority = 4;
3480 tc = 4;
3481 break;
3482 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3483 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003484 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003485 priority = 3;
3486 tc = 3;
3487 break;
3488 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003489 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003490 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003491 priority = 2;
3492 tc = 2;
3493 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003494 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003495 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3496 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003497 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003498 priority = 1;
3499 tc = 1;
3500 break;
3501 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003502 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3503 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003504 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003505 break;
3506 default:
3507 continue;
3508 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003509
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003510 if (max_cpu_policers <= policer_id &&
3511 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3512 return -EIO;
3513
3514 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003515 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3516 if (err)
3517 return err;
3518 }
3519
3520 return 0;
3521}
3522
3523static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3524{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003525 int i;
3526 int err;
3527
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003528 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3529 if (err)
3530 return err;
3531
Nogah Frankel579c82e2016-11-25 10:33:42 +01003532 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003533 if (err)
3534 return err;
3535
Nogah Frankel45449132016-11-25 10:33:35 +01003536 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003537 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003538 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003539 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003540 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003541 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003542
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003543 }
3544 return 0;
3545
Nogah Frankel45449132016-11-25 10:33:35 +01003546err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003547 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003548 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003549 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003550 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003551 }
3552 return err;
3553}
3554
3555static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3556{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003557 int i;
3558
Nogah Frankel45449132016-11-25 10:33:35 +01003559 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003560 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003561 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003562 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003563 }
3564}
3565
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003566static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3567{
3568 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003569 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003570
3571 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3572 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3573 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3574 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3575 MLXSW_REG_SLCR_LAG_HASH_SIP |
3576 MLXSW_REG_SLCR_LAG_HASH_DIP |
3577 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3578 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3579 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003580 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3581 if (err)
3582 return err;
3583
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003584 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3585 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003586 return -EIO;
3587
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003588 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003589 sizeof(struct mlxsw_sp_upper),
3590 GFP_KERNEL);
3591 if (!mlxsw_sp->lags)
3592 return -ENOMEM;
3593
3594 return 0;
3595}
3596
3597static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3598{
3599 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003600}
3601
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003602static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3603{
3604 char htgt_pl[MLXSW_REG_HTGT_LEN];
3605
Nogah Frankel579c82e2016-11-25 10:33:42 +01003606 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3607 MLXSW_REG_HTGT_INVALID_POLICER,
3608 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3609 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003610 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3611}
3612
Petr Machatac30f5d02017-10-16 16:26:35 +02003613static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3614 unsigned long event, void *ptr);
3615
Jiri Pirkob2f10572016-04-08 19:11:23 +02003616static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003617 const struct mlxsw_bus_info *mlxsw_bus_info)
3618{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003619 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003620 int err;
3621
3622 mlxsw_sp->core = mlxsw_core;
3623 mlxsw_sp->bus_info = mlxsw_bus_info;
3624
Yotam Gigi6b742192017-05-23 21:56:29 +02003625 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3626 if (err) {
3627 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3628 return err;
3629 }
3630
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003631 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3632 if (err) {
3633 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3634 return err;
3635 }
3636
Ido Schimmela875a2e2017-10-22 23:11:44 +02003637 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3638 if (err) {
3639 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3640 return err;
3641 }
3642
Ido Schimmela1107482017-05-26 08:37:39 +02003643 err = mlxsw_sp_fids_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003644 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003645 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
Ido Schimmela875a2e2017-10-22 23:11:44 +02003646 goto err_fids_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003647 }
3648
Ido Schimmela1107482017-05-26 08:37:39 +02003649 err = mlxsw_sp_traps_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003650 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003651 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3652 goto err_traps_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003653 }
3654
3655 err = mlxsw_sp_buffers_init(mlxsw_sp);
3656 if (err) {
3657 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3658 goto err_buffers_init;
3659 }
3660
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003661 err = mlxsw_sp_lag_init(mlxsw_sp);
3662 if (err) {
3663 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3664 goto err_lag_init;
3665 }
3666
Petr Machatacda880de2018-04-29 10:56:11 +03003667 /* Initialize SPAN before router and switchdev, so that those components
3668 * can call mlxsw_sp_span_respin().
3669 */
3670 err = mlxsw_sp_span_init(mlxsw_sp);
3671 if (err) {
3672 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3673 goto err_span_init;
3674 }
3675
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003676 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3677 if (err) {
3678 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3679 goto err_switchdev_init;
3680 }
3681
Yotam Gigie2b2d352017-09-19 10:00:08 +02003682 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3683 if (err) {
3684 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3685 goto err_counter_pool_init;
3686 }
3687
Yotam Gigid3b939b2017-09-19 10:00:09 +02003688 err = mlxsw_sp_afa_init(mlxsw_sp);
3689 if (err) {
3690 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3691 goto err_afa_init;
3692 }
3693
Ido Schimmel464dce12016-07-02 11:00:15 +02003694 err = mlxsw_sp_router_init(mlxsw_sp);
3695 if (err) {
3696 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3697 goto err_router_init;
3698 }
3699
Petr Machata803335a2018-02-27 14:53:46 +01003700 /* Initialize netdevice notifier after router and SPAN is initialized,
3701 * so that the event handler can use router structures and call SPAN
3702 * respin.
Petr Machatac30f5d02017-10-16 16:26:35 +02003703 */
3704 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3705 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3706 if (err) {
3707 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3708 goto err_netdev_notifier;
3709 }
3710
Jiri Pirko22a67762017-02-03 10:29:07 +01003711 err = mlxsw_sp_acl_init(mlxsw_sp);
3712 if (err) {
3713 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3714 goto err_acl_init;
3715 }
3716
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003717 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3718 if (err) {
3719 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3720 goto err_dpipe_init;
3721 }
3722
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003723 err = mlxsw_sp_ports_create(mlxsw_sp);
3724 if (err) {
3725 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3726 goto err_ports_create;
3727 }
3728
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003729 return 0;
3730
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003731err_ports_create:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003732 mlxsw_sp_dpipe_fini(mlxsw_sp);
3733err_dpipe_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01003734 mlxsw_sp_acl_fini(mlxsw_sp);
3735err_acl_init:
Petr Machatac30f5d02017-10-16 16:26:35 +02003736 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3737err_netdev_notifier:
Ido Schimmel464dce12016-07-02 11:00:15 +02003738 mlxsw_sp_router_fini(mlxsw_sp);
3739err_router_init:
Yotam Gigid3b939b2017-09-19 10:00:09 +02003740 mlxsw_sp_afa_fini(mlxsw_sp);
3741err_afa_init:
Yotam Gigie2b2d352017-09-19 10:00:08 +02003742 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3743err_counter_pool_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003744 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003745err_switchdev_init:
Petr Machatacda880de2018-04-29 10:56:11 +03003746 mlxsw_sp_span_fini(mlxsw_sp);
3747err_span_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003748 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003749err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02003750 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003751err_buffers_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003752 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003753err_traps_init:
3754 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003755err_fids_init:
3756 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003757 return err;
3758}
3759
Jiri Pirkob2f10572016-04-08 19:11:23 +02003760static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003761{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003762 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003763
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003764 mlxsw_sp_ports_remove(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003765 mlxsw_sp_dpipe_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01003766 mlxsw_sp_acl_fini(mlxsw_sp);
Petr Machatac30f5d02017-10-16 16:26:35 +02003767 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
Ido Schimmel464dce12016-07-02 11:00:15 +02003768 mlxsw_sp_router_fini(mlxsw_sp);
Yotam Gigid3b939b2017-09-19 10:00:09 +02003769 mlxsw_sp_afa_fini(mlxsw_sp);
Yotam Gigie2b2d352017-09-19 10:00:08 +02003770 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003771 mlxsw_sp_switchdev_fini(mlxsw_sp);
Petr Machatacda880de2018-04-29 10:56:11 +03003772 mlxsw_sp_span_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003773 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02003774 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003775 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003776 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003777 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003778}
3779
Bhumika Goyal159fe882017-08-11 19:10:42 +05303780static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003781 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01003782 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003783 .used_flood_tables = 1,
3784 .used_flood_mode = 1,
3785 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003786 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003787 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003788 .max_fid_flood_tables = 3,
Ido Schimmela1107482017-05-26 08:37:39 +02003789 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003790 .used_max_ib_mc = 1,
3791 .max_ib_mc = 0,
3792 .used_max_pkey = 1,
3793 .max_pkey = 0,
Jiri Pirko110d2d22018-04-01 17:34:56 +03003794 .used_kvd_sizes = 1,
Ido Schimmelf11fbaf2017-10-22 23:11:49 +02003795 .kvd_hash_single_parts = 59,
3796 .kvd_hash_double_parts = 41,
Jiri Pirkoc6022422016-07-05 11:27:46 +02003797 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003798 .swid_config = {
3799 {
3800 .used_type = 1,
3801 .type = MLXSW_PORT_SWID_TYPE_ETH,
3802 }
3803 },
3804};
3805
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003806static void
Jiri Pirko77d27092018-02-28 13:12:09 +01003807mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
3808 struct devlink_resource_size_params *kvd_size_params,
3809 struct devlink_resource_size_params *linear_size_params,
3810 struct devlink_resource_size_params *hash_double_size_params,
3811 struct devlink_resource_size_params *hash_single_size_params)
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003812{
3813 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3814 KVD_SINGLE_MIN_SIZE);
3815 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3816 KVD_DOUBLE_MIN_SIZE);
3817 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3818 u32 linear_size_min = 0;
3819
Jiri Pirko77d27092018-02-28 13:12:09 +01003820 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
3821 MLXSW_SP_KVD_GRANULARITY,
3822 DEVLINK_RESOURCE_UNIT_ENTRY);
3823 devlink_resource_size_params_init(linear_size_params, linear_size_min,
3824 kvd_size - single_size_min -
3825 double_size_min,
3826 MLXSW_SP_KVD_GRANULARITY,
3827 DEVLINK_RESOURCE_UNIT_ENTRY);
3828 devlink_resource_size_params_init(hash_double_size_params,
3829 double_size_min,
3830 kvd_size - single_size_min -
3831 linear_size_min,
3832 MLXSW_SP_KVD_GRANULARITY,
3833 DEVLINK_RESOURCE_UNIT_ENTRY);
3834 devlink_resource_size_params_init(hash_single_size_params,
3835 single_size_min,
3836 kvd_size - double_size_min -
3837 linear_size_min,
3838 MLXSW_SP_KVD_GRANULARITY,
3839 DEVLINK_RESOURCE_UNIT_ENTRY);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003840}
3841
3842static int mlxsw_sp_resources_register(struct mlxsw_core *mlxsw_core)
3843{
3844 struct devlink *devlink = priv_to_devlink(mlxsw_core);
Jiri Pirko77d27092018-02-28 13:12:09 +01003845 struct devlink_resource_size_params hash_single_size_params;
3846 struct devlink_resource_size_params hash_double_size_params;
3847 struct devlink_resource_size_params linear_size_params;
3848 struct devlink_resource_size_params kvd_size_params;
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003849 u32 kvd_size, single_size, double_size, linear_size;
3850 const struct mlxsw_config_profile *profile;
3851 int err;
3852
3853 profile = &mlxsw_sp_config_profile;
3854 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
3855 return -EIO;
3856
Jiri Pirko77d27092018-02-28 13:12:09 +01003857 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
3858 &linear_size_params,
3859 &hash_double_size_params,
3860 &hash_single_size_params);
3861
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003862 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3863 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
David Ahern14530742018-03-20 19:31:14 -07003864 kvd_size, MLXSW_SP_RESOURCE_KVD,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003865 DEVLINK_RESOURCE_ID_PARENT_TOP,
Jiri Pirkofc56be42018-04-05 22:13:21 +02003866 &kvd_size_params);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003867 if (err)
3868 return err;
3869
3870 linear_size = profile->kvd_linear_size;
3871 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
David Ahern14530742018-03-20 19:31:14 -07003872 linear_size,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003873 MLXSW_SP_RESOURCE_KVD_LINEAR,
3874 MLXSW_SP_RESOURCE_KVD,
Jiri Pirkofc56be42018-04-05 22:13:21 +02003875 &linear_size_params);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003876 if (err)
3877 return err;
3878
Jiri Pirko88d2fbc2018-04-01 17:34:58 +03003879 err = mlxsw_sp_kvdl_resources_register(mlxsw_core);
Arkadi Sharshevsky51d3c082018-02-20 08:44:22 +01003880 if (err)
3881 return err;
3882
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003883 double_size = kvd_size - linear_size;
3884 double_size *= profile->kvd_hash_double_parts;
3885 double_size /= profile->kvd_hash_double_parts +
3886 profile->kvd_hash_single_parts;
Jiri Pirko72779c92018-04-01 17:34:54 +03003887 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003888 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
David Ahern14530742018-03-20 19:31:14 -07003889 double_size,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003890 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3891 MLXSW_SP_RESOURCE_KVD,
Jiri Pirkofc56be42018-04-05 22:13:21 +02003892 &hash_double_size_params);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003893 if (err)
3894 return err;
3895
3896 single_size = kvd_size - double_size - linear_size;
3897 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
David Ahern14530742018-03-20 19:31:14 -07003898 single_size,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003899 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3900 MLXSW_SP_RESOURCE_KVD,
Jiri Pirkofc56be42018-04-05 22:13:21 +02003901 &hash_single_size_params);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003902 if (err)
3903 return err;
3904
3905 return 0;
3906}
3907
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01003908static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
3909 const struct mlxsw_config_profile *profile,
3910 u64 *p_single_size, u64 *p_double_size,
3911 u64 *p_linear_size)
3912{
3913 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3914 u32 double_size;
3915 int err;
3916
3917 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
Jiri Pirko110d2d22018-04-01 17:34:56 +03003918 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01003919 return -EIO;
3920
3921 /* The hash part is what left of the kvd without the
3922 * linear part. It is split to the single size and
3923 * double size by the parts ratio from the profile.
3924 * Both sizes must be a multiplications of the
3925 * granularity from the profile. In case the user
3926 * provided the sizes they are obtained via devlink.
3927 */
3928 err = devlink_resource_size_get(devlink,
3929 MLXSW_SP_RESOURCE_KVD_LINEAR,
3930 p_linear_size);
3931 if (err)
3932 *p_linear_size = profile->kvd_linear_size;
3933
3934 err = devlink_resource_size_get(devlink,
3935 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3936 p_double_size);
3937 if (err) {
3938 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3939 *p_linear_size;
3940 double_size *= profile->kvd_hash_double_parts;
3941 double_size /= profile->kvd_hash_double_parts +
3942 profile->kvd_hash_single_parts;
3943 *p_double_size = rounddown(double_size,
Jiri Pirko72779c92018-04-01 17:34:54 +03003944 MLXSW_SP_KVD_GRANULARITY);
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01003945 }
3946
3947 err = devlink_resource_size_get(devlink,
3948 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3949 p_single_size);
3950 if (err)
3951 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3952 *p_double_size - *p_linear_size;
3953
3954 /* Check results are legal. */
3955 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3956 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
3957 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
3958 return -EIO;
3959
3960 return 0;
3961}
3962
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003963static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02003964 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003965 .priv_size = sizeof(struct mlxsw_sp),
3966 .init = mlxsw_sp_init,
3967 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003968 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003969 .port_split = mlxsw_sp_port_split,
3970 .port_unsplit = mlxsw_sp_port_unsplit,
3971 .sb_pool_get = mlxsw_sp_sb_pool_get,
3972 .sb_pool_set = mlxsw_sp_sb_pool_set,
3973 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3974 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3975 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3976 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3977 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3978 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3979 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3980 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3981 .txhdr_construct = mlxsw_sp_txhdr_construct,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003982 .resources_register = mlxsw_sp_resources_register,
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01003983 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003984 .txhdr_len = MLXSW_TXHDR_LEN,
3985 .profile = &mlxsw_sp_config_profile,
Jiri Pirkoad3f20b2018-04-01 17:34:57 +03003986 .res_query_enabled = true,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003987};
3988
Jiri Pirko22a67762017-02-03 10:29:07 +01003989bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003990{
3991 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3992}
3993
Jiri Pirko1182e532017-03-06 21:25:20 +01003994static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07003995{
Jiri Pirko1182e532017-03-06 21:25:20 +01003996 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07003997 int ret = 0;
3998
3999 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01004000 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07004001 ret = 1;
4002 }
4003
4004 return ret;
4005}
4006
Ido Schimmelc57529e2017-05-26 08:37:31 +02004007struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004008{
Jiri Pirko1182e532017-03-06 21:25:20 +01004009 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004010
4011 if (mlxsw_sp_port_dev_check(dev))
4012 return netdev_priv(dev);
4013
Jiri Pirko1182e532017-03-06 21:25:20 +01004014 mlxsw_sp_port = NULL;
4015 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004016
Jiri Pirko1182e532017-03-06 21:25:20 +01004017 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004018}
4019
Ido Schimmel4724ba562017-03-10 08:53:39 +01004020struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004021{
4022 struct mlxsw_sp_port *mlxsw_sp_port;
4023
4024 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4025 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4026}
4027
Arkadi Sharshevskyaf0613782017-06-08 08:44:20 +02004028struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004029{
Jiri Pirko1182e532017-03-06 21:25:20 +01004030 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004031
4032 if (mlxsw_sp_port_dev_check(dev))
4033 return netdev_priv(dev);
4034
Jiri Pirko1182e532017-03-06 21:25:20 +01004035 mlxsw_sp_port = NULL;
4036 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4037 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004038
Jiri Pirko1182e532017-03-06 21:25:20 +01004039 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004040}
4041
4042struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4043{
4044 struct mlxsw_sp_port *mlxsw_sp_port;
4045
4046 rcu_read_lock();
4047 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4048 if (mlxsw_sp_port)
4049 dev_hold(mlxsw_sp_port->dev);
4050 rcu_read_unlock();
4051 return mlxsw_sp_port;
4052}
4053
4054void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4055{
4056 dev_put(mlxsw_sp_port->dev);
4057}
4058
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004059static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004060{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004061 char sldr_pl[MLXSW_REG_SLDR_LEN];
4062
4063 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4064 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4065}
4066
4067static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4068{
4069 char sldr_pl[MLXSW_REG_SLDR_LEN];
4070
4071 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4072 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4073}
4074
4075static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4076 u16 lag_id, u8 port_index)
4077{
4078 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4079 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4080
4081 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4082 lag_id, port_index);
4083 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4084}
4085
4086static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4087 u16 lag_id)
4088{
4089 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4090 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4091
4092 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4093 lag_id);
4094 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4095}
4096
4097static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4098 u16 lag_id)
4099{
4100 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4101 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4102
4103 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4104 lag_id);
4105 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4106}
4107
4108static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4109 u16 lag_id)
4110{
4111 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4112 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4113
4114 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4115 lag_id);
4116 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4117}
4118
4119static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4120 struct net_device *lag_dev,
4121 u16 *p_lag_id)
4122{
4123 struct mlxsw_sp_upper *lag;
4124 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004125 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004126 int i;
4127
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004128 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4129 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004130 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4131 if (lag->ref_count) {
4132 if (lag->dev == lag_dev) {
4133 *p_lag_id = i;
4134 return 0;
4135 }
4136 } else if (free_lag_id < 0) {
4137 free_lag_id = i;
4138 }
4139 }
4140 if (free_lag_id < 0)
4141 return -EBUSY;
4142 *p_lag_id = free_lag_id;
4143 return 0;
4144}
4145
4146static bool
4147mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4148 struct net_device *lag_dev,
David Aherne58376e2017-10-04 17:48:51 -07004149 struct netdev_lag_upper_info *lag_upper_info,
4150 struct netlink_ext_ack *extack)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004151{
4152 u16 lag_id;
4153
David Aherne58376e2017-10-04 17:48:51 -07004154 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004155 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004156 return false;
David Aherne58376e2017-10-04 17:48:51 -07004157 }
4158 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004159 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004160 return false;
David Aherne58376e2017-10-04 17:48:51 -07004161 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004162 return true;
4163}
4164
4165static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4166 u16 lag_id, u8 *p_port_index)
4167{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004168 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004169 int i;
4170
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004171 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4172 MAX_LAG_MEMBERS);
4173 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004174 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4175 *p_port_index = i;
4176 return 0;
4177 }
4178 }
4179 return -EBUSY;
4180}
4181
4182static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4183 struct net_device *lag_dev)
4184{
4185 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004186 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004187 struct mlxsw_sp_upper *lag;
4188 u16 lag_id;
4189 u8 port_index;
4190 int err;
4191
4192 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4193 if (err)
4194 return err;
4195 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4196 if (!lag->ref_count) {
4197 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4198 if (err)
4199 return err;
4200 lag->dev = lag_dev;
4201 }
4202
4203 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4204 if (err)
4205 return err;
4206 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4207 if (err)
4208 goto err_col_port_add;
4209 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4210 if (err)
4211 goto err_col_port_enable;
4212
4213 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4214 mlxsw_sp_port->local_port);
4215 mlxsw_sp_port->lag_id = lag_id;
4216 mlxsw_sp_port->lagged = 1;
4217 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004218
Ido Schimmelc57529e2017-05-26 08:37:31 +02004219 /* Port is no longer usable as a router interface */
4220 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4221 if (mlxsw_sp_port_vlan->fid)
Ido Schimmela1107482017-05-26 08:37:39 +02004222 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004223
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004224 return 0;
4225
Ido Schimmel51554db2016-05-06 22:18:39 +02004226err_col_port_enable:
4227 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004228err_col_port_add:
4229 if (!lag->ref_count)
4230 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004231 return err;
4232}
4233
Ido Schimmel82e6db02016-06-20 23:04:04 +02004234static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4235 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004236{
4237 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004238 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004239 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004240
4241 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004242 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004243 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4244 WARN_ON(lag->ref_count == 0);
4245
Ido Schimmel82e6db02016-06-20 23:04:04 +02004246 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4247 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004248
Ido Schimmelc57529e2017-05-26 08:37:31 +02004249 /* Any VLANs configured on the port are no longer valid */
4250 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004251
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004252 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004253 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004254
4255 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4256 mlxsw_sp_port->local_port);
4257 mlxsw_sp_port->lagged = 0;
4258 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004259
Ido Schimmelc57529e2017-05-26 08:37:31 +02004260 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4261 /* Make sure untagged frames are allowed to ingress */
4262 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004263}
4264
Jiri Pirko74581202015-12-03 12:12:30 +01004265static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4266 u16 lag_id)
4267{
4268 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4269 char sldr_pl[MLXSW_REG_SLDR_LEN];
4270
4271 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4272 mlxsw_sp_port->local_port);
4273 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4274}
4275
4276static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4277 u16 lag_id)
4278{
4279 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4280 char sldr_pl[MLXSW_REG_SLDR_LEN];
4281
4282 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4283 mlxsw_sp_port->local_port);
4284 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4285}
4286
4287static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4288 bool lag_tx_enabled)
4289{
4290 if (lag_tx_enabled)
4291 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4292 mlxsw_sp_port->lag_id);
4293 else
4294 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4295 mlxsw_sp_port->lag_id);
4296}
4297
4298static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4299 struct netdev_lag_lower_state_info *info)
4300{
4301 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4302}
4303
Jiri Pirko2b94e582017-04-18 16:55:37 +02004304static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4305 bool enable)
4306{
4307 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4308 enum mlxsw_reg_spms_state spms_state;
4309 char *spms_pl;
4310 u16 vid;
4311 int err;
4312
4313 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4314 MLXSW_REG_SPMS_STATE_DISCARDING;
4315
4316 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4317 if (!spms_pl)
4318 return -ENOMEM;
4319 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4320
4321 for (vid = 0; vid < VLAN_N_VID; vid++)
4322 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4323
4324 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4325 kfree(spms_pl);
4326 return err;
4327}
4328
4329static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4330{
Yuval Mintzfccff082017-12-15 08:44:21 +01004331 u16 vid = 1;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004332 int err;
4333
Ido Schimmel4aafc362017-05-26 08:37:25 +02004334 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004335 if (err)
4336 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02004337 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4338 if (err)
4339 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004340 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4341 true, false);
4342 if (err)
4343 goto err_port_vlan_set;
Yuval Mintzfccff082017-12-15 08:44:21 +01004344
4345 for (; vid <= VLAN_N_VID - 1; vid++) {
4346 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4347 vid, false);
4348 if (err)
4349 goto err_vid_learning_set;
4350 }
4351
Jiri Pirko2b94e582017-04-18 16:55:37 +02004352 return 0;
4353
Yuval Mintzfccff082017-12-15 08:44:21 +01004354err_vid_learning_set:
4355 for (vid--; vid >= 1; vid--)
4356 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004357err_port_vlan_set:
4358 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004359err_port_stp_set:
4360 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004361 return err;
4362}
4363
4364static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4365{
Yuval Mintzfccff082017-12-15 08:44:21 +01004366 u16 vid;
4367
4368 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4369 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4370 vid, true);
4371
Jiri Pirko2b94e582017-04-18 16:55:37 +02004372 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4373 false, false);
4374 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004375 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004376}
4377
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004378static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4379 struct net_device *dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004380 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004381{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004382 struct netdev_notifier_changeupper_info *info;
4383 struct mlxsw_sp_port *mlxsw_sp_port;
David Aherne58376e2017-10-04 17:48:51 -07004384 struct netlink_ext_ack *extack;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004385 struct net_device *upper_dev;
4386 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004387 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004388
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004389 mlxsw_sp_port = netdev_priv(dev);
4390 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4391 info = ptr;
David Aherne58376e2017-10-04 17:48:51 -07004392 extack = netdev_notifier_info_to_extack(&info->info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004393
4394 switch (event) {
4395 case NETDEV_PRECHANGEUPPER:
4396 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004397 if (!is_vlan_dev(upper_dev) &&
4398 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004399 !netif_is_bridge_master(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004400 !netif_is_ovs_master(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004401 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004402 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004403 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004404 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004405 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004406 if (netdev_has_any_upper_dev(upper_dev) &&
4407 (!netif_is_bridge_master(upper_dev) ||
4408 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4409 upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004410 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004411 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004412 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004413 if (netif_is_lag_master(upper_dev) &&
4414 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
David Aherne58376e2017-10-04 17:48:51 -07004415 info->upper_info, extack))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004416 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004417 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004418 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004419 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004420 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004421 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004422 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004423 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004424 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004425 }
4426 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004427 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004428 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004429 }
4430 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004431 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004432 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004433 }
Petr Machata47bf9df2018-05-27 09:48:41 +03004434 if (is_vlan_dev(upper_dev) &&
4435 vlan_dev_vlan_id(upper_dev) == 1) {
4436 NL_SET_ERR_MSG_MOD(extack, "Creating a VLAN device with VID 1 is unsupported: VLAN 1 carries untagged traffic");
4437 return -EINVAL;
4438 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004439 break;
4440 case NETDEV_CHANGEUPPER:
4441 upper_dev = info->upper_dev;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004442 if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004443 if (info->linking)
4444 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004445 lower_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004446 upper_dev,
4447 extack);
Ido Schimmel7117a572016-06-20 23:04:06 +02004448 else
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004449 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4450 lower_dev,
4451 upper_dev);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004452 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004453 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004454 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4455 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004456 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004457 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4458 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004459 } else if (netif_is_ovs_master(upper_dev)) {
4460 if (info->linking)
4461 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4462 else
4463 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004464 }
4465 break;
4466 }
4467
Ido Schimmel80bedf12016-06-20 23:03:59 +02004468 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004469}
4470
Jiri Pirko74581202015-12-03 12:12:30 +01004471static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4472 unsigned long event, void *ptr)
4473{
4474 struct netdev_notifier_changelowerstate_info *info;
4475 struct mlxsw_sp_port *mlxsw_sp_port;
4476 int err;
4477
4478 mlxsw_sp_port = netdev_priv(dev);
4479 info = ptr;
4480
4481 switch (event) {
4482 case NETDEV_CHANGELOWERSTATE:
4483 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4484 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4485 info->lower_state_info);
4486 if (err)
4487 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4488 }
4489 break;
4490 }
4491
Ido Schimmel80bedf12016-06-20 23:03:59 +02004492 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004493}
4494
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004495static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4496 struct net_device *port_dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004497 unsigned long event, void *ptr)
4498{
4499 switch (event) {
4500 case NETDEV_PRECHANGEUPPER:
4501 case NETDEV_CHANGEUPPER:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004502 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4503 event, ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004504 case NETDEV_CHANGELOWERSTATE:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004505 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4506 ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004507 }
4508
Ido Schimmel80bedf12016-06-20 23:03:59 +02004509 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004510}
4511
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004512static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4513 unsigned long event, void *ptr)
4514{
4515 struct net_device *dev;
4516 struct list_head *iter;
4517 int ret;
4518
4519 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4520 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004521 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4522 ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004523 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004524 return ret;
4525 }
4526 }
4527
Ido Schimmel80bedf12016-06-20 23:03:59 +02004528 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004529}
4530
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004531static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4532 struct net_device *dev,
4533 unsigned long event, void *ptr,
4534 u16 vid)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004535{
4536 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel90045fc2017-12-25 09:05:33 +01004537 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004538 struct netdev_notifier_changeupper_info *info = ptr;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004539 struct netlink_ext_ack *extack;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004540 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004541 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004542
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004543 extack = netdev_notifier_info_to_extack(&info->info);
4544
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004545 switch (event) {
4546 case NETDEV_PRECHANGEUPPER:
4547 upper_dev = info->upper_dev;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004548 if (!netif_is_bridge_master(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004549 NL_SET_ERR_MSG_MOD(extack, "VLAN devices only support bridge and VRF uppers");
Ido Schimmel80bedf12016-06-20 23:03:59 +02004550 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004551 }
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004552 if (!info->linking)
4553 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004554 if (netdev_has_any_upper_dev(upper_dev) &&
4555 (!netif_is_bridge_master(upper_dev) ||
4556 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4557 upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004558 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004559 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004560 }
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004561 break;
4562 case NETDEV_CHANGEUPPER:
4563 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004564 if (netif_is_bridge_master(upper_dev)) {
4565 if (info->linking)
Ido Schimmelc57529e2017-05-26 08:37:31 +02004566 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4567 vlan_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004568 upper_dev,
4569 extack);
Ido Schimmel1f880612017-03-10 08:53:35 +01004570 else
Ido Schimmelc57529e2017-05-26 08:37:31 +02004571 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4572 vlan_dev,
4573 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004574 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004575 err = -EINVAL;
4576 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004577 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004578 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004579 }
4580
Ido Schimmel80bedf12016-06-20 23:03:59 +02004581 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004582}
4583
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004584static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4585 struct net_device *lag_dev,
4586 unsigned long event,
4587 void *ptr, u16 vid)
Ido Schimmel272c4472015-12-15 16:03:47 +01004588{
4589 struct net_device *dev;
4590 struct list_head *iter;
4591 int ret;
4592
4593 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4594 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004595 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4596 event, ptr,
4597 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004598 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004599 return ret;
4600 }
4601 }
4602
Ido Schimmel80bedf12016-06-20 23:03:59 +02004603 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004604}
4605
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004606static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4607 unsigned long event, void *ptr)
4608{
4609 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4610 u16 vid = vlan_dev_vlan_id(vlan_dev);
4611
Ido Schimmel272c4472015-12-15 16:03:47 +01004612 if (mlxsw_sp_port_dev_check(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004613 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4614 event, ptr, vid);
Ido Schimmel272c4472015-12-15 16:03:47 +01004615 else if (netif_is_lag_master(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004616 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4617 real_dev, event,
4618 ptr, vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004619
Ido Schimmel80bedf12016-06-20 23:03:59 +02004620 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004621}
4622
Ido Schimmelb1e45522017-04-30 19:47:14 +03004623static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4624{
4625 struct netdev_notifier_changeupper_info *info = ptr;
4626
4627 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4628 return false;
4629 return netif_is_l3_master(info->upper_dev);
4630}
4631
Petr Machata00635872017-10-16 16:26:37 +02004632static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004633 unsigned long event, void *ptr)
4634{
4635 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Petr Machata079c9f32018-02-27 14:53:44 +01004636 struct mlxsw_sp_span_entry *span_entry;
Petr Machata00635872017-10-16 16:26:37 +02004637 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004638 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004639
Petr Machata00635872017-10-16 16:26:37 +02004640 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
Petr Machata079c9f32018-02-27 14:53:44 +01004641 if (event == NETDEV_UNREGISTER) {
4642 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
4643 if (span_entry)
4644 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
4645 }
Petr Machata803335a2018-02-27 14:53:46 +01004646 mlxsw_sp_span_respin(mlxsw_sp);
Petr Machata079c9f32018-02-27 14:53:44 +01004647
Petr Machata796ec772017-11-03 10:03:29 +01004648 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
4649 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
4650 event, ptr);
Petr Machata61481f22017-11-03 10:03:41 +01004651 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
4652 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
4653 event, ptr);
Petr Machata00635872017-10-16 16:26:37 +02004654 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004655 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03004656 else if (mlxsw_sp_is_vrf_event(event, ptr))
4657 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004658 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004659 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004660 else if (netif_is_lag_master(dev))
4661 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4662 else if (is_vlan_dev(dev))
4663 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004664
Ido Schimmel80bedf12016-06-20 23:03:59 +02004665 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004666}
4667
David Ahern89d5dd22017-10-18 09:56:55 -07004668static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
4669 .notifier_call = mlxsw_sp_inetaddr_valid_event,
4670};
4671
Ido Schimmel99724c12016-07-04 08:23:14 +02004672static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4673 .notifier_call = mlxsw_sp_inetaddr_event,
David Ahern89d5dd22017-10-18 09:56:55 -07004674};
4675
4676static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
4677 .notifier_call = mlxsw_sp_inet6addr_valid_event,
Ido Schimmel99724c12016-07-04 08:23:14 +02004678};
4679
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004680static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
4681 .notifier_call = mlxsw_sp_inet6addr_event,
4682};
4683
Jiri Pirko1d20d232016-10-27 15:12:59 +02004684static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4685 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4686 {0, },
4687};
4688
4689static struct pci_driver mlxsw_sp_pci_driver = {
4690 .name = mlxsw_sp_driver_name,
4691 .id_table = mlxsw_sp_pci_id_table,
4692};
4693
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004694static int __init mlxsw_sp_module_init(void)
4695{
4696 int err;
4697
David Ahern89d5dd22017-10-18 09:56:55 -07004698 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004699 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004700 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004701 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004702
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004703 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4704 if (err)
4705 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02004706
4707 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4708 if (err)
4709 goto err_pci_driver_register;
4710
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004711 return 0;
4712
Jiri Pirko1d20d232016-10-27 15:12:59 +02004713err_pci_driver_register:
4714 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004715err_core_driver_register:
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004716 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004717 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02004718 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004719 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004720 return err;
4721}
4722
4723static void __exit mlxsw_sp_module_exit(void)
4724{
Jiri Pirko1d20d232016-10-27 15:12:59 +02004725 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004726 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004727 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004728 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004729 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004730 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004731}
4732
4733module_init(mlxsw_sp_module_init);
4734module_exit(mlxsw_sp_module_exit);
4735
4736MODULE_LICENSE("Dual BSD/GPL");
4737MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4738MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02004739MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Yotam Gigi6b742192017-05-23 21:56:29 +02004740MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);