blob: ea72556b9e6a51fa62845c9619227331cbf2298a [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Petr Machata803335a2018-02-27 14:53:46 +01003 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
Jiri Pirko22a67762017-02-03 10:29:07 +01004 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +020056#include <linux/netlink.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020057#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020058#include <net/pkt_cls.h>
59#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020060#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010061#include <net/tc_act/tc_sample.h>
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +020062#include <net/addrconf.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020063
64#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020065#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020066#include "core.h"
67#include "reg.h"
68#include "port.h"
69#include "trap.h"
70#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010071#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020072#include "spectrum_dpipe.h"
Yotam Gigid3b939b2017-09-19 10:00:09 +020073#include "spectrum_acl_flex_actions.h"
Petr Machataa629ef22018-02-13 11:27:48 +010074#include "spectrum_span.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020075#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020076
Yotam Gigi6b742192017-05-23 21:56:29 +020077#define MLXSW_FWREV_MAJOR 13
Tal Bar1c6e1032018-03-21 09:34:05 +020078#define MLXSW_FWREV_MINOR 1620
79#define MLXSW_FWREV_SUBMINOR 192
Yuval Mintzfd5204c2018-01-18 12:55:23 +010080#define MLXSW_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
Yotam Gigi6b742192017-05-23 21:56:29 +020081
82#define MLXSW_SP_FW_FILENAME \
Yotam Gigia4e1ce22017-06-04 16:49:58 +020083 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
Yotam Gigi6b742192017-05-23 21:56:29 +020084 "." __stringify(MLXSW_FWREV_MINOR) \
85 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
86
Jiri Pirko56ade8f2015-10-16 14:01:37 +020087static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
88static const char mlxsw_sp_driver_version[] = "1.0";
89
90/* tx_hdr_version
91 * Tx header version.
92 * Must be set to 1.
93 */
94MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
95
96/* tx_hdr_ctl
97 * Packet control type.
98 * 0 - Ethernet control (e.g. EMADs, LACP)
99 * 1 - Ethernet data
100 */
101MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
102
103/* tx_hdr_proto
104 * Packet protocol type. Must be set to 1 (Ethernet).
105 */
106MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
107
108/* tx_hdr_rx_is_router
109 * Packet is sent from the router. Valid for data packets only.
110 */
111MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
112
113/* tx_hdr_fid_valid
114 * Indicates if the 'fid' field is valid and should be used for
115 * forwarding lookup. Valid for data packets only.
116 */
117MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
118
119/* tx_hdr_swid
120 * Switch partition ID. Must be set to 0.
121 */
122MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
123
124/* tx_hdr_control_tclass
125 * Indicates if the packet should use the control TClass and not one
126 * of the data TClasses.
127 */
128MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
129
130/* tx_hdr_etclass
131 * Egress TClass to be used on the egress device on the egress port.
132 */
133MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
134
135/* tx_hdr_port_mid
136 * Destination local port for unicast packets.
137 * Destination multicast ID for multicast packets.
138 *
139 * Control packets are directed to a specific egress port, while data
140 * packets are transmitted through the CPU port (0) into the switch partition,
141 * where forwarding rules are applied.
142 */
143MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
144
145/* tx_hdr_fid
146 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
147 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
148 * Valid for data packets only.
149 */
150MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
151
152/* tx_hdr_type
153 * 0 - Data packets
154 * 6 - Control packets
155 */
156MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
157
Yotam Gigie5e5c882017-05-23 21:56:27 +0200158struct mlxsw_sp_mlxfw_dev {
159 struct mlxfw_dev mlxfw_dev;
160 struct mlxsw_sp *mlxsw_sp;
161};
162
163static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
164 u16 component_index, u32 *p_max_size,
165 u8 *p_align_bits, u16 *p_max_write_size)
166{
167 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
168 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
169 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
170 char mcqi_pl[MLXSW_REG_MCQI_LEN];
171 int err;
172
173 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
174 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
175 if (err)
176 return err;
177 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
178 p_max_write_size);
179
180 *p_align_bits = max_t(u8, *p_align_bits, 2);
181 *p_max_write_size = min_t(u16, *p_max_write_size,
182 MLXSW_REG_MCDA_MAX_DATA_LEN);
183 return 0;
184}
185
186static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
187{
188 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
189 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
190 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
191 char mcc_pl[MLXSW_REG_MCC_LEN];
192 u8 control_state;
193 int err;
194
195 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
196 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
197 if (err)
198 return err;
199
200 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
201 if (control_state != MLXFW_FSM_STATE_IDLE)
202 return -EBUSY;
203
204 mlxsw_reg_mcc_pack(mcc_pl,
205 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
206 0, *fwhandle, 0);
207 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
208}
209
210static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
211 u32 fwhandle, u16 component_index,
212 u32 component_size)
213{
214 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
215 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
217 char mcc_pl[MLXSW_REG_MCC_LEN];
218
219 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
220 component_index, fwhandle, component_size);
221 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
222}
223
224static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
225 u32 fwhandle, u8 *data, u16 size,
226 u32 offset)
227{
228 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
229 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
230 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
231 char mcda_pl[MLXSW_REG_MCDA_LEN];
232
233 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
234 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
235}
236
237static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
238 u32 fwhandle, u16 component_index)
239{
240 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
241 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
242 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
243 char mcc_pl[MLXSW_REG_MCC_LEN];
244
245 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
246 component_index, fwhandle, 0);
247 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
248}
249
250static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
251{
252 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
253 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
254 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
255 char mcc_pl[MLXSW_REG_MCC_LEN];
256
257 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
258 fwhandle, 0);
259 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
260}
261
262static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
263 enum mlxfw_fsm_state *fsm_state,
264 enum mlxfw_fsm_state_err *fsm_state_err)
265{
266 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
267 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
268 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
269 char mcc_pl[MLXSW_REG_MCC_LEN];
270 u8 control_state;
271 u8 error_code;
272 int err;
273
274 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
275 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
276 if (err)
277 return err;
278
279 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
280 *fsm_state = control_state;
281 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
282 MLXFW_FSM_STATE_ERR_MAX);
283 return 0;
284}
285
286static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
287{
288 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
289 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
290 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
291 char mcc_pl[MLXSW_REG_MCC_LEN];
292
293 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
294 fwhandle, 0);
295 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
296}
297
298static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
299{
300 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
301 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
302 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
303 char mcc_pl[MLXSW_REG_MCC_LEN];
304
305 mlxsw_reg_mcc_pack(mcc_pl,
306 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
307 fwhandle, 0);
308 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
309}
310
311static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
312 .component_query = mlxsw_sp_component_query,
313 .fsm_lock = mlxsw_sp_fsm_lock,
314 .fsm_component_update = mlxsw_sp_fsm_component_update,
315 .fsm_block_download = mlxsw_sp_fsm_block_download,
316 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
317 .fsm_activate = mlxsw_sp_fsm_activate,
318 .fsm_query_state = mlxsw_sp_fsm_query_state,
319 .fsm_cancel = mlxsw_sp_fsm_cancel,
320 .fsm_release = mlxsw_sp_fsm_release
321};
322
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300323static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
324 const struct firmware *firmware)
325{
326 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
327 .mlxfw_dev = {
328 .ops = &mlxsw_sp_mlxfw_dev_ops,
329 .psid = mlxsw_sp->bus_info->psid,
330 .psid_size = strlen(mlxsw_sp->bus_info->psid),
331 },
332 .mlxsw_sp = mlxsw_sp
333 };
334
335 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
336}
337
Yotam Gigi6b742192017-05-23 21:56:29 +0200338static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
339{
340 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
Yotam Gigi6b742192017-05-23 21:56:29 +0200341 const struct firmware *firmware;
342 int err;
343
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100344 /* Validate driver & FW are compatible */
345 if (rev->major != MLXSW_FWREV_MAJOR) {
346 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
347 rev->major, MLXSW_FWREV_MAJOR);
348 return -EINVAL;
349 }
350 if (MLXSW_FWREV_MINOR_TO_BRANCH(rev->minor) ==
351 MLXSW_FWREV_MINOR_TO_BRANCH(MLXSW_FWREV_MINOR))
Yotam Gigi6b742192017-05-23 21:56:29 +0200352 return 0;
353
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100354 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200355 rev->major, rev->minor, rev->subminor);
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100356 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200357 MLXSW_SP_FW_FILENAME);
358
359 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
360 mlxsw_sp->bus_info->dev);
361 if (err) {
362 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
363 MLXSW_SP_FW_FILENAME);
364 return err;
365 }
366
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300367 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
Yotam Gigi6b742192017-05-23 21:56:29 +0200368 release_firmware(firmware);
369 return err;
370}
371
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100372int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
373 unsigned int counter_index, u64 *packets,
374 u64 *bytes)
375{
376 char mgpc_pl[MLXSW_REG_MGPC_LEN];
377 int err;
378
379 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200380 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100381 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
382 if (err)
383 return err;
Arkadi Sharshevsky7cfcbc72017-08-24 08:40:08 +0200384 if (packets)
385 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
386 if (bytes)
387 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100388 return 0;
389}
390
391static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
392 unsigned int counter_index)
393{
394 char mgpc_pl[MLXSW_REG_MGPC_LEN];
395
396 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200397 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100398 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
399}
400
401int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
402 unsigned int *p_counter_index)
403{
404 int err;
405
406 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
407 p_counter_index);
408 if (err)
409 return err;
410 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
411 if (err)
412 goto err_counter_clear;
413 return 0;
414
415err_counter_clear:
416 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
417 *p_counter_index);
418 return err;
419}
420
421void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
422 unsigned int counter_index)
423{
424 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
425 counter_index);
426}
427
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200428static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
429 const struct mlxsw_tx_info *tx_info)
430{
431 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
432
433 memset(txhdr, 0, MLXSW_TXHDR_LEN);
434
435 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
436 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
437 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
438 mlxsw_tx_hdr_swid_set(txhdr, 0);
439 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
440 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
441 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
442}
443
Petr Machata541e1152018-04-29 10:56:09 +0300444enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200445{
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200446 switch (state) {
447 case BR_STATE_FORWARDING:
Petr Machata541e1152018-04-29 10:56:09 +0300448 return MLXSW_REG_SPMS_STATE_FORWARDING;
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200449 case BR_STATE_LEARNING:
Petr Machata541e1152018-04-29 10:56:09 +0300450 return MLXSW_REG_SPMS_STATE_LEARNING;
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200451 case BR_STATE_LISTENING: /* fall-through */
452 case BR_STATE_DISABLED: /* fall-through */
453 case BR_STATE_BLOCKING:
Petr Machata541e1152018-04-29 10:56:09 +0300454 return MLXSW_REG_SPMS_STATE_DISCARDING;
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200455 default:
456 BUG();
457 }
Petr Machata541e1152018-04-29 10:56:09 +0300458}
459
460int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
461 u8 state)
462{
463 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
464 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
465 char *spms_pl;
466 int err;
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200467
468 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
469 if (!spms_pl)
470 return -ENOMEM;
471 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
472 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
473
474 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
475 kfree(spms_pl);
476 return err;
477}
478
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200479static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
480{
Elad Raz5b090742016-10-28 21:35:46 +0200481 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200482 int err;
483
484 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
485 if (err)
486 return err;
487 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
488 return 0;
489}
490
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100491static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
492 bool enable, u32 rate)
493{
494 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
495 char mpsc_pl[MLXSW_REG_MPSC_LEN];
496
497 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
498 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
499}
500
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200501static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
502 bool is_up)
503{
504 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
505 char paos_pl[MLXSW_REG_PAOS_LEN];
506
507 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
508 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
509 MLXSW_PORT_ADMIN_STATUS_DOWN);
510 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
511}
512
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200513static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
514 unsigned char *addr)
515{
516 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
517 char ppad_pl[MLXSW_REG_PPAD_LEN];
518
519 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
520 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
521 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
522}
523
524static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
525{
526 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
527 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
528
529 ether_addr_copy(addr, mlxsw_sp->base_mac);
530 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
531 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
532}
533
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200534static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
535{
536 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
537 char pmtu_pl[MLXSW_REG_PMTU_LEN];
538 int max_mtu;
539 int err;
540
541 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
542 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
543 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
544 if (err)
545 return err;
546 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
547
548 if (mtu > max_mtu)
549 return -EINVAL;
550
551 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
552 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
553}
554
555static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
556{
557 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel5b153852017-06-08 08:47:44 +0200558 char pspa_pl[MLXSW_REG_PSPA_LEN];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200559
Ido Schimmel5b153852017-06-08 08:47:44 +0200560 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
561 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200562}
563
Ido Schimmela1107482017-05-26 08:37:39 +0200564int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200565{
566 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
567 char svpe_pl[MLXSW_REG_SVPE_LEN];
568
569 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
570 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
571}
572
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200573int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
574 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200575{
576 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
577 char *spvmlr_pl;
578 int err;
579
580 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
581 if (!spvmlr_pl)
582 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200583 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
584 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200585 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
586 kfree(spvmlr_pl);
587 return err;
588}
589
Ido Schimmelb02eae92017-05-16 19:38:34 +0200590static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
591 u16 vid)
592{
593 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
594 char spvid_pl[MLXSW_REG_SPVID_LEN];
595
596 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
597 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
598}
599
600static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
601 bool allow)
602{
603 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
604 char spaft_pl[MLXSW_REG_SPAFT_LEN];
605
606 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
607 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
608}
609
610int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
611{
612 int err;
613
614 if (!vid) {
615 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
616 if (err)
617 return err;
618 } else {
619 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
620 if (err)
621 return err;
622 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
623 if (err)
624 goto err_port_allow_untagged_set;
625 }
626
627 mlxsw_sp_port->pvid = vid;
628 return 0;
629
630err_port_allow_untagged_set:
631 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
632 return err;
633}
634
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200635static int
636mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
637{
638 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
639 char sspr_pl[MLXSW_REG_SSPR_LEN];
640
641 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
642 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
643}
644
Ido Schimmeld664b412016-06-09 09:51:40 +0200645static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
646 u8 local_port, u8 *p_module,
647 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200648{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200649 char pmlp_pl[MLXSW_REG_PMLP_LEN];
650 int err;
651
Ido Schimmel558c2d52016-02-26 17:32:29 +0100652 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200653 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
654 if (err)
655 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100656 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
657 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200658 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200659 return 0;
660}
661
Ido Schimmel2e915e02017-06-08 08:47:45 +0200662static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100663 u8 module, u8 width, u8 lane)
664{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200665 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel18f1e702016-02-26 17:32:31 +0100666 char pmlp_pl[MLXSW_REG_PMLP_LEN];
667 int i;
668
Ido Schimmel2e915e02017-06-08 08:47:45 +0200669 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel18f1e702016-02-26 17:32:31 +0100670 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
671 for (i = 0; i < width; i++) {
672 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
673 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
674 }
675
676 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
677}
678
Ido Schimmel2e915e02017-06-08 08:47:45 +0200679static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100680{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200681 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100682 char pmlp_pl[MLXSW_REG_PMLP_LEN];
683
Ido Schimmel2e915e02017-06-08 08:47:45 +0200684 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100685 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
686 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
687}
688
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200689static int mlxsw_sp_port_open(struct net_device *dev)
690{
691 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
692 int err;
693
694 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
695 if (err)
696 return err;
697 netif_start_queue(dev);
698 return 0;
699}
700
701static int mlxsw_sp_port_stop(struct net_device *dev)
702{
703 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
704
705 netif_stop_queue(dev);
706 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
707}
708
709static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
710 struct net_device *dev)
711{
712 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
713 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
714 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
715 const struct mlxsw_tx_info tx_info = {
716 .local_port = mlxsw_sp_port->local_port,
717 .is_emad = false,
718 };
719 u64 len;
720 int err;
721
Jiri Pirko307c2432016-04-08 19:11:22 +0200722 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200723 return NETDEV_TX_BUSY;
724
725 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
726 struct sk_buff *skb_orig = skb;
727
728 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
729 if (!skb) {
730 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
731 dev_kfree_skb_any(skb_orig);
732 return NETDEV_TX_OK;
733 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +0100734 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200735 }
736
737 if (eth_skb_pad(skb)) {
738 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
739 return NETDEV_TX_OK;
740 }
741
742 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +0200743 /* TX header is consumed by HW on the way so we shouldn't count its
744 * bytes as being sent.
745 */
746 len = skb->len - MLXSW_TXHDR_LEN;
747
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200748 /* Due to a race we might fail here because of a full queue. In that
749 * unlikely case we simply drop the packet.
750 */
Jiri Pirko307c2432016-04-08 19:11:22 +0200751 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200752
753 if (!err) {
754 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
755 u64_stats_update_begin(&pcpu_stats->syncp);
756 pcpu_stats->tx_packets++;
757 pcpu_stats->tx_bytes += len;
758 u64_stats_update_end(&pcpu_stats->syncp);
759 } else {
760 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
761 dev_kfree_skb_any(skb);
762 }
763 return NETDEV_TX_OK;
764}
765
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100766static void mlxsw_sp_set_rx_mode(struct net_device *dev)
767{
768}
769
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200770static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
771{
772 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
773 struct sockaddr *addr = p;
774 int err;
775
776 if (!is_valid_ether_addr(addr->sa_data))
777 return -EADDRNOTAVAIL;
778
779 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
780 if (err)
781 return err;
782 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
783 return 0;
784}
785
Ido Schimmel18281f22017-03-24 08:02:51 +0100786static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
787 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200788{
Ido Schimmel18281f22017-03-24 08:02:51 +0100789 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100790}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200791
Ido Schimmelf417f042017-03-24 08:02:50 +0100792#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +0100793
794static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
795 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +0100796{
Ido Schimmel18281f22017-03-24 08:02:51 +0100797 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
798 BITS_PER_BYTE));
799 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
800 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100801}
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200802
Ido Schimmel18281f22017-03-24 08:02:51 +0100803/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +0100804 * Assumes 100m cable and maximum MTU.
805 */
Ido Schimmel18281f22017-03-24 08:02:51 +0100806#define MLXSW_SP_PAUSE_DELAY 58752
807
808static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
809 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +0100810{
811 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +0100812 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +0100813 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +0100814 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200815 else
Ido Schimmelf417f042017-03-24 08:02:50 +0100816 return 0;
817}
818
819static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
820 bool lossy)
821{
822 if (lossy)
823 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
824 else
825 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
826 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200827}
828
829int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200830 u8 *prio_tc, bool pause_en,
831 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +0200832{
833 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200834 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
835 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200836 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200837 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200838
839 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
840 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
841 if (err)
842 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200843
844 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
845 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200846 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +0100847 bool lossy;
848 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200849
850 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
851 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200852 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200853 configure = true;
854 break;
855 }
856 }
857
858 if (!configure)
859 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +0100860
861 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +0100862 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
863 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
864 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +0100865 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200866 }
867
Ido Schimmelff6551e2016-04-06 17:10:03 +0200868 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
869}
870
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200871static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200872 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200873{
874 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
875 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200876 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200877 u8 *prio_tc;
878
879 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200880 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200881
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200882 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200883 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200884}
885
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200886static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
887{
888 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200889 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200890 int err;
891
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200892 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200893 if (err)
894 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200895 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
896 if (err)
897 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200898 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
899 if (err)
900 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200901 dev->mtu = mtu;
902 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200903
904err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +0200905 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
906err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200907 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +0200908 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200909}
910
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +0300911static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200912mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
913 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200914{
915 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
916 struct mlxsw_sp_port_pcpu_stats *p;
917 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
918 u32 tx_dropped = 0;
919 unsigned int start;
920 int i;
921
922 for_each_possible_cpu(i) {
923 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
924 do {
925 start = u64_stats_fetch_begin_irq(&p->syncp);
926 rx_packets = p->rx_packets;
927 rx_bytes = p->rx_bytes;
928 tx_packets = p->tx_packets;
929 tx_bytes = p->tx_bytes;
930 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
931
932 stats->rx_packets += rx_packets;
933 stats->rx_bytes += rx_bytes;
934 stats->tx_packets += tx_packets;
935 stats->tx_bytes += tx_bytes;
936 /* tx_dropped is u32, updated without syncp protection. */
937 tx_dropped += p->tx_dropped;
938 }
939 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200940 return 0;
941}
942
Or Gerlitz3df5b3c2016-11-22 23:09:54 +0200943static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200944{
945 switch (attr_id) {
946 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
947 return true;
948 }
949
950 return false;
951}
952
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +0300953static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
954 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200955{
956 switch (attr_id) {
957 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
958 return mlxsw_sp_port_get_sw_stats64(dev, sp);
959 }
960
961 return -EINVAL;
962}
963
964static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
965 int prio, char *ppcnt_pl)
966{
967 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
968 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
969
970 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
971 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
972}
973
974static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
975 struct rtnl_link_stats64 *stats)
976{
977 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
978 int err;
979
980 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
981 0, ppcnt_pl);
982 if (err)
983 goto out;
984
985 stats->tx_packets =
986 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
987 stats->rx_packets =
988 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
989 stats->tx_bytes =
990 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
991 stats->rx_bytes =
992 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
993 stats->multicast =
994 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
995
996 stats->rx_crc_errors =
997 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
998 stats->rx_frame_errors =
999 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1000
1001 stats->rx_length_errors = (
1002 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1003 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1004 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1005
1006 stats->rx_errors = (stats->rx_crc_errors +
1007 stats->rx_frame_errors + stats->rx_length_errors);
1008
1009out:
1010 return err;
1011}
1012
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001013static void
1014mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1015 struct mlxsw_sp_port_xstats *xstats)
1016{
1017 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1018 int err, i;
1019
1020 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1021 ppcnt_pl);
1022 if (!err)
1023 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1024
1025 for (i = 0; i < TC_MAX_QUEUE; i++) {
1026 err = mlxsw_sp_port_get_stats_raw(dev,
1027 MLXSW_REG_PPCNT_TC_CONG_TC,
1028 i, ppcnt_pl);
1029 if (!err)
1030 xstats->wred_drop[i] =
1031 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1032
1033 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1034 i, ppcnt_pl);
1035 if (err)
1036 continue;
1037
1038 xstats->backlog[i] =
1039 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1040 xstats->tail_drop[i] =
1041 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1042 }
Nogah Frankel2f880472018-02-28 10:44:59 +01001043
1044 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1045 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
1046 i, ppcnt_pl);
1047 if (err)
1048 continue;
1049
1050 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
1051 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
1052 }
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001053}
1054
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001055static void update_stats_cache(struct work_struct *work)
1056{
1057 struct mlxsw_sp_port *mlxsw_sp_port =
1058 container_of(work, struct mlxsw_sp_port,
Nogah Frankel9deef432017-10-26 10:55:32 +02001059 periodic_hw_stats.update_dw.work);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001060
1061 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1062 goto out;
1063
1064 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
Nogah Frankel9deef432017-10-26 10:55:32 +02001065 &mlxsw_sp_port->periodic_hw_stats.stats);
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001066 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1067 &mlxsw_sp_port->periodic_hw_stats.xstats);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001068
1069out:
Nogah Frankel9deef432017-10-26 10:55:32 +02001070 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001071 MLXSW_HW_STATS_UPDATE_TIME);
1072}
1073
1074/* Return the stats from a cache that is updated periodically,
1075 * as this function might get called in an atomic context.
1076 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001077static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001078mlxsw_sp_port_get_stats64(struct net_device *dev,
1079 struct rtnl_link_stats64 *stats)
1080{
1081 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1082
Nogah Frankel9deef432017-10-26 10:55:32 +02001083 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001084}
1085
Jiri Pirko93cd0812017-04-18 16:55:35 +02001086static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1087 u16 vid_begin, u16 vid_end,
1088 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001089{
1090 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1091 char *spvm_pl;
1092 int err;
1093
1094 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1095 if (!spvm_pl)
1096 return -ENOMEM;
1097
1098 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1099 vid_end, is_member, untagged);
1100 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1101 kfree(spvm_pl);
1102 return err;
1103}
1104
Jiri Pirko93cd0812017-04-18 16:55:35 +02001105int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1106 u16 vid_end, bool is_member, bool untagged)
1107{
1108 u16 vid, vid_e;
1109 int err;
1110
1111 for (vid = vid_begin; vid <= vid_end;
1112 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1113 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1114 vid_end);
1115
1116 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1117 is_member, untagged);
1118 if (err)
1119 return err;
1120 }
1121
1122 return 0;
1123}
1124
Ido Schimmelc57529e2017-05-26 08:37:31 +02001125static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001126{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001127 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001128
Ido Schimmelc57529e2017-05-26 08:37:31 +02001129 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1130 &mlxsw_sp_port->vlans_list, list)
1131 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001132}
1133
Ido Schimmel31a08a52017-05-26 08:37:26 +02001134static struct mlxsw_sp_port_vlan *
1135mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1136{
1137 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001138 bool untagged = vid == 1;
1139 int err;
1140
1141 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1142 if (err)
1143 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001144
1145 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001146 if (!mlxsw_sp_port_vlan) {
1147 err = -ENOMEM;
1148 goto err_port_vlan_alloc;
1149 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02001150
1151 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
Ido Schimmelb3529af2018-02-28 13:12:11 +01001152 mlxsw_sp_port_vlan->ref_count = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02001153 mlxsw_sp_port_vlan->vid = vid;
1154 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1155
1156 return mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001157
1158err_port_vlan_alloc:
1159 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1160 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001161}
1162
1163static void
1164mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1165{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001166 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1167 u16 vid = mlxsw_sp_port_vlan->vid;
Ido Schimmel7cbecf22017-05-26 08:37:28 +02001168
Ido Schimmel31a08a52017-05-26 08:37:26 +02001169 list_del(&mlxsw_sp_port_vlan->list);
1170 kfree(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001171 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1172}
1173
1174struct mlxsw_sp_port_vlan *
1175mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1176{
1177 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1178
1179 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelb3529af2018-02-28 13:12:11 +01001180 if (mlxsw_sp_port_vlan) {
1181 mlxsw_sp_port_vlan->ref_count++;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001182 return mlxsw_sp_port_vlan;
Ido Schimmelb3529af2018-02-28 13:12:11 +01001183 }
Ido Schimmelc57529e2017-05-26 08:37:31 +02001184
1185 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1186}
1187
1188void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1189{
Ido Schimmela1107482017-05-26 08:37:39 +02001190 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1191
Ido Schimmelb3529af2018-02-28 13:12:11 +01001192 if (--mlxsw_sp_port_vlan->ref_count != 0)
1193 return;
1194
Ido Schimmelc57529e2017-05-26 08:37:31 +02001195 if (mlxsw_sp_port_vlan->bridge_port)
1196 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
Ido Schimmela1107482017-05-26 08:37:39 +02001197 else if (fid)
1198 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001199
1200 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001201}
1202
Ido Schimmel05978482016-08-17 16:39:30 +02001203static int mlxsw_sp_port_add_vid(struct net_device *dev,
1204 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001205{
1206 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001207
1208 /* VLAN 0 is added to HW filter when device goes up, but it is
1209 * reserved in our case, so simply return.
1210 */
1211 if (!vid)
1212 return 0;
1213
Ido Schimmelc57529e2017-05-26 08:37:31 +02001214 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001215}
1216
Ido Schimmel32d863f2016-07-02 11:00:10 +02001217static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1218 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001219{
1220 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001221 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001222
1223 /* VLAN 0 is removed from HW filter when device goes down, but
1224 * it is reserved in our case, so simply return.
1225 */
1226 if (!vid)
1227 return 0;
1228
Ido Schimmel31a08a52017-05-26 08:37:26 +02001229 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001230 if (!mlxsw_sp_port_vlan)
Ido Schimmel31a08a52017-05-26 08:37:26 +02001231 return 0;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001232 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001233
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001234 return 0;
1235}
1236
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001237static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1238 size_t len)
1239{
1240 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001241
Jiri Pirkoec932fb2018-05-18 09:29:04 +02001242 return mlxsw_core_port_get_phys_port_name(mlxsw_sp_port->mlxsw_sp->core,
1243 mlxsw_sp_port->local_port,
1244 name, len);
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001245}
1246
Yotam Gigi763b4b72016-07-21 12:03:17 +02001247static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001248mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1249 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001250 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1251
1252 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1253 if (mall_tc_entry->cookie == cookie)
1254 return mall_tc_entry;
1255
1256 return NULL;
1257}
1258
1259static int
1260mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001261 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001262 const struct tc_action *a,
1263 bool ingress)
1264{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001265 enum mlxsw_sp_span_type span_type;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001266 struct net_device *to_dev;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001267
Cong Wang9f8a7392017-12-05 16:17:26 -08001268 to_dev = tcf_mirred_dev(a);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001269 if (!to_dev) {
1270 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1271 return -EINVAL;
1272 }
1273
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001274 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001275 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Petr Machata079c9f32018-02-27 14:53:44 +01001276 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type,
Petr Machata98977082018-02-27 14:53:41 +01001277 true, &mirror->span_id);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001278}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001279
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001280static void
1281mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1282 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1283{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001284 enum mlxsw_sp_span_type span_type;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001285
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001286 span_type = mirror->ingress ?
1287 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Petr Machata98977082018-02-27 14:53:41 +01001288 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +01001289 span_type, true);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001290}
1291
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001292static int
1293mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1294 struct tc_cls_matchall_offload *cls,
1295 const struct tc_action *a,
1296 bool ingress)
1297{
1298 int err;
1299
1300 if (!mlxsw_sp_port->sample)
1301 return -EOPNOTSUPP;
1302 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1303 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1304 return -EEXIST;
1305 }
1306 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1307 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1308 return -EOPNOTSUPP;
1309 }
1310
1311 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1312 tcf_sample_psample_group(a));
1313 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1314 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1315 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1316
1317 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1318 if (err)
1319 goto err_port_sample_set;
1320 return 0;
1321
1322err_port_sample_set:
1323 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1324 return err;
1325}
1326
1327static void
1328mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1329{
1330 if (!mlxsw_sp_port->sample)
1331 return;
1332
1333 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1334 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1335}
1336
Yotam Gigi763b4b72016-07-21 12:03:17 +02001337static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001338 struct tc_cls_matchall_offload *f,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001339 bool ingress)
1340{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001341 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001342 __be16 protocol = f->common.protocol;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001343 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001344 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001345 int err;
1346
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001347 if (!tcf_exts_has_one_action(f->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001348 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001349 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001350 }
1351
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001352 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1353 if (!mall_tc_entry)
1354 return -ENOMEM;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001355 mall_tc_entry->cookie = f->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001356
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001357 tcf_exts_to_list(f->exts, &actions);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001358 a = list_first_entry(&actions, struct tc_action, list);
1359
1360 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1361 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1362
1363 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1364 mirror = &mall_tc_entry->mirror;
1365 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1366 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001367 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1368 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001369 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001370 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001371 } else {
1372 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001373 }
1374
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001375 if (err)
1376 goto err_add_action;
1377
1378 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001379 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001380
1381err_add_action:
1382 kfree(mall_tc_entry);
1383 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001384}
1385
1386static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001387 struct tc_cls_matchall_offload *f)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001388{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001389 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001390
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001391 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001392 f->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001393 if (!mall_tc_entry) {
1394 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1395 return;
1396 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001397 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001398
1399 switch (mall_tc_entry->type) {
1400 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001401 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1402 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001403 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001404 case MLXSW_SP_PORT_MALL_SAMPLE:
1405 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1406 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001407 default:
1408 WARN_ON(1);
1409 }
1410
Yotam Gigi763b4b72016-07-21 12:03:17 +02001411 kfree(mall_tc_entry);
1412}
1413
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001414static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001415 struct tc_cls_matchall_offload *f,
1416 bool ingress)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001417{
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001418 switch (f->command) {
1419 case TC_CLSMATCHALL_REPLACE:
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001420 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001421 ingress);
1422 case TC_CLSMATCHALL_DESTROY:
1423 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1424 return 0;
1425 default:
1426 return -EOPNOTSUPP;
1427 }
1428}
1429
1430static int
Jiri Pirko3aaff322018-01-17 11:46:56 +01001431mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1432 struct tc_cls_flower_offload *f)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001433{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001434 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1435
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001436 switch (f->command) {
1437 case TC_CLSFLOWER_REPLACE:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001438 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001439 case TC_CLSFLOWER_DESTROY:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001440 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001441 return 0;
1442 case TC_CLSFLOWER_STATS:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001443 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001444 default:
1445 return -EOPNOTSUPP;
1446 }
1447}
1448
Jiri Pirko3aaff322018-01-17 11:46:56 +01001449static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1450 void *type_data,
1451 void *cb_priv, bool ingress)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001452{
1453 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1454
1455 switch (type) {
1456 case TC_SETUP_CLSMATCHALL:
Jakub Kicinski15f4edb2018-01-25 14:00:51 -08001457 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1458 type_data))
Jiri Pirko3aaff322018-01-17 11:46:56 +01001459 return -EOPNOTSUPP;
1460
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001461 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1462 ingress);
1463 case TC_SETUP_CLSFLOWER:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001464 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001465 default:
1466 return -EOPNOTSUPP;
1467 }
1468}
1469
Jiri Pirko3aaff322018-01-17 11:46:56 +01001470static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1471 void *type_data,
1472 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001473{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001474 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1475 cb_priv, true);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001476}
1477
Jiri Pirko3aaff322018-01-17 11:46:56 +01001478static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1479 void *type_data,
1480 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001481{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001482 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1483 cb_priv, false);
1484}
1485
1486static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1487 void *type_data, void *cb_priv)
1488{
1489 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1490
1491 switch (type) {
1492 case TC_SETUP_CLSMATCHALL:
1493 return 0;
1494 case TC_SETUP_CLSFLOWER:
1495 if (mlxsw_sp_acl_block_disabled(acl_block))
1496 return -EOPNOTSUPP;
1497
1498 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1499 default:
1500 return -EOPNOTSUPP;
1501 }
1502}
1503
1504static int
1505mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
John Hurley60513bd2018-06-25 14:30:04 -07001506 struct tcf_block *block, bool ingress,
1507 struct netlink_ext_ack *extack)
Jiri Pirko3aaff322018-01-17 11:46:56 +01001508{
1509 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1510 struct mlxsw_sp_acl_block *acl_block;
1511 struct tcf_block_cb *block_cb;
1512 int err;
1513
1514 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1515 mlxsw_sp);
1516 if (!block_cb) {
1517 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1518 if (!acl_block)
1519 return -ENOMEM;
1520 block_cb = __tcf_block_cb_register(block,
1521 mlxsw_sp_setup_tc_block_cb_flower,
John Hurley60513bd2018-06-25 14:30:04 -07001522 mlxsw_sp, acl_block, extack);
Jiri Pirko3aaff322018-01-17 11:46:56 +01001523 if (IS_ERR(block_cb)) {
1524 err = PTR_ERR(block_cb);
1525 goto err_cb_register;
1526 }
1527 } else {
1528 acl_block = tcf_block_cb_priv(block_cb);
1529 }
1530 tcf_block_cb_incref(block_cb);
1531 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1532 mlxsw_sp_port, ingress);
1533 if (err)
1534 goto err_block_bind;
1535
1536 if (ingress)
1537 mlxsw_sp_port->ing_acl_block = acl_block;
1538 else
1539 mlxsw_sp_port->eg_acl_block = acl_block;
1540
1541 return 0;
1542
1543err_block_bind:
1544 if (!tcf_block_cb_decref(block_cb)) {
John Hurley32636742018-06-25 14:30:10 -07001545 __tcf_block_cb_unregister(block, block_cb);
Jiri Pirko3aaff322018-01-17 11:46:56 +01001546err_cb_register:
1547 mlxsw_sp_acl_block_destroy(acl_block);
1548 }
1549 return err;
1550}
1551
1552static void
1553mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1554 struct tcf_block *block, bool ingress)
1555{
1556 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1557 struct mlxsw_sp_acl_block *acl_block;
1558 struct tcf_block_cb *block_cb;
1559 int err;
1560
1561 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1562 mlxsw_sp);
1563 if (!block_cb)
1564 return;
1565
1566 if (ingress)
1567 mlxsw_sp_port->ing_acl_block = NULL;
1568 else
1569 mlxsw_sp_port->eg_acl_block = NULL;
1570
1571 acl_block = tcf_block_cb_priv(block_cb);
1572 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1573 mlxsw_sp_port, ingress);
1574 if (!err && !tcf_block_cb_decref(block_cb)) {
John Hurley32636742018-06-25 14:30:10 -07001575 __tcf_block_cb_unregister(block, block_cb);
Jiri Pirko3aaff322018-01-17 11:46:56 +01001576 mlxsw_sp_acl_block_destroy(acl_block);
1577 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001578}
1579
1580static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1581 struct tc_block_offload *f)
1582{
1583 tc_setup_cb_t *cb;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001584 bool ingress;
1585 int err;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001586
Jiri Pirko3aaff322018-01-17 11:46:56 +01001587 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1588 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1589 ingress = true;
1590 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1591 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1592 ingress = false;
1593 } else {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001594 return -EOPNOTSUPP;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001595 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001596
1597 switch (f->command) {
1598 case TC_BLOCK_BIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001599 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
John Hurley60513bd2018-06-25 14:30:04 -07001600 mlxsw_sp_port, f->extack);
Jiri Pirko3aaff322018-01-17 11:46:56 +01001601 if (err)
1602 return err;
1603 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
John Hurley60513bd2018-06-25 14:30:04 -07001604 f->block, ingress,
1605 f->extack);
Jiri Pirko3aaff322018-01-17 11:46:56 +01001606 if (err) {
1607 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1608 return err;
1609 }
1610 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001611 case TC_BLOCK_UNBIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001612 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1613 f->block, ingress);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001614 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1615 return 0;
1616 default:
1617 return -EOPNOTSUPP;
1618 }
1619}
1620
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001621static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
Jiri Pirkode4784c2017-08-07 10:15:32 +02001622 void *type_data)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001623{
1624 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1625
Jiri Pirko2572ac52017-08-07 10:15:17 +02001626 switch (type) {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001627 case TC_SETUP_BLOCK:
1628 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
Nogah Frankel96f17e02017-11-06 07:23:45 +01001629 case TC_SETUP_QDISC_RED:
1630 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
Nogah Frankel46a36152018-01-14 12:33:16 +01001631 case TC_SETUP_QDISC_PRIO:
1632 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
Jiri Pirko2572ac52017-08-07 10:15:17 +02001633 default:
1634 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001635 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001636}
1637
Jiri Pirko9454d932017-12-06 09:41:12 +01001638
1639static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1640{
1641 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1642
Jiri Pirko3aaff322018-01-17 11:46:56 +01001643 if (!enable) {
1644 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1645 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1646 !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1647 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1648 return -EINVAL;
1649 }
1650 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1651 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1652 } else {
1653 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1654 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
Jiri Pirko9454d932017-12-06 09:41:12 +01001655 }
1656 return 0;
1657}
1658
1659typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1660
1661static int mlxsw_sp_handle_feature(struct net_device *dev,
1662 netdev_features_t wanted_features,
1663 netdev_features_t feature,
1664 mlxsw_sp_feature_handler feature_handler)
1665{
1666 netdev_features_t changes = wanted_features ^ dev->features;
1667 bool enable = !!(wanted_features & feature);
1668 int err;
1669
1670 if (!(changes & feature))
1671 return 0;
1672
1673 err = feature_handler(dev, enable);
1674 if (err) {
1675 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1676 enable ? "Enable" : "Disable", &feature, err);
1677 return err;
1678 }
1679
1680 if (enable)
1681 dev->features |= feature;
1682 else
1683 dev->features &= ~feature;
1684
1685 return 0;
1686}
1687static int mlxsw_sp_set_features(struct net_device *dev,
1688 netdev_features_t features)
1689{
1690 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1691 mlxsw_sp_feature_hw_tc);
1692}
1693
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001694static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1695 .ndo_open = mlxsw_sp_port_open,
1696 .ndo_stop = mlxsw_sp_port_stop,
1697 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001698 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001699 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001700 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1701 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1702 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001703 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1704 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001705 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1706 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001707 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko9454d932017-12-06 09:41:12 +01001708 .ndo_set_features = mlxsw_sp_set_features,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001709};
1710
1711static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1712 struct ethtool_drvinfo *drvinfo)
1713{
1714 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1715 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1716
1717 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1718 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1719 sizeof(drvinfo->version));
1720 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1721 "%d.%d.%d",
1722 mlxsw_sp->bus_info->fw_rev.major,
1723 mlxsw_sp->bus_info->fw_rev.minor,
1724 mlxsw_sp->bus_info->fw_rev.subminor);
1725 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1726 sizeof(drvinfo->bus_info));
1727}
1728
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001729static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1730 struct ethtool_pauseparam *pause)
1731{
1732 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1733
1734 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1735 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1736}
1737
1738static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1739 struct ethtool_pauseparam *pause)
1740{
1741 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1742
1743 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1744 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1745 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1746
1747 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1748 pfcc_pl);
1749}
1750
1751static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1752 struct ethtool_pauseparam *pause)
1753{
1754 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1755 bool pause_en = pause->tx_pause || pause->rx_pause;
1756 int err;
1757
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001758 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1759 netdev_err(dev, "PFC already enabled on port\n");
1760 return -EINVAL;
1761 }
1762
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001763 if (pause->autoneg) {
1764 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1765 return -EINVAL;
1766 }
1767
1768 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1769 if (err) {
1770 netdev_err(dev, "Failed to configure port's headroom\n");
1771 return err;
1772 }
1773
1774 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1775 if (err) {
1776 netdev_err(dev, "Failed to set PAUSE parameters\n");
1777 goto err_port_pause_configure;
1778 }
1779
1780 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1781 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1782
1783 return 0;
1784
1785err_port_pause_configure:
1786 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1787 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1788 return err;
1789}
1790
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001791struct mlxsw_sp_port_hw_stats {
1792 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02001793 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01001794 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001795};
1796
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001797static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001798 {
1799 .str = "a_frames_transmitted_ok",
1800 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1801 },
1802 {
1803 .str = "a_frames_received_ok",
1804 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1805 },
1806 {
1807 .str = "a_frame_check_sequence_errors",
1808 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1809 },
1810 {
1811 .str = "a_alignment_errors",
1812 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1813 },
1814 {
1815 .str = "a_octets_transmitted_ok",
1816 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1817 },
1818 {
1819 .str = "a_octets_received_ok",
1820 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1821 },
1822 {
1823 .str = "a_multicast_frames_xmitted_ok",
1824 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1825 },
1826 {
1827 .str = "a_broadcast_frames_xmitted_ok",
1828 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1829 },
1830 {
1831 .str = "a_multicast_frames_received_ok",
1832 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1833 },
1834 {
1835 .str = "a_broadcast_frames_received_ok",
1836 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1837 },
1838 {
1839 .str = "a_in_range_length_errors",
1840 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1841 },
1842 {
1843 .str = "a_out_of_range_length_field",
1844 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1845 },
1846 {
1847 .str = "a_frame_too_long_errors",
1848 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1849 },
1850 {
1851 .str = "a_symbol_error_during_carrier",
1852 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1853 },
1854 {
1855 .str = "a_mac_control_frames_transmitted",
1856 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1857 },
1858 {
1859 .str = "a_mac_control_frames_received",
1860 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1861 },
1862 {
1863 .str = "a_unsupported_opcodes_received",
1864 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1865 },
1866 {
1867 .str = "a_pause_mac_ctrl_frames_received",
1868 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1869 },
1870 {
1871 .str = "a_pause_mac_ctrl_frames_xmitted",
1872 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1873 },
1874};
1875
1876#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1877
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001878static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1879 {
1880 .str = "rx_octets_prio",
1881 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1882 },
1883 {
1884 .str = "rx_frames_prio",
1885 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1886 },
1887 {
1888 .str = "tx_octets_prio",
1889 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1890 },
1891 {
1892 .str = "tx_frames_prio",
1893 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1894 },
1895 {
1896 .str = "rx_pause_prio",
1897 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1898 },
1899 {
1900 .str = "rx_pause_duration_prio",
1901 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1902 },
1903 {
1904 .str = "tx_pause_prio",
1905 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1906 },
1907 {
1908 .str = "tx_pause_duration_prio",
1909 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1910 },
1911};
1912
1913#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1914
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001915static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1916 {
1917 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01001918 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1919 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001920 },
1921 {
1922 .str = "tc_no_buffer_discard_uc_tc",
1923 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1924 },
1925};
1926
1927#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1928
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001929#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001930 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1931 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001932 IEEE_8021QAZ_MAX_TCS)
1933
1934static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1935{
1936 int i;
1937
1938 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1939 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1940 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1941 *p += ETH_GSTRING_LEN;
1942 }
1943}
1944
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001945static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1946{
1947 int i;
1948
1949 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1950 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1951 mlxsw_sp_port_hw_tc_stats[i].str, tc);
1952 *p += ETH_GSTRING_LEN;
1953 }
1954}
1955
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001956static void mlxsw_sp_port_get_strings(struct net_device *dev,
1957 u32 stringset, u8 *data)
1958{
1959 u8 *p = data;
1960 int i;
1961
1962 switch (stringset) {
1963 case ETH_SS_STATS:
1964 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1965 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1966 ETH_GSTRING_LEN);
1967 p += ETH_GSTRING_LEN;
1968 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001969
1970 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1971 mlxsw_sp_port_get_prio_strings(&p, i);
1972
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001973 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1974 mlxsw_sp_port_get_tc_strings(&p, i);
1975
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001976 break;
1977 }
1978}
1979
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001980static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1981 enum ethtool_phys_id_state state)
1982{
1983 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1984 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1985 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1986 bool active;
1987
1988 switch (state) {
1989 case ETHTOOL_ID_ACTIVE:
1990 active = true;
1991 break;
1992 case ETHTOOL_ID_INACTIVE:
1993 active = false;
1994 break;
1995 default:
1996 return -EOPNOTSUPP;
1997 }
1998
1999 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2000 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2001}
2002
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002003static int
2004mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2005 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2006{
2007 switch (grp) {
2008 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2009 *p_hw_stats = mlxsw_sp_port_hw_stats;
2010 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2011 break;
2012 case MLXSW_REG_PPCNT_PRIO_CNT:
2013 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2014 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2015 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002016 case MLXSW_REG_PPCNT_TC_CNT:
2017 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2018 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2019 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002020 default:
2021 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002022 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002023 }
2024 return 0;
2025}
2026
2027static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2028 enum mlxsw_reg_ppcnt_grp grp, int prio,
2029 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002030{
Ido Schimmel18281f22017-03-24 08:02:51 +01002031 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2032 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002033 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002034 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002035 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002036 int err;
2037
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002038 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2039 if (err)
2040 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002041 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002042 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002043 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002044 if (!hw_stats[i].cells_bytes)
2045 continue;
2046 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2047 data[data_index + i]);
2048 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002049}
2050
2051static void mlxsw_sp_port_get_stats(struct net_device *dev,
2052 struct ethtool_stats *stats, u64 *data)
2053{
2054 int i, data_index = 0;
2055
2056 /* IEEE 802.3 Counters */
2057 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2058 data, data_index);
2059 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2060
2061 /* Per-Priority Counters */
2062 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2063 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2064 data, data_index);
2065 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2066 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002067
2068 /* Per-TC Counters */
2069 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2070 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2071 data, data_index);
2072 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2073 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002074}
2075
2076static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2077{
2078 switch (sset) {
2079 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002080 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002081 default:
2082 return -EOPNOTSUPP;
2083 }
2084}
2085
2086struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002087 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002088 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002089 u32 speed;
2090};
2091
2092static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2093 {
2094 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002095 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2096 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002097 },
2098 {
2099 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2100 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002101 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2102 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002103 },
2104 {
2105 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002106 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2107 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002108 },
2109 {
2110 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2111 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002112 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2113 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002114 },
2115 {
2116 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2117 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2118 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2119 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002120 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2121 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002122 },
2123 {
2124 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002125 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2126 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002127 },
2128 {
2129 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002130 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2131 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002132 },
2133 {
2134 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002135 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2136 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002137 },
2138 {
2139 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002140 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2141 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002142 },
2143 {
2144 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002145 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2146 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002147 },
2148 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002149 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2150 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2151 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002152 },
2153 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002154 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2155 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2156 .speed = SPEED_25000,
2157 },
2158 {
2159 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2160 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2161 .speed = SPEED_25000,
2162 },
2163 {
2164 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2165 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2166 .speed = SPEED_25000,
2167 },
2168 {
2169 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2170 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2171 .speed = SPEED_50000,
2172 },
2173 {
2174 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2175 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2176 .speed = SPEED_50000,
2177 },
2178 {
2179 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2180 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2181 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002182 },
2183 {
2184 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002185 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2186 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002187 },
2188 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002189 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2190 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2191 .speed = SPEED_56000,
2192 },
2193 {
2194 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2195 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2196 .speed = SPEED_56000,
2197 },
2198 {
2199 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2200 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2201 .speed = SPEED_56000,
2202 },
2203 {
2204 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2205 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2206 .speed = SPEED_100000,
2207 },
2208 {
2209 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2210 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2211 .speed = SPEED_100000,
2212 },
2213 {
2214 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2215 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2216 .speed = SPEED_100000,
2217 },
2218 {
2219 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2220 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2221 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002222 },
2223};
2224
2225#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2226
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002227static void
2228mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2229 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002230{
2231 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2232 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2233 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2234 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2235 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2236 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002237 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002238
2239 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2240 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2241 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2242 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2243 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002244 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002245}
2246
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002247static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002248{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002249 int i;
2250
2251 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2252 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002253 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2254 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002255 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002256}
2257
2258static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002259 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002260{
2261 u32 speed = SPEED_UNKNOWN;
2262 u8 duplex = DUPLEX_UNKNOWN;
2263 int i;
2264
2265 if (!carrier_ok)
2266 goto out;
2267
2268 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2269 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2270 speed = mlxsw_sp_port_link_mode[i].speed;
2271 duplex = DUPLEX_FULL;
2272 break;
2273 }
2274 }
2275out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002276 cmd->base.speed = speed;
2277 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002278}
2279
2280static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2281{
2282 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2283 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2284 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2285 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2286 return PORT_FIBRE;
2287
2288 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2289 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2290 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2291 return PORT_DA;
2292
2293 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2294 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2295 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2296 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2297 return PORT_NONE;
2298
2299 return PORT_OTHER;
2300}
2301
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002302static u32
2303mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002304{
2305 u32 ptys_proto = 0;
2306 int i;
2307
2308 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002309 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2310 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002311 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2312 }
2313 return ptys_proto;
2314}
2315
2316static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2317{
2318 u32 ptys_proto = 0;
2319 int i;
2320
2321 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2322 if (speed == mlxsw_sp_port_link_mode[i].speed)
2323 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2324 }
2325 return ptys_proto;
2326}
2327
Ido Schimmel18f1e702016-02-26 17:32:31 +01002328static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2329{
2330 u32 ptys_proto = 0;
2331 int i;
2332
2333 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2334 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2335 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2336 }
2337 return ptys_proto;
2338}
2339
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002340static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2341 struct ethtool_link_ksettings *cmd)
2342{
2343 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2344 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2345 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2346
2347 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2348 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2349}
2350
2351static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2352 struct ethtool_link_ksettings *cmd)
2353{
2354 if (!autoneg)
2355 return;
2356
2357 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2358 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2359}
2360
2361static void
2362mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2363 struct ethtool_link_ksettings *cmd)
2364{
2365 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2366 return;
2367
2368 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2369 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2370}
2371
2372static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2373 struct ethtool_link_ksettings *cmd)
2374{
2375 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2376 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2377 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2378 char ptys_pl[MLXSW_REG_PTYS_LEN];
2379 u8 autoneg_status;
2380 bool autoneg;
2381 int err;
2382
2383 autoneg = mlxsw_sp_port->link.autoneg;
Tal Bar8e1ed732018-03-21 09:34:06 +02002384 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002385 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2386 if (err)
2387 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002388 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2389 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002390
2391 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2392
2393 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2394
2395 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2396 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2397 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2398
2399 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2400 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2401 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2402 cmd);
2403
2404 return 0;
2405}
2406
2407static int
2408mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2409 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002410{
2411 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2412 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2413 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002414 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002415 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002416 int err;
2417
Tal Bar8e1ed732018-03-21 09:34:06 +02002418 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002419 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002420 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002421 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002422 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002423
2424 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2425 eth_proto_new = autoneg ?
2426 mlxsw_sp_to_ptys_advert_link(cmd) :
2427 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002428
2429 eth_proto_new = eth_proto_new & eth_proto_cap;
2430 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002431 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002432 return -EINVAL;
2433 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002434
Elad Raz401c8b42016-10-28 21:35:52 +02002435 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
Tal Bar8e1ed732018-03-21 09:34:06 +02002436 eth_proto_new, autoneg);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002437 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002438 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002439 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002440
Ido Schimmel6277d462016-07-15 11:14:58 +02002441 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002442 return 0;
2443
Ido Schimmel0c83f882016-09-12 13:26:23 +02002444 mlxsw_sp_port->link.autoneg = autoneg;
2445
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002446 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2447 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002448
2449 return 0;
2450}
2451
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002452static int mlxsw_sp_flash_device(struct net_device *dev,
2453 struct ethtool_flash *flash)
2454{
2455 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2456 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2457 const struct firmware *firmware;
2458 int err;
2459
2460 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2461 return -EOPNOTSUPP;
2462
2463 dev_hold(dev);
2464 rtnl_unlock();
2465
2466 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2467 if (err)
2468 goto out;
2469 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2470 release_firmware(firmware);
2471out:
2472 rtnl_lock();
2473 dev_put(dev);
2474 return err;
2475}
2476
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002477#define MLXSW_SP_I2C_ADDR_LOW 0x50
2478#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2479#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002480
2481static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2482 u16 offset, u16 size, void *data,
2483 unsigned int *p_read_size)
2484{
2485 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2486 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2487 char mcia_pl[MLXSW_REG_MCIA_LEN];
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002488 u16 i2c_addr;
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002489 int status;
2490 int err;
2491
2492 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002493
2494 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2495 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2496 /* Cross pages read, read until offset 256 in low page */
2497 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2498
2499 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2500 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2501 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2502 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2503 }
2504
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002505 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002506 0, 0, offset, size, i2c_addr);
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002507
2508 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2509 if (err)
2510 return err;
2511
2512 status = mlxsw_reg_mcia_status_get(mcia_pl);
2513 if (status)
2514 return -EIO;
2515
2516 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2517 memcpy(data, eeprom_tmp, size);
2518 *p_read_size = size;
2519
2520 return 0;
2521}
2522
2523enum mlxsw_sp_eeprom_module_info_rev_id {
2524 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2525 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2526 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2527};
2528
2529enum mlxsw_sp_eeprom_module_info_id {
2530 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2531 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2532 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2533 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2534};
2535
2536enum mlxsw_sp_eeprom_module_info {
2537 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2538 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2539 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2540};
2541
2542static int mlxsw_sp_get_module_info(struct net_device *netdev,
2543 struct ethtool_modinfo *modinfo)
2544{
2545 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2546 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2547 u8 module_rev_id, module_id;
2548 unsigned int read_size;
2549 int err;
2550
2551 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2552 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2553 module_info, &read_size);
2554 if (err)
2555 return err;
2556
2557 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2558 return -EIO;
2559
2560 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2561 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2562
2563 switch (module_id) {
2564 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2565 modinfo->type = ETH_MODULE_SFF_8436;
2566 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2567 break;
2568 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2569 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2570 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2571 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2572 modinfo->type = ETH_MODULE_SFF_8636;
2573 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2574 } else {
2575 modinfo->type = ETH_MODULE_SFF_8436;
2576 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2577 }
2578 break;
2579 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2580 modinfo->type = ETH_MODULE_SFF_8472;
2581 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2582 break;
2583 default:
2584 return -EINVAL;
2585 }
2586
2587 return 0;
2588}
2589
2590static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2591 struct ethtool_eeprom *ee,
2592 u8 *data)
2593{
2594 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2595 int offset = ee->offset;
2596 unsigned int read_size;
2597 int i = 0;
2598 int err;
2599
2600 if (!ee->len)
2601 return -EINVAL;
2602
2603 memset(data, 0, ee->len);
2604
2605 while (i < ee->len) {
2606 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2607 ee->len - i, data + i,
2608 &read_size);
2609 if (err) {
2610 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2611 return err;
2612 }
2613
2614 i += read_size;
2615 offset += read_size;
2616 }
2617
2618 return 0;
2619}
2620
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002621static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2622 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2623 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002624 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2625 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002626 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002627 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002628 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2629 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002630 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2631 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002632 .flash_device = mlxsw_sp_flash_device,
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002633 .get_module_info = mlxsw_sp_get_module_info,
2634 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002635};
2636
Ido Schimmel18f1e702016-02-26 17:32:31 +01002637static int
2638mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2639{
2640 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2641 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2642 char ptys_pl[MLXSW_REG_PTYS_LEN];
2643 u32 eth_proto_admin;
2644
2645 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002646 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
Tal Bar8e1ed732018-03-21 09:34:06 +02002647 eth_proto_admin, mlxsw_sp_port->link.autoneg);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002648 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2649}
2650
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002651int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2652 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2653 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002654{
2655 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2656 char qeec_pl[MLXSW_REG_QEEC_LEN];
2657
2658 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2659 next_index);
2660 mlxsw_reg_qeec_de_set(qeec_pl, true);
2661 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2662 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2663 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2664}
2665
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002666int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2667 enum mlxsw_reg_qeec_hr hr, u8 index,
2668 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002669{
2670 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2671 char qeec_pl[MLXSW_REG_QEEC_LEN];
2672
2673 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2674 next_index);
2675 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2676 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2677 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2678}
2679
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002680int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2681 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002682{
2683 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2684 char qtct_pl[MLXSW_REG_QTCT_LEN];
2685
2686 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2687 tclass);
2688 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2689}
2690
2691static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2692{
2693 int err, i;
2694
2695 /* Setup the elements hierarcy, so that each TC is linked to
2696 * one subgroup, which are all member in the same group.
2697 */
2698 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2699 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2700 0);
2701 if (err)
2702 return err;
2703 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2704 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2705 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2706 0, false, 0);
2707 if (err)
2708 return err;
2709 }
2710 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2711 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2712 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2713 false, 0);
2714 if (err)
2715 return err;
2716 }
2717
2718 /* Make sure the max shaper is disabled in all hierarcies that
2719 * support it.
2720 */
2721 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2722 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2723 MLXSW_REG_QEEC_MAS_DIS);
2724 if (err)
2725 return err;
2726 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2727 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2728 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2729 i, 0,
2730 MLXSW_REG_QEEC_MAS_DIS);
2731 if (err)
2732 return err;
2733 }
2734 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2735 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2736 MLXSW_REG_QEEC_HIERARCY_TC,
2737 i, i,
2738 MLXSW_REG_QEEC_MAS_DIS);
2739 if (err)
2740 return err;
2741 }
2742
2743 /* Map all priorities to traffic class 0. */
2744 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2745 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2746 if (err)
2747 return err;
2748 }
2749
2750 return 0;
2751}
2752
Ido Schimmel5b153852017-06-08 08:47:44 +02002753static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2754 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002755{
Ido Schimmelc57529e2017-05-26 08:37:31 +02002756 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002757 struct mlxsw_sp_port *mlxsw_sp_port;
2758 struct net_device *dev;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002759 int err;
2760
Ido Schimmel5b153852017-06-08 08:47:44 +02002761 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2762 if (err) {
2763 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2764 local_port);
2765 return err;
2766 }
2767
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002768 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
Ido Schimmel5b153852017-06-08 08:47:44 +02002769 if (!dev) {
2770 err = -ENOMEM;
2771 goto err_alloc_etherdev;
2772 }
Jiri Pirkof20a91f2016-10-27 15:13:00 +02002773 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002774 mlxsw_sp_port = netdev_priv(dev);
2775 mlxsw_sp_port->dev = dev;
2776 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2777 mlxsw_sp_port->local_port = local_port;
Ido Schimmelc57529e2017-05-26 08:37:31 +02002778 mlxsw_sp_port->pvid = 1;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002779 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02002780 mlxsw_sp_port->mapping.module = module;
2781 mlxsw_sp_port->mapping.width = width;
2782 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002783 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02002784 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02002785 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002786
2787 mlxsw_sp_port->pcpu_stats =
2788 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2789 if (!mlxsw_sp_port->pcpu_stats) {
2790 err = -ENOMEM;
2791 goto err_alloc_stats;
2792 }
2793
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002794 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2795 GFP_KERNEL);
2796 if (!mlxsw_sp_port->sample) {
2797 err = -ENOMEM;
2798 goto err_alloc_sample;
2799 }
2800
Nogah Frankel9deef432017-10-26 10:55:32 +02002801 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002802 &update_stats_cache);
2803
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002804 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2805 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2806
Ido Schimmel2e915e02017-06-08 08:47:45 +02002807 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
Ido Schimmel5b153852017-06-08 08:47:44 +02002808 if (err) {
2809 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2810 mlxsw_sp_port->local_port);
2811 goto err_port_module_map;
2812 }
2813
Ido Schimmel3247ff22016-09-08 08:16:02 +02002814 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2815 if (err) {
2816 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2817 mlxsw_sp_port->local_port);
2818 goto err_port_swid_set;
2819 }
2820
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002821 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2822 if (err) {
2823 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2824 mlxsw_sp_port->local_port);
2825 goto err_dev_addr_init;
2826 }
2827
2828 netif_carrier_off(dev);
2829
2830 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02002831 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2832 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002833
Jarod Wilsond894be52016-10-20 13:55:16 -04002834 dev->min_mtu = 0;
2835 dev->max_mtu = ETH_MAX_MTU;
2836
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002837 /* Each packet needs to have a Tx header (metadata) on top all other
2838 * headers.
2839 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02002840 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002841
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002842 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2843 if (err) {
2844 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2845 mlxsw_sp_port->local_port);
2846 goto err_port_system_port_mapping_set;
2847 }
2848
Ido Schimmel18f1e702016-02-26 17:32:31 +01002849 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2850 if (err) {
2851 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2852 mlxsw_sp_port->local_port);
2853 goto err_port_speed_by_width_set;
2854 }
2855
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002856 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2857 if (err) {
2858 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2859 mlxsw_sp_port->local_port);
2860 goto err_port_mtu_set;
2861 }
2862
2863 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2864 if (err)
2865 goto err_port_admin_status_set;
2866
2867 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2868 if (err) {
2869 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2870 mlxsw_sp_port->local_port);
2871 goto err_port_buffers_init;
2872 }
2873
Ido Schimmel90183b92016-04-06 17:10:08 +02002874 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2875 if (err) {
2876 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2877 mlxsw_sp_port->local_port);
2878 goto err_port_ets_init;
2879 }
2880
Ido Schimmelf00817d2016-04-06 17:10:09 +02002881 /* ETS and buffers must be initialized before DCB. */
2882 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2883 if (err) {
2884 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2885 mlxsw_sp_port->local_port);
2886 goto err_port_dcb_init;
2887 }
2888
Ido Schimmela1107482017-05-26 08:37:39 +02002889 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
Ido Schimmel45a4a162017-05-16 19:38:35 +02002890 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02002891 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
Ido Schimmel45a4a162017-05-16 19:38:35 +02002892 mlxsw_sp_port->local_port);
Ido Schimmela1107482017-05-26 08:37:39 +02002893 goto err_port_fids_init;
Ido Schimmel45a4a162017-05-16 19:38:35 +02002894 }
2895
Nogah Frankel371b4372018-01-10 14:59:57 +01002896 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
2897 if (err) {
2898 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
2899 mlxsw_sp_port->local_port);
2900 goto err_port_qdiscs_init;
2901 }
2902
Ido Schimmelc57529e2017-05-26 08:37:31 +02002903 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
2904 if (IS_ERR(mlxsw_sp_port_vlan)) {
2905 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
Ido Schimmel05978482016-08-17 16:39:30 +02002906 mlxsw_sp_port->local_port);
Wei Yongjund86fd112017-11-06 11:11:28 +00002907 err = PTR_ERR(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002908 goto err_port_vlan_get;
Ido Schimmel05978482016-08-17 16:39:30 +02002909 }
2910
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002911 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02002912 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002913 err = register_netdev(dev);
2914 if (err) {
2915 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2916 mlxsw_sp_port->local_port);
2917 goto err_register_netdev;
2918 }
2919
Elad Razd808c7e2016-10-28 21:35:57 +02002920 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
Jiri Pirkob9ffcba2018-05-18 09:29:00 +02002921 mlxsw_sp_port, dev, module + 1,
2922 mlxsw_sp_port->split, lane / width);
Nogah Frankel9deef432017-10-26 10:55:32 +02002923 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002924 return 0;
2925
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002926err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02002927 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002928 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002929 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
2930err_port_vlan_get:
Nogah Frankel371b4372018-01-10 14:59:57 +01002931 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
2932err_port_qdiscs_init:
Ido Schimmela1107482017-05-26 08:37:39 +02002933 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
2934err_port_fids_init:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03002935 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002936err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02002937err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002938err_port_buffers_init:
2939err_port_admin_status_set:
2940err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01002941err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002942err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002943err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02002944 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2945err_port_swid_set:
Ido Schimmel2e915e02017-06-08 08:47:45 +02002946 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Ido Schimmel5b153852017-06-08 08:47:44 +02002947err_port_module_map:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002948 kfree(mlxsw_sp_port->sample);
2949err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002950 free_percpu(mlxsw_sp_port->pcpu_stats);
2951err_alloc_stats:
2952 free_netdev(dev);
Ido Schimmel5b153852017-06-08 08:47:44 +02002953err_alloc_etherdev:
Jiri Pirko67963a32016-10-28 21:35:55 +02002954 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2955 return err;
2956}
2957
Ido Schimmel5b153852017-06-08 08:47:44 +02002958static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002959{
2960 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2961
Nogah Frankel9deef432017-10-26 10:55:32 +02002962 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02002963 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002964 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02002965 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002966 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002967 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Nogah Frankel371b4372018-01-10 14:59:57 +01002968 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
Ido Schimmela1107482017-05-26 08:37:39 +02002969 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002970 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01002971 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
Ido Schimmel2e915e02017-06-08 08:47:45 +02002972 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002973 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01002974 free_percpu(mlxsw_sp_port->pcpu_stats);
Ido Schimmel31a08a52017-05-26 08:37:26 +02002975 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002976 free_netdev(mlxsw_sp_port->dev);
Jiri Pirko67963a32016-10-28 21:35:55 +02002977 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2978}
2979
Jiri Pirkof83e2102016-10-28 21:35:49 +02002980static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2981{
2982 return mlxsw_sp->ports[local_port] != NULL;
2983}
2984
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002985static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2986{
2987 int i;
2988
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002989 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002990 if (mlxsw_sp_port_created(mlxsw_sp, i))
2991 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002992 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002993 kfree(mlxsw_sp->ports);
2994}
2995
2996static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2997{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002998 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02002999 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003000 size_t alloc_size;
3001 int i;
3002 int err;
3003
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003004 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003005 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3006 if (!mlxsw_sp->ports)
3007 return -ENOMEM;
3008
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003009 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3010 GFP_KERNEL);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003011 if (!mlxsw_sp->port_to_module) {
3012 err = -ENOMEM;
3013 goto err_port_to_module_alloc;
3014 }
3015
3016 for (i = 1; i < max_ports; i++) {
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003017 /* Mark as invalid */
3018 mlxsw_sp->port_to_module[i] = -1;
3019
Ido Schimmel558c2d52016-02-26 17:32:29 +01003020 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003021 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01003022 if (err)
3023 goto err_port_module_info_get;
3024 if (!width)
3025 continue;
3026 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02003027 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3028 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003029 if (err)
3030 goto err_port_create;
3031 }
3032 return 0;
3033
3034err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01003035err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003036 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003037 if (mlxsw_sp_port_created(mlxsw_sp, i))
3038 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003039 kfree(mlxsw_sp->port_to_module);
3040err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003041 kfree(mlxsw_sp->ports);
3042 return err;
3043}
3044
Ido Schimmel18f1e702016-02-26 17:32:31 +01003045static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3046{
3047 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3048
3049 return local_port - offset;
3050}
3051
Ido Schimmelbe945352016-06-09 09:51:39 +02003052static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3053 u8 module, unsigned int count)
3054{
3055 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3056 int err, i;
3057
3058 for (i = 0; i < count; i++) {
Ido Schimmelbe945352016-06-09 09:51:39 +02003059 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02003060 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02003061 if (err)
3062 goto err_port_create;
3063 }
3064
3065 return 0;
3066
3067err_port_create:
3068 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003069 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3070 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02003071 return err;
3072}
3073
3074static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3075 u8 base_port, unsigned int count)
3076{
3077 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3078 int i;
3079
3080 /* Split by four means we need to re-create two ports, otherwise
3081 * only one.
3082 */
3083 count = count / 2;
3084
3085 for (i = 0; i < count; i++) {
3086 local_port = base_port + i * 2;
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003087 if (mlxsw_sp->port_to_module[local_port] < 0)
3088 continue;
Ido Schimmelbe945352016-06-09 09:51:39 +02003089 module = mlxsw_sp->port_to_module[local_port];
3090
Ido Schimmelbe945352016-06-09 09:51:39 +02003091 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003092 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003093 }
3094}
3095
Jiri Pirkob2f10572016-04-08 19:11:23 +02003096static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
David Ahern3fcc7732018-06-05 08:14:11 -07003097 unsigned int count,
3098 struct netlink_ext_ack *extack)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003099{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003100 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003101 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003102 u8 module, cur_width, base_port;
3103 int i;
3104 int err;
3105
3106 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3107 if (!mlxsw_sp_port) {
3108 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3109 local_port);
David Ahern3fcc7732018-06-05 08:14:11 -07003110 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003111 return -EINVAL;
3112 }
3113
Ido Schimmeld664b412016-06-09 09:51:40 +02003114 module = mlxsw_sp_port->mapping.module;
3115 cur_width = mlxsw_sp_port->mapping.width;
3116
Ido Schimmel18f1e702016-02-26 17:32:31 +01003117 if (count != 2 && count != 4) {
3118 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
David Ahern3fcc7732018-06-05 08:14:11 -07003119 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003120 return -EINVAL;
3121 }
3122
Ido Schimmel18f1e702016-02-26 17:32:31 +01003123 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3124 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
David Ahern3fcc7732018-06-05 08:14:11 -07003125 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003126 return -EINVAL;
3127 }
3128
3129 /* Make sure we have enough slave (even) ports for the split. */
3130 if (count == 2) {
3131 base_port = local_port;
3132 if (mlxsw_sp->ports[base_port + 1]) {
3133 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
David Ahern3fcc7732018-06-05 08:14:11 -07003134 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003135 return -EINVAL;
3136 }
3137 } else {
3138 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3139 if (mlxsw_sp->ports[base_port + 1] ||
3140 mlxsw_sp->ports[base_port + 3]) {
3141 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
David Ahern3fcc7732018-06-05 08:14:11 -07003142 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003143 return -EINVAL;
3144 }
3145 }
3146
3147 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003148 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3149 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003150
Ido Schimmelbe945352016-06-09 09:51:39 +02003151 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3152 if (err) {
3153 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3154 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003155 }
3156
3157 return 0;
3158
Ido Schimmelbe945352016-06-09 09:51:39 +02003159err_port_split_create:
3160 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003161 return err;
3162}
3163
David Ahern3fcc7732018-06-05 08:14:11 -07003164static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port,
3165 struct netlink_ext_ack *extack)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003166{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003167 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003168 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003169 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003170 unsigned int count;
3171 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003172
3173 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3174 if (!mlxsw_sp_port) {
3175 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3176 local_port);
David Ahern3fcc7732018-06-05 08:14:11 -07003177 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003178 return -EINVAL;
3179 }
3180
3181 if (!mlxsw_sp_port->split) {
David Ahern3fcc7732018-06-05 08:14:11 -07003182 netdev_err(mlxsw_sp_port->dev, "Port was not split\n");
3183 NL_SET_ERR_MSG_MOD(extack, "Port was not split");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003184 return -EINVAL;
3185 }
3186
Ido Schimmeld664b412016-06-09 09:51:40 +02003187 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003188 count = cur_width == 1 ? 4 : 2;
3189
3190 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3191
3192 /* Determine which ports to remove. */
3193 if (count == 2 && local_port >= base_port + 2)
3194 base_port = base_port + 2;
3195
3196 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003197 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3198 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003199
Ido Schimmelbe945352016-06-09 09:51:39 +02003200 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003201
3202 return 0;
3203}
3204
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003205static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3206 char *pude_pl, void *priv)
3207{
3208 struct mlxsw_sp *mlxsw_sp = priv;
3209 struct mlxsw_sp_port *mlxsw_sp_port;
3210 enum mlxsw_reg_pude_oper_status status;
3211 u8 local_port;
3212
3213 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3214 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003215 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003216 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003217
3218 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3219 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3220 netdev_info(mlxsw_sp_port->dev, "link up\n");
3221 netif_carrier_on(mlxsw_sp_port->dev);
3222 } else {
3223 netdev_info(mlxsw_sp_port->dev, "link down\n");
3224 netif_carrier_off(mlxsw_sp_port->dev);
3225 }
3226}
3227
Nogah Frankel14eeda92016-11-25 10:33:32 +01003228static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3229 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003230{
3231 struct mlxsw_sp *mlxsw_sp = priv;
3232 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3233 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3234
3235 if (unlikely(!mlxsw_sp_port)) {
3236 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3237 local_port);
3238 return;
3239 }
3240
3241 skb->dev = mlxsw_sp_port->dev;
3242
3243 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3244 u64_stats_update_begin(&pcpu_stats->syncp);
3245 pcpu_stats->rx_packets++;
3246 pcpu_stats->rx_bytes += skb->len;
3247 u64_stats_update_end(&pcpu_stats->syncp);
3248
3249 skb->protocol = eth_type_trans(skb, skb->dev);
3250 netif_receive_skb(skb);
3251}
3252
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003253static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3254 void *priv)
3255{
3256 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003257 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003258}
3259
Yotam Gigia0040c82017-10-03 09:58:10 +02003260static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3261 u8 local_port, void *priv)
3262{
3263 skb->offload_mr_fwd_mark = 1;
3264 skb->offload_fwd_mark = 1;
3265 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3266}
3267
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003268static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3269 void *priv)
3270{
3271 struct mlxsw_sp *mlxsw_sp = priv;
3272 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3273 struct psample_group *psample_group;
3274 u32 size;
3275
3276 if (unlikely(!mlxsw_sp_port)) {
3277 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3278 local_port);
3279 goto out;
3280 }
3281 if (unlikely(!mlxsw_sp_port->sample)) {
3282 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3283 local_port);
3284 goto out;
3285 }
3286
3287 size = mlxsw_sp_port->sample->truncate ?
3288 mlxsw_sp_port->sample->trunc_size : skb->len;
3289
3290 rcu_read_lock();
3291 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3292 if (!psample_group)
3293 goto out_unlock;
3294 psample_sample_packet(psample_group, skb, size,
3295 mlxsw_sp_port->dev->ifindex, 0,
3296 mlxsw_sp_port->sample->rate);
3297out_unlock:
3298 rcu_read_unlock();
3299out:
3300 consume_skb(skb);
3301}
3302
Nogah Frankel117b0da2016-11-25 10:33:44 +01003303#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003304 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003305 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003306
Nogah Frankel117b0da2016-11-25 10:33:44 +01003307#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003308 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003309 _is_ctrl, SP_##_trap_group, DISCARD)
3310
Yotam Gigia0040c82017-10-03 09:58:10 +02003311#define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3312 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3313 _is_ctrl, SP_##_trap_group, DISCARD)
3314
Nogah Frankel117b0da2016-11-25 10:33:44 +01003315#define MLXSW_SP_EVENTL(_func, _trap_id) \
3316 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003317
Nogah Frankel45449132016-11-25 10:33:35 +01003318static const struct mlxsw_listener mlxsw_sp_listener[] = {
3319 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003320 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003321 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003322 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3323 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3324 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3325 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3326 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3327 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3328 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3329 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3330 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3331 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3332 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003333 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003334 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3335 false),
3336 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3337 false),
3338 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3339 false),
3340 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3341 false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003342 /* L3 traps */
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003343 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3344 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3345 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003346 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003347 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3348 false),
3349 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3350 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3351 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3352 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3353 false),
3354 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3355 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3356 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003357 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003358 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3359 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3360 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3361 false),
3362 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3363 false),
3364 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3365 false),
3366 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3367 false),
3368 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3369 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3370 false),
3371 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3372 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
Ido Schimmel7607dd32017-07-17 14:15:30 +02003373 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003374 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
Petr Machata86484de2017-09-02 23:49:27 +02003375 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003376 /* PKT Sample trap */
3377 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
Jiri Pirko0db7b382017-06-06 14:12:05 +02003378 false, SP_IP2ME, DISCARD),
3379 /* ACL trap */
3380 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
Yotam Gigib48cfc82017-09-19 10:00:20 +02003381 /* Multicast Router Traps */
3382 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
Yuval Mintz6a170d32018-03-26 15:01:45 +03003383 MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false),
Yotam Gigib48cfc82017-09-19 10:00:20 +02003384 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3385 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
Yotam Gigia0040c82017-10-03 09:58:10 +02003386 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003387};
3388
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003389static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3390{
3391 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3392 enum mlxsw_reg_qpcr_ir_units ir_units;
3393 int max_cpu_policers;
3394 bool is_bytes;
3395 u8 burst_size;
3396 u32 rate;
3397 int i, err;
3398
3399 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3400 return -EIO;
3401
3402 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3403
3404 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3405 for (i = 0; i < max_cpu_policers; i++) {
3406 is_bytes = false;
3407 switch (i) {
3408 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3409 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3410 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3411 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003412 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3413 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003414 rate = 128;
3415 burst_size = 7;
3416 break;
3417 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003418 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003419 rate = 16 * 1024;
3420 burst_size = 10;
3421 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003422 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003423 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3424 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003425 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003426 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3427 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003428 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003429 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003430 rate = 1024;
3431 burst_size = 7;
3432 break;
3433 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3434 is_bytes = true;
3435 rate = 4 * 1024;
3436 burst_size = 4;
3437 break;
3438 default:
3439 continue;
3440 }
3441
3442 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3443 burst_size);
3444 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3445 if (err)
3446 return err;
3447 }
3448
3449 return 0;
3450}
3451
Nogah Frankel579c82e2016-11-25 10:33:42 +01003452static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003453{
3454 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003455 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003456 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003457 int max_trap_groups;
3458 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003459 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003460 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003461
3462 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3463 return -EIO;
3464
3465 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003466 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003467
3468 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003469 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003470 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003471 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3472 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3473 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3474 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003475 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003476 priority = 5;
3477 tc = 5;
3478 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003479 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003480 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3481 priority = 4;
3482 tc = 4;
3483 break;
3484 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3485 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003486 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003487 priority = 3;
3488 tc = 3;
3489 break;
3490 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003491 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003492 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003493 priority = 2;
3494 tc = 2;
3495 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003496 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003497 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3498 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003499 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003500 priority = 1;
3501 tc = 1;
3502 break;
3503 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003504 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3505 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003506 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003507 break;
3508 default:
3509 continue;
3510 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003511
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003512 if (max_cpu_policers <= policer_id &&
3513 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3514 return -EIO;
3515
3516 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003517 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3518 if (err)
3519 return err;
3520 }
3521
3522 return 0;
3523}
3524
3525static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3526{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003527 int i;
3528 int err;
3529
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003530 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3531 if (err)
3532 return err;
3533
Nogah Frankel579c82e2016-11-25 10:33:42 +01003534 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003535 if (err)
3536 return err;
3537
Nogah Frankel45449132016-11-25 10:33:35 +01003538 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003539 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003540 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003541 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003542 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003543 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003544
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003545 }
3546 return 0;
3547
Nogah Frankel45449132016-11-25 10:33:35 +01003548err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003549 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003550 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003551 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003552 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003553 }
3554 return err;
3555}
3556
3557static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3558{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003559 int i;
3560
Nogah Frankel45449132016-11-25 10:33:35 +01003561 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003562 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003563 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003564 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003565 }
3566}
3567
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003568static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3569{
3570 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003571 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003572
3573 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3574 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3575 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3576 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3577 MLXSW_REG_SLCR_LAG_HASH_SIP |
3578 MLXSW_REG_SLCR_LAG_HASH_DIP |
3579 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3580 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3581 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003582 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3583 if (err)
3584 return err;
3585
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003586 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3587 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003588 return -EIO;
3589
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003590 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003591 sizeof(struct mlxsw_sp_upper),
3592 GFP_KERNEL);
3593 if (!mlxsw_sp->lags)
3594 return -ENOMEM;
3595
3596 return 0;
3597}
3598
3599static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3600{
3601 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003602}
3603
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003604static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3605{
3606 char htgt_pl[MLXSW_REG_HTGT_LEN];
3607
Nogah Frankel579c82e2016-11-25 10:33:42 +01003608 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3609 MLXSW_REG_HTGT_INVALID_POLICER,
3610 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3611 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003612 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3613}
3614
Petr Machatac30f5d02017-10-16 16:26:35 +02003615static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3616 unsigned long event, void *ptr);
3617
Jiri Pirkob2f10572016-04-08 19:11:23 +02003618static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003619 const struct mlxsw_bus_info *mlxsw_bus_info)
3620{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003621 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003622 int err;
3623
Jiri Pirkoebcff742018-07-08 23:51:16 +03003624 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
Jiri Pirko9dbab6f2018-07-08 10:00:19 +03003625 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
Jiri Pirko8fae4392018-07-08 23:51:19 +03003626 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
Jiri Pirko9dbab6f2018-07-08 10:00:19 +03003627
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003628 mlxsw_sp->core = mlxsw_core;
3629 mlxsw_sp->bus_info = mlxsw_bus_info;
3630
Yotam Gigi6b742192017-05-23 21:56:29 +02003631 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3632 if (err) {
3633 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3634 return err;
3635 }
3636
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003637 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3638 if (err) {
3639 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3640 return err;
3641 }
3642
Ido Schimmela875a2e2017-10-22 23:11:44 +02003643 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3644 if (err) {
3645 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3646 return err;
3647 }
3648
Ido Schimmela1107482017-05-26 08:37:39 +02003649 err = mlxsw_sp_fids_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003650 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003651 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
Ido Schimmela875a2e2017-10-22 23:11:44 +02003652 goto err_fids_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003653 }
3654
Ido Schimmela1107482017-05-26 08:37:39 +02003655 err = mlxsw_sp_traps_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003656 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003657 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3658 goto err_traps_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003659 }
3660
3661 err = mlxsw_sp_buffers_init(mlxsw_sp);
3662 if (err) {
3663 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3664 goto err_buffers_init;
3665 }
3666
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003667 err = mlxsw_sp_lag_init(mlxsw_sp);
3668 if (err) {
3669 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3670 goto err_lag_init;
3671 }
3672
Petr Machatacda880de2018-04-29 10:56:11 +03003673 /* Initialize SPAN before router and switchdev, so that those components
3674 * can call mlxsw_sp_span_respin().
3675 */
3676 err = mlxsw_sp_span_init(mlxsw_sp);
3677 if (err) {
3678 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3679 goto err_span_init;
3680 }
3681
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003682 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3683 if (err) {
3684 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3685 goto err_switchdev_init;
3686 }
3687
Yotam Gigie2b2d352017-09-19 10:00:08 +02003688 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3689 if (err) {
3690 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3691 goto err_counter_pool_init;
3692 }
3693
Yotam Gigid3b939b2017-09-19 10:00:09 +02003694 err = mlxsw_sp_afa_init(mlxsw_sp);
3695 if (err) {
3696 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3697 goto err_afa_init;
3698 }
3699
Ido Schimmel464dce12016-07-02 11:00:15 +02003700 err = mlxsw_sp_router_init(mlxsw_sp);
3701 if (err) {
3702 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3703 goto err_router_init;
3704 }
3705
Petr Machata803335a2018-02-27 14:53:46 +01003706 /* Initialize netdevice notifier after router and SPAN is initialized,
3707 * so that the event handler can use router structures and call SPAN
3708 * respin.
Petr Machatac30f5d02017-10-16 16:26:35 +02003709 */
3710 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3711 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3712 if (err) {
3713 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3714 goto err_netdev_notifier;
3715 }
3716
Jiri Pirko22a67762017-02-03 10:29:07 +01003717 err = mlxsw_sp_acl_init(mlxsw_sp);
3718 if (err) {
3719 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3720 goto err_acl_init;
3721 }
3722
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003723 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3724 if (err) {
3725 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3726 goto err_dpipe_init;
3727 }
3728
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003729 err = mlxsw_sp_ports_create(mlxsw_sp);
3730 if (err) {
3731 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3732 goto err_ports_create;
3733 }
3734
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003735 return 0;
3736
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003737err_ports_create:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003738 mlxsw_sp_dpipe_fini(mlxsw_sp);
3739err_dpipe_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01003740 mlxsw_sp_acl_fini(mlxsw_sp);
3741err_acl_init:
Petr Machatac30f5d02017-10-16 16:26:35 +02003742 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3743err_netdev_notifier:
Ido Schimmel464dce12016-07-02 11:00:15 +02003744 mlxsw_sp_router_fini(mlxsw_sp);
3745err_router_init:
Yotam Gigid3b939b2017-09-19 10:00:09 +02003746 mlxsw_sp_afa_fini(mlxsw_sp);
3747err_afa_init:
Yotam Gigie2b2d352017-09-19 10:00:08 +02003748 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3749err_counter_pool_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003750 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003751err_switchdev_init:
Petr Machatacda880de2018-04-29 10:56:11 +03003752 mlxsw_sp_span_fini(mlxsw_sp);
3753err_span_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003754 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003755err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02003756 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003757err_buffers_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003758 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003759err_traps_init:
3760 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003761err_fids_init:
3762 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003763 return err;
3764}
3765
Jiri Pirkob2f10572016-04-08 19:11:23 +02003766static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003767{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003768 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003769
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003770 mlxsw_sp_ports_remove(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003771 mlxsw_sp_dpipe_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01003772 mlxsw_sp_acl_fini(mlxsw_sp);
Petr Machatac30f5d02017-10-16 16:26:35 +02003773 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
Ido Schimmel464dce12016-07-02 11:00:15 +02003774 mlxsw_sp_router_fini(mlxsw_sp);
Yotam Gigid3b939b2017-09-19 10:00:09 +02003775 mlxsw_sp_afa_fini(mlxsw_sp);
Yotam Gigie2b2d352017-09-19 10:00:08 +02003776 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003777 mlxsw_sp_switchdev_fini(mlxsw_sp);
Petr Machatacda880de2018-04-29 10:56:11 +03003778 mlxsw_sp_span_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003779 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02003780 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003781 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003782 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003783 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003784}
3785
Bhumika Goyal159fe882017-08-11 19:10:42 +05303786static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003787 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01003788 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003789 .used_flood_tables = 1,
3790 .used_flood_mode = 1,
3791 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003792 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003793 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003794 .max_fid_flood_tables = 3,
Ido Schimmela1107482017-05-26 08:37:39 +02003795 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003796 .used_max_ib_mc = 1,
3797 .max_ib_mc = 0,
3798 .used_max_pkey = 1,
3799 .max_pkey = 0,
Jiri Pirko110d2d22018-04-01 17:34:56 +03003800 .used_kvd_sizes = 1,
Ido Schimmelf11fbaf2017-10-22 23:11:49 +02003801 .kvd_hash_single_parts = 59,
3802 .kvd_hash_double_parts = 41,
Jiri Pirkoc6022422016-07-05 11:27:46 +02003803 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003804 .swid_config = {
3805 {
3806 .used_type = 1,
3807 .type = MLXSW_PORT_SWID_TYPE_ETH,
3808 }
3809 },
3810};
3811
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003812static void
Jiri Pirko77d27092018-02-28 13:12:09 +01003813mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
3814 struct devlink_resource_size_params *kvd_size_params,
3815 struct devlink_resource_size_params *linear_size_params,
3816 struct devlink_resource_size_params *hash_double_size_params,
3817 struct devlink_resource_size_params *hash_single_size_params)
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003818{
3819 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3820 KVD_SINGLE_MIN_SIZE);
3821 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3822 KVD_DOUBLE_MIN_SIZE);
3823 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3824 u32 linear_size_min = 0;
3825
Jiri Pirko77d27092018-02-28 13:12:09 +01003826 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
3827 MLXSW_SP_KVD_GRANULARITY,
3828 DEVLINK_RESOURCE_UNIT_ENTRY);
3829 devlink_resource_size_params_init(linear_size_params, linear_size_min,
3830 kvd_size - single_size_min -
3831 double_size_min,
3832 MLXSW_SP_KVD_GRANULARITY,
3833 DEVLINK_RESOURCE_UNIT_ENTRY);
3834 devlink_resource_size_params_init(hash_double_size_params,
3835 double_size_min,
3836 kvd_size - single_size_min -
3837 linear_size_min,
3838 MLXSW_SP_KVD_GRANULARITY,
3839 DEVLINK_RESOURCE_UNIT_ENTRY);
3840 devlink_resource_size_params_init(hash_single_size_params,
3841 single_size_min,
3842 kvd_size - double_size_min -
3843 linear_size_min,
3844 MLXSW_SP_KVD_GRANULARITY,
3845 DEVLINK_RESOURCE_UNIT_ENTRY);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003846}
3847
3848static int mlxsw_sp_resources_register(struct mlxsw_core *mlxsw_core)
3849{
3850 struct devlink *devlink = priv_to_devlink(mlxsw_core);
Jiri Pirko77d27092018-02-28 13:12:09 +01003851 struct devlink_resource_size_params hash_single_size_params;
3852 struct devlink_resource_size_params hash_double_size_params;
3853 struct devlink_resource_size_params linear_size_params;
3854 struct devlink_resource_size_params kvd_size_params;
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003855 u32 kvd_size, single_size, double_size, linear_size;
3856 const struct mlxsw_config_profile *profile;
3857 int err;
3858
3859 profile = &mlxsw_sp_config_profile;
3860 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
3861 return -EIO;
3862
Jiri Pirko77d27092018-02-28 13:12:09 +01003863 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
3864 &linear_size_params,
3865 &hash_double_size_params,
3866 &hash_single_size_params);
3867
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003868 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3869 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
David Ahern14530742018-03-20 19:31:14 -07003870 kvd_size, MLXSW_SP_RESOURCE_KVD,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003871 DEVLINK_RESOURCE_ID_PARENT_TOP,
Jiri Pirkofc56be42018-04-05 22:13:21 +02003872 &kvd_size_params);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003873 if (err)
3874 return err;
3875
3876 linear_size = profile->kvd_linear_size;
3877 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
David Ahern14530742018-03-20 19:31:14 -07003878 linear_size,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003879 MLXSW_SP_RESOURCE_KVD_LINEAR,
3880 MLXSW_SP_RESOURCE_KVD,
Jiri Pirkofc56be42018-04-05 22:13:21 +02003881 &linear_size_params);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003882 if (err)
3883 return err;
3884
Jiri Pirkoebcff742018-07-08 23:51:16 +03003885 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
Arkadi Sharshevsky51d3c082018-02-20 08:44:22 +01003886 if (err)
3887 return err;
3888
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003889 double_size = kvd_size - linear_size;
3890 double_size *= profile->kvd_hash_double_parts;
3891 double_size /= profile->kvd_hash_double_parts +
3892 profile->kvd_hash_single_parts;
Jiri Pirko72779c92018-04-01 17:34:54 +03003893 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003894 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
David Ahern14530742018-03-20 19:31:14 -07003895 double_size,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003896 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3897 MLXSW_SP_RESOURCE_KVD,
Jiri Pirkofc56be42018-04-05 22:13:21 +02003898 &hash_double_size_params);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003899 if (err)
3900 return err;
3901
3902 single_size = kvd_size - double_size - linear_size;
3903 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
David Ahern14530742018-03-20 19:31:14 -07003904 single_size,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003905 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3906 MLXSW_SP_RESOURCE_KVD,
Jiri Pirkofc56be42018-04-05 22:13:21 +02003907 &hash_single_size_params);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003908 if (err)
3909 return err;
3910
3911 return 0;
3912}
3913
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01003914static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
3915 const struct mlxsw_config_profile *profile,
3916 u64 *p_single_size, u64 *p_double_size,
3917 u64 *p_linear_size)
3918{
3919 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3920 u32 double_size;
3921 int err;
3922
3923 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
Jiri Pirko110d2d22018-04-01 17:34:56 +03003924 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01003925 return -EIO;
3926
3927 /* The hash part is what left of the kvd without the
3928 * linear part. It is split to the single size and
3929 * double size by the parts ratio from the profile.
3930 * Both sizes must be a multiplications of the
3931 * granularity from the profile. In case the user
3932 * provided the sizes they are obtained via devlink.
3933 */
3934 err = devlink_resource_size_get(devlink,
3935 MLXSW_SP_RESOURCE_KVD_LINEAR,
3936 p_linear_size);
3937 if (err)
3938 *p_linear_size = profile->kvd_linear_size;
3939
3940 err = devlink_resource_size_get(devlink,
3941 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3942 p_double_size);
3943 if (err) {
3944 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3945 *p_linear_size;
3946 double_size *= profile->kvd_hash_double_parts;
3947 double_size /= profile->kvd_hash_double_parts +
3948 profile->kvd_hash_single_parts;
3949 *p_double_size = rounddown(double_size,
Jiri Pirko72779c92018-04-01 17:34:54 +03003950 MLXSW_SP_KVD_GRANULARITY);
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01003951 }
3952
3953 err = devlink_resource_size_get(devlink,
3954 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3955 p_single_size);
3956 if (err)
3957 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3958 *p_double_size - *p_linear_size;
3959
3960 /* Check results are legal. */
3961 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3962 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
3963 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
3964 return -EIO;
3965
3966 return 0;
3967}
3968
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003969static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02003970 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003971 .priv_size = sizeof(struct mlxsw_sp),
3972 .init = mlxsw_sp_init,
3973 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003974 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003975 .port_split = mlxsw_sp_port_split,
3976 .port_unsplit = mlxsw_sp_port_unsplit,
3977 .sb_pool_get = mlxsw_sp_sb_pool_get,
3978 .sb_pool_set = mlxsw_sp_sb_pool_set,
3979 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3980 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3981 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3982 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3983 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3984 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3985 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3986 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3987 .txhdr_construct = mlxsw_sp_txhdr_construct,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003988 .resources_register = mlxsw_sp_resources_register,
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01003989 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003990 .txhdr_len = MLXSW_TXHDR_LEN,
3991 .profile = &mlxsw_sp_config_profile,
Jiri Pirkoad3f20b2018-04-01 17:34:57 +03003992 .res_query_enabled = true,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003993};
3994
Jiri Pirko22a67762017-02-03 10:29:07 +01003995bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003996{
3997 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3998}
3999
Jiri Pirko1182e532017-03-06 21:25:20 +01004000static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07004001{
Jiri Pirko1182e532017-03-06 21:25:20 +01004002 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07004003 int ret = 0;
4004
4005 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01004006 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07004007 ret = 1;
4008 }
4009
4010 return ret;
4011}
4012
Ido Schimmelc57529e2017-05-26 08:37:31 +02004013struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004014{
Jiri Pirko1182e532017-03-06 21:25:20 +01004015 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004016
4017 if (mlxsw_sp_port_dev_check(dev))
4018 return netdev_priv(dev);
4019
Jiri Pirko1182e532017-03-06 21:25:20 +01004020 mlxsw_sp_port = NULL;
4021 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004022
Jiri Pirko1182e532017-03-06 21:25:20 +01004023 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004024}
4025
Ido Schimmel4724ba562017-03-10 08:53:39 +01004026struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004027{
4028 struct mlxsw_sp_port *mlxsw_sp_port;
4029
4030 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4031 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4032}
4033
Arkadi Sharshevskyaf0613782017-06-08 08:44:20 +02004034struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004035{
Jiri Pirko1182e532017-03-06 21:25:20 +01004036 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004037
4038 if (mlxsw_sp_port_dev_check(dev))
4039 return netdev_priv(dev);
4040
Jiri Pirko1182e532017-03-06 21:25:20 +01004041 mlxsw_sp_port = NULL;
4042 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4043 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004044
Jiri Pirko1182e532017-03-06 21:25:20 +01004045 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004046}
4047
4048struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4049{
4050 struct mlxsw_sp_port *mlxsw_sp_port;
4051
4052 rcu_read_lock();
4053 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4054 if (mlxsw_sp_port)
4055 dev_hold(mlxsw_sp_port->dev);
4056 rcu_read_unlock();
4057 return mlxsw_sp_port;
4058}
4059
4060void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4061{
4062 dev_put(mlxsw_sp_port->dev);
4063}
4064
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004065static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004066{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004067 char sldr_pl[MLXSW_REG_SLDR_LEN];
4068
4069 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4070 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4071}
4072
4073static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4074{
4075 char sldr_pl[MLXSW_REG_SLDR_LEN];
4076
4077 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4078 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4079}
4080
4081static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4082 u16 lag_id, u8 port_index)
4083{
4084 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4085 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4086
4087 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4088 lag_id, port_index);
4089 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4090}
4091
4092static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4093 u16 lag_id)
4094{
4095 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4096 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4097
4098 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4099 lag_id);
4100 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4101}
4102
4103static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4104 u16 lag_id)
4105{
4106 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4107 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4108
4109 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4110 lag_id);
4111 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4112}
4113
4114static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4115 u16 lag_id)
4116{
4117 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4118 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4119
4120 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4121 lag_id);
4122 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4123}
4124
4125static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4126 struct net_device *lag_dev,
4127 u16 *p_lag_id)
4128{
4129 struct mlxsw_sp_upper *lag;
4130 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004131 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004132 int i;
4133
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004134 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4135 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004136 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4137 if (lag->ref_count) {
4138 if (lag->dev == lag_dev) {
4139 *p_lag_id = i;
4140 return 0;
4141 }
4142 } else if (free_lag_id < 0) {
4143 free_lag_id = i;
4144 }
4145 }
4146 if (free_lag_id < 0)
4147 return -EBUSY;
4148 *p_lag_id = free_lag_id;
4149 return 0;
4150}
4151
4152static bool
4153mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4154 struct net_device *lag_dev,
David Aherne58376e2017-10-04 17:48:51 -07004155 struct netdev_lag_upper_info *lag_upper_info,
4156 struct netlink_ext_ack *extack)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004157{
4158 u16 lag_id;
4159
David Aherne58376e2017-10-04 17:48:51 -07004160 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004161 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004162 return false;
David Aherne58376e2017-10-04 17:48:51 -07004163 }
4164 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004165 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004166 return false;
David Aherne58376e2017-10-04 17:48:51 -07004167 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004168 return true;
4169}
4170
4171static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4172 u16 lag_id, u8 *p_port_index)
4173{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004174 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004175 int i;
4176
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004177 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4178 MAX_LAG_MEMBERS);
4179 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004180 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4181 *p_port_index = i;
4182 return 0;
4183 }
4184 }
4185 return -EBUSY;
4186}
4187
4188static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4189 struct net_device *lag_dev)
4190{
4191 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004192 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004193 struct mlxsw_sp_upper *lag;
4194 u16 lag_id;
4195 u8 port_index;
4196 int err;
4197
4198 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4199 if (err)
4200 return err;
4201 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4202 if (!lag->ref_count) {
4203 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4204 if (err)
4205 return err;
4206 lag->dev = lag_dev;
4207 }
4208
4209 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4210 if (err)
4211 return err;
4212 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4213 if (err)
4214 goto err_col_port_add;
4215 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4216 if (err)
4217 goto err_col_port_enable;
4218
4219 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4220 mlxsw_sp_port->local_port);
4221 mlxsw_sp_port->lag_id = lag_id;
4222 mlxsw_sp_port->lagged = 1;
4223 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004224
Ido Schimmelc57529e2017-05-26 08:37:31 +02004225 /* Port is no longer usable as a router interface */
4226 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4227 if (mlxsw_sp_port_vlan->fid)
Ido Schimmela1107482017-05-26 08:37:39 +02004228 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004229
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004230 return 0;
4231
Ido Schimmel51554db2016-05-06 22:18:39 +02004232err_col_port_enable:
4233 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004234err_col_port_add:
4235 if (!lag->ref_count)
4236 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004237 return err;
4238}
4239
Ido Schimmel82e6db02016-06-20 23:04:04 +02004240static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4241 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004242{
4243 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004244 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004245 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004246
4247 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004248 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004249 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4250 WARN_ON(lag->ref_count == 0);
4251
Ido Schimmel82e6db02016-06-20 23:04:04 +02004252 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4253 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004254
Ido Schimmelc57529e2017-05-26 08:37:31 +02004255 /* Any VLANs configured on the port are no longer valid */
4256 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004257
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004258 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004259 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004260
4261 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4262 mlxsw_sp_port->local_port);
4263 mlxsw_sp_port->lagged = 0;
4264 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004265
Ido Schimmelc57529e2017-05-26 08:37:31 +02004266 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4267 /* Make sure untagged frames are allowed to ingress */
4268 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004269}
4270
Jiri Pirko74581202015-12-03 12:12:30 +01004271static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4272 u16 lag_id)
4273{
4274 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4275 char sldr_pl[MLXSW_REG_SLDR_LEN];
4276
4277 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4278 mlxsw_sp_port->local_port);
4279 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4280}
4281
4282static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4283 u16 lag_id)
4284{
4285 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4286 char sldr_pl[MLXSW_REG_SLDR_LEN];
4287
4288 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4289 mlxsw_sp_port->local_port);
4290 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4291}
4292
4293static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4294 bool lag_tx_enabled)
4295{
4296 if (lag_tx_enabled)
4297 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4298 mlxsw_sp_port->lag_id);
4299 else
4300 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4301 mlxsw_sp_port->lag_id);
4302}
4303
4304static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4305 struct netdev_lag_lower_state_info *info)
4306{
4307 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4308}
4309
Jiri Pirko2b94e582017-04-18 16:55:37 +02004310static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4311 bool enable)
4312{
4313 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4314 enum mlxsw_reg_spms_state spms_state;
4315 char *spms_pl;
4316 u16 vid;
4317 int err;
4318
4319 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4320 MLXSW_REG_SPMS_STATE_DISCARDING;
4321
4322 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4323 if (!spms_pl)
4324 return -ENOMEM;
4325 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4326
4327 for (vid = 0; vid < VLAN_N_VID; vid++)
4328 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4329
4330 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4331 kfree(spms_pl);
4332 return err;
4333}
4334
4335static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4336{
Yuval Mintzfccff082017-12-15 08:44:21 +01004337 u16 vid = 1;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004338 int err;
4339
Ido Schimmel4aafc362017-05-26 08:37:25 +02004340 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004341 if (err)
4342 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02004343 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4344 if (err)
4345 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004346 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4347 true, false);
4348 if (err)
4349 goto err_port_vlan_set;
Yuval Mintzfccff082017-12-15 08:44:21 +01004350
4351 for (; vid <= VLAN_N_VID - 1; vid++) {
4352 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4353 vid, false);
4354 if (err)
4355 goto err_vid_learning_set;
4356 }
4357
Jiri Pirko2b94e582017-04-18 16:55:37 +02004358 return 0;
4359
Yuval Mintzfccff082017-12-15 08:44:21 +01004360err_vid_learning_set:
4361 for (vid--; vid >= 1; vid--)
4362 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004363err_port_vlan_set:
4364 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004365err_port_stp_set:
4366 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004367 return err;
4368}
4369
4370static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4371{
Yuval Mintzfccff082017-12-15 08:44:21 +01004372 u16 vid;
4373
4374 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4375 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4376 vid, true);
4377
Jiri Pirko2b94e582017-04-18 16:55:37 +02004378 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4379 false, false);
4380 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004381 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004382}
4383
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004384static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4385 struct net_device *dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004386 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004387{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004388 struct netdev_notifier_changeupper_info *info;
4389 struct mlxsw_sp_port *mlxsw_sp_port;
David Aherne58376e2017-10-04 17:48:51 -07004390 struct netlink_ext_ack *extack;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004391 struct net_device *upper_dev;
4392 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004393 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004394
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004395 mlxsw_sp_port = netdev_priv(dev);
4396 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4397 info = ptr;
David Aherne58376e2017-10-04 17:48:51 -07004398 extack = netdev_notifier_info_to_extack(&info->info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004399
4400 switch (event) {
4401 case NETDEV_PRECHANGEUPPER:
4402 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004403 if (!is_vlan_dev(upper_dev) &&
4404 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004405 !netif_is_bridge_master(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004406 !netif_is_ovs_master(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004407 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004408 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004409 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004410 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004411 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004412 if (netdev_has_any_upper_dev(upper_dev) &&
4413 (!netif_is_bridge_master(upper_dev) ||
4414 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4415 upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004416 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004417 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004418 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004419 if (netif_is_lag_master(upper_dev) &&
4420 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
David Aherne58376e2017-10-04 17:48:51 -07004421 info->upper_info, extack))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004422 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004423 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004424 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004425 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004426 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004427 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004428 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004429 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004430 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004431 }
4432 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004433 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004434 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004435 }
4436 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004437 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004438 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004439 }
Petr Machata47bf9df2018-05-27 09:48:41 +03004440 if (is_vlan_dev(upper_dev) &&
4441 vlan_dev_vlan_id(upper_dev) == 1) {
4442 NL_SET_ERR_MSG_MOD(extack, "Creating a VLAN device with VID 1 is unsupported: VLAN 1 carries untagged traffic");
4443 return -EINVAL;
4444 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004445 break;
4446 case NETDEV_CHANGEUPPER:
4447 upper_dev = info->upper_dev;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004448 if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004449 if (info->linking)
4450 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004451 lower_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004452 upper_dev,
4453 extack);
Ido Schimmel7117a572016-06-20 23:04:06 +02004454 else
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004455 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4456 lower_dev,
4457 upper_dev);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004458 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004459 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004460 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4461 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004462 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004463 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4464 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004465 } else if (netif_is_ovs_master(upper_dev)) {
4466 if (info->linking)
4467 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4468 else
4469 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004470 }
4471 break;
4472 }
4473
Ido Schimmel80bedf12016-06-20 23:03:59 +02004474 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004475}
4476
Jiri Pirko74581202015-12-03 12:12:30 +01004477static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4478 unsigned long event, void *ptr)
4479{
4480 struct netdev_notifier_changelowerstate_info *info;
4481 struct mlxsw_sp_port *mlxsw_sp_port;
4482 int err;
4483
4484 mlxsw_sp_port = netdev_priv(dev);
4485 info = ptr;
4486
4487 switch (event) {
4488 case NETDEV_CHANGELOWERSTATE:
4489 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4490 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4491 info->lower_state_info);
4492 if (err)
4493 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4494 }
4495 break;
4496 }
4497
Ido Schimmel80bedf12016-06-20 23:03:59 +02004498 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004499}
4500
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004501static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4502 struct net_device *port_dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004503 unsigned long event, void *ptr)
4504{
4505 switch (event) {
4506 case NETDEV_PRECHANGEUPPER:
4507 case NETDEV_CHANGEUPPER:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004508 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4509 event, ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004510 case NETDEV_CHANGELOWERSTATE:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004511 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4512 ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004513 }
4514
Ido Schimmel80bedf12016-06-20 23:03:59 +02004515 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004516}
4517
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004518static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4519 unsigned long event, void *ptr)
4520{
4521 struct net_device *dev;
4522 struct list_head *iter;
4523 int ret;
4524
4525 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4526 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004527 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4528 ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004529 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004530 return ret;
4531 }
4532 }
4533
Ido Schimmel80bedf12016-06-20 23:03:59 +02004534 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004535}
4536
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004537static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4538 struct net_device *dev,
4539 unsigned long event, void *ptr,
4540 u16 vid)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004541{
4542 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel90045fc2017-12-25 09:05:33 +01004543 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004544 struct netdev_notifier_changeupper_info *info = ptr;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004545 struct netlink_ext_ack *extack;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004546 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004547 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004548
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004549 extack = netdev_notifier_info_to_extack(&info->info);
4550
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004551 switch (event) {
4552 case NETDEV_PRECHANGEUPPER:
4553 upper_dev = info->upper_dev;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004554 if (!netif_is_bridge_master(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004555 NL_SET_ERR_MSG_MOD(extack, "VLAN devices only support bridge and VRF uppers");
Ido Schimmel80bedf12016-06-20 23:03:59 +02004556 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004557 }
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004558 if (!info->linking)
4559 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004560 if (netdev_has_any_upper_dev(upper_dev) &&
4561 (!netif_is_bridge_master(upper_dev) ||
4562 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4563 upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004564 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004565 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004566 }
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004567 break;
4568 case NETDEV_CHANGEUPPER:
4569 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004570 if (netif_is_bridge_master(upper_dev)) {
4571 if (info->linking)
Ido Schimmelc57529e2017-05-26 08:37:31 +02004572 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4573 vlan_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004574 upper_dev,
4575 extack);
Ido Schimmel1f880612017-03-10 08:53:35 +01004576 else
Ido Schimmelc57529e2017-05-26 08:37:31 +02004577 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4578 vlan_dev,
4579 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004580 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004581 err = -EINVAL;
4582 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004583 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004584 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004585 }
4586
Ido Schimmel80bedf12016-06-20 23:03:59 +02004587 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004588}
4589
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004590static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4591 struct net_device *lag_dev,
4592 unsigned long event,
4593 void *ptr, u16 vid)
Ido Schimmel272c4472015-12-15 16:03:47 +01004594{
4595 struct net_device *dev;
4596 struct list_head *iter;
4597 int ret;
4598
4599 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4600 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004601 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4602 event, ptr,
4603 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004604 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004605 return ret;
4606 }
4607 }
4608
Ido Schimmel80bedf12016-06-20 23:03:59 +02004609 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004610}
4611
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004612static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4613 unsigned long event, void *ptr)
4614{
4615 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4616 u16 vid = vlan_dev_vlan_id(vlan_dev);
4617
Ido Schimmel272c4472015-12-15 16:03:47 +01004618 if (mlxsw_sp_port_dev_check(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004619 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4620 event, ptr, vid);
Ido Schimmel272c4472015-12-15 16:03:47 +01004621 else if (netif_is_lag_master(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004622 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4623 real_dev, event,
4624 ptr, vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004625
Ido Schimmel80bedf12016-06-20 23:03:59 +02004626 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004627}
4628
Ido Schimmelb1e45522017-04-30 19:47:14 +03004629static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4630{
4631 struct netdev_notifier_changeupper_info *info = ptr;
4632
4633 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4634 return false;
4635 return netif_is_l3_master(info->upper_dev);
4636}
4637
Petr Machata00635872017-10-16 16:26:37 +02004638static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004639 unsigned long event, void *ptr)
4640{
4641 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Petr Machata079c9f32018-02-27 14:53:44 +01004642 struct mlxsw_sp_span_entry *span_entry;
Petr Machata00635872017-10-16 16:26:37 +02004643 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004644 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004645
Petr Machata00635872017-10-16 16:26:37 +02004646 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
Petr Machata079c9f32018-02-27 14:53:44 +01004647 if (event == NETDEV_UNREGISTER) {
4648 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
4649 if (span_entry)
4650 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
4651 }
Petr Machata803335a2018-02-27 14:53:46 +01004652 mlxsw_sp_span_respin(mlxsw_sp);
Petr Machata079c9f32018-02-27 14:53:44 +01004653
Petr Machata796ec772017-11-03 10:03:29 +01004654 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
4655 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
4656 event, ptr);
Petr Machata61481f22017-11-03 10:03:41 +01004657 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
4658 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
4659 event, ptr);
Petr Machata00635872017-10-16 16:26:37 +02004660 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004661 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03004662 else if (mlxsw_sp_is_vrf_event(event, ptr))
4663 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004664 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004665 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004666 else if (netif_is_lag_master(dev))
4667 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4668 else if (is_vlan_dev(dev))
4669 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004670
Ido Schimmel80bedf12016-06-20 23:03:59 +02004671 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004672}
4673
David Ahern89d5dd22017-10-18 09:56:55 -07004674static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
4675 .notifier_call = mlxsw_sp_inetaddr_valid_event,
4676};
4677
Ido Schimmel99724c12016-07-04 08:23:14 +02004678static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4679 .notifier_call = mlxsw_sp_inetaddr_event,
David Ahern89d5dd22017-10-18 09:56:55 -07004680};
4681
4682static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
4683 .notifier_call = mlxsw_sp_inet6addr_valid_event,
Ido Schimmel99724c12016-07-04 08:23:14 +02004684};
4685
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004686static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
4687 .notifier_call = mlxsw_sp_inet6addr_event,
4688};
4689
Jiri Pirko1d20d232016-10-27 15:12:59 +02004690static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4691 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4692 {0, },
4693};
4694
4695static struct pci_driver mlxsw_sp_pci_driver = {
4696 .name = mlxsw_sp_driver_name,
4697 .id_table = mlxsw_sp_pci_id_table,
4698};
4699
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004700static int __init mlxsw_sp_module_init(void)
4701{
4702 int err;
4703
David Ahern89d5dd22017-10-18 09:56:55 -07004704 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004705 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004706 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004707 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004708
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004709 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4710 if (err)
4711 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02004712
4713 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4714 if (err)
4715 goto err_pci_driver_register;
4716
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004717 return 0;
4718
Jiri Pirko1d20d232016-10-27 15:12:59 +02004719err_pci_driver_register:
4720 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004721err_core_driver_register:
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004722 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004723 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02004724 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004725 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004726 return err;
4727}
4728
4729static void __exit mlxsw_sp_module_exit(void)
4730{
Jiri Pirko1d20d232016-10-27 15:12:59 +02004731 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004732 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004733 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004734 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004735 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004736 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004737}
4738
4739module_init(mlxsw_sp_module_init);
4740module_exit(mlxsw_sp_module_exit);
4741
4742MODULE_LICENSE("Dual BSD/GPL");
4743MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4744MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02004745MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Yotam Gigi6b742192017-05-23 21:56:29 +02004746MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);