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Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1	//===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
				2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
				9	// This file was originally auto-generated from a GPU register header file and
				10	// all the instruction definitions were originally commented out. Instructions
				11	// that are not yet supported remain commented out.
				12	//===----------------------------------------------------------------------===//
				13
Eric Christopher	7792e32	2015-01-30 23:24:40 +0000	[diff] [blame]	14	def isGCN : Predicate<"Subtarget->getGeneration() "
Matt Arsenault	43e92fe	2016-06-24 06:30:11 +0000	[diff] [blame]	15	">= SISubtarget::SOUTHERN_ISLANDS">,
Tom Stellard	d7e6f13	2015-04-08 01:09:26 +0000	[diff] [blame]	16	AssemblerPredicate<"FeatureGCN">;
Marek Olsak	7d77728	2015-03-24 13:40:15 +0000	[diff] [blame]	17	def isSI : Predicate<"Subtarget->getGeneration() "
Matt Arsenault	43e92fe	2016-06-24 06:30:11 +0000	[diff] [blame]	18	"== SISubtarget::SOUTHERN_ISLANDS">,
Matt Arsenault	d6adfb4	2015-09-24 19:52:21 +0000	[diff] [blame]	19	AssemblerPredicate<"FeatureSouthernIslands">;
				20
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	21	def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
				22	def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
				23
Valery Pykhtin	a34fb49	2016-08-30 15:20:31 +0000	[diff] [blame]	24	include "SOPInstructions.td"
				25
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	26	let SubtargetPredicate = isGCN in {
Tom Stellard	0e70de5	2014-05-16 20:56:45 +0000	[diff] [blame]	27
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	28	//===----------------------------------------------------------------------===//
Tom Stellard	3a35d8f	2014-10-01 14:44:45 +0000	[diff] [blame]	29	// EXP Instructions
				30	//===----------------------------------------------------------------------===//
				31
				32	defm EXP : EXP_m;
				33
				34	//===----------------------------------------------------------------------===//
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	35	// SMRD Instructions
				36	//===----------------------------------------------------------------------===//
				37
Artem Tamazov	38e496b	2016-04-29 17:04:50 +0000	[diff] [blame]	38	// We are using the SReg_32_XM0 and not the SReg_32 register class for 32-bit
				39	// SMRD instructions, because the SReg_32_XM0 register class does not include M0
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	40	// and writing to M0 from an SMRD instruction will hang the GPU.
Artem Tamazov	38e496b	2016-04-29 17:04:50 +0000	[diff] [blame]	41	defm S_LOAD_DWORD : SMRD_Helper <smrd<0x00>, "s_load_dword", SReg_64, SReg_32_XM0>;
Matt Arsenault	0a3ac1b	2015-08-22 00:54:31 +0000	[diff] [blame]	42	defm S_LOAD_DWORDX2 : SMRD_Helper <smrd<0x01>, "s_load_dwordx2", SReg_64, SReg_64>;
				43	defm S_LOAD_DWORDX4 : SMRD_Helper <smrd<0x02>, "s_load_dwordx4", SReg_64, SReg_128>;
				44	defm S_LOAD_DWORDX8 : SMRD_Helper <smrd<0x03>, "s_load_dwordx8", SReg_64, SReg_256>;
				45	defm S_LOAD_DWORDX16 : SMRD_Helper <smrd<0x04>, "s_load_dwordx16", SReg_64, SReg_512>;
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	46
				47	defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
Artem Tamazov	38e496b	2016-04-29 17:04:50 +0000	[diff] [blame]	48	smrd<0x08>, "s_buffer_load_dword", SReg_128, SReg_32_XM0
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	49	>;
				50
				51	defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
Matt Arsenault	0a3ac1b	2015-08-22 00:54:31 +0000	[diff] [blame]	52	smrd<0x09>, "s_buffer_load_dwordx2", SReg_128, SReg_64
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	53	>;
				54
				55	defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
Matt Arsenault	0a3ac1b	2015-08-22 00:54:31 +0000	[diff] [blame]	56	smrd<0x0a>, "s_buffer_load_dwordx4", SReg_128, SReg_128
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	57	>;
				58
				59	defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
Matt Arsenault	0a3ac1b	2015-08-22 00:54:31 +0000	[diff] [blame]	60	smrd<0x0b>, "s_buffer_load_dwordx8", SReg_128, SReg_256
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	61	>;
				62
				63	defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
Matt Arsenault	0a3ac1b	2015-08-22 00:54:31 +0000	[diff] [blame]	64	smrd<0x0c>, "s_buffer_load_dwordx16", SReg_128, SReg_512
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	65	>;
				66
Matt Arsenault	61738cb	2016-02-27 08:53:46 +0000	[diff] [blame]	67	let mayStore = ? in {
				68	// FIXME: mayStore = ? is a workaround for tablegen bug for different
				69	// inferred mayStore flags for the instruction pattern vs. standalone
				70	// Pat. Each considers the other contradictory.
				71
				72	defm S_MEMTIME : SMRD_Special <smrd<0x1e, 0x24>, "s_memtime",
Valery Pykhtin	a4db224	2016-03-10 13:06:08 +0000	[diff] [blame]	73	(outs SReg_64:$sdst), ?, " $sdst", [(set i64:$sdst, (int_amdgcn_s_memtime))]
Matt Arsenault	61738cb	2016-02-27 08:53:46 +0000	[diff] [blame]	74	>;
				75	}
Matt Arsenault	e66621b	2015-09-24 19:52:27 +0000	[diff] [blame]	76
				77	defm S_DCACHE_INV : SMRD_Inval <smrd<0x1f, 0x20>, "s_dcache_inv",
				78	int_amdgcn_s_dcache_inv>;
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	79
				80	//===----------------------------------------------------------------------===//
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	81
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	82	// VOPC Instructions
				83	//===----------------------------------------------------------------------===//
				84
Matt Arsenault	0943b0e	2015-03-23 18:45:38 +0000	[diff] [blame]	85	let isCompare = 1, isCommutable = 1 in {
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	86
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	87	defm V_CMP_F_F32 : VOPC_F32 <vopc<0x0, 0x40>, "v_cmp_f_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	88	defm V_CMP_LT_F32 : VOPC_F32 <vopc<0x1, 0x41>, "v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	89	defm V_CMP_EQ_F32 : VOPC_F32 <vopc<0x2, 0x42>, "v_cmp_eq_f32", COND_OEQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	90	defm V_CMP_LE_F32 : VOPC_F32 <vopc<0x3, 0x43>, "v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	91	defm V_CMP_GT_F32 : VOPC_F32 <vopc<0x4, 0x44>, "v_cmp_gt_f32", COND_OGT>;
Matt Arsenault	9cded7a	2014-12-11 22:15:35 +0000	[diff] [blame]	92	defm V_CMP_LG_F32 : VOPC_F32 <vopc<0x5, 0x45>, "v_cmp_lg_f32", COND_ONE>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	93	defm V_CMP_GE_F32 : VOPC_F32 <vopc<0x6, 0x46>, "v_cmp_ge_f32", COND_OGE>;
				94	defm V_CMP_O_F32 : VOPC_F32 <vopc<0x7, 0x47>, "v_cmp_o_f32", COND_O>;
				95	defm V_CMP_U_F32 : VOPC_F32 <vopc<0x8, 0x48>, "v_cmp_u_f32", COND_UO>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	96	defm V_CMP_NGE_F32 : VOPC_F32 <vopc<0x9, 0x49>, "v_cmp_nge_f32", COND_ULT, "v_cmp_nle_f32">;
Matt Arsenault	58d502f	2014-12-11 22:15:43 +0000	[diff] [blame]	97	defm V_CMP_NLG_F32 : VOPC_F32 <vopc<0xa, 0x4a>, "v_cmp_nlg_f32", COND_UEQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	98	defm V_CMP_NGT_F32 : VOPC_F32 <vopc<0xb, 0x4b>, "v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">;
Matt Arsenault	8b989ef	2014-12-11 22:15:39 +0000	[diff] [blame]	99	defm V_CMP_NLE_F32 : VOPC_F32 <vopc<0xc, 0x4c>, "v_cmp_nle_f32", COND_UGT>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	100	defm V_CMP_NEQ_F32 : VOPC_F32 <vopc<0xd, 0x4d>, "v_cmp_neq_f32", COND_UNE>;
Matt Arsenault	8b989ef	2014-12-11 22:15:39 +0000	[diff] [blame]	101	defm V_CMP_NLT_F32 : VOPC_F32 <vopc<0xe, 0x4e>, "v_cmp_nlt_f32", COND_UGE>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	102	defm V_CMP_TRU_F32 : VOPC_F32 <vopc<0xf, 0x4f>, "v_cmp_tru_f32">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	103
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	104
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	105	defm V_CMPX_F_F32 : VOPCX_F32 <vopc<0x10, 0x50>, "v_cmpx_f_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	106	defm V_CMPX_LT_F32 : VOPCX_F32 <vopc<0x11, 0x51>, "v_cmpx_lt_f32", "v_cmpx_gt_f32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	107	defm V_CMPX_EQ_F32 : VOPCX_F32 <vopc<0x12, 0x52>, "v_cmpx_eq_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	108	defm V_CMPX_LE_F32 : VOPCX_F32 <vopc<0x13, 0x53>, "v_cmpx_le_f32", "v_cmpx_ge_f32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	109	defm V_CMPX_GT_F32 : VOPCX_F32 <vopc<0x14, 0x54>, "v_cmpx_gt_f32">;
				110	defm V_CMPX_LG_F32 : VOPCX_F32 <vopc<0x15, 0x55>, "v_cmpx_lg_f32">;
				111	defm V_CMPX_GE_F32 : VOPCX_F32 <vopc<0x16, 0x56>, "v_cmpx_ge_f32">;
				112	defm V_CMPX_O_F32 : VOPCX_F32 <vopc<0x17, 0x57>, "v_cmpx_o_f32">;
				113	defm V_CMPX_U_F32 : VOPCX_F32 <vopc<0x18, 0x58>, "v_cmpx_u_f32">;
				114	defm V_CMPX_NGE_F32 : VOPCX_F32 <vopc<0x19, 0x59>, "v_cmpx_nge_f32">;
				115	defm V_CMPX_NLG_F32 : VOPCX_F32 <vopc<0x1a, 0x5a>, "v_cmpx_nlg_f32">;
				116	defm V_CMPX_NGT_F32 : VOPCX_F32 <vopc<0x1b, 0x5b>, "v_cmpx_ngt_f32">;
				117	defm V_CMPX_NLE_F32 : VOPCX_F32 <vopc<0x1c, 0x5c>, "v_cmpx_nle_f32">;
				118	defm V_CMPX_NEQ_F32 : VOPCX_F32 <vopc<0x1d, 0x5d>, "v_cmpx_neq_f32">;
				119	defm V_CMPX_NLT_F32 : VOPCX_F32 <vopc<0x1e, 0x5e>, "v_cmpx_nlt_f32">;
				120	defm V_CMPX_TRU_F32 : VOPCX_F32 <vopc<0x1f, 0x5f>, "v_cmpx_tru_f32">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	121
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	122
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	123	defm V_CMP_F_F64 : VOPC_F64 <vopc<0x20, 0x60>, "v_cmp_f_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	124	defm V_CMP_LT_F64 : VOPC_F64 <vopc<0x21, 0x61>, "v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	125	defm V_CMP_EQ_F64 : VOPC_F64 <vopc<0x22, 0x62>, "v_cmp_eq_f64", COND_OEQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	126	defm V_CMP_LE_F64 : VOPC_F64 <vopc<0x23, 0x63>, "v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	127	defm V_CMP_GT_F64 : VOPC_F64 <vopc<0x24, 0x64>, "v_cmp_gt_f64", COND_OGT>;
Matt Arsenault	9cded7a	2014-12-11 22:15:35 +0000	[diff] [blame]	128	defm V_CMP_LG_F64 : VOPC_F64 <vopc<0x25, 0x65>, "v_cmp_lg_f64", COND_ONE>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	129	defm V_CMP_GE_F64 : VOPC_F64 <vopc<0x26, 0x66>, "v_cmp_ge_f64", COND_OGE>;
				130	defm V_CMP_O_F64 : VOPC_F64 <vopc<0x27, 0x67>, "v_cmp_o_f64", COND_O>;
				131	defm V_CMP_U_F64 : VOPC_F64 <vopc<0x28, 0x68>, "v_cmp_u_f64", COND_UO>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	132	defm V_CMP_NGE_F64 : VOPC_F64 <vopc<0x29, 0x69>, "v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">;
Matt Arsenault	58d502f	2014-12-11 22:15:43 +0000	[diff] [blame]	133	defm V_CMP_NLG_F64 : VOPC_F64 <vopc<0x2a, 0x6a>, "v_cmp_nlg_f64", COND_UEQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	134	defm V_CMP_NGT_F64 : VOPC_F64 <vopc<0x2b, 0x6b>, "v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">;
Matt Arsenault	8b989ef	2014-12-11 22:15:39 +0000	[diff] [blame]	135	defm V_CMP_NLE_F64 : VOPC_F64 <vopc<0x2c, 0x6c>, "v_cmp_nle_f64", COND_UGT>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	136	defm V_CMP_NEQ_F64 : VOPC_F64 <vopc<0x2d, 0x6d>, "v_cmp_neq_f64", COND_UNE>;
Matt Arsenault	8b989ef	2014-12-11 22:15:39 +0000	[diff] [blame]	137	defm V_CMP_NLT_F64 : VOPC_F64 <vopc<0x2e, 0x6e>, "v_cmp_nlt_f64", COND_UGE>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	138	defm V_CMP_TRU_F64 : VOPC_F64 <vopc<0x2f, 0x6f>, "v_cmp_tru_f64">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	139
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	140
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	141	defm V_CMPX_F_F64 : VOPCX_F64 <vopc<0x30, 0x70>, "v_cmpx_f_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	142	defm V_CMPX_LT_F64 : VOPCX_F64 <vopc<0x31, 0x71>, "v_cmpx_lt_f64", "v_cmpx_gt_f64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	143	defm V_CMPX_EQ_F64 : VOPCX_F64 <vopc<0x32, 0x72>, "v_cmpx_eq_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	144	defm V_CMPX_LE_F64 : VOPCX_F64 <vopc<0x33, 0x73>, "v_cmpx_le_f64", "v_cmpx_ge_f64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	145	defm V_CMPX_GT_F64 : VOPCX_F64 <vopc<0x34, 0x74>, "v_cmpx_gt_f64">;
				146	defm V_CMPX_LG_F64 : VOPCX_F64 <vopc<0x35, 0x75>, "v_cmpx_lg_f64">;
				147	defm V_CMPX_GE_F64 : VOPCX_F64 <vopc<0x36, 0x76>, "v_cmpx_ge_f64">;
				148	defm V_CMPX_O_F64 : VOPCX_F64 <vopc<0x37, 0x77>, "v_cmpx_o_f64">;
				149	defm V_CMPX_U_F64 : VOPCX_F64 <vopc<0x38, 0x78>, "v_cmpx_u_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	150	defm V_CMPX_NGE_F64 : VOPCX_F64 <vopc<0x39, 0x79>, "v_cmpx_nge_f64", "v_cmpx_nle_f64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	151	defm V_CMPX_NLG_F64 : VOPCX_F64 <vopc<0x3a, 0x7a>, "v_cmpx_nlg_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	152	defm V_CMPX_NGT_F64 : VOPCX_F64 <vopc<0x3b, 0x7b>, "v_cmpx_ngt_f64", "v_cmpx_nlt_f64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	153	defm V_CMPX_NLE_F64 : VOPCX_F64 <vopc<0x3c, 0x7c>, "v_cmpx_nle_f64">;
				154	defm V_CMPX_NEQ_F64 : VOPCX_F64 <vopc<0x3d, 0x7d>, "v_cmpx_neq_f64">;
				155	defm V_CMPX_NLT_F64 : VOPCX_F64 <vopc<0x3e, 0x7e>, "v_cmpx_nlt_f64">;
				156	defm V_CMPX_TRU_F64 : VOPCX_F64 <vopc<0x3f, 0x7f>, "v_cmpx_tru_f64">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	157
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	158
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	159	let SubtargetPredicate = isSICI in {
				160
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	161	defm V_CMPS_F_F32 : VOPC_F32 <vopc<0x40>, "v_cmps_f_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	162	defm V_CMPS_LT_F32 : VOPC_F32 <vopc<0x41>, "v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	163	defm V_CMPS_EQ_F32 : VOPC_F32 <vopc<0x42>, "v_cmps_eq_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	164	defm V_CMPS_LE_F32 : VOPC_F32 <vopc<0x43>, "v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	165	defm V_CMPS_GT_F32 : VOPC_F32 <vopc<0x44>, "v_cmps_gt_f32">;
				166	defm V_CMPS_LG_F32 : VOPC_F32 <vopc<0x45>, "v_cmps_lg_f32">;
				167	defm V_CMPS_GE_F32 : VOPC_F32 <vopc<0x46>, "v_cmps_ge_f32">;
				168	defm V_CMPS_O_F32 : VOPC_F32 <vopc<0x47>, "v_cmps_o_f32">;
				169	defm V_CMPS_U_F32 : VOPC_F32 <vopc<0x48>, "v_cmps_u_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	170	defm V_CMPS_NGE_F32 : VOPC_F32 <vopc<0x49>, "v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	171	defm V_CMPS_NLG_F32 : VOPC_F32 <vopc<0x4a>, "v_cmps_nlg_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	172	defm V_CMPS_NGT_F32 : VOPC_F32 <vopc<0x4b>, "v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	173	defm V_CMPS_NLE_F32 : VOPC_F32 <vopc<0x4c>, "v_cmps_nle_f32">;
				174	defm V_CMPS_NEQ_F32 : VOPC_F32 <vopc<0x4d>, "v_cmps_neq_f32">;
				175	defm V_CMPS_NLT_F32 : VOPC_F32 <vopc<0x4e>, "v_cmps_nlt_f32">;
				176	defm V_CMPS_TRU_F32 : VOPC_F32 <vopc<0x4f>, "v_cmps_tru_f32">;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	177
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	178
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	179	defm V_CMPSX_F_F32 : VOPCX_F32 <vopc<0x50>, "v_cmpsx_f_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	180	defm V_CMPSX_LT_F32 : VOPCX_F32 <vopc<0x51>, "v_cmpsx_lt_f32", "v_cmpsx_gt_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	181	defm V_CMPSX_EQ_F32 : VOPCX_F32 <vopc<0x52>, "v_cmpsx_eq_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	182	defm V_CMPSX_LE_F32 : VOPCX_F32 <vopc<0x53>, "v_cmpsx_le_f32", "v_cmpsx_ge_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	183	defm V_CMPSX_GT_F32 : VOPCX_F32 <vopc<0x54>, "v_cmpsx_gt_f32">;
				184	defm V_CMPSX_LG_F32 : VOPCX_F32 <vopc<0x55>, "v_cmpsx_lg_f32">;
				185	defm V_CMPSX_GE_F32 : VOPCX_F32 <vopc<0x56>, "v_cmpsx_ge_f32">;
				186	defm V_CMPSX_O_F32 : VOPCX_F32 <vopc<0x57>, "v_cmpsx_o_f32">;
				187	defm V_CMPSX_U_F32 : VOPCX_F32 <vopc<0x58>, "v_cmpsx_u_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	188	defm V_CMPSX_NGE_F32 : VOPCX_F32 <vopc<0x59>, "v_cmpsx_nge_f32", "v_cmpsx_nle_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	189	defm V_CMPSX_NLG_F32 : VOPCX_F32 <vopc<0x5a>, "v_cmpsx_nlg_f32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	190	defm V_CMPSX_NGT_F32 : VOPCX_F32 <vopc<0x5b>, "v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	191	defm V_CMPSX_NLE_F32 : VOPCX_F32 <vopc<0x5c>, "v_cmpsx_nle_f32">;
				192	defm V_CMPSX_NEQ_F32 : VOPCX_F32 <vopc<0x5d>, "v_cmpsx_neq_f32">;
				193	defm V_CMPSX_NLT_F32 : VOPCX_F32 <vopc<0x5e>, "v_cmpsx_nlt_f32">;
				194	defm V_CMPSX_TRU_F32 : VOPCX_F32 <vopc<0x5f>, "v_cmpsx_tru_f32">;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	195
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	196
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	197	defm V_CMPS_F_F64 : VOPC_F64 <vopc<0x60>, "v_cmps_f_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	198	defm V_CMPS_LT_F64 : VOPC_F64 <vopc<0x61>, "v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	199	defm V_CMPS_EQ_F64 : VOPC_F64 <vopc<0x62>, "v_cmps_eq_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	200	defm V_CMPS_LE_F64 : VOPC_F64 <vopc<0x63>, "v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	201	defm V_CMPS_GT_F64 : VOPC_F64 <vopc<0x64>, "v_cmps_gt_f64">;
				202	defm V_CMPS_LG_F64 : VOPC_F64 <vopc<0x65>, "v_cmps_lg_f64">;
				203	defm V_CMPS_GE_F64 : VOPC_F64 <vopc<0x66>, "v_cmps_ge_f64">;
				204	defm V_CMPS_O_F64 : VOPC_F64 <vopc<0x67>, "v_cmps_o_f64">;
				205	defm V_CMPS_U_F64 : VOPC_F64 <vopc<0x68>, "v_cmps_u_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	206	defm V_CMPS_NGE_F64 : VOPC_F64 <vopc<0x69>, "v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	207	defm V_CMPS_NLG_F64 : VOPC_F64 <vopc<0x6a>, "v_cmps_nlg_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	208	defm V_CMPS_NGT_F64 : VOPC_F64 <vopc<0x6b>, "v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	209	defm V_CMPS_NLE_F64 : VOPC_F64 <vopc<0x6c>, "v_cmps_nle_f64">;
				210	defm V_CMPS_NEQ_F64 : VOPC_F64 <vopc<0x6d>, "v_cmps_neq_f64">;
				211	defm V_CMPS_NLT_F64 : VOPC_F64 <vopc<0x6e>, "v_cmps_nlt_f64">;
				212	defm V_CMPS_TRU_F64 : VOPC_F64 <vopc<0x6f>, "v_cmps_tru_f64">;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	213
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	214
Matt Arsenault	05b617f	2015-03-23 18:45:23 +0000	[diff] [blame]	215	defm V_CMPSX_F_F64 : VOPCX_F64 <vopc<0x70>, "v_cmpsx_f_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	216	defm V_CMPSX_LT_F64 : VOPCX_F64 <vopc<0x71>, "v_cmpsx_lt_f64", "v_cmpsx_gt_f64">;
Matt Arsenault	05b617f	2015-03-23 18:45:23 +0000	[diff] [blame]	217	defm V_CMPSX_EQ_F64 : VOPCX_F64 <vopc<0x72>, "v_cmpsx_eq_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	218	defm V_CMPSX_LE_F64 : VOPCX_F64 <vopc<0x73>, "v_cmpsx_le_f64", "v_cmpsx_ge_f64">;
Matt Arsenault	05b617f	2015-03-23 18:45:23 +0000	[diff] [blame]	219	defm V_CMPSX_GT_F64 : VOPCX_F64 <vopc<0x74>, "v_cmpsx_gt_f64">;
				220	defm V_CMPSX_LG_F64 : VOPCX_F64 <vopc<0x75>, "v_cmpsx_lg_f64">;
				221	defm V_CMPSX_GE_F64 : VOPCX_F64 <vopc<0x76>, "v_cmpsx_ge_f64">;
				222	defm V_CMPSX_O_F64 : VOPCX_F64 <vopc<0x77>, "v_cmpsx_o_f64">;
				223	defm V_CMPSX_U_F64 : VOPCX_F64 <vopc<0x78>, "v_cmpsx_u_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	224	defm V_CMPSX_NGE_F64 : VOPCX_F64 <vopc<0x79>, "v_cmpsx_nge_f64", "v_cmpsx_nle_f64">;
Matt Arsenault	05b617f	2015-03-23 18:45:23 +0000	[diff] [blame]	225	defm V_CMPSX_NLG_F64 : VOPCX_F64 <vopc<0x7a>, "v_cmpsx_nlg_f64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	226	defm V_CMPSX_NGT_F64 : VOPCX_F64 <vopc<0x7b>, "v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">;
Matt Arsenault	05b617f	2015-03-23 18:45:23 +0000	[diff] [blame]	227	defm V_CMPSX_NLE_F64 : VOPCX_F64 <vopc<0x7c>, "v_cmpsx_nle_f64">;
				228	defm V_CMPSX_NEQ_F64 : VOPCX_F64 <vopc<0x7d>, "v_cmpsx_neq_f64">;
				229	defm V_CMPSX_NLT_F64 : VOPCX_F64 <vopc<0x7e>, "v_cmpsx_nlt_f64">;
				230	defm V_CMPSX_TRU_F64 : VOPCX_F64 <vopc<0x7f>, "v_cmpsx_tru_f64">;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	231
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	232	} // End SubtargetPredicate = isSICI
				233
				234	defm V_CMP_F_I32 : VOPC_I32 <vopc<0x80, 0xc0>, "v_cmp_f_i32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	235	defm V_CMP_LT_I32 : VOPC_I32 <vopc<0x81, 0xc1>, "v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	236	defm V_CMP_EQ_I32 : VOPC_I32 <vopc<0x82, 0xc2>, "v_cmp_eq_i32", COND_EQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	237	defm V_CMP_LE_I32 : VOPC_I32 <vopc<0x83, 0xc3>, "v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	238	defm V_CMP_GT_I32 : VOPC_I32 <vopc<0x84, 0xc4>, "v_cmp_gt_i32", COND_SGT>;
				239	defm V_CMP_NE_I32 : VOPC_I32 <vopc<0x85, 0xc5>, "v_cmp_ne_i32", COND_NE>;
				240	defm V_CMP_GE_I32 : VOPC_I32 <vopc<0x86, 0xc6>, "v_cmp_ge_i32", COND_SGE>;
				241	defm V_CMP_T_I32 : VOPC_I32 <vopc<0x87, 0xc7>, "v_cmp_t_i32">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	242
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	243
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	244	defm V_CMPX_F_I32 : VOPCX_I32 <vopc<0x90, 0xd0>, "v_cmpx_f_i32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	245	defm V_CMPX_LT_I32 : VOPCX_I32 <vopc<0x91, 0xd1>, "v_cmpx_lt_i32", "v_cmpx_gt_i32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	246	defm V_CMPX_EQ_I32 : VOPCX_I32 <vopc<0x92, 0xd2>, "v_cmpx_eq_i32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	247	defm V_CMPX_LE_I32 : VOPCX_I32 <vopc<0x93, 0xd3>, "v_cmpx_le_i32", "v_cmpx_ge_i32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	248	defm V_CMPX_GT_I32 : VOPCX_I32 <vopc<0x94, 0xd4>, "v_cmpx_gt_i32">;
				249	defm V_CMPX_NE_I32 : VOPCX_I32 <vopc<0x95, 0xd5>, "v_cmpx_ne_i32">;
				250	defm V_CMPX_GE_I32 : VOPCX_I32 <vopc<0x96, 0xd6>, "v_cmpx_ge_i32">;
				251	defm V_CMPX_T_I32 : VOPCX_I32 <vopc<0x97, 0xd7>, "v_cmpx_t_i32">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	252
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	253
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	254	defm V_CMP_F_I64 : VOPC_I64 <vopc<0xa0, 0xe0>, "v_cmp_f_i64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	255	defm V_CMP_LT_I64 : VOPC_I64 <vopc<0xa1, 0xe1>, "v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	256	defm V_CMP_EQ_I64 : VOPC_I64 <vopc<0xa2, 0xe2>, "v_cmp_eq_i64", COND_EQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	257	defm V_CMP_LE_I64 : VOPC_I64 <vopc<0xa3, 0xe3>, "v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	258	defm V_CMP_GT_I64 : VOPC_I64 <vopc<0xa4, 0xe4>, "v_cmp_gt_i64", COND_SGT>;
				259	defm V_CMP_NE_I64 : VOPC_I64 <vopc<0xa5, 0xe5>, "v_cmp_ne_i64", COND_NE>;
				260	defm V_CMP_GE_I64 : VOPC_I64 <vopc<0xa6, 0xe6>, "v_cmp_ge_i64", COND_SGE>;
				261	defm V_CMP_T_I64 : VOPC_I64 <vopc<0xa7, 0xe7>, "v_cmp_t_i64">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	262
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	263
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	264	defm V_CMPX_F_I64 : VOPCX_I64 <vopc<0xb0, 0xf0>, "v_cmpx_f_i64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	265	defm V_CMPX_LT_I64 : VOPCX_I64 <vopc<0xb1, 0xf1>, "v_cmpx_lt_i64", "v_cmpx_gt_i64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	266	defm V_CMPX_EQ_I64 : VOPCX_I64 <vopc<0xb2, 0xf2>, "v_cmpx_eq_i64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	267	defm V_CMPX_LE_I64 : VOPCX_I64 <vopc<0xb3, 0xf3>, "v_cmpx_le_i64", "v_cmpx_ge_i64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	268	defm V_CMPX_GT_I64 : VOPCX_I64 <vopc<0xb4, 0xf4>, "v_cmpx_gt_i64">;
				269	defm V_CMPX_NE_I64 : VOPCX_I64 <vopc<0xb5, 0xf5>, "v_cmpx_ne_i64">;
				270	defm V_CMPX_GE_I64 : VOPCX_I64 <vopc<0xb6, 0xf6>, "v_cmpx_ge_i64">;
				271	defm V_CMPX_T_I64 : VOPCX_I64 <vopc<0xb7, 0xf7>, "v_cmpx_t_i64">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	272
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	273
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	274	defm V_CMP_F_U32 : VOPC_I32 <vopc<0xc0, 0xc8>, "v_cmp_f_u32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	275	defm V_CMP_LT_U32 : VOPC_I32 <vopc<0xc1, 0xc9>, "v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	276	defm V_CMP_EQ_U32 : VOPC_I32 <vopc<0xc2, 0xca>, "v_cmp_eq_u32", COND_EQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	277	defm V_CMP_LE_U32 : VOPC_I32 <vopc<0xc3, 0xcb>, "v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	278	defm V_CMP_GT_U32 : VOPC_I32 <vopc<0xc4, 0xcc>, "v_cmp_gt_u32", COND_UGT>;
				279	defm V_CMP_NE_U32 : VOPC_I32 <vopc<0xc5, 0xcd>, "v_cmp_ne_u32", COND_NE>;
				280	defm V_CMP_GE_U32 : VOPC_I32 <vopc<0xc6, 0xce>, "v_cmp_ge_u32", COND_UGE>;
				281	defm V_CMP_T_U32 : VOPC_I32 <vopc<0xc7, 0xcf>, "v_cmp_t_u32">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	282
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	283
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	284	defm V_CMPX_F_U32 : VOPCX_I32 <vopc<0xd0, 0xd8>, "v_cmpx_f_u32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	285	defm V_CMPX_LT_U32 : VOPCX_I32 <vopc<0xd1, 0xd9>, "v_cmpx_lt_u32", "v_cmpx_gt_u32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	286	defm V_CMPX_EQ_U32 : VOPCX_I32 <vopc<0xd2, 0xda>, "v_cmpx_eq_u32">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	287	defm V_CMPX_LE_U32 : VOPCX_I32 <vopc<0xd3, 0xdb>, "v_cmpx_le_u32", "v_cmpx_le_u32">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	288	defm V_CMPX_GT_U32 : VOPCX_I32 <vopc<0xd4, 0xdc>, "v_cmpx_gt_u32">;
				289	defm V_CMPX_NE_U32 : VOPCX_I32 <vopc<0xd5, 0xdd>, "v_cmpx_ne_u32">;
				290	defm V_CMPX_GE_U32 : VOPCX_I32 <vopc<0xd6, 0xde>, "v_cmpx_ge_u32">;
				291	defm V_CMPX_T_U32 : VOPCX_I32 <vopc<0xd7, 0xdf>, "v_cmpx_t_u32">;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	292
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	293
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	294	defm V_CMP_F_U64 : VOPC_I64 <vopc<0xe0, 0xe8>, "v_cmp_f_u64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	295	defm V_CMP_LT_U64 : VOPC_I64 <vopc<0xe1, 0xe9>, "v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	296	defm V_CMP_EQ_U64 : VOPC_I64 <vopc<0xe2, 0xea>, "v_cmp_eq_u64", COND_EQ>;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	297	defm V_CMP_LE_U64 : VOPC_I64 <vopc<0xe3, 0xeb>, "v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	298	defm V_CMP_GT_U64 : VOPC_I64 <vopc<0xe4, 0xec>, "v_cmp_gt_u64", COND_UGT>;
				299	defm V_CMP_NE_U64 : VOPC_I64 <vopc<0xe5, 0xed>, "v_cmp_ne_u64", COND_NE>;
				300	defm V_CMP_GE_U64 : VOPC_I64 <vopc<0xe6, 0xee>, "v_cmp_ge_u64", COND_UGE>;
				301	defm V_CMP_T_U64 : VOPC_I64 <vopc<0xe7, 0xef>, "v_cmp_t_u64">;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	302
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	303	defm V_CMPX_F_U64 : VOPCX_I64 <vopc<0xf0, 0xf8>, "v_cmpx_f_u64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	304	defm V_CMPX_LT_U64 : VOPCX_I64 <vopc<0xf1, 0xf9>, "v_cmpx_lt_u64", "v_cmpx_gt_u64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	305	defm V_CMPX_EQ_U64 : VOPCX_I64 <vopc<0xf2, 0xfa>, "v_cmpx_eq_u64">;
Matt Arsenault	f5b2cd8	2015-03-23 18:45:30 +0000	[diff] [blame]	306	defm V_CMPX_LE_U64 : VOPCX_I64 <vopc<0xf3, 0xfb>, "v_cmpx_le_u64", "v_cmpx_ge_u64">;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	307	defm V_CMPX_GT_U64 : VOPCX_I64 <vopc<0xf4, 0xfc>, "v_cmpx_gt_u64">;
				308	defm V_CMPX_NE_U64 : VOPCX_I64 <vopc<0xf5, 0xfd>, "v_cmpx_ne_u64">;
				309	defm V_CMPX_GE_U64 : VOPCX_I64 <vopc<0xf6, 0xfe>, "v_cmpx_ge_u64">;
				310	defm V_CMPX_T_U64 : VOPCX_I64 <vopc<0xf7, 0xff>, "v_cmpx_t_u64">;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	311
Matt Arsenault	0943b0e	2015-03-23 18:45:38 +0000	[diff] [blame]	312	} // End isCompare = 1, isCommutable = 1
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	313
Matt Arsenault	4831ce5	2015-01-06 23:00:37 +0000	[diff] [blame]	314	defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <vopc<0x88, 0x10>, "v_cmp_class_f32">;
Matt Arsenault	4831ce5	2015-01-06 23:00:37 +0000	[diff] [blame]	315	defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <vopc<0x98, 0x11>, "v_cmpx_class_f32">;
Matt Arsenault	4831ce5	2015-01-06 23:00:37 +0000	[diff] [blame]	316	defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <vopc<0xa8, 0x12>, "v_cmp_class_f64">;
Matt Arsenault	4831ce5	2015-01-06 23:00:37 +0000	[diff] [blame]	317	defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <vopc<0xb8, 0x13>, "v_cmpx_class_f64">;
Matt Arsenault	42f39e1	2015-03-23 18:45:35 +0000	[diff] [blame]	318
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	319	//===----------------------------------------------------------------------===//
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	320	// MUBUF Instructions
				321	//===----------------------------------------------------------------------===//
Matt Arsenault	dd78b80	2014-03-19 22:19:56 +0000	[diff] [blame]	322
Tom Stellard	aec94b3	2015-02-27 14:59:46 +0000	[diff] [blame]	323	defm BUFFER_LOAD_FORMAT_X : MUBUF_Load_Helper <
				324	mubuf<0x00>, "buffer_load_format_x", VGPR_32
				325	>;
				326	defm BUFFER_LOAD_FORMAT_XY : MUBUF_Load_Helper <
				327	mubuf<0x01>, "buffer_load_format_xy", VReg_64
				328	>;
				329	defm BUFFER_LOAD_FORMAT_XYZ : MUBUF_Load_Helper <
				330	mubuf<0x02>, "buffer_load_format_xyz", VReg_96
				331	>;
				332	defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <
				333	mubuf<0x03>, "buffer_load_format_xyzw", VReg_128
				334	>;
Nicolai Haehnle	b48275f	2016-04-19 21:58:33 +0000	[diff] [blame]	335	defm BUFFER_STORE_FORMAT_X : MUBUF_Store_Helper <
				336	mubuf<0x04>, "buffer_store_format_x", VGPR_32
				337	>;
				338	defm BUFFER_STORE_FORMAT_XY : MUBUF_Store_Helper <
				339	mubuf<0x05>, "buffer_store_format_xy", VReg_64
				340	>;
				341	defm BUFFER_STORE_FORMAT_XYZ : MUBUF_Store_Helper <
				342	mubuf<0x06>, "buffer_store_format_xyz", VReg_96
				343	>;
				344	defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Store_Helper <
				345	mubuf<0x07>, "buffer_store_format_xyzw", VReg_128
				346	>;
Tom Stellard	7c1838d	2014-07-02 20:53:56 +0000	[diff] [blame]	347	defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <
Tom Stellard	17a0ec54	2016-07-04 20:41:48 +0000	[diff] [blame]	348	mubuf<0x08, 0x10>, "buffer_load_ubyte", VGPR_32, i32, mubuf_az_extloadi8
Tom Stellard	7c1838d	2014-07-02 20:53:56 +0000	[diff] [blame]	349	>;
				350	defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <
Tom Stellard	17a0ec54	2016-07-04 20:41:48 +0000	[diff] [blame]	351	mubuf<0x09, 0x11>, "buffer_load_sbyte", VGPR_32, i32, mubuf_sextloadi8
Tom Stellard	7c1838d	2014-07-02 20:53:56 +0000	[diff] [blame]	352	>;
				353	defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <
Tom Stellard	17a0ec54	2016-07-04 20:41:48 +0000	[diff] [blame]	354	mubuf<0x0a, 0x12>, "buffer_load_ushort", VGPR_32, i32, mubuf_az_extloadi16
Tom Stellard	7c1838d	2014-07-02 20:53:56 +0000	[diff] [blame]	355	>;
				356	defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <
Tom Stellard	17a0ec54	2016-07-04 20:41:48 +0000	[diff] [blame]	357	mubuf<0x0b, 0x13>, "buffer_load_sshort", VGPR_32, i32, mubuf_sextloadi16
Tom Stellard	7c1838d	2014-07-02 20:53:56 +0000	[diff] [blame]	358	>;
				359	defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <
Tom Stellard	a6f24c6	2015-12-15 20:55:55 +0000	[diff] [blame]	360	mubuf<0x0c, 0x14>, "buffer_load_dword", VGPR_32, i32, mubuf_load
Tom Stellard	7c1838d	2014-07-02 20:53:56 +0000	[diff] [blame]	361	>;
				362	defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <
Tom Stellard	a6f24c6	2015-12-15 20:55:55 +0000	[diff] [blame]	363	mubuf<0x0d, 0x15>, "buffer_load_dwordx2", VReg_64, v2i32, mubuf_load
Tom Stellard	7c1838d	2014-07-02 20:53:56 +0000	[diff] [blame]	364	>;
				365	defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <
Tom Stellard	a6f24c6	2015-12-15 20:55:55 +0000	[diff] [blame]	366	mubuf<0x0e, 0x17>, "buffer_load_dwordx4", VReg_128, v4i32, mubuf_load
Tom Stellard	7c1838d	2014-07-02 20:53:56 +0000	[diff] [blame]	367	>;
Tom Stellard	d3ee8c1	2013-08-16 01:12:06 +0000	[diff] [blame]	368
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	369	defm BUFFER_STORE_BYTE : MUBUF_Store_Helper <
Marek Olsak	ee98b11	2015-01-27 17:24:58 +0000	[diff] [blame]	370	mubuf<0x18>, "buffer_store_byte", VGPR_32, i32, truncstorei8_global
Tom Stellard	d3ee8c1	2013-08-16 01:12:06 +0000	[diff] [blame]	371	>;
				372
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	373	defm BUFFER_STORE_SHORT : MUBUF_Store_Helper <
Marek Olsak	ee98b11	2015-01-27 17:24:58 +0000	[diff] [blame]	374	mubuf<0x1a>, "buffer_store_short", VGPR_32, i32, truncstorei16_global
Tom Stellard	d3ee8c1	2013-08-16 01:12:06 +0000	[diff] [blame]	375	>;
Tom Stellard	754f80f	2013-04-05 23:31:51 +0000	[diff] [blame]	376
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	377	defm BUFFER_STORE_DWORD : MUBUF_Store_Helper <
Marek Olsak	ee98b11	2015-01-27 17:24:58 +0000	[diff] [blame]	378	mubuf<0x1c>, "buffer_store_dword", VGPR_32, i32, global_store
Tom Stellard	754f80f	2013-04-05 23:31:51 +0000	[diff] [blame]	379	>;
				380
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	381	defm BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
Marek Olsak	ee98b11	2015-01-27 17:24:58 +0000	[diff] [blame]	382	mubuf<0x1d>, "buffer_store_dwordx2", VReg_64, v2i32, global_store
Tom Stellard	754f80f	2013-04-05 23:31:51 +0000	[diff] [blame]	383	>;
Tom Stellard	556d9aa	2013-06-03 17:39:37 +0000	[diff] [blame]	384
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	385	defm BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
Marek Olsak	ee98b11	2015-01-27 17:24:58 +0000	[diff] [blame]	386	mubuf<0x1e, 0x1f>, "buffer_store_dwordx4", VReg_128, v4i32, global_store
Tom Stellard	556d9aa	2013-06-03 17:39:37 +0000	[diff] [blame]	387	>;
Marek Olsak	ee98b11	2015-01-27 17:24:58 +0000	[diff] [blame]	388
Aaron Watry	8114437	2014-10-17 23:33:03 +0000	[diff] [blame]	389	defm BUFFER_ATOMIC_SWAP : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	390	mubuf<0x30, 0x40>, "buffer_atomic_swap", VGPR_32, i32, atomic_swap_global
Aaron Watry	8114437	2014-10-17 23:33:03 +0000	[diff] [blame]	391	>;
Nicolai Haehnle	ad63638	2016-03-18 16:24:31 +0000	[diff] [blame]	392	defm BUFFER_ATOMIC_CMPSWAP : MUBUF_Atomic <
				393	mubuf<0x31, 0x41>, "buffer_atomic_cmpswap", VReg_64, v2i32, null_frag
				394	>;
Tom Stellard	7980fc8	2014-09-25 18:30:26 +0000	[diff] [blame]	395	defm BUFFER_ATOMIC_ADD : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	396	mubuf<0x32, 0x42>, "buffer_atomic_add", VGPR_32, i32, atomic_add_global
Tom Stellard	7980fc8	2014-09-25 18:30:26 +0000	[diff] [blame]	397	>;
Aaron Watry	328f1ba	2014-10-17 23:32:52 +0000	[diff] [blame]	398	defm BUFFER_ATOMIC_SUB : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	399	mubuf<0x33, 0x43>, "buffer_atomic_sub", VGPR_32, i32, atomic_sub_global
Aaron Watry	328f1ba	2014-10-17 23:32:52 +0000	[diff] [blame]	400	>;
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	401	//def BUFFER_ATOMIC_RSUB : MUBUF_ <mubuf<0x34>, "buffer_atomic_rsub", []>; // isn't on CI & VI
Aaron Watry	58c9992	2014-10-17 23:32:57 +0000	[diff] [blame]	402	defm BUFFER_ATOMIC_SMIN : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	403	mubuf<0x35, 0x44>, "buffer_atomic_smin", VGPR_32, i32, atomic_min_global
Aaron Watry	58c9992	2014-10-17 23:32:57 +0000	[diff] [blame]	404	>;
				405	defm BUFFER_ATOMIC_UMIN : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	406	mubuf<0x36, 0x45>, "buffer_atomic_umin", VGPR_32, i32, atomic_umin_global
Aaron Watry	58c9992	2014-10-17 23:32:57 +0000	[diff] [blame]	407	>;
Aaron Watry	29f295d	2014-10-17 23:32:56 +0000	[diff] [blame]	408	defm BUFFER_ATOMIC_SMAX : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	409	mubuf<0x37, 0x46>, "buffer_atomic_smax", VGPR_32, i32, atomic_max_global
Aaron Watry	29f295d	2014-10-17 23:32:56 +0000	[diff] [blame]	410	>;
				411	defm BUFFER_ATOMIC_UMAX : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	412	mubuf<0x38, 0x47>, "buffer_atomic_umax", VGPR_32, i32, atomic_umax_global
Aaron Watry	29f295d	2014-10-17 23:32:56 +0000	[diff] [blame]	413	>;
Aaron Watry	6212780	2014-10-17 23:32:54 +0000	[diff] [blame]	414	defm BUFFER_ATOMIC_AND : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	415	mubuf<0x39, 0x48>, "buffer_atomic_and", VGPR_32, i32, atomic_and_global
Aaron Watry	6212780	2014-10-17 23:32:54 +0000	[diff] [blame]	416	>;
Aaron Watry	8a911e6	2014-10-17 23:32:59 +0000	[diff] [blame]	417	defm BUFFER_ATOMIC_OR : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	418	mubuf<0x3a, 0x49>, "buffer_atomic_or", VGPR_32, i32, atomic_or_global
Aaron Watry	8a911e6	2014-10-17 23:32:59 +0000	[diff] [blame]	419	>;
Aaron Watry	d672ee2	2014-10-17 23:33:01 +0000	[diff] [blame]	420	defm BUFFER_ATOMIC_XOR : MUBUF_Atomic <
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	421	mubuf<0x3b, 0x4a>, "buffer_atomic_xor", VGPR_32, i32, atomic_xor_global
Aaron Watry	d672ee2	2014-10-17 23:33:01 +0000	[diff] [blame]	422	>;
Matt Arsenault	a9dbdca	2016-04-12 14:05:04 +0000	[diff] [blame]	423	defm BUFFER_ATOMIC_INC : MUBUF_Atomic <
				424	mubuf<0x3c, 0x4b>, "buffer_atomic_inc", VGPR_32, i32, atomic_inc_global
				425	>;
				426	defm BUFFER_ATOMIC_DEC : MUBUF_Atomic <
				427	mubuf<0x3d, 0x4c>, "buffer_atomic_dec", VGPR_32, i32, atomic_dec_global
				428	>;
				429
Matt Arsenault	64fa2f4	2016-04-12 14:05:11 +0000	[diff] [blame]	430	//def BUFFER_ATOMIC_FCMPSWAP : MUBUF_Atomic <mubuf<0x3e>, "buffer_atomic_fcmpswap", []>; // isn't on VI
				431	//def BUFFER_ATOMIC_FMIN : MUBUF_Atomic <mubuf<0x3f>, "buffer_atomic_fmin", []>; // isn't on VI
				432	//def BUFFER_ATOMIC_FMAX : MUBUF_Atomic <mubuf<0x40>, "buffer_atomic_fmax", []>; // isn't on VI
				433	defm BUFFER_ATOMIC_SWAP_X2 : MUBUF_Atomic <
				434	mubuf<0x50, 0x60>, "buffer_atomic_swap_x2", VReg_64, i64, atomic_swap_global
				435	>;
Tom Stellard	354a43c	2016-04-01 18:27:37 +0000	[diff] [blame]	436	defm BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_Atomic <
				437	mubuf<0x51, 0x61>, "buffer_atomic_cmpswap_x2", VReg_128, v2i64, null_frag
				438	>;
Matt Arsenault	64fa2f4	2016-04-12 14:05:11 +0000	[diff] [blame]	439	defm BUFFER_ATOMIC_ADD_X2 : MUBUF_Atomic <
				440	mubuf<0x52, 0x62>, "buffer_atomic_add_x2", VReg_64, i64, atomic_add_global
				441	>;
				442	defm BUFFER_ATOMIC_SUB_X2 : MUBUF_Atomic <
				443	mubuf<0x53, 0x63>, "buffer_atomic_sub_x2", VReg_64, i64, atomic_sub_global
				444	>;
				445	//defm BUFFER_ATOMIC_RSUB_X2 : MUBUF_Atomic <mubuf<0x54>, "buffer_atomic_rsub_x2", []>; // isn't on CI & VI
				446	defm BUFFER_ATOMIC_SMIN_X2 : MUBUF_Atomic <
				447	mubuf<0x55, 0x64>, "buffer_atomic_smin_x2", VReg_64, i64, atomic_min_global
				448	>;
				449	defm BUFFER_ATOMIC_UMIN_X2 : MUBUF_Atomic <
				450	mubuf<0x56, 0x65>, "buffer_atomic_umin_x2", VReg_64, i64, atomic_umin_global
				451	>;
				452	defm BUFFER_ATOMIC_SMAX_X2 : MUBUF_Atomic <
				453	mubuf<0x57, 0x66>, "buffer_atomic_smax_x2", VReg_64, i64, atomic_max_global
				454	>;
				455	defm BUFFER_ATOMIC_UMAX_X2 : MUBUF_Atomic <
				456	mubuf<0x58, 0x67>, "buffer_atomic_umax_x2", VReg_64, i64, atomic_umax_global
				457	>;
				458	defm BUFFER_ATOMIC_AND_X2 : MUBUF_Atomic <
				459	mubuf<0x59, 0x68>, "buffer_atomic_and_x2", VReg_64, i64, atomic_and_global
				460	>;
				461	defm BUFFER_ATOMIC_OR_X2 : MUBUF_Atomic <
				462	mubuf<0x5a, 0x69>, "buffer_atomic_or_x2", VReg_64, i64, atomic_or_global
				463	>;
				464	defm BUFFER_ATOMIC_XOR_X2 : MUBUF_Atomic <
				465	mubuf<0x5b, 0x6a>, "buffer_atomic_xor_x2", VReg_64, i64, atomic_xor_global
				466	>;
Matt Arsenault	a9dbdca	2016-04-12 14:05:04 +0000	[diff] [blame]	467	defm BUFFER_ATOMIC_INC_X2 : MUBUF_Atomic <
				468	mubuf<0x5c, 0x6b>, "buffer_atomic_inc_x2", VReg_64, i64, atomic_inc_global
				469	>;
				470	defm BUFFER_ATOMIC_DEC_X2 : MUBUF_Atomic <
				471	mubuf<0x5d, 0x6c>, "buffer_atomic_dec_x2", VReg_64, i64, atomic_dec_global
				472	>;
Marek Olsak	19d9e1f	2015-01-27 17:25:02 +0000	[diff] [blame]	473	//def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <mubuf<0x5e>, "buffer_atomic_fcmpswap_x2", []>; // isn't on VI
				474	//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <mubuf<0x5f>, "buffer_atomic_fmin_x2", []>; // isn't on VI
				475	//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <mubuf<0x60>, "buffer_atomic_fmax_x2", []>; // isn't on VI
Matt Arsenault	d6adfb4	2015-09-24 19:52:21 +0000	[diff] [blame]	476
Tom Stellard	e1818af	2016-02-18 03:42:32 +0000	[diff] [blame]	477	let SubtargetPredicate = isSI, DisableVIDecoder = 1 in {
Matt Arsenault	d6adfb4	2015-09-24 19:52:21 +0000	[diff] [blame]	478	defm BUFFER_WBINVL1_SC : MUBUF_Invalidate <mubuf<0x70>, "buffer_wbinvl1_sc", int_amdgcn_buffer_wbinvl1_sc>; // isn't on CI & VI
				479	}
				480
				481	defm BUFFER_WBINVL1 : MUBUF_Invalidate <mubuf<0x71, 0x3e>, "buffer_wbinvl1", int_amdgcn_buffer_wbinvl1>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	482
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	483	//===----------------------------------------------------------------------===//
				484	// MTBUF Instructions
				485	//===----------------------------------------------------------------------===//
				486
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	487	//def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "tbuffer_load_format_x", []>;
				488	//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "tbuffer_load_format_xy", []>;
				489	//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "tbuffer_load_format_xyz", []>;
				490	defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "tbuffer_load_format_xyzw", VReg_128>;
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	491	defm TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "tbuffer_store_format_x", VGPR_32>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	492	defm TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "tbuffer_store_format_xy", VReg_64>;
				493	defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "tbuffer_store_format_xyz", VReg_128>;
				494	defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "tbuffer_store_format_xyzw", VReg_128>;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	495
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	496	//===----------------------------------------------------------------------===//
				497	// MIMG Instructions
				498	//===----------------------------------------------------------------------===//
Tom Stellard	8909380	2013-02-07 19:39:40 +0000	[diff] [blame]	499
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	500	defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load">;
				501	defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip">;
				502	//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"image_load_pck", 0x00000002>;
				503	//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"image_load_pck_sgn", 0x00000003>;
				504	//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"image_load_mip_pck", 0x00000004>;
				505	//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"image_load_mip_pck_sgn", 0x00000005>;
Nicolai Haehnle	f2c64db	2016-02-18 16:44:18 +0000	[diff] [blame]	506	defm IMAGE_STORE : MIMG_Store <0x00000008, "image_store">;
				507	defm IMAGE_STORE_MIP : MIMG_Store <0x00000009, "image_store_mip">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	508	//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"image_store_pck", 0x0000000a>;
				509	//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"image_store_mip_pck", 0x0000000b>;
				510	defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo">;
Nikolay Haustov	5bf46ac1	2016-03-04 10:39:50 +0000	[diff] [blame]	511	defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimg<0x0f, 0x10>, "image_atomic_swap">;
				512	defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimg<0x10, 0x11>, "image_atomic_cmpswap", VReg_64>;
				513	defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimg<0x11, 0x12>, "image_atomic_add">;
				514	defm IMAGE_ATOMIC_SUB : MIMG_Atomic <mimg<0x12, 0x13>, "image_atomic_sub">;
				515	//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>; -- not on VI
				516	defm IMAGE_ATOMIC_SMIN : MIMG_Atomic <mimg<0x14>, "image_atomic_smin">;
				517	defm IMAGE_ATOMIC_UMIN : MIMG_Atomic <mimg<0x15>, "image_atomic_umin">;
				518	defm IMAGE_ATOMIC_SMAX : MIMG_Atomic <mimg<0x16>, "image_atomic_smax">;
				519	defm IMAGE_ATOMIC_UMAX : MIMG_Atomic <mimg<0x17>, "image_atomic_umax">;
				520	defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimg<0x18>, "image_atomic_and">;
				521	defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimg<0x19>, "image_atomic_or">;
				522	defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimg<0x1a>, "image_atomic_xor">;
				523	defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimg<0x1b>, "image_atomic_inc">;
				524	defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimg<0x1c>, "image_atomic_dec">;
				525	//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d>; -- not on VI
				526	//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>; -- not on VI
				527	//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>; -- not on VI
Michel Danzer	494391b	2015-02-06 02:51:20 +0000	[diff] [blame]	528	defm IMAGE_SAMPLE : MIMG_Sampler_WQM <0x00000020, "image_sample">;
				529	defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <0x00000021, "image_sample_cl">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	530	defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "image_sample_d">;
				531	defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "image_sample_d_cl">;
				532	defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "image_sample_l">;
Michel Danzer	494391b	2015-02-06 02:51:20 +0000	[diff] [blame]	533	defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <0x00000025, "image_sample_b">;
				534	defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <0x00000026, "image_sample_b_cl">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	535	defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "image_sample_lz">;
Michel Danzer	494391b	2015-02-06 02:51:20 +0000	[diff] [blame]	536	defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <0x00000028, "image_sample_c">;
				537	defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <0x00000029, "image_sample_c_cl">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	538	defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "image_sample_c_d">;
				539	defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "image_sample_c_d_cl">;
				540	defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "image_sample_c_l">;
Michel Danzer	494391b	2015-02-06 02:51:20 +0000	[diff] [blame]	541	defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <0x0000002d, "image_sample_c_b">;
				542	defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <0x0000002e, "image_sample_c_b_cl">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	543	defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "image_sample_c_lz">;
Michel Danzer	494391b	2015-02-06 02:51:20 +0000	[diff] [blame]	544	defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <0x00000030, "image_sample_o">;
				545	defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <0x00000031, "image_sample_cl_o">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	546	defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "image_sample_d_o">;
				547	defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "image_sample_d_cl_o">;
				548	defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "image_sample_l_o">;
Michel Danzer	494391b	2015-02-06 02:51:20 +0000	[diff] [blame]	549	defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <0x00000035, "image_sample_b_o">;
				550	defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <0x00000036, "image_sample_b_cl_o">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	551	defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "image_sample_lz_o">;
Michel Danzer	494391b	2015-02-06 02:51:20 +0000	[diff] [blame]	552	defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <0x00000038, "image_sample_c_o">;
				553	defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <0x00000039, "image_sample_c_cl_o">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	554	defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "image_sample_c_d_o">;
				555	defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "image_sample_c_d_cl_o">;
				556	defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "image_sample_c_l_o">;
Michel Danzer	494391b	2015-02-06 02:51:20 +0000	[diff] [blame]	557	defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <0x0000003d, "image_sample_c_b_o">;
				558	defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <0x0000003e, "image_sample_c_b_cl_o">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	559	defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "image_sample_c_lz_o">;
Michel Danzer	494391b	2015-02-06 02:51:20 +0000	[diff] [blame]	560	defm IMAGE_GATHER4 : MIMG_Gather_WQM <0x00000040, "image_gather4">;
				561	defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <0x00000041, "image_gather4_cl">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	562	defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "image_gather4_l">;
Michel Danzer	494391b	2015-02-06 02:51:20 +0000	[diff] [blame]	563	defm IMAGE_GATHER4_B : MIMG_Gather_WQM <0x00000045, "image_gather4_b">;
				564	defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <0x00000046, "image_gather4_b_cl">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	565	defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "image_gather4_lz">;
Michel Danzer	494391b	2015-02-06 02:51:20 +0000	[diff] [blame]	566	defm IMAGE_GATHER4_C : MIMG_Gather_WQM <0x00000048, "image_gather4_c">;
				567	defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <0x00000049, "image_gather4_c_cl">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	568	defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "image_gather4_c_l">;
Michel Danzer	494391b	2015-02-06 02:51:20 +0000	[diff] [blame]	569	defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <0x0000004d, "image_gather4_c_b">;
				570	defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <0x0000004e, "image_gather4_c_b_cl">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	571	defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "image_gather4_c_lz">;
Michel Danzer	494391b	2015-02-06 02:51:20 +0000	[diff] [blame]	572	defm IMAGE_GATHER4_O : MIMG_Gather_WQM <0x00000050, "image_gather4_o">;
				573	defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <0x00000051, "image_gather4_cl_o">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	574	defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "image_gather4_l_o">;
Michel Danzer	494391b	2015-02-06 02:51:20 +0000	[diff] [blame]	575	defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <0x00000055, "image_gather4_b_o">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	576	defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "image_gather4_b_cl_o">;
				577	defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "image_gather4_lz_o">;
Michel Danzer	494391b	2015-02-06 02:51:20 +0000	[diff] [blame]	578	defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <0x00000058, "image_gather4_c_o">;
				579	defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <0x00000059, "image_gather4_c_cl_o">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	580	defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "image_gather4_c_l_o">;
Michel Danzer	494391b	2015-02-06 02:51:20 +0000	[diff] [blame]	581	defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <0x0000005d, "image_gather4_c_b_o">;
				582	defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <0x0000005e, "image_gather4_c_b_cl_o">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	583	defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "image_gather4_c_lz_o">;
Michel Danzer	494391b	2015-02-06 02:51:20 +0000	[diff] [blame]	584	defm IMAGE_GET_LOD : MIMG_Sampler_WQM <0x00000060, "image_get_lod">;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	585	defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "image_sample_cd">;
				586	defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "image_sample_cd_cl">;
				587	defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "image_sample_c_cd">;
				588	defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "image_sample_c_cd_cl">;
				589	defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "image_sample_cd_o">;
				590	defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "image_sample_cd_cl_o">;
				591	defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "image_sample_c_cd_o">;
				592	defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "image_sample_c_cd_cl_o">;
				593	//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>;
				594	//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	595
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	596	//===----------------------------------------------------------------------===//
				597	// VOP1 Instructions
				598	//===----------------------------------------------------------------------===//
				599
Tom Stellard	88e0b25	2015-10-06 15:57:53 +0000	[diff] [blame]	600	let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in {
				601	defm V_NOP : VOP1Inst <vop1<0x0>, "v_nop", VOP_NONE>;
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	602	}
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	603
Matthias Braun	e1a6741	2015-04-24 00:25:50 +0000	[diff] [blame]	604	let isMoveImm = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in {
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	605	defm V_MOV_B32 : VOP1Inst <vop1<0x1>, "v_mov_b32", VOP_I32_I32>;
Matt Arsenault	f273370	2014-07-30 03:18:57 +0000	[diff] [blame]	606	} // End isMoveImm = 1
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	607
Tom Stellard	fbe435d	2014-03-17 17:03:51 +0000	[diff] [blame]	608	let Uses = [EXEC] in {
				609
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	610	// FIXME: Specify SchedRW for READFIRSTLANE_B32
				611
Tom Stellard	fbe435d	2014-03-17 17:03:51 +0000	[diff] [blame]	612	def V_READFIRSTLANE_B32 : VOP1 <
				613	0x00000002,
				614	(outs SReg_32:$vdst),
Changpeng Fang	75f0968	2016-08-24 20:35:23 +0000	[diff] [blame]	615	(ins VGPR_32:$src0),
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	616	"v_readfirstlane_b32 $vdst, $src0",
Changpeng Fang	75f0968	2016-08-24 20:35:23 +0000	[diff] [blame]	617	[(set i32:$vdst, (int_amdgcn_readfirstlane i32:$src0))]
Matt Arsenault	4234542	2016-05-11 00:32:31 +0000	[diff] [blame]	618	> {
				619	let isConvergent = 1;
				620	}
Tom Stellard	fbe435d	2014-03-17 17:03:51 +0000	[diff] [blame]	621
				622	}
				623
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	624	let SchedRW = [WriteQuarterRate32] in {
				625
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	626	defm V_CVT_I32_F64 : VOP1Inst <vop1<0x3>, "v_cvt_i32_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	627	VOP_I32_F64, fp_to_sint
Niels Ole Salscheider	4715d88	2013-08-08 16:06:08 +0000	[diff] [blame]	628	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	629	defm V_CVT_F64_I32 : VOP1Inst <vop1<0x4>, "v_cvt_f64_i32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	630	VOP_F64_I32, sint_to_fp
Niels Ole Salscheider	4715d88	2013-08-08 16:06:08 +0000	[diff] [blame]	631	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	632	defm V_CVT_F32_I32 : VOP1Inst <vop1<0x5>, "v_cvt_f32_i32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	633	VOP_F32_I32, sint_to_fp
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	634	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	635	defm V_CVT_F32_U32 : VOP1Inst <vop1<0x6>, "v_cvt_f32_u32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	636	VOP_F32_I32, uint_to_fp
Tom Stellard	c932d73	2013-05-06 23:02:07 +0000	[diff] [blame]	637	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	638	defm V_CVT_U32_F32 : VOP1Inst <vop1<0x7>, "v_cvt_u32_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	639	VOP_I32_F32, fp_to_uint
Tom Stellard	73c31d5	2013-08-14 22:21:57 +0000	[diff] [blame]	640	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	641	defm V_CVT_I32_F32 : VOP1Inst <vop1<0x8>, "v_cvt_i32_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	642	VOP_I32_F32, fp_to_sint
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	643	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	644	defm V_CVT_F16_F32 : VOP1Inst <vop1<0xa>, "v_cvt_f16_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	645	VOP_I32_F32, fp_to_f16
Matt Arsenault	b0df925	2014-07-10 03:22:20 +0000	[diff] [blame]	646	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	647	defm V_CVT_F32_F16 : VOP1Inst <vop1<0xb>, "v_cvt_f32_f16",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	648	VOP_F32_I32, f16_to_fp
Matt Arsenault	b0df925	2014-07-10 03:22:20 +0000	[diff] [blame]	649	>;
Matt Arsenault	eeb2a7e	2015-01-15 23:58:35 +0000	[diff] [blame]	650	defm V_CVT_RPI_I32_F32 : VOP1Inst <vop1<0xc>, "v_cvt_rpi_i32_f32",
				651	VOP_I32_F32, cvt_rpi_i32_f32>;
				652	defm V_CVT_FLR_I32_F32 : VOP1Inst <vop1<0xd>, "v_cvt_flr_i32_f32",
				653	VOP_I32_F32, cvt_flr_i32_f32>;
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	654	defm V_CVT_OFF_F32_I4 : VOP1Inst <vop1<0x0e>, "v_cvt_off_f32_i4", VOP_F32_I32>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	655	defm V_CVT_F32_F64 : VOP1Inst <vop1<0xf>, "v_cvt_f32_f64",
Michael Kuperstein	2bc3d4d	2016-08-18 20:08:15 +0000	[diff] [blame]	656	VOP_F32_F64, fpround
Niels Ole Salscheider	719fbc9	2013-08-08 16:06:15 +0000	[diff] [blame]	657	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	658	defm V_CVT_F64_F32 : VOP1Inst <vop1<0x10>, "v_cvt_f64_f32",
Michael Kuperstein	2bc3d4d	2016-08-18 20:08:15 +0000	[diff] [blame]	659	VOP_F64_F32, fpextend
Niels Ole Salscheider	719fbc9	2013-08-08 16:06:15 +0000	[diff] [blame]	660	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	661	defm V_CVT_F32_UBYTE0 : VOP1Inst <vop1<0x11>, "v_cvt_f32_ubyte0",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	662	VOP_F32_I32, AMDGPUcvt_f32_ubyte0
Matt Arsenault	364a674	2014-06-11 17:50:44 +0000	[diff] [blame]	663	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	664	defm V_CVT_F32_UBYTE1 : VOP1Inst <vop1<0x12>, "v_cvt_f32_ubyte1",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	665	VOP_F32_I32, AMDGPUcvt_f32_ubyte1
Matt Arsenault	364a674	2014-06-11 17:50:44 +0000	[diff] [blame]	666	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	667	defm V_CVT_F32_UBYTE2 : VOP1Inst <vop1<0x13>, "v_cvt_f32_ubyte2",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	668	VOP_F32_I32, AMDGPUcvt_f32_ubyte2
Matt Arsenault	364a674	2014-06-11 17:50:44 +0000	[diff] [blame]	669	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	670	defm V_CVT_F32_UBYTE3 : VOP1Inst <vop1<0x14>, "v_cvt_f32_ubyte3",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	671	VOP_F32_I32, AMDGPUcvt_f32_ubyte3
Matt Arsenault	364a674	2014-06-11 17:50:44 +0000	[diff] [blame]	672	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	673	defm V_CVT_U32_F64 : VOP1Inst <vop1<0x15>, "v_cvt_u32_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	674	VOP_I32_F64, fp_to_uint
Matt Arsenault	c3a73c3	2014-05-22 03:20:30 +0000	[diff] [blame]	675	>;
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	676	defm V_CVT_F64_U32 : VOP1Inst <vop1<0x16>, "v_cvt_f64_u32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	677	VOP_F64_I32, uint_to_fp
Matt Arsenault	c3a73c3	2014-05-22 03:20:30 +0000	[diff] [blame]	678	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	679
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	680	} // End SchedRW = [WriteQuarterRate32]
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	681
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	682	defm V_FRACT_F32 : VOP1Inst <vop1<0x20, 0x1b>, "v_fract_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	683	VOP_F32_F32, AMDGPUfract
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	684	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	685	defm V_TRUNC_F32 : VOP1Inst <vop1<0x21, 0x1c>, "v_trunc_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	686	VOP_F32_F32, ftrunc
Tom Stellard	9b3d253	2013-05-06 23:02:00 +0000	[diff] [blame]	687	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	688	defm V_CEIL_F32 : VOP1Inst <vop1<0x22, 0x1d>, "v_ceil_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	689	VOP_F32_F32, fceil
Michel Danzer	c3ea404	2013-02-22 11:22:49 +0000	[diff] [blame]	690	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	691	defm V_RNDNE_F32 : VOP1Inst <vop1<0x23, 0x1e>, "v_rndne_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	692	VOP_F32_F32, frint
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	693	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	694	defm V_FLOOR_F32 : VOP1Inst <vop1<0x24, 0x1f>, "v_floor_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	695	VOP_F32_F32, ffloor
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	696	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	697	defm V_EXP_F32 : VOP1Inst <vop1<0x25, 0x20>, "v_exp_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	698	VOP_F32_F32, fexp2
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	699	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	700
				701	let SchedRW = [WriteQuarterRate32] in {
				702
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	703	defm V_LOG_F32 : VOP1Inst <vop1<0x27, 0x21>, "v_log_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	704	VOP_F32_F32, flog2
Michel Danzer	349cabe	2013-02-07 14:55:16 +0000	[diff] [blame]	705	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	706	defm V_RCP_F32 : VOP1Inst <vop1<0x2a, 0x22>, "v_rcp_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	707	VOP_F32_F32, AMDGPUrcp
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	708	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	709	defm V_RCP_IFLAG_F32 : VOP1Inst <vop1<0x2b, 0x23>, "v_rcp_iflag_f32",
				710	VOP_F32_F32
Matt Arsenault	257d48d	2014-06-24 22:13:39 +0000	[diff] [blame]	711	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	712	defm V_RSQ_F32 : VOP1Inst <vop1<0x2e, 0x24>, "v_rsq_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	713	VOP_F32_F32, AMDGPUrsq
Matt Arsenault	1513046	2014-06-05 00:15:55 +0000	[diff] [blame]	714	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	715
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	716	} // End SchedRW = [WriteQuarterRate32]
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	717
				718	let SchedRW = [WriteDouble] in {
				719
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	720	defm V_RCP_F64 : VOP1Inst <vop1<0x2f, 0x25>, "v_rcp_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	721	VOP_F64_F64, AMDGPUrcp
Tom Stellard	7512c08	2013-07-12 18:14:56 +0000	[diff] [blame]	722	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	723	defm V_RSQ_F64 : VOP1Inst <vop1<0x31, 0x26>, "v_rsq_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	724	VOP_F64_F64, AMDGPUrsq
Matt Arsenault	1513046	2014-06-05 00:15:55 +0000	[diff] [blame]	725	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	726
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	727	} // End SchedRW = [WriteDouble];
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	728
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	729	defm V_SQRT_F32 : VOP1Inst <vop1<0x33, 0x27>, "v_sqrt_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	730	VOP_F32_F32, fsqrt
Tom Stellard	8ed7b45	2013-07-12 18:15:13 +0000	[diff] [blame]	731	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	732
				733	let SchedRW = [WriteDouble] in {
				734
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	735	defm V_SQRT_F64 : VOP1Inst <vop1<0x34, 0x28>, "v_sqrt_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	736	VOP_F64_F64, fsqrt
Tom Stellard	8ed7b45	2013-07-12 18:15:13 +0000	[diff] [blame]	737	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	738
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	739	} // End SchedRW = [WriteDouble]
				740
				741	let SchedRW = [WriteQuarterRate32] in {
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	742
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	743	defm V_SIN_F32 : VOP1Inst <vop1<0x35, 0x29>, "v_sin_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	744	VOP_F32_F32, AMDGPUsin
Matt Arsenault	ad14ce8	2014-07-19 18:44:39 +0000	[diff] [blame]	745	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	746	defm V_COS_F32 : VOP1Inst <vop1<0x36, 0x2a>, "v_cos_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	747	VOP_F32_F32, AMDGPUcos
Matt Arsenault	ad14ce8	2014-07-19 18:44:39 +0000	[diff] [blame]	748	>;
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	749
				750	} // End SchedRW = [WriteQuarterRate32]
				751
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	752	defm V_NOT_B32 : VOP1Inst <vop1<0x37, 0x2b>, "v_not_b32", VOP_I32_I32>;
				753	defm V_BFREV_B32 : VOP1Inst <vop1<0x38, 0x2c>, "v_bfrev_b32", VOP_I32_I32>;
				754	defm V_FFBH_U32 : VOP1Inst <vop1<0x39, 0x2d>, "v_ffbh_u32", VOP_I32_I32>;
				755	defm V_FFBL_B32 : VOP1Inst <vop1<0x3a, 0x2e>, "v_ffbl_b32", VOP_I32_I32>;
				756	defm V_FFBH_I32 : VOP1Inst <vop1<0x3b, 0x2f>, "v_ffbh_i32", VOP_I32_I32>;
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	757	defm V_FREXP_EXP_I32_F64 : VOP1Inst <vop1<0x3c,0x30>, "v_frexp_exp_i32_f64",
Matt Arsenault	2fe4fbc	2016-03-30 22:28:52 +0000	[diff] [blame]	758	VOP_I32_F64, int_amdgcn_frexp_exp
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	759	>;
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	760
				761	let SchedRW = [WriteDoubleAdd] in {
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	762	defm V_FREXP_MANT_F64 : VOP1Inst <vop1<0x3d, 0x31>, "v_frexp_mant_f64",
Matt Arsenault	b96b573	2016-03-21 16:11:05 +0000	[diff] [blame]	763	VOP_F64_F64, int_amdgcn_frexp_mant
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	764	>;
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	765
				766	defm V_FRACT_F64 : VOP1Inst <vop1<0x3e, 0x32>, "v_fract_f64",
Matt Arsenault	7401516	2016-05-28 00:19:52 +0000	[diff] [blame]	767	VOP_F64_F64, AMDGPUfract
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	768	>;
				769	} // End SchedRW = [WriteDoubleAdd]
				770
				771
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	772	defm V_FREXP_EXP_I32_F32 : VOP1Inst <vop1<0x3f, 0x33>, "v_frexp_exp_i32_f32",
Matt Arsenault	2fe4fbc	2016-03-30 22:28:52 +0000	[diff] [blame]	773	VOP_I32_F32, int_amdgcn_frexp_exp
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	774	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	775	defm V_FREXP_MANT_F32 : VOP1Inst <vop1<0x40, 0x34>, "v_frexp_mant_f32",
Matt Arsenault	b96b573	2016-03-21 16:11:05 +0000	[diff] [blame]	776	VOP_F32_F32, int_amdgcn_frexp_mant
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	777	>;
Tom Stellard	88e0b25	2015-10-06 15:57:53 +0000	[diff] [blame]	778	let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in {
Sam Kolton	3025e7f	2016-04-26 13:33:56 +0000	[diff] [blame]	779	defm V_CLREXCP : VOP1Inst <vop1<0x41,0x35>, "v_clrexcp", VOP_NO_EXT<VOP_NONE>>;
Tom Stellard	c34c37a	2015-02-18 16:08:15 +0000	[diff] [blame]	780	}
Matt Arsenault	fc0ad42	2015-10-07 17:46:32 +0000	[diff] [blame]	781
				782	let Uses = [M0, EXEC] in {
Matt Arsenault	cb540bc	2016-07-19 00:35:03 +0000	[diff] [blame]	783	// v_movreld_b32 is a special case because the destination output
				784	// register is really a source. It isn't actually read (but may be
				785	// written), and is only to provide the base register to start
				786	// indexing from. Tablegen seems to not let you define an implicit
				787	// virtual register output for the super register being written into,
				788	// so this must have an implicit def of the register added to it.
				789	defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42, 0x36>, "v_movreld_b32", VOP_MOVRELD>;
				790	defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43, 0x37>, "v_movrels_b32", VOP_I32_VI32_NO_EXT>;
Sam Kolton	3025e7f	2016-04-26 13:33:56 +0000	[diff] [blame]	791	defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44, 0x38>, "v_movrelsd_b32", VOP_NO_EXT<VOP_I32_I32>>;
Matt Arsenault	cb540bc	2016-07-19 00:35:03 +0000	[diff] [blame]	792
Matt Arsenault	fc0ad42	2015-10-07 17:46:32 +0000	[diff] [blame]	793	} // End Uses = [M0, EXEC]
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	794
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	795	// These instruction only exist on SI and CI
				796	let SubtargetPredicate = isSICI in {
				797
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	798	let SchedRW = [WriteQuarterRate32] in {
				799
Tom Stellard	4b3e755	2015-04-23 19:33:52 +0000	[diff] [blame]	800	defm V_MOV_FED_B32 : VOP1InstSI <vop1<0x9>, "v_mov_fed_b32", VOP_I32_I32>;
Matt Arsenault	ce56a0e	2016-02-13 01:19:56 +0000	[diff] [blame]	801	defm V_LOG_CLAMP_F32 : VOP1InstSI <vop1<0x26>, "v_log_clamp_f32",
				802	VOP_F32_F32, int_amdgcn_log_clamp>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	803	defm V_RCP_CLAMP_F32 : VOP1InstSI <vop1<0x28>, "v_rcp_clamp_f32", VOP_F32_F32>;
Matt Arsenault	32fc527	2016-07-26 16:45:45 +0000	[diff] [blame]	804	defm V_RCP_LEGACY_F32 : VOP1InstSI <vop1<0x29>, "v_rcp_legacy_f32",
				805	VOP_F32_F32, AMDGPUrcp_legacy>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	806	defm V_RSQ_CLAMP_F32 : VOP1InstSI <vop1<0x2c>, "v_rsq_clamp_f32",
Matt Arsenault	79963e8	2016-02-13 01:03:00 +0000	[diff] [blame]	807	VOP_F32_F32, AMDGPUrsq_clamp
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	808	>;
				809	defm V_RSQ_LEGACY_F32 : VOP1InstSI <vop1<0x2d>, "v_rsq_legacy_f32",
				810	VOP_F32_F32, AMDGPUrsq_legacy
				811	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	812
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	813	} // End SchedRW = [WriteQuarterRate32]
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	814
				815	let SchedRW = [WriteDouble] in {
				816
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	817	defm V_RCP_CLAMP_F64 : VOP1InstSI <vop1<0x30>, "v_rcp_clamp_f64", VOP_F64_F64>;
				818	defm V_RSQ_CLAMP_F64 : VOP1InstSI <vop1<0x32>, "v_rsq_clamp_f64",
Matt Arsenault	79963e8	2016-02-13 01:03:00 +0000	[diff] [blame]	819	VOP_F64_F64, AMDGPUrsq_clamp
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	820	>;
				821
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	822	} // End SchedRW = [WriteDouble]
				823
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	824	} // End SubtargetPredicate = isSICI
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	825
				826	//===----------------------------------------------------------------------===//
				827	// VINTRP Instructions
				828	//===----------------------------------------------------------------------===//
				829
Matt Arsenault	80f766a	2015-09-10 01:23:28 +0000	[diff] [blame]	830	let Uses = [M0, EXEC] in {
Tom Stellard	2a9d947	2015-05-12 15:00:46 +0000	[diff] [blame]	831
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	832	// FIXME: Specify SchedRW for VINTRP insturctions.
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	833
				834	multiclass V_INTERP_P1_F32_m : VINTRP_m <
				835	0x00000000,
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	836	(outs VGPR_32:$dst),
Tom Stellard	2a9d947	2015-05-12 15:00:46 +0000	[diff] [blame]	837	(ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr),
				838	"v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [m0]",
				839	[(set f32:$dst, (AMDGPUinterp_p1 i32:$i, (i32 imm:$attr_chan),
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	840	(i32 imm:$attr)))]
				841	>;
				842
				843	let OtherPredicates = [has32BankLDS] in {
				844
				845	defm V_INTERP_P1_F32 : V_INTERP_P1_F32_m;
				846
				847	} // End OtherPredicates = [has32BankLDS]
				848
Tom Stellard	e1818af	2016-02-18 03:42:32 +0000	[diff] [blame]	849	let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1 in {
Tom Stellard	ec87f84	2015-05-25 16:15:54 +0000	[diff] [blame]	850
				851	defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m;
				852
Tom Stellard	e1818af	2016-02-18 03:42:32 +0000	[diff] [blame]	853	} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	854
Tom Stellard	5082816	2015-05-25 16:15:56 +0000	[diff] [blame]	855	let DisableEncoding = "$src0", Constraints = "$src0 = $dst" in {
				856
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	857	defm V_INTERP_P2_F32 : VINTRP_m <
Tom Stellard	c70cf90	2015-05-25 16:15:50 +0000	[diff] [blame]	858	0x00000001,
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	859	(outs VGPR_32:$dst),
Tom Stellard	2a9d947	2015-05-12 15:00:46 +0000	[diff] [blame]	860	(ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr),
				861	"v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [m0]",
				862	[(set f32:$dst, (AMDGPUinterp_p2 f32:$src0, i32:$j, (i32 imm:$attr_chan),
Tom Stellard	5082816	2015-05-25 16:15:56 +0000	[diff] [blame]	863	(i32 imm:$attr)))]>;
				864
				865	} // End DisableEncoding = "$src0", Constraints = "$src0 = $dst"
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	866
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	867	defm V_INTERP_MOV_F32 : VINTRP_m <
Tom Stellard	c70cf90	2015-05-25 16:15:50 +0000	[diff] [blame]	868	0x00000002,
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	869	(outs VGPR_32:$dst),
Tom Stellard	2a9d947	2015-05-12 15:00:46 +0000	[diff] [blame]	870	(ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr),
				871	"v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [m0]",
				872	[(set f32:$dst, (AMDGPUinterp_mov (i32 imm:$src0), (i32 imm:$attr_chan),
				873	(i32 imm:$attr)))]>;
				874
Matt Arsenault	80f766a	2015-09-10 01:23:28 +0000	[diff] [blame]	875	} // End Uses = [M0, EXEC]
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	876
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	877	//===----------------------------------------------------------------------===//
				878	// VOP2 Instructions
				879	//===----------------------------------------------------------------------===//
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	880
Artem Tamazov	1354877	2016-06-06 15:23:43 +0000	[diff] [blame]	881	defm V_CNDMASK_B32 : VOP2eInst <vop2<0x0, 0x0>, "v_cndmask_b32",
				882	VOP2e_I32_I32_I32_I1
				883	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	884
				885	let isCommutable = 1 in {
				886	defm V_ADD_F32 : VOP2Inst <vop2<0x3, 0x1>, "v_add_f32",
				887	VOP_F32_F32_F32, fadd
				888	>;
				889
				890	defm V_SUB_F32 : VOP2Inst <vop2<0x4, 0x2>, "v_sub_f32", VOP_F32_F32_F32, fsub>;
				891	defm V_SUBREV_F32 : VOP2Inst <vop2<0x5, 0x3>, "v_subrev_f32",
				892	VOP_F32_F32_F32, null_frag, "v_sub_f32"
				893	>;
				894	} // End isCommutable = 1
				895
				896	let isCommutable = 1 in {
				897
				898	defm V_MUL_LEGACY_F32 : VOP2Inst <vop2<0x7, 0x4>, "v_mul_legacy_f32",
Matt Arsenault	32fc527	2016-07-26 16:45:45 +0000	[diff] [blame]	899	VOP_F32_F32_F32, AMDGPUfmul_legacy
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	900	>;
				901
				902	defm V_MUL_F32 : VOP2Inst <vop2<0x8, 0x5>, "v_mul_f32",
				903	VOP_F32_F32_F32, fmul
				904	>;
				905
				906	defm V_MUL_I32_I24 : VOP2Inst <vop2<0x9, 0x6>, "v_mul_i32_i24",
				907	VOP_I32_I32_I32, AMDGPUmul_i24
				908	>;
Tom Stellard	894b988	2015-02-18 16:08:14 +0000	[diff] [blame]	909
				910	defm V_MUL_HI_I32_I24 : VOP2Inst <vop2<0xa,0x7>, "v_mul_hi_i32_i24",
Matt Arsenault	2712d4a	2016-08-27 01:32:27 +0000	[diff] [blame]	911	VOP_I32_I32_I32, AMDGPUmulhi_i24
Tom Stellard	894b988	2015-02-18 16:08:14 +0000	[diff] [blame]	912	>;
				913
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	914	defm V_MUL_U32_U24 : VOP2Inst <vop2<0xb, 0x8>, "v_mul_u32_u24",
				915	VOP_I32_I32_I32, AMDGPUmul_u24
				916	>;
Tom Stellard	894b988	2015-02-18 16:08:14 +0000	[diff] [blame]	917
				918	defm V_MUL_HI_U32_U24 : VOP2Inst <vop2<0xc,0x9>, "v_mul_hi_u32_u24",
Matt Arsenault	2712d4a	2016-08-27 01:32:27 +0000	[diff] [blame]	919	VOP_I32_I32_I32, AMDGPUmulhi_u24
Tom Stellard	894b988	2015-02-18 16:08:14 +0000	[diff] [blame]	920	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	921
				922	defm V_MIN_F32 : VOP2Inst <vop2<0xf, 0xa>, "v_min_f32", VOP_F32_F32_F32,
				923	fminnum>;
				924	defm V_MAX_F32 : VOP2Inst <vop2<0x10, 0xb>, "v_max_f32", VOP_F32_F32_F32,
				925	fmaxnum>;
Marek Olsak	24ae2cd	2015-02-03 21:53:08 +0000	[diff] [blame]	926	defm V_MIN_I32 : VOP2Inst <vop2<0x11, 0xc>, "v_min_i32", VOP_I32_I32_I32>;
				927	defm V_MAX_I32 : VOP2Inst <vop2<0x12, 0xd>, "v_max_i32", VOP_I32_I32_I32>;
				928	defm V_MIN_U32 : VOP2Inst <vop2<0x13, 0xe>, "v_min_u32", VOP_I32_I32_I32>;
				929	defm V_MAX_U32 : VOP2Inst <vop2<0x14, 0xf>, "v_max_u32", VOP_I32_I32_I32>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	930
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	931	defm V_LSHRREV_B32 : VOP2Inst <
				932	vop2<0x16, 0x10>, "v_lshrrev_b32", VOP_I32_I32_I32, null_frag,
Marek Olsak	7585a29	2015-02-03 17:38:05 +0000	[diff] [blame]	933	"v_lshr_b32"
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	934	>;
				935
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	936	defm V_ASHRREV_I32 : VOP2Inst <
				937	vop2<0x18, 0x11>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag,
Marek Olsak	7585a29	2015-02-03 17:38:05 +0000	[diff] [blame]	938	"v_ashr_i32"
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	939	>;
				940
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	941	defm V_LSHLREV_B32 : VOP2Inst <
				942	vop2<0x1a, 0x12>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag,
Marek Olsak	7585a29	2015-02-03 17:38:05 +0000	[diff] [blame]	943	"v_lshl_b32"
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	944	>;
				945
Marek Olsak	24ae2cd	2015-02-03 21:53:08 +0000	[diff] [blame]	946	defm V_AND_B32 : VOP2Inst <vop2<0x1b, 0x13>, "v_and_b32", VOP_I32_I32_I32>;
				947	defm V_OR_B32 : VOP2Inst <vop2<0x1c, 0x14>, "v_or_b32", VOP_I32_I32_I32>;
				948	defm V_XOR_B32 : VOP2Inst <vop2<0x1d, 0x15>, "v_xor_b32", VOP_I32_I32_I32>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	949
Tom Stellard	cc4c871	2016-02-16 18:14:56 +0000	[diff] [blame]	950	let Constraints = "$vdst = $src2", DisableEncoding="$src2",
Tom Stellard	db5a11f	2015-07-13 15:47:57 +0000	[diff] [blame]	951	isConvertibleToThreeAddress = 1 in {
				952	defm V_MAC_F32 : VOP2Inst <vop2<0x1f, 0x16>, "v_mac_f32", VOP_MAC>;
				953	}
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	954	} // End isCommutable = 1
				955
Nikolay Haustov	6560781	2016-03-11 09:27:25 +0000	[diff] [blame]	956	defm V_MADMK_F32 : VOP2MADK <vop2<0x20, 0x17>, "v_madmk_f32", VOP_MADMK>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	957
				958	let isCommutable = 1 in {
Nikolay Haustov	6560781	2016-03-11 09:27:25 +0000	[diff] [blame]	959	defm V_MADAK_F32 : VOP2MADK <vop2<0x21, 0x18>, "v_madak_f32", VOP_MADAK>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	960	} // End isCommutable = 1
				961
Matt Arsenault	86d336e	2015-09-08 21:15:00 +0000	[diff] [blame]	962	let isCommutable = 1 in {
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	963	// No patterns so that the scalar instructions are always selected.
				964	// The scalar versions will be replaced with vector when needed later.
				965
				966	// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in VI,
				967	// but the VI instructions behave the same as the SI versions.
				968	defm V_ADD_I32 : VOP2bInst <vop2<0x25, 0x19>, "v_add_i32",
Matt Arsenault	e4d0c14	2015-08-29 07:16:50 +0000	[diff] [blame]	969	VOP2b_I32_I1_I32_I32
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	970	>;
Matt Arsenault	e4d0c14	2015-08-29 07:16:50 +0000	[diff] [blame]	971	defm V_SUB_I32 : VOP2bInst <vop2<0x26, 0x1a>, "v_sub_i32", VOP2b_I32_I1_I32_I32>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	972
				973	defm V_SUBREV_I32 : VOP2bInst <vop2<0x27, 0x1b>, "v_subrev_i32",
Matt Arsenault	e4d0c14	2015-08-29 07:16:50 +0000	[diff] [blame]	974	VOP2b_I32_I1_I32_I32, null_frag, "v_sub_i32"
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	975	>;
				976
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	977	defm V_ADDC_U32 : VOP2bInst <vop2<0x28, 0x1c>, "v_addc_u32",
Matt Arsenault	86d336e	2015-09-08 21:15:00 +0000	[diff] [blame]	978	VOP2b_I32_I1_I32_I32_I1
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	979	>;
				980	defm V_SUBB_U32 : VOP2bInst <vop2<0x29, 0x1d>, "v_subb_u32",
Matt Arsenault	86d336e	2015-09-08 21:15:00 +0000	[diff] [blame]	981	VOP2b_I32_I1_I32_I32_I1
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	982	>;
				983	defm V_SUBBREV_U32 : VOP2bInst <vop2<0x2a, 0x1e>, "v_subbrev_u32",
Matt Arsenault	86d336e	2015-09-08 21:15:00 +0000	[diff] [blame]	984	VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32"
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	985	>;
				986
Matt Arsenault	86d336e	2015-09-08 21:15:00 +0000	[diff] [blame]	987	} // End isCommutable = 1
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	988
Matt Arsenault	529cf25	2016-06-23 01:26:16 +0000	[diff] [blame]	989	// These are special and do not read the exec mask.
				990	let isConvergent = 1, Uses = []<Register> in {
Matt Arsenault	4234542	2016-05-11 00:32:31 +0000	[diff] [blame]	991
Marek Olsak	15e4a59	2015-01-15 18:42:55 +0000	[diff] [blame]	992	defm V_READLANE_B32 : VOP2SI_3VI_m <
				993	vop3 <0x001, 0x289>,
				994	"v_readlane_b32",
Tom Stellard	c149dc0	2013-11-27 21:23:35 +0000	[diff] [blame]	995	(outs SReg_32:$vdst),
Changpeng Fang	75f0968	2016-08-24 20:35:23 +0000	[diff] [blame]	996	(ins VGPR_32:$src0, SCSrc_32:$src1),
				997	"v_readlane_b32 $vdst, $src0, $src1",
				998	[(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))]
Tom Stellard	c149dc0	2013-11-27 21:23:35 +0000	[diff] [blame]	999	>;
				1000
Marek Olsak	15e4a59	2015-01-15 18:42:55 +0000	[diff] [blame]	1001	defm V_WRITELANE_B32 : VOP2SI_3VI_m <
				1002	vop3 <0x002, 0x28a>,
				1003	"v_writelane_b32",
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	1004	(outs VGPR_32:$vdst),
Marek Olsak	9b8f32e	2015-02-18 22:12:45 +0000	[diff] [blame]	1005	(ins SReg_32:$src0, SCSrc_32:$src1),
				1006	"v_writelane_b32 $vdst, $src0, $src1"
Tom Stellard	c149dc0	2013-11-27 21:23:35 +0000	[diff] [blame]	1007	>;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1008
Matt Arsenault	4234542	2016-05-11 00:32:31 +0000	[diff] [blame]	1009	} // End isConvergent = 1
				1010
Marek Olsak	15e4a59	2015-01-15 18:42:55 +0000	[diff] [blame]	1011	// These instructions only exist on SI and CI
				1012	let SubtargetPredicate = isSICI in {
				1013
Tom Stellard	85656ca	2015-08-07 15:34:30 +0000	[diff] [blame]	1014	let isCommutable = 1 in {
				1015	defm V_MAC_LEGACY_F32 : VOP2InstSI <vop2<0x6>, "v_mac_legacy_f32",
				1016	VOP_F32_F32_F32
				1017	>;
				1018	} // End isCommutable = 1
				1019
Marek Olsak	191507e	2015-02-03 17:38:12 +0000	[diff] [blame]	1020	defm V_MIN_LEGACY_F32 : VOP2InstSI <vop2<0xd>, "v_min_legacy_f32",
Matt Arsenault	da59f3d	2014-11-13 23:03:09 +0000	[diff] [blame]	1021	VOP_F32_F32_F32, AMDGPUfmin_legacy
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1022	>;
Marek Olsak	191507e	2015-02-03 17:38:12 +0000	[diff] [blame]	1023	defm V_MAX_LEGACY_F32 : VOP2InstSI <vop2<0xe>, "v_max_legacy_f32",
Matt Arsenault	da59f3d	2014-11-13 23:03:09 +0000	[diff] [blame]	1024	VOP_F32_F32_F32, AMDGPUfmax_legacy
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1025	>;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	1026
Matt Arsenault	1e3a4eb	2014-12-12 02:30:37 +0000	[diff] [blame]	1027	let isCommutable = 1 in {
Marek Olsak	24ae2cd	2015-02-03 21:53:08 +0000	[diff] [blame]	1028	defm V_LSHR_B32 : VOP2InstSI <vop2<0x15>, "v_lshr_b32", VOP_I32_I32_I32>;
				1029	defm V_ASHR_I32 : VOP2InstSI <vop2<0x17>, "v_ashr_i32", VOP_I32_I32_I32>;
				1030	defm V_LSHL_B32 : VOP2InstSI <vop2<0x19>, "v_lshl_b32", VOP_I32_I32_I32>;
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	1031	} // End isCommutable = 1
Marek Olsak	f0b130a	2015-01-15 18:43:06 +0000	[diff] [blame]	1032	} // End let SubtargetPredicate = SICI
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	1033
Marek Olsak	63a7b08	2015-03-24 13:40:21 +0000	[diff] [blame]	1034	defm V_BFM_B32 : VOP2_VI3_Inst <vop23<0x1e, 0x293>, "v_bfm_b32",
				1035	VOP_I32_I32_I32
Marek Olsak	f0b130a	2015-01-15 18:43:06 +0000	[diff] [blame]	1036	>;
				1037	defm V_BCNT_U32_B32 : VOP2_VI3_Inst <vop23<0x22, 0x28b>, "v_bcnt_u32_b32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1038	VOP_I32_I32_I32
				1039	>;
Marek Olsak	f0b130a	2015-01-15 18:43:06 +0000	[diff] [blame]	1040	defm V_MBCNT_LO_U32_B32 : VOP2_VI3_Inst <vop23<0x23, 0x28c>, "v_mbcnt_lo_u32_b32",
Tom Stellard	43f52df	2015-12-15 17:02:52 +0000	[diff] [blame]	1041	VOP_I32_I32_I32, int_amdgcn_mbcnt_lo
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1042	>;
Marek Olsak	f0b130a	2015-01-15 18:43:06 +0000	[diff] [blame]	1043	defm V_MBCNT_HI_U32_B32 : VOP2_VI3_Inst <vop23<0x24, 0x28d>, "v_mbcnt_hi_u32_b32",
Tom Stellard	43f52df	2015-12-15 17:02:52 +0000	[diff] [blame]	1044	VOP_I32_I32_I32, int_amdgcn_mbcnt_hi
Marek Olsak	f0b130a	2015-01-15 18:43:06 +0000	[diff] [blame]	1045	>;
				1046	defm V_LDEXP_F32 : VOP2_VI3_Inst <vop23<0x2b, 0x288>, "v_ldexp_f32",
Matt Arsenault	2e7cc48	2014-08-15 17:30:25 +0000	[diff] [blame]	1047	VOP_F32_F32_I32, AMDGPUldexp
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1048	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1049
Marek Olsak	11057ee	2015-02-03 17:38:01 +0000	[diff] [blame]	1050	defm V_CVT_PKACCUM_U8_F32 : VOP2_VI3_Inst <vop23<0x2c, 0x1f0>, "v_cvt_pkaccum_u8_f32",
				1051	VOP_I32_F32_I32>; // TODO: set "Uses = dst"
				1052
				1053	defm V_CVT_PKNORM_I16_F32 : VOP2_VI3_Inst <vop23<0x2d, 0x294>, "v_cvt_pknorm_i16_f32",
				1054	VOP_I32_F32_F32
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1055	>;
Marek Olsak	11057ee	2015-02-03 17:38:01 +0000	[diff] [blame]	1056	defm V_CVT_PKNORM_U16_F32 : VOP2_VI3_Inst <vop23<0x2e, 0x295>, "v_cvt_pknorm_u16_f32",
				1057	VOP_I32_F32_F32
				1058	>;
				1059	defm V_CVT_PKRTZ_F16_F32 : VOP2_VI3_Inst <vop23<0x2f, 0x296>, "v_cvt_pkrtz_f16_f32",
				1060	VOP_I32_F32_F32, int_SI_packf16
				1061	>;
				1062	defm V_CVT_PK_U16_U32 : VOP2_VI3_Inst <vop23<0x30, 0x297>, "v_cvt_pk_u16_u32",
				1063	VOP_I32_I32_I32
				1064	>;
				1065	defm V_CVT_PK_I16_I32 : VOP2_VI3_Inst <vop23<0x31, 0x298>, "v_cvt_pk_i16_i32",
				1066	VOP_I32_I32_I32
				1067	>;
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	1068
				1069	//===----------------------------------------------------------------------===//
				1070	// VOP3 Instructions
				1071	//===----------------------------------------------------------------------===//
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1072
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	1073	let isCommutable = 1 in {
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1074	defm V_MAD_LEGACY_F32 : VOP3Inst <vop3<0x140, 0x1c0>, "v_mad_legacy_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1075	VOP_F32_F32_F32_F32
Matt Arsenault	f37abc7	2014-05-22 17:45:20 +0000	[diff] [blame]	1076	>;
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	1077
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1078	defm V_MAD_F32 : VOP3Inst <vop3<0x141, 0x1c1>, "v_mad_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1079	VOP_F32_F32_F32_F32, fmad
Tom Stellard	5263948	2013-07-23 01:48:49 +0000	[diff] [blame]	1080	>;
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	1081
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1082	defm V_MAD_I32_I24 : VOP3Inst <vop3<0x142, 0x1c2>, "v_mad_i32_i24",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1083	VOP_I32_I32_I32_I32, AMDGPUmad_i24
				1084	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1085	defm V_MAD_U32_U24 : VOP3Inst <vop3<0x143, 0x1c3>, "v_mad_u32_u24",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1086	VOP_I32_I32_I32_I32, AMDGPUmad_u24
Tom Stellard	5263948	2013-07-23 01:48:49 +0000	[diff] [blame]	1087	>;
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	1088	} // End isCommutable = 1
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1089
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1090	defm V_CUBEID_F32 : VOP3Inst <vop3<0x144, 0x1c4>, "v_cubeid_f32",
Matt Arsenault	051d6f9	2016-01-26 04:29:56 +0000	[diff] [blame]	1091	VOP_F32_F32_F32_F32, int_amdgcn_cubeid
Niels Ole Salscheider	6509ac6	2013-08-10 10:38:47 +0000	[diff] [blame]	1092	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1093	defm V_CUBESC_F32 : VOP3Inst <vop3<0x145, 0x1c5>, "v_cubesc_f32",
Matt Arsenault	051d6f9	2016-01-26 04:29:56 +0000	[diff] [blame]	1094	VOP_F32_F32_F32_F32, int_amdgcn_cubesc
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1095	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1096	defm V_CUBETC_F32 : VOP3Inst <vop3<0x146, 0x1c6>, "v_cubetc_f32",
Matt Arsenault	051d6f9	2016-01-26 04:29:56 +0000	[diff] [blame]	1097	VOP_F32_F32_F32_F32, int_amdgcn_cubetc
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1098	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1099	defm V_CUBEMA_F32 : VOP3Inst <vop3<0x147, 0x1c7>, "v_cubema_f32",
Matt Arsenault	051d6f9	2016-01-26 04:29:56 +0000	[diff] [blame]	1100	VOP_F32_F32_F32_F32, int_amdgcn_cubema
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1101	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1102
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1103	defm V_BFE_U32 : VOP3Inst <vop3<0x148, 0x1c8>, "v_bfe_u32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1104	VOP_I32_I32_I32_I32, AMDGPUbfe_u32
				1105	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1106	defm V_BFE_I32 : VOP3Inst <vop3<0x149, 0x1c9>, "v_bfe_i32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1107	VOP_I32_I32_I32_I32, AMDGPUbfe_i32
				1108	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1109
				1110	defm V_BFI_B32 : VOP3Inst <vop3<0x14a, 0x1ca>, "v_bfi_b32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1111	VOP_I32_I32_I32_I32, AMDGPUbfi
				1112	>;
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	1113
				1114	let isCommutable = 1 in {
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1115	defm V_FMA_F32 : VOP3Inst <vop3<0x14b, 0x1cb>, "v_fma_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1116	VOP_F32_F32_F32_F32, fma
				1117	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1118	defm V_FMA_F64 : VOP3Inst <vop3<0x14c, 0x1cc>, "v_fma_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1119	VOP_F64_F64_F64_F64, fma
Niels Ole Salscheider	6509ac6	2013-08-10 10:38:47 +0000	[diff] [blame]	1120	>;
Wei Ding	5b2636a	2016-07-12 18:02:14 +0000	[diff] [blame]	1121
				1122	defm V_LERP_U8 : VOP3Inst <vop3<0x14d, 0x1cd>, "v_lerp_u8",
				1123	VOP_I32_I32_I32_I32, int_amdgcn_lerp
				1124	>;
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	1125	} // End isCommutable = 1
				1126
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	1127	//def V_LERP_U8 : VOP3_U8 <0x0000014d, "v_lerp_u8", []>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1128	defm V_ALIGNBIT_B32 : VOP3Inst <vop3<0x14e, 0x1ce>, "v_alignbit_b32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1129	VOP_I32_I32_I32_I32
				1130	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1131	defm V_ALIGNBYTE_B32 : VOP3Inst <vop3<0x14f, 0x1cf>, "v_alignbyte_b32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1132	VOP_I32_I32_I32_I32
				1133	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1134
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	1135	defm V_MIN3_F32 : VOP3Inst <vop3<0x151, 0x1d0>, "v_min3_f32",
Matt Arsenault	cc3c2b3	2014-11-14 20:08:52 +0000	[diff] [blame]	1136	VOP_F32_F32_F32_F32, AMDGPUfmin3>;
				1137
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	1138	defm V_MIN3_I32 : VOP3Inst <vop3<0x152, 0x1d1>, "v_min3_i32",
Matt Arsenault	cc3c2b3	2014-11-14 20:08:52 +0000	[diff] [blame]	1139	VOP_I32_I32_I32_I32, AMDGPUsmin3
				1140	>;
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	1141	defm V_MIN3_U32 : VOP3Inst <vop3<0x153, 0x1d2>, "v_min3_u32",
Matt Arsenault	cc3c2b3	2014-11-14 20:08:52 +0000	[diff] [blame]	1142	VOP_I32_I32_I32_I32, AMDGPUumin3
				1143	>;
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	1144	defm V_MAX3_F32 : VOP3Inst <vop3<0x154, 0x1d3>, "v_max3_f32",
Matt Arsenault	cc3c2b3	2014-11-14 20:08:52 +0000	[diff] [blame]	1145	VOP_F32_F32_F32_F32, AMDGPUfmax3
				1146	>;
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	1147	defm V_MAX3_I32 : VOP3Inst <vop3<0x155, 0x1d4>, "v_max3_i32",
Matt Arsenault	cc3c2b3	2014-11-14 20:08:52 +0000	[diff] [blame]	1148	VOP_I32_I32_I32_I32, AMDGPUsmax3
				1149	>;
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	1150	defm V_MAX3_U32 : VOP3Inst <vop3<0x156, 0x1d5>, "v_max3_u32",
Matt Arsenault	cc3c2b3	2014-11-14 20:08:52 +0000	[diff] [blame]	1151	VOP_I32_I32_I32_I32, AMDGPUumax3
				1152	>;
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	1153	defm V_MED3_F32 : VOP3Inst <vop3<0x157, 0x1d6>, "v_med3_f32",
Matt Arsenault	f639c32	2016-01-28 20:53:42 +0000	[diff] [blame]	1154	VOP_F32_F32_F32_F32, AMDGPUfmed3
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	1155	>;
				1156	defm V_MED3_I32 : VOP3Inst <vop3<0x158, 0x1d7>, "v_med3_i32",
Matt Arsenault	f639c32	2016-01-28 20:53:42 +0000	[diff] [blame]	1157	VOP_I32_I32_I32_I32, AMDGPUsmed3
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	1158	>;
				1159	defm V_MED3_U32 : VOP3Inst <vop3<0x159, 0x1d8>, "v_med3_u32",
Matt Arsenault	f639c32	2016-01-28 20:53:42 +0000	[diff] [blame]	1160	VOP_I32_I32_I32_I32, AMDGPUumed3
Marek Olsak	794ff83	2015-01-27 17:25:15 +0000	[diff] [blame]	1161	>;
				1162
Wei Ding	34e1753	2016-08-11 16:33:53 +0000	[diff] [blame]	1163	defm V_SAD_U8 : VOP3Inst <vop3 <0x15a, 0x1d9>, "v_sad_u8",
				1164	VOP_I32_I32_I32_I32, int_amdgcn_sad_u8>;
				1165
				1166	defm V_SAD_HI_U8 : VOP3Inst <vop3 <0x15b, 0x1da>, "v_sad_hi_u8",
				1167	VOP_I32_I32_I32_I32, int_amdgcn_sad_hi_u8>;
				1168
				1169	defm V_SAD_U16 : VOP3Inst <vop3<0x15c, 0x1db>, "v_sad_u16",
				1170	VOP_I32_I32_I32_I32, int_amdgcn_sad_u16>;
				1171
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1172	defm V_SAD_U32 : VOP3Inst <vop3<0x15d, 0x1dc>, "v_sad_u32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1173	VOP_I32_I32_I32_I32
				1174	>;
Wei Ding	70cda07	2016-08-11 20:34:48 +0000	[diff] [blame]	1175
				1176	defm V_CVT_PK_U8_F32 : VOP3Inst<vop3<0x15e, 0x1dd>, "v_cvt_pk_u8_f32",
				1177	VOP_I32_F32_I32_I32, int_amdgcn_cvt_pk_u8_f32
				1178	>;
				1179
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1180	//def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "v_cvt_pk_u8_f32", []>;
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1181	defm V_DIV_FIXUP_F32 : VOP3Inst <
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1182	vop3<0x15f, 0x1de>, "v_div_fixup_f32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	1183	>;
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	1184
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	1185	let SchedRW = [WriteDoubleAdd] in {
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	1186
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1187	defm V_DIV_FIXUP_F64 : VOP3Inst <
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1188	vop3<0x160, 0x1df>, "v_div_fixup_f64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	1189	>;
Tom Stellard	1cfd7a5	2013-05-20 15:02:12 +0000	[diff] [blame]	1190
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	1191	} // End SchedRW = [WriteDouble]
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	1192
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	1193	let SchedRW = [WriteDoubleAdd] in {
Tom Stellard	7512c08	2013-07-12 18:14:56 +0000	[diff] [blame]	1194	let isCommutable = 1 in {
				1195
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1196	defm V_ADD_F64 : VOP3Inst <vop3<0x164, 0x280>, "v_add_f64",
Tom Stellard	a90b952	2016-02-11 03:28:15 +0000	[diff] [blame]	1197	VOP_F64_F64_F64, fadd, 1
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1198	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1199	defm V_MUL_F64 : VOP3Inst <vop3<0x165, 0x281>, "v_mul_f64",
Tom Stellard	a90b952	2016-02-11 03:28:15 +0000	[diff] [blame]	1200	VOP_F64_F64_F64, fmul, 1
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1201	>;
Matt Arsenault	7c93690	2014-10-21 23:01:01 +0000	[diff] [blame]	1202
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1203	defm V_MIN_F64 : VOP3Inst <vop3<0x166, 0x282>, "v_min_f64",
Tom Stellard	a90b952	2016-02-11 03:28:15 +0000	[diff] [blame]	1204	VOP_F64_F64_F64, fminnum, 1
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1205	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1206	defm V_MAX_F64 : VOP3Inst <vop3<0x167, 0x283>, "v_max_f64",
Tom Stellard	a90b952	2016-02-11 03:28:15 +0000	[diff] [blame]	1207	VOP_F64_F64_F64, fmaxnum, 1
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1208	>;
Tom Stellard	7512c08	2013-07-12 18:14:56 +0000	[diff] [blame]	1209
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1210	} // End isCommutable = 1
Tom Stellard	7512c08	2013-07-12 18:14:56 +0000	[diff] [blame]	1211
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1212	defm V_LDEXP_F64 : VOP3Inst <vop3<0x168, 0x284>, "v_ldexp_f64",
Tom Stellard	a90b952	2016-02-11 03:28:15 +0000	[diff] [blame]	1213	VOP_F64_F64_I32, AMDGPUldexp, 1
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1214	>;
Christian Konig	70a5032	2013-03-27 09:12:51 +0000	[diff] [blame]	1215
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1216	} // End let SchedRW = [WriteDoubleAdd]
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	1217
				1218	let isCommutable = 1, SchedRW = [WriteQuarterRate32] in {
Christian Konig	70a5032	2013-03-27 09:12:51 +0000	[diff] [blame]	1219
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1220	defm V_MUL_LO_U32 : VOP3Inst <vop3<0x169, 0x285>, "v_mul_lo_u32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1221	VOP_I32_I32_I32
				1222	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1223	defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a, 0x286>, "v_mul_hi_u32",
Matt Arsenault	8d90302	2016-01-22 18:42:49 +0000	[diff] [blame]	1224	VOP_I32_I32_I32, mulhu
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1225	>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1226
Tom Stellard	e1818af	2016-02-18 03:42:32 +0000	[diff] [blame]	1227	let DisableVIDecoder=1 in { // removed from VI as identical to V_MUL_LO_U32
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1228	defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b, 0x285>, "v_mul_lo_i32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1229	VOP_I32_I32_I32
				1230	>;
Tom Stellard	e1818af	2016-02-18 03:42:32 +0000	[diff] [blame]	1231	}
				1232
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1233	defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32",
Matt Arsenault	8d90302	2016-01-22 18:42:49 +0000	[diff] [blame]	1234	VOP_I32_I32_I32, mulhs
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1235	>;
Christian Konig	70a5032	2013-03-27 09:12:51 +0000	[diff] [blame]	1236
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1237	} // End isCommutable = 1, SchedRW = [WriteQuarterRate32]
Christian Konig	70a5032	2013-03-27 09:12:51 +0000	[diff] [blame]	1238
Matt Arsenault	6e26b8d	2015-02-14 04:03:18 +0000	[diff] [blame]	1239	let SchedRW = [WriteFloatFMA, WriteSALU] in {
Matt Arsenault	e98a074	2015-09-26 02:25:48 +0000	[diff] [blame]	1240	defm V_DIV_SCALE_F32 : VOP3bInst <vop3<0x16d, 0x1e0>, "v_div_scale_f32",
Tom Stellard	e993451	2016-02-11 18:25:26 +0000	[diff] [blame]	1241	VOP3b_F32_I1_F32_F32_F32, [], 1
Matt Arsenault	e98a074	2015-09-26 02:25:48 +0000	[diff] [blame]	1242	>;
Matt Arsenault	6e26b8d	2015-02-14 04:03:18 +0000	[diff] [blame]	1243	}
Matt Arsenault	f2b0aeb	2014-06-23 18:28:28 +0000	[diff] [blame]	1244
Matt Arsenault	6e26b8d	2015-02-14 04:03:18 +0000	[diff] [blame]	1245	let SchedRW = [WriteDouble, WriteSALU] in {
Matt Arsenault	f2b0aeb	2014-06-23 18:28:28 +0000	[diff] [blame]	1246	// Double precision division pre-scale.
Matt Arsenault	e98a074	2015-09-26 02:25:48 +0000	[diff] [blame]	1247	defm V_DIV_SCALE_F64 : VOP3bInst <vop3<0x16e, 0x1e1>, "v_div_scale_f64",
Tom Stellard	e993451	2016-02-11 18:25:26 +0000	[diff] [blame]	1248	VOP3b_F64_I1_F64_F64_F64, [], 1
Matt Arsenault	e98a074	2015-09-26 02:25:48 +0000	[diff] [blame]	1249	>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1250	} // End SchedRW = [WriteDouble]
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	1251
Matt Arsenault	80f766a	2015-09-10 01:23:28 +0000	[diff] [blame]	1252	let isCommutable = 1, Uses = [VCC, EXEC] in {
Matt Arsenault	1bc9d95	2015-02-14 04:22:00 +0000	[diff] [blame]	1253
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	1254	let SchedRW = [WriteFloatFMA] in {
Matt Arsenault	1bc9d95	2015-02-14 04:22:00 +0000	[diff] [blame]	1255	// v_div_fmas_f32:
				1256	// result = src0 * src1 + src2
				1257	// if (vcc)
				1258	// result *= 2^32
				1259	//
				1260	defm V_DIV_FMAS_F32 : VOP3_VCC_Inst <vop3<0x16f, 0x1e2>, "v_div_fmas_f32",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1261	VOP_F32_F32_F32_F32, AMDGPUdiv_fmas
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	1262	>;
Matt Arsenault	e8df879	2015-08-22 00:50:41 +0000	[diff] [blame]	1263	}
Matt Arsenault	1bc9d95	2015-02-14 04:22:00 +0000	[diff] [blame]	1264
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	1265	let SchedRW = [WriteDouble] in {
Matt Arsenault	1bc9d95	2015-02-14 04:22:00 +0000	[diff] [blame]	1266	// v_div_fmas_f64:
				1267	// result = src0 * src1 + src2
				1268	// if (vcc)
				1269	// result *= 2^64
				1270	//
				1271	defm V_DIV_FMAS_F64 : VOP3_VCC_Inst <vop3<0x170, 0x1e3>, "v_div_fmas_f64",
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1272	VOP_F64_F64_F64_F64, AMDGPUdiv_fmas
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	1273	>;
Matt Arsenault	1bc9d95	2015-02-14 04:22:00 +0000	[diff] [blame]	1274
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	1275	} // End SchedRW = [WriteDouble]
Matt Arsenault	80f766a	2015-09-10 01:23:28 +0000	[diff] [blame]	1276	} // End isCommutable = 1, Uses = [VCC, EXEC]
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	1277
Wei Ding	34e1753	2016-08-11 16:33:53 +0000	[diff] [blame]	1278	defm V_MSAD_U8 : VOP3Inst <vop3<0x171, 0x1e4>, "v_msad_u8",
				1279	VOP_I32_I32_I32_I32, int_amdgcn_msad_u8>;
				1280
				1281	defm V_MQSAD_PK_U16_U8 : VOP3Inst <vop3<0x173, 0x1e6>, "v_mqsad_pk_u16_u8",
Wei Ding	52bb661	2016-08-18 19:51:14 +0000	[diff] [blame]	1282	VOP_I64_I64_I32_I64, int_amdgcn_mqsad_pk_u16_u8>;
Wei Ding	34e1753	2016-08-11 16:33:53 +0000	[diff] [blame]	1283
Tom Stellard	326d6ec	2014-11-05 14:50:53 +0000	[diff] [blame]	1284	//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "v_mqsad_u8", []>;
Matt Arsenault	95e4866	2014-11-13 19:26:47 +0000	[diff] [blame]	1285
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	1286	let SchedRW = [WriteDouble] in {
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	1287	defm V_TRIG_PREOP_F64 : VOP3Inst <
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1288	vop3<0x174, 0x292>, "v_trig_preop_f64", VOP_F64_F64_I32, AMDGPUtrig_preop
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	1289	>;
Matt Arsenault	e27a41b	2013-11-18 20:09:32 +0000	[diff] [blame]	1290
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1291	} // End SchedRW = [WriteDouble]
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	1292
Marek Olsak	eae20ab	2015-01-15 18:42:40 +0000	[diff] [blame]	1293	// These instructions only exist on SI and CI
				1294	let SubtargetPredicate = isSICI in {
				1295
Marek Olsak	24ae2cd	2015-02-03 21:53:08 +0000	[diff] [blame]	1296	defm V_LSHL_B64 : VOP3Inst <vop3<0x161>, "v_lshl_b64", VOP_I64_I64_I32>;
				1297	defm V_LSHR_B64 : VOP3Inst <vop3<0x162>, "v_lshr_b64", VOP_I64_I64_I32>;
				1298	defm V_ASHR_I64 : VOP3Inst <vop3<0x163>, "v_ashr_i64", VOP_I64_I64_I32>;
Marek Olsak	eae20ab	2015-01-15 18:42:40 +0000	[diff] [blame]	1299
				1300	defm V_MULLIT_F32 : VOP3Inst <vop3<0x150>, "v_mullit_f32",
				1301	VOP_F32_F32_F32_F32>;
				1302
				1303	} // End SubtargetPredicate = isSICI
				1304
Tom Stellard	e1818af	2016-02-18 03:42:32 +0000	[diff] [blame]	1305	let SubtargetPredicate = isVI, DisableSIDecoder = 1 in {
Marek Olsak	707a6d0	2015-02-03 21:53:01 +0000	[diff] [blame]	1306
				1307	defm V_LSHLREV_B64 : VOP3Inst <vop3<0, 0x28f>, "v_lshlrev_b64",
				1308	VOP_I64_I32_I64
				1309	>;
				1310	defm V_LSHRREV_B64 : VOP3Inst <vop3<0, 0x290>, "v_lshrrev_b64",
				1311	VOP_I64_I32_I64
				1312	>;
				1313	defm V_ASHRREV_I64 : VOP3Inst <vop3<0, 0x291>, "v_ashrrev_i64",
				1314	VOP_I64_I32_I64
				1315	>;
				1316
				1317	} // End SubtargetPredicate = isVI
				1318
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	1319	//===----------------------------------------------------------------------===//
				1320	// Pseudo Instructions
				1321	//===----------------------------------------------------------------------===//
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1322
				1323	let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in {
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1324
Marek Olsak	7d77728	2015-03-24 13:40:15 +0000	[diff] [blame]	1325	// For use in patterns
Tom Stellard	cc4c871	2016-02-16 18:14:56 +0000	[diff] [blame]	1326	def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$vdst),
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1327	(ins VSrc_64:$src0, VSrc_64:$src1, SSrc_64:$src2), "", []> {
				1328	let isPseudo = 1;
				1329	let isCodeGenOnly = 1;
Matt Arsenault	22e4179	2016-08-27 01:00:37 +0000	[diff] [blame]	1330	let usesCustomInserter = 1;
Tom Stellard	60024a0	2014-09-24 01:33:24 +0000	[diff] [blame]	1331	}
				1332
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1333	// 64-bit vector move instruction. This is mainly used by the SIFoldOperands
				1334	// pass to enable folding of inline immediates.
				1335	def V_MOV_B64_PSEUDO : PseudoInstSI <(outs VReg_64:$vdst), (ins VSrc_64:$src0)> {
				1336	let VALU = 1;
				1337	}
				1338	} // End let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC]
				1339
Changpeng Fang	01f6062	2016-03-15 17:28:44 +0000	[diff] [blame]	1340	let usesCustomInserter = 1, SALU = 1 in {
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1341	def GET_GROUPSTATICSIZE : PseudoInstSI <(outs SReg_32:$sdst), (ins),
Changpeng Fang	01f6062	2016-03-15 17:28:44 +0000	[diff] [blame]	1342	[(set SReg_32:$sdst, (int_amdgcn_groupstaticsize))]>;
				1343	} // End let usesCustomInserter = 1, SALU = 1
				1344
Matt Arsenault	8fb3738	2013-10-11 21:03:36 +0000	[diff] [blame]	1345	// SI pseudo instructions. These are used by the CFG structurizer pass
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1346	// and should be lowered to ISA instructions prior to codegen.
				1347
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1348	let hasSideEffects = 1 in {
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1349
				1350	// Dummy terminator instruction to use after control flow instructions
				1351	// replaced with exec mask operations.
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1352	def SI_MASK_BRANCH : PseudoInstSI <
Matt Arsenault	f98a596	2016-08-27 00:42:21 +0000	[diff] [blame]	1353	(outs), (ins brtarget:$target)> {
Matt Arsenault	57431c9	2016-08-10 19:11:42 +0000	[diff] [blame]	1354	let isBranch = 0;
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1355	let isTerminator = 1;
Matt Arsenault	57431c9	2016-08-10 19:11:42 +0000	[diff] [blame]	1356	let isBarrier = 0;
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1357	let SALU = 1;
Matt Arsenault	78fc9da	2016-08-22 19:33:16 +0000	[diff] [blame]	1358	let Uses = [EXEC];
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1359	}
				1360
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1361	let isTerminator = 1 in {
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1362
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1363	def SI_IF: CFPseudoInstSI <
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1364	(outs SReg_64:$dst), (ins SReg_64:$vcc, brtarget:$target),
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1365	[(set i64:$dst, (int_amdgcn_if i1:$vcc, bb:$target))], 1, 1> {
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1366	let Constraints = "";
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1367	let Size = 8;
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1368	}
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1369
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1370	def SI_ELSE : CFPseudoInstSI <
				1371	(outs SReg_64:$dst), (ins SReg_64:$src, brtarget:$target, i1imm:$execfix), [], 1, 1> {
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1372	let Constraints = "$src = $dst";
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1373	let Size = 12;
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1374	}
				1375
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1376	def SI_LOOP : CFPseudoInstSI <
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1377	(outs), (ins SReg_64:$saved, brtarget:$target),
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1378	[(int_amdgcn_loop i64:$saved, bb:$target)], 1, 1> {
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1379	let Size = 8;
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1380	let isBranch = 1;
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1381	}
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1382
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1383	} // End isBranch = 1, isTerminator = 1
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1384
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1385	def SI_END_CF : CFPseudoInstSI <
				1386	(outs), (ins SReg_64:$saved),
				1387	[(int_amdgcn_end_cf i64:$saved)], 1, 1> {
				1388	let Size = 4;
				1389	}
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1390
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1391	def SI_BREAK : CFPseudoInstSI <
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1392	(outs SReg_64:$dst), (ins SReg_64:$src),
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1393	[(set i64:$dst, (int_amdgcn_break i64:$src))], 1> {
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1394	let Size = 4;
				1395	}
Matt Arsenault	48d70cb	2016-07-09 17:18:39 +0000	[diff] [blame]	1396
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1397	def SI_IF_BREAK : CFPseudoInstSI <
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1398	(outs SReg_64:$dst), (ins SReg_64:$vcc, SReg_64:$src),
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1399	[(set i64:$dst, (int_amdgcn_if_break i1:$vcc, i64:$src))]> {
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1400	let Size = 4;
				1401	}
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1402
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1403	def SI_ELSE_BREAK : CFPseudoInstSI <
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1404	(outs SReg_64:$dst), (ins SReg_64:$src0, SReg_64:$src1),
Matt Arsenault	c6b1350	2016-08-10 19:11:51 +0000	[diff] [blame]	1405	[(set i64:$dst, (int_amdgcn_else_break i64:$src0, i64:$src1))]> {
				1406	let Size = 4;
				1407	}
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1408
Tom Stellard	aa79834	2015-05-01 03:44:09 +0000	[diff] [blame]	1409	let Uses = [EXEC], Defs = [EXEC,VCC] in {
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1410	def SI_KILL : PseudoInstSI <
				1411	(outs), (ins VSrc_32:$src),
Matt Arsenault	03006fd	2016-07-19 16:27:56 +0000	[diff] [blame]	1412	[(AMDGPUkill i32:$src)]> {
Matt Arsenault	786724a	2016-07-12 21:41:32 +0000	[diff] [blame]	1413	let isConvergent = 1;
				1414	let usesCustomInserter = 1;
				1415	}
				1416
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1417	def SI_KILL_TERMINATOR : SPseudoInstSI <
Matt Arsenault	786724a	2016-07-12 21:41:32 +0000	[diff] [blame]	1418	(outs), (ins VSrc_32:$src)> {
				1419	let isTerminator = 1;
				1420	}
				1421
Tom Stellard	aa79834	2015-05-01 03:44:09 +0000	[diff] [blame]	1422	} // End Uses = [EXEC], Defs = [EXEC,VCC]
Tom Stellard	be8ebee	2013-01-18 21:15:50 +0000	[diff] [blame]	1423
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1424	} // End mayLoad = 1, mayStore = 1, hasSideEffects = 1
Tom Stellard	f879435	2012-12-19 22:10:31 +0000	[diff] [blame]	1425
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1426	def SI_PS_LIVE : PseudoInstSI <
				1427	(outs SReg_64:$dst), (ins),
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1428	[(set i1:$dst, (int_amdgcn_ps_live))]> {
				1429	let SALU = 1;
				1430	}
Nicolai Haehnle	b0c9748	2016-04-22 04:04:08 +0000	[diff] [blame]	1431
Matt Arsenault	4ac341c	2016-04-14 21:58:15 +0000	[diff] [blame]	1432	// Used as an isel pseudo to directly emit initialization with an
				1433	// s_mov_b32 rather than a copy of another initialized
				1434	// register. MachineCSE skips copies, and we don't want to have to
				1435	// fold operands before it runs.
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1436	def SI_INIT_M0 : SPseudoInstSI <(outs), (ins SSrc_32:$src)> {
Matt Arsenault	4ac341c	2016-04-14 21:58:15 +0000	[diff] [blame]	1437	let Defs = [M0];
				1438	let usesCustomInserter = 1;
Matt Arsenault	4ac341c	2016-04-14 21:58:15 +0000	[diff] [blame]	1439	let isAsCheapAsAMove = 1;
Matt Arsenault	4ac341c	2016-04-14 21:58:15 +0000	[diff] [blame]	1440	let isReMaterializable = 1;
				1441	}
				1442
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1443	def SI_RETURN : SPseudoInstSI <
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1444	(outs), (ins variable_ops), [(AMDGPUreturn)]> {
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1445	let isTerminator = 1;
				1446	let isBarrier = 1;
				1447	let isReturn = 1;
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1448	let hasSideEffects = 1;
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1449	let hasNoSchedulingInfo = 1;
				1450	}
				1451
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1452	let Defs = [M0, EXEC],
Matt Arsenault	3cb4dde	2016-06-22 23:40:57 +0000	[diff] [blame]	1453	UseNamedOperandTable = 1 in {
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1454
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1455	class SI_INDIRECT_SRC<RegisterClass rc> : VPseudoInstSI <
Matt Arsenault	cb540bc	2016-07-19 00:35:03 +0000	[diff] [blame]	1456	(outs VGPR_32:$vdst),
				1457	(ins rc:$src, VS_32:$idx, i32imm:$offset)> {
				1458	let usesCustomInserter = 1;
				1459	}
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1460
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1461	class SI_INDIRECT_DST<RegisterClass rc> : VPseudoInstSI <
Matt Arsenault	cb540bc	2016-07-19 00:35:03 +0000	[diff] [blame]	1462	(outs rc:$vdst),
				1463	(ins rc:$src, VS_32:$idx, i32imm:$offset, VGPR_32:$val)> {
Matt Arsenault	3cb4dde	2016-06-22 23:40:57 +0000	[diff] [blame]	1464	let Constraints = "$src = $vdst";
Matt Arsenault	cb540bc	2016-07-19 00:35:03 +0000	[diff] [blame]	1465	let usesCustomInserter = 1;
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1466	}
				1467
Matt Arsenault	2841927	2015-10-07 00:42:51 +0000	[diff] [blame]	1468	// TODO: We can support indirect SGPR access.
				1469	def SI_INDIRECT_SRC_V1 : SI_INDIRECT_SRC<VGPR_32>;
				1470	def SI_INDIRECT_SRC_V2 : SI_INDIRECT_SRC<VReg_64>;
				1471	def SI_INDIRECT_SRC_V4 : SI_INDIRECT_SRC<VReg_128>;
				1472	def SI_INDIRECT_SRC_V8 : SI_INDIRECT_SRC<VReg_256>;
				1473	def SI_INDIRECT_SRC_V16 : SI_INDIRECT_SRC<VReg_512>;
				1474
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	1475	def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VGPR_32>;
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1476	def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
				1477	def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
				1478	def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
				1479	def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
				1480
Matt Arsenault	cb540bc	2016-07-19 00:35:03 +0000	[diff] [blame]	1481	} // End Uses = [EXEC], Defs = [M0, EXEC]
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	1482
Tom Stellard	eba6107	2014-05-02 15:41:42 +0000	[diff] [blame]	1483	multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
Matt Arsenault	80f766a	2015-09-10 01:23:28 +0000	[diff] [blame]	1484	let UseNamedOperandTable = 1, Uses = [EXEC] in {
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1485	def _SAVE : PseudoInstSI <
Tom Stellard	42fb60e	2015-01-14 15:42:31 +0000	[diff] [blame]	1486	(outs),
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1487	(ins sgpr_class:$src, i32imm:$frame_idx)> {
Matt Arsenault	9a32cd3	2015-08-29 06:48:57 +0000	[diff] [blame]	1488	let mayStore = 1;
				1489	let mayLoad = 0;
				1490	}
Tom Stellard	eba6107	2014-05-02 15:41:42 +0000	[diff] [blame]	1491
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1492	def _RESTORE : PseudoInstSI <
Tom Stellard	42fb60e	2015-01-14 15:42:31 +0000	[diff] [blame]	1493	(outs sgpr_class:$dst),
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1494	(ins i32imm:$frame_idx)> {
Matt Arsenault	9a32cd3	2015-08-29 06:48:57 +0000	[diff] [blame]	1495	let mayStore = 0;
				1496	let mayLoad = 1;
				1497	}
Tom Stellard	42fb60e	2015-01-14 15:42:31 +0000	[diff] [blame]	1498	} // End UseNamedOperandTable = 1
Tom Stellard	eba6107	2014-05-02 15:41:42 +0000	[diff] [blame]	1499	}
				1500
Tom Stellard	c274349	2015-05-12 15:00:53 +0000	[diff] [blame]	1501	// It's unclear whether you can use M0 as the output of v_readlane_b32
Artem Tamazov	38e496b	2016-04-29 17:04:50 +0000	[diff] [blame]	1502	// instructions, so use SReg_32_XM0 register class for spills to prevent
Tom Stellard	c274349	2015-05-12 15:00:53 +0000	[diff] [blame]	1503	// this from happening.
Artem Tamazov	38e496b	2016-04-29 17:04:50 +0000	[diff] [blame]	1504	defm SI_SPILL_S32 : SI_SPILL_SGPR <SReg_32_XM0>;
Tom Stellard	eba6107	2014-05-02 15:41:42 +0000	[diff] [blame]	1505	defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
				1506	defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
				1507	defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;
				1508	defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
				1509
Tom Stellard	9646890	2014-09-24 01:33:17 +0000	[diff] [blame]	1510	multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> {
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1511	let UseNamedOperandTable = 1, VGPRSpill = 1 in {
				1512	def _SAVE : VPseudoInstSI <
Tom Stellard	42fb60e	2015-01-14 15:42:31 +0000	[diff] [blame]	1513	(outs),
Tom Stellard	95292bb	2015-01-20 17:49:47 +0000	[diff] [blame]	1514	(ins vgpr_class:$src, i32imm:$frame_idx, SReg_128:$scratch_rsrc,
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1515	SReg_32:$scratch_offset, i32imm:$offset)> {
Matt Arsenault	9a32cd3	2015-08-29 06:48:57 +0000	[diff] [blame]	1516	let mayStore = 1;
				1517	let mayLoad = 0;
				1518	}
Tom Stellard	9646890	2014-09-24 01:33:17 +0000	[diff] [blame]	1519
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1520	def _RESTORE : VPseudoInstSI <
Tom Stellard	42fb60e	2015-01-14 15:42:31 +0000	[diff] [blame]	1521	(outs vgpr_class:$dst),
Tom Stellard	649b5db	2016-03-04 18:31:18 +0000	[diff] [blame]	1522	(ins i32imm:$frame_idx, SReg_128:$scratch_rsrc, SReg_32:$scratch_offset,
Matt Arsenault	9babdf4	2016-06-22 20:15:28 +0000	[diff] [blame]	1523	i32imm:$offset)> {
Matt Arsenault	9a32cd3	2015-08-29 06:48:57 +0000	[diff] [blame]	1524	let mayStore = 0;
				1525	let mayLoad = 1;
				1526	}
Tom Stellard	a77c3f7	2015-05-12 18:59:17 +0000	[diff] [blame]	1527	} // End UseNamedOperandTable = 1, VGPRSpill = 1
Tom Stellard	9646890	2014-09-24 01:33:17 +0000	[diff] [blame]	1528	}
				1529
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	1530	defm SI_SPILL_V32 : SI_SPILL_VGPR <VGPR_32>;
Tom Stellard	9646890	2014-09-24 01:33:17 +0000	[diff] [blame]	1531	defm SI_SPILL_V64 : SI_SPILL_VGPR <VReg_64>;
				1532	defm SI_SPILL_V96 : SI_SPILL_VGPR <VReg_96>;
				1533	defm SI_SPILL_V128 : SI_SPILL_VGPR <VReg_128>;
				1534	defm SI_SPILL_V256 : SI_SPILL_VGPR <VReg_256>;
				1535	defm SI_SPILL_V512 : SI_SPILL_VGPR <VReg_512>;
				1536
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1537	def SI_PC_ADD_REL_OFFSET : SPseudoInstSI <
Tom Stellard	067c815	2014-07-21 14:01:14 +0000	[diff] [blame]	1538	(outs SReg_64:$dst),
Tom Stellard	bf3e6e5	2016-06-14 20:29:59 +0000	[diff] [blame]	1539	(ins si_ga:$ptr),
Matt Arsenault	fc7e6a0	2016-07-12 00:23:17 +0000	[diff] [blame]	1540	[(set SReg_64:$dst, (i64 (SIpc_add_rel_offset (tglobaladdr:$ptr))))]> {
Matt Arsenault	71ed8a6	2016-08-27 03:00:51 +0000	[diff] [blame]	1541	let Defs = [SCC];
Matt Arsenault	d092a06	2015-10-02 18:58:37 +0000	[diff] [blame]	1542	}
Tom Stellard	067c815	2014-07-21 14:01:14 +0000	[diff] [blame]	1543
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	1544	} // End SubtargetPredicate = isGCN
Tom Stellard	0e70de5	2014-05-16 20:56:45 +0000	[diff] [blame]	1545
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	1546	let Predicates = [isGCN] in {
Tom Stellard	0e70de5	2014-05-16 20:56:45 +0000	[diff] [blame]	1547
Nicolai Haehnle	3b57200	2016-07-28 11:39:24 +0000	[diff] [blame]	1548	def : Pat<
				1549	(int_amdgcn_else i64:$src, bb:$target),
				1550	(SI_ELSE $src, $target, 0)
				1551	>;
				1552
Tom Stellard	be8ebee	2013-01-18 21:15:50 +0000	[diff] [blame]	1553	def : Pat <
				1554	(int_AMDGPU_kilp),
Michel Danzer	9e61c4b	2014-02-27 01:47:09 +0000	[diff] [blame]	1555	(SI_KILL 0xbf800000)
Tom Stellard	be8ebee	2013-01-18 21:15:50 +0000	[diff] [blame]	1556	>;
				1557
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1558	/* int_SI_vs_load_input */
				1559	def : Pat<
Tom Stellard	bc5b537	2014-06-13 16:38:59 +0000	[diff] [blame]	1560	(SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr),
Tom Stellard	c229baa	2015-03-10 16:16:49 +0000	[diff] [blame]	1561	(BUFFER_LOAD_FORMAT_XYZW_IDXEN $buf_idx_vgpr, $tlst, 0, imm:$attr_offset, 0, 0, 0)
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1562	>;
				1563
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1564	def : Pat <
				1565	(int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1566	f32:$src0, f32:$src1, f32:$src2, f32:$src3),
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1567	(EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1568	$src0, $src1, $src2, $src3)
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1569	>;
				1570
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	1571	//===----------------------------------------------------------------------===//
Nicolai Haehnle	b142770	2016-03-10 18:43:50 +0000	[diff] [blame]	1572	// buffer_load/store_format patterns
				1573	//===----------------------------------------------------------------------===//
Nicolai Haehnle	b142770	2016-03-10 18:43:50 +0000	[diff] [blame]	1574
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1575	multiclass MUBUF_LoadIntrinsicPat<SDPatternOperator name, ValueType vt,
				1576	string opcode> {
Nicolai Haehnle	95e8ffd	2016-03-18 16:24:40 +0000	[diff] [blame]	1577	def : Pat<
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1578	(vt (name v4i32:$rsrc, 0,
				1579	(MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
				1580	imm:$glc, imm:$slc)),
Nicolai Haehnle	95e8ffd	2016-03-18 16:24:40 +0000	[diff] [blame]	1581	(!cast<MUBUF>(opcode # _OFFSET) $rsrc, $soffset, (as_i16imm $offset),
				1582	(as_i1imm $glc), (as_i1imm $slc), 0)
				1583	>;
Nicolai Haehnle	b142770	2016-03-10 18:43:50 +0000	[diff] [blame]	1584
Nicolai Haehnle	95e8ffd	2016-03-18 16:24:40 +0000	[diff] [blame]	1585	def : Pat<
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1586	(vt (name v4i32:$rsrc, i32:$vindex,
				1587	(MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
				1588	imm:$glc, imm:$slc)),
Nicolai Haehnle	95e8ffd	2016-03-18 16:24:40 +0000	[diff] [blame]	1589	(!cast<MUBUF>(opcode # _IDXEN) $vindex, $rsrc, $soffset, (as_i16imm $offset),
				1590	(as_i1imm $glc), (as_i1imm $slc), 0)
				1591	>;
Nicolai Haehnle	b142770	2016-03-10 18:43:50 +0000	[diff] [blame]	1592
Nicolai Haehnle	95e8ffd	2016-03-18 16:24:40 +0000	[diff] [blame]	1593	def : Pat<
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1594	(vt (name v4i32:$rsrc, 0,
				1595	(MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
				1596	imm:$glc, imm:$slc)),
Nicolai Haehnle	95e8ffd	2016-03-18 16:24:40 +0000	[diff] [blame]	1597	(!cast<MUBUF>(opcode # _OFFEN) $voffset, $rsrc, $soffset, (as_i16imm $offset),
				1598	(as_i1imm $glc), (as_i1imm $slc), 0)
				1599	>;
				1600
				1601	def : Pat<
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1602	(vt (name v4i32:$rsrc, i32:$vindex,
				1603	(MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
				1604	imm:$glc, imm:$slc)),
Nicolai Haehnle	95e8ffd	2016-03-18 16:24:40 +0000	[diff] [blame]	1605	(!cast<MUBUF>(opcode # _BOTHEN)
				1606	(REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
				1607	$rsrc, $soffset, (as_i16imm $offset),
				1608	(as_i1imm $glc), (as_i1imm $slc), 0)
				1609	>;
				1610	}
				1611
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1612	defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load_format, f32, "BUFFER_LOAD_FORMAT_X">;
				1613	defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load_format, v2f32, "BUFFER_LOAD_FORMAT_XY">;
				1614	defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load_format, v4f32, "BUFFER_LOAD_FORMAT_XYZW">;
				1615	defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load, f32, "BUFFER_LOAD_DWORD">;
				1616	defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load, v2f32, "BUFFER_LOAD_DWORDX2">;
				1617	defm : MUBUF_LoadIntrinsicPat<int_amdgcn_buffer_load, v4f32, "BUFFER_LOAD_DWORDX4">;
Nicolai Haehnle	b142770	2016-03-10 18:43:50 +0000	[diff] [blame]	1618
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1619	multiclass MUBUF_StoreIntrinsicPat<SDPatternOperator name, ValueType vt,
				1620	string opcode> {
				1621	def : Pat<
				1622	(name vt:$vdata, v4i32:$rsrc, 0,
				1623	(MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
				1624	imm:$glc, imm:$slc),
Nicolai Haehnle	8a482b3	2016-08-02 19:31:14 +0000	[diff] [blame]	1625	(!cast<MUBUF>(opcode # _OFFSET_exact) $vdata, $rsrc, $soffset, (as_i16imm $offset),
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1626	(as_i1imm $glc), (as_i1imm $slc), 0)
				1627	>;
Nicolai Haehnle	b142770	2016-03-10 18:43:50 +0000	[diff] [blame]	1628
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1629	def : Pat<
				1630	(name vt:$vdata, v4i32:$rsrc, i32:$vindex,
				1631	(MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
				1632	imm:$glc, imm:$slc),
Nicolai Haehnle	8a482b3	2016-08-02 19:31:14 +0000	[diff] [blame]	1633	(!cast<MUBUF>(opcode # _IDXEN_exact) $vdata, $vindex, $rsrc, $soffset,
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1634	(as_i16imm $offset), (as_i1imm $glc),
				1635	(as_i1imm $slc), 0)
				1636	>;
Nicolai Haehnle	b142770	2016-03-10 18:43:50 +0000	[diff] [blame]	1637
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1638	def : Pat<
				1639	(name vt:$vdata, v4i32:$rsrc, 0,
				1640	(MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
				1641	imm:$glc, imm:$slc),
Nicolai Haehnle	8a482b3	2016-08-02 19:31:14 +0000	[diff] [blame]	1642	(!cast<MUBUF>(opcode # _OFFEN_exact) $vdata, $voffset, $rsrc, $soffset,
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1643	(as_i16imm $offset), (as_i1imm $glc),
				1644	(as_i1imm $slc), 0)
				1645	>;
Nicolai Haehnle	b142770	2016-03-10 18:43:50 +0000	[diff] [blame]	1646
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1647	def : Pat<
				1648	(name vt:$vdata, v4i32:$rsrc, i32:$vindex,
				1649	(MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
				1650	imm:$glc, imm:$slc),
Nicolai Haehnle	8a482b3	2016-08-02 19:31:14 +0000	[diff] [blame]	1651	(!cast<MUBUF>(opcode # _BOTHEN_exact)
Nicolai Haehnle	df77c9a	2016-04-12 21:18:10 +0000	[diff] [blame]	1652	$vdata,
				1653	(REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
				1654	$rsrc, $soffset, (as_i16imm $offset),
				1655	(as_i1imm $glc), (as_i1imm $slc), 0)
				1656	>;
				1657	}
				1658
				1659	defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store_format, f32, "BUFFER_STORE_FORMAT_X">;
				1660	defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store_format, v2f32, "BUFFER_STORE_FORMAT_XY">;
				1661	defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store_format, v4f32, "BUFFER_STORE_FORMAT_XYZW">;
				1662	defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store, f32, "BUFFER_STORE_DWORD">;
				1663	defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store, v2f32, "BUFFER_STORE_DWORDX2">;
				1664	defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store, v4f32, "BUFFER_STORE_DWORDX4">;
Nicolai Haehnle	b142770	2016-03-10 18:43:50 +0000	[diff] [blame]	1665
				1666	//===----------------------------------------------------------------------===//
Nicolai Haehnle	ad63638	2016-03-18 16:24:31 +0000	[diff] [blame]	1667	// buffer_atomic patterns
				1668	//===----------------------------------------------------------------------===//
				1669	multiclass BufferAtomicPatterns<SDPatternOperator name, string opcode> {
				1670	def : Pat<
				1671	(name i32:$vdata_in, v4i32:$rsrc, 0,
				1672	(MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
				1673	imm:$slc),
				1674	(!cast<MUBUF>(opcode # _RTN_OFFSET) $vdata_in, $rsrc, $soffset,
				1675	(as_i16imm $offset), (as_i1imm $slc))
				1676	>;
				1677
				1678	def : Pat<
				1679	(name i32:$vdata_in, v4i32:$rsrc, i32:$vindex,
				1680	(MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
				1681	imm:$slc),
				1682	(!cast<MUBUF>(opcode # _RTN_IDXEN) $vdata_in, $vindex, $rsrc, $soffset,
				1683	(as_i16imm $offset), (as_i1imm $slc))
				1684	>;
				1685
				1686	def : Pat<
				1687	(name i32:$vdata_in, v4i32:$rsrc, 0,
				1688	(MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
				1689	imm:$slc),
				1690	(!cast<MUBUF>(opcode # _RTN_OFFEN) $vdata_in, $voffset, $rsrc, $soffset,
				1691	(as_i16imm $offset), (as_i1imm $slc))
				1692	>;
				1693
				1694	def : Pat<
				1695	(name i32:$vdata_in, v4i32:$rsrc, i32:$vindex,
				1696	(MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
				1697	imm:$slc),
				1698	(!cast<MUBUF>(opcode # _RTN_BOTHEN)
				1699	$vdata_in,
				1700	(REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
				1701	$rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc))
				1702	>;
				1703	}
				1704
				1705	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_swap, "BUFFER_ATOMIC_SWAP">;
				1706	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_add, "BUFFER_ATOMIC_ADD">;
				1707	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_sub, "BUFFER_ATOMIC_SUB">;
				1708	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_smin, "BUFFER_ATOMIC_SMIN">;
				1709	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_umin, "BUFFER_ATOMIC_UMIN">;
				1710	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_smax, "BUFFER_ATOMIC_SMAX">;
				1711	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_umax, "BUFFER_ATOMIC_UMAX">;
				1712	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_and, "BUFFER_ATOMIC_AND">;
				1713	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_or, "BUFFER_ATOMIC_OR">;
				1714	defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_xor, "BUFFER_ATOMIC_XOR">;
				1715
				1716	def : Pat<
				1717	(int_amdgcn_buffer_atomic_cmpswap
				1718	i32:$data, i32:$cmp, v4i32:$rsrc, 0,
				1719	(MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
				1720	imm:$slc),
				1721	(EXTRACT_SUBREG
				1722	(BUFFER_ATOMIC_CMPSWAP_RTN_OFFSET
				1723	(REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
				1724	$rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
				1725	sub0)
				1726	>;
				1727
				1728	def : Pat<
				1729	(int_amdgcn_buffer_atomic_cmpswap
				1730	i32:$data, i32:$cmp, v4i32:$rsrc, i32:$vindex,
				1731	(MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
				1732	imm:$slc),
				1733	(EXTRACT_SUBREG
				1734	(BUFFER_ATOMIC_CMPSWAP_RTN_IDXEN
				1735	(REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
				1736	$vindex, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
				1737	sub0)
				1738	>;
				1739
				1740	def : Pat<
				1741	(int_amdgcn_buffer_atomic_cmpswap
				1742	i32:$data, i32:$cmp, v4i32:$rsrc, 0,
				1743	(MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
				1744	imm:$slc),
				1745	(EXTRACT_SUBREG
				1746	(BUFFER_ATOMIC_CMPSWAP_RTN_OFFEN
				1747	(REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
				1748	$voffset, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
				1749	sub0)
				1750	>;
				1751
				1752	def : Pat<
				1753	(int_amdgcn_buffer_atomic_cmpswap
				1754	i32:$data, i32:$cmp, v4i32:$rsrc, i32:$vindex,
				1755	(MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
				1756	imm:$slc),
				1757	(EXTRACT_SUBREG
				1758	(BUFFER_ATOMIC_CMPSWAP_RTN_BOTHEN
				1759	(REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
				1760	(REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
				1761	$rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
				1762	sub0)
				1763	>;
				1764
Changpeng Fang	278a5b3	2016-03-10 16:47:15 +0000	[diff] [blame]	1765	//===----------------------------------------------------------------------===//
Wei Ding	07e0371	2016-07-28 16:42:13 +0000	[diff] [blame]	1766	// V_ICMPIntrinsic Pattern.
				1767	//===----------------------------------------------------------------------===//
				1768	class ICMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> : Pat <
				1769	(AMDGPUsetcc vt:$src0, vt:$src1, cond),
				1770	(inst $src0, $src1)
				1771	>;
				1772
				1773	def : ICMP_Pattern <COND_EQ, V_CMP_EQ_I32_e64, i32>;
				1774	def : ICMP_Pattern <COND_NE, V_CMP_NE_I32_e64, i32>;
				1775	def : ICMP_Pattern <COND_UGT, V_CMP_GT_U32_e64, i32>;
				1776	def : ICMP_Pattern <COND_UGE, V_CMP_GE_U32_e64, i32>;
				1777	def : ICMP_Pattern <COND_ULT, V_CMP_LT_U32_e64, i32>;
				1778	def : ICMP_Pattern <COND_ULE, V_CMP_LE_U32_e64, i32>;
				1779	def : ICMP_Pattern <COND_SGT, V_CMP_GT_I32_e64, i32>;
				1780	def : ICMP_Pattern <COND_SGE, V_CMP_GE_I32_e64, i32>;
				1781	def : ICMP_Pattern <COND_SLT, V_CMP_LT_I32_e64, i32>;
				1782	def : ICMP_Pattern <COND_SLE, V_CMP_LE_I32_e64, i32>;
				1783
				1784	def : ICMP_Pattern <COND_EQ, V_CMP_EQ_I64_e64, i64>;
				1785	def : ICMP_Pattern <COND_NE, V_CMP_NE_I64_e64, i64>;
				1786	def : ICMP_Pattern <COND_UGT, V_CMP_GT_U64_e64, i64>;
				1787	def : ICMP_Pattern <COND_UGE, V_CMP_GE_U64_e64, i64>;
				1788	def : ICMP_Pattern <COND_ULT, V_CMP_LT_U64_e64, i64>;
				1789	def : ICMP_Pattern <COND_ULE, V_CMP_LE_U64_e64, i64>;
				1790	def : ICMP_Pattern <COND_SGT, V_CMP_GT_I64_e64, i64>;
				1791	def : ICMP_Pattern <COND_SGE, V_CMP_GE_I64_e64, i64>;
				1792	def : ICMP_Pattern <COND_SLT, V_CMP_LT_I64_e64, i64>;
				1793	def : ICMP_Pattern <COND_SLE, V_CMP_LE_I64_e64, i64>;
				1794
				1795	class FCMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> : Pat <
				1796	(i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
				1797	(vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),
				1798	(inst $src0_modifiers, $src0, $src1_modifiers, $src1,
				1799	DSTCLAMP.NONE, DSTOMOD.NONE)
				1800	>;
				1801
				1802	def : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F32_e64, f32>;
				1803	def : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F32_e64, f32>;
				1804	def : FCMP_Pattern <COND_OGT, V_CMP_GT_F32_e64, f32>;
				1805	def : FCMP_Pattern <COND_OGE, V_CMP_GE_F32_e64, f32>;
				1806	def : FCMP_Pattern <COND_OLT, V_CMP_LT_F32_e64, f32>;
				1807	def : FCMP_Pattern <COND_OLE, V_CMP_LE_F32_e64, f32>;
				1808
				1809	def : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F64_e64, f64>;
				1810	def : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F64_e64, f64>;
				1811	def : FCMP_Pattern <COND_OGT, V_CMP_GT_F64_e64, f64>;
				1812	def : FCMP_Pattern <COND_OGE, V_CMP_GE_F64_e64, f64>;
				1813	def : FCMP_Pattern <COND_OLT, V_CMP_LT_F64_e64, f64>;
				1814	def : FCMP_Pattern <COND_OLE, V_CMP_LE_F64_e64, f64>;
				1815
				1816	def : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F32_e64, f32>;
				1817	def : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F32_e64, f32>;
				1818	def : FCMP_Pattern <COND_UGT, V_CMP_NLE_F32_e64, f32>;
				1819	def : FCMP_Pattern <COND_UGE, V_CMP_NLT_F32_e64, f32>;
				1820	def : FCMP_Pattern <COND_ULT, V_CMP_NGE_F32_e64, f32>;
				1821	def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F32_e64, f32>;
				1822
				1823	def : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F64_e64, f64>;
				1824	def : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F64_e64, f64>;
				1825	def : FCMP_Pattern <COND_UGT, V_CMP_NLE_F64_e64, f64>;
				1826	def : FCMP_Pattern <COND_UGE, V_CMP_NLT_F64_e64, f64>;
				1827	def : FCMP_Pattern <COND_ULT, V_CMP_NGE_F64_e64, f64>;
				1828	def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F64_e64, f64>;
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	1829	// SMRD Patterns
				1830	//===----------------------------------------------------------------------===//
				1831
Tom Stellard	217361c	2015-08-06 19:28:38 +0000	[diff] [blame]	1832	multiclass SMRD_Pattern <string Instr, ValueType vt> {
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	1833
Tom Stellard	dee26a2	2015-08-06 19:28:30 +0000	[diff] [blame]	1834	// 1. IMM offset
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	1835	def : Pat <
Tom Stellard	a6f24c6	2015-12-15 20:55:55 +0000	[diff] [blame]	1836	(smrd_load (SMRDImm i64:$sbase, i32:$offset)),
Tom Stellard	217361c	2015-08-06 19:28:38 +0000	[diff] [blame]	1837	(vt (!cast<SMRD>(Instr#"_IMM") $sbase, $offset))
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	1838	>;
				1839
Tom Stellard	dee26a2	2015-08-06 19:28:30 +0000	[diff] [blame]	1840	// 2. SGPR offset
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	1841	def : Pat <
Tom Stellard	a6f24c6	2015-12-15 20:55:55 +0000	[diff] [blame]	1842	(smrd_load (SMRDSgpr i64:$sbase, i32:$offset)),
Tom Stellard	217361c	2015-08-06 19:28:38 +0000	[diff] [blame]	1843	(vt (!cast<SMRD>(Instr#"_SGPR") $sbase, $offset))
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	1844	>;
Tom Stellard	217361c	2015-08-06 19:28:38 +0000	[diff] [blame]	1845
				1846	def : Pat <
Tom Stellard	a6f24c6	2015-12-15 20:55:55 +0000	[diff] [blame]	1847	(smrd_load (SMRDImm32 i64:$sbase, i32:$offset)),
Tom Stellard	217361c	2015-08-06 19:28:38 +0000	[diff] [blame]	1848	(vt (!cast<SMRD>(Instr#"_IMM_ci") $sbase, $offset))
				1849	> {
				1850	let Predicates = [isCIOnly];
				1851	}
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	1852	}
				1853
Tom Stellard	a6f24c6	2015-12-15 20:55:55 +0000	[diff] [blame]	1854	// Global and constant loads can be selected to either MUBUF or SMRD
				1855	// instructions, but SMRD instructions are faster so we want the instruction
				1856	// selector to prefer those.
				1857	let AddedComplexity = 100 in {
				1858
Tom Stellard	217361c	2015-08-06 19:28:38 +0000	[diff] [blame]	1859	defm : SMRD_Pattern <"S_LOAD_DWORD", i32>;
				1860	defm : SMRD_Pattern <"S_LOAD_DWORDX2", v2i32>;
				1861	defm : SMRD_Pattern <"S_LOAD_DWORDX4", v4i32>;
Tom Stellard	217361c	2015-08-06 19:28:38 +0000	[diff] [blame]	1862	defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>;
				1863	defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>;
Marek Olsak	58f61a8	2014-12-07 17:17:38 +0000	[diff] [blame]	1864
Tom Stellard	dee26a2	2015-08-06 19:28:30 +0000	[diff] [blame]	1865	// 1. Offset as an immediate
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	1866	def : Pat <
Tom Stellard	dee26a2	2015-08-06 19:28:30 +0000	[diff] [blame]	1867	(SIload_constant v4i32:$sbase, (SMRDBufferImm i32:$offset)),
				1868	(S_BUFFER_LOAD_DWORD_IMM $sbase, $offset)
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	1869	>;
				1870
				1871	// 2. Offset loaded in an 32bit SGPR
				1872	def : Pat <
Tom Stellard	dee26a2	2015-08-06 19:28:30 +0000	[diff] [blame]	1873	(SIload_constant v4i32:$sbase, (SMRDBufferSgpr i32:$offset)),
				1874	(S_BUFFER_LOAD_DWORD_SGPR $sbase, $offset)
Tom Stellard	8d6d449	2014-04-22 16:33:57 +0000	[diff] [blame]	1875	>;
				1876
Tom Stellard	217361c	2015-08-06 19:28:38 +0000	[diff] [blame]	1877	let Predicates = [isCI] in {
				1878
				1879	def : Pat <
				1880	(SIload_constant v4i32:$sbase, (SMRDBufferImm32 i32:$offset)),
				1881	(S_BUFFER_LOAD_DWORD_IMM_ci $sbase, $offset)
				1882	>;
				1883
				1884	} // End Predicates = [isCI]
				1885
Tom Stellard	a6f24c6	2015-12-15 20:55:55 +0000	[diff] [blame]	1886	} // End let AddedComplexity = 10000
				1887
Tom Stellard	ae4c9e7	2014-06-20 17:06:11 +0000	[diff] [blame]	1888	//===----------------------------------------------------------------------===//
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	1889	// VOP1 Patterns
				1890	//===----------------------------------------------------------------------===//
				1891
Matt Arsenault	22ca3f8	2014-07-15 23:50:10 +0000	[diff] [blame]	1892	let Predicates = [UnsafeFPMath] in {
Matt Arsenault	0bbcd8b	2015-02-14 04:30:08 +0000	[diff] [blame]	1893
				1894	//def : RcpPat<V_RCP_F64_e32, f64>;
				1895	//defm : RsqPat<V_RSQ_F64_e32, f64>;
				1896	//defm : RsqPat<V_RSQ_F32_e32, f32>;
				1897
				1898	def : RsqPat<V_RSQ_F32_e32, f32>;
				1899	def : RsqPat<V_RSQ_F64_e32, f64>;
Matt Arsenault	7401516	2016-05-28 00:19:52 +0000	[diff] [blame]	1900
				1901	// Convert (x - floor(x)) to fract(x)
				1902	def : Pat <
				1903	(f32 (fsub (f32 (VOP3Mods f32:$x, i32:$mods)),
				1904	(f32 (ffloor (f32 (VOP3Mods f32:$x, i32:$mods)))))),
				1905	(V_FRACT_F32_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)
				1906	>;
				1907
				1908	// Convert (x + (-floor(x))) to fract(x)
				1909	def : Pat <
				1910	(f64 (fadd (f64 (VOP3Mods f64:$x, i32:$mods)),
				1911	(f64 (fneg (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))))))),
				1912	(V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)
				1913	>;
				1914
				1915	} // End Predicates = [UnsafeFPMath]
Matt Arsenault	e9fa3b8	2014-07-15 20:18:31 +0000	[diff] [blame]	1916
Matt Arsenault	a0050b0	2014-06-19 01:19:19 +0000	[diff] [blame]	1917	//===----------------------------------------------------------------------===//
Tom Stellard	58ac744	2014-04-29 23:12:48 +0000	[diff] [blame]	1918	// VOP2 Patterns
				1919	//===----------------------------------------------------------------------===//
				1920
Tom Stellard	ae4c9e7	2014-06-20 17:06:11 +0000	[diff] [blame]	1921	def : Pat <
				1922	(i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)),
Matt Arsenault	49dd428	2014-09-15 17:15:02 +0000	[diff] [blame]	1923	(V_BCNT_U32_B32_e64 $popcnt, $val)
Tom Stellard	ae4c9e7	2014-06-20 17:06:11 +0000	[diff] [blame]	1924	>;
				1925
Tom Stellard	5224df3	2015-03-10 16:16:44 +0000	[diff] [blame]	1926	def : Pat <
				1927	(i32 (select i1:$src0, i32:$src1, i32:$src2)),
				1928	(V_CNDMASK_B32_e64 $src2, $src1, $src0)
				1929	>;
				1930
Tom Stellard	db5a11f	2015-07-13 15:47:57 +0000	[diff] [blame]	1931	// Pattern for V_MAC_F32
				1932	def : Pat <
				1933	(fmad (VOP3NoMods0 f32:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
				1934	(VOP3NoMods f32:$src1, i32:$src1_modifiers),
				1935	(VOP3NoMods f32:$src2, i32:$src2_modifiers)),
				1936	(V_MAC_F32_e64 $src0_modifiers, $src0, $src1_modifiers, $src1,
				1937	$src2_modifiers, $src2, $clamp, $omod)
				1938	>;
				1939
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	1940	/******** ======================= ********/
				1941	/******** Image sampling patterns ********/
				1942	/******** ======================= ********/
Tom Stellard	ae6c06e	2013-02-07 17:02:13 +0000	[diff] [blame]	1943
Marek Olsak	d8ecaee	2014-07-11 17:11:46 +0000	[diff] [blame]	1944	// Image + sampler
Marek Olsak	51b8e7b	2014-06-18 22:00:29 +0000	[diff] [blame]	1945	class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
Marek Olsak	eac5062	2014-07-11 17:11:52 +0000	[diff] [blame]	1946	(name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm,
Marek Olsak	51b8e7b	2014-06-18 22:00:29 +0000	[diff] [blame]	1947	i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
Nikolay Haustov	2f684f1	2016-02-26 09:51:05 +0000	[diff] [blame]	1948	(opcode $addr, $rsrc, $sampler,
				1949	(as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc),
				1950	(as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da))
Marek Olsak	51b8e7b	2014-06-18 22:00:29 +0000	[diff] [blame]	1951	>;
				1952
Marek Olsak	d8ecaee	2014-07-11 17:11:46 +0000	[diff] [blame]	1953	multiclass SampleRawPatterns<SDPatternOperator name, string opcode> {
				1954	def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
				1955	def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
				1956	def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
				1957	def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>;
				1958	def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>;
				1959	}
				1960
Changpeng Fang	fb9c381	2016-08-10 21:15:30 +0000	[diff] [blame]	1961
				1962	// Image + sampler for amdgcn
				1963	// TODO:
				1964	// 1. Handle half data type like v4f16, and add D16 bit support;
				1965	// 2. Handle v4i32 rsrc type (Register Class for the instruction to be SReg_128).
				1966	// 3. Add A16 support when we pass address of half type.
				1967	multiclass AMDGCNSamplePattern<SDPatternOperator name, MIMG opcode, ValueType vt> {
				1968	def : Pat<
				1969	(v4f32 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i1:$unorm, i1:$glc,
				1970	i1:$slc, i1:$lwe, i1:$da)),
				1971	(opcode $addr, $rsrc, $sampler,
				1972	(as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc),
				1973	0, 0, (as_i1imm $lwe), (as_i1imm $da))
				1974	>;
				1975	}
				1976
				1977	multiclass AMDGCNSamplePatterns<SDPatternOperator name, string opcode> {
				1978	defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V4_V1), f32>;
				1979	defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V4_V2), v2f32>;
				1980	defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V4_V4), v4f32>;
				1981	defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V4_V8), v8f32>;
				1982	defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V4_V16), v16f32>;
				1983	}
				1984
				1985
Marek Olsak	d8ecaee	2014-07-11 17:11:46 +0000	[diff] [blame]	1986	// Image only
				1987	class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
Nicolai Haehnle	f2c64db	2016-02-18 16:44:18 +0000	[diff] [blame]	1988	(name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$unorm,
				1989	imm:$r128, imm:$da, imm:$glc, imm:$slc, imm:$tfe, imm:$lwe),
Nikolay Haustov	2f684f1	2016-02-26 09:51:05 +0000	[diff] [blame]	1990	(opcode $addr, $rsrc,
				1991	(as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc),
				1992	(as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da))
Marek Olsak	d8ecaee	2014-07-11 17:11:46 +0000	[diff] [blame]	1993	>;
				1994
				1995	multiclass ImagePatterns<SDPatternOperator name, string opcode> {
				1996	def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
				1997	def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
				1998	def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
				1999	}
				2000
Nicolai Haehnle	f2c64db	2016-02-18 16:44:18 +0000	[diff] [blame]	2001	class ImageLoadPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
				2002	(name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$r128, imm:$da, imm:$glc,
				2003	imm:$slc),
Nikolay Haustov	2f684f1	2016-02-26 09:51:05 +0000	[diff] [blame]	2004	(opcode $addr, $rsrc,
				2005	(as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc),
				2006	(as_i1imm $r128), 0, 0, (as_i1imm $da))
Nicolai Haehnle	f2c64db	2016-02-18 16:44:18 +0000	[diff] [blame]	2007	>;
				2008
				2009	multiclass ImageLoadPatterns<SDPatternOperator name, string opcode> {
				2010	def : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
				2011	def : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
				2012	def : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
				2013	}
				2014
				2015	class ImageStorePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
				2016	(name v4f32:$data, vt:$addr, v8i32:$rsrc, i32:$dmask, imm:$r128, imm:$da,
				2017	imm:$glc, imm:$slc),
Nikolay Haustov	2f684f1	2016-02-26 09:51:05 +0000	[diff] [blame]	2018	(opcode $data, $addr, $rsrc,
				2019	(as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc),
				2020	(as_i1imm $r128), 0, 0, (as_i1imm $da))
Nicolai Haehnle	f2c64db	2016-02-18 16:44:18 +0000	[diff] [blame]	2021	>;
				2022
				2023	multiclass ImageStorePatterns<SDPatternOperator name, string opcode> {
				2024	def : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
				2025	def : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
				2026	def : ImageStorePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
				2027	}
				2028
Nikolay Haustov	5bf46ac1	2016-03-04 10:39:50 +0000	[diff] [blame]	2029	class ImageAtomicPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
				2030	(name i32:$vdata, vt:$addr, v8i32:$rsrc, imm:$r128, imm:$da, imm:$slc),
				2031	(opcode $vdata, $addr, $rsrc, 1, 1, 1, (as_i1imm $slc), (as_i1imm $r128), 0, 0, (as_i1imm $da))
				2032	>;
				2033
				2034	multiclass ImageAtomicPatterns<SDPatternOperator name, string opcode> {
				2035	def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V1), i32>;
				2036	def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V2), v2i32>;
				2037	def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V4), v4i32>;
				2038	}
				2039
				2040	class ImageAtomicCmpSwapPattern<MIMG opcode, ValueType vt> : Pat <
				2041	(int_amdgcn_image_atomic_cmpswap i32:$vsrc, i32:$vcmp, vt:$addr, v8i32:$rsrc,
				2042	imm:$r128, imm:$da, imm:$slc),
				2043	(EXTRACT_SUBREG
				2044	(opcode (REG_SEQUENCE VReg_64, $vsrc, sub0, $vcmp, sub1),
				2045	$addr, $rsrc, 3, 1, 1, (as_i1imm $slc), (as_i1imm $r128), 0, 0, (as_i1imm $da)),
				2046	sub0)
				2047	>;
				2048
Changpeng Fang	fb9c381	2016-08-10 21:15:30 +0000	[diff] [blame]	2049	// ======= SI Image Intrinsics ================
				2050
				2051	// Image load
				2052	defm : ImagePatterns<int_SI_image_load, "IMAGE_LOAD">;
				2053	defm : ImagePatterns<int_SI_image_load_mip, "IMAGE_LOAD_MIP">;
				2054	def : ImagePattern<int_SI_getresinfo, IMAGE_GET_RESINFO_V4_V1, i32>;
				2055
Marek Olsak	d8ecaee	2014-07-11 17:11:46 +0000	[diff] [blame]	2056	// Basic sample
				2057	defm : SampleRawPatterns<int_SI_image_sample, "IMAGE_SAMPLE">;
				2058	defm : SampleRawPatterns<int_SI_image_sample_cl, "IMAGE_SAMPLE_CL">;
				2059	defm : SampleRawPatterns<int_SI_image_sample_d, "IMAGE_SAMPLE_D">;
				2060	defm : SampleRawPatterns<int_SI_image_sample_d_cl, "IMAGE_SAMPLE_D_CL">;
				2061	defm : SampleRawPatterns<int_SI_image_sample_l, "IMAGE_SAMPLE_L">;
				2062	defm : SampleRawPatterns<int_SI_image_sample_b, "IMAGE_SAMPLE_B">;
				2063	defm : SampleRawPatterns<int_SI_image_sample_b_cl, "IMAGE_SAMPLE_B_CL">;
				2064	defm : SampleRawPatterns<int_SI_image_sample_lz, "IMAGE_SAMPLE_LZ">;
				2065	defm : SampleRawPatterns<int_SI_image_sample_cd, "IMAGE_SAMPLE_CD">;
				2066	defm : SampleRawPatterns<int_SI_image_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">;
				2067
				2068	// Sample with comparison
				2069	defm : SampleRawPatterns<int_SI_image_sample_c, "IMAGE_SAMPLE_C">;
				2070	defm : SampleRawPatterns<int_SI_image_sample_c_cl, "IMAGE_SAMPLE_C_CL">;
				2071	defm : SampleRawPatterns<int_SI_image_sample_c_d, "IMAGE_SAMPLE_C_D">;
				2072	defm : SampleRawPatterns<int_SI_image_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">;
				2073	defm : SampleRawPatterns<int_SI_image_sample_c_l, "IMAGE_SAMPLE_C_L">;
				2074	defm : SampleRawPatterns<int_SI_image_sample_c_b, "IMAGE_SAMPLE_C_B">;
				2075	defm : SampleRawPatterns<int_SI_image_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">;
				2076	defm : SampleRawPatterns<int_SI_image_sample_c_lz, "IMAGE_SAMPLE_C_LZ">;
				2077	defm : SampleRawPatterns<int_SI_image_sample_c_cd, "IMAGE_SAMPLE_C_CD">;
				2078	defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">;
				2079
				2080	// Sample with offsets
				2081	defm : SampleRawPatterns<int_SI_image_sample_o, "IMAGE_SAMPLE_O">;
				2082	defm : SampleRawPatterns<int_SI_image_sample_cl_o, "IMAGE_SAMPLE_CL_O">;
				2083	defm : SampleRawPatterns<int_SI_image_sample_d_o, "IMAGE_SAMPLE_D_O">;
				2084	defm : SampleRawPatterns<int_SI_image_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">;
				2085	defm : SampleRawPatterns<int_SI_image_sample_l_o, "IMAGE_SAMPLE_L_O">;
				2086	defm : SampleRawPatterns<int_SI_image_sample_b_o, "IMAGE_SAMPLE_B_O">;
				2087	defm : SampleRawPatterns<int_SI_image_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">;
				2088	defm : SampleRawPatterns<int_SI_image_sample_lz_o, "IMAGE_SAMPLE_LZ_O">;
				2089	defm : SampleRawPatterns<int_SI_image_sample_cd_o, "IMAGE_SAMPLE_CD_O">;
				2090	defm : SampleRawPatterns<int_SI_image_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">;
				2091
				2092	// Sample with comparison and offsets
				2093	defm : SampleRawPatterns<int_SI_image_sample_c_o, "IMAGE_SAMPLE_C_O">;
				2094	defm : SampleRawPatterns<int_SI_image_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">;
				2095	defm : SampleRawPatterns<int_SI_image_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">;
				2096	defm : SampleRawPatterns<int_SI_image_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">;
				2097	defm : SampleRawPatterns<int_SI_image_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">;
				2098	defm : SampleRawPatterns<int_SI_image_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">;
				2099	defm : SampleRawPatterns<int_SI_image_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">;
				2100	defm : SampleRawPatterns<int_SI_image_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">;
				2101	defm : SampleRawPatterns<int_SI_image_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">;
				2102	defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">;
				2103
				2104	// Gather opcodes
Marek Olsak	51b8e7b	2014-06-18 22:00:29 +0000	[diff] [blame]	2105	// Only the variants which make sense are defined.
				2106	def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V2, v2i32>;
				2107	def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V4, v4i32>;
				2108	def : SampleRawPattern<int_SI_gather4_cl, IMAGE_GATHER4_CL_V4_V4, v4i32>;
				2109	def : SampleRawPattern<int_SI_gather4_l, IMAGE_GATHER4_L_V4_V4, v4i32>;
				2110	def : SampleRawPattern<int_SI_gather4_b, IMAGE_GATHER4_B_V4_V4, v4i32>;
				2111	def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V4, v4i32>;
				2112	def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8i32>;
				2113	def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V2, v2i32>;
				2114	def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V4, v4i32>;
				2115
				2116	def : SampleRawPattern<int_SI_gather4_c, IMAGE_GATHER4_C_V4_V4, v4i32>;
				2117	def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V4, v4i32>;
				2118	def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8i32>;
				2119	def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V4, v4i32>;
				2120	def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8i32>;
				2121	def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V4, v4i32>;
				2122	def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8i32>;
				2123	def : SampleRawPattern<int_SI_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8i32>;
				2124	def : SampleRawPattern<int_SI_gather4_c_lz, IMAGE_GATHER4_C_LZ_V4_V4, v4i32>;
				2125
				2126	def : SampleRawPattern<int_SI_gather4_o, IMAGE_GATHER4_O_V4_V4, v4i32>;
				2127	def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V4, v4i32>;
				2128	def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8i32>;
				2129	def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V4, v4i32>;
				2130	def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V8, v8i32>;
				2131	def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V4, v4i32>;
				2132	def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V8, v8i32>;
				2133	def : SampleRawPattern<int_SI_gather4_b_cl_o, IMAGE_GATHER4_B_CL_O_V4_V8, v8i32>;
				2134	def : SampleRawPattern<int_SI_gather4_lz_o, IMAGE_GATHER4_LZ_O_V4_V4, v4i32>;
				2135
				2136	def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V4, v4i32>;
				2137	def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V8, v8i32>;
				2138	def : SampleRawPattern<int_SI_gather4_c_cl_o, IMAGE_GATHER4_C_CL_O_V4_V8, v8i32>;
				2139	def : SampleRawPattern<int_SI_gather4_c_l_o, IMAGE_GATHER4_C_L_O_V4_V8, v8i32>;
				2140	def : SampleRawPattern<int_SI_gather4_c_b_o, IMAGE_GATHER4_C_B_O_V4_V8, v8i32>;
				2141	def : SampleRawPattern<int_SI_gather4_c_b_cl_o, IMAGE_GATHER4_C_B_CL_O_V4_V8, v8i32>;
				2142	def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V4, v4i32>;
				2143	def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V8, v8i32>;
				2144
				2145	def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V1, i32>;
				2146	def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V2, v2i32>;
				2147	def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V4, v4i32>;
				2148
Changpeng Fang	fb9c381	2016-08-10 21:15:30 +0000	[diff] [blame]	2149
				2150	// ======= amdgcn Image Intrinsics ==============
				2151
				2152	// Image load
Nicolai Haehnle	f2c64db	2016-02-18 16:44:18 +0000	[diff] [blame]	2153	defm : ImageLoadPatterns<int_amdgcn_image_load, "IMAGE_LOAD">;
				2154	defm : ImageLoadPatterns<int_amdgcn_image_load_mip, "IMAGE_LOAD_MIP">;
Changpeng Fang	fb9c381	2016-08-10 21:15:30 +0000	[diff] [blame]	2155
				2156	// Image store
Nicolai Haehnle	f2c64db	2016-02-18 16:44:18 +0000	[diff] [blame]	2157	defm : ImageStorePatterns<int_amdgcn_image_store, "IMAGE_STORE">;
				2158	defm : ImageStorePatterns<int_amdgcn_image_store_mip, "IMAGE_STORE_MIP">;
Changpeng Fang	fb9c381	2016-08-10 21:15:30 +0000	[diff] [blame]	2159
				2160	// Basic sample
				2161	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample, "IMAGE_SAMPLE">;
				2162	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cl, "IMAGE_SAMPLE_CL">;
				2163	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_d, "IMAGE_SAMPLE_D">;
				2164	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_d_cl, "IMAGE_SAMPLE_D_CL">;
				2165	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_l, "IMAGE_SAMPLE_L">;
				2166	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_b, "IMAGE_SAMPLE_B">;
				2167	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_b_cl, "IMAGE_SAMPLE_B_CL">;
				2168	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_lz, "IMAGE_SAMPLE_LZ">;
				2169	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cd, "IMAGE_SAMPLE_CD">;
				2170	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">;
				2171
				2172	// Sample with comparison
				2173	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c, "IMAGE_SAMPLE_C">;
				2174	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cl, "IMAGE_SAMPLE_C_CL">;
				2175	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_d, "IMAGE_SAMPLE_C_D">;
				2176	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">;
				2177	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_l, "IMAGE_SAMPLE_C_L">;
				2178	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_b, "IMAGE_SAMPLE_C_B">;
				2179	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">;
				2180	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_lz, "IMAGE_SAMPLE_C_LZ">;
				2181	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cd, "IMAGE_SAMPLE_C_CD">;
				2182	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">;
				2183
				2184	// Sample with offsets
				2185	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_o, "IMAGE_SAMPLE_O">;
				2186	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cl_o, "IMAGE_SAMPLE_CL_O">;
				2187	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_d_o, "IMAGE_SAMPLE_D_O">;
				2188	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">;
				2189	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_l_o, "IMAGE_SAMPLE_L_O">;
				2190	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_b_o, "IMAGE_SAMPLE_B_O">;
				2191	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">;
				2192	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_lz_o, "IMAGE_SAMPLE_LZ_O">;
				2193	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cd_o, "IMAGE_SAMPLE_CD_O">;
				2194	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">;
				2195
				2196	// Sample with comparison and offsets
				2197	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_o, "IMAGE_SAMPLE_C_O">;
				2198	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">;
				2199	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">;
				2200	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">;
				2201	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">;
				2202	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">;
				2203	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">;
				2204	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">;
				2205	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">;
				2206	defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">;
				2207
				2208	// Gather opcodes
				2209	// Only the variants which make sense are defined.
				2210	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4, IMAGE_GATHER4_V4_V2, v2f32>;
				2211	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4, IMAGE_GATHER4_V4_V4, v4f32>;
				2212	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_cl, IMAGE_GATHER4_CL_V4_V4, v4f32>;
				2213	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_l, IMAGE_GATHER4_L_V4_V4, v4f32>;
				2214	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_b, IMAGE_GATHER4_B_V4_V4, v4f32>;
				2215	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V4, v4f32>;
				2216	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8f32>;
				2217	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_lz, IMAGE_GATHER4_LZ_V4_V2, v2f32>;
				2218	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_lz, IMAGE_GATHER4_LZ_V4_V4, v4f32>;
				2219
				2220	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c, IMAGE_GATHER4_C_V4_V4, v4f32>;
				2221	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V4, v4f32>;
				2222	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8f32>;
				2223	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_l, IMAGE_GATHER4_C_L_V4_V4, v4f32>;
				2224	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8f32>;
				2225	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_b, IMAGE_GATHER4_C_B_V4_V4, v4f32>;
				2226	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8f32>;
				2227	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8f32>;
				2228	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_lz, IMAGE_GATHER4_C_LZ_V4_V4, v4f32>;
				2229
				2230	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_o, IMAGE_GATHER4_O_V4_V4, v4f32>;
				2231	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V4, v4f32>;
				2232	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8f32>;
				2233	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_l_o, IMAGE_GATHER4_L_O_V4_V4, v4f32>;
				2234	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_l_o, IMAGE_GATHER4_L_O_V4_V8, v8f32>;
				2235	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_b_o, IMAGE_GATHER4_B_O_V4_V4, v4f32>;
				2236	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_b_o, IMAGE_GATHER4_B_O_V4_V8, v8f32>;
				2237	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_b_cl_o, IMAGE_GATHER4_B_CL_O_V4_V8, v8f32>;
				2238	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_lz_o, IMAGE_GATHER4_LZ_O_V4_V4, v4f32>;
				2239
				2240	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_o, IMAGE_GATHER4_C_O_V4_V4, v4f32>;
				2241	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_o, IMAGE_GATHER4_C_O_V4_V8, v8f32>;
				2242	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_cl_o, IMAGE_GATHER4_C_CL_O_V4_V8, v8f32>;
				2243	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_l_o, IMAGE_GATHER4_C_L_O_V4_V8, v8f32>;
				2244	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_b_o, IMAGE_GATHER4_C_B_O_V4_V8, v8f32>;
				2245	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_b_cl_o, IMAGE_GATHER4_C_B_CL_O_V4_V8, v8f32>;
				2246	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V4, v4f32>;
				2247	defm : AMDGCNSamplePattern<int_amdgcn_image_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V8, v8f32>;
				2248
				2249	defm : AMDGCNSamplePattern<int_amdgcn_image_getlod, IMAGE_GET_LOD_V4_V1, f32>;
				2250	defm : AMDGCNSamplePattern<int_amdgcn_image_getlod, IMAGE_GET_LOD_V4_V2, v2f32>;
				2251	defm : AMDGCNSamplePattern<int_amdgcn_image_getlod, IMAGE_GET_LOD_V4_V4, v4f32>;
				2252
				2253	// Image atomics
Nikolay Haustov	5bf46ac1	2016-03-04 10:39:50 +0000	[diff] [blame]	2254	defm : ImageAtomicPatterns<int_amdgcn_image_atomic_swap, "IMAGE_ATOMIC_SWAP">;
				2255	def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V1, i32>;
				2256	def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V2, v2i32>;
				2257	def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V4, v4i32>;
				2258	defm : ImageAtomicPatterns<int_amdgcn_image_atomic_add, "IMAGE_ATOMIC_ADD">;
				2259	defm : ImageAtomicPatterns<int_amdgcn_image_atomic_sub, "IMAGE_ATOMIC_SUB">;
				2260	defm : ImageAtomicPatterns<int_amdgcn_image_atomic_smin, "IMAGE_ATOMIC_SMIN">;
				2261	defm : ImageAtomicPatterns<int_amdgcn_image_atomic_umin, "IMAGE_ATOMIC_UMIN">;
				2262	defm : ImageAtomicPatterns<int_amdgcn_image_atomic_smax, "IMAGE_ATOMIC_SMAX">;
				2263	defm : ImageAtomicPatterns<int_amdgcn_image_atomic_umax, "IMAGE_ATOMIC_UMAX">;
				2264	defm : ImageAtomicPatterns<int_amdgcn_image_atomic_and, "IMAGE_ATOMIC_AND">;
				2265	defm : ImageAtomicPatterns<int_amdgcn_image_atomic_or, "IMAGE_ATOMIC_OR">;
				2266	defm : ImageAtomicPatterns<int_amdgcn_image_atomic_xor, "IMAGE_ATOMIC_XOR">;
				2267	defm : ImageAtomicPatterns<int_amdgcn_image_atomic_inc, "IMAGE_ATOMIC_INC">;
				2268	defm : ImageAtomicPatterns<int_amdgcn_image_atomic_dec, "IMAGE_ATOMIC_DEC">;
Marek Olsak	d8ecaee	2014-07-11 17:11:46 +0000	[diff] [blame]	2269
Tom Stellard	9fa1791	2013-08-14 23:24:45 +0000	[diff] [blame]	2270	/* SIsample for simple 1D texture lookup */
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	2271	def : Pat <
Matt Arsenault	c5f6152	2016-01-26 04:43:48 +0000	[diff] [blame]	2272	(SIsample i32:$addr, v8i32:$rsrc, v4i32:$sampler, imm),
Nikolay Haustov	2f684f1	2016-02-26 09:51:05 +0000	[diff] [blame]	2273	(IMAGE_SAMPLE_V4_V1 $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0)
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	2274	>;
				2275
Tom Stellard	9fa1791	2013-08-14 23:24:45 +0000	[diff] [blame]	2276	class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
Matt Arsenault	c5f6152	2016-01-26 04:43:48 +0000	[diff] [blame]	2277	(name vt:$addr, v8i32:$rsrc, v4i32:$sampler, imm),
Nikolay Haustov	2f684f1	2016-02-26 09:51:05 +0000	[diff] [blame]	2278	(opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0)
Tom Stellard	c9b9031	2013-01-21 15:40:48 +0000	[diff] [blame]	2279	>;
				2280
Tom Stellard	9fa1791	2013-08-14 23:24:45 +0000	[diff] [blame]	2281	class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
Matt Arsenault	c5f6152	2016-01-26 04:43:48 +0000	[diff] [blame]	2282	(name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_RECT),
Nikolay Haustov	2f684f1	2016-02-26 09:51:05 +0000	[diff] [blame]	2283	(opcode $addr, $rsrc, $sampler, 0xf, 1, 0, 0, 0, 0, 0, 0)
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	2284	>;
				2285
Tom Stellard	9fa1791	2013-08-14 23:24:45 +0000	[diff] [blame]	2286	class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
Matt Arsenault	c5f6152	2016-01-26 04:43:48 +0000	[diff] [blame]	2287	(name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_ARRAY),
Nikolay Haustov	2f684f1	2016-02-26 09:51:05 +0000	[diff] [blame]	2288	(opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1)
Tom Stellard	462516b	2013-02-07 17:02:14 +0000	[diff] [blame]	2289	>;
				2290
Tom Stellard	9fa1791	2013-08-14 23:24:45 +0000	[diff] [blame]	2291	class SampleShadowPattern<SDNode name, MIMG opcode,
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2292	ValueType vt> : Pat <
Matt Arsenault	c5f6152	2016-01-26 04:43:48 +0000	[diff] [blame]	2293	(name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW),
Nikolay Haustov	2f684f1	2016-02-26 09:51:05 +0000	[diff] [blame]	2294	(opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0)
Tom Stellard	462516b	2013-02-07 17:02:14 +0000	[diff] [blame]	2295	>;
				2296
Tom Stellard	9fa1791	2013-08-14 23:24:45 +0000	[diff] [blame]	2297	class SampleShadowArrayPattern<SDNode name, MIMG opcode,
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2298	ValueType vt> : Pat <
Matt Arsenault	c5f6152	2016-01-26 04:43:48 +0000	[diff] [blame]	2299	(name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
Nikolay Haustov	2f684f1	2016-02-26 09:51:05 +0000	[diff] [blame]	2300	(opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1)
Tom Stellard	462516b	2013-02-07 17:02:14 +0000	[diff] [blame]	2301	>;
				2302
Tom Stellard	9fa1791	2013-08-14 23:24:45 +0000	[diff] [blame]	2303	/* SIsample* for texture lookups consuming more address parameters */
Tom Stellard	16a9a20	2013-08-14 23:24:17 +0000	[diff] [blame]	2304	multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
				2305	MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
				2306	MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
Tom Stellard	9fa1791	2013-08-14 23:24:45 +0000	[diff] [blame]	2307	def : SamplePattern <SIsample, sample, addr_type>;
				2308	def : SampleRectPattern <SIsample, sample, addr_type>;
				2309	def : SampleArrayPattern <SIsample, sample, addr_type>;
				2310	def : SampleShadowPattern <SIsample, sample_c, addr_type>;
				2311	def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
Tom Stellard	ae6c06e	2013-02-07 17:02:13 +0000	[diff] [blame]	2312
Tom Stellard	9fa1791	2013-08-14 23:24:45 +0000	[diff] [blame]	2313	def : SamplePattern <SIsamplel, sample_l, addr_type>;
				2314	def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
				2315	def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
				2316	def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
Tom Stellard	ae6c06e	2013-02-07 17:02:13 +0000	[diff] [blame]	2317
Tom Stellard	9fa1791	2013-08-14 23:24:45 +0000	[diff] [blame]	2318	def : SamplePattern <SIsampleb, sample_b, addr_type>;
				2319	def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
				2320	def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
				2321	def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
Michel Danzer	83f87c4	2013-07-10 16:36:36 +0000	[diff] [blame]	2322
Tom Stellard	9fa1791	2013-08-14 23:24:45 +0000	[diff] [blame]	2323	def : SamplePattern <SIsampled, sample_d, addr_type>;
				2324	def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
				2325	def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
				2326	def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
Tom Stellard	ae6c06e	2013-02-07 17:02:13 +0000	[diff] [blame]	2327	}
				2328
Tom Stellard	682bfbc	2013-10-10 17:11:24 +0000	[diff] [blame]	2329	defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2,
				2330	IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2,
				2331	IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2,
				2332	IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2,
Tom Stellard	16a9a20	2013-08-14 23:24:17 +0000	[diff] [blame]	2333	v2i32>;
Tom Stellard	682bfbc	2013-10-10 17:11:24 +0000	[diff] [blame]	2334	defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4,
				2335	IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4,
				2336	IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4,
				2337	IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4,
Tom Stellard	16a9a20	2013-08-14 23:24:17 +0000	[diff] [blame]	2338	v4i32>;
Tom Stellard	682bfbc	2013-10-10 17:11:24 +0000	[diff] [blame]	2339	defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8,
				2340	IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8,
				2341	IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8,
				2342	IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8,
Tom Stellard	16a9a20	2013-08-14 23:24:17 +0000	[diff] [blame]	2343	v8i32>;
Tom Stellard	682bfbc	2013-10-10 17:11:24 +0000	[diff] [blame]	2344	defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
				2345	IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16,
				2346	IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16,
				2347	IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
Tom Stellard	16a9a20	2013-08-14 23:24:17 +0000	[diff] [blame]	2348	v16i32>;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	2349
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	2350	/******** ============================================ ********/
				2351	/******** Extraction, Insertion, Building and Casting ********/
				2352	/******** ============================================ ********/
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	2353
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	2354	foreach Index = 0-2 in {
				2355	def Extract_Element_v2i32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2356	i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	2357	>;
				2358	def Insert_Element_v2i32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2359	i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	2360	>;
				2361
				2362	def Extract_Element_v2f32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2363	f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	2364	>;
				2365	def Insert_Element_v2f32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2366	f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	2367	>;
				2368	}
				2369
				2370	foreach Index = 0-3 in {
				2371	def Extract_Element_v4i32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2372	i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	2373	>;
				2374	def Insert_Element_v4i32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2375	i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	2376	>;
				2377
				2378	def Extract_Element_v4f32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2379	f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	2380	>;
				2381	def Insert_Element_v4f32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2382	f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	2383	>;
				2384	}
				2385
				2386	foreach Index = 0-7 in {
				2387	def Extract_Element_v8i32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2388	i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	2389	>;
				2390	def Insert_Element_v8i32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2391	i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	2392	>;
				2393
				2394	def Extract_Element_v8f32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2395	f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	2396	>;
				2397	def Insert_Element_v8f32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2398	f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	2399	>;
				2400	}
				2401
				2402	foreach Index = 0-15 in {
				2403	def Extract_Element_v16i32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2404	i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	2405	>;
				2406	def Insert_Element_v16i32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2407	i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	2408	>;
				2409
				2410	def Extract_Element_v16f32_#Index : Extract_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2411	f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	2412	>;
				2413	def Insert_Element_v16f32_#Index : Insert_Element <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2414	f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
Christian Konig	4a1b9c3	2013-03-18 11:34:10 +0000	[diff] [blame]	2415	>;
				2416	}
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	2417
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	2418	// FIXME: Why do only some of these type combinations for SReg and
				2419	// VReg?
				2420	// 32-bit bitcast
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	2421	def : BitConvert <i32, f32, VGPR_32>;
Tom Stellard	45c0b3a	2015-01-07 20:59:25 +0000	[diff] [blame]	2422	def : BitConvert <f32, i32, VGPR_32>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	2423	def : BitConvert <i32, f32, SReg_32>;
				2424	def : BitConvert <f32, i32, SReg_32>;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	2425
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	2426	// 64-bit bitcast
Tom Stellard	7512c08	2013-07-12 18:14:56 +0000	[diff] [blame]	2427	def : BitConvert <i64, f64, VReg_64>;
Tom Stellard	7512c08	2013-07-12 18:14:56 +0000	[diff] [blame]	2428	def : BitConvert <f64, i64, VReg_64>;
Tom Stellard	ed2f614	2013-07-18 21:43:42 +0000	[diff] [blame]	2429	def : BitConvert <v2i32, v2f32, VReg_64>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	2430	def : BitConvert <v2f32, v2i32, VReg_64>;
Tom Stellard	7ea3d6d	2014-03-31 14:01:55 +0000	[diff] [blame]	2431	def : BitConvert <i64, v2i32, VReg_64>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	2432	def : BitConvert <v2i32, i64, VReg_64>;
Matt Arsenault	064c206	2014-06-11 17:40:32 +0000	[diff] [blame]	2433	def : BitConvert <i64, v2f32, VReg_64>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	2434	def : BitConvert <v2f32, i64, VReg_64>;
Tom Stellard	8f30721	2015-12-15 17:11:17 +0000	[diff] [blame]	2435	def : BitConvert <f64, v2f32, VReg_64>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	2436	def : BitConvert <v2f32, f64, VReg_64>;
Matt Arsenault	2acc7a4	2014-06-11 19:31:13 +0000	[diff] [blame]	2437	def : BitConvert <f64, v2i32, VReg_64>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	2438	def : BitConvert <v2i32, f64, VReg_64>;
Tom Stellard	8374720	2013-07-18 21:43:53 +0000	[diff] [blame]	2439	def : BitConvert <v4i32, v4f32, VReg_128>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	2440	def : BitConvert <v4f32, v4i32, VReg_128>;
Tom Stellard	8374720	2013-07-18 21:43:53 +0000	[diff] [blame]	2441
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	2442	// 128-bit bitcast
Matt Arsenault	61001bb	2015-11-25 19:58:34 +0000	[diff] [blame]	2443	def : BitConvert <v2i64, v4i32, SReg_128>;
				2444	def : BitConvert <v4i32, v2i64, SReg_128>;
Tom Stellard	8f30721	2015-12-15 17:11:17 +0000	[diff] [blame]	2445	def : BitConvert <v2f64, v4f32, VReg_128>;
Matt Arsenault	61001bb	2015-11-25 19:58:34 +0000	[diff] [blame]	2446	def : BitConvert <v2f64, v4i32, VReg_128>;
Tom Stellard	8f30721	2015-12-15 17:11:17 +0000	[diff] [blame]	2447	def : BitConvert <v4f32, v2f64, VReg_128>;
Matt Arsenault	61001bb	2015-11-25 19:58:34 +0000	[diff] [blame]	2448	def : BitConvert <v4i32, v2f64, VReg_128>;
Matt Arsenault	e57206d	2016-05-25 18:07:36 +0000	[diff] [blame]	2449	def : BitConvert <v2i64, v2f64, VReg_128>;
				2450	def : BitConvert <v2f64, v2i64, VReg_128>;
Matt Arsenault	61001bb	2015-11-25 19:58:34 +0000	[diff] [blame]	2451
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	2452	// 256-bit bitcast
Tom Stellard	967bf58	2014-02-13 23:34:15 +0000	[diff] [blame]	2453	def : BitConvert <v8i32, v8f32, SReg_256>;
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	2454	def : BitConvert <v8f32, v8i32, SReg_256>;
Matt Arsenault	f5958dd	2014-02-02 00:05:35 +0000	[diff] [blame]	2455	def : BitConvert <v8i32, v8f32, VReg_256>;
				2456	def : BitConvert <v8f32, v8i32, VReg_256>;
Tom Stellard	20ee94f	2013-08-14 22:22:09 +0000	[diff] [blame]	2457
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	2458	// 512-bit bitcast
Matt Arsenault	f5958dd	2014-02-02 00:05:35 +0000	[diff] [blame]	2459	def : BitConvert <v16i32, v16f32, VReg_512>;
				2460	def : BitConvert <v16f32, v16i32, VReg_512>;
				2461
Christian Konig	8dbe6f6	2013-02-21 15:17:27 +0000	[diff] [blame]	2462	/******** =================== ********/
				2463	/******** Src & Dst modifiers ********/
				2464	/******** =================== ********/
				2465
				2466	def : Pat <
Matt Arsenault	1cffa4c	2014-11-13 19:49:04 +0000	[diff] [blame]	2467	(AMDGPUclamp (VOP3Mods0Clamp f32:$src0, i32:$src0_modifiers, i32:$omod),
				2468	(f32 FP_ZERO), (f32 FP_ONE)),
				2469	(V_ADD_F32_e64 $src0_modifiers, $src0, 0, 0, 1, $omod)
Christian Konig	8dbe6f6	2013-02-21 15:17:27 +0000	[diff] [blame]	2470	>;
				2471
Michel Danzer	624b02a	2014-02-04 07:12:38 +0000	[diff] [blame]	2472	/******** ================================ ********/
				2473	/******** Floating point absolute/negative ********/
				2474	/******** ================================ ********/
				2475
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	2476	// Prevent expanding both fneg and fabs.
Michel Danzer	624b02a	2014-02-04 07:12:38 +0000	[diff] [blame]	2477
Michel Danzer	624b02a	2014-02-04 07:12:38 +0000	[diff] [blame]	2478	def : Pat <
				2479	(fneg (fabs f32:$src)),
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	2480	(S_OR_B32 $src, 0x80000000) // Set sign bit
Michel Danzer	624b02a	2014-02-04 07:12:38 +0000	[diff] [blame]	2481	>;
				2482
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	2483	// FIXME: Should use S_OR_B32
Matt Arsenault	13623d0	2014-08-15 18:42:18 +0000	[diff] [blame]	2484	def : Pat <
				2485	(fneg (fabs f64:$src)),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2486	(REG_SEQUENCE VReg_64,
				2487	(i32 (EXTRACT_SUBREG f64:$src, sub0)),
				2488	sub0,
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	2489	(V_OR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2490	(V_MOV_B32_e32 0x80000000)), // Set sign bit.
				2491	sub1)
Matt Arsenault	13623d0	2014-08-15 18:42:18 +0000	[diff] [blame]	2492	>;
				2493
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	2494	def : Pat <
				2495	(fabs f32:$src),
				2496	(V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff))
				2497	>;
Vincent Lejeune	79a5834	2014-05-10 19:18:25 +0000	[diff] [blame]	2498
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	2499	def : Pat <
				2500	(fneg f32:$src),
				2501	(V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000))
				2502	>;
Christian Konig	8dbe6f6	2013-02-21 15:17:27 +0000	[diff] [blame]	2503
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	2504	def : Pat <
				2505	(fabs f64:$src),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2506	(REG_SEQUENCE VReg_64,
				2507	(i32 (EXTRACT_SUBREG f64:$src, sub0)),
				2508	sub0,
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	2509	(V_AND_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2510	(V_MOV_B32_e32 0x7fffffff)), // Set sign bit.
				2511	sub1)
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	2512	>;
Vincent Lejeune	79a5834	2014-05-10 19:18:25 +0000	[diff] [blame]	2513
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	2514	def : Pat <
				2515	(fneg f64:$src),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2516	(REG_SEQUENCE VReg_64,
				2517	(i32 (EXTRACT_SUBREG f64:$src, sub0)),
				2518	sub0,
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	2519	(V_XOR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2520	(V_MOV_B32_e32 0x80000000)),
				2521	sub1)
Matt Arsenault	fabf545	2014-08-15 18:42:22 +0000	[diff] [blame]	2522	>;
Christian Konig	8dbe6f6	2013-02-21 15:17:27 +0000	[diff] [blame]	2523
Christian Konig	c756cb99	2013-02-16 11:28:22 +0000	[diff] [blame]	2524	/******** ================== ********/
				2525	/******** Immediate Patterns ********/
				2526	/******** ================== ********/
				2527
				2528	def : Pat <
Tom Stellard	df94dc3	2013-08-14 23:24:24 +0000	[diff] [blame]	2529	(SGPRImm<(i32 imm)>:$imm),
				2530	(S_MOV_B32 imm:$imm)
				2531	>;
				2532
				2533	def : Pat <
				2534	(SGPRImm<(f32 fpimm)>:$imm),
Tom Stellard	fb77f00	2015-01-13 22:59:41 +0000	[diff] [blame]	2535	(S_MOV_B32 (f32 (bitcast_fpimm_to_i32 $imm)))
Tom Stellard	df94dc3	2013-08-14 23:24:24 +0000	[diff] [blame]	2536	>;
				2537
				2538	def : Pat <
Christian Konig	c756cb99	2013-02-16 11:28:22 +0000	[diff] [blame]	2539	(i32 imm:$imm),
				2540	(V_MOV_B32_e32 imm:$imm)
				2541	>;
				2542
				2543	def : Pat <
				2544	(f32 fpimm:$imm),
Tom Stellard	fb77f00	2015-01-13 22:59:41 +0000	[diff] [blame]	2545	(V_MOV_B32_e32 (f32 (bitcast_fpimm_to_i32 $imm)))
Christian Konig	c756cb99	2013-02-16 11:28:22 +0000	[diff] [blame]	2546	>;
				2547
				2548	def : Pat <
Christian Konig	b559b07	2013-02-16 11:28:36 +0000	[diff] [blame]	2549	(i64 InlineImm<i64>:$imm),
				2550	(S_MOV_B64 InlineImm<i64>:$imm)
				2551	>;
				2552
Matt Arsenault	becd656	2014-12-03 05:22:35 +0000	[diff] [blame]	2553	// XXX - Should this use a s_cmp to set SCC?
				2554
				2555	// Set to sign-extended 64-bit value (true = -1, false = 0)
				2556	def : Pat <
				2557	(i1 imm:$imm),
				2558	(S_MOV_B64 (i64 (as_i64imm $imm)))
				2559	>;
				2560
Matt Arsenault	303011a	2014-12-17 21:04:08 +0000	[diff] [blame]	2561	def : Pat <
				2562	(f64 InlineFPImm<f64>:$imm),
Tom Stellard	fb77f00	2015-01-13 22:59:41 +0000	[diff] [blame]	2563	(S_MOV_B64 (f64 (bitcast_fpimm_to_i64 InlineFPImm<f64>:$imm)))
Matt Arsenault	303011a	2014-12-17 21:04:08 +0000	[diff] [blame]	2564	>;
				2565
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	2566	/******** ================== ********/
				2567	/******** Intrinsic Patterns ********/
				2568	/******** ================== ********/
				2569
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2570	def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	2571
				2572	def : Pat <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2573	(int_AMDGPU_cube v4f32:$src),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2574	(REG_SEQUENCE VReg_128,
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	2575	(V_CUBETC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
				2576	0 /* src1_modifiers */, (EXTRACT_SUBREG $src, sub1),
				2577	0 /* src2_modifiers */, (EXTRACT_SUBREG $src, sub2),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2578	0 /* clamp /, 0 / omod */), sub0,
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	2579	(V_CUBESC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
				2580	0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
				2581	0 /* src2_modifiers */,(EXTRACT_SUBREG $src, sub2),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2582	0 /* clamp /, 0 / omod */), sub1,
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	2583	(V_CUBEMA_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
				2584	0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
				2585	0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2586	0 /* clamp /, 0 / omod */), sub2,
Tom Stellard	b4a313a	2014-08-01 00:32:39 +0000	[diff] [blame]	2587	(V_CUBEID_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
				2588	0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
				2589	0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2590	0 /* clamp /, 0 / omod */), sub3)
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	2591	>;
				2592
Michel Danzer	0cc991e	2013-02-22 11:22:58 +0000	[diff] [blame]	2593	def : Pat <
Tom Stellard	40b7f1f	2013-05-02 15:30:12 +0000	[diff] [blame]	2594	(i32 (sext i1:$src0)),
				2595	(V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
Michel Danzer	0cc991e	2013-02-22 11:22:58 +0000	[diff] [blame]	2596	>;
				2597
Tom Stellard	f16d38c	2014-02-13 23:34:13 +0000	[diff] [blame]	2598	class Ext32Pat <SDNode ext> : Pat <
				2599	(i32 (ext i1:$src0)),
Michel Danzer	5d26fdf	2014-02-05 09:48:05 +0000	[diff] [blame]	2600	(V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
				2601	>;
				2602
Tom Stellard	f16d38c	2014-02-13 23:34:13 +0000	[diff] [blame]	2603	def : Ext32Pat <zext>;
				2604	def : Ext32Pat <anyext>;
				2605
Matt Arsenault	382d945	2016-01-26 04:49:22 +0000	[diff] [blame]	2606	// Offset in an 32-bit VGPR
Christian Konig	7a14a47	2013-03-18 11:34:00 +0000	[diff] [blame]	2607	def : Pat <
Tom Stellard	868fd92	2014-04-17 21:00:11 +0000	[diff] [blame]	2608	(SIload_constant v4i32:$sbase, i32:$voff),
Tom Stellard	c229baa	2015-03-10 16:16:49 +0000	[diff] [blame]	2609	(BUFFER_LOAD_DWORD_OFFEN $voff, $sbase, 0, 0, 0, 0, 0)
Christian Konig	7a14a47	2013-03-18 11:34:00 +0000	[diff] [blame]	2610	>;
				2611
Michel Danzer	8caa904	2013-04-10 17:17:56 +0000	[diff] [blame]	2612	// The multiplication scales from [0,1] to the unsigned integer range
				2613	def : Pat <
				2614	(AMDGPUurecip i32:$src0),
				2615	(V_CVT_U32_F32_e32
				2616	(V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
				2617	(V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
				2618	>;
				2619
Tom Stellard	0289ff4	2014-05-16 20:56:44 +0000	[diff] [blame]	2620	//===----------------------------------------------------------------------===//
				2621	// VOP3 Patterns
				2622	//===----------------------------------------------------------------------===//
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	2623
Matt Arsenault	eb26020	2014-05-22 18:00:15 +0000	[diff] [blame]	2624	def : IMad24Pat<V_MAD_I32_I24>;
				2625	def : UMad24Pat<V_MAD_U32_U24>;
				2626
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2627	defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>;
Tom Stellard	0289ff4	2014-05-16 20:56:44 +0000	[diff] [blame]	2628	def : ROTRPattern <V_ALIGNBIT_B32>;
				2629
Tom Stellard	556d9aa	2013-06-03 17:39:37 +0000	[diff] [blame]	2630	//===----------------------------------------------------------------------===//
				2631	// MUBUF Patterns
				2632	//===----------------------------------------------------------------------===//
				2633
Jan Vesely	43b7b5b	2016-04-07 19:23:11 +0000	[diff] [blame]	2634	class MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
				2635	PatFrag constant_ld> : Pat <
Tom Stellard	1f9939f	2015-02-27 14:59:41 +0000	[diff] [blame]	2636	(vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
				2637	i16:$offset, i1:$glc, i1:$slc, i1:$tfe))),
Tom Stellard	c229baa	2015-03-10 16:16:49 +0000	[diff] [blame]	2638	(Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, $glc, $slc, $tfe)
Tom Stellard	07a10a3	2013-06-03 17:39:43 +0000	[diff] [blame]	2639	>;
Jan Vesely	43b7b5b	2016-04-07 19:23:11 +0000	[diff] [blame]	2640
				2641	multiclass MUBUFLoad_Atomic_Pattern <MUBUF Instr_ADDR64, MUBUF Instr_OFFSET,
				2642	ValueType vt, PatFrag atomic_ld> {
				2643	def : Pat <
				2644	(vt (atomic_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
				2645	i16:$offset, i1:$slc))),
				2646	(Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, 1, $slc, 0)
				2647	>;
				2648
				2649	def : Pat <
				2650	(vt (atomic_ld (MUBUFOffsetNoGLC v4i32:$rsrc, i32:$soffset, i16:$offset))),
				2651	(Instr_OFFSET $rsrc, $soffset, (as_i16imm $offset), 1, 0, 0)
				2652	>;
Tom Stellard	07a10a3	2013-06-03 17:39:43 +0000	[diff] [blame]	2653	}
				2654
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	2655	let Predicates = [isSICI] in {
Jan Vesely	43b7b5b	2016-04-07 19:23:11 +0000	[diff] [blame]	2656	def : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>;
				2657	def : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>;
				2658	def : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>;
				2659	def : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>;
				2660
				2661	defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORD_ADDR64, BUFFER_LOAD_DWORD_OFFSET, i32, mubuf_load_atomic>;
				2662	defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, BUFFER_LOAD_DWORDX2_OFFSET, i64, mubuf_load_atomic>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	2663	} // End Predicates = [isSICI]
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	2664
				2665	class MUBUFScratchLoadPat <MUBUF Instr, ValueType vt, PatFrag ld> : Pat <
				2666	(vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr,
				2667	i32:$soffset, u16imm:$offset))),
Tom Stellard	c229baa	2015-03-10 16:16:49 +0000	[diff] [blame]	2668	(Instr $vaddr, $srsrc, $soffset, $offset, 0, 0, 0)
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	2669	>;
				2670
				2671	def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i32, sextloadi8_private>;
				2672	def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i32, extloadi8_private>;
				2673	def : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, i32, sextloadi16_private>;
				2674	def : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, i32, extloadi16_private>;
				2675	def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORD_OFFEN, i32, load_private>;
				2676	def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, v2i32, load_private>;
				2677	def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, v4i32, load_private>;
Tom Stellard	07a10a3	2013-06-03 17:39:43 +0000	[diff] [blame]	2678
Michel Danzer	1373622	2014-01-27 07:20:51 +0000	[diff] [blame]	2679	// BUFFER_LOAD_DWORD*, addr64=0
				2680	multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
				2681	MUBUF bothen> {
				2682
				2683	def : Pat <
Tom Stellard	8e44d94	2014-07-21 15:44:55 +0000	[diff] [blame]	2684	(vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset,
Michel Danzer	1373622	2014-01-27 07:20:51 +0000	[diff] [blame]	2685	imm:$offset, 0, 0, imm:$glc, imm:$slc,
				2686	imm:$tfe)),
Tom Stellard	49282c9	2015-02-27 14:59:44 +0000	[diff] [blame]	2687	(offset $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc),
Michel Danzer	1373622	2014-01-27 07:20:51 +0000	[diff] [blame]	2688	(as_i1imm $slc), (as_i1imm $tfe))
				2689	>;
				2690
				2691	def : Pat <
Tom Stellard	868fd92	2014-04-17 21:00:11 +0000	[diff] [blame]	2692	(vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	2693	imm:$offset, 1, 0, imm:$glc, imm:$slc,
Michel Danzer	1373622	2014-01-27 07:20:51 +0000	[diff] [blame]	2694	imm:$tfe)),
Tom Stellard	c229baa	2015-03-10 16:16:49 +0000	[diff] [blame]	2695	(offen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
Michel Danzer	1373622	2014-01-27 07:20:51 +0000	[diff] [blame]	2696	(as_i1imm $tfe))
				2697	>;
				2698
				2699	def : Pat <
Tom Stellard	868fd92	2014-04-17 21:00:11 +0000	[diff] [blame]	2700	(vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
Michel Danzer	1373622	2014-01-27 07:20:51 +0000	[diff] [blame]	2701	imm:$offset, 0, 1, imm:$glc, imm:$slc,
				2702	imm:$tfe)),
Tom Stellard	c229baa	2015-03-10 16:16:49 +0000	[diff] [blame]	2703	(idxen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc),
Michel Danzer	1373622	2014-01-27 07:20:51 +0000	[diff] [blame]	2704	(as_i1imm $slc), (as_i1imm $tfe))
				2705	>;
				2706
				2707	def : Pat <
Tom Stellard	868fd92	2014-04-17 21:00:11 +0000	[diff] [blame]	2708	(vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset,
Matt Arsenault	caa1288	2015-02-18 02:04:38 +0000	[diff] [blame]	2709	imm:$offset, 1, 1, imm:$glc, imm:$slc,
Michel Danzer	1373622	2014-01-27 07:20:51 +0000	[diff] [blame]	2710	imm:$tfe)),
Tom Stellard	c229baa	2015-03-10 16:16:49 +0000	[diff] [blame]	2711	(bothen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
Michel Danzer	1373622	2014-01-27 07:20:51 +0000	[diff] [blame]	2712	(as_i1imm $tfe))
				2713	>;
				2714	}
				2715
				2716	defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
				2717	BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
				2718	defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
				2719	BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
				2720	defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
				2721	BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
				2722
Jan Vesely	43b7b5b	2016-04-07 19:23:11 +0000	[diff] [blame]	2723	multiclass MUBUFStore_Atomic_Pattern <MUBUF Instr_ADDR64, MUBUF Instr_OFFSET,
				2724	ValueType vt, PatFrag atomic_st> {
				2725	// Store follows atomic op convention so address is forst
				2726	def : Pat <
				2727	(atomic_st (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
				2728	i16:$offset, i1:$slc), vt:$val),
				2729	(Instr_ADDR64 $val, $vaddr, $srsrc, $soffset, $offset, 1, $slc, 0)
				2730	>;
				2731
				2732	def : Pat <
				2733	(atomic_st (MUBUFOffsetNoGLC v4i32:$rsrc, i32:$soffset, i16:$offset), vt:$val),
				2734	(Instr_OFFSET $val, $rsrc, $soffset, (as_i16imm $offset), 1, 0, 0)
				2735	>;
				2736	}
				2737	let Predicates = [isSICI] in {
				2738	defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORD_ADDR64, BUFFER_STORE_DWORD_OFFSET, i32, global_store_atomic>;
				2739	defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORDX2_ADDR64, BUFFER_STORE_DWORDX2_OFFSET, i64, global_store_atomic>;
				2740	} // End Predicates = [isSICI]
				2741
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	2742	class MUBUFScratchStorePat <MUBUF Instr, ValueType vt, PatFrag st> : Pat <
Tom Stellard	ddea486	2014-08-11 22:18:14 +0000	[diff] [blame]	2743	(st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset,
				2744	u16imm:$offset)),
Tom Stellard	c229baa	2015-03-10 16:16:49 +0000	[diff] [blame]	2745	(Instr $value, $vaddr, $srsrc, $soffset, $offset, 0, 0, 0)
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	2746	>;
				2747
Tom Stellard	ddea486	2014-08-11 22:18:14 +0000	[diff] [blame]	2748	def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i32, truncstorei8_private>;
				2749	def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i32, truncstorei16_private>;
				2750	def : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, i32, store_private>;
				2751	def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, v2i32, store_private>;
				2752	def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, v4i32, store_private>;
Tom Stellard	b02094e	2014-07-21 15:45:01 +0000	[diff] [blame]	2753
Tom Stellard	afcf12f	2013-09-12 02:55:14 +0000	[diff] [blame]	2754	//===----------------------------------------------------------------------===//
				2755	// MTBUF Patterns
				2756	//===----------------------------------------------------------------------===//
				2757
				2758	// TBUFFER_STORE_FORMAT_*, addr64=0
				2759	class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
Tom Stellard	868fd92	2014-04-17 21:00:11 +0000	[diff] [blame]	2760	(SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
Tom Stellard	afcf12f	2013-09-12 02:55:14 +0000	[diff] [blame]	2761	i32:$soffset, imm:$inst_offset, imm:$dfmt,
				2762	imm:$nfmt, imm:$offen, imm:$idxen,
				2763	imm:$glc, imm:$slc, imm:$tfe),
				2764	(opcode
				2765	$vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
				2766	(as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
				2767	(as_i1imm $slc), (as_i1imm $tfe), $soffset)
				2768	>;
				2769
				2770	def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
				2771	def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
				2772	def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
				2773	def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
				2774
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	2775	/******** ====================== ********/
				2776	/******** Indirect adressing ********/
				2777	/******** ====================== ********/
				2778
Matt Arsenault	2841927	2015-10-07 00:42:51 +0000	[diff] [blame]	2779	multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, string VecSize> {
Matt Arsenault	1322b6f	2016-07-09 01:13:56 +0000	[diff] [blame]	2780	// Extract with offset
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	2781	def : Pat<
Nicolai Haehnle	7968c34	2016-07-12 08:12:16 +0000	[diff] [blame]	2782	(eltvt (extractelt vt:$src, (MOVRELOffset i32:$idx, (i32 imm:$offset)))),
Matt Arsenault	1322b6f	2016-07-09 01:13:56 +0000	[diff] [blame]	2783	(!cast<Instruction>("SI_INDIRECT_SRC_"#VecSize) $src, $idx, imm:$offset)
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	2784	>;
				2785
Matt Arsenault	1322b6f	2016-07-09 01:13:56 +0000	[diff] [blame]	2786	// Insert with offset
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	2787	def : Pat<
Nicolai Haehnle	7968c34	2016-07-12 08:12:16 +0000	[diff] [blame]	2788	(insertelt vt:$src, eltvt:$val, (MOVRELOffset i32:$idx, (i32 imm:$offset))),
Matt Arsenault	1322b6f	2016-07-09 01:13:56 +0000	[diff] [blame]	2789	(!cast<Instruction>("SI_INDIRECT_DST_"#VecSize) $src, $idx, imm:$offset, $val)
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	2790	>;
				2791	}
				2792
Matt Arsenault	2841927	2015-10-07 00:42:51 +0000	[diff] [blame]	2793	defm : SI_INDIRECT_Pattern <v2f32, f32, "V2">;
				2794	defm : SI_INDIRECT_Pattern <v4f32, f32, "V4">;
				2795	defm : SI_INDIRECT_Pattern <v8f32, f32, "V8">;
				2796	defm : SI_INDIRECT_Pattern <v16f32, f32, "V16">;
Matt Arsenault	f5958dd	2014-02-02 00:05:35 +0000	[diff] [blame]	2797
Matt Arsenault	2841927	2015-10-07 00:42:51 +0000	[diff] [blame]	2798	defm : SI_INDIRECT_Pattern <v2i32, i32, "V2">;
				2799	defm : SI_INDIRECT_Pattern <v4i32, i32, "V4">;
				2800	defm : SI_INDIRECT_Pattern <v8i32, i32, "V8">;
				2801	defm : SI_INDIRECT_Pattern <v16i32, i32, "V16">;
Christian Konig	2989ffc	2013-03-18 11:34:16 +0000	[diff] [blame]	2802
Tom Stellard	81d871d	2013-11-13 23:36:50 +0000	[diff] [blame]	2803	//===----------------------------------------------------------------------===//
Wei Ding	1041a64	2016-08-24 14:59:47 +0000	[diff] [blame]	2804	// SAD Patterns
				2805	//===----------------------------------------------------------------------===//
				2806
				2807	def : Pat <
				2808	(add (sub_oneuse (umax i32:$src0, i32:$src1),
				2809	(umin i32:$src0, i32:$src1)),
				2810	i32:$src2),
				2811	(V_SAD_U32 $src0, $src1, $src2)
				2812	>;
				2813
				2814	def : Pat <
				2815	(add (select_oneuse (i1 (setugt i32:$src0, i32:$src1)),
				2816	(sub i32:$src0, i32:$src1),
				2817	(sub i32:$src1, i32:$src0)),
				2818	i32:$src2),
				2819	(V_SAD_U32 $src0, $src1, $src2)
				2820	>;
				2821
				2822	//===----------------------------------------------------------------------===//
Matt Arsenault	5dbd5db	2014-04-22 03:49:30 +0000	[diff] [blame]	2823	// Conversion Patterns
				2824	//===----------------------------------------------------------------------===//
				2825
				2826	def : Pat<(i32 (sext_inreg i32:$src, i1)),
				2827	(S_BFE_I32 i32:$src, 65536)>; // 0 \| 1 << 16
				2828
Matt Arsenault	5dbd5db	2014-04-22 03:49:30 +0000	[diff] [blame]	2829	// Handle sext_inreg in i64
				2830	def : Pat <
				2831	(i64 (sext_inreg i64:$src, i1)),
Matt Arsenault	9481221	2014-11-14 18:18:16 +0000	[diff] [blame]	2832	(S_BFE_I64 i64:$src, 0x10000) // 0 \| 1 << 16
Matt Arsenault	5dbd5db	2014-04-22 03:49:30 +0000	[diff] [blame]	2833	>;
				2834
				2835	def : Pat <
				2836	(i64 (sext_inreg i64:$src, i8)),
Matt Arsenault	9481221	2014-11-14 18:18:16 +0000	[diff] [blame]	2837	(S_BFE_I64 i64:$src, 0x80000) // 0 \| 8 << 16
Matt Arsenault	5dbd5db	2014-04-22 03:49:30 +0000	[diff] [blame]	2838	>;
				2839
				2840	def : Pat <
				2841	(i64 (sext_inreg i64:$src, i16)),
Matt Arsenault	9481221	2014-11-14 18:18:16 +0000	[diff] [blame]	2842	(S_BFE_I64 i64:$src, 0x100000) // 0 \| 16 << 16
				2843	>;
				2844
				2845	def : Pat <
				2846	(i64 (sext_inreg i64:$src, i32)),
				2847	(S_BFE_I64 i64:$src, 0x200000) // 0 \| 32 << 16
Matt Arsenault	5dbd5db	2014-04-22 03:49:30 +0000	[diff] [blame]	2848	>;
				2849
Matt Arsenault	c6b69a9	2016-07-26 23:06:33 +0000	[diff] [blame]	2850	def : Pat <
				2851	(i64 (zext i32:$src)),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2852	(REG_SEQUENCE SReg_64, $src, sub0, (S_MOV_B32 0), sub1)
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	2853	>;
				2854
Matt Arsenault	c6b69a9	2016-07-26 23:06:33 +0000	[diff] [blame]	2855	def : Pat <
				2856	(i64 (anyext i32:$src)),
				2857	(REG_SEQUENCE SReg_64, $src, sub0, (i32 (IMPLICIT_DEF)), sub1)
				2858	>;
				2859
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	2860	class ZExt_i64_i1_Pat <SDNode ext> : Pat <
				2861	(i64 (ext i1:$src)),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2862	(REG_SEQUENCE VReg_64,
				2863	(V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0,
				2864	(S_MOV_B32 0), sub1)
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	2865	>;
				2866
				2867
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	2868	def : ZExt_i64_i1_Pat<zext>;
				2869	def : ZExt_i64_i1_Pat<anyext>;
				2870
Tom Stellard	bc4497b	2016-02-12 23:45:29 +0000	[diff] [blame]	2871	// FIXME: We need to use COPY_TO_REGCLASS to work-around the fact that
				2872	// REG_SEQUENCE patterns don't support instructions with multiple outputs.
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	2873	def : Pat <
				2874	(i64 (sext i32:$src)),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2875	(REG_SEQUENCE SReg_64, $src, sub0,
Artem Tamazov	38e496b	2016-04-29 17:04:50 +0000	[diff] [blame]	2876	(i32 (COPY_TO_REGCLASS (S_ASHR_I32 $src, 31), SReg_32_XM0)), sub1)
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	2877	>;
				2878
				2879	def : Pat <
				2880	(i64 (sext i1:$src)),
Matt Arsenault	7d858d8	2014-11-02 23:46:54 +0000	[diff] [blame]	2881	(REG_SEQUENCE VReg_64,
				2882	(V_CNDMASK_B32_e64 0, -1, $src), sub0,
Matt Arsenault	b2cbf79	2014-06-10 18:54:59 +0000	[diff] [blame]	2883	(V_CNDMASK_B32_e64 0, -1, $src), sub1)
				2884	>;
				2885
Matt Arsenault	7fb961f	2016-07-22 17:01:21 +0000	[diff] [blame]	2886	class FPToI1Pat<Instruction Inst, int KOne, ValueType vt, SDPatternOperator fp_to_int> : Pat <
				2887	(i1 (fp_to_int (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)))),
				2888	(i1 (Inst 0, KOne, $src0_modifiers, $src0, DSTCLAMP.NONE, DSTOMOD.NONE))
				2889	>;
				2890
				2891	def : FPToI1Pat<V_CMP_EQ_F32_e64, CONST.FP32_ONE, f32, fp_to_uint>;
				2892	def : FPToI1Pat<V_CMP_EQ_F32_e64, CONST.FP32_NEG_ONE, f32, fp_to_sint>;
				2893	def : FPToI1Pat<V_CMP_EQ_F64_e64, CONST.FP64_ONE, f64, fp_to_uint>;
				2894	def : FPToI1Pat<V_CMP_EQ_F64_e64, CONST.FP64_NEG_ONE, f64, fp_to_sint>;
				2895
Matt Arsenault	becd656	2014-12-03 05:22:35 +0000	[diff] [blame]	2896	// If we need to perform a logical operation on i1 values, we need to
				2897	// use vector comparisons since there is only one SCC register. Vector
				2898	// comparisions still write to a pair of SGPRs, so treat these as
				2899	// 64-bit comparisons. When legalizing SGPR copies, instructions
				2900	// resulting in the copies from SCC to these instructions will be
				2901	// moved to the VALU.
				2902	def : Pat <
				2903	(i1 (and i1:$src0, i1:$src1)),
				2904	(S_AND_B64 $src0, $src1)
				2905	>;
				2906
				2907	def : Pat <
				2908	(i1 (or i1:$src0, i1:$src1)),
				2909	(S_OR_B64 $src0, $src1)
				2910	>;
				2911
				2912	def : Pat <
				2913	(i1 (xor i1:$src0, i1:$src1)),
				2914	(S_XOR_B64 $src0, $src1)
				2915	>;
				2916
Matt Arsenault	aeca2fa	2014-05-31 06:47:42 +0000	[diff] [blame]	2917	def : Pat <
				2918	(f32 (sint_to_fp i1:$src)),
				2919	(V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src)
				2920	>;
				2921
				2922	def : Pat <
				2923	(f32 (uint_to_fp i1:$src)),
				2924	(V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src)
				2925	>;
				2926
				2927	def : Pat <
				2928	(f64 (sint_to_fp i1:$src)),
Matt Arsenault	becd656	2014-12-03 05:22:35 +0000	[diff] [blame]	2929	(V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src))
Matt Arsenault	aeca2fa	2014-05-31 06:47:42 +0000	[diff] [blame]	2930	>;
				2931
				2932	def : Pat <
				2933	(f64 (uint_to_fp i1:$src)),
				2934	(V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src))
				2935	>;
				2936
Matt Arsenault	5dbd5db	2014-04-22 03:49:30 +0000	[diff] [blame]	2937	//===----------------------------------------------------------------------===//
Tom Stellard	fb96169	2013-10-23 00:44:19 +0000	[diff] [blame]	2938	// Miscellaneous Patterns
				2939	//===----------------------------------------------------------------------===//
				2940
				2941	def : Pat <
Tom Stellard	81d871d	2013-11-13 23:36:50 +0000	[diff] [blame]	2942	(i32 (trunc i64:$a)),
				2943	(EXTRACT_SUBREG $a, sub0)
				2944	>;
				2945
Michel Danzer	bf1a641	2014-01-28 03:01:16 +0000	[diff] [blame]	2946	def : Pat <
				2947	(i1 (trunc i32:$a)),
Marek Olsak	f924dd6	2015-10-29 15:05:03 +0000	[diff] [blame]	2948	(V_CMP_EQ_I32_e64 (S_AND_B32 (i32 1), $a), 1)
Michel Danzer	bf1a641	2014-01-28 03:01:16 +0000	[diff] [blame]	2949	>;
				2950
Matt Arsenault	e306a32	2014-10-21 16:25:08 +0000	[diff] [blame]	2951	def : Pat <
Matt Arsenault	abd271b	2015-02-05 06:05:13 +0000	[diff] [blame]	2952	(i1 (trunc i64:$a)),
Marek Olsak	f924dd6	2015-10-29 15:05:03 +0000	[diff] [blame]	2953	(V_CMP_EQ_I32_e64 (S_AND_B32 (i32 1),
Matt Arsenault	abd271b	2015-02-05 06:05:13 +0000	[diff] [blame]	2954	(EXTRACT_SUBREG $a, sub0)), 1)
				2955	>;
				2956
				2957	def : Pat <
Matt Arsenault	e306a32	2014-10-21 16:25:08 +0000	[diff] [blame]	2958	(i32 (bswap i32:$a)),
				2959	(V_BFI_B32 (S_MOV_B32 0x00ff00ff),
				2960	(V_ALIGNBIT_B32 $a, $a, 24),
				2961	(V_ALIGNBIT_B32 $a, $a, 8))
				2962	>;
				2963
Matt Arsenault	477b1782	2014-12-12 02:30:29 +0000	[diff] [blame]	2964	def : Pat <
				2965	(f32 (select i1:$src2, f32:$src1, f32:$src0)),
				2966	(V_CNDMASK_B32_e64 $src0, $src1, $src2)
				2967	>;
				2968
Marek Olsak	63a7b08	2015-03-24 13:40:21 +0000	[diff] [blame]	2969	multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> {
				2970	def : Pat <
				2971	(vt (shl (vt (add (vt (shl 1, vt:$a)), -1)), vt:$b)),
				2972	(BFM $a, $b)
				2973	>;
				2974
				2975	def : Pat <
				2976	(vt (add (vt (shl 1, vt:$a)), -1)),
				2977	(BFM $a, (MOV 0))
				2978	>;
				2979	}
				2980
				2981	defm : BFMPatterns <i32, S_BFM_B32, S_MOV_B32>;
				2982	// FIXME: defm : BFMPatterns <i64, S_BFM_B64, S_MOV_B64>;
				2983
Marek Olsak	949f5da	2015-03-24 13:40:34 +0000	[diff] [blame]	2984	def : BFEPattern <V_BFE_U32, S_MOV_B32>;
				2985
Matt Arsenault	61738cb	2016-02-27 08:53:46 +0000	[diff] [blame]	2986	let Predicates = [isSICI] in {
				2987	def : Pat <
				2988	(i64 (readcyclecounter)),
				2989	(S_MEMTIME)
				2990	>;
				2991	}
				2992
Matt Arsenault	9cd9071	2016-04-14 01:42:16 +0000	[diff] [blame]	2993	def : Pat<
				2994	(fcanonicalize f32:$src),
				2995	(V_MUL_F32_e64 0, CONST.FP32_ONE, 0, $src, 0, 0)
				2996	>;
				2997
				2998	def : Pat<
				2999	(fcanonicalize f64:$src),
				3000	(V_MUL_F64 0, CONST.FP64_ONE, 0, $src, 0, 0)
				3001	>;
				3002
Marek Olsak	43650e4	2015-03-24 13:40:08 +0000	[diff] [blame]	3003	//===----------------------------------------------------------------------===//
				3004	// Fract Patterns
				3005	//===----------------------------------------------------------------------===//
				3006
Marek Olsak	7d77728	2015-03-24 13:40:15 +0000	[diff] [blame]	3007	let Predicates = [isSI] in {
				3008
				3009	// V_FRACT is buggy on SI, so the F32 version is never used and (x-floor(x)) is
				3010	// used instead. However, SI doesn't have V_FLOOR_F64, so the most efficient
				3011	// way to implement it is using V_FRACT_F64.
				3012	// The workaround for the V_FRACT bug is:
				3013	// fract(x) = isnan(x) ? x : min(V_FRACT(x), 0.99999999999999999)
				3014
Marek Olsak	7d77728	2015-03-24 13:40:15 +0000	[diff] [blame]	3015	// Convert floor(x) to (x - fract(x))
				3016	def : Pat <
				3017	(f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))),
				3018	(V_ADD_F64
				3019	$mods,
				3020	$x,
				3021	SRCMODS.NEG,
				3022	(V_CNDMASK_B64_PSEUDO
Marek Olsak	7d77728	2015-03-24 13:40:15 +0000	[diff] [blame]	3023	(V_MIN_F64
				3024	SRCMODS.NONE,
				3025	(V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE),
				3026	SRCMODS.NONE,
				3027	(V_MOV_B64_PSEUDO 0x3fefffffffffffff),
				3028	DSTCLAMP.NONE, DSTOMOD.NONE),
Marek Olsak	1354b87	2015-07-27 11:37:42 +0000	[diff] [blame]	3029	$x,
Marek Olsak	7d77728	2015-03-24 13:40:15 +0000	[diff] [blame]	3030	(V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, 3/NaN/)),
				3031	DSTCLAMP.NONE, DSTOMOD.NONE)
				3032	>;
				3033
				3034	} // End Predicates = [isSI]
				3035
Tom Stellard	fb96169	2013-10-23 00:44:19 +0000	[diff] [blame]	3036	//============================================================================//
Tom Stellard	eac65dd	2013-05-03 17:21:20 +0000	[diff] [blame]	3037	// Miscellaneous Optimization Patterns
				3038	//============================================================================//
				3039
Matt Arsenault	49dd428	2014-09-15 17:15:02 +0000	[diff] [blame]	3040	def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64>;
Tom Stellard	eac65dd	2013-05-03 17:21:20 +0000	[diff] [blame]	3041
Matt Arsenault	c89f291	2016-03-07 21:54:48 +0000	[diff] [blame]	3042	def : IntMed3Pat<V_MED3_I32, smax, smax_oneuse, smin_oneuse>;
				3043	def : IntMed3Pat<V_MED3_U32, umax, umax_oneuse, umin_oneuse>;
				3044
Tom Stellard	245c15f	2015-05-26 15:55:52 +0000	[diff] [blame]	3045	//============================================================================//
				3046	// Assembler aliases
				3047	//============================================================================//
				3048
				3049	def : MnemonicAlias<"v_add_u32", "v_add_i32">;
				3050	def : MnemonicAlias<"v_sub_u32", "v_sub_i32">;
				3051	def : MnemonicAlias<"v_subrev_u32", "v_subrev_i32">;
				3052
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	3053	} // End isGCN predicate