Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Keith Packard <keithp@keithp.com> |
| 26 | * |
| 27 | */ |
| 28 | |
| 29 | #include <linux/seq_file.h> |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 30 | #include <linux/circ_buf.h> |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 31 | #include <linux/ctype.h> |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 32 | #include <linux/debugfs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 33 | #include <linux/slab.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 34 | #include <linux/export.h> |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 35 | #include <linux/list_sort.h> |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 36 | #include <asm/msr-index.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 37 | #include <drm/drmP.h> |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 38 | #include "intel_drv.h" |
Chris Wilson | e5c6526 | 2010-11-01 11:35:28 +0000 | [diff] [blame] | 39 | #include "intel_ringbuffer.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 40 | #include <drm/i915_drm.h> |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 41 | #include "i915_drv.h" |
| 42 | |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 43 | enum { |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 44 | ACTIVE_LIST, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 45 | INACTIVE_LIST, |
Chris Wilson | d21d597 | 2010-09-26 11:19:33 +0100 | [diff] [blame] | 46 | PINNED_LIST, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 47 | }; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 48 | |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 49 | static const char *yesno(int v) |
| 50 | { |
| 51 | return v ? "yes" : "no"; |
| 52 | } |
| 53 | |
Damien Lespiau | 497666d | 2013-10-15 18:55:39 +0100 | [diff] [blame] | 54 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
| 55 | * allocated we need to hook into the minor for release. */ |
| 56 | static int |
| 57 | drm_add_fake_info_node(struct drm_minor *minor, |
| 58 | struct dentry *ent, |
| 59 | const void *key) |
| 60 | { |
| 61 | struct drm_info_node *node; |
| 62 | |
| 63 | node = kmalloc(sizeof(*node), GFP_KERNEL); |
| 64 | if (node == NULL) { |
| 65 | debugfs_remove(ent); |
| 66 | return -ENOMEM; |
| 67 | } |
| 68 | |
| 69 | node->minor = minor; |
| 70 | node->dent = ent; |
| 71 | node->info_ent = (void *) key; |
| 72 | |
| 73 | mutex_lock(&minor->debugfs_lock); |
| 74 | list_add(&node->list, &minor->debugfs_list); |
| 75 | mutex_unlock(&minor->debugfs_lock); |
| 76 | |
| 77 | return 0; |
| 78 | } |
| 79 | |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 80 | static int i915_capabilities(struct seq_file *m, void *data) |
| 81 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 82 | struct drm_info_node *node = m->private; |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 83 | struct drm_device *dev = node->minor->dev; |
| 84 | const struct intel_device_info *info = INTEL_INFO(dev); |
| 85 | |
| 86 | seq_printf(m, "gen: %d\n", info->gen); |
Paulo Zanoni | 03d00ac | 2011-10-14 18:17:41 -0300 | [diff] [blame] | 87 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 88 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
| 89 | #define SEP_SEMICOLON ; |
| 90 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); |
| 91 | #undef PRINT_FLAG |
| 92 | #undef SEP_SEMICOLON |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 93 | |
| 94 | return 0; |
| 95 | } |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 96 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 97 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 98 | { |
Daniel Vetter | 4feb765 | 2014-11-24 11:21:52 +0100 | [diff] [blame] | 99 | if (i915_gem_obj_is_pinned(obj)) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 100 | return "p"; |
| 101 | else |
| 102 | return " "; |
| 103 | } |
| 104 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 105 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 106 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 107 | switch (obj->tiling_mode) { |
| 108 | default: |
| 109 | case I915_TILING_NONE: return " "; |
| 110 | case I915_TILING_X: return "X"; |
| 111 | case I915_TILING_Y: return "Y"; |
| 112 | } |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 113 | } |
| 114 | |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 115 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
| 116 | { |
Tvrtko Ursulin | aff4376 | 2014-10-24 12:42:33 +0100 | [diff] [blame] | 117 | return i915_gem_obj_to_ggtt(obj) ? "g" : " "; |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 118 | } |
| 119 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 120 | static void |
| 121 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) |
| 122 | { |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 123 | struct i915_vma *vma; |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 124 | int pin_count = 0; |
| 125 | |
Ville Syrjälä | fb1ae91 | 2013-08-22 19:21:30 +0300 | [diff] [blame] | 126 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 127 | &obj->base, |
| 128 | get_pin_flag(obj), |
| 129 | get_tiling_flag(obj), |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 130 | get_global_flag(obj), |
Eric Anholt | a05a586 | 2011-12-20 08:54:15 -0800 | [diff] [blame] | 131 | obj->base.size / 1024, |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 132 | obj->base.read_domains, |
| 133 | obj->base.write_domain, |
John Harrison | 97b2a6a | 2014-11-24 18:49:26 +0000 | [diff] [blame] | 134 | i915_gem_request_get_seqno(obj->last_read_req), |
| 135 | i915_gem_request_get_seqno(obj->last_write_req), |
| 136 | i915_gem_request_get_seqno(obj->last_fenced_req), |
Chris Wilson | 0a4cd7c | 2014-08-22 14:41:39 +0100 | [diff] [blame] | 137 | i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level), |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 138 | obj->dirty ? " dirty" : "", |
| 139 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); |
| 140 | if (obj->base.name) |
| 141 | seq_printf(m, " (name: %d)", obj->base.name); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 142 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 143 | if (vma->pin_count > 0) |
| 144 | pin_count++; |
| 145 | seq_printf(m, " (pinned x %d)", pin_count); |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 146 | if (obj->pin_display) |
| 147 | seq_printf(m, " (display)"); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 148 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
| 149 | seq_printf(m, " (fence: %d)", obj->fence_reg); |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 150 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
| 151 | if (!i915_is_ggtt(vma->vm)) |
| 152 | seq_puts(m, " (pp"); |
| 153 | else |
| 154 | seq_puts(m, " (g"); |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 155 | seq_printf(m, "gtt offset: %08lx, size: %08lx, type: %u)", |
| 156 | vma->node.start, vma->node.size, |
| 157 | vma->ggtt_view.type); |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 158 | } |
Chris Wilson | c1ad11f | 2012-11-15 11:32:21 +0000 | [diff] [blame] | 159 | if (obj->stolen) |
| 160 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 161 | if (obj->pin_mappable || obj->fault_mappable) { |
| 162 | char s[3], *t = s; |
| 163 | if (obj->pin_mappable) |
| 164 | *t++ = 'p'; |
| 165 | if (obj->fault_mappable) |
| 166 | *t++ = 'f'; |
| 167 | *t = '\0'; |
| 168 | seq_printf(m, " (%s mappable)", s); |
| 169 | } |
John Harrison | 41c5241 | 2014-11-24 18:49:43 +0000 | [diff] [blame] | 170 | if (obj->last_read_req != NULL) |
| 171 | seq_printf(m, " (%s)", |
| 172 | i915_gem_request_get_ring(obj->last_read_req)->name); |
Daniel Vetter | d5a81ef | 2014-06-18 14:46:49 +0200 | [diff] [blame] | 173 | if (obj->frontbuffer_bits) |
| 174 | seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 175 | } |
| 176 | |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 177 | static void describe_ctx(struct seq_file *m, struct intel_context *ctx) |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 178 | { |
Oscar Mateo | ea0c76f | 2014-07-03 16:27:59 +0100 | [diff] [blame] | 179 | seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i'); |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 180 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
| 181 | seq_putc(m, ' '); |
| 182 | } |
| 183 | |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 184 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 185 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 186 | struct drm_info_node *node = m->private; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 187 | uintptr_t list = (uintptr_t) node->info_ent->data; |
| 188 | struct list_head *head; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 189 | struct drm_device *dev = node->minor->dev; |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 190 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 191 | struct i915_address_space *vm = &dev_priv->gtt.base; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 192 | struct i915_vma *vma; |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 193 | size_t total_obj_size, total_gtt_size; |
| 194 | int count, ret; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 195 | |
| 196 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 197 | if (ret) |
| 198 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 199 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 200 | /* FIXME: the user of this interface might want more than just GGTT */ |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 201 | switch (list) { |
| 202 | case ACTIVE_LIST: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 203 | seq_puts(m, "Active:\n"); |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 204 | head = &vm->active_list; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 205 | break; |
| 206 | case INACTIVE_LIST: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 207 | seq_puts(m, "Inactive:\n"); |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 208 | head = &vm->inactive_list; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 209 | break; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 210 | default: |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 211 | mutex_unlock(&dev->struct_mutex); |
| 212 | return -EINVAL; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 213 | } |
| 214 | |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 215 | total_obj_size = total_gtt_size = count = 0; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 216 | list_for_each_entry(vma, head, mm_list) { |
| 217 | seq_printf(m, " "); |
| 218 | describe_obj(m, vma->obj); |
| 219 | seq_printf(m, "\n"); |
| 220 | total_obj_size += vma->obj->base.size; |
| 221 | total_gtt_size += vma->node.size; |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 222 | count++; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 223 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 224 | mutex_unlock(&dev->struct_mutex); |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 225 | |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 226 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 227 | count, total_obj_size, total_gtt_size); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 228 | return 0; |
| 229 | } |
| 230 | |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 231 | static int obj_rank_by_stolen(void *priv, |
| 232 | struct list_head *A, struct list_head *B) |
| 233 | { |
| 234 | struct drm_i915_gem_object *a = |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 235 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 236 | struct drm_i915_gem_object *b = |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 237 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 238 | |
| 239 | return a->stolen->start - b->stolen->start; |
| 240 | } |
| 241 | |
| 242 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) |
| 243 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 244 | struct drm_info_node *node = m->private; |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 245 | struct drm_device *dev = node->minor->dev; |
| 246 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 247 | struct drm_i915_gem_object *obj; |
| 248 | size_t total_obj_size, total_gtt_size; |
| 249 | LIST_HEAD(stolen); |
| 250 | int count, ret; |
| 251 | |
| 252 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 253 | if (ret) |
| 254 | return ret; |
| 255 | |
| 256 | total_obj_size = total_gtt_size = count = 0; |
| 257 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
| 258 | if (obj->stolen == NULL) |
| 259 | continue; |
| 260 | |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 261 | list_add(&obj->obj_exec_link, &stolen); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 262 | |
| 263 | total_obj_size += obj->base.size; |
| 264 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
| 265 | count++; |
| 266 | } |
| 267 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
| 268 | if (obj->stolen == NULL) |
| 269 | continue; |
| 270 | |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 271 | list_add(&obj->obj_exec_link, &stolen); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 272 | |
| 273 | total_obj_size += obj->base.size; |
| 274 | count++; |
| 275 | } |
| 276 | list_sort(NULL, &stolen, obj_rank_by_stolen); |
| 277 | seq_puts(m, "Stolen:\n"); |
| 278 | while (!list_empty(&stolen)) { |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 279 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 280 | seq_puts(m, " "); |
| 281 | describe_obj(m, obj); |
| 282 | seq_putc(m, '\n'); |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 283 | list_del_init(&obj->obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 284 | } |
| 285 | mutex_unlock(&dev->struct_mutex); |
| 286 | |
| 287 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 288 | count, total_obj_size, total_gtt_size); |
| 289 | return 0; |
| 290 | } |
| 291 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 292 | #define count_objects(list, member) do { \ |
| 293 | list_for_each_entry(obj, list, member) { \ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 294 | size += i915_gem_obj_ggtt_size(obj); \ |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 295 | ++count; \ |
| 296 | if (obj->map_and_fenceable) { \ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 297 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 298 | ++mappable_count; \ |
| 299 | } \ |
| 300 | } \ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 301 | } while (0) |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 302 | |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 303 | struct file_stats { |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 304 | struct drm_i915_file_private *file_priv; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 305 | int count; |
Chris Wilson | c67a17e | 2014-03-19 13:45:46 +0000 | [diff] [blame] | 306 | size_t total, unbound; |
| 307 | size_t global, shared; |
| 308 | size_t active, inactive; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 309 | }; |
| 310 | |
| 311 | static int per_file_stats(int id, void *ptr, void *data) |
| 312 | { |
| 313 | struct drm_i915_gem_object *obj = ptr; |
| 314 | struct file_stats *stats = data; |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 315 | struct i915_vma *vma; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 316 | |
| 317 | stats->count++; |
| 318 | stats->total += obj->base.size; |
| 319 | |
Chris Wilson | c67a17e | 2014-03-19 13:45:46 +0000 | [diff] [blame] | 320 | if (obj->base.name || obj->base.dma_buf) |
| 321 | stats->shared += obj->base.size; |
| 322 | |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 323 | if (USES_FULL_PPGTT(obj->base.dev)) { |
| 324 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
| 325 | struct i915_hw_ppgtt *ppgtt; |
| 326 | |
| 327 | if (!drm_mm_node_allocated(&vma->node)) |
| 328 | continue; |
| 329 | |
| 330 | if (i915_is_ggtt(vma->vm)) { |
| 331 | stats->global += obj->base.size; |
| 332 | continue; |
| 333 | } |
| 334 | |
| 335 | ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base); |
Daniel Vetter | 4d88470 | 2014-08-06 15:04:47 +0200 | [diff] [blame] | 336 | if (ppgtt->file_priv != stats->file_priv) |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 337 | continue; |
| 338 | |
John Harrison | 41c5241 | 2014-11-24 18:49:43 +0000 | [diff] [blame] | 339 | if (obj->active) /* XXX per-vma statistic */ |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 340 | stats->active += obj->base.size; |
| 341 | else |
| 342 | stats->inactive += obj->base.size; |
| 343 | |
| 344 | return 0; |
| 345 | } |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 346 | } else { |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 347 | if (i915_gem_obj_ggtt_bound(obj)) { |
| 348 | stats->global += obj->base.size; |
John Harrison | 41c5241 | 2014-11-24 18:49:43 +0000 | [diff] [blame] | 349 | if (obj->active) |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 350 | stats->active += obj->base.size; |
| 351 | else |
| 352 | stats->inactive += obj->base.size; |
| 353 | return 0; |
| 354 | } |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 355 | } |
| 356 | |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 357 | if (!list_empty(&obj->global_list)) |
| 358 | stats->unbound += obj->base.size; |
| 359 | |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 360 | return 0; |
| 361 | } |
| 362 | |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 363 | #define print_file_stats(m, name, stats) \ |
| 364 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \ |
| 365 | name, \ |
| 366 | stats.count, \ |
| 367 | stats.total, \ |
| 368 | stats.active, \ |
| 369 | stats.inactive, \ |
| 370 | stats.global, \ |
| 371 | stats.shared, \ |
| 372 | stats.unbound) |
| 373 | |
| 374 | static void print_batch_pool_stats(struct seq_file *m, |
| 375 | struct drm_i915_private *dev_priv) |
| 376 | { |
| 377 | struct drm_i915_gem_object *obj; |
| 378 | struct file_stats stats; |
| 379 | |
| 380 | memset(&stats, 0, sizeof(stats)); |
| 381 | |
| 382 | list_for_each_entry(obj, |
| 383 | &dev_priv->mm.batch_pool.cache_list, |
| 384 | batch_pool_list) |
| 385 | per_file_stats(0, obj, &stats); |
| 386 | |
| 387 | print_file_stats(m, "batch pool", stats); |
| 388 | } |
| 389 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 390 | #define count_vmas(list, member) do { \ |
| 391 | list_for_each_entry(vma, list, member) { \ |
| 392 | size += i915_gem_obj_ggtt_size(vma->obj); \ |
| 393 | ++count; \ |
| 394 | if (vma->obj->map_and_fenceable) { \ |
| 395 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ |
| 396 | ++mappable_count; \ |
| 397 | } \ |
| 398 | } \ |
| 399 | } while (0) |
| 400 | |
| 401 | static int i915_gem_object_info(struct seq_file *m, void* data) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 402 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 403 | struct drm_info_node *node = m->private; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 404 | struct drm_device *dev = node->minor->dev; |
| 405 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 406 | u32 count, mappable_count, purgeable_count; |
| 407 | size_t size, mappable_size, purgeable_size; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 408 | struct drm_i915_gem_object *obj; |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 409 | struct i915_address_space *vm = &dev_priv->gtt.base; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 410 | struct drm_file *file; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 411 | struct i915_vma *vma; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 412 | int ret; |
| 413 | |
| 414 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 415 | if (ret) |
| 416 | return ret; |
| 417 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 418 | seq_printf(m, "%u objects, %zu bytes\n", |
| 419 | dev_priv->mm.object_count, |
| 420 | dev_priv->mm.object_memory); |
| 421 | |
| 422 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 423 | count_objects(&dev_priv->mm.bound_list, global_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 424 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
| 425 | count, mappable_count, size, mappable_size); |
| 426 | |
| 427 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 428 | count_vmas(&vm->active_list, mm_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 429 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
| 430 | count, mappable_count, size, mappable_size); |
| 431 | |
| 432 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 433 | count_vmas(&vm->inactive_list, mm_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 434 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
| 435 | count, mappable_count, size, mappable_size); |
| 436 | |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 437 | size = count = purgeable_size = purgeable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 438 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 439 | size += obj->base.size, ++count; |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 440 | if (obj->madv == I915_MADV_DONTNEED) |
| 441 | purgeable_size += obj->base.size, ++purgeable_count; |
| 442 | } |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 443 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
| 444 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 445 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 446 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 447 | if (obj->fault_mappable) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 448 | size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 449 | ++count; |
| 450 | } |
| 451 | if (obj->pin_mappable) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 452 | mappable_size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 453 | ++mappable_count; |
| 454 | } |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 455 | if (obj->madv == I915_MADV_DONTNEED) { |
| 456 | purgeable_size += obj->base.size; |
| 457 | ++purgeable_count; |
| 458 | } |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 459 | } |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 460 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
| 461 | purgeable_count, purgeable_size); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 462 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
| 463 | mappable_count, mappable_size); |
| 464 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", |
| 465 | count, size); |
| 466 | |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 467 | seq_printf(m, "%zu [%lu] gtt total\n", |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 468 | dev_priv->gtt.base.total, |
| 469 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 470 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 471 | seq_putc(m, '\n'); |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 472 | print_batch_pool_stats(m, dev_priv); |
| 473 | |
| 474 | seq_putc(m, '\n'); |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 475 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
| 476 | struct file_stats stats; |
Tetsuo Handa | 3ec2f42 | 2014-01-03 20:42:18 +0900 | [diff] [blame] | 477 | struct task_struct *task; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 478 | |
| 479 | memset(&stats, 0, sizeof(stats)); |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 480 | stats.file_priv = file->driver_priv; |
Chris Wilson | 5b5ffff | 2014-06-17 09:56:24 +0100 | [diff] [blame] | 481 | spin_lock(&file->table_lock); |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 482 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
Chris Wilson | 5b5ffff | 2014-06-17 09:56:24 +0100 | [diff] [blame] | 483 | spin_unlock(&file->table_lock); |
Tetsuo Handa | 3ec2f42 | 2014-01-03 20:42:18 +0900 | [diff] [blame] | 484 | /* |
| 485 | * Although we have a valid reference on file->pid, that does |
| 486 | * not guarantee that the task_struct who called get_pid() is |
| 487 | * still alive (e.g. get_pid(current) => fork() => exit()). |
| 488 | * Therefore, we need to protect this ->comm access using RCU. |
| 489 | */ |
| 490 | rcu_read_lock(); |
| 491 | task = pid_task(file->pid, PIDTYPE_PID); |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 492 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
Tetsuo Handa | 3ec2f42 | 2014-01-03 20:42:18 +0900 | [diff] [blame] | 493 | rcu_read_unlock(); |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 494 | } |
| 495 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 496 | mutex_unlock(&dev->struct_mutex); |
| 497 | |
| 498 | return 0; |
| 499 | } |
| 500 | |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 501 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 502 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 503 | struct drm_info_node *node = m->private; |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 504 | struct drm_device *dev = node->minor->dev; |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 505 | uintptr_t list = (uintptr_t) node->info_ent->data; |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 506 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 507 | struct drm_i915_gem_object *obj; |
| 508 | size_t total_obj_size, total_gtt_size; |
| 509 | int count, ret; |
| 510 | |
| 511 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 512 | if (ret) |
| 513 | return ret; |
| 514 | |
| 515 | total_obj_size = total_gtt_size = count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 516 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 517 | if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 518 | continue; |
| 519 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 520 | seq_puts(m, " "); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 521 | describe_obj(m, obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 522 | seq_putc(m, '\n'); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 523 | total_obj_size += obj->base.size; |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 524 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 525 | count++; |
| 526 | } |
| 527 | |
| 528 | mutex_unlock(&dev->struct_mutex); |
| 529 | |
| 530 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 531 | count, total_obj_size, total_gtt_size); |
| 532 | |
| 533 | return 0; |
| 534 | } |
| 535 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 536 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
| 537 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 538 | struct drm_info_node *node = m->private; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 539 | struct drm_device *dev = node->minor->dev; |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 540 | struct drm_i915_private *dev_priv = dev->dev_private; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 541 | struct intel_crtc *crtc; |
Daniel Vetter | 8a270eb | 2014-06-17 22:34:37 +0200 | [diff] [blame] | 542 | int ret; |
| 543 | |
| 544 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 545 | if (ret) |
| 546 | return ret; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 547 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 548 | for_each_intel_crtc(dev, crtc) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 549 | const char pipe = pipe_name(crtc->pipe); |
| 550 | const char plane = plane_name(crtc->plane); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 551 | struct intel_unpin_work *work; |
| 552 | |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 553 | spin_lock_irq(&dev->event_lock); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 554 | work = crtc->unpin_work; |
| 555 | if (work == NULL) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 556 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 557 | pipe, plane); |
| 558 | } else { |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 559 | u32 addr; |
| 560 | |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 561 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 562 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 563 | pipe, plane); |
| 564 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 565 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 566 | pipe, plane); |
| 567 | } |
Daniel Vetter | 3a8a946 | 2014-11-26 14:39:48 +0100 | [diff] [blame] | 568 | if (work->flip_queued_req) { |
| 569 | struct intel_engine_cs *ring = |
| 570 | i915_gem_request_get_ring(work->flip_queued_req); |
| 571 | |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 572 | seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n", |
Daniel Vetter | 3a8a946 | 2014-11-26 14:39:48 +0100 | [diff] [blame] | 573 | ring->name, |
John Harrison | f06cc1b | 2014-11-24 18:49:37 +0000 | [diff] [blame] | 574 | i915_gem_request_get_seqno(work->flip_queued_req), |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 575 | dev_priv->next_seqno, |
Daniel Vetter | 3a8a946 | 2014-11-26 14:39:48 +0100 | [diff] [blame] | 576 | ring->get_seqno(ring, true), |
John Harrison | 1b5a433 | 2014-11-24 18:49:42 +0000 | [diff] [blame] | 577 | i915_gem_request_completed(work->flip_queued_req, true)); |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 578 | } else |
| 579 | seq_printf(m, "Flip not associated with any ring\n"); |
| 580 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", |
| 581 | work->flip_queued_vblank, |
| 582 | work->flip_ready_vblank, |
| 583 | drm_vblank_count(dev, crtc->pipe)); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 584 | if (work->enable_stall_check) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 585 | seq_puts(m, "Stall check enabled, "); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 586 | else |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 587 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 588 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 589 | |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 590 | if (INTEL_INFO(dev)->gen >= 4) |
| 591 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); |
| 592 | else |
| 593 | addr = I915_READ(DSPADDR(crtc->plane)); |
| 594 | seq_printf(m, "Current scanout address 0x%08x\n", addr); |
| 595 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 596 | if (work->pending_flip_obj) { |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 597 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); |
| 598 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 599 | } |
| 600 | } |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 601 | spin_unlock_irq(&dev->event_lock); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 602 | } |
| 603 | |
Daniel Vetter | 8a270eb | 2014-06-17 22:34:37 +0200 | [diff] [blame] | 604 | mutex_unlock(&dev->struct_mutex); |
| 605 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 606 | return 0; |
| 607 | } |
| 608 | |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 609 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
| 610 | { |
| 611 | struct drm_info_node *node = m->private; |
| 612 | struct drm_device *dev = node->minor->dev; |
| 613 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 614 | struct drm_i915_gem_object *obj; |
| 615 | int count = 0; |
| 616 | int ret; |
| 617 | |
| 618 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 619 | if (ret) |
| 620 | return ret; |
| 621 | |
| 622 | seq_puts(m, "cache:\n"); |
| 623 | list_for_each_entry(obj, |
| 624 | &dev_priv->mm.batch_pool.cache_list, |
| 625 | batch_pool_list) { |
| 626 | seq_puts(m, " "); |
| 627 | describe_obj(m, obj); |
| 628 | seq_putc(m, '\n'); |
| 629 | count++; |
| 630 | } |
| 631 | |
| 632 | seq_printf(m, "total: %d\n", count); |
| 633 | |
| 634 | mutex_unlock(&dev->struct_mutex); |
| 635 | |
| 636 | return 0; |
| 637 | } |
| 638 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 639 | static int i915_gem_request_info(struct seq_file *m, void *data) |
| 640 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 641 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 642 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 643 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 644 | struct intel_engine_cs *ring; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 645 | struct drm_i915_gem_request *gem_request; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 646 | int ret, count, i; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 647 | |
| 648 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 649 | if (ret) |
| 650 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 651 | |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 652 | count = 0; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 653 | for_each_ring(ring, dev_priv, i) { |
| 654 | if (list_empty(&ring->request_list)) |
| 655 | continue; |
| 656 | |
| 657 | seq_printf(m, "%s requests:\n", ring->name); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 658 | list_for_each_entry(gem_request, |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 659 | &ring->request_list, |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 660 | list) { |
| 661 | seq_printf(m, " %d @ %d\n", |
| 662 | gem_request->seqno, |
| 663 | (int) (jiffies - gem_request->emitted_jiffies)); |
| 664 | } |
| 665 | count++; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 666 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 667 | mutex_unlock(&dev->struct_mutex); |
| 668 | |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 669 | if (count == 0) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 670 | seq_puts(m, "No requests\n"); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 671 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 672 | return 0; |
| 673 | } |
| 674 | |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 675 | static void i915_ring_seqno_info(struct seq_file *m, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 676 | struct intel_engine_cs *ring) |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 677 | { |
| 678 | if (ring->get_seqno) { |
Mika Kuoppala | 43a7b92 | 2012-12-04 15:12:01 +0200 | [diff] [blame] | 679 | seq_printf(m, "Current sequence (%s): %u\n", |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 680 | ring->name, ring->get_seqno(ring, false)); |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 681 | } |
| 682 | } |
| 683 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 684 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
| 685 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 686 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 687 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 688 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 689 | struct intel_engine_cs *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 690 | int ret, i; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 691 | |
| 692 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 693 | if (ret) |
| 694 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 695 | intel_runtime_pm_get(dev_priv); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 696 | |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 697 | for_each_ring(ring, dev_priv, i) |
| 698 | i915_ring_seqno_info(m, ring); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 699 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 700 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 701 | mutex_unlock(&dev->struct_mutex); |
| 702 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 703 | return 0; |
| 704 | } |
| 705 | |
| 706 | |
| 707 | static int i915_interrupt_info(struct seq_file *m, void *data) |
| 708 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 709 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 710 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 711 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 712 | struct intel_engine_cs *ring; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 713 | int ret, i, pipe; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 714 | |
| 715 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 716 | if (ret) |
| 717 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 718 | intel_runtime_pm_get(dev_priv); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 719 | |
Ville Syrjälä | 74e1ca8 | 2014-04-09 13:28:09 +0300 | [diff] [blame] | 720 | if (IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | 74e1ca8 | 2014-04-09 13:28:09 +0300 | [diff] [blame] | 721 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
| 722 | I915_READ(GEN8_MASTER_IRQ)); |
| 723 | |
| 724 | seq_printf(m, "Display IER:\t%08x\n", |
| 725 | I915_READ(VLV_IER)); |
| 726 | seq_printf(m, "Display IIR:\t%08x\n", |
| 727 | I915_READ(VLV_IIR)); |
| 728 | seq_printf(m, "Display IIR_RW:\t%08x\n", |
| 729 | I915_READ(VLV_IIR_RW)); |
| 730 | seq_printf(m, "Display IMR:\t%08x\n", |
| 731 | I915_READ(VLV_IMR)); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 732 | for_each_pipe(dev_priv, pipe) |
Ville Syrjälä | 74e1ca8 | 2014-04-09 13:28:09 +0300 | [diff] [blame] | 733 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
| 734 | pipe_name(pipe), |
| 735 | I915_READ(PIPESTAT(pipe))); |
| 736 | |
| 737 | seq_printf(m, "Port hotplug:\t%08x\n", |
| 738 | I915_READ(PORT_HOTPLUG_EN)); |
| 739 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", |
| 740 | I915_READ(VLV_DPFLIPSTAT)); |
| 741 | seq_printf(m, "DPINVGTT:\t%08x\n", |
| 742 | I915_READ(DPINVGTT)); |
| 743 | |
| 744 | for (i = 0; i < 4; i++) { |
| 745 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", |
| 746 | i, I915_READ(GEN8_GT_IMR(i))); |
| 747 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", |
| 748 | i, I915_READ(GEN8_GT_IIR(i))); |
| 749 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", |
| 750 | i, I915_READ(GEN8_GT_IER(i))); |
| 751 | } |
| 752 | |
| 753 | seq_printf(m, "PCU interrupt mask:\t%08x\n", |
| 754 | I915_READ(GEN8_PCU_IMR)); |
| 755 | seq_printf(m, "PCU interrupt identity:\t%08x\n", |
| 756 | I915_READ(GEN8_PCU_IIR)); |
| 757 | seq_printf(m, "PCU interrupt enable:\t%08x\n", |
| 758 | I915_READ(GEN8_PCU_IER)); |
| 759 | } else if (INTEL_INFO(dev)->gen >= 8) { |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 760 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
| 761 | I915_READ(GEN8_MASTER_IRQ)); |
| 762 | |
| 763 | for (i = 0; i < 4; i++) { |
| 764 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", |
| 765 | i, I915_READ(GEN8_GT_IMR(i))); |
| 766 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", |
| 767 | i, I915_READ(GEN8_GT_IIR(i))); |
| 768 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", |
| 769 | i, I915_READ(GEN8_GT_IER(i))); |
| 770 | } |
| 771 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 772 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 773 | if (!intel_display_power_is_enabled(dev_priv, |
Paulo Zanoni | 22c5996 | 2014-08-08 17:45:32 -0300 | [diff] [blame] | 774 | POWER_DOMAIN_PIPE(pipe))) { |
| 775 | seq_printf(m, "Pipe %c power disabled\n", |
| 776 | pipe_name(pipe)); |
| 777 | continue; |
| 778 | } |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 779 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 780 | pipe_name(pipe), |
| 781 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 782 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 783 | pipe_name(pipe), |
| 784 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 785 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 786 | pipe_name(pipe), |
| 787 | I915_READ(GEN8_DE_PIPE_IER(pipe))); |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 788 | } |
| 789 | |
| 790 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", |
| 791 | I915_READ(GEN8_DE_PORT_IMR)); |
| 792 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", |
| 793 | I915_READ(GEN8_DE_PORT_IIR)); |
| 794 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", |
| 795 | I915_READ(GEN8_DE_PORT_IER)); |
| 796 | |
| 797 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", |
| 798 | I915_READ(GEN8_DE_MISC_IMR)); |
| 799 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", |
| 800 | I915_READ(GEN8_DE_MISC_IIR)); |
| 801 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", |
| 802 | I915_READ(GEN8_DE_MISC_IER)); |
| 803 | |
| 804 | seq_printf(m, "PCU interrupt mask:\t%08x\n", |
| 805 | I915_READ(GEN8_PCU_IMR)); |
| 806 | seq_printf(m, "PCU interrupt identity:\t%08x\n", |
| 807 | I915_READ(GEN8_PCU_IIR)); |
| 808 | seq_printf(m, "PCU interrupt enable:\t%08x\n", |
| 809 | I915_READ(GEN8_PCU_IER)); |
| 810 | } else if (IS_VALLEYVIEW(dev)) { |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 811 | seq_printf(m, "Display IER:\t%08x\n", |
| 812 | I915_READ(VLV_IER)); |
| 813 | seq_printf(m, "Display IIR:\t%08x\n", |
| 814 | I915_READ(VLV_IIR)); |
| 815 | seq_printf(m, "Display IIR_RW:\t%08x\n", |
| 816 | I915_READ(VLV_IIR_RW)); |
| 817 | seq_printf(m, "Display IMR:\t%08x\n", |
| 818 | I915_READ(VLV_IMR)); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 819 | for_each_pipe(dev_priv, pipe) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 820 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
| 821 | pipe_name(pipe), |
| 822 | I915_READ(PIPESTAT(pipe))); |
| 823 | |
| 824 | seq_printf(m, "Master IER:\t%08x\n", |
| 825 | I915_READ(VLV_MASTER_IER)); |
| 826 | |
| 827 | seq_printf(m, "Render IER:\t%08x\n", |
| 828 | I915_READ(GTIER)); |
| 829 | seq_printf(m, "Render IIR:\t%08x\n", |
| 830 | I915_READ(GTIIR)); |
| 831 | seq_printf(m, "Render IMR:\t%08x\n", |
| 832 | I915_READ(GTIMR)); |
| 833 | |
| 834 | seq_printf(m, "PM IER:\t\t%08x\n", |
| 835 | I915_READ(GEN6_PMIER)); |
| 836 | seq_printf(m, "PM IIR:\t\t%08x\n", |
| 837 | I915_READ(GEN6_PMIIR)); |
| 838 | seq_printf(m, "PM IMR:\t\t%08x\n", |
| 839 | I915_READ(GEN6_PMIMR)); |
| 840 | |
| 841 | seq_printf(m, "Port hotplug:\t%08x\n", |
| 842 | I915_READ(PORT_HOTPLUG_EN)); |
| 843 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", |
| 844 | I915_READ(VLV_DPFLIPSTAT)); |
| 845 | seq_printf(m, "DPINVGTT:\t%08x\n", |
| 846 | I915_READ(DPINVGTT)); |
| 847 | |
| 848 | } else if (!HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 5f6a169 | 2009-08-10 21:37:24 +0800 | [diff] [blame] | 849 | seq_printf(m, "Interrupt enable: %08x\n", |
| 850 | I915_READ(IER)); |
| 851 | seq_printf(m, "Interrupt identity: %08x\n", |
| 852 | I915_READ(IIR)); |
| 853 | seq_printf(m, "Interrupt mask: %08x\n", |
| 854 | I915_READ(IMR)); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 855 | for_each_pipe(dev_priv, pipe) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 856 | seq_printf(m, "Pipe %c stat: %08x\n", |
| 857 | pipe_name(pipe), |
| 858 | I915_READ(PIPESTAT(pipe))); |
Zhenyu Wang | 5f6a169 | 2009-08-10 21:37:24 +0800 | [diff] [blame] | 859 | } else { |
| 860 | seq_printf(m, "North Display Interrupt enable: %08x\n", |
| 861 | I915_READ(DEIER)); |
| 862 | seq_printf(m, "North Display Interrupt identity: %08x\n", |
| 863 | I915_READ(DEIIR)); |
| 864 | seq_printf(m, "North Display Interrupt mask: %08x\n", |
| 865 | I915_READ(DEIMR)); |
| 866 | seq_printf(m, "South Display Interrupt enable: %08x\n", |
| 867 | I915_READ(SDEIER)); |
| 868 | seq_printf(m, "South Display Interrupt identity: %08x\n", |
| 869 | I915_READ(SDEIIR)); |
| 870 | seq_printf(m, "South Display Interrupt mask: %08x\n", |
| 871 | I915_READ(SDEIMR)); |
| 872 | seq_printf(m, "Graphics Interrupt enable: %08x\n", |
| 873 | I915_READ(GTIER)); |
| 874 | seq_printf(m, "Graphics Interrupt identity: %08x\n", |
| 875 | I915_READ(GTIIR)); |
| 876 | seq_printf(m, "Graphics Interrupt mask: %08x\n", |
| 877 | I915_READ(GTIMR)); |
| 878 | } |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 879 | for_each_ring(ring, dev_priv, i) { |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 880 | if (INTEL_INFO(dev)->gen >= 6) { |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 881 | seq_printf(m, |
| 882 | "Graphics Interrupt mask (%s): %08x\n", |
| 883 | ring->name, I915_READ_IMR(ring)); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 884 | } |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 885 | i915_ring_seqno_info(m, ring); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 886 | } |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 887 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 888 | mutex_unlock(&dev->struct_mutex); |
| 889 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 890 | return 0; |
| 891 | } |
| 892 | |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 893 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
| 894 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 895 | struct drm_info_node *node = m->private; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 896 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 897 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 898 | int i, ret; |
| 899 | |
| 900 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 901 | if (ret) |
| 902 | return ret; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 903 | |
| 904 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); |
| 905 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
| 906 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 907 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 908 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 909 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
| 910 | i, dev_priv->fence_regs[i].pin_count); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 911 | if (obj == NULL) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 912 | seq_puts(m, "unused"); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 913 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 914 | describe_obj(m, obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 915 | seq_putc(m, '\n'); |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 916 | } |
| 917 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 918 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 919 | return 0; |
| 920 | } |
| 921 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 922 | static int i915_hws_info(struct seq_file *m, void *data) |
| 923 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 924 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 925 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 926 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 927 | struct intel_engine_cs *ring; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 928 | const u32 *hws; |
Chris Wilson | 4066c0a | 2010-10-29 21:00:54 +0100 | [diff] [blame] | 929 | int i; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 930 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 931 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 932 | hws = ring->status_page.page_addr; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 933 | if (hws == NULL) |
| 934 | return 0; |
| 935 | |
| 936 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { |
| 937 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 938 | i * 4, |
| 939 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); |
| 940 | } |
| 941 | return 0; |
| 942 | } |
| 943 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 944 | static ssize_t |
| 945 | i915_error_state_write(struct file *filp, |
| 946 | const char __user *ubuf, |
| 947 | size_t cnt, |
| 948 | loff_t *ppos) |
| 949 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 950 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 951 | struct drm_device *dev = error_priv->dev; |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 952 | int ret; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 953 | |
| 954 | DRM_DEBUG_DRIVER("Resetting error state\n"); |
| 955 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 956 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 957 | if (ret) |
| 958 | return ret; |
| 959 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 960 | i915_destroy_error_state(dev); |
| 961 | mutex_unlock(&dev->struct_mutex); |
| 962 | |
| 963 | return cnt; |
| 964 | } |
| 965 | |
| 966 | static int i915_error_state_open(struct inode *inode, struct file *file) |
| 967 | { |
| 968 | struct drm_device *dev = inode->i_private; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 969 | struct i915_error_state_file_priv *error_priv; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 970 | |
| 971 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); |
| 972 | if (!error_priv) |
| 973 | return -ENOMEM; |
| 974 | |
| 975 | error_priv->dev = dev; |
| 976 | |
Mika Kuoppala | 95d5bfb | 2013-06-06 15:18:40 +0300 | [diff] [blame] | 977 | i915_error_state_get(dev, error_priv); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 978 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 979 | file->private_data = error_priv; |
| 980 | |
| 981 | return 0; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 982 | } |
| 983 | |
| 984 | static int i915_error_state_release(struct inode *inode, struct file *file) |
| 985 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 986 | struct i915_error_state_file_priv *error_priv = file->private_data; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 987 | |
Mika Kuoppala | 95d5bfb | 2013-06-06 15:18:40 +0300 | [diff] [blame] | 988 | i915_error_state_put(error_priv); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 989 | kfree(error_priv); |
| 990 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 991 | return 0; |
| 992 | } |
| 993 | |
| 994 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
| 995 | size_t count, loff_t *pos) |
| 996 | { |
| 997 | struct i915_error_state_file_priv *error_priv = file->private_data; |
| 998 | struct drm_i915_error_state_buf error_str; |
| 999 | loff_t tmp_pos = 0; |
| 1000 | ssize_t ret_count = 0; |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 1001 | int ret; |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1002 | |
Chris Wilson | 0a4cd7c | 2014-08-22 14:41:39 +0100 | [diff] [blame] | 1003 | ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos); |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 1004 | if (ret) |
| 1005 | return ret; |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1006 | |
Mika Kuoppala | fc16b48 | 2013-06-06 15:18:39 +0300 | [diff] [blame] | 1007 | ret = i915_error_state_to_str(&error_str, error_priv); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1008 | if (ret) |
| 1009 | goto out; |
| 1010 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1011 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
| 1012 | error_str.buf, |
| 1013 | error_str.bytes); |
| 1014 | |
| 1015 | if (ret_count < 0) |
| 1016 | ret = ret_count; |
| 1017 | else |
| 1018 | *pos = error_str.start + ret_count; |
| 1019 | out: |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 1020 | i915_error_state_buf_release(&error_str); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1021 | return ret ?: ret_count; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 1022 | } |
| 1023 | |
| 1024 | static const struct file_operations i915_error_state_fops = { |
| 1025 | .owner = THIS_MODULE, |
| 1026 | .open = i915_error_state_open, |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1027 | .read = i915_error_state_read, |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 1028 | .write = i915_error_state_write, |
| 1029 | .llseek = default_llseek, |
| 1030 | .release = i915_error_state_release, |
| 1031 | }; |
| 1032 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1033 | static int |
| 1034 | i915_next_seqno_get(void *data, u64 *val) |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1035 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1036 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1037 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1038 | int ret; |
| 1039 | |
| 1040 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1041 | if (ret) |
| 1042 | return ret; |
| 1043 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1044 | *val = dev_priv->next_seqno; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1045 | mutex_unlock(&dev->struct_mutex); |
| 1046 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1047 | return 0; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1048 | } |
| 1049 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1050 | static int |
| 1051 | i915_next_seqno_set(void *data, u64 val) |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1052 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1053 | struct drm_device *dev = data; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1054 | int ret; |
| 1055 | |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1056 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1057 | if (ret) |
| 1058 | return ret; |
| 1059 | |
Mika Kuoppala | e94fbaa | 2012-12-19 11:13:09 +0200 | [diff] [blame] | 1060 | ret = i915_gem_set_seqno(dev, val); |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1061 | mutex_unlock(&dev->struct_mutex); |
| 1062 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1063 | return ret; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1064 | } |
| 1065 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1066 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
| 1067 | i915_next_seqno_get, i915_next_seqno_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 1068 | "0x%llx\n"); |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1069 | |
Deepak S | adb4bd1 | 2014-03-31 11:30:02 +0530 | [diff] [blame] | 1070 | static int i915_frequency_info(struct seq_file *m, void *unused) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1071 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1072 | struct drm_info_node *node = m->private; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1073 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1074 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1075 | int ret = 0; |
| 1076 | |
| 1077 | intel_runtime_pm_get(dev_priv); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1078 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 1079 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 1080 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1081 | if (IS_GEN5(dev)) { |
| 1082 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
| 1083 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); |
| 1084 | |
| 1085 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); |
| 1086 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); |
| 1087 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> |
| 1088 | MEMSTAT_VID_SHIFT); |
| 1089 | seq_printf(m, "Current P-state: %d\n", |
| 1090 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 1091 | } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) || |
| 1092 | IS_BROADWELL(dev)) { |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1093 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
| 1094 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
| 1095 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1096 | u32 rpmodectl, rpinclimit, rpdeclimit; |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1097 | u32 rpstat, cagf, reqf; |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1098 | u32 rpupei, rpcurup, rpprevup; |
| 1099 | u32 rpdownei, rpcurdown, rpprevdown; |
Paulo Zanoni | 9dd3c60 | 2014-08-01 18:14:48 -0300 | [diff] [blame] | 1100 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1101 | int max_freq; |
| 1102 | |
| 1103 | /* RPSTAT1 is in the GT power well */ |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 1104 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1105 | if (ret) |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1106 | goto out; |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 1107 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 1108 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1109 | |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1110 | reqf = I915_READ(GEN6_RPNSWREQ); |
| 1111 | reqf &= ~GEN6_TURBO_DISABLE; |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 1112 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1113 | reqf >>= 24; |
| 1114 | else |
| 1115 | reqf >>= 25; |
| 1116 | reqf *= GT_FREQUENCY_MULTIPLIER; |
| 1117 | |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1118 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
| 1119 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); |
| 1120 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); |
| 1121 | |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1122 | rpstat = I915_READ(GEN6_RPSTAT1); |
| 1123 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); |
| 1124 | rpcurup = I915_READ(GEN6_RP_CUR_UP); |
| 1125 | rpprevup = I915_READ(GEN6_RP_PREV_UP); |
| 1126 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); |
| 1127 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); |
| 1128 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 1129 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 1130 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
| 1131 | else |
| 1132 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; |
| 1133 | cagf *= GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1134 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 1135 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 1136 | mutex_unlock(&dev->struct_mutex); |
| 1137 | |
Paulo Zanoni | 9dd3c60 | 2014-08-01 18:14:48 -0300 | [diff] [blame] | 1138 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
| 1139 | pm_ier = I915_READ(GEN6_PMIER); |
| 1140 | pm_imr = I915_READ(GEN6_PMIMR); |
| 1141 | pm_isr = I915_READ(GEN6_PMISR); |
| 1142 | pm_iir = I915_READ(GEN6_PMIIR); |
| 1143 | pm_mask = I915_READ(GEN6_PMINTRMSK); |
| 1144 | } else { |
| 1145 | pm_ier = I915_READ(GEN8_GT_IER(2)); |
| 1146 | pm_imr = I915_READ(GEN8_GT_IMR(2)); |
| 1147 | pm_isr = I915_READ(GEN8_GT_ISR(2)); |
| 1148 | pm_iir = I915_READ(GEN8_GT_IIR(2)); |
| 1149 | pm_mask = I915_READ(GEN6_PMINTRMSK); |
| 1150 | } |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1151 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
Paulo Zanoni | 9dd3c60 | 2014-08-01 18:14:48 -0300 | [diff] [blame] | 1152 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1153 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1154 | seq_printf(m, "Render p-state ratio: %d\n", |
| 1155 | (gt_perf_status & 0xff00) >> 8); |
| 1156 | seq_printf(m, "Render p-state VID: %d\n", |
| 1157 | gt_perf_status & 0xff); |
| 1158 | seq_printf(m, "Render p-state limit: %d\n", |
| 1159 | rp_state_limits & 0xff); |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1160 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
| 1161 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); |
| 1162 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); |
| 1163 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1164 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 1165 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1166 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
| 1167 | GEN6_CURICONT_MASK); |
| 1168 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & |
| 1169 | GEN6_CURBSYTAVG_MASK); |
| 1170 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & |
| 1171 | GEN6_CURBSYTAVG_MASK); |
| 1172 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & |
| 1173 | GEN6_CURIAVG_MASK); |
| 1174 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & |
| 1175 | GEN6_CURBSYTAVG_MASK); |
| 1176 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & |
| 1177 | GEN6_CURBSYTAVG_MASK); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1178 | |
| 1179 | max_freq = (rp_state_cap & 0xff0000) >> 16; |
| 1180 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1181 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1182 | |
| 1183 | max_freq = (rp_state_cap & 0xff00) >> 8; |
| 1184 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1185 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1186 | |
| 1187 | max_freq = rp_state_cap & 0xff; |
| 1188 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1189 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Ben Widawsky | 31c7738 | 2013-04-05 14:29:22 -0700 | [diff] [blame] | 1190 | |
| 1191 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1192 | dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1193 | } else if (IS_VALLEYVIEW(dev)) { |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 1194 | u32 freq_sts; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1195 | |
Jesse Barnes | 259bd5d | 2013-04-22 15:59:30 -0700 | [diff] [blame] | 1196 | mutex_lock(&dev_priv->rps.hw_lock); |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 1197 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1198 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
| 1199 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); |
| 1200 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1201 | seq_printf(m, "max GPU freq: %d MHz\n", |
Deepak S | b2435c9 | 2014-07-17 14:21:14 +0530 | [diff] [blame] | 1202 | vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1203 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1204 | seq_printf(m, "min GPU freq: %d MHz\n", |
Deepak S | b2435c9 | 2014-07-17 14:21:14 +0530 | [diff] [blame] | 1205 | vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq)); |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 1206 | |
| 1207 | seq_printf(m, "efficient (RPe) frequency: %d MHz\n", |
Deepak S | b2435c9 | 2014-07-17 14:21:14 +0530 | [diff] [blame] | 1208 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1209 | |
| 1210 | seq_printf(m, "current GPU freq: %d MHz\n", |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 1211 | vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); |
Jesse Barnes | 259bd5d | 2013-04-22 15:59:30 -0700 | [diff] [blame] | 1212 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1213 | } else { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1214 | seq_puts(m, "no P-state info available\n"); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1215 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1216 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1217 | out: |
| 1218 | intel_runtime_pm_put(dev_priv); |
| 1219 | return ret; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1220 | } |
| 1221 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1222 | static int ironlake_drpc_info(struct seq_file *m) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1223 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1224 | struct drm_info_node *node = m->private; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1225 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1226 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1227 | u32 rgvmodectl, rstdbyctl; |
| 1228 | u16 crstandvid; |
| 1229 | int ret; |
| 1230 | |
| 1231 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1232 | if (ret) |
| 1233 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1234 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1235 | |
| 1236 | rgvmodectl = I915_READ(MEMMODECTL); |
| 1237 | rstdbyctl = I915_READ(RSTDBYCTL); |
| 1238 | crstandvid = I915_READ16(CRSTANDVID); |
| 1239 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1240 | intel_runtime_pm_put(dev_priv); |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1241 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1242 | |
| 1243 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? |
| 1244 | "yes" : "no"); |
| 1245 | seq_printf(m, "Boost freq: %d\n", |
| 1246 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> |
| 1247 | MEMMODE_BOOST_FREQ_SHIFT); |
| 1248 | seq_printf(m, "HW control enabled: %s\n", |
| 1249 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); |
| 1250 | seq_printf(m, "SW control enabled: %s\n", |
| 1251 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); |
| 1252 | seq_printf(m, "Gated voltage change: %s\n", |
| 1253 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); |
| 1254 | seq_printf(m, "Starting frequency: P%d\n", |
| 1255 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1256 | seq_printf(m, "Max P-state: P%d\n", |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1257 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1258 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
| 1259 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); |
| 1260 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); |
| 1261 | seq_printf(m, "Render standby enabled: %s\n", |
| 1262 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1263 | seq_puts(m, "Current RS state: "); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1264 | switch (rstdbyctl & RSX_STATUS_MASK) { |
| 1265 | case RSX_STATUS_ON: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1266 | seq_puts(m, "on\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1267 | break; |
| 1268 | case RSX_STATUS_RC1: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1269 | seq_puts(m, "RC1\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1270 | break; |
| 1271 | case RSX_STATUS_RC1E: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1272 | seq_puts(m, "RC1E\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1273 | break; |
| 1274 | case RSX_STATUS_RS1: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1275 | seq_puts(m, "RS1\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1276 | break; |
| 1277 | case RSX_STATUS_RS2: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1278 | seq_puts(m, "RS2 (RC6)\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1279 | break; |
| 1280 | case RSX_STATUS_RS3: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1281 | seq_puts(m, "RC3 (RC6+)\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1282 | break; |
| 1283 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1284 | seq_puts(m, "unknown\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1285 | break; |
| 1286 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1287 | |
| 1288 | return 0; |
| 1289 | } |
| 1290 | |
Mika Kuoppala | f65367b | 2015-01-16 11:34:42 +0200 | [diff] [blame] | 1291 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
Chris Wilson | b2cff0d | 2015-01-16 11:34:37 +0200 | [diff] [blame] | 1292 | { |
| 1293 | struct drm_info_node *node = m->private; |
| 1294 | struct drm_device *dev = node->minor->dev; |
| 1295 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1296 | struct intel_uncore_forcewake_domain *fw_domain; |
Chris Wilson | b2cff0d | 2015-01-16 11:34:37 +0200 | [diff] [blame] | 1297 | int i; |
| 1298 | |
| 1299 | spin_lock_irq(&dev_priv->uncore.lock); |
| 1300 | for_each_fw_domain(fw_domain, dev_priv, i) { |
| 1301 | seq_printf(m, "%s.wake_count = %u\n", |
Mika Kuoppala | 05a2fb1 | 2015-01-19 16:20:43 +0200 | [diff] [blame] | 1302 | intel_uncore_forcewake_domain_to_str(i), |
Chris Wilson | b2cff0d | 2015-01-16 11:34:37 +0200 | [diff] [blame] | 1303 | fw_domain->wake_count); |
| 1304 | } |
| 1305 | spin_unlock_irq(&dev_priv->uncore.lock); |
| 1306 | |
| 1307 | return 0; |
| 1308 | } |
| 1309 | |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1310 | static int vlv_drpc_info(struct seq_file *m) |
| 1311 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1312 | struct drm_info_node *node = m->private; |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1313 | struct drm_device *dev = node->minor->dev; |
| 1314 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 6b312cd | 2014-11-19 20:07:42 +0200 | [diff] [blame] | 1315 | u32 rpmodectl1, rcctl1, pw_status; |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1316 | |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 1317 | intel_runtime_pm_get(dev_priv); |
| 1318 | |
Ville Syrjälä | 6b312cd | 2014-11-19 20:07:42 +0200 | [diff] [blame] | 1319 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1320 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
| 1321 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
| 1322 | |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 1323 | intel_runtime_pm_put(dev_priv); |
| 1324 | |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1325 | seq_printf(m, "Video Turbo Mode: %s\n", |
| 1326 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); |
| 1327 | seq_printf(m, "Turbo enabled: %s\n", |
| 1328 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); |
| 1329 | seq_printf(m, "HW control enabled: %s\n", |
| 1330 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); |
| 1331 | seq_printf(m, "SW control enabled: %s\n", |
| 1332 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == |
| 1333 | GEN6_RP_MEDIA_SW_MODE)); |
| 1334 | seq_printf(m, "RC6 Enabled: %s\n", |
| 1335 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | |
| 1336 | GEN6_RC_CTL_EI_MODE(1)))); |
| 1337 | seq_printf(m, "Render Power Well: %s\n", |
Ville Syrjälä | 6b312cd | 2014-11-19 20:07:42 +0200 | [diff] [blame] | 1338 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1339 | seq_printf(m, "Media Power Well: %s\n", |
Ville Syrjälä | 6b312cd | 2014-11-19 20:07:42 +0200 | [diff] [blame] | 1340 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1341 | |
Imre Deak | 9cc19be | 2014-04-14 20:24:24 +0300 | [diff] [blame] | 1342 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
| 1343 | I915_READ(VLV_GT_RENDER_RC6)); |
| 1344 | seq_printf(m, "Media RC6 residency since boot: %u\n", |
| 1345 | I915_READ(VLV_GT_MEDIA_RC6)); |
| 1346 | |
Mika Kuoppala | f65367b | 2015-01-16 11:34:42 +0200 | [diff] [blame] | 1347 | return i915_forcewake_domains(m, NULL); |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1348 | } |
| 1349 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1350 | static int gen6_drpc_info(struct seq_file *m) |
| 1351 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1352 | struct drm_info_node *node = m->private; |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1353 | struct drm_device *dev = node->minor->dev; |
| 1354 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | ecd8fae | 2012-09-26 10:34:02 -0700 | [diff] [blame] | 1355 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
Daniel Vetter | 93b525d | 2012-01-25 13:52:43 +0100 | [diff] [blame] | 1356 | unsigned forcewake_count; |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 1357 | int count = 0, ret; |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1358 | |
| 1359 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1360 | if (ret) |
| 1361 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1362 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1363 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1364 | spin_lock_irq(&dev_priv->uncore.lock); |
Chris Wilson | b2cff0d | 2015-01-16 11:34:37 +0200 | [diff] [blame] | 1365 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1366 | spin_unlock_irq(&dev_priv->uncore.lock); |
Daniel Vetter | 93b525d | 2012-01-25 13:52:43 +0100 | [diff] [blame] | 1367 | |
| 1368 | if (forcewake_count) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1369 | seq_puts(m, "RC information inaccurate because somebody " |
| 1370 | "holds a forcewake reference \n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1371 | } else { |
| 1372 | /* NB: we cannot use forcewake, else we read the wrong values */ |
| 1373 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) |
| 1374 | udelay(10); |
| 1375 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); |
| 1376 | } |
| 1377 | |
| 1378 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); |
Chris Wilson | ed71f1b | 2013-07-19 20:36:56 +0100 | [diff] [blame] | 1379 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1380 | |
| 1381 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
| 1382 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
| 1383 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | 44cbd33 | 2012-11-06 14:36:36 +0000 | [diff] [blame] | 1384 | mutex_lock(&dev_priv->rps.hw_lock); |
| 1385 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
| 1386 | mutex_unlock(&dev_priv->rps.hw_lock); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1387 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1388 | intel_runtime_pm_put(dev_priv); |
| 1389 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1390 | seq_printf(m, "Video Turbo Mode: %s\n", |
| 1391 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); |
| 1392 | seq_printf(m, "HW control enabled: %s\n", |
| 1393 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); |
| 1394 | seq_printf(m, "SW control enabled: %s\n", |
| 1395 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == |
| 1396 | GEN6_RP_MEDIA_SW_MODE)); |
Eric Anholt | fff24e2 | 2012-01-23 16:14:05 -0800 | [diff] [blame] | 1397 | seq_printf(m, "RC1e Enabled: %s\n", |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1398 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
| 1399 | seq_printf(m, "RC6 Enabled: %s\n", |
| 1400 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); |
| 1401 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
| 1402 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); |
| 1403 | seq_printf(m, "Deepest RC6 Enabled: %s\n", |
| 1404 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1405 | seq_puts(m, "Current RC state: "); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1406 | switch (gt_core_status & GEN6_RCn_MASK) { |
| 1407 | case GEN6_RC0: |
| 1408 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1409 | seq_puts(m, "Core Power Down\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1410 | else |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1411 | seq_puts(m, "on\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1412 | break; |
| 1413 | case GEN6_RC3: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1414 | seq_puts(m, "RC3\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1415 | break; |
| 1416 | case GEN6_RC6: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1417 | seq_puts(m, "RC6\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1418 | break; |
| 1419 | case GEN6_RC7: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1420 | seq_puts(m, "RC7\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1421 | break; |
| 1422 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1423 | seq_puts(m, "Unknown\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1424 | break; |
| 1425 | } |
| 1426 | |
| 1427 | seq_printf(m, "Core Power Down: %s\n", |
| 1428 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); |
Ben Widawsky | cce66a2 | 2012-03-27 18:59:38 -0700 | [diff] [blame] | 1429 | |
| 1430 | /* Not exactly sure what this is */ |
| 1431 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", |
| 1432 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); |
| 1433 | seq_printf(m, "RC6 residency since boot: %u\n", |
| 1434 | I915_READ(GEN6_GT_GFX_RC6)); |
| 1435 | seq_printf(m, "RC6+ residency since boot: %u\n", |
| 1436 | I915_READ(GEN6_GT_GFX_RC6p)); |
| 1437 | seq_printf(m, "RC6++ residency since boot: %u\n", |
| 1438 | I915_READ(GEN6_GT_GFX_RC6pp)); |
| 1439 | |
Ben Widawsky | ecd8fae | 2012-09-26 10:34:02 -0700 | [diff] [blame] | 1440 | seq_printf(m, "RC6 voltage: %dmV\n", |
| 1441 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); |
| 1442 | seq_printf(m, "RC6+ voltage: %dmV\n", |
| 1443 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); |
| 1444 | seq_printf(m, "RC6++ voltage: %dmV\n", |
| 1445 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1446 | return 0; |
| 1447 | } |
| 1448 | |
| 1449 | static int i915_drpc_info(struct seq_file *m, void *unused) |
| 1450 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1451 | struct drm_info_node *node = m->private; |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1452 | struct drm_device *dev = node->minor->dev; |
| 1453 | |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1454 | if (IS_VALLEYVIEW(dev)) |
| 1455 | return vlv_drpc_info(m); |
Vedang Patel | ac66cf4 | 2014-08-26 10:42:51 -0700 | [diff] [blame] | 1456 | else if (INTEL_INFO(dev)->gen >= 6) |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1457 | return gen6_drpc_info(m); |
| 1458 | else |
| 1459 | return ironlake_drpc_info(m); |
| 1460 | } |
| 1461 | |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1462 | static int i915_fbc_status(struct seq_file *m, void *unused) |
| 1463 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1464 | struct drm_info_node *node = m->private; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1465 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1466 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1467 | |
Daniel Vetter | 3a77c4c | 2014-01-10 08:50:12 +0100 | [diff] [blame] | 1468 | if (!HAS_FBC(dev)) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1469 | seq_puts(m, "FBC unsupported on this chipset\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1470 | return 0; |
| 1471 | } |
| 1472 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1473 | intel_runtime_pm_get(dev_priv); |
| 1474 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1475 | if (intel_fbc_enabled(dev)) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1476 | seq_puts(m, "FBC enabled\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1477 | } else { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1478 | seq_puts(m, "FBC disabled: "); |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 1479 | switch (dev_priv->fbc.no_fbc_reason) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 1480 | case FBC_OK: |
| 1481 | seq_puts(m, "FBC actived, but currently disabled in hardware"); |
| 1482 | break; |
| 1483 | case FBC_UNSUPPORTED: |
| 1484 | seq_puts(m, "unsupported by this chipset"); |
| 1485 | break; |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1486 | case FBC_NO_OUTPUT: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1487 | seq_puts(m, "no outputs"); |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1488 | break; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1489 | case FBC_STOLEN_TOO_SMALL: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1490 | seq_puts(m, "not enough stolen memory"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1491 | break; |
| 1492 | case FBC_UNSUPPORTED_MODE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1493 | seq_puts(m, "mode not supported"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1494 | break; |
| 1495 | case FBC_MODE_TOO_LARGE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1496 | seq_puts(m, "mode too large"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1497 | break; |
| 1498 | case FBC_BAD_PLANE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1499 | seq_puts(m, "FBC unsupported on plane"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1500 | break; |
| 1501 | case FBC_NOT_TILED: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1502 | seq_puts(m, "scanout buffer not tiled"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1503 | break; |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1504 | case FBC_MULTIPLE_PIPES: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1505 | seq_puts(m, "multiple pipes are enabled"); |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1506 | break; |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 1507 | case FBC_MODULE_PARAM: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1508 | seq_puts(m, "disabled per module param (default off)"); |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 1509 | break; |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 1510 | case FBC_CHIP_DEFAULT: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1511 | seq_puts(m, "disabled per chip default"); |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 1512 | break; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1513 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1514 | seq_puts(m, "unknown reason"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1515 | } |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1516 | seq_putc(m, '\n'); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1517 | } |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1518 | |
| 1519 | intel_runtime_pm_put(dev_priv); |
| 1520 | |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1521 | return 0; |
| 1522 | } |
| 1523 | |
Rodrigo Vivi | da46f93 | 2014-08-01 02:04:45 -0700 | [diff] [blame] | 1524 | static int i915_fbc_fc_get(void *data, u64 *val) |
| 1525 | { |
| 1526 | struct drm_device *dev = data; |
| 1527 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1528 | |
| 1529 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) |
| 1530 | return -ENODEV; |
| 1531 | |
| 1532 | drm_modeset_lock_all(dev); |
| 1533 | *val = dev_priv->fbc.false_color; |
| 1534 | drm_modeset_unlock_all(dev); |
| 1535 | |
| 1536 | return 0; |
| 1537 | } |
| 1538 | |
| 1539 | static int i915_fbc_fc_set(void *data, u64 val) |
| 1540 | { |
| 1541 | struct drm_device *dev = data; |
| 1542 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1543 | u32 reg; |
| 1544 | |
| 1545 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) |
| 1546 | return -ENODEV; |
| 1547 | |
| 1548 | drm_modeset_lock_all(dev); |
| 1549 | |
| 1550 | reg = I915_READ(ILK_DPFC_CONTROL); |
| 1551 | dev_priv->fbc.false_color = val; |
| 1552 | |
| 1553 | I915_WRITE(ILK_DPFC_CONTROL, val ? |
| 1554 | (reg | FBC_CTL_FALSE_COLOR) : |
| 1555 | (reg & ~FBC_CTL_FALSE_COLOR)); |
| 1556 | |
| 1557 | drm_modeset_unlock_all(dev); |
| 1558 | return 0; |
| 1559 | } |
| 1560 | |
| 1561 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, |
| 1562 | i915_fbc_fc_get, i915_fbc_fc_set, |
| 1563 | "%llu\n"); |
| 1564 | |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1565 | static int i915_ips_status(struct seq_file *m, void *unused) |
| 1566 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1567 | struct drm_info_node *node = m->private; |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1568 | struct drm_device *dev = node->minor->dev; |
| 1569 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1570 | |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 1571 | if (!HAS_IPS(dev)) { |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1572 | seq_puts(m, "not supported\n"); |
| 1573 | return 0; |
| 1574 | } |
| 1575 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1576 | intel_runtime_pm_get(dev_priv); |
| 1577 | |
Rodrigo Vivi | 0eaa53f | 2014-06-30 04:45:01 -0700 | [diff] [blame] | 1578 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
| 1579 | yesno(i915.enable_ips)); |
| 1580 | |
| 1581 | if (INTEL_INFO(dev)->gen >= 8) { |
| 1582 | seq_puts(m, "Currently: unknown\n"); |
| 1583 | } else { |
| 1584 | if (I915_READ(IPS_CTL) & IPS_ENABLE) |
| 1585 | seq_puts(m, "Currently: enabled\n"); |
| 1586 | else |
| 1587 | seq_puts(m, "Currently: disabled\n"); |
| 1588 | } |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1589 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1590 | intel_runtime_pm_put(dev_priv); |
| 1591 | |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1592 | return 0; |
| 1593 | } |
| 1594 | |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1595 | static int i915_sr_status(struct seq_file *m, void *unused) |
| 1596 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1597 | struct drm_info_node *node = m->private; |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1598 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1599 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1600 | bool sr_enabled = false; |
| 1601 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1602 | intel_runtime_pm_get(dev_priv); |
| 1603 | |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 1604 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 5ba2aaa | 2010-08-19 18:04:08 +0100 | [diff] [blame] | 1605 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1606 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1607 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
| 1608 | else if (IS_I915GM(dev)) |
| 1609 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
| 1610 | else if (IS_PINEVIEW(dev)) |
| 1611 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
| 1612 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1613 | intel_runtime_pm_put(dev_priv); |
| 1614 | |
Chris Wilson | 5ba2aaa | 2010-08-19 18:04:08 +0100 | [diff] [blame] | 1615 | seq_printf(m, "self-refresh: %s\n", |
| 1616 | sr_enabled ? "enabled" : "disabled"); |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1617 | |
| 1618 | return 0; |
| 1619 | } |
| 1620 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1621 | static int i915_emon_status(struct seq_file *m, void *unused) |
| 1622 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1623 | struct drm_info_node *node = m->private; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1624 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1625 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1626 | unsigned long temp, chipset, gfx; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1627 | int ret; |
| 1628 | |
Chris Wilson | 582be6b | 2012-04-30 19:35:02 +0100 | [diff] [blame] | 1629 | if (!IS_GEN5(dev)) |
| 1630 | return -ENODEV; |
| 1631 | |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1632 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1633 | if (ret) |
| 1634 | return ret; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1635 | |
| 1636 | temp = i915_mch_val(dev_priv); |
| 1637 | chipset = i915_chipset_val(dev_priv); |
| 1638 | gfx = i915_gfx_val(dev_priv); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1639 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1640 | |
| 1641 | seq_printf(m, "GMCH temp: %ld\n", temp); |
| 1642 | seq_printf(m, "Chipset power: %ld\n", chipset); |
| 1643 | seq_printf(m, "GFX power: %ld\n", gfx); |
| 1644 | seq_printf(m, "Total power: %ld\n", chipset + gfx); |
| 1645 | |
| 1646 | return 0; |
| 1647 | } |
| 1648 | |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1649 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
| 1650 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1651 | struct drm_info_node *node = m->private; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1652 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1653 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1654 | int ret = 0; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1655 | int gpu_freq, ia_freq; |
| 1656 | |
Jesse Barnes | 1c70c0c | 2011-06-29 13:34:36 -0700 | [diff] [blame] | 1657 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1658 | seq_puts(m, "unsupported on this chipset\n"); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1659 | return 0; |
| 1660 | } |
| 1661 | |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1662 | intel_runtime_pm_get(dev_priv); |
| 1663 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 1664 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 1665 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1666 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1667 | if (ret) |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1668 | goto out; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1669 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1670 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1671 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1672 | for (gpu_freq = dev_priv->rps.min_freq_softlimit; |
| 1673 | gpu_freq <= dev_priv->rps.max_freq_softlimit; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1674 | gpu_freq++) { |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 1675 | ia_freq = gpu_freq; |
| 1676 | sandybridge_pcode_read(dev_priv, |
| 1677 | GEN6_PCODE_READ_MIN_FREQ_TABLE, |
| 1678 | &ia_freq); |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 1679 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
| 1680 | gpu_freq * GT_FREQUENCY_MULTIPLIER, |
| 1681 | ((ia_freq >> 0) & 0xff) * 100, |
| 1682 | ((ia_freq >> 8) & 0xff) * 100); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1683 | } |
| 1684 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1685 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1686 | |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1687 | out: |
| 1688 | intel_runtime_pm_put(dev_priv); |
| 1689 | return ret; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1690 | } |
| 1691 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1692 | static int i915_opregion(struct seq_file *m, void *unused) |
| 1693 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1694 | struct drm_info_node *node = m->private; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1695 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1696 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1697 | struct intel_opregion *opregion = &dev_priv->opregion; |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1698 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1699 | int ret; |
| 1700 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1701 | if (data == NULL) |
| 1702 | return -ENOMEM; |
| 1703 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1704 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1705 | if (ret) |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1706 | goto out; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1707 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1708 | if (opregion->header) { |
| 1709 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); |
| 1710 | seq_write(m, data, OPREGION_SIZE); |
| 1711 | } |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1712 | |
| 1713 | mutex_unlock(&dev->struct_mutex); |
| 1714 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1715 | out: |
| 1716 | kfree(data); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1717 | return 0; |
| 1718 | } |
| 1719 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1720 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
| 1721 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1722 | struct drm_info_node *node = m->private; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1723 | struct drm_device *dev = node->minor->dev; |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1724 | struct intel_fbdev *ifbdev = NULL; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1725 | struct intel_framebuffer *fb; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1726 | |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1727 | #ifdef CONFIG_DRM_I915_FBDEV |
| 1728 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1729 | |
| 1730 | ifbdev = dev_priv->fbdev; |
| 1731 | fb = to_intel_framebuffer(ifbdev->helper.fb); |
| 1732 | |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1733 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1734 | fb->base.width, |
| 1735 | fb->base.height, |
| 1736 | fb->base.depth, |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1737 | fb->base.bits_per_pixel, |
| 1738 | atomic_read(&fb->base.refcount.refcount)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1739 | describe_obj(m, fb->obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1740 | seq_putc(m, '\n'); |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1741 | #endif |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1742 | |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1743 | mutex_lock(&dev->mode_config.fb_lock); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1744 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
Daniel Vetter | 131a56d | 2013-10-17 14:35:31 +0200 | [diff] [blame] | 1745 | if (ifbdev && &fb->base == ifbdev->helper.fb) |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1746 | continue; |
| 1747 | |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1748 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1749 | fb->base.width, |
| 1750 | fb->base.height, |
| 1751 | fb->base.depth, |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1752 | fb->base.bits_per_pixel, |
| 1753 | atomic_read(&fb->base.refcount.refcount)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1754 | describe_obj(m, fb->obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1755 | seq_putc(m, '\n'); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1756 | } |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1757 | mutex_unlock(&dev->mode_config.fb_lock); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1758 | |
| 1759 | return 0; |
| 1760 | } |
| 1761 | |
Oscar Mateo | c9fe99b | 2014-07-24 17:04:46 +0100 | [diff] [blame] | 1762 | static void describe_ctx_ringbuf(struct seq_file *m, |
| 1763 | struct intel_ringbuffer *ringbuf) |
| 1764 | { |
| 1765 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", |
| 1766 | ringbuf->space, ringbuf->head, ringbuf->tail, |
| 1767 | ringbuf->last_retired_head); |
| 1768 | } |
| 1769 | |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1770 | static int i915_context_status(struct seq_file *m, void *unused) |
| 1771 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1772 | struct drm_info_node *node = m->private; |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1773 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1774 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1775 | struct intel_engine_cs *ring; |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 1776 | struct intel_context *ctx; |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 1777 | int ret, i; |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1778 | |
Daniel Vetter | f3d2887 | 2014-05-29 23:23:08 +0200 | [diff] [blame] | 1779 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1780 | if (ret) |
| 1781 | return ret; |
| 1782 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1783 | if (dev_priv->ips.pwrctx) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1784 | seq_puts(m, "power context "); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1785 | describe_obj(m, dev_priv->ips.pwrctx); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1786 | seq_putc(m, '\n'); |
Ben Widawsky | dc501fb | 2011-06-29 11:41:51 -0700 | [diff] [blame] | 1787 | } |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1788 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1789 | if (dev_priv->ips.renderctx) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1790 | seq_puts(m, "render context "); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1791 | describe_obj(m, dev_priv->ips.renderctx); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1792 | seq_putc(m, '\n'); |
Ben Widawsky | dc501fb | 2011-06-29 11:41:51 -0700 | [diff] [blame] | 1793 | } |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1794 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1795 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
Oscar Mateo | c9fe99b | 2014-07-24 17:04:46 +0100 | [diff] [blame] | 1796 | if (!i915.enable_execlists && |
| 1797 | ctx->legacy_hw_ctx.rcs_state == NULL) |
Chris Wilson | b77f699 | 2014-04-30 08:30:00 +0100 | [diff] [blame] | 1798 | continue; |
| 1799 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1800 | seq_puts(m, "HW context "); |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 1801 | describe_ctx(m, ctx); |
Oscar Mateo | c9fe99b | 2014-07-24 17:04:46 +0100 | [diff] [blame] | 1802 | for_each_ring(ring, dev_priv, i) { |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1803 | if (ring->default_context == ctx) |
Oscar Mateo | c9fe99b | 2014-07-24 17:04:46 +0100 | [diff] [blame] | 1804 | seq_printf(m, "(default context %s) ", |
| 1805 | ring->name); |
| 1806 | } |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1807 | |
Oscar Mateo | c9fe99b | 2014-07-24 17:04:46 +0100 | [diff] [blame] | 1808 | if (i915.enable_execlists) { |
| 1809 | seq_putc(m, '\n'); |
| 1810 | for_each_ring(ring, dev_priv, i) { |
| 1811 | struct drm_i915_gem_object *ctx_obj = |
| 1812 | ctx->engine[i].state; |
| 1813 | struct intel_ringbuffer *ringbuf = |
| 1814 | ctx->engine[i].ringbuf; |
| 1815 | |
| 1816 | seq_printf(m, "%s: ", ring->name); |
| 1817 | if (ctx_obj) |
| 1818 | describe_obj(m, ctx_obj); |
| 1819 | if (ringbuf) |
| 1820 | describe_ctx_ringbuf(m, ringbuf); |
| 1821 | seq_putc(m, '\n'); |
| 1822 | } |
| 1823 | } else { |
| 1824 | describe_obj(m, ctx->legacy_hw_ctx.rcs_state); |
| 1825 | } |
| 1826 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1827 | seq_putc(m, '\n'); |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 1828 | } |
| 1829 | |
Daniel Vetter | f3d2887 | 2014-05-29 23:23:08 +0200 | [diff] [blame] | 1830 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1831 | |
| 1832 | return 0; |
| 1833 | } |
| 1834 | |
Thomas Daniel | 064ca1d | 2014-12-02 13:21:18 +0000 | [diff] [blame] | 1835 | static void i915_dump_lrc_obj(struct seq_file *m, |
| 1836 | struct intel_engine_cs *ring, |
| 1837 | struct drm_i915_gem_object *ctx_obj) |
| 1838 | { |
| 1839 | struct page *page; |
| 1840 | uint32_t *reg_state; |
| 1841 | int j; |
| 1842 | unsigned long ggtt_offset = 0; |
| 1843 | |
| 1844 | if (ctx_obj == NULL) { |
| 1845 | seq_printf(m, "Context on %s with no gem object\n", |
| 1846 | ring->name); |
| 1847 | return; |
| 1848 | } |
| 1849 | |
| 1850 | seq_printf(m, "CONTEXT: %s %u\n", ring->name, |
| 1851 | intel_execlists_ctx_id(ctx_obj)); |
| 1852 | |
| 1853 | if (!i915_gem_obj_ggtt_bound(ctx_obj)) |
| 1854 | seq_puts(m, "\tNot bound in GGTT\n"); |
| 1855 | else |
| 1856 | ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj); |
| 1857 | |
| 1858 | if (i915_gem_object_get_pages(ctx_obj)) { |
| 1859 | seq_puts(m, "\tFailed to get pages for context object\n"); |
| 1860 | return; |
| 1861 | } |
| 1862 | |
| 1863 | page = i915_gem_object_get_page(ctx_obj, 1); |
| 1864 | if (!WARN_ON(page == NULL)) { |
| 1865 | reg_state = kmap_atomic(page); |
| 1866 | |
| 1867 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { |
| 1868 | seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 1869 | ggtt_offset + 4096 + (j * 4), |
| 1870 | reg_state[j], reg_state[j + 1], |
| 1871 | reg_state[j + 2], reg_state[j + 3]); |
| 1872 | } |
| 1873 | kunmap_atomic(reg_state); |
| 1874 | } |
| 1875 | |
| 1876 | seq_putc(m, '\n'); |
| 1877 | } |
| 1878 | |
Ben Widawsky | c0ab1ae | 2014-08-07 13:24:26 +0100 | [diff] [blame] | 1879 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
| 1880 | { |
| 1881 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1882 | struct drm_device *dev = node->minor->dev; |
| 1883 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1884 | struct intel_engine_cs *ring; |
| 1885 | struct intel_context *ctx; |
| 1886 | int ret, i; |
| 1887 | |
| 1888 | if (!i915.enable_execlists) { |
| 1889 | seq_printf(m, "Logical Ring Contexts are disabled\n"); |
| 1890 | return 0; |
| 1891 | } |
| 1892 | |
| 1893 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1894 | if (ret) |
| 1895 | return ret; |
| 1896 | |
| 1897 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
| 1898 | for_each_ring(ring, dev_priv, i) { |
Thomas Daniel | 064ca1d | 2014-12-02 13:21:18 +0000 | [diff] [blame] | 1899 | if (ring->default_context != ctx) |
| 1900 | i915_dump_lrc_obj(m, ring, |
| 1901 | ctx->engine[i].state); |
Ben Widawsky | c0ab1ae | 2014-08-07 13:24:26 +0100 | [diff] [blame] | 1902 | } |
| 1903 | } |
| 1904 | |
| 1905 | mutex_unlock(&dev->struct_mutex); |
| 1906 | |
| 1907 | return 0; |
| 1908 | } |
| 1909 | |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 1910 | static int i915_execlists(struct seq_file *m, void *data) |
| 1911 | { |
| 1912 | struct drm_info_node *node = (struct drm_info_node *)m->private; |
| 1913 | struct drm_device *dev = node->minor->dev; |
| 1914 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1915 | struct intel_engine_cs *ring; |
| 1916 | u32 status_pointer; |
| 1917 | u8 read_pointer; |
| 1918 | u8 write_pointer; |
| 1919 | u32 status; |
| 1920 | u32 ctx_id; |
| 1921 | struct list_head *cursor; |
| 1922 | int ring_id, i; |
| 1923 | int ret; |
| 1924 | |
| 1925 | if (!i915.enable_execlists) { |
| 1926 | seq_puts(m, "Logical Ring Contexts are disabled\n"); |
| 1927 | return 0; |
| 1928 | } |
| 1929 | |
| 1930 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1931 | if (ret) |
| 1932 | return ret; |
| 1933 | |
Michel Thierry | fc0412e | 2014-10-16 16:13:38 +0100 | [diff] [blame] | 1934 | intel_runtime_pm_get(dev_priv); |
| 1935 | |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 1936 | for_each_ring(ring, dev_priv, ring_id) { |
Nick Hoath | 6d3d827 | 2015-01-15 13:10:39 +0000 | [diff] [blame] | 1937 | struct drm_i915_gem_request *head_req = NULL; |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 1938 | int count = 0; |
| 1939 | unsigned long flags; |
| 1940 | |
| 1941 | seq_printf(m, "%s\n", ring->name); |
| 1942 | |
| 1943 | status = I915_READ(RING_EXECLIST_STATUS(ring)); |
| 1944 | ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4); |
| 1945 | seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n", |
| 1946 | status, ctx_id); |
| 1947 | |
| 1948 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); |
| 1949 | seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer); |
| 1950 | |
| 1951 | read_pointer = ring->next_context_status_buffer; |
| 1952 | write_pointer = status_pointer & 0x07; |
| 1953 | if (read_pointer > write_pointer) |
| 1954 | write_pointer += 6; |
| 1955 | seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n", |
| 1956 | read_pointer, write_pointer); |
| 1957 | |
| 1958 | for (i = 0; i < 6; i++) { |
| 1959 | status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i); |
| 1960 | ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4); |
| 1961 | |
| 1962 | seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n", |
| 1963 | i, status, ctx_id); |
| 1964 | } |
| 1965 | |
| 1966 | spin_lock_irqsave(&ring->execlist_lock, flags); |
| 1967 | list_for_each(cursor, &ring->execlist_queue) |
| 1968 | count++; |
| 1969 | head_req = list_first_entry_or_null(&ring->execlist_queue, |
Nick Hoath | 6d3d827 | 2015-01-15 13:10:39 +0000 | [diff] [blame] | 1970 | struct drm_i915_gem_request, execlist_link); |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 1971 | spin_unlock_irqrestore(&ring->execlist_lock, flags); |
| 1972 | |
| 1973 | seq_printf(m, "\t%d requests in queue\n", count); |
| 1974 | if (head_req) { |
| 1975 | struct drm_i915_gem_object *ctx_obj; |
| 1976 | |
Nick Hoath | 6d3d827 | 2015-01-15 13:10:39 +0000 | [diff] [blame] | 1977 | ctx_obj = head_req->ctx->engine[ring_id].state; |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 1978 | seq_printf(m, "\tHead request id: %u\n", |
| 1979 | intel_execlists_ctx_id(ctx_obj)); |
| 1980 | seq_printf(m, "\tHead request tail: %u\n", |
Nick Hoath | 6d3d827 | 2015-01-15 13:10:39 +0000 | [diff] [blame] | 1981 | head_req->tail); |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 1982 | } |
| 1983 | |
| 1984 | seq_putc(m, '\n'); |
| 1985 | } |
| 1986 | |
Michel Thierry | fc0412e | 2014-10-16 16:13:38 +0100 | [diff] [blame] | 1987 | intel_runtime_pm_put(dev_priv); |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 1988 | mutex_unlock(&dev->struct_mutex); |
| 1989 | |
| 1990 | return 0; |
| 1991 | } |
| 1992 | |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1993 | static const char *swizzle_string(unsigned swizzle) |
| 1994 | { |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 1995 | switch (swizzle) { |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1996 | case I915_BIT_6_SWIZZLE_NONE: |
| 1997 | return "none"; |
| 1998 | case I915_BIT_6_SWIZZLE_9: |
| 1999 | return "bit9"; |
| 2000 | case I915_BIT_6_SWIZZLE_9_10: |
| 2001 | return "bit9/bit10"; |
| 2002 | case I915_BIT_6_SWIZZLE_9_11: |
| 2003 | return "bit9/bit11"; |
| 2004 | case I915_BIT_6_SWIZZLE_9_10_11: |
| 2005 | return "bit9/bit10/bit11"; |
| 2006 | case I915_BIT_6_SWIZZLE_9_17: |
| 2007 | return "bit9/bit17"; |
| 2008 | case I915_BIT_6_SWIZZLE_9_10_17: |
| 2009 | return "bit9/bit10/bit17"; |
| 2010 | case I915_BIT_6_SWIZZLE_UNKNOWN: |
Masanari Iida | 8a168ca | 2012-12-29 02:00:09 +0900 | [diff] [blame] | 2011 | return "unknown"; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2012 | } |
| 2013 | |
| 2014 | return "bug"; |
| 2015 | } |
| 2016 | |
| 2017 | static int i915_swizzle_info(struct seq_file *m, void *data) |
| 2018 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2019 | struct drm_info_node *node = m->private; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2020 | struct drm_device *dev = node->minor->dev; |
| 2021 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 2022 | int ret; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2023 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 2024 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2025 | if (ret) |
| 2026 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2027 | intel_runtime_pm_get(dev_priv); |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 2028 | |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2029 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
| 2030 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); |
| 2031 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", |
| 2032 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); |
| 2033 | |
| 2034 | if (IS_GEN3(dev) || IS_GEN4(dev)) { |
| 2035 | seq_printf(m, "DDC = 0x%08x\n", |
| 2036 | I915_READ(DCC)); |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 2037 | seq_printf(m, "DDC2 = 0x%08x\n", |
| 2038 | I915_READ(DCC2)); |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2039 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
| 2040 | I915_READ16(C0DRB3)); |
| 2041 | seq_printf(m, "C1DRB3 = 0x%04x\n", |
| 2042 | I915_READ16(C1DRB3)); |
Ben Widawsky | 9d3203e | 2013-11-02 21:07:14 -0700 | [diff] [blame] | 2043 | } else if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | 3fa7d23 | 2012-01-31 16:47:56 +0100 | [diff] [blame] | 2044 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
| 2045 | I915_READ(MAD_DIMM_C0)); |
| 2046 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", |
| 2047 | I915_READ(MAD_DIMM_C1)); |
| 2048 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", |
| 2049 | I915_READ(MAD_DIMM_C2)); |
| 2050 | seq_printf(m, "TILECTL = 0x%08x\n", |
| 2051 | I915_READ(TILECTL)); |
Robert Beckett | 5907f5f | 2014-01-23 14:23:14 +0000 | [diff] [blame] | 2052 | if (INTEL_INFO(dev)->gen >= 8) |
Ben Widawsky | 9d3203e | 2013-11-02 21:07:14 -0700 | [diff] [blame] | 2053 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
| 2054 | I915_READ(GAMTARBMODE)); |
| 2055 | else |
| 2056 | seq_printf(m, "ARB_MODE = 0x%08x\n", |
| 2057 | I915_READ(ARB_MODE)); |
Daniel Vetter | 3fa7d23 | 2012-01-31 16:47:56 +0100 | [diff] [blame] | 2058 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
| 2059 | I915_READ(DISP_ARB_CTL)); |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2060 | } |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 2061 | |
| 2062 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) |
| 2063 | seq_puts(m, "L-shaped memory detected\n"); |
| 2064 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2065 | intel_runtime_pm_put(dev_priv); |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2066 | mutex_unlock(&dev->struct_mutex); |
| 2067 | |
| 2068 | return 0; |
| 2069 | } |
| 2070 | |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2071 | static int per_file_ctx(int id, void *ptr, void *data) |
| 2072 | { |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 2073 | struct intel_context *ctx = ptr; |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2074 | struct seq_file *m = data; |
Daniel Vetter | ae6c480 | 2014-08-06 15:04:53 +0200 | [diff] [blame] | 2075 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
| 2076 | |
| 2077 | if (!ppgtt) { |
| 2078 | seq_printf(m, " no ppgtt for context %d\n", |
| 2079 | ctx->user_handle); |
| 2080 | return 0; |
| 2081 | } |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2082 | |
Oscar Mateo | f83d651 | 2014-05-22 14:13:38 +0100 | [diff] [blame] | 2083 | if (i915_gem_context_is_default(ctx)) |
| 2084 | seq_puts(m, " default context:\n"); |
| 2085 | else |
Oscar Mateo | 821d66d | 2014-07-03 16:28:00 +0100 | [diff] [blame] | 2086 | seq_printf(m, " context %d:\n", ctx->user_handle); |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2087 | ppgtt->debug_dump(ppgtt, m); |
| 2088 | |
| 2089 | return 0; |
| 2090 | } |
| 2091 | |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2092 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2093 | { |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2094 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2095 | struct intel_engine_cs *ring; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2096 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 2097 | int unused, i; |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2098 | |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2099 | if (!ppgtt) |
| 2100 | return; |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2101 | |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2102 | seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages); |
Ben Widawsky | 5abbcca | 2014-02-21 13:06:34 -0800 | [diff] [blame] | 2103 | seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2104 | for_each_ring(ring, dev_priv, unused) { |
| 2105 | seq_printf(m, "%s\n", ring->name); |
| 2106 | for (i = 0; i < 4; i++) { |
| 2107 | u32 offset = 0x270 + i * 8; |
| 2108 | u64 pdp = I915_READ(ring->mmio_base + offset + 4); |
| 2109 | pdp <<= 32; |
| 2110 | pdp |= I915_READ(ring->mmio_base + offset); |
Ville Syrjälä | a2a5b15 | 2014-03-31 18:17:16 +0300 | [diff] [blame] | 2111 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2112 | } |
| 2113 | } |
| 2114 | } |
| 2115 | |
| 2116 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
| 2117 | { |
| 2118 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2119 | struct intel_engine_cs *ring; |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2120 | struct drm_file *file; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2121 | int i; |
| 2122 | |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2123 | if (INTEL_INFO(dev)->gen == 6) |
| 2124 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
| 2125 | |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 2126 | for_each_ring(ring, dev_priv, i) { |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2127 | seq_printf(m, "%s\n", ring->name); |
| 2128 | if (INTEL_INFO(dev)->gen == 7) |
| 2129 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); |
| 2130 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); |
| 2131 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); |
| 2132 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); |
| 2133 | } |
| 2134 | if (dev_priv->mm.aliasing_ppgtt) { |
| 2135 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 2136 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 2137 | seq_puts(m, "aliasing PPGTT:\n"); |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2138 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2139 | |
Ben Widawsky | 87d60b6 | 2013-12-06 14:11:29 -0800 | [diff] [blame] | 2140 | ppgtt->debug_dump(ppgtt, m); |
Daniel Vetter | ae6c480 | 2014-08-06 15:04:53 +0200 | [diff] [blame] | 2141 | } |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2142 | |
| 2143 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
| 2144 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2145 | |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2146 | seq_printf(m, "proc: %s\n", |
| 2147 | get_pid_task(file->pid, PIDTYPE_PID)->comm); |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2148 | idr_for_each(&file_priv->context_idr, per_file_ctx, m); |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2149 | } |
| 2150 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2151 | } |
| 2152 | |
| 2153 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
| 2154 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2155 | struct drm_info_node *node = m->private; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2156 | struct drm_device *dev = node->minor->dev; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2157 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2158 | |
| 2159 | int ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2160 | if (ret) |
| 2161 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2162 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2163 | |
| 2164 | if (INTEL_INFO(dev)->gen >= 8) |
| 2165 | gen8_ppgtt_info(m, dev); |
| 2166 | else if (INTEL_INFO(dev)->gen >= 6) |
| 2167 | gen6_ppgtt_info(m, dev); |
| 2168 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2169 | intel_runtime_pm_put(dev_priv); |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2170 | mutex_unlock(&dev->struct_mutex); |
| 2171 | |
| 2172 | return 0; |
| 2173 | } |
| 2174 | |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 2175 | static int i915_llc(struct seq_file *m, void *data) |
| 2176 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2177 | struct drm_info_node *node = m->private; |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 2178 | struct drm_device *dev = node->minor->dev; |
| 2179 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2180 | |
| 2181 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ |
| 2182 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); |
| 2183 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); |
| 2184 | |
| 2185 | return 0; |
| 2186 | } |
| 2187 | |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2188 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
| 2189 | { |
| 2190 | struct drm_info_node *node = m->private; |
| 2191 | struct drm_device *dev = node->minor->dev; |
| 2192 | struct drm_i915_private *dev_priv = dev->dev_private; |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 2193 | u32 psrperf = 0; |
Rodrigo Vivi | a6cbdb8 | 2014-11-14 08:52:40 -0800 | [diff] [blame] | 2194 | u32 stat[3]; |
| 2195 | enum pipe pipe; |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 2196 | bool enabled = false; |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2197 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2198 | intel_runtime_pm_get(dev_priv); |
| 2199 | |
Daniel Vetter | fa128fa | 2014-07-11 10:30:17 -0700 | [diff] [blame] | 2200 | mutex_lock(&dev_priv->psr.lock); |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 2201 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
| 2202 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); |
Daniel Vetter | 2807cf6 | 2014-07-11 10:30:11 -0700 | [diff] [blame] | 2203 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
Rodrigo Vivi | 5755c78 | 2014-06-12 10:16:45 -0700 | [diff] [blame] | 2204 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
Daniel Vetter | fa128fa | 2014-07-11 10:30:17 -0700 | [diff] [blame] | 2205 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
| 2206 | dev_priv->psr.busy_frontbuffer_bits); |
| 2207 | seq_printf(m, "Re-enable work scheduled: %s\n", |
| 2208 | yesno(work_busy(&dev_priv->psr.work.work))); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2209 | |
Rodrigo Vivi | a6cbdb8 | 2014-11-14 08:52:40 -0800 | [diff] [blame] | 2210 | if (HAS_PSR(dev)) { |
| 2211 | if (HAS_DDI(dev)) |
| 2212 | enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; |
| 2213 | else { |
| 2214 | for_each_pipe(dev_priv, pipe) { |
| 2215 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & |
| 2216 | VLV_EDP_PSR_CURR_STATE_MASK; |
| 2217 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || |
| 2218 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) |
| 2219 | enabled = true; |
| 2220 | } |
| 2221 | } |
| 2222 | } |
| 2223 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2224 | |
Rodrigo Vivi | a6cbdb8 | 2014-11-14 08:52:40 -0800 | [diff] [blame] | 2225 | if (!HAS_DDI(dev)) |
| 2226 | for_each_pipe(dev_priv, pipe) { |
| 2227 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || |
| 2228 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) |
| 2229 | seq_printf(m, " pipe %c", pipe_name(pipe)); |
| 2230 | } |
| 2231 | seq_puts(m, "\n"); |
| 2232 | |
Rodrigo Vivi | fb49581 | 2015-01-12 10:14:33 -0800 | [diff] [blame] | 2233 | seq_printf(m, "Link standby: %s\n", |
| 2234 | yesno((bool)dev_priv->psr.link_standby)); |
| 2235 | |
Rodrigo Vivi | a6cbdb8 | 2014-11-14 08:52:40 -0800 | [diff] [blame] | 2236 | /* CHV PSR has no kind of performance counter */ |
| 2237 | if (HAS_PSR(dev) && HAS_DDI(dev)) { |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 2238 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & |
| 2239 | EDP_PSR_PERF_CNT_MASK; |
Rodrigo Vivi | a6cbdb8 | 2014-11-14 08:52:40 -0800 | [diff] [blame] | 2240 | |
| 2241 | seq_printf(m, "Performance_Counter: %u\n", psrperf); |
| 2242 | } |
Daniel Vetter | fa128fa | 2014-07-11 10:30:17 -0700 | [diff] [blame] | 2243 | mutex_unlock(&dev_priv->psr.lock); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2244 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2245 | intel_runtime_pm_put(dev_priv); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2246 | return 0; |
| 2247 | } |
| 2248 | |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 2249 | static int i915_sink_crc(struct seq_file *m, void *data) |
| 2250 | { |
| 2251 | struct drm_info_node *node = m->private; |
| 2252 | struct drm_device *dev = node->minor->dev; |
| 2253 | struct intel_encoder *encoder; |
| 2254 | struct intel_connector *connector; |
| 2255 | struct intel_dp *intel_dp = NULL; |
| 2256 | int ret; |
| 2257 | u8 crc[6]; |
| 2258 | |
| 2259 | drm_modeset_lock_all(dev); |
| 2260 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 2261 | base.head) { |
| 2262 | |
| 2263 | if (connector->base.dpms != DRM_MODE_DPMS_ON) |
| 2264 | continue; |
| 2265 | |
Paulo Zanoni | b6ae3c7 | 2014-02-13 17:51:33 -0200 | [diff] [blame] | 2266 | if (!connector->base.encoder) |
| 2267 | continue; |
| 2268 | |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 2269 | encoder = to_intel_encoder(connector->base.encoder); |
| 2270 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 2271 | continue; |
| 2272 | |
| 2273 | intel_dp = enc_to_intel_dp(&encoder->base); |
| 2274 | |
| 2275 | ret = intel_dp_sink_crc(intel_dp, crc); |
| 2276 | if (ret) |
| 2277 | goto out; |
| 2278 | |
| 2279 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", |
| 2280 | crc[0], crc[1], crc[2], |
| 2281 | crc[3], crc[4], crc[5]); |
| 2282 | goto out; |
| 2283 | } |
| 2284 | ret = -ENODEV; |
| 2285 | out: |
| 2286 | drm_modeset_unlock_all(dev); |
| 2287 | return ret; |
| 2288 | } |
| 2289 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 2290 | static int i915_energy_uJ(struct seq_file *m, void *data) |
| 2291 | { |
| 2292 | struct drm_info_node *node = m->private; |
| 2293 | struct drm_device *dev = node->minor->dev; |
| 2294 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2295 | u64 power; |
| 2296 | u32 units; |
| 2297 | |
| 2298 | if (INTEL_INFO(dev)->gen < 6) |
| 2299 | return -ENODEV; |
| 2300 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 2301 | intel_runtime_pm_get(dev_priv); |
| 2302 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 2303 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
| 2304 | power = (power & 0x1f00) >> 8; |
| 2305 | units = 1000000 / (1 << power); /* convert to uJ */ |
| 2306 | power = I915_READ(MCH_SECP_NRG_STTS); |
| 2307 | power *= units; |
| 2308 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 2309 | intel_runtime_pm_put(dev_priv); |
| 2310 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 2311 | seq_printf(m, "%llu", (long long unsigned)power); |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2312 | |
| 2313 | return 0; |
| 2314 | } |
| 2315 | |
| 2316 | static int i915_pc8_status(struct seq_file *m, void *unused) |
| 2317 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2318 | struct drm_info_node *node = m->private; |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2319 | struct drm_device *dev = node->minor->dev; |
| 2320 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2321 | |
Zhenyu Wang | 85b8d5c | 2014-04-01 19:39:48 -0300 | [diff] [blame] | 2322 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2323 | seq_puts(m, "not supported\n"); |
| 2324 | return 0; |
| 2325 | } |
| 2326 | |
Paulo Zanoni | 86c4ec0 | 2014-02-21 13:52:24 -0300 | [diff] [blame] | 2327 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2328 | seq_printf(m, "IRQs disabled: %s\n", |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 2329 | yesno(!intel_irqs_enabled(dev_priv))); |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2330 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 2331 | return 0; |
| 2332 | } |
| 2333 | |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 2334 | static const char *power_domain_str(enum intel_display_power_domain domain) |
| 2335 | { |
| 2336 | switch (domain) { |
| 2337 | case POWER_DOMAIN_PIPE_A: |
| 2338 | return "PIPE_A"; |
| 2339 | case POWER_DOMAIN_PIPE_B: |
| 2340 | return "PIPE_B"; |
| 2341 | case POWER_DOMAIN_PIPE_C: |
| 2342 | return "PIPE_C"; |
| 2343 | case POWER_DOMAIN_PIPE_A_PANEL_FITTER: |
| 2344 | return "PIPE_A_PANEL_FITTER"; |
| 2345 | case POWER_DOMAIN_PIPE_B_PANEL_FITTER: |
| 2346 | return "PIPE_B_PANEL_FITTER"; |
| 2347 | case POWER_DOMAIN_PIPE_C_PANEL_FITTER: |
| 2348 | return "PIPE_C_PANEL_FITTER"; |
| 2349 | case POWER_DOMAIN_TRANSCODER_A: |
| 2350 | return "TRANSCODER_A"; |
| 2351 | case POWER_DOMAIN_TRANSCODER_B: |
| 2352 | return "TRANSCODER_B"; |
| 2353 | case POWER_DOMAIN_TRANSCODER_C: |
| 2354 | return "TRANSCODER_C"; |
| 2355 | case POWER_DOMAIN_TRANSCODER_EDP: |
| 2356 | return "TRANSCODER_EDP"; |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 2357 | case POWER_DOMAIN_PORT_DDI_A_2_LANES: |
| 2358 | return "PORT_DDI_A_2_LANES"; |
| 2359 | case POWER_DOMAIN_PORT_DDI_A_4_LANES: |
| 2360 | return "PORT_DDI_A_4_LANES"; |
| 2361 | case POWER_DOMAIN_PORT_DDI_B_2_LANES: |
| 2362 | return "PORT_DDI_B_2_LANES"; |
| 2363 | case POWER_DOMAIN_PORT_DDI_B_4_LANES: |
| 2364 | return "PORT_DDI_B_4_LANES"; |
| 2365 | case POWER_DOMAIN_PORT_DDI_C_2_LANES: |
| 2366 | return "PORT_DDI_C_2_LANES"; |
| 2367 | case POWER_DOMAIN_PORT_DDI_C_4_LANES: |
| 2368 | return "PORT_DDI_C_4_LANES"; |
| 2369 | case POWER_DOMAIN_PORT_DDI_D_2_LANES: |
| 2370 | return "PORT_DDI_D_2_LANES"; |
| 2371 | case POWER_DOMAIN_PORT_DDI_D_4_LANES: |
| 2372 | return "PORT_DDI_D_4_LANES"; |
| 2373 | case POWER_DOMAIN_PORT_DSI: |
| 2374 | return "PORT_DSI"; |
| 2375 | case POWER_DOMAIN_PORT_CRT: |
| 2376 | return "PORT_CRT"; |
| 2377 | case POWER_DOMAIN_PORT_OTHER: |
| 2378 | return "PORT_OTHER"; |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 2379 | case POWER_DOMAIN_VGA: |
| 2380 | return "VGA"; |
| 2381 | case POWER_DOMAIN_AUDIO: |
| 2382 | return "AUDIO"; |
Paulo Zanoni | bd2bb1b | 2014-07-04 11:27:38 -0300 | [diff] [blame] | 2383 | case POWER_DOMAIN_PLLS: |
| 2384 | return "PLLS"; |
Satheeshakrishna M | 1407121 | 2015-01-16 15:57:51 +0000 | [diff] [blame^] | 2385 | case POWER_DOMAIN_AUX_A: |
| 2386 | return "AUX_A"; |
| 2387 | case POWER_DOMAIN_AUX_B: |
| 2388 | return "AUX_B"; |
| 2389 | case POWER_DOMAIN_AUX_C: |
| 2390 | return "AUX_C"; |
| 2391 | case POWER_DOMAIN_AUX_D: |
| 2392 | return "AUX_D"; |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 2393 | case POWER_DOMAIN_INIT: |
| 2394 | return "INIT"; |
| 2395 | default: |
Daniel Vetter | 5f77eeb | 2014-12-08 16:40:10 +0100 | [diff] [blame] | 2396 | MISSING_CASE(domain); |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 2397 | return "?"; |
| 2398 | } |
| 2399 | } |
| 2400 | |
| 2401 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
| 2402 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2403 | struct drm_info_node *node = m->private; |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 2404 | struct drm_device *dev = node->minor->dev; |
| 2405 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2406 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 2407 | int i; |
| 2408 | |
| 2409 | mutex_lock(&power_domains->lock); |
| 2410 | |
| 2411 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); |
| 2412 | for (i = 0; i < power_domains->power_well_count; i++) { |
| 2413 | struct i915_power_well *power_well; |
| 2414 | enum intel_display_power_domain power_domain; |
| 2415 | |
| 2416 | power_well = &power_domains->power_wells[i]; |
| 2417 | seq_printf(m, "%-25s %d\n", power_well->name, |
| 2418 | power_well->count); |
| 2419 | |
| 2420 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; |
| 2421 | power_domain++) { |
| 2422 | if (!(BIT(power_domain) & power_well->domains)) |
| 2423 | continue; |
| 2424 | |
| 2425 | seq_printf(m, " %-23s %d\n", |
| 2426 | power_domain_str(power_domain), |
| 2427 | power_domains->domain_use_count[power_domain]); |
| 2428 | } |
| 2429 | } |
| 2430 | |
| 2431 | mutex_unlock(&power_domains->lock); |
| 2432 | |
| 2433 | return 0; |
| 2434 | } |
| 2435 | |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2436 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
| 2437 | struct drm_display_mode *mode) |
| 2438 | { |
| 2439 | int i; |
| 2440 | |
| 2441 | for (i = 0; i < tabs; i++) |
| 2442 | seq_putc(m, '\t'); |
| 2443 | |
| 2444 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", |
| 2445 | mode->base.id, mode->name, |
| 2446 | mode->vrefresh, mode->clock, |
| 2447 | mode->hdisplay, mode->hsync_start, |
| 2448 | mode->hsync_end, mode->htotal, |
| 2449 | mode->vdisplay, mode->vsync_start, |
| 2450 | mode->vsync_end, mode->vtotal, |
| 2451 | mode->type, mode->flags); |
| 2452 | } |
| 2453 | |
| 2454 | static void intel_encoder_info(struct seq_file *m, |
| 2455 | struct intel_crtc *intel_crtc, |
| 2456 | struct intel_encoder *intel_encoder) |
| 2457 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2458 | struct drm_info_node *node = m->private; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2459 | struct drm_device *dev = node->minor->dev; |
| 2460 | struct drm_crtc *crtc = &intel_crtc->base; |
| 2461 | struct intel_connector *intel_connector; |
| 2462 | struct drm_encoder *encoder; |
| 2463 | |
| 2464 | encoder = &intel_encoder->base; |
| 2465 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", |
Jani Nikula | 8e329a0 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 2466 | encoder->base.id, encoder->name); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2467 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
| 2468 | struct drm_connector *connector = &intel_connector->base; |
| 2469 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", |
| 2470 | connector->base.id, |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 2471 | connector->name, |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2472 | drm_get_connector_status_name(connector->status)); |
| 2473 | if (connector->status == connector_status_connected) { |
| 2474 | struct drm_display_mode *mode = &crtc->mode; |
| 2475 | seq_printf(m, ", mode:\n"); |
| 2476 | intel_seq_print_mode(m, 2, mode); |
| 2477 | } else { |
| 2478 | seq_putc(m, '\n'); |
| 2479 | } |
| 2480 | } |
| 2481 | } |
| 2482 | |
| 2483 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) |
| 2484 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2485 | struct drm_info_node *node = m->private; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2486 | struct drm_device *dev = node->minor->dev; |
| 2487 | struct drm_crtc *crtc = &intel_crtc->base; |
| 2488 | struct intel_encoder *intel_encoder; |
| 2489 | |
Matt Roper | 5aa8a93 | 2014-06-16 10:12:55 -0700 | [diff] [blame] | 2490 | if (crtc->primary->fb) |
| 2491 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
| 2492 | crtc->primary->fb->base.id, crtc->x, crtc->y, |
| 2493 | crtc->primary->fb->width, crtc->primary->fb->height); |
| 2494 | else |
| 2495 | seq_puts(m, "\tprimary plane disabled\n"); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2496 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
| 2497 | intel_encoder_info(m, intel_crtc, intel_encoder); |
| 2498 | } |
| 2499 | |
| 2500 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) |
| 2501 | { |
| 2502 | struct drm_display_mode *mode = panel->fixed_mode; |
| 2503 | |
| 2504 | seq_printf(m, "\tfixed mode:\n"); |
| 2505 | intel_seq_print_mode(m, 2, mode); |
| 2506 | } |
| 2507 | |
| 2508 | static void intel_dp_info(struct seq_file *m, |
| 2509 | struct intel_connector *intel_connector) |
| 2510 | { |
| 2511 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
| 2512 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
| 2513 | |
| 2514 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); |
| 2515 | seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" : |
| 2516 | "no"); |
| 2517 | if (intel_encoder->type == INTEL_OUTPUT_EDP) |
| 2518 | intel_panel_info(m, &intel_connector->panel); |
| 2519 | } |
| 2520 | |
| 2521 | static void intel_hdmi_info(struct seq_file *m, |
| 2522 | struct intel_connector *intel_connector) |
| 2523 | { |
| 2524 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
| 2525 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); |
| 2526 | |
| 2527 | seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" : |
| 2528 | "no"); |
| 2529 | } |
| 2530 | |
| 2531 | static void intel_lvds_info(struct seq_file *m, |
| 2532 | struct intel_connector *intel_connector) |
| 2533 | { |
| 2534 | intel_panel_info(m, &intel_connector->panel); |
| 2535 | } |
| 2536 | |
| 2537 | static void intel_connector_info(struct seq_file *m, |
| 2538 | struct drm_connector *connector) |
| 2539 | { |
| 2540 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 2541 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
Jesse Barnes | f103fc7 | 2014-02-20 12:39:57 -0800 | [diff] [blame] | 2542 | struct drm_display_mode *mode; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2543 | |
| 2544 | seq_printf(m, "connector %d: type %s, status: %s\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 2545 | connector->base.id, connector->name, |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2546 | drm_get_connector_status_name(connector->status)); |
| 2547 | if (connector->status == connector_status_connected) { |
| 2548 | seq_printf(m, "\tname: %s\n", connector->display_info.name); |
| 2549 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", |
| 2550 | connector->display_info.width_mm, |
| 2551 | connector->display_info.height_mm); |
| 2552 | seq_printf(m, "\tsubpixel order: %s\n", |
| 2553 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); |
| 2554 | seq_printf(m, "\tCEA rev: %d\n", |
| 2555 | connector->display_info.cea_rev); |
| 2556 | } |
Dave Airlie | 36cd744 | 2014-05-02 13:44:18 +1000 | [diff] [blame] | 2557 | if (intel_encoder) { |
| 2558 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
| 2559 | intel_encoder->type == INTEL_OUTPUT_EDP) |
| 2560 | intel_dp_info(m, intel_connector); |
| 2561 | else if (intel_encoder->type == INTEL_OUTPUT_HDMI) |
| 2562 | intel_hdmi_info(m, intel_connector); |
| 2563 | else if (intel_encoder->type == INTEL_OUTPUT_LVDS) |
| 2564 | intel_lvds_info(m, intel_connector); |
| 2565 | } |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2566 | |
Jesse Barnes | f103fc7 | 2014-02-20 12:39:57 -0800 | [diff] [blame] | 2567 | seq_printf(m, "\tmodes:\n"); |
| 2568 | list_for_each_entry(mode, &connector->modes, head) |
| 2569 | intel_seq_print_mode(m, 2, mode); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2570 | } |
| 2571 | |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2572 | static bool cursor_active(struct drm_device *dev, int pipe) |
| 2573 | { |
| 2574 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2575 | u32 state; |
| 2576 | |
| 2577 | if (IS_845G(dev) || IS_I865G(dev)) |
| 2578 | state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2579 | else |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 2580 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2581 | |
| 2582 | return state; |
| 2583 | } |
| 2584 | |
| 2585 | static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) |
| 2586 | { |
| 2587 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2588 | u32 pos; |
| 2589 | |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 2590 | pos = I915_READ(CURPOS(pipe)); |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2591 | |
| 2592 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; |
| 2593 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) |
| 2594 | *x = -*x; |
| 2595 | |
| 2596 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; |
| 2597 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) |
| 2598 | *y = -*y; |
| 2599 | |
| 2600 | return cursor_active(dev, pipe); |
| 2601 | } |
| 2602 | |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2603 | static int i915_display_info(struct seq_file *m, void *unused) |
| 2604 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2605 | struct drm_info_node *node = m->private; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2606 | struct drm_device *dev = node->minor->dev; |
Paulo Zanoni | b0e5ddf | 2014-04-01 14:55:10 -0300 | [diff] [blame] | 2607 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2608 | struct intel_crtc *crtc; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2609 | struct drm_connector *connector; |
| 2610 | |
Paulo Zanoni | b0e5ddf | 2014-04-01 14:55:10 -0300 | [diff] [blame] | 2611 | intel_runtime_pm_get(dev_priv); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2612 | drm_modeset_lock_all(dev); |
| 2613 | seq_printf(m, "CRTC info\n"); |
| 2614 | seq_printf(m, "---------\n"); |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 2615 | for_each_intel_crtc(dev, crtc) { |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2616 | bool active; |
| 2617 | int x, y; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2618 | |
Chris Wilson | 57127ef | 2014-07-04 08:20:11 +0100 | [diff] [blame] | 2619 | seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n", |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2620 | crtc->base.base.id, pipe_name(crtc->pipe), |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2621 | yesno(crtc->active), crtc->config->pipe_src_w, |
| 2622 | crtc->config->pipe_src_h); |
Paulo Zanoni | a23dc65 | 2014-04-01 14:55:11 -0300 | [diff] [blame] | 2623 | if (crtc->active) { |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2624 | intel_crtc_info(m, crtc); |
| 2625 | |
Paulo Zanoni | a23dc65 | 2014-04-01 14:55:11 -0300 | [diff] [blame] | 2626 | active = cursor_position(dev, crtc->pipe, &x, &y); |
Chris Wilson | 57127ef | 2014-07-04 08:20:11 +0100 | [diff] [blame] | 2627 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 2628 | yesno(crtc->cursor_base), |
Chris Wilson | 57127ef | 2014-07-04 08:20:11 +0100 | [diff] [blame] | 2629 | x, y, crtc->cursor_width, crtc->cursor_height, |
| 2630 | crtc->cursor_addr, yesno(active)); |
Paulo Zanoni | a23dc65 | 2014-04-01 14:55:11 -0300 | [diff] [blame] | 2631 | } |
Daniel Vetter | cace841 | 2014-05-22 17:56:31 +0200 | [diff] [blame] | 2632 | |
| 2633 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", |
| 2634 | yesno(!crtc->cpu_fifo_underrun_disabled), |
| 2635 | yesno(!crtc->pch_fifo_underrun_disabled)); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2636 | } |
| 2637 | |
| 2638 | seq_printf(m, "\n"); |
| 2639 | seq_printf(m, "Connector info\n"); |
| 2640 | seq_printf(m, "--------------\n"); |
| 2641 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 2642 | intel_connector_info(m, connector); |
| 2643 | } |
| 2644 | drm_modeset_unlock_all(dev); |
Paulo Zanoni | b0e5ddf | 2014-04-01 14:55:10 -0300 | [diff] [blame] | 2645 | intel_runtime_pm_put(dev_priv); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2646 | |
| 2647 | return 0; |
| 2648 | } |
| 2649 | |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 2650 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
| 2651 | { |
| 2652 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2653 | struct drm_device *dev = node->minor->dev; |
| 2654 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2655 | struct intel_engine_cs *ring; |
| 2656 | int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
| 2657 | int i, j, ret; |
| 2658 | |
| 2659 | if (!i915_semaphore_is_enabled(dev)) { |
| 2660 | seq_puts(m, "Semaphores are disabled\n"); |
| 2661 | return 0; |
| 2662 | } |
| 2663 | |
| 2664 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2665 | if (ret) |
| 2666 | return ret; |
Paulo Zanoni | 0387206 | 2014-07-09 14:31:57 -0300 | [diff] [blame] | 2667 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 2668 | |
| 2669 | if (IS_BROADWELL(dev)) { |
| 2670 | struct page *page; |
| 2671 | uint64_t *seqno; |
| 2672 | |
| 2673 | page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0); |
| 2674 | |
| 2675 | seqno = (uint64_t *)kmap_atomic(page); |
| 2676 | for_each_ring(ring, dev_priv, i) { |
| 2677 | uint64_t offset; |
| 2678 | |
| 2679 | seq_printf(m, "%s\n", ring->name); |
| 2680 | |
| 2681 | seq_puts(m, " Last signal:"); |
| 2682 | for (j = 0; j < num_rings; j++) { |
| 2683 | offset = i * I915_NUM_RINGS + j; |
| 2684 | seq_printf(m, "0x%08llx (0x%02llx) ", |
| 2685 | seqno[offset], offset * 8); |
| 2686 | } |
| 2687 | seq_putc(m, '\n'); |
| 2688 | |
| 2689 | seq_puts(m, " Last wait: "); |
| 2690 | for (j = 0; j < num_rings; j++) { |
| 2691 | offset = i + (j * I915_NUM_RINGS); |
| 2692 | seq_printf(m, "0x%08llx (0x%02llx) ", |
| 2693 | seqno[offset], offset * 8); |
| 2694 | } |
| 2695 | seq_putc(m, '\n'); |
| 2696 | |
| 2697 | } |
| 2698 | kunmap_atomic(seqno); |
| 2699 | } else { |
| 2700 | seq_puts(m, " Last signal:"); |
| 2701 | for_each_ring(ring, dev_priv, i) |
| 2702 | for (j = 0; j < num_rings; j++) |
| 2703 | seq_printf(m, "0x%08x\n", |
| 2704 | I915_READ(ring->semaphore.mbox.signal[j])); |
| 2705 | seq_putc(m, '\n'); |
| 2706 | } |
| 2707 | |
| 2708 | seq_puts(m, "\nSync seqno:\n"); |
| 2709 | for_each_ring(ring, dev_priv, i) { |
| 2710 | for (j = 0; j < num_rings; j++) { |
| 2711 | seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]); |
| 2712 | } |
| 2713 | seq_putc(m, '\n'); |
| 2714 | } |
| 2715 | seq_putc(m, '\n'); |
| 2716 | |
Paulo Zanoni | 0387206 | 2014-07-09 14:31:57 -0300 | [diff] [blame] | 2717 | intel_runtime_pm_put(dev_priv); |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 2718 | mutex_unlock(&dev->struct_mutex); |
| 2719 | return 0; |
| 2720 | } |
| 2721 | |
Daniel Vetter | 728e29d | 2014-06-25 22:01:53 +0300 | [diff] [blame] | 2722 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
| 2723 | { |
| 2724 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2725 | struct drm_device *dev = node->minor->dev; |
| 2726 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2727 | int i; |
| 2728 | |
| 2729 | drm_modeset_lock_all(dev); |
| 2730 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 2731 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
| 2732 | |
| 2733 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); |
Ander Conselvan de Oliveira | 1e6f2dd | 2014-10-29 11:32:31 +0200 | [diff] [blame] | 2734 | seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n", |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 2735 | pll->config.crtc_mask, pll->active, yesno(pll->on)); |
Daniel Vetter | 728e29d | 2014-06-25 22:01:53 +0300 | [diff] [blame] | 2736 | seq_printf(m, " tracked hardware state:\n"); |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 2737 | seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); |
| 2738 | seq_printf(m, " dpll_md: 0x%08x\n", |
| 2739 | pll->config.hw_state.dpll_md); |
| 2740 | seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); |
| 2741 | seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); |
| 2742 | seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); |
Daniel Vetter | 728e29d | 2014-06-25 22:01:53 +0300 | [diff] [blame] | 2743 | } |
| 2744 | drm_modeset_unlock_all(dev); |
| 2745 | |
| 2746 | return 0; |
| 2747 | } |
| 2748 | |
Damien Lespiau | 1ed1ef9 | 2014-08-30 16:50:59 +0100 | [diff] [blame] | 2749 | static int i915_wa_registers(struct seq_file *m, void *unused) |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 2750 | { |
| 2751 | int i; |
| 2752 | int ret; |
| 2753 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2754 | struct drm_device *dev = node->minor->dev; |
| 2755 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2756 | |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 2757 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2758 | if (ret) |
| 2759 | return ret; |
| 2760 | |
| 2761 | intel_runtime_pm_get(dev_priv); |
| 2762 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 2763 | seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count); |
| 2764 | for (i = 0; i < dev_priv->workarounds.count; ++i) { |
Mika Kuoppala | 2fa60f6 | 2014-10-07 17:21:27 +0300 | [diff] [blame] | 2765 | u32 addr, mask, value, read; |
| 2766 | bool ok; |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 2767 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 2768 | addr = dev_priv->workarounds.reg[i].addr; |
| 2769 | mask = dev_priv->workarounds.reg[i].mask; |
Mika Kuoppala | 2fa60f6 | 2014-10-07 17:21:27 +0300 | [diff] [blame] | 2770 | value = dev_priv->workarounds.reg[i].value; |
| 2771 | read = I915_READ(addr); |
| 2772 | ok = (value & mask) == (read & mask); |
| 2773 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", |
| 2774 | addr, value, mask, read, ok ? "OK" : "FAIL"); |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 2775 | } |
| 2776 | |
| 2777 | intel_runtime_pm_put(dev_priv); |
| 2778 | mutex_unlock(&dev->struct_mutex); |
| 2779 | |
| 2780 | return 0; |
| 2781 | } |
| 2782 | |
Damien Lespiau | c5511e4 | 2014-11-04 17:06:51 +0000 | [diff] [blame] | 2783 | static int i915_ddb_info(struct seq_file *m, void *unused) |
| 2784 | { |
| 2785 | struct drm_info_node *node = m->private; |
| 2786 | struct drm_device *dev = node->minor->dev; |
| 2787 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2788 | struct skl_ddb_allocation *ddb; |
| 2789 | struct skl_ddb_entry *entry; |
| 2790 | enum pipe pipe; |
| 2791 | int plane; |
| 2792 | |
Damien Lespiau | 2fcffe1 | 2014-12-03 17:33:24 +0000 | [diff] [blame] | 2793 | if (INTEL_INFO(dev)->gen < 9) |
| 2794 | return 0; |
| 2795 | |
Damien Lespiau | c5511e4 | 2014-11-04 17:06:51 +0000 | [diff] [blame] | 2796 | drm_modeset_lock_all(dev); |
| 2797 | |
| 2798 | ddb = &dev_priv->wm.skl_hw.ddb; |
| 2799 | |
| 2800 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); |
| 2801 | |
| 2802 | for_each_pipe(dev_priv, pipe) { |
| 2803 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); |
| 2804 | |
| 2805 | for_each_plane(pipe, plane) { |
| 2806 | entry = &ddb->plane[pipe][plane]; |
| 2807 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, |
| 2808 | entry->start, entry->end, |
| 2809 | skl_ddb_entry_size(entry)); |
| 2810 | } |
| 2811 | |
| 2812 | entry = &ddb->cursor[pipe]; |
| 2813 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
| 2814 | entry->end, skl_ddb_entry_size(entry)); |
| 2815 | } |
| 2816 | |
| 2817 | drm_modeset_unlock_all(dev); |
| 2818 | |
| 2819 | return 0; |
| 2820 | } |
| 2821 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2822 | struct pipe_crc_info { |
| 2823 | const char *name; |
| 2824 | struct drm_device *dev; |
| 2825 | enum pipe pipe; |
| 2826 | }; |
| 2827 | |
Dave Airlie | 11bed958 | 2014-05-12 15:22:27 +1000 | [diff] [blame] | 2828 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
| 2829 | { |
| 2830 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2831 | struct drm_device *dev = node->minor->dev; |
| 2832 | struct drm_encoder *encoder; |
| 2833 | struct intel_encoder *intel_encoder; |
| 2834 | struct intel_digital_port *intel_dig_port; |
| 2835 | drm_modeset_lock_all(dev); |
| 2836 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 2837 | intel_encoder = to_intel_encoder(encoder); |
| 2838 | if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT) |
| 2839 | continue; |
| 2840 | intel_dig_port = enc_to_dig_port(encoder); |
| 2841 | if (!intel_dig_port->dp.can_mst) |
| 2842 | continue; |
| 2843 | |
| 2844 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
| 2845 | } |
| 2846 | drm_modeset_unlock_all(dev); |
| 2847 | return 0; |
| 2848 | } |
| 2849 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2850 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 2851 | { |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 2852 | struct pipe_crc_info *info = inode->i_private; |
| 2853 | struct drm_i915_private *dev_priv = info->dev->dev_private; |
| 2854 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
| 2855 | |
Daniel Vetter | 7eb1c49 | 2013-11-14 11:30:43 +0100 | [diff] [blame] | 2856 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
| 2857 | return -ENODEV; |
| 2858 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2859 | spin_lock_irq(&pipe_crc->lock); |
| 2860 | |
| 2861 | if (pipe_crc->opened) { |
| 2862 | spin_unlock_irq(&pipe_crc->lock); |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 2863 | return -EBUSY; /* already open */ |
| 2864 | } |
| 2865 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2866 | pipe_crc->opened = true; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2867 | filep->private_data = inode->i_private; |
| 2868 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2869 | spin_unlock_irq(&pipe_crc->lock); |
| 2870 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2871 | return 0; |
| 2872 | } |
| 2873 | |
| 2874 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) |
| 2875 | { |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 2876 | struct pipe_crc_info *info = inode->i_private; |
| 2877 | struct drm_i915_private *dev_priv = info->dev->dev_private; |
| 2878 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
| 2879 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2880 | spin_lock_irq(&pipe_crc->lock); |
| 2881 | pipe_crc->opened = false; |
| 2882 | spin_unlock_irq(&pipe_crc->lock); |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 2883 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2884 | return 0; |
| 2885 | } |
| 2886 | |
| 2887 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ |
| 2888 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) |
| 2889 | /* account for \'0' */ |
| 2890 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) |
| 2891 | |
| 2892 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) |
| 2893 | { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2894 | assert_spin_locked(&pipe_crc->lock); |
| 2895 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
| 2896 | INTEL_PIPE_CRC_ENTRIES_NR); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2897 | } |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 2898 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2899 | static ssize_t |
| 2900 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, |
| 2901 | loff_t *pos) |
| 2902 | { |
| 2903 | struct pipe_crc_info *info = filep->private_data; |
| 2904 | struct drm_device *dev = info->dev; |
| 2905 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2906 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
| 2907 | char buf[PIPE_CRC_BUFFER_LEN]; |
Ville Syrjälä | 9ad6d99 | 2014-12-09 21:28:32 +0200 | [diff] [blame] | 2908 | int n_entries; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2909 | ssize_t bytes_read; |
| 2910 | |
| 2911 | /* |
| 2912 | * Don't allow user space to provide buffers not big enough to hold |
| 2913 | * a line of data. |
| 2914 | */ |
| 2915 | if (count < PIPE_CRC_LINE_LEN) |
| 2916 | return -EINVAL; |
| 2917 | |
| 2918 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) |
| 2919 | return 0; |
| 2920 | |
| 2921 | /* nothing to read */ |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2922 | spin_lock_irq(&pipe_crc->lock); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2923 | while (pipe_crc_data_count(pipe_crc) == 0) { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2924 | int ret; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2925 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2926 | if (filep->f_flags & O_NONBLOCK) { |
| 2927 | spin_unlock_irq(&pipe_crc->lock); |
| 2928 | return -EAGAIN; |
| 2929 | } |
| 2930 | |
| 2931 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
| 2932 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); |
| 2933 | if (ret) { |
| 2934 | spin_unlock_irq(&pipe_crc->lock); |
| 2935 | return ret; |
| 2936 | } |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2937 | } |
| 2938 | |
| 2939 | /* We now have one or more entries to read */ |
Ville Syrjälä | 9ad6d99 | 2014-12-09 21:28:32 +0200 | [diff] [blame] | 2940 | n_entries = count / PIPE_CRC_LINE_LEN; |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2941 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2942 | bytes_read = 0; |
Ville Syrjälä | 9ad6d99 | 2014-12-09 21:28:32 +0200 | [diff] [blame] | 2943 | while (n_entries > 0) { |
| 2944 | struct intel_pipe_crc_entry *entry = |
| 2945 | &pipe_crc->entries[pipe_crc->tail]; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2946 | int ret; |
| 2947 | |
Ville Syrjälä | 9ad6d99 | 2014-12-09 21:28:32 +0200 | [diff] [blame] | 2948 | if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
| 2949 | INTEL_PIPE_CRC_ENTRIES_NR) < 1) |
| 2950 | break; |
| 2951 | |
| 2952 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); |
| 2953 | pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); |
| 2954 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2955 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
| 2956 | "%8u %8x %8x %8x %8x %8x\n", |
| 2957 | entry->frame, entry->crc[0], |
| 2958 | entry->crc[1], entry->crc[2], |
| 2959 | entry->crc[3], entry->crc[4]); |
| 2960 | |
Ville Syrjälä | 9ad6d99 | 2014-12-09 21:28:32 +0200 | [diff] [blame] | 2961 | spin_unlock_irq(&pipe_crc->lock); |
| 2962 | |
| 2963 | ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2964 | if (ret == PIPE_CRC_LINE_LEN) |
| 2965 | return -EFAULT; |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 2966 | |
Ville Syrjälä | 9ad6d99 | 2014-12-09 21:28:32 +0200 | [diff] [blame] | 2967 | user_buf += PIPE_CRC_LINE_LEN; |
| 2968 | n_entries--; |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 2969 | |
Ville Syrjälä | 9ad6d99 | 2014-12-09 21:28:32 +0200 | [diff] [blame] | 2970 | spin_lock_irq(&pipe_crc->lock); |
| 2971 | } |
| 2972 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2973 | spin_unlock_irq(&pipe_crc->lock); |
| 2974 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2975 | return bytes_read; |
| 2976 | } |
| 2977 | |
| 2978 | static const struct file_operations i915_pipe_crc_fops = { |
| 2979 | .owner = THIS_MODULE, |
| 2980 | .open = i915_pipe_crc_open, |
| 2981 | .read = i915_pipe_crc_read, |
| 2982 | .release = i915_pipe_crc_release, |
| 2983 | }; |
| 2984 | |
| 2985 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { |
| 2986 | { |
| 2987 | .name = "i915_pipe_A_crc", |
| 2988 | .pipe = PIPE_A, |
| 2989 | }, |
| 2990 | { |
| 2991 | .name = "i915_pipe_B_crc", |
| 2992 | .pipe = PIPE_B, |
| 2993 | }, |
| 2994 | { |
| 2995 | .name = "i915_pipe_C_crc", |
| 2996 | .pipe = PIPE_C, |
| 2997 | }, |
| 2998 | }; |
| 2999 | |
| 3000 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, |
| 3001 | enum pipe pipe) |
| 3002 | { |
| 3003 | struct drm_device *dev = minor->dev; |
| 3004 | struct dentry *ent; |
| 3005 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; |
| 3006 | |
| 3007 | info->dev = dev; |
| 3008 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, |
| 3009 | &i915_pipe_crc_fops); |
Wei Yongjun | f3c5fe9 | 2013-12-16 14:13:25 +0800 | [diff] [blame] | 3010 | if (!ent) |
| 3011 | return -ENOMEM; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3012 | |
| 3013 | return drm_add_fake_info_node(minor, ent, info); |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 3014 | } |
| 3015 | |
Daniel Vetter | e8dfcf7 | 2013-10-16 11:51:54 +0200 | [diff] [blame] | 3016 | static const char * const pipe_crc_sources[] = { |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3017 | "none", |
| 3018 | "plane1", |
| 3019 | "plane2", |
| 3020 | "pf", |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3021 | "pipe", |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 3022 | "TV", |
| 3023 | "DP-B", |
| 3024 | "DP-C", |
| 3025 | "DP-D", |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3026 | "auto", |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3027 | }; |
| 3028 | |
| 3029 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) |
| 3030 | { |
| 3031 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); |
| 3032 | return pipe_crc_sources[source]; |
| 3033 | } |
| 3034 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3035 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3036 | { |
| 3037 | struct drm_device *dev = m->private; |
| 3038 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3039 | int i; |
| 3040 | |
| 3041 | for (i = 0; i < I915_MAX_PIPES; i++) |
| 3042 | seq_printf(m, "%c %s\n", pipe_name(i), |
| 3043 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); |
| 3044 | |
| 3045 | return 0; |
| 3046 | } |
| 3047 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3048 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3049 | { |
| 3050 | struct drm_device *dev = inode->i_private; |
| 3051 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3052 | return single_open(file, display_crc_ctl_show, dev); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3053 | } |
| 3054 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3055 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 3056 | uint32_t *val) |
| 3057 | { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3058 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
| 3059 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; |
| 3060 | |
| 3061 | switch (*source) { |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 3062 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 3063 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; |
| 3064 | break; |
| 3065 | case INTEL_PIPE_CRC_SOURCE_NONE: |
| 3066 | *val = 0; |
| 3067 | break; |
| 3068 | default: |
| 3069 | return -EINVAL; |
| 3070 | } |
| 3071 | |
| 3072 | return 0; |
| 3073 | } |
| 3074 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3075 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
| 3076 | enum intel_pipe_crc_source *source) |
| 3077 | { |
| 3078 | struct intel_encoder *encoder; |
| 3079 | struct intel_crtc *crtc; |
Daniel Vetter | 2675680 | 2013-11-01 10:50:23 +0100 | [diff] [blame] | 3080 | struct intel_digital_port *dig_port; |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3081 | int ret = 0; |
| 3082 | |
| 3083 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; |
| 3084 | |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 3085 | drm_modeset_lock_all(dev); |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 3086 | for_each_intel_encoder(dev, encoder) { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3087 | if (!encoder->base.crtc) |
| 3088 | continue; |
| 3089 | |
| 3090 | crtc = to_intel_crtc(encoder->base.crtc); |
| 3091 | |
| 3092 | if (crtc->pipe != pipe) |
| 3093 | continue; |
| 3094 | |
| 3095 | switch (encoder->type) { |
| 3096 | case INTEL_OUTPUT_TVOUT: |
| 3097 | *source = INTEL_PIPE_CRC_SOURCE_TV; |
| 3098 | break; |
| 3099 | case INTEL_OUTPUT_DISPLAYPORT: |
| 3100 | case INTEL_OUTPUT_EDP: |
Daniel Vetter | 2675680 | 2013-11-01 10:50:23 +0100 | [diff] [blame] | 3101 | dig_port = enc_to_dig_port(&encoder->base); |
| 3102 | switch (dig_port->port) { |
| 3103 | case PORT_B: |
| 3104 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; |
| 3105 | break; |
| 3106 | case PORT_C: |
| 3107 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; |
| 3108 | break; |
| 3109 | case PORT_D: |
| 3110 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; |
| 3111 | break; |
| 3112 | default: |
| 3113 | WARN(1, "nonexisting DP port %c\n", |
| 3114 | port_name(dig_port->port)); |
| 3115 | break; |
| 3116 | } |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3117 | break; |
Paulo Zanoni | 6847d71 | 2014-10-27 17:47:52 -0200 | [diff] [blame] | 3118 | default: |
| 3119 | break; |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3120 | } |
| 3121 | } |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 3122 | drm_modeset_unlock_all(dev); |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3123 | |
| 3124 | return ret; |
| 3125 | } |
| 3126 | |
| 3127 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, |
| 3128 | enum pipe pipe, |
| 3129 | enum intel_pipe_crc_source *source, |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3130 | uint32_t *val) |
| 3131 | { |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3132 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3133 | bool need_stable_symbols = false; |
| 3134 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3135 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
| 3136 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); |
| 3137 | if (ret) |
| 3138 | return ret; |
| 3139 | } |
| 3140 | |
| 3141 | switch (*source) { |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3142 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 3143 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; |
| 3144 | break; |
| 3145 | case INTEL_PIPE_CRC_SOURCE_DP_B: |
| 3146 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3147 | need_stable_symbols = true; |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3148 | break; |
| 3149 | case INTEL_PIPE_CRC_SOURCE_DP_C: |
| 3150 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3151 | need_stable_symbols = true; |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3152 | break; |
Ville Syrjälä | 2be5792 | 2014-12-09 21:28:29 +0200 | [diff] [blame] | 3153 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
| 3154 | if (!IS_CHERRYVIEW(dev)) |
| 3155 | return -EINVAL; |
| 3156 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; |
| 3157 | need_stable_symbols = true; |
| 3158 | break; |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3159 | case INTEL_PIPE_CRC_SOURCE_NONE: |
| 3160 | *val = 0; |
| 3161 | break; |
| 3162 | default: |
| 3163 | return -EINVAL; |
| 3164 | } |
| 3165 | |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3166 | /* |
| 3167 | * When the pipe CRC tap point is after the transcoders we need |
| 3168 | * to tweak symbol-level features to produce a deterministic series of |
| 3169 | * symbols for a given frame. We need to reset those features only once |
| 3170 | * a frame (instead of every nth symbol): |
| 3171 | * - DC-balance: used to ensure a better clock recovery from the data |
| 3172 | * link (SDVO) |
| 3173 | * - DisplayPort scrambling: used for EMI reduction |
| 3174 | */ |
| 3175 | if (need_stable_symbols) { |
| 3176 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 3177 | |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3178 | tmp |= DC_BALANCE_RESET_VLV; |
Ville Syrjälä | eb73667 | 2014-12-09 21:28:28 +0200 | [diff] [blame] | 3179 | switch (pipe) { |
| 3180 | case PIPE_A: |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3181 | tmp |= PIPE_A_SCRAMBLE_RESET; |
Ville Syrjälä | eb73667 | 2014-12-09 21:28:28 +0200 | [diff] [blame] | 3182 | break; |
| 3183 | case PIPE_B: |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3184 | tmp |= PIPE_B_SCRAMBLE_RESET; |
Ville Syrjälä | eb73667 | 2014-12-09 21:28:28 +0200 | [diff] [blame] | 3185 | break; |
| 3186 | case PIPE_C: |
| 3187 | tmp |= PIPE_C_SCRAMBLE_RESET; |
| 3188 | break; |
| 3189 | default: |
| 3190 | return -EINVAL; |
| 3191 | } |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3192 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 3193 | } |
| 3194 | |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3195 | return 0; |
| 3196 | } |
| 3197 | |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3198 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3199 | enum pipe pipe, |
| 3200 | enum intel_pipe_crc_source *source, |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3201 | uint32_t *val) |
| 3202 | { |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3203 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3204 | bool need_stable_symbols = false; |
| 3205 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3206 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
| 3207 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); |
| 3208 | if (ret) |
| 3209 | return ret; |
| 3210 | } |
| 3211 | |
| 3212 | switch (*source) { |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3213 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 3214 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; |
| 3215 | break; |
| 3216 | case INTEL_PIPE_CRC_SOURCE_TV: |
| 3217 | if (!SUPPORTS_TV(dev)) |
| 3218 | return -EINVAL; |
| 3219 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; |
| 3220 | break; |
| 3221 | case INTEL_PIPE_CRC_SOURCE_DP_B: |
| 3222 | if (!IS_G4X(dev)) |
| 3223 | return -EINVAL; |
| 3224 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3225 | need_stable_symbols = true; |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3226 | break; |
| 3227 | case INTEL_PIPE_CRC_SOURCE_DP_C: |
| 3228 | if (!IS_G4X(dev)) |
| 3229 | return -EINVAL; |
| 3230 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3231 | need_stable_symbols = true; |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3232 | break; |
| 3233 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
| 3234 | if (!IS_G4X(dev)) |
| 3235 | return -EINVAL; |
| 3236 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3237 | need_stable_symbols = true; |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3238 | break; |
| 3239 | case INTEL_PIPE_CRC_SOURCE_NONE: |
| 3240 | *val = 0; |
| 3241 | break; |
| 3242 | default: |
| 3243 | return -EINVAL; |
| 3244 | } |
| 3245 | |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3246 | /* |
| 3247 | * When the pipe CRC tap point is after the transcoders we need |
| 3248 | * to tweak symbol-level features to produce a deterministic series of |
| 3249 | * symbols for a given frame. We need to reset those features only once |
| 3250 | * a frame (instead of every nth symbol): |
| 3251 | * - DC-balance: used to ensure a better clock recovery from the data |
| 3252 | * link (SDVO) |
| 3253 | * - DisplayPort scrambling: used for EMI reduction |
| 3254 | */ |
| 3255 | if (need_stable_symbols) { |
| 3256 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 3257 | |
| 3258 | WARN_ON(!IS_G4X(dev)); |
| 3259 | |
| 3260 | I915_WRITE(PORT_DFT_I9XX, |
| 3261 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); |
| 3262 | |
| 3263 | if (pipe == PIPE_A) |
| 3264 | tmp |= PIPE_A_SCRAMBLE_RESET; |
| 3265 | else |
| 3266 | tmp |= PIPE_B_SCRAMBLE_RESET; |
| 3267 | |
| 3268 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 3269 | } |
| 3270 | |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3271 | return 0; |
| 3272 | } |
| 3273 | |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3274 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
| 3275 | enum pipe pipe) |
| 3276 | { |
| 3277 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3278 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 3279 | |
Ville Syrjälä | eb73667 | 2014-12-09 21:28:28 +0200 | [diff] [blame] | 3280 | switch (pipe) { |
| 3281 | case PIPE_A: |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3282 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
Ville Syrjälä | eb73667 | 2014-12-09 21:28:28 +0200 | [diff] [blame] | 3283 | break; |
| 3284 | case PIPE_B: |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3285 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
Ville Syrjälä | eb73667 | 2014-12-09 21:28:28 +0200 | [diff] [blame] | 3286 | break; |
| 3287 | case PIPE_C: |
| 3288 | tmp &= ~PIPE_C_SCRAMBLE_RESET; |
| 3289 | break; |
| 3290 | default: |
| 3291 | return; |
| 3292 | } |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3293 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
| 3294 | tmp &= ~DC_BALANCE_RESET_VLV; |
| 3295 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 3296 | |
| 3297 | } |
| 3298 | |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3299 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
| 3300 | enum pipe pipe) |
| 3301 | { |
| 3302 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3303 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 3304 | |
| 3305 | if (pipe == PIPE_A) |
| 3306 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
| 3307 | else |
| 3308 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
| 3309 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 3310 | |
| 3311 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { |
| 3312 | I915_WRITE(PORT_DFT_I9XX, |
| 3313 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); |
| 3314 | } |
| 3315 | } |
| 3316 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3317 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3318 | uint32_t *val) |
| 3319 | { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3320 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
| 3321 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; |
| 3322 | |
| 3323 | switch (*source) { |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3324 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
| 3325 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; |
| 3326 | break; |
| 3327 | case INTEL_PIPE_CRC_SOURCE_PLANE2: |
| 3328 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; |
| 3329 | break; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3330 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 3331 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; |
| 3332 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 3333 | case INTEL_PIPE_CRC_SOURCE_NONE: |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3334 | *val = 0; |
| 3335 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 3336 | default: |
| 3337 | return -EINVAL; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3338 | } |
| 3339 | |
| 3340 | return 0; |
| 3341 | } |
| 3342 | |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3343 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev) |
| 3344 | { |
| 3345 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3346 | struct intel_crtc *crtc = |
| 3347 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); |
| 3348 | |
| 3349 | drm_modeset_lock_all(dev); |
| 3350 | /* |
| 3351 | * If we use the eDP transcoder we need to make sure that we don't |
| 3352 | * bypass the pfit, since otherwise the pipe CRC source won't work. Only |
| 3353 | * relevant on hsw with pipe A when using the always-on power well |
| 3354 | * routing. |
| 3355 | */ |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 3356 | if (crtc->config->cpu_transcoder == TRANSCODER_EDP && |
| 3357 | !crtc->config->pch_pfit.enabled) { |
| 3358 | crtc->config->pch_pfit.force_thru = true; |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3359 | |
| 3360 | intel_display_power_get(dev_priv, |
| 3361 | POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); |
| 3362 | |
| 3363 | dev_priv->display.crtc_disable(&crtc->base); |
| 3364 | dev_priv->display.crtc_enable(&crtc->base); |
| 3365 | } |
| 3366 | drm_modeset_unlock_all(dev); |
| 3367 | } |
| 3368 | |
| 3369 | static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev) |
| 3370 | { |
| 3371 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3372 | struct intel_crtc *crtc = |
| 3373 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); |
| 3374 | |
| 3375 | drm_modeset_lock_all(dev); |
| 3376 | /* |
| 3377 | * If we use the eDP transcoder we need to make sure that we don't |
| 3378 | * bypass the pfit, since otherwise the pipe CRC source won't work. Only |
| 3379 | * relevant on hsw with pipe A when using the always-on power well |
| 3380 | * routing. |
| 3381 | */ |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 3382 | if (crtc->config->pch_pfit.force_thru) { |
| 3383 | crtc->config->pch_pfit.force_thru = false; |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3384 | |
| 3385 | dev_priv->display.crtc_disable(&crtc->base); |
| 3386 | dev_priv->display.crtc_enable(&crtc->base); |
| 3387 | |
| 3388 | intel_display_power_put(dev_priv, |
| 3389 | POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); |
| 3390 | } |
| 3391 | drm_modeset_unlock_all(dev); |
| 3392 | } |
| 3393 | |
| 3394 | static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, |
| 3395 | enum pipe pipe, |
| 3396 | enum intel_pipe_crc_source *source, |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3397 | uint32_t *val) |
| 3398 | { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3399 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
| 3400 | *source = INTEL_PIPE_CRC_SOURCE_PF; |
| 3401 | |
| 3402 | switch (*source) { |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3403 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
| 3404 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; |
| 3405 | break; |
| 3406 | case INTEL_PIPE_CRC_SOURCE_PLANE2: |
| 3407 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; |
| 3408 | break; |
| 3409 | case INTEL_PIPE_CRC_SOURCE_PF: |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3410 | if (IS_HASWELL(dev) && pipe == PIPE_A) |
| 3411 | hsw_trans_edp_pipe_A_crc_wa(dev); |
| 3412 | |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3413 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
| 3414 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 3415 | case INTEL_PIPE_CRC_SOURCE_NONE: |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3416 | *val = 0; |
| 3417 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 3418 | default: |
| 3419 | return -EINVAL; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3420 | } |
| 3421 | |
| 3422 | return 0; |
| 3423 | } |
| 3424 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3425 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
| 3426 | enum intel_pipe_crc_source source) |
| 3427 | { |
| 3428 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | cc3da17 | 2013-10-15 18:55:31 +0100 | [diff] [blame] | 3429 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
Paulo Zanoni | 8c740dc | 2014-10-17 18:42:03 -0300 | [diff] [blame] | 3430 | struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, |
| 3431 | pipe)); |
Borislav Petkov | 432f334 | 2013-11-21 16:49:46 +0100 | [diff] [blame] | 3432 | u32 val = 0; /* shut up gcc */ |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3433 | int ret; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3434 | |
Damien Lespiau | cc3da17 | 2013-10-15 18:55:31 +0100 | [diff] [blame] | 3435 | if (pipe_crc->source == source) |
| 3436 | return 0; |
| 3437 | |
Damien Lespiau | ae676fc | 2013-10-15 18:55:32 +0100 | [diff] [blame] | 3438 | /* forbid changing the source without going back to 'none' */ |
| 3439 | if (pipe_crc->source && source) |
| 3440 | return -EINVAL; |
| 3441 | |
Daniel Vetter | 9d8b058 | 2014-11-25 14:00:40 +0100 | [diff] [blame] | 3442 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) { |
| 3443 | DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); |
| 3444 | return -EIO; |
| 3445 | } |
| 3446 | |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 3447 | if (IS_GEN2(dev)) |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3448 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 3449 | else if (INTEL_INFO(dev)->gen < 5) |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3450 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3451 | else if (IS_VALLEYVIEW(dev)) |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3452 | ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3453 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3454 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3455 | else |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3456 | ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3457 | |
| 3458 | if (ret != 0) |
| 3459 | return ret; |
| 3460 | |
Damien Lespiau | 4b58436 | 2013-10-15 18:55:33 +0100 | [diff] [blame] | 3461 | /* none -> real source transition */ |
| 3462 | if (source) { |
Ville Syrjälä | 4252fbc | 2014-12-09 21:28:30 +0200 | [diff] [blame] | 3463 | struct intel_pipe_crc_entry *entries; |
| 3464 | |
Damien Lespiau | 7cd6ccf | 2013-10-15 18:55:38 +0100 | [diff] [blame] | 3465 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
| 3466 | pipe_name(pipe), pipe_crc_source_name(source)); |
| 3467 | |
Ville Syrjälä | 3cf54b3 | 2014-12-09 21:28:31 +0200 | [diff] [blame] | 3468 | entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, |
| 3469 | sizeof(pipe_crc->entries[0]), |
Ville Syrjälä | 4252fbc | 2014-12-09 21:28:30 +0200 | [diff] [blame] | 3470 | GFP_KERNEL); |
| 3471 | if (!entries) |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 3472 | return -ENOMEM; |
| 3473 | |
Paulo Zanoni | 8c740dc | 2014-10-17 18:42:03 -0300 | [diff] [blame] | 3474 | /* |
| 3475 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets |
| 3476 | * enabled and disabled dynamically based on package C states, |
| 3477 | * user space can't make reliable use of the CRCs, so let's just |
| 3478 | * completely disable it. |
| 3479 | */ |
| 3480 | hsw_disable_ips(crtc); |
| 3481 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3482 | spin_lock_irq(&pipe_crc->lock); |
Daniel Vetter | 64387b6 | 2014-12-10 11:00:29 +0100 | [diff] [blame] | 3483 | kfree(pipe_crc->entries); |
Ville Syrjälä | 4252fbc | 2014-12-09 21:28:30 +0200 | [diff] [blame] | 3484 | pipe_crc->entries = entries; |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3485 | pipe_crc->head = 0; |
| 3486 | pipe_crc->tail = 0; |
| 3487 | spin_unlock_irq(&pipe_crc->lock); |
Damien Lespiau | 4b58436 | 2013-10-15 18:55:33 +0100 | [diff] [blame] | 3488 | } |
| 3489 | |
Damien Lespiau | cc3da17 | 2013-10-15 18:55:31 +0100 | [diff] [blame] | 3490 | pipe_crc->source = source; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3491 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3492 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
| 3493 | POSTING_READ(PIPE_CRC_CTL(pipe)); |
| 3494 | |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 3495 | /* real source -> none transition */ |
| 3496 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3497 | struct intel_pipe_crc_entry *entries; |
Daniel Vetter | a33d710 | 2014-06-06 08:22:08 +0200 | [diff] [blame] | 3498 | struct intel_crtc *crtc = |
| 3499 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3500 | |
Damien Lespiau | 7cd6ccf | 2013-10-15 18:55:38 +0100 | [diff] [blame] | 3501 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
| 3502 | pipe_name(pipe)); |
| 3503 | |
Daniel Vetter | a33d710 | 2014-06-06 08:22:08 +0200 | [diff] [blame] | 3504 | drm_modeset_lock(&crtc->base.mutex, NULL); |
| 3505 | if (crtc->active) |
| 3506 | intel_wait_for_vblank(dev, pipe); |
| 3507 | drm_modeset_unlock(&crtc->base.mutex); |
Daniel Vetter | bcf17ab | 2013-10-16 22:55:50 +0200 | [diff] [blame] | 3508 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3509 | spin_lock_irq(&pipe_crc->lock); |
| 3510 | entries = pipe_crc->entries; |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 3511 | pipe_crc->entries = NULL; |
Ville Syrjälä | 9ad6d99 | 2014-12-09 21:28:32 +0200 | [diff] [blame] | 3512 | pipe_crc->head = 0; |
| 3513 | pipe_crc->tail = 0; |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3514 | spin_unlock_irq(&pipe_crc->lock); |
| 3515 | |
| 3516 | kfree(entries); |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3517 | |
| 3518 | if (IS_G4X(dev)) |
| 3519 | g4x_undo_pipe_scramble_reset(dev, pipe); |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3520 | else if (IS_VALLEYVIEW(dev)) |
| 3521 | vlv_undo_pipe_scramble_reset(dev, pipe); |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3522 | else if (IS_HASWELL(dev) && pipe == PIPE_A) |
| 3523 | hsw_undo_trans_edp_pipe_A_crc_wa(dev); |
Paulo Zanoni | 8c740dc | 2014-10-17 18:42:03 -0300 | [diff] [blame] | 3524 | |
| 3525 | hsw_enable_ips(crtc); |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 3526 | } |
| 3527 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3528 | return 0; |
| 3529 | } |
| 3530 | |
| 3531 | /* |
| 3532 | * Parse pipe CRC command strings: |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3533 | * command: wsp* object wsp+ name wsp+ source wsp* |
| 3534 | * object: 'pipe' |
| 3535 | * name: (A | B | C) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3536 | * source: (none | plane1 | plane2 | pf) |
| 3537 | * wsp: (#0x20 | #0x9 | #0xA)+ |
| 3538 | * |
| 3539 | * eg.: |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3540 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
| 3541 | * "pipe A none" -> Stop CRC |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3542 | */ |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3543 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3544 | { |
| 3545 | int n_words = 0; |
| 3546 | |
| 3547 | while (*buf) { |
| 3548 | char *end; |
| 3549 | |
| 3550 | /* skip leading white space */ |
| 3551 | buf = skip_spaces(buf); |
| 3552 | if (!*buf) |
| 3553 | break; /* end of buffer */ |
| 3554 | |
| 3555 | /* find end of word */ |
| 3556 | for (end = buf; *end && !isspace(*end); end++) |
| 3557 | ; |
| 3558 | |
| 3559 | if (n_words == max_words) { |
| 3560 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", |
| 3561 | max_words); |
| 3562 | return -EINVAL; /* ran out of words[] before bytes */ |
| 3563 | } |
| 3564 | |
| 3565 | if (*end) |
| 3566 | *end++ = '\0'; |
| 3567 | words[n_words++] = buf; |
| 3568 | buf = end; |
| 3569 | } |
| 3570 | |
| 3571 | return n_words; |
| 3572 | } |
| 3573 | |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3574 | enum intel_pipe_crc_object { |
| 3575 | PIPE_CRC_OBJECT_PIPE, |
| 3576 | }; |
| 3577 | |
Daniel Vetter | e8dfcf7 | 2013-10-16 11:51:54 +0200 | [diff] [blame] | 3578 | static const char * const pipe_crc_objects[] = { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3579 | "pipe", |
| 3580 | }; |
| 3581 | |
| 3582 | static int |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3583 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3584 | { |
| 3585 | int i; |
| 3586 | |
| 3587 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) |
| 3588 | if (!strcmp(buf, pipe_crc_objects[i])) { |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3589 | *o = i; |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3590 | return 0; |
| 3591 | } |
| 3592 | |
| 3593 | return -EINVAL; |
| 3594 | } |
| 3595 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3596 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3597 | { |
| 3598 | const char name = buf[0]; |
| 3599 | |
| 3600 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) |
| 3601 | return -EINVAL; |
| 3602 | |
| 3603 | *pipe = name - 'A'; |
| 3604 | |
| 3605 | return 0; |
| 3606 | } |
| 3607 | |
| 3608 | static int |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3609 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3610 | { |
| 3611 | int i; |
| 3612 | |
| 3613 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) |
| 3614 | if (!strcmp(buf, pipe_crc_sources[i])) { |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3615 | *s = i; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3616 | return 0; |
| 3617 | } |
| 3618 | |
| 3619 | return -EINVAL; |
| 3620 | } |
| 3621 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3622 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3623 | { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3624 | #define N_WORDS 3 |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3625 | int n_words; |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3626 | char *words[N_WORDS]; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3627 | enum pipe pipe; |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3628 | enum intel_pipe_crc_object object; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3629 | enum intel_pipe_crc_source source; |
| 3630 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3631 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3632 | if (n_words != N_WORDS) { |
| 3633 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", |
| 3634 | N_WORDS); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3635 | return -EINVAL; |
| 3636 | } |
| 3637 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3638 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3639 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3640 | return -EINVAL; |
| 3641 | } |
| 3642 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3643 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3644 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
| 3645 | return -EINVAL; |
| 3646 | } |
| 3647 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3648 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3649 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3650 | return -EINVAL; |
| 3651 | } |
| 3652 | |
| 3653 | return pipe_crc_set_source(dev, pipe, source); |
| 3654 | } |
| 3655 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3656 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
| 3657 | size_t len, loff_t *offp) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3658 | { |
| 3659 | struct seq_file *m = file->private_data; |
| 3660 | struct drm_device *dev = m->private; |
| 3661 | char *tmpbuf; |
| 3662 | int ret; |
| 3663 | |
| 3664 | if (len == 0) |
| 3665 | return 0; |
| 3666 | |
| 3667 | if (len > PAGE_SIZE - 1) { |
| 3668 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", |
| 3669 | PAGE_SIZE); |
| 3670 | return -E2BIG; |
| 3671 | } |
| 3672 | |
| 3673 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); |
| 3674 | if (!tmpbuf) |
| 3675 | return -ENOMEM; |
| 3676 | |
| 3677 | if (copy_from_user(tmpbuf, ubuf, len)) { |
| 3678 | ret = -EFAULT; |
| 3679 | goto out; |
| 3680 | } |
| 3681 | tmpbuf[len] = '\0'; |
| 3682 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3683 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3684 | |
| 3685 | out: |
| 3686 | kfree(tmpbuf); |
| 3687 | if (ret < 0) |
| 3688 | return ret; |
| 3689 | |
| 3690 | *offp += len; |
| 3691 | return len; |
| 3692 | } |
| 3693 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3694 | static const struct file_operations i915_display_crc_ctl_fops = { |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3695 | .owner = THIS_MODULE, |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3696 | .open = display_crc_ctl_open, |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3697 | .read = seq_read, |
| 3698 | .llseek = seq_lseek, |
| 3699 | .release = single_release, |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3700 | .write = display_crc_ctl_write |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3701 | }; |
| 3702 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3703 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3704 | { |
| 3705 | struct drm_device *dev = m->private; |
Damien Lespiau | 546c81f | 2014-05-13 15:30:26 +0100 | [diff] [blame] | 3706 | int num_levels = ilk_wm_max_level(dev) + 1; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3707 | int level; |
| 3708 | |
| 3709 | drm_modeset_lock_all(dev); |
| 3710 | |
| 3711 | for (level = 0; level < num_levels; level++) { |
| 3712 | unsigned int latency = wm[level]; |
| 3713 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3714 | /* |
| 3715 | * - WM1+ latency values in 0.5us units |
| 3716 | * - latencies are in us on gen9 |
| 3717 | */ |
| 3718 | if (INTEL_INFO(dev)->gen >= 9) |
| 3719 | latency *= 10; |
| 3720 | else if (level > 0) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3721 | latency *= 5; |
| 3722 | |
| 3723 | seq_printf(m, "WM%d %u (%u.%u usec)\n", |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3724 | level, wm[level], latency / 10, latency % 10); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3725 | } |
| 3726 | |
| 3727 | drm_modeset_unlock_all(dev); |
| 3728 | } |
| 3729 | |
| 3730 | static int pri_wm_latency_show(struct seq_file *m, void *data) |
| 3731 | { |
| 3732 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3733 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3734 | const uint16_t *latencies; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3735 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3736 | if (INTEL_INFO(dev)->gen >= 9) |
| 3737 | latencies = dev_priv->wm.skl_latency; |
| 3738 | else |
| 3739 | latencies = to_i915(dev)->wm.pri_latency; |
| 3740 | |
| 3741 | wm_latency_show(m, latencies); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3742 | |
| 3743 | return 0; |
| 3744 | } |
| 3745 | |
| 3746 | static int spr_wm_latency_show(struct seq_file *m, void *data) |
| 3747 | { |
| 3748 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3749 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3750 | const uint16_t *latencies; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3751 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3752 | if (INTEL_INFO(dev)->gen >= 9) |
| 3753 | latencies = dev_priv->wm.skl_latency; |
| 3754 | else |
| 3755 | latencies = to_i915(dev)->wm.spr_latency; |
| 3756 | |
| 3757 | wm_latency_show(m, latencies); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3758 | |
| 3759 | return 0; |
| 3760 | } |
| 3761 | |
| 3762 | static int cur_wm_latency_show(struct seq_file *m, void *data) |
| 3763 | { |
| 3764 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3765 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3766 | const uint16_t *latencies; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3767 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3768 | if (INTEL_INFO(dev)->gen >= 9) |
| 3769 | latencies = dev_priv->wm.skl_latency; |
| 3770 | else |
| 3771 | latencies = to_i915(dev)->wm.cur_latency; |
| 3772 | |
| 3773 | wm_latency_show(m, latencies); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3774 | |
| 3775 | return 0; |
| 3776 | } |
| 3777 | |
| 3778 | static int pri_wm_latency_open(struct inode *inode, struct file *file) |
| 3779 | { |
| 3780 | struct drm_device *dev = inode->i_private; |
| 3781 | |
Sonika Jindal | 9ad0257 | 2014-07-21 15:23:39 +0530 | [diff] [blame] | 3782 | if (HAS_GMCH_DISPLAY(dev)) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3783 | return -ENODEV; |
| 3784 | |
| 3785 | return single_open(file, pri_wm_latency_show, dev); |
| 3786 | } |
| 3787 | |
| 3788 | static int spr_wm_latency_open(struct inode *inode, struct file *file) |
| 3789 | { |
| 3790 | struct drm_device *dev = inode->i_private; |
| 3791 | |
Sonika Jindal | 9ad0257 | 2014-07-21 15:23:39 +0530 | [diff] [blame] | 3792 | if (HAS_GMCH_DISPLAY(dev)) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3793 | return -ENODEV; |
| 3794 | |
| 3795 | return single_open(file, spr_wm_latency_show, dev); |
| 3796 | } |
| 3797 | |
| 3798 | static int cur_wm_latency_open(struct inode *inode, struct file *file) |
| 3799 | { |
| 3800 | struct drm_device *dev = inode->i_private; |
| 3801 | |
Sonika Jindal | 9ad0257 | 2014-07-21 15:23:39 +0530 | [diff] [blame] | 3802 | if (HAS_GMCH_DISPLAY(dev)) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3803 | return -ENODEV; |
| 3804 | |
| 3805 | return single_open(file, cur_wm_latency_show, dev); |
| 3806 | } |
| 3807 | |
| 3808 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3809 | size_t len, loff_t *offp, uint16_t wm[8]) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3810 | { |
| 3811 | struct seq_file *m = file->private_data; |
| 3812 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3813 | uint16_t new[8] = { 0 }; |
Damien Lespiau | 546c81f | 2014-05-13 15:30:26 +0100 | [diff] [blame] | 3814 | int num_levels = ilk_wm_max_level(dev) + 1; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3815 | int level; |
| 3816 | int ret; |
| 3817 | char tmp[32]; |
| 3818 | |
| 3819 | if (len >= sizeof(tmp)) |
| 3820 | return -EINVAL; |
| 3821 | |
| 3822 | if (copy_from_user(tmp, ubuf, len)) |
| 3823 | return -EFAULT; |
| 3824 | |
| 3825 | tmp[len] = '\0'; |
| 3826 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3827 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
| 3828 | &new[0], &new[1], &new[2], &new[3], |
| 3829 | &new[4], &new[5], &new[6], &new[7]); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3830 | if (ret != num_levels) |
| 3831 | return -EINVAL; |
| 3832 | |
| 3833 | drm_modeset_lock_all(dev); |
| 3834 | |
| 3835 | for (level = 0; level < num_levels; level++) |
| 3836 | wm[level] = new[level]; |
| 3837 | |
| 3838 | drm_modeset_unlock_all(dev); |
| 3839 | |
| 3840 | return len; |
| 3841 | } |
| 3842 | |
| 3843 | |
| 3844 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, |
| 3845 | size_t len, loff_t *offp) |
| 3846 | { |
| 3847 | struct seq_file *m = file->private_data; |
| 3848 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3849 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3850 | uint16_t *latencies; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3851 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3852 | if (INTEL_INFO(dev)->gen >= 9) |
| 3853 | latencies = dev_priv->wm.skl_latency; |
| 3854 | else |
| 3855 | latencies = to_i915(dev)->wm.pri_latency; |
| 3856 | |
| 3857 | return wm_latency_write(file, ubuf, len, offp, latencies); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3858 | } |
| 3859 | |
| 3860 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, |
| 3861 | size_t len, loff_t *offp) |
| 3862 | { |
| 3863 | struct seq_file *m = file->private_data; |
| 3864 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3865 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3866 | uint16_t *latencies; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3867 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3868 | if (INTEL_INFO(dev)->gen >= 9) |
| 3869 | latencies = dev_priv->wm.skl_latency; |
| 3870 | else |
| 3871 | latencies = to_i915(dev)->wm.spr_latency; |
| 3872 | |
| 3873 | return wm_latency_write(file, ubuf, len, offp, latencies); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3874 | } |
| 3875 | |
| 3876 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, |
| 3877 | size_t len, loff_t *offp) |
| 3878 | { |
| 3879 | struct seq_file *m = file->private_data; |
| 3880 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3881 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3882 | uint16_t *latencies; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3883 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3884 | if (INTEL_INFO(dev)->gen >= 9) |
| 3885 | latencies = dev_priv->wm.skl_latency; |
| 3886 | else |
| 3887 | latencies = to_i915(dev)->wm.cur_latency; |
| 3888 | |
| 3889 | return wm_latency_write(file, ubuf, len, offp, latencies); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3890 | } |
| 3891 | |
| 3892 | static const struct file_operations i915_pri_wm_latency_fops = { |
| 3893 | .owner = THIS_MODULE, |
| 3894 | .open = pri_wm_latency_open, |
| 3895 | .read = seq_read, |
| 3896 | .llseek = seq_lseek, |
| 3897 | .release = single_release, |
| 3898 | .write = pri_wm_latency_write |
| 3899 | }; |
| 3900 | |
| 3901 | static const struct file_operations i915_spr_wm_latency_fops = { |
| 3902 | .owner = THIS_MODULE, |
| 3903 | .open = spr_wm_latency_open, |
| 3904 | .read = seq_read, |
| 3905 | .llseek = seq_lseek, |
| 3906 | .release = single_release, |
| 3907 | .write = spr_wm_latency_write |
| 3908 | }; |
| 3909 | |
| 3910 | static const struct file_operations i915_cur_wm_latency_fops = { |
| 3911 | .owner = THIS_MODULE, |
| 3912 | .open = cur_wm_latency_open, |
| 3913 | .read = seq_read, |
| 3914 | .llseek = seq_lseek, |
| 3915 | .release = single_release, |
| 3916 | .write = cur_wm_latency_write |
| 3917 | }; |
| 3918 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3919 | static int |
| 3920 | i915_wedged_get(void *data, u64 *val) |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3921 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3922 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 3923 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3924 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3925 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3926 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3927 | return 0; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3928 | } |
| 3929 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3930 | static int |
| 3931 | i915_wedged_set(void *data, u64 val) |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3932 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3933 | struct drm_device *dev = data; |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 3934 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3935 | |
| 3936 | intel_runtime_pm_get(dev_priv); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3937 | |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 3938 | i915_handle_error(dev, val, |
| 3939 | "Manually setting wedged to %llu", val); |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 3940 | |
| 3941 | intel_runtime_pm_put(dev_priv); |
| 3942 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3943 | return 0; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3944 | } |
| 3945 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3946 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
| 3947 | i915_wedged_get, i915_wedged_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 3948 | "%llu\n"); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3949 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3950 | static int |
| 3951 | i915_ring_stop_get(void *data, u64 *val) |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3952 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3953 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 3954 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3955 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3956 | *val = dev_priv->gpu_error.stop_rings; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3957 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3958 | return 0; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3959 | } |
| 3960 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3961 | static int |
| 3962 | i915_ring_stop_set(void *data, u64 val) |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3963 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3964 | struct drm_device *dev = data; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3965 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3966 | int ret; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3967 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3968 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3969 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 3970 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 3971 | if (ret) |
| 3972 | return ret; |
| 3973 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 3974 | dev_priv->gpu_error.stop_rings = val; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3975 | mutex_unlock(&dev->struct_mutex); |
| 3976 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3977 | return 0; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3978 | } |
| 3979 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3980 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
| 3981 | i915_ring_stop_get, i915_ring_stop_set, |
| 3982 | "0x%08llx\n"); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 3983 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 3984 | static int |
| 3985 | i915_ring_missed_irq_get(void *data, u64 *val) |
| 3986 | { |
| 3987 | struct drm_device *dev = data; |
| 3988 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3989 | |
| 3990 | *val = dev_priv->gpu_error.missed_irq_rings; |
| 3991 | return 0; |
| 3992 | } |
| 3993 | |
| 3994 | static int |
| 3995 | i915_ring_missed_irq_set(void *data, u64 val) |
| 3996 | { |
| 3997 | struct drm_device *dev = data; |
| 3998 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3999 | int ret; |
| 4000 | |
| 4001 | /* Lock against concurrent debugfs callers */ |
| 4002 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 4003 | if (ret) |
| 4004 | return ret; |
| 4005 | dev_priv->gpu_error.missed_irq_rings = val; |
| 4006 | mutex_unlock(&dev->struct_mutex); |
| 4007 | |
| 4008 | return 0; |
| 4009 | } |
| 4010 | |
| 4011 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, |
| 4012 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, |
| 4013 | "0x%08llx\n"); |
| 4014 | |
| 4015 | static int |
| 4016 | i915_ring_test_irq_get(void *data, u64 *val) |
| 4017 | { |
| 4018 | struct drm_device *dev = data; |
| 4019 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4020 | |
| 4021 | *val = dev_priv->gpu_error.test_irq_rings; |
| 4022 | |
| 4023 | return 0; |
| 4024 | } |
| 4025 | |
| 4026 | static int |
| 4027 | i915_ring_test_irq_set(void *data, u64 val) |
| 4028 | { |
| 4029 | struct drm_device *dev = data; |
| 4030 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4031 | int ret; |
| 4032 | |
| 4033 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
| 4034 | |
| 4035 | /* Lock against concurrent debugfs callers */ |
| 4036 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 4037 | if (ret) |
| 4038 | return ret; |
| 4039 | |
| 4040 | dev_priv->gpu_error.test_irq_rings = val; |
| 4041 | mutex_unlock(&dev->struct_mutex); |
| 4042 | |
| 4043 | return 0; |
| 4044 | } |
| 4045 | |
| 4046 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, |
| 4047 | i915_ring_test_irq_get, i915_ring_test_irq_set, |
| 4048 | "0x%08llx\n"); |
| 4049 | |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4050 | #define DROP_UNBOUND 0x1 |
| 4051 | #define DROP_BOUND 0x2 |
| 4052 | #define DROP_RETIRE 0x4 |
| 4053 | #define DROP_ACTIVE 0x8 |
| 4054 | #define DROP_ALL (DROP_UNBOUND | \ |
| 4055 | DROP_BOUND | \ |
| 4056 | DROP_RETIRE | \ |
| 4057 | DROP_ACTIVE) |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4058 | static int |
| 4059 | i915_drop_caches_get(void *data, u64 *val) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4060 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4061 | *val = DROP_ALL; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4062 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4063 | return 0; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4064 | } |
| 4065 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4066 | static int |
| 4067 | i915_drop_caches_set(void *data, u64 val) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4068 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4069 | struct drm_device *dev = data; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4070 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4071 | int ret; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4072 | |
Ben Widawsky | 2f9fe5f | 2013-11-25 09:54:37 -0800 | [diff] [blame] | 4073 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4074 | |
| 4075 | /* No need to check and wait for gpu resets, only libdrm auto-restarts |
| 4076 | * on ioctls on -EAGAIN. */ |
| 4077 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 4078 | if (ret) |
| 4079 | return ret; |
| 4080 | |
| 4081 | if (val & DROP_ACTIVE) { |
| 4082 | ret = i915_gpu_idle(dev); |
| 4083 | if (ret) |
| 4084 | goto unlock; |
| 4085 | } |
| 4086 | |
| 4087 | if (val & (DROP_RETIRE | DROP_ACTIVE)) |
| 4088 | i915_gem_retire_requests(dev); |
| 4089 | |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 4090 | if (val & DROP_BOUND) |
| 4091 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); |
Chris Wilson | 4ad72b7 | 2014-09-03 19:23:37 +0100 | [diff] [blame] | 4092 | |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 4093 | if (val & DROP_UNBOUND) |
| 4094 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4095 | |
| 4096 | unlock: |
| 4097 | mutex_unlock(&dev->struct_mutex); |
| 4098 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4099 | return ret; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4100 | } |
| 4101 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4102 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
| 4103 | i915_drop_caches_get, i915_drop_caches_set, |
| 4104 | "0x%08llx\n"); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4105 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4106 | static int |
| 4107 | i915_max_freq_get(void *data, u64 *val) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4108 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4109 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 4110 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4111 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4112 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 4113 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4114 | return -ENODEV; |
| 4115 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 4116 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 4117 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4118 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4119 | if (ret) |
| 4120 | return ret; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4121 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4122 | if (IS_VALLEYVIEW(dev)) |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4123 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4124 | else |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4125 | *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4126 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4127 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4128 | return 0; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4129 | } |
| 4130 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4131 | static int |
| 4132 | i915_max_freq_set(void *data, u64 val) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4133 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4134 | struct drm_device *dev = data; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4135 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4136 | u32 rp_state_cap, hw_max, hw_min; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4137 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4138 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 4139 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4140 | return -ENODEV; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4141 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 4142 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 4143 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4144 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4145 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4146 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4147 | if (ret) |
| 4148 | return ret; |
| 4149 | |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4150 | /* |
| 4151 | * Turbo will still be enabled, but won't go above the set value. |
| 4152 | */ |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4153 | if (IS_VALLEYVIEW(dev)) { |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 4154 | val = vlv_freq_opcode(dev_priv, val); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4155 | |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 4156 | hw_max = dev_priv->rps.max_freq; |
| 4157 | hw_min = dev_priv->rps.min_freq; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4158 | } else { |
| 4159 | do_div(val, GT_FREQUENCY_MULTIPLIER); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4160 | |
| 4161 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4162 | hw_max = dev_priv->rps.max_freq; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4163 | hw_min = (rp_state_cap >> 16) & 0xff; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4164 | } |
| 4165 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4166 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4167 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 4168 | return -EINVAL; |
| 4169 | } |
| 4170 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4171 | dev_priv->rps.max_freq_softlimit = val; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4172 | |
| 4173 | if (IS_VALLEYVIEW(dev)) |
| 4174 | valleyview_set_rps(dev, val); |
| 4175 | else |
| 4176 | gen6_set_rps(dev, val); |
| 4177 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4178 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4179 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4180 | return 0; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4181 | } |
| 4182 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4183 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
| 4184 | i915_max_freq_get, i915_max_freq_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 4185 | "%llu\n"); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4186 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4187 | static int |
| 4188 | i915_min_freq_get(void *data, u64 *val) |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4189 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4190 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 4191 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4192 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4193 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 4194 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4195 | return -ENODEV; |
| 4196 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 4197 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 4198 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4199 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4200 | if (ret) |
| 4201 | return ret; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4202 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4203 | if (IS_VALLEYVIEW(dev)) |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4204 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4205 | else |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4206 | *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4207 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4208 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4209 | return 0; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4210 | } |
| 4211 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4212 | static int |
| 4213 | i915_min_freq_set(void *data, u64 val) |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4214 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4215 | struct drm_device *dev = data; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4216 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4217 | u32 rp_state_cap, hw_max, hw_min; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4218 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4219 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 4220 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4221 | return -ENODEV; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4222 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 4223 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 4224 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4225 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4226 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4227 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4228 | if (ret) |
| 4229 | return ret; |
| 4230 | |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4231 | /* |
| 4232 | * Turbo will still be enabled, but won't go below the set value. |
| 4233 | */ |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4234 | if (IS_VALLEYVIEW(dev)) { |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 4235 | val = vlv_freq_opcode(dev_priv, val); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4236 | |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 4237 | hw_max = dev_priv->rps.max_freq; |
| 4238 | hw_min = dev_priv->rps.min_freq; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4239 | } else { |
| 4240 | do_div(val, GT_FREQUENCY_MULTIPLIER); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4241 | |
| 4242 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4243 | hw_max = dev_priv->rps.max_freq; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4244 | hw_min = (rp_state_cap >> 16) & 0xff; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4245 | } |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4246 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4247 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4248 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 4249 | return -EINVAL; |
| 4250 | } |
| 4251 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4252 | dev_priv->rps.min_freq_softlimit = val; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4253 | |
| 4254 | if (IS_VALLEYVIEW(dev)) |
| 4255 | valleyview_set_rps(dev, val); |
| 4256 | else |
| 4257 | gen6_set_rps(dev, val); |
| 4258 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4259 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4260 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4261 | return 0; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4262 | } |
| 4263 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4264 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
| 4265 | i915_min_freq_get, i915_min_freq_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 4266 | "%llu\n"); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4267 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4268 | static int |
| 4269 | i915_cache_sharing_get(void *data, u64 *val) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4270 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4271 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 4272 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4273 | u32 snpcr; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4274 | int ret; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4275 | |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4276 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 4277 | return -ENODEV; |
| 4278 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 4279 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 4280 | if (ret) |
| 4281 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4282 | intel_runtime_pm_get(dev_priv); |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 4283 | |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4284 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4285 | |
| 4286 | intel_runtime_pm_put(dev_priv); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4287 | mutex_unlock(&dev_priv->dev->struct_mutex); |
| 4288 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4289 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4290 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4291 | return 0; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4292 | } |
| 4293 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4294 | static int |
| 4295 | i915_cache_sharing_set(void *data, u64 val) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4296 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4297 | struct drm_device *dev = data; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4298 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4299 | u32 snpcr; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4300 | |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4301 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 4302 | return -ENODEV; |
| 4303 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4304 | if (val > 3) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4305 | return -EINVAL; |
| 4306 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4307 | intel_runtime_pm_get(dev_priv); |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4308 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4309 | |
| 4310 | /* Update the cache sharing policy here as well */ |
| 4311 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
| 4312 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
| 4313 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); |
| 4314 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
| 4315 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4316 | intel_runtime_pm_put(dev_priv); |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4317 | return 0; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4318 | } |
| 4319 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4320 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
| 4321 | i915_cache_sharing_get, i915_cache_sharing_set, |
| 4322 | "%llu\n"); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4323 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4324 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
| 4325 | { |
| 4326 | struct drm_device *dev = inode->i_private; |
| 4327 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4328 | |
Daniel Vetter | 075edca | 2012-01-24 09:44:28 +0100 | [diff] [blame] | 4329 | if (INTEL_INFO(dev)->gen < 6) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4330 | return 0; |
| 4331 | |
Chris Wilson | 6daccb0 | 2015-01-16 11:34:35 +0200 | [diff] [blame] | 4332 | intel_runtime_pm_get(dev_priv); |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4333 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4334 | |
| 4335 | return 0; |
| 4336 | } |
| 4337 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 4338 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4339 | { |
| 4340 | struct drm_device *dev = inode->i_private; |
| 4341 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4342 | |
Daniel Vetter | 075edca | 2012-01-24 09:44:28 +0100 | [diff] [blame] | 4343 | if (INTEL_INFO(dev)->gen < 6) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4344 | return 0; |
| 4345 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 4346 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Chris Wilson | 6daccb0 | 2015-01-16 11:34:35 +0200 | [diff] [blame] | 4347 | intel_runtime_pm_put(dev_priv); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4348 | |
| 4349 | return 0; |
| 4350 | } |
| 4351 | |
| 4352 | static const struct file_operations i915_forcewake_fops = { |
| 4353 | .owner = THIS_MODULE, |
| 4354 | .open = i915_forcewake_open, |
| 4355 | .release = i915_forcewake_release, |
| 4356 | }; |
| 4357 | |
| 4358 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) |
| 4359 | { |
| 4360 | struct drm_device *dev = minor->dev; |
| 4361 | struct dentry *ent; |
| 4362 | |
| 4363 | ent = debugfs_create_file("i915_forcewake_user", |
Ben Widawsky | 8eb5729 | 2011-05-11 15:10:58 -0700 | [diff] [blame] | 4364 | S_IRUSR, |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4365 | root, dev, |
| 4366 | &i915_forcewake_fops); |
Wei Yongjun | f3c5fe9 | 2013-12-16 14:13:25 +0800 | [diff] [blame] | 4367 | if (!ent) |
| 4368 | return -ENOMEM; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4369 | |
Ben Widawsky | 8eb5729 | 2011-05-11 15:10:58 -0700 | [diff] [blame] | 4370 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4371 | } |
| 4372 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 4373 | static int i915_debugfs_create(struct dentry *root, |
| 4374 | struct drm_minor *minor, |
| 4375 | const char *name, |
| 4376 | const struct file_operations *fops) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4377 | { |
| 4378 | struct drm_device *dev = minor->dev; |
| 4379 | struct dentry *ent; |
| 4380 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 4381 | ent = debugfs_create_file(name, |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4382 | S_IRUGO | S_IWUSR, |
| 4383 | root, dev, |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 4384 | fops); |
Wei Yongjun | f3c5fe9 | 2013-12-16 14:13:25 +0800 | [diff] [blame] | 4385 | if (!ent) |
| 4386 | return -ENOMEM; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4387 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 4388 | return drm_add_fake_info_node(minor, ent, fops); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4389 | } |
| 4390 | |
Lespiau, Damien | 06c5bf8 | 2013-10-17 19:09:56 +0100 | [diff] [blame] | 4391 | static const struct drm_info_list i915_debugfs_list[] = { |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 4392 | {"i915_capabilities", i915_capabilities, 0}, |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4393 | {"i915_gem_objects", i915_gem_object_info, 0}, |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 4394 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 4395 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 4396 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 4397 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 4398 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 4399 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4400 | {"i915_gem_request", i915_gem_request_info, 0}, |
| 4401 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 4402 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4403 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 4404 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
| 4405 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, |
| 4406 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, |
Xiang, Haihao | 9010ebf | 2013-05-29 09:22:36 -0700 | [diff] [blame] | 4407 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
Brad Volkin | 493018d | 2014-12-11 12:13:08 -0800 | [diff] [blame] | 4408 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
Deepak S | adb4bd1 | 2014-03-31 11:30:02 +0530 | [diff] [blame] | 4409 | {"i915_frequency_info", i915_frequency_info, 0}, |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 4410 | {"i915_drpc_info", i915_drpc_info, 0}, |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 4411 | {"i915_emon_status", i915_emon_status, 0}, |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 4412 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 4413 | {"i915_fbc_status", i915_fbc_status, 0}, |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 4414 | {"i915_ips_status", i915_ips_status, 0}, |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 4415 | {"i915_sr_status", i915_sr_status, 0}, |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 4416 | {"i915_opregion", i915_opregion, 0}, |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 4417 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 4418 | {"i915_context_status", i915_context_status, 0}, |
Ben Widawsky | c0ab1ae | 2014-08-07 13:24:26 +0100 | [diff] [blame] | 4419 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 4420 | {"i915_execlists", i915_execlists, 0}, |
Mika Kuoppala | f65367b | 2015-01-16 11:34:42 +0200 | [diff] [blame] | 4421 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 4422 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 4423 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 4424 | {"i915_llc", i915_llc, 0}, |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 4425 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 4426 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 4427 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 4428 | {"i915_pc8_status", i915_pc8_status, 0}, |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 4429 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 4430 | {"i915_display_info", i915_display_info, 0}, |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 4431 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
Daniel Vetter | 728e29d | 2014-06-25 22:01:53 +0300 | [diff] [blame] | 4432 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
Dave Airlie | 11bed958 | 2014-05-12 15:22:27 +1000 | [diff] [blame] | 4433 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
Damien Lespiau | 1ed1ef9 | 2014-08-30 16:50:59 +0100 | [diff] [blame] | 4434 | {"i915_wa_registers", i915_wa_registers, 0}, |
Damien Lespiau | c5511e4 | 2014-11-04 17:06:51 +0000 | [diff] [blame] | 4435 | {"i915_ddb_info", i915_ddb_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4436 | }; |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 4437 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4438 | |
Lespiau, Damien | 06c5bf8 | 2013-10-17 19:09:56 +0100 | [diff] [blame] | 4439 | static const struct i915_debugfs_files { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4440 | const char *name; |
| 4441 | const struct file_operations *fops; |
| 4442 | } i915_debugfs_files[] = { |
| 4443 | {"i915_wedged", &i915_wedged_fops}, |
| 4444 | {"i915_max_freq", &i915_max_freq_fops}, |
| 4445 | {"i915_min_freq", &i915_min_freq_fops}, |
| 4446 | {"i915_cache_sharing", &i915_cache_sharing_fops}, |
| 4447 | {"i915_ring_stop", &i915_ring_stop_fops}, |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 4448 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
| 4449 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4450 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
| 4451 | {"i915_error_state", &i915_error_state_fops}, |
| 4452 | {"i915_next_seqno", &i915_next_seqno_fops}, |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 4453 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4454 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
| 4455 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, |
| 4456 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, |
Rodrigo Vivi | da46f93 | 2014-08-01 02:04:45 -0700 | [diff] [blame] | 4457 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4458 | }; |
| 4459 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4460 | void intel_display_crc_init(struct drm_device *dev) |
| 4461 | { |
| 4462 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | b378360 | 2013-11-14 11:30:42 +0100 | [diff] [blame] | 4463 | enum pipe pipe; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4464 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4465 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | b378360 | 2013-11-14 11:30:42 +0100 | [diff] [blame] | 4466 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4467 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 4468 | pipe_crc->opened = false; |
| 4469 | spin_lock_init(&pipe_crc->lock); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4470 | init_waitqueue_head(&pipe_crc->wq); |
| 4471 | } |
| 4472 | } |
| 4473 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 4474 | int i915_debugfs_init(struct drm_minor *minor) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4475 | { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4476 | int ret, i; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 4477 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4478 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
| 4479 | if (ret) |
| 4480 | return ret; |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 4481 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4482 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
| 4483 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); |
| 4484 | if (ret) |
| 4485 | return ret; |
| 4486 | } |
| 4487 | |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4488 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
| 4489 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
| 4490 | i915_debugfs_files[i].name, |
| 4491 | i915_debugfs_files[i].fops); |
| 4492 | if (ret) |
| 4493 | return ret; |
| 4494 | } |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 4495 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 4496 | return drm_debugfs_create_files(i915_debugfs_list, |
| 4497 | I915_DEBUGFS_ENTRIES, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4498 | minor->debugfs_root, minor); |
| 4499 | } |
| 4500 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 4501 | void i915_debugfs_cleanup(struct drm_minor *minor) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4502 | { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4503 | int i; |
| 4504 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 4505 | drm_debugfs_remove_files(i915_debugfs_list, |
| 4506 | I915_DEBUGFS_ENTRIES, minor); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4507 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4508 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
| 4509 | 1, minor); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4510 | |
Daniel Vetter | e309a99 | 2013-10-16 22:55:51 +0200 | [diff] [blame] | 4511 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4512 | struct drm_info_list *info_list = |
| 4513 | (struct drm_info_list *)&i915_pipe_crc_data[i]; |
| 4514 | |
| 4515 | drm_debugfs_remove_files(info_list, 1, minor); |
| 4516 | } |
| 4517 | |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4518 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
| 4519 | struct drm_info_list *info_list = |
| 4520 | (struct drm_info_list *) i915_debugfs_files[i].fops; |
| 4521 | |
| 4522 | drm_debugfs_remove_files(info_list, 1, minor); |
| 4523 | } |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4524 | } |