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Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Petr Machata803335a2018-02-27 14:53:46 +01003 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
Jiri Pirko22a67762017-02-03 10:29:07 +01004 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +020056#include <linux/netlink.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020057#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020058#include <net/pkt_cls.h>
59#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020060#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010061#include <net/tc_act/tc_sample.h>
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +020062#include <net/addrconf.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020063
64#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020065#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020066#include "core.h"
67#include "reg.h"
68#include "port.h"
69#include "trap.h"
70#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010071#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020072#include "spectrum_dpipe.h"
Yotam Gigid3b939b2017-09-19 10:00:09 +020073#include "spectrum_acl_flex_actions.h"
Petr Machataa629ef22018-02-13 11:27:48 +010074#include "spectrum_span.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020075#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020076
Jiri Pirkoabfd6182018-07-08 23:51:26 +030077#define MLXSW_SP_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
Yotam Gigi6b742192017-05-23 21:56:29 +020078
Jiri Pirkoabfd6182018-07-08 23:51:26 +030079#define MLXSW_SP1_FWREV_MAJOR 13
80#define MLXSW_SP1_FWREV_MINOR 1620
81#define MLXSW_SP1_FWREV_SUBMINOR 192
82
83static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
84 .major = MLXSW_SP1_FWREV_MAJOR,
85 .minor = MLXSW_SP1_FWREV_MINOR,
86 .subminor = MLXSW_SP1_FWREV_SUBMINOR,
87};
88
89#define MLXSW_SP1_FW_FILENAME \
90 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
91 "." __stringify(MLXSW_SP1_FWREV_MINOR) \
92 "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2"
Yotam Gigi6b742192017-05-23 21:56:29 +020093
Jiri Pirko56ade8f2015-10-16 14:01:37 +020094static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
95static const char mlxsw_sp_driver_version[] = "1.0";
96
97/* tx_hdr_version
98 * Tx header version.
99 * Must be set to 1.
100 */
101MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
102
103/* tx_hdr_ctl
104 * Packet control type.
105 * 0 - Ethernet control (e.g. EMADs, LACP)
106 * 1 - Ethernet data
107 */
108MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
109
110/* tx_hdr_proto
111 * Packet protocol type. Must be set to 1 (Ethernet).
112 */
113MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
114
115/* tx_hdr_rx_is_router
116 * Packet is sent from the router. Valid for data packets only.
117 */
118MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
119
120/* tx_hdr_fid_valid
121 * Indicates if the 'fid' field is valid and should be used for
122 * forwarding lookup. Valid for data packets only.
123 */
124MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
125
126/* tx_hdr_swid
127 * Switch partition ID. Must be set to 0.
128 */
129MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
130
131/* tx_hdr_control_tclass
132 * Indicates if the packet should use the control TClass and not one
133 * of the data TClasses.
134 */
135MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
136
137/* tx_hdr_etclass
138 * Egress TClass to be used on the egress device on the egress port.
139 */
140MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
141
142/* tx_hdr_port_mid
143 * Destination local port for unicast packets.
144 * Destination multicast ID for multicast packets.
145 *
146 * Control packets are directed to a specific egress port, while data
147 * packets are transmitted through the CPU port (0) into the switch partition,
148 * where forwarding rules are applied.
149 */
150MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
151
152/* tx_hdr_fid
153 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
154 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
155 * Valid for data packets only.
156 */
157MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
158
159/* tx_hdr_type
160 * 0 - Data packets
161 * 6 - Control packets
162 */
163MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
164
Yotam Gigie5e5c882017-05-23 21:56:27 +0200165struct mlxsw_sp_mlxfw_dev {
166 struct mlxfw_dev mlxfw_dev;
167 struct mlxsw_sp *mlxsw_sp;
168};
169
170static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
171 u16 component_index, u32 *p_max_size,
172 u8 *p_align_bits, u16 *p_max_write_size)
173{
174 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
175 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
176 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
177 char mcqi_pl[MLXSW_REG_MCQI_LEN];
178 int err;
179
180 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
181 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
182 if (err)
183 return err;
184 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
185 p_max_write_size);
186
187 *p_align_bits = max_t(u8, *p_align_bits, 2);
188 *p_max_write_size = min_t(u16, *p_max_write_size,
189 MLXSW_REG_MCDA_MAX_DATA_LEN);
190 return 0;
191}
192
193static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
194{
195 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
196 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
197 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
198 char mcc_pl[MLXSW_REG_MCC_LEN];
199 u8 control_state;
200 int err;
201
202 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
203 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
204 if (err)
205 return err;
206
207 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
208 if (control_state != MLXFW_FSM_STATE_IDLE)
209 return -EBUSY;
210
211 mlxsw_reg_mcc_pack(mcc_pl,
212 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
213 0, *fwhandle, 0);
214 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
215}
216
217static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
218 u32 fwhandle, u16 component_index,
219 u32 component_size)
220{
221 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
222 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
223 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
224 char mcc_pl[MLXSW_REG_MCC_LEN];
225
226 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
227 component_index, fwhandle, component_size);
228 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
229}
230
231static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
232 u32 fwhandle, u8 *data, u16 size,
233 u32 offset)
234{
235 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
236 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
237 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
238 char mcda_pl[MLXSW_REG_MCDA_LEN];
239
240 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
241 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
242}
243
244static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
245 u32 fwhandle, u16 component_index)
246{
247 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
248 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
249 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
250 char mcc_pl[MLXSW_REG_MCC_LEN];
251
252 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
253 component_index, fwhandle, 0);
254 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
255}
256
257static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
258{
259 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
260 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
261 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
262 char mcc_pl[MLXSW_REG_MCC_LEN];
263
264 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
265 fwhandle, 0);
266 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
267}
268
269static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
270 enum mlxfw_fsm_state *fsm_state,
271 enum mlxfw_fsm_state_err *fsm_state_err)
272{
273 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
274 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
275 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
276 char mcc_pl[MLXSW_REG_MCC_LEN];
277 u8 control_state;
278 u8 error_code;
279 int err;
280
281 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
282 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
283 if (err)
284 return err;
285
286 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
287 *fsm_state = control_state;
288 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
289 MLXFW_FSM_STATE_ERR_MAX);
290 return 0;
291}
292
293static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
294{
295 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
296 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
297 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
298 char mcc_pl[MLXSW_REG_MCC_LEN];
299
300 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
301 fwhandle, 0);
302 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
303}
304
305static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
306{
307 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
308 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
309 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
310 char mcc_pl[MLXSW_REG_MCC_LEN];
311
312 mlxsw_reg_mcc_pack(mcc_pl,
313 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
314 fwhandle, 0);
315 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
316}
317
318static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
319 .component_query = mlxsw_sp_component_query,
320 .fsm_lock = mlxsw_sp_fsm_lock,
321 .fsm_component_update = mlxsw_sp_fsm_component_update,
322 .fsm_block_download = mlxsw_sp_fsm_block_download,
323 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
324 .fsm_activate = mlxsw_sp_fsm_activate,
325 .fsm_query_state = mlxsw_sp_fsm_query_state,
326 .fsm_cancel = mlxsw_sp_fsm_cancel,
327 .fsm_release = mlxsw_sp_fsm_release
328};
329
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300330static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
331 const struct firmware *firmware)
332{
333 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
334 .mlxfw_dev = {
335 .ops = &mlxsw_sp_mlxfw_dev_ops,
336 .psid = mlxsw_sp->bus_info->psid,
337 .psid_size = strlen(mlxsw_sp->bus_info->psid),
338 },
339 .mlxsw_sp = mlxsw_sp
340 };
341
342 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
343}
344
Yotam Gigi6b742192017-05-23 21:56:29 +0200345static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
346{
347 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
Jiri Pirkoabfd6182018-07-08 23:51:26 +0300348 const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev;
349 const char *fw_filename = mlxsw_sp->fw_filename;
Yotam Gigi6b742192017-05-23 21:56:29 +0200350 const struct firmware *firmware;
351 int err;
352
Jiri Pirkoabfd6182018-07-08 23:51:26 +0300353 /* Don't check if driver does not require it */
354 if (!req_rev || !fw_filename)
355 return 0;
356
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100357 /* Validate driver & FW are compatible */
Jiri Pirkoabfd6182018-07-08 23:51:26 +0300358 if (rev->major != req_rev->major) {
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100359 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
Jiri Pirkoabfd6182018-07-08 23:51:26 +0300360 rev->major, req_rev->major);
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100361 return -EINVAL;
362 }
Jiri Pirkoabfd6182018-07-08 23:51:26 +0300363 if (MLXSW_SP_FWREV_MINOR_TO_BRANCH(rev->minor) ==
364 MLXSW_SP_FWREV_MINOR_TO_BRANCH(req_rev->minor))
Yotam Gigi6b742192017-05-23 21:56:29 +0200365 return 0;
366
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100367 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200368 rev->major, rev->minor, rev->subminor);
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100369 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
Jiri Pirkoabfd6182018-07-08 23:51:26 +0300370 fw_filename);
Yotam Gigi6b742192017-05-23 21:56:29 +0200371
Jiri Pirkoabfd6182018-07-08 23:51:26 +0300372 err = request_firmware_direct(&firmware, fw_filename,
Yotam Gigi6b742192017-05-23 21:56:29 +0200373 mlxsw_sp->bus_info->dev);
374 if (err) {
375 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
Jiri Pirkoabfd6182018-07-08 23:51:26 +0300376 fw_filename);
Yotam Gigi6b742192017-05-23 21:56:29 +0200377 return err;
378 }
379
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300380 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
Yotam Gigi6b742192017-05-23 21:56:29 +0200381 release_firmware(firmware);
382 return err;
383}
384
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100385int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
386 unsigned int counter_index, u64 *packets,
387 u64 *bytes)
388{
389 char mgpc_pl[MLXSW_REG_MGPC_LEN];
390 int err;
391
392 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200393 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100394 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
395 if (err)
396 return err;
Arkadi Sharshevsky7cfcbc72017-08-24 08:40:08 +0200397 if (packets)
398 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
399 if (bytes)
400 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100401 return 0;
402}
403
404static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
405 unsigned int counter_index)
406{
407 char mgpc_pl[MLXSW_REG_MGPC_LEN];
408
409 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200410 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100411 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
412}
413
414int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
415 unsigned int *p_counter_index)
416{
417 int err;
418
419 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
420 p_counter_index);
421 if (err)
422 return err;
423 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
424 if (err)
425 goto err_counter_clear;
426 return 0;
427
428err_counter_clear:
429 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
430 *p_counter_index);
431 return err;
432}
433
434void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
435 unsigned int counter_index)
436{
437 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
438 counter_index);
439}
440
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200441static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
442 const struct mlxsw_tx_info *tx_info)
443{
444 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
445
446 memset(txhdr, 0, MLXSW_TXHDR_LEN);
447
448 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
449 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
450 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
451 mlxsw_tx_hdr_swid_set(txhdr, 0);
452 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
453 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
454 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
455}
456
Petr Machata541e1152018-04-29 10:56:09 +0300457enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200458{
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200459 switch (state) {
460 case BR_STATE_FORWARDING:
Petr Machata541e1152018-04-29 10:56:09 +0300461 return MLXSW_REG_SPMS_STATE_FORWARDING;
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200462 case BR_STATE_LEARNING:
Petr Machata541e1152018-04-29 10:56:09 +0300463 return MLXSW_REG_SPMS_STATE_LEARNING;
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200464 case BR_STATE_LISTENING: /* fall-through */
465 case BR_STATE_DISABLED: /* fall-through */
466 case BR_STATE_BLOCKING:
Petr Machata541e1152018-04-29 10:56:09 +0300467 return MLXSW_REG_SPMS_STATE_DISCARDING;
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200468 default:
469 BUG();
470 }
Petr Machata541e1152018-04-29 10:56:09 +0300471}
472
473int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
474 u8 state)
475{
476 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
477 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
478 char *spms_pl;
479 int err;
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200480
481 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
482 if (!spms_pl)
483 return -ENOMEM;
484 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
485 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
486
487 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
488 kfree(spms_pl);
489 return err;
490}
491
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200492static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
493{
Elad Raz5b090742016-10-28 21:35:46 +0200494 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200495 int err;
496
497 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
498 if (err)
499 return err;
500 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
501 return 0;
502}
503
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100504static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
505 bool enable, u32 rate)
506{
507 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
508 char mpsc_pl[MLXSW_REG_MPSC_LEN];
509
510 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
511 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
512}
513
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200514static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
515 bool is_up)
516{
517 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
518 char paos_pl[MLXSW_REG_PAOS_LEN];
519
520 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
521 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
522 MLXSW_PORT_ADMIN_STATUS_DOWN);
523 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
524}
525
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200526static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
527 unsigned char *addr)
528{
529 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
530 char ppad_pl[MLXSW_REG_PPAD_LEN];
531
532 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
533 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
534 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
535}
536
537static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
538{
539 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
540 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
541
542 ether_addr_copy(addr, mlxsw_sp->base_mac);
543 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
544 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
545}
546
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200547static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
548{
549 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
550 char pmtu_pl[MLXSW_REG_PMTU_LEN];
551 int max_mtu;
552 int err;
553
554 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
555 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
556 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
557 if (err)
558 return err;
559 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
560
561 if (mtu > max_mtu)
562 return -EINVAL;
563
564 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
565 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
566}
567
568static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
569{
570 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel5b153852017-06-08 08:47:44 +0200571 char pspa_pl[MLXSW_REG_PSPA_LEN];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200572
Ido Schimmel5b153852017-06-08 08:47:44 +0200573 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
574 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200575}
576
Ido Schimmela1107482017-05-26 08:37:39 +0200577int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200578{
579 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
580 char svpe_pl[MLXSW_REG_SVPE_LEN];
581
582 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
583 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
584}
585
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200586int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
587 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200588{
589 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
590 char *spvmlr_pl;
591 int err;
592
593 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
594 if (!spvmlr_pl)
595 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200596 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
597 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200598 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
599 kfree(spvmlr_pl);
600 return err;
601}
602
Ido Schimmelb02eae92017-05-16 19:38:34 +0200603static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
604 u16 vid)
605{
606 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
607 char spvid_pl[MLXSW_REG_SPVID_LEN];
608
609 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
610 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
611}
612
613static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
614 bool allow)
615{
616 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
617 char spaft_pl[MLXSW_REG_SPAFT_LEN];
618
619 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
620 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
621}
622
623int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
624{
625 int err;
626
627 if (!vid) {
628 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
629 if (err)
630 return err;
631 } else {
632 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
633 if (err)
634 return err;
635 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
636 if (err)
637 goto err_port_allow_untagged_set;
638 }
639
640 mlxsw_sp_port->pvid = vid;
641 return 0;
642
643err_port_allow_untagged_set:
644 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
645 return err;
646}
647
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200648static int
649mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
650{
651 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
652 char sspr_pl[MLXSW_REG_SSPR_LEN];
653
654 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
655 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
656}
657
Ido Schimmeld664b412016-06-09 09:51:40 +0200658static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
659 u8 local_port, u8 *p_module,
660 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200661{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200662 char pmlp_pl[MLXSW_REG_PMLP_LEN];
663 int err;
664
Ido Schimmel558c2d52016-02-26 17:32:29 +0100665 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200666 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
667 if (err)
668 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100669 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
670 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200671 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200672 return 0;
673}
674
Ido Schimmel2e915e02017-06-08 08:47:45 +0200675static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100676 u8 module, u8 width, u8 lane)
677{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200678 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel18f1e702016-02-26 17:32:31 +0100679 char pmlp_pl[MLXSW_REG_PMLP_LEN];
680 int i;
681
Ido Schimmel2e915e02017-06-08 08:47:45 +0200682 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel18f1e702016-02-26 17:32:31 +0100683 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
684 for (i = 0; i < width; i++) {
685 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
686 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
687 }
688
689 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
690}
691
Ido Schimmel2e915e02017-06-08 08:47:45 +0200692static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100693{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200694 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100695 char pmlp_pl[MLXSW_REG_PMLP_LEN];
696
Ido Schimmel2e915e02017-06-08 08:47:45 +0200697 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100698 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
699 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
700}
701
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200702static int mlxsw_sp_port_open(struct net_device *dev)
703{
704 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
705 int err;
706
707 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
708 if (err)
709 return err;
710 netif_start_queue(dev);
711 return 0;
712}
713
714static int mlxsw_sp_port_stop(struct net_device *dev)
715{
716 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
717
718 netif_stop_queue(dev);
719 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
720}
721
722static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
723 struct net_device *dev)
724{
725 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
726 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
727 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
728 const struct mlxsw_tx_info tx_info = {
729 .local_port = mlxsw_sp_port->local_port,
730 .is_emad = false,
731 };
732 u64 len;
733 int err;
734
Jiri Pirko307c2432016-04-08 19:11:22 +0200735 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200736 return NETDEV_TX_BUSY;
737
738 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
739 struct sk_buff *skb_orig = skb;
740
741 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
742 if (!skb) {
743 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
744 dev_kfree_skb_any(skb_orig);
745 return NETDEV_TX_OK;
746 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +0100747 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200748 }
749
750 if (eth_skb_pad(skb)) {
751 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
752 return NETDEV_TX_OK;
753 }
754
755 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +0200756 /* TX header is consumed by HW on the way so we shouldn't count its
757 * bytes as being sent.
758 */
759 len = skb->len - MLXSW_TXHDR_LEN;
760
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200761 /* Due to a race we might fail here because of a full queue. In that
762 * unlikely case we simply drop the packet.
763 */
Jiri Pirko307c2432016-04-08 19:11:22 +0200764 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200765
766 if (!err) {
767 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
768 u64_stats_update_begin(&pcpu_stats->syncp);
769 pcpu_stats->tx_packets++;
770 pcpu_stats->tx_bytes += len;
771 u64_stats_update_end(&pcpu_stats->syncp);
772 } else {
773 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
774 dev_kfree_skb_any(skb);
775 }
776 return NETDEV_TX_OK;
777}
778
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100779static void mlxsw_sp_set_rx_mode(struct net_device *dev)
780{
781}
782
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200783static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
784{
785 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
786 struct sockaddr *addr = p;
787 int err;
788
789 if (!is_valid_ether_addr(addr->sa_data))
790 return -EADDRNOTAVAIL;
791
792 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
793 if (err)
794 return err;
795 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
796 return 0;
797}
798
Ido Schimmel18281f22017-03-24 08:02:51 +0100799static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
800 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200801{
Ido Schimmel18281f22017-03-24 08:02:51 +0100802 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100803}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200804
Ido Schimmelf417f042017-03-24 08:02:50 +0100805#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +0100806
807static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
808 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +0100809{
Ido Schimmel18281f22017-03-24 08:02:51 +0100810 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
811 BITS_PER_BYTE));
812 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
813 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100814}
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200815
Ido Schimmel18281f22017-03-24 08:02:51 +0100816/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +0100817 * Assumes 100m cable and maximum MTU.
818 */
Ido Schimmel18281f22017-03-24 08:02:51 +0100819#define MLXSW_SP_PAUSE_DELAY 58752
820
821static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
822 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +0100823{
824 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +0100825 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +0100826 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +0100827 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200828 else
Ido Schimmelf417f042017-03-24 08:02:50 +0100829 return 0;
830}
831
832static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
833 bool lossy)
834{
835 if (lossy)
836 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
837 else
838 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
839 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200840}
841
842int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200843 u8 *prio_tc, bool pause_en,
844 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +0200845{
846 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200847 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
848 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200849 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200850 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200851
852 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
853 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
854 if (err)
855 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200856
857 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
858 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200859 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +0100860 bool lossy;
861 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200862
863 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
864 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200865 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200866 configure = true;
867 break;
868 }
869 }
870
871 if (!configure)
872 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +0100873
874 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +0100875 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
876 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
877 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +0100878 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200879 }
880
Ido Schimmelff6551e2016-04-06 17:10:03 +0200881 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
882}
883
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200884static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200885 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200886{
887 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
888 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200889 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200890 u8 *prio_tc;
891
892 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200893 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200894
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200895 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200896 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200897}
898
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200899static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
900{
901 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200902 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200903 int err;
904
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200905 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200906 if (err)
907 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200908 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
909 if (err)
910 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200911 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
912 if (err)
913 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200914 dev->mtu = mtu;
915 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200916
917err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +0200918 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
919err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200920 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +0200921 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200922}
923
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +0300924static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200925mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
926 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200927{
928 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
929 struct mlxsw_sp_port_pcpu_stats *p;
930 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
931 u32 tx_dropped = 0;
932 unsigned int start;
933 int i;
934
935 for_each_possible_cpu(i) {
936 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
937 do {
938 start = u64_stats_fetch_begin_irq(&p->syncp);
939 rx_packets = p->rx_packets;
940 rx_bytes = p->rx_bytes;
941 tx_packets = p->tx_packets;
942 tx_bytes = p->tx_bytes;
943 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
944
945 stats->rx_packets += rx_packets;
946 stats->rx_bytes += rx_bytes;
947 stats->tx_packets += tx_packets;
948 stats->tx_bytes += tx_bytes;
949 /* tx_dropped is u32, updated without syncp protection. */
950 tx_dropped += p->tx_dropped;
951 }
952 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200953 return 0;
954}
955
Or Gerlitz3df5b3c2016-11-22 23:09:54 +0200956static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200957{
958 switch (attr_id) {
959 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
960 return true;
961 }
962
963 return false;
964}
965
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +0300966static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
967 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200968{
969 switch (attr_id) {
970 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
971 return mlxsw_sp_port_get_sw_stats64(dev, sp);
972 }
973
974 return -EINVAL;
975}
976
977static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
978 int prio, char *ppcnt_pl)
979{
980 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
981 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
982
983 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
984 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
985}
986
987static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
988 struct rtnl_link_stats64 *stats)
989{
990 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
991 int err;
992
993 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
994 0, ppcnt_pl);
995 if (err)
996 goto out;
997
998 stats->tx_packets =
999 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1000 stats->rx_packets =
1001 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1002 stats->tx_bytes =
1003 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1004 stats->rx_bytes =
1005 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1006 stats->multicast =
1007 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1008
1009 stats->rx_crc_errors =
1010 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1011 stats->rx_frame_errors =
1012 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1013
1014 stats->rx_length_errors = (
1015 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1016 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1017 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1018
1019 stats->rx_errors = (stats->rx_crc_errors +
1020 stats->rx_frame_errors + stats->rx_length_errors);
1021
1022out:
1023 return err;
1024}
1025
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001026static void
1027mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1028 struct mlxsw_sp_port_xstats *xstats)
1029{
1030 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1031 int err, i;
1032
1033 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1034 ppcnt_pl);
1035 if (!err)
1036 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1037
1038 for (i = 0; i < TC_MAX_QUEUE; i++) {
1039 err = mlxsw_sp_port_get_stats_raw(dev,
1040 MLXSW_REG_PPCNT_TC_CONG_TC,
1041 i, ppcnt_pl);
1042 if (!err)
1043 xstats->wred_drop[i] =
1044 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1045
1046 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1047 i, ppcnt_pl);
1048 if (err)
1049 continue;
1050
1051 xstats->backlog[i] =
1052 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1053 xstats->tail_drop[i] =
1054 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1055 }
Nogah Frankel2f880472018-02-28 10:44:59 +01001056
1057 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1058 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
1059 i, ppcnt_pl);
1060 if (err)
1061 continue;
1062
1063 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
1064 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
1065 }
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001066}
1067
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001068static void update_stats_cache(struct work_struct *work)
1069{
1070 struct mlxsw_sp_port *mlxsw_sp_port =
1071 container_of(work, struct mlxsw_sp_port,
Nogah Frankel9deef432017-10-26 10:55:32 +02001072 periodic_hw_stats.update_dw.work);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001073
1074 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1075 goto out;
1076
1077 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
Nogah Frankel9deef432017-10-26 10:55:32 +02001078 &mlxsw_sp_port->periodic_hw_stats.stats);
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001079 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1080 &mlxsw_sp_port->periodic_hw_stats.xstats);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001081
1082out:
Nogah Frankel9deef432017-10-26 10:55:32 +02001083 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001084 MLXSW_HW_STATS_UPDATE_TIME);
1085}
1086
1087/* Return the stats from a cache that is updated periodically,
1088 * as this function might get called in an atomic context.
1089 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001090static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001091mlxsw_sp_port_get_stats64(struct net_device *dev,
1092 struct rtnl_link_stats64 *stats)
1093{
1094 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1095
Nogah Frankel9deef432017-10-26 10:55:32 +02001096 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001097}
1098
Jiri Pirko93cd0812017-04-18 16:55:35 +02001099static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1100 u16 vid_begin, u16 vid_end,
1101 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001102{
1103 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1104 char *spvm_pl;
1105 int err;
1106
1107 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1108 if (!spvm_pl)
1109 return -ENOMEM;
1110
1111 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1112 vid_end, is_member, untagged);
1113 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1114 kfree(spvm_pl);
1115 return err;
1116}
1117
Jiri Pirko93cd0812017-04-18 16:55:35 +02001118int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1119 u16 vid_end, bool is_member, bool untagged)
1120{
1121 u16 vid, vid_e;
1122 int err;
1123
1124 for (vid = vid_begin; vid <= vid_end;
1125 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1126 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1127 vid_end);
1128
1129 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1130 is_member, untagged);
1131 if (err)
1132 return err;
1133 }
1134
1135 return 0;
1136}
1137
Ido Schimmelc57529e2017-05-26 08:37:31 +02001138static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001139{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001140 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001141
Ido Schimmelc57529e2017-05-26 08:37:31 +02001142 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1143 &mlxsw_sp_port->vlans_list, list)
1144 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001145}
1146
Ido Schimmel31a08a52017-05-26 08:37:26 +02001147static struct mlxsw_sp_port_vlan *
1148mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1149{
1150 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001151 bool untagged = vid == 1;
1152 int err;
1153
1154 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1155 if (err)
1156 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001157
1158 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001159 if (!mlxsw_sp_port_vlan) {
1160 err = -ENOMEM;
1161 goto err_port_vlan_alloc;
1162 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02001163
1164 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
Ido Schimmelb3529af2018-02-28 13:12:11 +01001165 mlxsw_sp_port_vlan->ref_count = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02001166 mlxsw_sp_port_vlan->vid = vid;
1167 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1168
1169 return mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001170
1171err_port_vlan_alloc:
1172 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1173 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001174}
1175
1176static void
1177mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1178{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001179 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1180 u16 vid = mlxsw_sp_port_vlan->vid;
Ido Schimmel7cbecf22017-05-26 08:37:28 +02001181
Ido Schimmel31a08a52017-05-26 08:37:26 +02001182 list_del(&mlxsw_sp_port_vlan->list);
1183 kfree(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001184 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1185}
1186
1187struct mlxsw_sp_port_vlan *
1188mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1189{
1190 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1191
1192 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelb3529af2018-02-28 13:12:11 +01001193 if (mlxsw_sp_port_vlan) {
1194 mlxsw_sp_port_vlan->ref_count++;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001195 return mlxsw_sp_port_vlan;
Ido Schimmelb3529af2018-02-28 13:12:11 +01001196 }
Ido Schimmelc57529e2017-05-26 08:37:31 +02001197
1198 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1199}
1200
1201void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1202{
Ido Schimmela1107482017-05-26 08:37:39 +02001203 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1204
Ido Schimmelb3529af2018-02-28 13:12:11 +01001205 if (--mlxsw_sp_port_vlan->ref_count != 0)
1206 return;
1207
Ido Schimmelc57529e2017-05-26 08:37:31 +02001208 if (mlxsw_sp_port_vlan->bridge_port)
1209 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
Ido Schimmela1107482017-05-26 08:37:39 +02001210 else if (fid)
1211 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001212
1213 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001214}
1215
Ido Schimmel05978482016-08-17 16:39:30 +02001216static int mlxsw_sp_port_add_vid(struct net_device *dev,
1217 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001218{
1219 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001220
1221 /* VLAN 0 is added to HW filter when device goes up, but it is
1222 * reserved in our case, so simply return.
1223 */
1224 if (!vid)
1225 return 0;
1226
Ido Schimmelc57529e2017-05-26 08:37:31 +02001227 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001228}
1229
Ido Schimmel32d863f2016-07-02 11:00:10 +02001230static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1231 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001232{
1233 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001234 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001235
1236 /* VLAN 0 is removed from HW filter when device goes down, but
1237 * it is reserved in our case, so simply return.
1238 */
1239 if (!vid)
1240 return 0;
1241
Ido Schimmel31a08a52017-05-26 08:37:26 +02001242 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001243 if (!mlxsw_sp_port_vlan)
Ido Schimmel31a08a52017-05-26 08:37:26 +02001244 return 0;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001245 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001246
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001247 return 0;
1248}
1249
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001250static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1251 size_t len)
1252{
1253 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001254
Jiri Pirkoec932fb2018-05-18 09:29:04 +02001255 return mlxsw_core_port_get_phys_port_name(mlxsw_sp_port->mlxsw_sp->core,
1256 mlxsw_sp_port->local_port,
1257 name, len);
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001258}
1259
Yotam Gigi763b4b72016-07-21 12:03:17 +02001260static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001261mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1262 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001263 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1264
1265 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1266 if (mall_tc_entry->cookie == cookie)
1267 return mall_tc_entry;
1268
1269 return NULL;
1270}
1271
1272static int
1273mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001274 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001275 const struct tc_action *a,
1276 bool ingress)
1277{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001278 enum mlxsw_sp_span_type span_type;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001279 struct net_device *to_dev;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001280
Cong Wang9f8a7392017-12-05 16:17:26 -08001281 to_dev = tcf_mirred_dev(a);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001282 if (!to_dev) {
1283 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1284 return -EINVAL;
1285 }
1286
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001287 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001288 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Petr Machata079c9f32018-02-27 14:53:44 +01001289 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type,
Petr Machata98977082018-02-27 14:53:41 +01001290 true, &mirror->span_id);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001291}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001292
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001293static void
1294mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1295 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1296{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001297 enum mlxsw_sp_span_type span_type;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001298
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001299 span_type = mirror->ingress ?
1300 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Petr Machata98977082018-02-27 14:53:41 +01001301 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +01001302 span_type, true);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001303}
1304
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001305static int
1306mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1307 struct tc_cls_matchall_offload *cls,
1308 const struct tc_action *a,
1309 bool ingress)
1310{
1311 int err;
1312
1313 if (!mlxsw_sp_port->sample)
1314 return -EOPNOTSUPP;
1315 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1316 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1317 return -EEXIST;
1318 }
1319 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1320 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1321 return -EOPNOTSUPP;
1322 }
1323
1324 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1325 tcf_sample_psample_group(a));
1326 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1327 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1328 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1329
1330 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1331 if (err)
1332 goto err_port_sample_set;
1333 return 0;
1334
1335err_port_sample_set:
1336 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1337 return err;
1338}
1339
1340static void
1341mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1342{
1343 if (!mlxsw_sp_port->sample)
1344 return;
1345
1346 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1347 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1348}
1349
Yotam Gigi763b4b72016-07-21 12:03:17 +02001350static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001351 struct tc_cls_matchall_offload *f,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001352 bool ingress)
1353{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001354 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001355 __be16 protocol = f->common.protocol;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001356 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001357 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001358 int err;
1359
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001360 if (!tcf_exts_has_one_action(f->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001361 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001362 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001363 }
1364
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001365 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1366 if (!mall_tc_entry)
1367 return -ENOMEM;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001368 mall_tc_entry->cookie = f->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001369
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001370 tcf_exts_to_list(f->exts, &actions);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001371 a = list_first_entry(&actions, struct tc_action, list);
1372
1373 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1374 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1375
1376 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1377 mirror = &mall_tc_entry->mirror;
1378 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1379 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001380 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1381 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001382 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001383 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001384 } else {
1385 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001386 }
1387
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001388 if (err)
1389 goto err_add_action;
1390
1391 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001392 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001393
1394err_add_action:
1395 kfree(mall_tc_entry);
1396 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001397}
1398
1399static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001400 struct tc_cls_matchall_offload *f)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001401{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001402 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001403
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001404 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001405 f->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001406 if (!mall_tc_entry) {
1407 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1408 return;
1409 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001410 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001411
1412 switch (mall_tc_entry->type) {
1413 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001414 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1415 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001416 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001417 case MLXSW_SP_PORT_MALL_SAMPLE:
1418 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1419 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001420 default:
1421 WARN_ON(1);
1422 }
1423
Yotam Gigi763b4b72016-07-21 12:03:17 +02001424 kfree(mall_tc_entry);
1425}
1426
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001427static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001428 struct tc_cls_matchall_offload *f,
1429 bool ingress)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001430{
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001431 switch (f->command) {
1432 case TC_CLSMATCHALL_REPLACE:
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001433 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001434 ingress);
1435 case TC_CLSMATCHALL_DESTROY:
1436 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1437 return 0;
1438 default:
1439 return -EOPNOTSUPP;
1440 }
1441}
1442
1443static int
Jiri Pirko3aaff322018-01-17 11:46:56 +01001444mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1445 struct tc_cls_flower_offload *f)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001446{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001447 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1448
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001449 switch (f->command) {
1450 case TC_CLSFLOWER_REPLACE:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001451 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001452 case TC_CLSFLOWER_DESTROY:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001453 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001454 return 0;
1455 case TC_CLSFLOWER_STATS:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001456 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001457 default:
1458 return -EOPNOTSUPP;
1459 }
1460}
1461
Jiri Pirko3aaff322018-01-17 11:46:56 +01001462static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1463 void *type_data,
1464 void *cb_priv, bool ingress)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001465{
1466 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1467
1468 switch (type) {
1469 case TC_SETUP_CLSMATCHALL:
Jakub Kicinski15f4edb2018-01-25 14:00:51 -08001470 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1471 type_data))
Jiri Pirko3aaff322018-01-17 11:46:56 +01001472 return -EOPNOTSUPP;
1473
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001474 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1475 ingress);
1476 case TC_SETUP_CLSFLOWER:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001477 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001478 default:
1479 return -EOPNOTSUPP;
1480 }
1481}
1482
Jiri Pirko3aaff322018-01-17 11:46:56 +01001483static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1484 void *type_data,
1485 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001486{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001487 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1488 cb_priv, true);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001489}
1490
Jiri Pirko3aaff322018-01-17 11:46:56 +01001491static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1492 void *type_data,
1493 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001494{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001495 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1496 cb_priv, false);
1497}
1498
1499static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1500 void *type_data, void *cb_priv)
1501{
1502 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1503
1504 switch (type) {
1505 case TC_SETUP_CLSMATCHALL:
1506 return 0;
1507 case TC_SETUP_CLSFLOWER:
1508 if (mlxsw_sp_acl_block_disabled(acl_block))
1509 return -EOPNOTSUPP;
1510
1511 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1512 default:
1513 return -EOPNOTSUPP;
1514 }
1515}
1516
1517static int
1518mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
John Hurley60513bd2018-06-25 14:30:04 -07001519 struct tcf_block *block, bool ingress,
1520 struct netlink_ext_ack *extack)
Jiri Pirko3aaff322018-01-17 11:46:56 +01001521{
1522 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1523 struct mlxsw_sp_acl_block *acl_block;
1524 struct tcf_block_cb *block_cb;
1525 int err;
1526
1527 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1528 mlxsw_sp);
1529 if (!block_cb) {
1530 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1531 if (!acl_block)
1532 return -ENOMEM;
1533 block_cb = __tcf_block_cb_register(block,
1534 mlxsw_sp_setup_tc_block_cb_flower,
John Hurley60513bd2018-06-25 14:30:04 -07001535 mlxsw_sp, acl_block, extack);
Jiri Pirko3aaff322018-01-17 11:46:56 +01001536 if (IS_ERR(block_cb)) {
1537 err = PTR_ERR(block_cb);
1538 goto err_cb_register;
1539 }
1540 } else {
1541 acl_block = tcf_block_cb_priv(block_cb);
1542 }
1543 tcf_block_cb_incref(block_cb);
1544 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1545 mlxsw_sp_port, ingress);
1546 if (err)
1547 goto err_block_bind;
1548
1549 if (ingress)
1550 mlxsw_sp_port->ing_acl_block = acl_block;
1551 else
1552 mlxsw_sp_port->eg_acl_block = acl_block;
1553
1554 return 0;
1555
1556err_block_bind:
1557 if (!tcf_block_cb_decref(block_cb)) {
John Hurley32636742018-06-25 14:30:10 -07001558 __tcf_block_cb_unregister(block, block_cb);
Jiri Pirko3aaff322018-01-17 11:46:56 +01001559err_cb_register:
1560 mlxsw_sp_acl_block_destroy(acl_block);
1561 }
1562 return err;
1563}
1564
1565static void
1566mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1567 struct tcf_block *block, bool ingress)
1568{
1569 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1570 struct mlxsw_sp_acl_block *acl_block;
1571 struct tcf_block_cb *block_cb;
1572 int err;
1573
1574 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1575 mlxsw_sp);
1576 if (!block_cb)
1577 return;
1578
1579 if (ingress)
1580 mlxsw_sp_port->ing_acl_block = NULL;
1581 else
1582 mlxsw_sp_port->eg_acl_block = NULL;
1583
1584 acl_block = tcf_block_cb_priv(block_cb);
1585 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1586 mlxsw_sp_port, ingress);
1587 if (!err && !tcf_block_cb_decref(block_cb)) {
John Hurley32636742018-06-25 14:30:10 -07001588 __tcf_block_cb_unregister(block, block_cb);
Jiri Pirko3aaff322018-01-17 11:46:56 +01001589 mlxsw_sp_acl_block_destroy(acl_block);
1590 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001591}
1592
1593static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1594 struct tc_block_offload *f)
1595{
1596 tc_setup_cb_t *cb;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001597 bool ingress;
1598 int err;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001599
Jiri Pirko3aaff322018-01-17 11:46:56 +01001600 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1601 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1602 ingress = true;
1603 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1604 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1605 ingress = false;
1606 } else {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001607 return -EOPNOTSUPP;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001608 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001609
1610 switch (f->command) {
1611 case TC_BLOCK_BIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001612 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
John Hurley60513bd2018-06-25 14:30:04 -07001613 mlxsw_sp_port, f->extack);
Jiri Pirko3aaff322018-01-17 11:46:56 +01001614 if (err)
1615 return err;
1616 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
John Hurley60513bd2018-06-25 14:30:04 -07001617 f->block, ingress,
1618 f->extack);
Jiri Pirko3aaff322018-01-17 11:46:56 +01001619 if (err) {
1620 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1621 return err;
1622 }
1623 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001624 case TC_BLOCK_UNBIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001625 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1626 f->block, ingress);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001627 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1628 return 0;
1629 default:
1630 return -EOPNOTSUPP;
1631 }
1632}
1633
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001634static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
Jiri Pirkode4784c2017-08-07 10:15:32 +02001635 void *type_data)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001636{
1637 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1638
Jiri Pirko2572ac52017-08-07 10:15:17 +02001639 switch (type) {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001640 case TC_SETUP_BLOCK:
1641 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
Nogah Frankel96f17e02017-11-06 07:23:45 +01001642 case TC_SETUP_QDISC_RED:
1643 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
Nogah Frankel46a36152018-01-14 12:33:16 +01001644 case TC_SETUP_QDISC_PRIO:
1645 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
Jiri Pirko2572ac52017-08-07 10:15:17 +02001646 default:
1647 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001648 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001649}
1650
Jiri Pirko9454d932017-12-06 09:41:12 +01001651
1652static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1653{
1654 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1655
Jiri Pirko3aaff322018-01-17 11:46:56 +01001656 if (!enable) {
1657 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1658 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1659 !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1660 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1661 return -EINVAL;
1662 }
1663 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1664 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1665 } else {
1666 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1667 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
Jiri Pirko9454d932017-12-06 09:41:12 +01001668 }
1669 return 0;
1670}
1671
1672typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1673
1674static int mlxsw_sp_handle_feature(struct net_device *dev,
1675 netdev_features_t wanted_features,
1676 netdev_features_t feature,
1677 mlxsw_sp_feature_handler feature_handler)
1678{
1679 netdev_features_t changes = wanted_features ^ dev->features;
1680 bool enable = !!(wanted_features & feature);
1681 int err;
1682
1683 if (!(changes & feature))
1684 return 0;
1685
1686 err = feature_handler(dev, enable);
1687 if (err) {
1688 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1689 enable ? "Enable" : "Disable", &feature, err);
1690 return err;
1691 }
1692
1693 if (enable)
1694 dev->features |= feature;
1695 else
1696 dev->features &= ~feature;
1697
1698 return 0;
1699}
1700static int mlxsw_sp_set_features(struct net_device *dev,
1701 netdev_features_t features)
1702{
1703 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1704 mlxsw_sp_feature_hw_tc);
1705}
1706
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001707static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1708 .ndo_open = mlxsw_sp_port_open,
1709 .ndo_stop = mlxsw_sp_port_stop,
1710 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001711 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001712 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001713 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1714 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1715 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001716 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1717 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001718 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1719 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001720 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko9454d932017-12-06 09:41:12 +01001721 .ndo_set_features = mlxsw_sp_set_features,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001722};
1723
1724static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1725 struct ethtool_drvinfo *drvinfo)
1726{
1727 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1728 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1729
1730 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1731 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1732 sizeof(drvinfo->version));
1733 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1734 "%d.%d.%d",
1735 mlxsw_sp->bus_info->fw_rev.major,
1736 mlxsw_sp->bus_info->fw_rev.minor,
1737 mlxsw_sp->bus_info->fw_rev.subminor);
1738 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1739 sizeof(drvinfo->bus_info));
1740}
1741
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001742static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1743 struct ethtool_pauseparam *pause)
1744{
1745 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1746
1747 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1748 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1749}
1750
1751static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1752 struct ethtool_pauseparam *pause)
1753{
1754 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1755
1756 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1757 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1758 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1759
1760 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1761 pfcc_pl);
1762}
1763
1764static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1765 struct ethtool_pauseparam *pause)
1766{
1767 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1768 bool pause_en = pause->tx_pause || pause->rx_pause;
1769 int err;
1770
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001771 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1772 netdev_err(dev, "PFC already enabled on port\n");
1773 return -EINVAL;
1774 }
1775
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001776 if (pause->autoneg) {
1777 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1778 return -EINVAL;
1779 }
1780
1781 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1782 if (err) {
1783 netdev_err(dev, "Failed to configure port's headroom\n");
1784 return err;
1785 }
1786
1787 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1788 if (err) {
1789 netdev_err(dev, "Failed to set PAUSE parameters\n");
1790 goto err_port_pause_configure;
1791 }
1792
1793 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1794 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1795
1796 return 0;
1797
1798err_port_pause_configure:
1799 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1800 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1801 return err;
1802}
1803
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001804struct mlxsw_sp_port_hw_stats {
1805 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02001806 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01001807 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001808};
1809
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001810static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001811 {
1812 .str = "a_frames_transmitted_ok",
1813 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1814 },
1815 {
1816 .str = "a_frames_received_ok",
1817 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1818 },
1819 {
1820 .str = "a_frame_check_sequence_errors",
1821 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1822 },
1823 {
1824 .str = "a_alignment_errors",
1825 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1826 },
1827 {
1828 .str = "a_octets_transmitted_ok",
1829 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1830 },
1831 {
1832 .str = "a_octets_received_ok",
1833 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1834 },
1835 {
1836 .str = "a_multicast_frames_xmitted_ok",
1837 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1838 },
1839 {
1840 .str = "a_broadcast_frames_xmitted_ok",
1841 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1842 },
1843 {
1844 .str = "a_multicast_frames_received_ok",
1845 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1846 },
1847 {
1848 .str = "a_broadcast_frames_received_ok",
1849 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1850 },
1851 {
1852 .str = "a_in_range_length_errors",
1853 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1854 },
1855 {
1856 .str = "a_out_of_range_length_field",
1857 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1858 },
1859 {
1860 .str = "a_frame_too_long_errors",
1861 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1862 },
1863 {
1864 .str = "a_symbol_error_during_carrier",
1865 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1866 },
1867 {
1868 .str = "a_mac_control_frames_transmitted",
1869 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1870 },
1871 {
1872 .str = "a_mac_control_frames_received",
1873 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1874 },
1875 {
1876 .str = "a_unsupported_opcodes_received",
1877 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1878 },
1879 {
1880 .str = "a_pause_mac_ctrl_frames_received",
1881 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1882 },
1883 {
1884 .str = "a_pause_mac_ctrl_frames_xmitted",
1885 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1886 },
1887};
1888
1889#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1890
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001891static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1892 {
1893 .str = "rx_octets_prio",
1894 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1895 },
1896 {
1897 .str = "rx_frames_prio",
1898 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1899 },
1900 {
1901 .str = "tx_octets_prio",
1902 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1903 },
1904 {
1905 .str = "tx_frames_prio",
1906 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1907 },
1908 {
1909 .str = "rx_pause_prio",
1910 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1911 },
1912 {
1913 .str = "rx_pause_duration_prio",
1914 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1915 },
1916 {
1917 .str = "tx_pause_prio",
1918 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1919 },
1920 {
1921 .str = "tx_pause_duration_prio",
1922 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1923 },
1924};
1925
1926#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1927
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001928static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1929 {
1930 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01001931 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1932 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001933 },
1934 {
1935 .str = "tc_no_buffer_discard_uc_tc",
1936 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1937 },
1938};
1939
1940#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1941
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001942#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001943 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1944 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001945 IEEE_8021QAZ_MAX_TCS)
1946
1947static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1948{
1949 int i;
1950
1951 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1952 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1953 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1954 *p += ETH_GSTRING_LEN;
1955 }
1956}
1957
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001958static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1959{
1960 int i;
1961
1962 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1963 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1964 mlxsw_sp_port_hw_tc_stats[i].str, tc);
1965 *p += ETH_GSTRING_LEN;
1966 }
1967}
1968
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001969static void mlxsw_sp_port_get_strings(struct net_device *dev,
1970 u32 stringset, u8 *data)
1971{
1972 u8 *p = data;
1973 int i;
1974
1975 switch (stringset) {
1976 case ETH_SS_STATS:
1977 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1978 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1979 ETH_GSTRING_LEN);
1980 p += ETH_GSTRING_LEN;
1981 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001982
1983 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1984 mlxsw_sp_port_get_prio_strings(&p, i);
1985
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001986 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1987 mlxsw_sp_port_get_tc_strings(&p, i);
1988
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001989 break;
1990 }
1991}
1992
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001993static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1994 enum ethtool_phys_id_state state)
1995{
1996 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1997 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1998 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1999 bool active;
2000
2001 switch (state) {
2002 case ETHTOOL_ID_ACTIVE:
2003 active = true;
2004 break;
2005 case ETHTOOL_ID_INACTIVE:
2006 active = false;
2007 break;
2008 default:
2009 return -EOPNOTSUPP;
2010 }
2011
2012 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2013 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2014}
2015
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002016static int
2017mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2018 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2019{
2020 switch (grp) {
2021 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2022 *p_hw_stats = mlxsw_sp_port_hw_stats;
2023 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2024 break;
2025 case MLXSW_REG_PPCNT_PRIO_CNT:
2026 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2027 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2028 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002029 case MLXSW_REG_PPCNT_TC_CNT:
2030 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2031 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2032 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002033 default:
2034 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002035 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002036 }
2037 return 0;
2038}
2039
2040static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2041 enum mlxsw_reg_ppcnt_grp grp, int prio,
2042 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002043{
Ido Schimmel18281f22017-03-24 08:02:51 +01002044 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2045 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002046 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002047 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002048 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002049 int err;
2050
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002051 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2052 if (err)
2053 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002054 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002055 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002056 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002057 if (!hw_stats[i].cells_bytes)
2058 continue;
2059 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2060 data[data_index + i]);
2061 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002062}
2063
2064static void mlxsw_sp_port_get_stats(struct net_device *dev,
2065 struct ethtool_stats *stats, u64 *data)
2066{
2067 int i, data_index = 0;
2068
2069 /* IEEE 802.3 Counters */
2070 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2071 data, data_index);
2072 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2073
2074 /* Per-Priority Counters */
2075 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2076 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2077 data, data_index);
2078 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2079 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002080
2081 /* Per-TC Counters */
2082 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2083 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2084 data, data_index);
2085 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2086 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002087}
2088
2089static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2090{
2091 switch (sset) {
2092 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002093 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002094 default:
2095 return -EOPNOTSUPP;
2096 }
2097}
2098
2099struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002100 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002101 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002102 u32 speed;
2103};
2104
2105static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2106 {
2107 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002108 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2109 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002110 },
2111 {
2112 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2113 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002114 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2115 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002116 },
2117 {
2118 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002119 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2120 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002121 },
2122 {
2123 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2124 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002125 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2126 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002127 },
2128 {
2129 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2130 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2131 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2132 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002133 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2134 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002135 },
2136 {
2137 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002138 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2139 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002140 },
2141 {
2142 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002143 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2144 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002145 },
2146 {
2147 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002148 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2149 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002150 },
2151 {
2152 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002153 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2154 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002155 },
2156 {
2157 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002158 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2159 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002160 },
2161 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002162 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2163 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2164 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002165 },
2166 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002167 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2168 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2169 .speed = SPEED_25000,
2170 },
2171 {
2172 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2173 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2174 .speed = SPEED_25000,
2175 },
2176 {
2177 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2178 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2179 .speed = SPEED_25000,
2180 },
2181 {
2182 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2183 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2184 .speed = SPEED_50000,
2185 },
2186 {
2187 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2188 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2189 .speed = SPEED_50000,
2190 },
2191 {
2192 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2193 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2194 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002195 },
2196 {
2197 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002198 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2199 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002200 },
2201 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002202 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2203 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2204 .speed = SPEED_56000,
2205 },
2206 {
2207 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2208 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2209 .speed = SPEED_56000,
2210 },
2211 {
2212 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2213 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2214 .speed = SPEED_56000,
2215 },
2216 {
2217 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2218 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2219 .speed = SPEED_100000,
2220 },
2221 {
2222 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2223 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2224 .speed = SPEED_100000,
2225 },
2226 {
2227 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2228 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2229 .speed = SPEED_100000,
2230 },
2231 {
2232 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2233 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2234 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002235 },
2236};
2237
2238#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2239
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002240static void
2241mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2242 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002243{
2244 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2245 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2246 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2247 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2248 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2249 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002250 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002251
2252 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2253 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2254 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2255 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2256 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002257 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002258}
2259
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002260static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002261{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002262 int i;
2263
2264 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2265 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002266 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2267 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002268 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002269}
2270
2271static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002272 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002273{
2274 u32 speed = SPEED_UNKNOWN;
2275 u8 duplex = DUPLEX_UNKNOWN;
2276 int i;
2277
2278 if (!carrier_ok)
2279 goto out;
2280
2281 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2282 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2283 speed = mlxsw_sp_port_link_mode[i].speed;
2284 duplex = DUPLEX_FULL;
2285 break;
2286 }
2287 }
2288out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002289 cmd->base.speed = speed;
2290 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002291}
2292
2293static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2294{
2295 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2296 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2297 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2298 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2299 return PORT_FIBRE;
2300
2301 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2302 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2303 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2304 return PORT_DA;
2305
2306 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2307 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2308 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2309 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2310 return PORT_NONE;
2311
2312 return PORT_OTHER;
2313}
2314
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002315static u32
2316mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002317{
2318 u32 ptys_proto = 0;
2319 int i;
2320
2321 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002322 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2323 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002324 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2325 }
2326 return ptys_proto;
2327}
2328
2329static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2330{
2331 u32 ptys_proto = 0;
2332 int i;
2333
2334 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2335 if (speed == mlxsw_sp_port_link_mode[i].speed)
2336 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2337 }
2338 return ptys_proto;
2339}
2340
Ido Schimmel18f1e702016-02-26 17:32:31 +01002341static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2342{
2343 u32 ptys_proto = 0;
2344 int i;
2345
2346 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2347 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2348 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2349 }
2350 return ptys_proto;
2351}
2352
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002353static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2354 struct ethtool_link_ksettings *cmd)
2355{
2356 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2357 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2358 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2359
2360 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2361 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2362}
2363
2364static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2365 struct ethtool_link_ksettings *cmd)
2366{
2367 if (!autoneg)
2368 return;
2369
2370 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2371 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2372}
2373
2374static void
2375mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2376 struct ethtool_link_ksettings *cmd)
2377{
2378 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2379 return;
2380
2381 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2382 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2383}
2384
2385static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2386 struct ethtool_link_ksettings *cmd)
2387{
2388 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2389 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2390 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2391 char ptys_pl[MLXSW_REG_PTYS_LEN];
2392 u8 autoneg_status;
2393 bool autoneg;
2394 int err;
2395
2396 autoneg = mlxsw_sp_port->link.autoneg;
Tal Bar8e1ed732018-03-21 09:34:06 +02002397 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002398 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2399 if (err)
2400 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002401 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2402 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002403
2404 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2405
2406 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2407
2408 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2409 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2410 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2411
2412 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2413 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2414 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2415 cmd);
2416
2417 return 0;
2418}
2419
2420static int
2421mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2422 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002423{
2424 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2425 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2426 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002427 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002428 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002429 int err;
2430
Tal Bar8e1ed732018-03-21 09:34:06 +02002431 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002432 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002433 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002434 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002435 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002436
2437 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2438 eth_proto_new = autoneg ?
2439 mlxsw_sp_to_ptys_advert_link(cmd) :
2440 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002441
2442 eth_proto_new = eth_proto_new & eth_proto_cap;
2443 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002444 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002445 return -EINVAL;
2446 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002447
Elad Raz401c8b42016-10-28 21:35:52 +02002448 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
Tal Bar8e1ed732018-03-21 09:34:06 +02002449 eth_proto_new, autoneg);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002450 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002451 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002452 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002453
Ido Schimmel6277d462016-07-15 11:14:58 +02002454 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002455 return 0;
2456
Ido Schimmel0c83f882016-09-12 13:26:23 +02002457 mlxsw_sp_port->link.autoneg = autoneg;
2458
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002459 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2460 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002461
2462 return 0;
2463}
2464
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002465static int mlxsw_sp_flash_device(struct net_device *dev,
2466 struct ethtool_flash *flash)
2467{
2468 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2469 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2470 const struct firmware *firmware;
2471 int err;
2472
2473 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2474 return -EOPNOTSUPP;
2475
2476 dev_hold(dev);
2477 rtnl_unlock();
2478
2479 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2480 if (err)
2481 goto out;
2482 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2483 release_firmware(firmware);
2484out:
2485 rtnl_lock();
2486 dev_put(dev);
2487 return err;
2488}
2489
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002490#define MLXSW_SP_I2C_ADDR_LOW 0x50
2491#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2492#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002493
2494static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2495 u16 offset, u16 size, void *data,
2496 unsigned int *p_read_size)
2497{
2498 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2499 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2500 char mcia_pl[MLXSW_REG_MCIA_LEN];
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002501 u16 i2c_addr;
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002502 int status;
2503 int err;
2504
2505 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002506
2507 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2508 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2509 /* Cross pages read, read until offset 256 in low page */
2510 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2511
2512 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2513 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2514 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2515 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2516 }
2517
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002518 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002519 0, 0, offset, size, i2c_addr);
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002520
2521 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2522 if (err)
2523 return err;
2524
2525 status = mlxsw_reg_mcia_status_get(mcia_pl);
2526 if (status)
2527 return -EIO;
2528
2529 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2530 memcpy(data, eeprom_tmp, size);
2531 *p_read_size = size;
2532
2533 return 0;
2534}
2535
2536enum mlxsw_sp_eeprom_module_info_rev_id {
2537 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2538 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2539 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2540};
2541
2542enum mlxsw_sp_eeprom_module_info_id {
2543 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2544 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2545 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2546 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2547};
2548
2549enum mlxsw_sp_eeprom_module_info {
2550 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2551 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2552 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2553};
2554
2555static int mlxsw_sp_get_module_info(struct net_device *netdev,
2556 struct ethtool_modinfo *modinfo)
2557{
2558 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2559 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2560 u8 module_rev_id, module_id;
2561 unsigned int read_size;
2562 int err;
2563
2564 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2565 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2566 module_info, &read_size);
2567 if (err)
2568 return err;
2569
2570 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2571 return -EIO;
2572
2573 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2574 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2575
2576 switch (module_id) {
2577 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2578 modinfo->type = ETH_MODULE_SFF_8436;
2579 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2580 break;
2581 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2582 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2583 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2584 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2585 modinfo->type = ETH_MODULE_SFF_8636;
2586 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2587 } else {
2588 modinfo->type = ETH_MODULE_SFF_8436;
2589 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2590 }
2591 break;
2592 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2593 modinfo->type = ETH_MODULE_SFF_8472;
2594 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2595 break;
2596 default:
2597 return -EINVAL;
2598 }
2599
2600 return 0;
2601}
2602
2603static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2604 struct ethtool_eeprom *ee,
2605 u8 *data)
2606{
2607 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2608 int offset = ee->offset;
2609 unsigned int read_size;
2610 int i = 0;
2611 int err;
2612
2613 if (!ee->len)
2614 return -EINVAL;
2615
2616 memset(data, 0, ee->len);
2617
2618 while (i < ee->len) {
2619 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2620 ee->len - i, data + i,
2621 &read_size);
2622 if (err) {
2623 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2624 return err;
2625 }
2626
2627 i += read_size;
2628 offset += read_size;
2629 }
2630
2631 return 0;
2632}
2633
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002634static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2635 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2636 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002637 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2638 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002639 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002640 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002641 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2642 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002643 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2644 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002645 .flash_device = mlxsw_sp_flash_device,
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002646 .get_module_info = mlxsw_sp_get_module_info,
2647 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002648};
2649
Ido Schimmel18f1e702016-02-26 17:32:31 +01002650static int
2651mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2652{
2653 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2654 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2655 char ptys_pl[MLXSW_REG_PTYS_LEN];
2656 u32 eth_proto_admin;
2657
2658 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002659 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
Tal Bar8e1ed732018-03-21 09:34:06 +02002660 eth_proto_admin, mlxsw_sp_port->link.autoneg);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002661 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2662}
2663
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002664int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2665 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2666 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002667{
2668 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2669 char qeec_pl[MLXSW_REG_QEEC_LEN];
2670
2671 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2672 next_index);
2673 mlxsw_reg_qeec_de_set(qeec_pl, true);
2674 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2675 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2676 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2677}
2678
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002679int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2680 enum mlxsw_reg_qeec_hr hr, u8 index,
2681 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002682{
2683 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2684 char qeec_pl[MLXSW_REG_QEEC_LEN];
2685
2686 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2687 next_index);
2688 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2689 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2690 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2691}
2692
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002693int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2694 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002695{
2696 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2697 char qtct_pl[MLXSW_REG_QTCT_LEN];
2698
2699 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2700 tclass);
2701 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2702}
2703
2704static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2705{
2706 int err, i;
2707
2708 /* Setup the elements hierarcy, so that each TC is linked to
2709 * one subgroup, which are all member in the same group.
2710 */
2711 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2712 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2713 0);
2714 if (err)
2715 return err;
2716 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2717 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2718 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2719 0, false, 0);
2720 if (err)
2721 return err;
2722 }
2723 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2724 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2725 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2726 false, 0);
2727 if (err)
2728 return err;
2729 }
2730
2731 /* Make sure the max shaper is disabled in all hierarcies that
2732 * support it.
2733 */
2734 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2735 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2736 MLXSW_REG_QEEC_MAS_DIS);
2737 if (err)
2738 return err;
2739 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2740 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2741 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2742 i, 0,
2743 MLXSW_REG_QEEC_MAS_DIS);
2744 if (err)
2745 return err;
2746 }
2747 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2748 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2749 MLXSW_REG_QEEC_HIERARCY_TC,
2750 i, i,
2751 MLXSW_REG_QEEC_MAS_DIS);
2752 if (err)
2753 return err;
2754 }
2755
2756 /* Map all priorities to traffic class 0. */
2757 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2758 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2759 if (err)
2760 return err;
2761 }
2762
2763 return 0;
2764}
2765
Ido Schimmel5b153852017-06-08 08:47:44 +02002766static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2767 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002768{
Ido Schimmelc57529e2017-05-26 08:37:31 +02002769 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002770 struct mlxsw_sp_port *mlxsw_sp_port;
2771 struct net_device *dev;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002772 int err;
2773
Ido Schimmel5b153852017-06-08 08:47:44 +02002774 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2775 if (err) {
2776 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2777 local_port);
2778 return err;
2779 }
2780
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002781 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
Ido Schimmel5b153852017-06-08 08:47:44 +02002782 if (!dev) {
2783 err = -ENOMEM;
2784 goto err_alloc_etherdev;
2785 }
Jiri Pirkof20a91f2016-10-27 15:13:00 +02002786 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002787 mlxsw_sp_port = netdev_priv(dev);
2788 mlxsw_sp_port->dev = dev;
2789 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2790 mlxsw_sp_port->local_port = local_port;
Ido Schimmelc57529e2017-05-26 08:37:31 +02002791 mlxsw_sp_port->pvid = 1;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002792 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02002793 mlxsw_sp_port->mapping.module = module;
2794 mlxsw_sp_port->mapping.width = width;
2795 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002796 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02002797 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02002798 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002799
2800 mlxsw_sp_port->pcpu_stats =
2801 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2802 if (!mlxsw_sp_port->pcpu_stats) {
2803 err = -ENOMEM;
2804 goto err_alloc_stats;
2805 }
2806
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002807 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2808 GFP_KERNEL);
2809 if (!mlxsw_sp_port->sample) {
2810 err = -ENOMEM;
2811 goto err_alloc_sample;
2812 }
2813
Nogah Frankel9deef432017-10-26 10:55:32 +02002814 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002815 &update_stats_cache);
2816
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002817 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2818 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2819
Ido Schimmel2e915e02017-06-08 08:47:45 +02002820 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
Ido Schimmel5b153852017-06-08 08:47:44 +02002821 if (err) {
2822 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2823 mlxsw_sp_port->local_port);
2824 goto err_port_module_map;
2825 }
2826
Ido Schimmel3247ff22016-09-08 08:16:02 +02002827 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2828 if (err) {
2829 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2830 mlxsw_sp_port->local_port);
2831 goto err_port_swid_set;
2832 }
2833
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002834 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2835 if (err) {
2836 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2837 mlxsw_sp_port->local_port);
2838 goto err_dev_addr_init;
2839 }
2840
2841 netif_carrier_off(dev);
2842
2843 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02002844 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2845 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002846
Jarod Wilsond894be52016-10-20 13:55:16 -04002847 dev->min_mtu = 0;
2848 dev->max_mtu = ETH_MAX_MTU;
2849
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002850 /* Each packet needs to have a Tx header (metadata) on top all other
2851 * headers.
2852 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02002853 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002854
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002855 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2856 if (err) {
2857 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2858 mlxsw_sp_port->local_port);
2859 goto err_port_system_port_mapping_set;
2860 }
2861
Ido Schimmel18f1e702016-02-26 17:32:31 +01002862 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2863 if (err) {
2864 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2865 mlxsw_sp_port->local_port);
2866 goto err_port_speed_by_width_set;
2867 }
2868
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002869 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2870 if (err) {
2871 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2872 mlxsw_sp_port->local_port);
2873 goto err_port_mtu_set;
2874 }
2875
2876 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2877 if (err)
2878 goto err_port_admin_status_set;
2879
2880 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2881 if (err) {
2882 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2883 mlxsw_sp_port->local_port);
2884 goto err_port_buffers_init;
2885 }
2886
Ido Schimmel90183b92016-04-06 17:10:08 +02002887 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2888 if (err) {
2889 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2890 mlxsw_sp_port->local_port);
2891 goto err_port_ets_init;
2892 }
2893
Ido Schimmelf00817d2016-04-06 17:10:09 +02002894 /* ETS and buffers must be initialized before DCB. */
2895 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2896 if (err) {
2897 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2898 mlxsw_sp_port->local_port);
2899 goto err_port_dcb_init;
2900 }
2901
Ido Schimmela1107482017-05-26 08:37:39 +02002902 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
Ido Schimmel45a4a162017-05-16 19:38:35 +02002903 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02002904 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
Ido Schimmel45a4a162017-05-16 19:38:35 +02002905 mlxsw_sp_port->local_port);
Ido Schimmela1107482017-05-26 08:37:39 +02002906 goto err_port_fids_init;
Ido Schimmel45a4a162017-05-16 19:38:35 +02002907 }
2908
Nogah Frankel371b4372018-01-10 14:59:57 +01002909 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
2910 if (err) {
2911 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
2912 mlxsw_sp_port->local_port);
2913 goto err_port_qdiscs_init;
2914 }
2915
Ido Schimmelc57529e2017-05-26 08:37:31 +02002916 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
2917 if (IS_ERR(mlxsw_sp_port_vlan)) {
2918 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
Ido Schimmel05978482016-08-17 16:39:30 +02002919 mlxsw_sp_port->local_port);
Wei Yongjund86fd112017-11-06 11:11:28 +00002920 err = PTR_ERR(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002921 goto err_port_vlan_get;
Ido Schimmel05978482016-08-17 16:39:30 +02002922 }
2923
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002924 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02002925 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002926 err = register_netdev(dev);
2927 if (err) {
2928 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2929 mlxsw_sp_port->local_port);
2930 goto err_register_netdev;
2931 }
2932
Elad Razd808c7e2016-10-28 21:35:57 +02002933 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
Jiri Pirkob9ffcba2018-05-18 09:29:00 +02002934 mlxsw_sp_port, dev, module + 1,
2935 mlxsw_sp_port->split, lane / width);
Nogah Frankel9deef432017-10-26 10:55:32 +02002936 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002937 return 0;
2938
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002939err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02002940 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002941 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002942 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
2943err_port_vlan_get:
Nogah Frankel371b4372018-01-10 14:59:57 +01002944 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
2945err_port_qdiscs_init:
Ido Schimmela1107482017-05-26 08:37:39 +02002946 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
2947err_port_fids_init:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03002948 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002949err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02002950err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002951err_port_buffers_init:
2952err_port_admin_status_set:
2953err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01002954err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002955err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002956err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02002957 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2958err_port_swid_set:
Ido Schimmel2e915e02017-06-08 08:47:45 +02002959 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Ido Schimmel5b153852017-06-08 08:47:44 +02002960err_port_module_map:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002961 kfree(mlxsw_sp_port->sample);
2962err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002963 free_percpu(mlxsw_sp_port->pcpu_stats);
2964err_alloc_stats:
2965 free_netdev(dev);
Ido Schimmel5b153852017-06-08 08:47:44 +02002966err_alloc_etherdev:
Jiri Pirko67963a32016-10-28 21:35:55 +02002967 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2968 return err;
2969}
2970
Ido Schimmel5b153852017-06-08 08:47:44 +02002971static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002972{
2973 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2974
Nogah Frankel9deef432017-10-26 10:55:32 +02002975 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02002976 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002977 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02002978 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002979 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002980 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Nogah Frankel371b4372018-01-10 14:59:57 +01002981 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
Ido Schimmela1107482017-05-26 08:37:39 +02002982 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002983 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01002984 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
Ido Schimmel2e915e02017-06-08 08:47:45 +02002985 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002986 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01002987 free_percpu(mlxsw_sp_port->pcpu_stats);
Ido Schimmel31a08a52017-05-26 08:37:26 +02002988 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002989 free_netdev(mlxsw_sp_port->dev);
Jiri Pirko67963a32016-10-28 21:35:55 +02002990 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2991}
2992
Jiri Pirkof83e2102016-10-28 21:35:49 +02002993static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2994{
2995 return mlxsw_sp->ports[local_port] != NULL;
2996}
2997
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002998static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2999{
3000 int i;
3001
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003002 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003003 if (mlxsw_sp_port_created(mlxsw_sp, i))
3004 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003005 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003006 kfree(mlxsw_sp->ports);
3007}
3008
3009static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3010{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003011 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02003012 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003013 size_t alloc_size;
3014 int i;
3015 int err;
3016
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003017 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003018 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3019 if (!mlxsw_sp->ports)
3020 return -ENOMEM;
3021
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003022 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3023 GFP_KERNEL);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003024 if (!mlxsw_sp->port_to_module) {
3025 err = -ENOMEM;
3026 goto err_port_to_module_alloc;
3027 }
3028
3029 for (i = 1; i < max_ports; i++) {
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003030 /* Mark as invalid */
3031 mlxsw_sp->port_to_module[i] = -1;
3032
Ido Schimmel558c2d52016-02-26 17:32:29 +01003033 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003034 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01003035 if (err)
3036 goto err_port_module_info_get;
3037 if (!width)
3038 continue;
3039 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02003040 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3041 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003042 if (err)
3043 goto err_port_create;
3044 }
3045 return 0;
3046
3047err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01003048err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003049 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003050 if (mlxsw_sp_port_created(mlxsw_sp, i))
3051 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003052 kfree(mlxsw_sp->port_to_module);
3053err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003054 kfree(mlxsw_sp->ports);
3055 return err;
3056}
3057
Ido Schimmel18f1e702016-02-26 17:32:31 +01003058static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3059{
3060 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3061
3062 return local_port - offset;
3063}
3064
Ido Schimmelbe945352016-06-09 09:51:39 +02003065static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3066 u8 module, unsigned int count)
3067{
3068 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3069 int err, i;
3070
3071 for (i = 0; i < count; i++) {
Ido Schimmelbe945352016-06-09 09:51:39 +02003072 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02003073 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02003074 if (err)
3075 goto err_port_create;
3076 }
3077
3078 return 0;
3079
3080err_port_create:
3081 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003082 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3083 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02003084 return err;
3085}
3086
3087static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3088 u8 base_port, unsigned int count)
3089{
3090 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3091 int i;
3092
3093 /* Split by four means we need to re-create two ports, otherwise
3094 * only one.
3095 */
3096 count = count / 2;
3097
3098 for (i = 0; i < count; i++) {
3099 local_port = base_port + i * 2;
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003100 if (mlxsw_sp->port_to_module[local_port] < 0)
3101 continue;
Ido Schimmelbe945352016-06-09 09:51:39 +02003102 module = mlxsw_sp->port_to_module[local_port];
3103
Ido Schimmelbe945352016-06-09 09:51:39 +02003104 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003105 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003106 }
3107}
3108
Jiri Pirkob2f10572016-04-08 19:11:23 +02003109static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
David Ahern3fcc7732018-06-05 08:14:11 -07003110 unsigned int count,
3111 struct netlink_ext_ack *extack)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003112{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003113 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003114 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003115 u8 module, cur_width, base_port;
3116 int i;
3117 int err;
3118
3119 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3120 if (!mlxsw_sp_port) {
3121 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3122 local_port);
David Ahern3fcc7732018-06-05 08:14:11 -07003123 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003124 return -EINVAL;
3125 }
3126
Ido Schimmeld664b412016-06-09 09:51:40 +02003127 module = mlxsw_sp_port->mapping.module;
3128 cur_width = mlxsw_sp_port->mapping.width;
3129
Ido Schimmel18f1e702016-02-26 17:32:31 +01003130 if (count != 2 && count != 4) {
3131 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
David Ahern3fcc7732018-06-05 08:14:11 -07003132 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003133 return -EINVAL;
3134 }
3135
Ido Schimmel18f1e702016-02-26 17:32:31 +01003136 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3137 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
David Ahern3fcc7732018-06-05 08:14:11 -07003138 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003139 return -EINVAL;
3140 }
3141
3142 /* Make sure we have enough slave (even) ports for the split. */
3143 if (count == 2) {
3144 base_port = local_port;
3145 if (mlxsw_sp->ports[base_port + 1]) {
3146 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
David Ahern3fcc7732018-06-05 08:14:11 -07003147 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003148 return -EINVAL;
3149 }
3150 } else {
3151 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3152 if (mlxsw_sp->ports[base_port + 1] ||
3153 mlxsw_sp->ports[base_port + 3]) {
3154 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
David Ahern3fcc7732018-06-05 08:14:11 -07003155 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003156 return -EINVAL;
3157 }
3158 }
3159
3160 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003161 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3162 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003163
Ido Schimmelbe945352016-06-09 09:51:39 +02003164 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3165 if (err) {
3166 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3167 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003168 }
3169
3170 return 0;
3171
Ido Schimmelbe945352016-06-09 09:51:39 +02003172err_port_split_create:
3173 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003174 return err;
3175}
3176
David Ahern3fcc7732018-06-05 08:14:11 -07003177static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port,
3178 struct netlink_ext_ack *extack)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003179{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003180 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003181 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003182 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003183 unsigned int count;
3184 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003185
3186 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3187 if (!mlxsw_sp_port) {
3188 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3189 local_port);
David Ahern3fcc7732018-06-05 08:14:11 -07003190 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003191 return -EINVAL;
3192 }
3193
3194 if (!mlxsw_sp_port->split) {
David Ahern3fcc7732018-06-05 08:14:11 -07003195 netdev_err(mlxsw_sp_port->dev, "Port was not split\n");
3196 NL_SET_ERR_MSG_MOD(extack, "Port was not split");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003197 return -EINVAL;
3198 }
3199
Ido Schimmeld664b412016-06-09 09:51:40 +02003200 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003201 count = cur_width == 1 ? 4 : 2;
3202
3203 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3204
3205 /* Determine which ports to remove. */
3206 if (count == 2 && local_port >= base_port + 2)
3207 base_port = base_port + 2;
3208
3209 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003210 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3211 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003212
Ido Schimmelbe945352016-06-09 09:51:39 +02003213 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003214
3215 return 0;
3216}
3217
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003218static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3219 char *pude_pl, void *priv)
3220{
3221 struct mlxsw_sp *mlxsw_sp = priv;
3222 struct mlxsw_sp_port *mlxsw_sp_port;
3223 enum mlxsw_reg_pude_oper_status status;
3224 u8 local_port;
3225
3226 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3227 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003228 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003229 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003230
3231 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3232 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3233 netdev_info(mlxsw_sp_port->dev, "link up\n");
3234 netif_carrier_on(mlxsw_sp_port->dev);
3235 } else {
3236 netdev_info(mlxsw_sp_port->dev, "link down\n");
3237 netif_carrier_off(mlxsw_sp_port->dev);
3238 }
3239}
3240
Nogah Frankel14eeda92016-11-25 10:33:32 +01003241static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3242 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003243{
3244 struct mlxsw_sp *mlxsw_sp = priv;
3245 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3246 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3247
3248 if (unlikely(!mlxsw_sp_port)) {
3249 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3250 local_port);
3251 return;
3252 }
3253
3254 skb->dev = mlxsw_sp_port->dev;
3255
3256 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3257 u64_stats_update_begin(&pcpu_stats->syncp);
3258 pcpu_stats->rx_packets++;
3259 pcpu_stats->rx_bytes += skb->len;
3260 u64_stats_update_end(&pcpu_stats->syncp);
3261
3262 skb->protocol = eth_type_trans(skb, skb->dev);
3263 netif_receive_skb(skb);
3264}
3265
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003266static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3267 void *priv)
3268{
3269 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003270 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003271}
3272
Yotam Gigia0040c82017-10-03 09:58:10 +02003273static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3274 u8 local_port, void *priv)
3275{
3276 skb->offload_mr_fwd_mark = 1;
3277 skb->offload_fwd_mark = 1;
3278 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3279}
3280
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003281static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3282 void *priv)
3283{
3284 struct mlxsw_sp *mlxsw_sp = priv;
3285 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3286 struct psample_group *psample_group;
3287 u32 size;
3288
3289 if (unlikely(!mlxsw_sp_port)) {
3290 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3291 local_port);
3292 goto out;
3293 }
3294 if (unlikely(!mlxsw_sp_port->sample)) {
3295 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3296 local_port);
3297 goto out;
3298 }
3299
3300 size = mlxsw_sp_port->sample->truncate ?
3301 mlxsw_sp_port->sample->trunc_size : skb->len;
3302
3303 rcu_read_lock();
3304 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3305 if (!psample_group)
3306 goto out_unlock;
3307 psample_sample_packet(psample_group, skb, size,
3308 mlxsw_sp_port->dev->ifindex, 0,
3309 mlxsw_sp_port->sample->rate);
3310out_unlock:
3311 rcu_read_unlock();
3312out:
3313 consume_skb(skb);
3314}
3315
Nogah Frankel117b0da2016-11-25 10:33:44 +01003316#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003317 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003318 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003319
Nogah Frankel117b0da2016-11-25 10:33:44 +01003320#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003321 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003322 _is_ctrl, SP_##_trap_group, DISCARD)
3323
Yotam Gigia0040c82017-10-03 09:58:10 +02003324#define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3325 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3326 _is_ctrl, SP_##_trap_group, DISCARD)
3327
Nogah Frankel117b0da2016-11-25 10:33:44 +01003328#define MLXSW_SP_EVENTL(_func, _trap_id) \
3329 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003330
Nogah Frankel45449132016-11-25 10:33:35 +01003331static const struct mlxsw_listener mlxsw_sp_listener[] = {
3332 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003333 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003334 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003335 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3336 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3337 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3338 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3339 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3340 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3341 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3342 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3343 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3344 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3345 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003346 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003347 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3348 false),
3349 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3350 false),
3351 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3352 false),
3353 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3354 false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003355 /* L3 traps */
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003356 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3357 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3358 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003359 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003360 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3361 false),
3362 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3363 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3364 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3365 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3366 false),
3367 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3368 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3369 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003370 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003371 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3372 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3373 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3374 false),
3375 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3376 false),
3377 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3378 false),
3379 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3380 false),
3381 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3382 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3383 false),
3384 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3385 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
Ido Schimmel7607dd32017-07-17 14:15:30 +02003386 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003387 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
Petr Machata86484de2017-09-02 23:49:27 +02003388 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003389 /* PKT Sample trap */
3390 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
Jiri Pirko0db7b382017-06-06 14:12:05 +02003391 false, SP_IP2ME, DISCARD),
3392 /* ACL trap */
3393 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
Yotam Gigib48cfc82017-09-19 10:00:20 +02003394 /* Multicast Router Traps */
3395 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
Yuval Mintz6a170d32018-03-26 15:01:45 +03003396 MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false),
Yotam Gigib48cfc82017-09-19 10:00:20 +02003397 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3398 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
Yotam Gigia0040c82017-10-03 09:58:10 +02003399 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003400};
3401
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003402static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3403{
3404 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3405 enum mlxsw_reg_qpcr_ir_units ir_units;
3406 int max_cpu_policers;
3407 bool is_bytes;
3408 u8 burst_size;
3409 u32 rate;
3410 int i, err;
3411
3412 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3413 return -EIO;
3414
3415 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3416
3417 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3418 for (i = 0; i < max_cpu_policers; i++) {
3419 is_bytes = false;
3420 switch (i) {
3421 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3422 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3423 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3424 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003425 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3426 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003427 rate = 128;
3428 burst_size = 7;
3429 break;
3430 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003431 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003432 rate = 16 * 1024;
3433 burst_size = 10;
3434 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003435 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003436 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3437 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003438 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003439 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3440 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003441 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003442 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003443 rate = 1024;
3444 burst_size = 7;
3445 break;
3446 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3447 is_bytes = true;
3448 rate = 4 * 1024;
3449 burst_size = 4;
3450 break;
3451 default:
3452 continue;
3453 }
3454
3455 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3456 burst_size);
3457 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3458 if (err)
3459 return err;
3460 }
3461
3462 return 0;
3463}
3464
Nogah Frankel579c82e2016-11-25 10:33:42 +01003465static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003466{
3467 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003468 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003469 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003470 int max_trap_groups;
3471 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003472 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003473 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003474
3475 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3476 return -EIO;
3477
3478 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003479 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003480
3481 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003482 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003483 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003484 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3485 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3486 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3487 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003488 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003489 priority = 5;
3490 tc = 5;
3491 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003492 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003493 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3494 priority = 4;
3495 tc = 4;
3496 break;
3497 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3498 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003499 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003500 priority = 3;
3501 tc = 3;
3502 break;
3503 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003504 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003505 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003506 priority = 2;
3507 tc = 2;
3508 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003509 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003510 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3511 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003512 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003513 priority = 1;
3514 tc = 1;
3515 break;
3516 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003517 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3518 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003519 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003520 break;
3521 default:
3522 continue;
3523 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003524
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003525 if (max_cpu_policers <= policer_id &&
3526 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3527 return -EIO;
3528
3529 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003530 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3531 if (err)
3532 return err;
3533 }
3534
3535 return 0;
3536}
3537
3538static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3539{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003540 int i;
3541 int err;
3542
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003543 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3544 if (err)
3545 return err;
3546
Nogah Frankel579c82e2016-11-25 10:33:42 +01003547 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003548 if (err)
3549 return err;
3550
Nogah Frankel45449132016-11-25 10:33:35 +01003551 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003552 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003553 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003554 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003555 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003556 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003557
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003558 }
3559 return 0;
3560
Nogah Frankel45449132016-11-25 10:33:35 +01003561err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003562 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003563 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003564 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003565 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003566 }
3567 return err;
3568}
3569
3570static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3571{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003572 int i;
3573
Nogah Frankel45449132016-11-25 10:33:35 +01003574 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003575 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003576 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003577 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003578 }
3579}
3580
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003581static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3582{
3583 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003584 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003585
3586 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3587 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3588 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3589 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3590 MLXSW_REG_SLCR_LAG_HASH_SIP |
3591 MLXSW_REG_SLCR_LAG_HASH_DIP |
3592 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3593 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3594 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003595 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3596 if (err)
3597 return err;
3598
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003599 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3600 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003601 return -EIO;
3602
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003603 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003604 sizeof(struct mlxsw_sp_upper),
3605 GFP_KERNEL);
3606 if (!mlxsw_sp->lags)
3607 return -ENOMEM;
3608
3609 return 0;
3610}
3611
3612static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3613{
3614 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003615}
3616
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003617static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3618{
3619 char htgt_pl[MLXSW_REG_HTGT_LEN];
3620
Nogah Frankel579c82e2016-11-25 10:33:42 +01003621 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3622 MLXSW_REG_HTGT_INVALID_POLICER,
3623 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3624 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003625 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3626}
3627
Petr Machatac30f5d02017-10-16 16:26:35 +02003628static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3629 unsigned long event, void *ptr);
3630
Jiri Pirkob2f10572016-04-08 19:11:23 +02003631static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003632 const struct mlxsw_bus_info *mlxsw_bus_info)
3633{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003634 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003635 int err;
3636
Jiri Pirkoabfd6182018-07-08 23:51:26 +03003637 mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev;
3638 mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME;
Jiri Pirkoebcff742018-07-08 23:51:16 +03003639 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
Jiri Pirko9dbab6f2018-07-08 10:00:19 +03003640 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
Jiri Pirkoc17d2082018-07-08 23:51:22 +03003641 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
Jiri Pirko8fae4392018-07-08 23:51:19 +03003642 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
Jiri Pirko64eccd02018-07-08 23:51:20 +03003643 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
Jiri Pirko9dbab6f2018-07-08 10:00:19 +03003644
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003645 mlxsw_sp->core = mlxsw_core;
3646 mlxsw_sp->bus_info = mlxsw_bus_info;
3647
Yotam Gigi6b742192017-05-23 21:56:29 +02003648 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3649 if (err) {
3650 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3651 return err;
3652 }
3653
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003654 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3655 if (err) {
3656 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3657 return err;
3658 }
3659
Ido Schimmela875a2e2017-10-22 23:11:44 +02003660 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3661 if (err) {
3662 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3663 return err;
3664 }
3665
Ido Schimmela1107482017-05-26 08:37:39 +02003666 err = mlxsw_sp_fids_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003667 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003668 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
Ido Schimmela875a2e2017-10-22 23:11:44 +02003669 goto err_fids_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003670 }
3671
Ido Schimmela1107482017-05-26 08:37:39 +02003672 err = mlxsw_sp_traps_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003673 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003674 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3675 goto err_traps_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003676 }
3677
3678 err = mlxsw_sp_buffers_init(mlxsw_sp);
3679 if (err) {
3680 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3681 goto err_buffers_init;
3682 }
3683
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003684 err = mlxsw_sp_lag_init(mlxsw_sp);
3685 if (err) {
3686 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3687 goto err_lag_init;
3688 }
3689
Petr Machatacda880de2018-04-29 10:56:11 +03003690 /* Initialize SPAN before router and switchdev, so that those components
3691 * can call mlxsw_sp_span_respin().
3692 */
3693 err = mlxsw_sp_span_init(mlxsw_sp);
3694 if (err) {
3695 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3696 goto err_span_init;
3697 }
3698
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003699 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3700 if (err) {
3701 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3702 goto err_switchdev_init;
3703 }
3704
Yotam Gigie2b2d352017-09-19 10:00:08 +02003705 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3706 if (err) {
3707 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3708 goto err_counter_pool_init;
3709 }
3710
Yotam Gigid3b939b2017-09-19 10:00:09 +02003711 err = mlxsw_sp_afa_init(mlxsw_sp);
3712 if (err) {
3713 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3714 goto err_afa_init;
3715 }
3716
Ido Schimmel464dce12016-07-02 11:00:15 +02003717 err = mlxsw_sp_router_init(mlxsw_sp);
3718 if (err) {
3719 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3720 goto err_router_init;
3721 }
3722
Petr Machata803335a2018-02-27 14:53:46 +01003723 /* Initialize netdevice notifier after router and SPAN is initialized,
3724 * so that the event handler can use router structures and call SPAN
3725 * respin.
Petr Machatac30f5d02017-10-16 16:26:35 +02003726 */
3727 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3728 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3729 if (err) {
3730 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3731 goto err_netdev_notifier;
3732 }
3733
Jiri Pirko22a67762017-02-03 10:29:07 +01003734 err = mlxsw_sp_acl_init(mlxsw_sp);
3735 if (err) {
3736 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3737 goto err_acl_init;
3738 }
3739
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003740 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3741 if (err) {
3742 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3743 goto err_dpipe_init;
3744 }
3745
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003746 err = mlxsw_sp_ports_create(mlxsw_sp);
3747 if (err) {
3748 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3749 goto err_ports_create;
3750 }
3751
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003752 return 0;
3753
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003754err_ports_create:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003755 mlxsw_sp_dpipe_fini(mlxsw_sp);
3756err_dpipe_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01003757 mlxsw_sp_acl_fini(mlxsw_sp);
3758err_acl_init:
Petr Machatac30f5d02017-10-16 16:26:35 +02003759 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3760err_netdev_notifier:
Ido Schimmel464dce12016-07-02 11:00:15 +02003761 mlxsw_sp_router_fini(mlxsw_sp);
3762err_router_init:
Yotam Gigid3b939b2017-09-19 10:00:09 +02003763 mlxsw_sp_afa_fini(mlxsw_sp);
3764err_afa_init:
Yotam Gigie2b2d352017-09-19 10:00:08 +02003765 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3766err_counter_pool_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003767 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003768err_switchdev_init:
Petr Machatacda880de2018-04-29 10:56:11 +03003769 mlxsw_sp_span_fini(mlxsw_sp);
3770err_span_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003771 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003772err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02003773 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003774err_buffers_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003775 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003776err_traps_init:
3777 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003778err_fids_init:
3779 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003780 return err;
3781}
3782
Jiri Pirkob2f10572016-04-08 19:11:23 +02003783static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003784{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003785 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003786
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003787 mlxsw_sp_ports_remove(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003788 mlxsw_sp_dpipe_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01003789 mlxsw_sp_acl_fini(mlxsw_sp);
Petr Machatac30f5d02017-10-16 16:26:35 +02003790 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
Ido Schimmel464dce12016-07-02 11:00:15 +02003791 mlxsw_sp_router_fini(mlxsw_sp);
Yotam Gigid3b939b2017-09-19 10:00:09 +02003792 mlxsw_sp_afa_fini(mlxsw_sp);
Yotam Gigie2b2d352017-09-19 10:00:08 +02003793 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003794 mlxsw_sp_switchdev_fini(mlxsw_sp);
Petr Machatacda880de2018-04-29 10:56:11 +03003795 mlxsw_sp_span_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003796 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02003797 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003798 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003799 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003800 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003801}
3802
Bhumika Goyal159fe882017-08-11 19:10:42 +05303803static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003804 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01003805 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003806 .used_flood_tables = 1,
3807 .used_flood_mode = 1,
3808 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003809 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003810 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003811 .max_fid_flood_tables = 3,
Ido Schimmela1107482017-05-26 08:37:39 +02003812 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003813 .used_max_ib_mc = 1,
3814 .max_ib_mc = 0,
3815 .used_max_pkey = 1,
3816 .max_pkey = 0,
Jiri Pirko110d2d22018-04-01 17:34:56 +03003817 .used_kvd_sizes = 1,
Ido Schimmelf11fbaf2017-10-22 23:11:49 +02003818 .kvd_hash_single_parts = 59,
3819 .kvd_hash_double_parts = 41,
Jiri Pirkoc6022422016-07-05 11:27:46 +02003820 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003821 .swid_config = {
3822 {
3823 .used_type = 1,
3824 .type = MLXSW_PORT_SWID_TYPE_ETH,
3825 }
3826 },
3827};
3828
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003829static void
Jiri Pirko77d27092018-02-28 13:12:09 +01003830mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
3831 struct devlink_resource_size_params *kvd_size_params,
3832 struct devlink_resource_size_params *linear_size_params,
3833 struct devlink_resource_size_params *hash_double_size_params,
3834 struct devlink_resource_size_params *hash_single_size_params)
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003835{
3836 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3837 KVD_SINGLE_MIN_SIZE);
3838 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3839 KVD_DOUBLE_MIN_SIZE);
3840 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3841 u32 linear_size_min = 0;
3842
Jiri Pirko77d27092018-02-28 13:12:09 +01003843 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
3844 MLXSW_SP_KVD_GRANULARITY,
3845 DEVLINK_RESOURCE_UNIT_ENTRY);
3846 devlink_resource_size_params_init(linear_size_params, linear_size_min,
3847 kvd_size - single_size_min -
3848 double_size_min,
3849 MLXSW_SP_KVD_GRANULARITY,
3850 DEVLINK_RESOURCE_UNIT_ENTRY);
3851 devlink_resource_size_params_init(hash_double_size_params,
3852 double_size_min,
3853 kvd_size - single_size_min -
3854 linear_size_min,
3855 MLXSW_SP_KVD_GRANULARITY,
3856 DEVLINK_RESOURCE_UNIT_ENTRY);
3857 devlink_resource_size_params_init(hash_single_size_params,
3858 single_size_min,
3859 kvd_size - double_size_min -
3860 linear_size_min,
3861 MLXSW_SP_KVD_GRANULARITY,
3862 DEVLINK_RESOURCE_UNIT_ENTRY);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003863}
3864
3865static int mlxsw_sp_resources_register(struct mlxsw_core *mlxsw_core)
3866{
3867 struct devlink *devlink = priv_to_devlink(mlxsw_core);
Jiri Pirko77d27092018-02-28 13:12:09 +01003868 struct devlink_resource_size_params hash_single_size_params;
3869 struct devlink_resource_size_params hash_double_size_params;
3870 struct devlink_resource_size_params linear_size_params;
3871 struct devlink_resource_size_params kvd_size_params;
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003872 u32 kvd_size, single_size, double_size, linear_size;
3873 const struct mlxsw_config_profile *profile;
3874 int err;
3875
3876 profile = &mlxsw_sp_config_profile;
3877 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
3878 return -EIO;
3879
Jiri Pirko77d27092018-02-28 13:12:09 +01003880 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
3881 &linear_size_params,
3882 &hash_double_size_params,
3883 &hash_single_size_params);
3884
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003885 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3886 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
David Ahern14530742018-03-20 19:31:14 -07003887 kvd_size, MLXSW_SP_RESOURCE_KVD,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003888 DEVLINK_RESOURCE_ID_PARENT_TOP,
Jiri Pirkofc56be42018-04-05 22:13:21 +02003889 &kvd_size_params);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003890 if (err)
3891 return err;
3892
3893 linear_size = profile->kvd_linear_size;
3894 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
David Ahern14530742018-03-20 19:31:14 -07003895 linear_size,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003896 MLXSW_SP_RESOURCE_KVD_LINEAR,
3897 MLXSW_SP_RESOURCE_KVD,
Jiri Pirkofc56be42018-04-05 22:13:21 +02003898 &linear_size_params);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003899 if (err)
3900 return err;
3901
Jiri Pirkoebcff742018-07-08 23:51:16 +03003902 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
Arkadi Sharshevsky51d3c082018-02-20 08:44:22 +01003903 if (err)
3904 return err;
3905
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003906 double_size = kvd_size - linear_size;
3907 double_size *= profile->kvd_hash_double_parts;
3908 double_size /= profile->kvd_hash_double_parts +
3909 profile->kvd_hash_single_parts;
Jiri Pirko72779c92018-04-01 17:34:54 +03003910 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003911 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
David Ahern14530742018-03-20 19:31:14 -07003912 double_size,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003913 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3914 MLXSW_SP_RESOURCE_KVD,
Jiri Pirkofc56be42018-04-05 22:13:21 +02003915 &hash_double_size_params);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003916 if (err)
3917 return err;
3918
3919 single_size = kvd_size - double_size - linear_size;
3920 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
David Ahern14530742018-03-20 19:31:14 -07003921 single_size,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003922 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3923 MLXSW_SP_RESOURCE_KVD,
Jiri Pirkofc56be42018-04-05 22:13:21 +02003924 &hash_single_size_params);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01003925 if (err)
3926 return err;
3927
3928 return 0;
3929}
3930
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01003931static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
3932 const struct mlxsw_config_profile *profile,
3933 u64 *p_single_size, u64 *p_double_size,
3934 u64 *p_linear_size)
3935{
3936 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3937 u32 double_size;
3938 int err;
3939
3940 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
Jiri Pirko110d2d22018-04-01 17:34:56 +03003941 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01003942 return -EIO;
3943
3944 /* The hash part is what left of the kvd without the
3945 * linear part. It is split to the single size and
3946 * double size by the parts ratio from the profile.
3947 * Both sizes must be a multiplications of the
3948 * granularity from the profile. In case the user
3949 * provided the sizes they are obtained via devlink.
3950 */
3951 err = devlink_resource_size_get(devlink,
3952 MLXSW_SP_RESOURCE_KVD_LINEAR,
3953 p_linear_size);
3954 if (err)
3955 *p_linear_size = profile->kvd_linear_size;
3956
3957 err = devlink_resource_size_get(devlink,
3958 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3959 p_double_size);
3960 if (err) {
3961 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3962 *p_linear_size;
3963 double_size *= profile->kvd_hash_double_parts;
3964 double_size /= profile->kvd_hash_double_parts +
3965 profile->kvd_hash_single_parts;
3966 *p_double_size = rounddown(double_size,
Jiri Pirko72779c92018-04-01 17:34:54 +03003967 MLXSW_SP_KVD_GRANULARITY);
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01003968 }
3969
3970 err = devlink_resource_size_get(devlink,
3971 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3972 p_single_size);
3973 if (err)
3974 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3975 *p_double_size - *p_linear_size;
3976
3977 /* Check results are legal. */
3978 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3979 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
3980 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
3981 return -EIO;
3982
3983 return 0;
3984}
3985
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003986static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02003987 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003988 .priv_size = sizeof(struct mlxsw_sp),
3989 .init = mlxsw_sp_init,
3990 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003991 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003992 .port_split = mlxsw_sp_port_split,
3993 .port_unsplit = mlxsw_sp_port_unsplit,
3994 .sb_pool_get = mlxsw_sp_sb_pool_get,
3995 .sb_pool_set = mlxsw_sp_sb_pool_set,
3996 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3997 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3998 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3999 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4000 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4001 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4002 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4003 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4004 .txhdr_construct = mlxsw_sp_txhdr_construct,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004005 .resources_register = mlxsw_sp_resources_register,
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01004006 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02004007 .txhdr_len = MLXSW_TXHDR_LEN,
4008 .profile = &mlxsw_sp_config_profile,
Jiri Pirkoad3f20b2018-04-01 17:34:57 +03004009 .res_query_enabled = true,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004010};
4011
Jiri Pirko22a67762017-02-03 10:29:07 +01004012bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004013{
4014 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4015}
4016
Jiri Pirko1182e532017-03-06 21:25:20 +01004017static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07004018{
Jiri Pirko1182e532017-03-06 21:25:20 +01004019 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07004020 int ret = 0;
4021
4022 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01004023 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07004024 ret = 1;
4025 }
4026
4027 return ret;
4028}
4029
Ido Schimmelc57529e2017-05-26 08:37:31 +02004030struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004031{
Jiri Pirko1182e532017-03-06 21:25:20 +01004032 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004033
4034 if (mlxsw_sp_port_dev_check(dev))
4035 return netdev_priv(dev);
4036
Jiri Pirko1182e532017-03-06 21:25:20 +01004037 mlxsw_sp_port = NULL;
4038 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004039
Jiri Pirko1182e532017-03-06 21:25:20 +01004040 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004041}
4042
Ido Schimmel4724ba562017-03-10 08:53:39 +01004043struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004044{
4045 struct mlxsw_sp_port *mlxsw_sp_port;
4046
4047 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4048 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4049}
4050
Arkadi Sharshevskyaf0613782017-06-08 08:44:20 +02004051struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004052{
Jiri Pirko1182e532017-03-06 21:25:20 +01004053 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004054
4055 if (mlxsw_sp_port_dev_check(dev))
4056 return netdev_priv(dev);
4057
Jiri Pirko1182e532017-03-06 21:25:20 +01004058 mlxsw_sp_port = NULL;
4059 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4060 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004061
Jiri Pirko1182e532017-03-06 21:25:20 +01004062 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004063}
4064
4065struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4066{
4067 struct mlxsw_sp_port *mlxsw_sp_port;
4068
4069 rcu_read_lock();
4070 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4071 if (mlxsw_sp_port)
4072 dev_hold(mlxsw_sp_port->dev);
4073 rcu_read_unlock();
4074 return mlxsw_sp_port;
4075}
4076
4077void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4078{
4079 dev_put(mlxsw_sp_port->dev);
4080}
4081
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004082static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004083{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004084 char sldr_pl[MLXSW_REG_SLDR_LEN];
4085
4086 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4087 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4088}
4089
4090static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4091{
4092 char sldr_pl[MLXSW_REG_SLDR_LEN];
4093
4094 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4095 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4096}
4097
4098static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4099 u16 lag_id, u8 port_index)
4100{
4101 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4102 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4103
4104 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4105 lag_id, port_index);
4106 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4107}
4108
4109static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4110 u16 lag_id)
4111{
4112 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4113 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4114
4115 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4116 lag_id);
4117 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4118}
4119
4120static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4121 u16 lag_id)
4122{
4123 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4124 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4125
4126 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4127 lag_id);
4128 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4129}
4130
4131static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4132 u16 lag_id)
4133{
4134 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4135 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4136
4137 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4138 lag_id);
4139 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4140}
4141
4142static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4143 struct net_device *lag_dev,
4144 u16 *p_lag_id)
4145{
4146 struct mlxsw_sp_upper *lag;
4147 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004148 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004149 int i;
4150
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004151 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4152 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004153 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4154 if (lag->ref_count) {
4155 if (lag->dev == lag_dev) {
4156 *p_lag_id = i;
4157 return 0;
4158 }
4159 } else if (free_lag_id < 0) {
4160 free_lag_id = i;
4161 }
4162 }
4163 if (free_lag_id < 0)
4164 return -EBUSY;
4165 *p_lag_id = free_lag_id;
4166 return 0;
4167}
4168
4169static bool
4170mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4171 struct net_device *lag_dev,
David Aherne58376e2017-10-04 17:48:51 -07004172 struct netdev_lag_upper_info *lag_upper_info,
4173 struct netlink_ext_ack *extack)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004174{
4175 u16 lag_id;
4176
David Aherne58376e2017-10-04 17:48:51 -07004177 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004178 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004179 return false;
David Aherne58376e2017-10-04 17:48:51 -07004180 }
4181 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004182 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004183 return false;
David Aherne58376e2017-10-04 17:48:51 -07004184 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004185 return true;
4186}
4187
4188static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4189 u16 lag_id, u8 *p_port_index)
4190{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004191 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004192 int i;
4193
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004194 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4195 MAX_LAG_MEMBERS);
4196 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004197 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4198 *p_port_index = i;
4199 return 0;
4200 }
4201 }
4202 return -EBUSY;
4203}
4204
4205static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4206 struct net_device *lag_dev)
4207{
4208 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004209 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004210 struct mlxsw_sp_upper *lag;
4211 u16 lag_id;
4212 u8 port_index;
4213 int err;
4214
4215 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4216 if (err)
4217 return err;
4218 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4219 if (!lag->ref_count) {
4220 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4221 if (err)
4222 return err;
4223 lag->dev = lag_dev;
4224 }
4225
4226 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4227 if (err)
4228 return err;
4229 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4230 if (err)
4231 goto err_col_port_add;
4232 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4233 if (err)
4234 goto err_col_port_enable;
4235
4236 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4237 mlxsw_sp_port->local_port);
4238 mlxsw_sp_port->lag_id = lag_id;
4239 mlxsw_sp_port->lagged = 1;
4240 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004241
Ido Schimmelc57529e2017-05-26 08:37:31 +02004242 /* Port is no longer usable as a router interface */
4243 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4244 if (mlxsw_sp_port_vlan->fid)
Ido Schimmela1107482017-05-26 08:37:39 +02004245 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004246
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004247 return 0;
4248
Ido Schimmel51554db2016-05-06 22:18:39 +02004249err_col_port_enable:
4250 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004251err_col_port_add:
4252 if (!lag->ref_count)
4253 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004254 return err;
4255}
4256
Ido Schimmel82e6db02016-06-20 23:04:04 +02004257static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4258 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004259{
4260 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004261 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004262 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004263
4264 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004265 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004266 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4267 WARN_ON(lag->ref_count == 0);
4268
Ido Schimmel82e6db02016-06-20 23:04:04 +02004269 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4270 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004271
Ido Schimmelc57529e2017-05-26 08:37:31 +02004272 /* Any VLANs configured on the port are no longer valid */
4273 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004274
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004275 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004276 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004277
4278 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4279 mlxsw_sp_port->local_port);
4280 mlxsw_sp_port->lagged = 0;
4281 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004282
Ido Schimmelc57529e2017-05-26 08:37:31 +02004283 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4284 /* Make sure untagged frames are allowed to ingress */
4285 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004286}
4287
Jiri Pirko74581202015-12-03 12:12:30 +01004288static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4289 u16 lag_id)
4290{
4291 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4292 char sldr_pl[MLXSW_REG_SLDR_LEN];
4293
4294 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4295 mlxsw_sp_port->local_port);
4296 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4297}
4298
4299static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4300 u16 lag_id)
4301{
4302 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4303 char sldr_pl[MLXSW_REG_SLDR_LEN];
4304
4305 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4306 mlxsw_sp_port->local_port);
4307 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4308}
4309
4310static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4311 bool lag_tx_enabled)
4312{
4313 if (lag_tx_enabled)
4314 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4315 mlxsw_sp_port->lag_id);
4316 else
4317 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4318 mlxsw_sp_port->lag_id);
4319}
4320
4321static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4322 struct netdev_lag_lower_state_info *info)
4323{
4324 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4325}
4326
Jiri Pirko2b94e582017-04-18 16:55:37 +02004327static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4328 bool enable)
4329{
4330 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4331 enum mlxsw_reg_spms_state spms_state;
4332 char *spms_pl;
4333 u16 vid;
4334 int err;
4335
4336 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4337 MLXSW_REG_SPMS_STATE_DISCARDING;
4338
4339 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4340 if (!spms_pl)
4341 return -ENOMEM;
4342 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4343
4344 for (vid = 0; vid < VLAN_N_VID; vid++)
4345 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4346
4347 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4348 kfree(spms_pl);
4349 return err;
4350}
4351
4352static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4353{
Yuval Mintzfccff082017-12-15 08:44:21 +01004354 u16 vid = 1;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004355 int err;
4356
Ido Schimmel4aafc362017-05-26 08:37:25 +02004357 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004358 if (err)
4359 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02004360 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4361 if (err)
4362 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004363 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4364 true, false);
4365 if (err)
4366 goto err_port_vlan_set;
Yuval Mintzfccff082017-12-15 08:44:21 +01004367
4368 for (; vid <= VLAN_N_VID - 1; vid++) {
4369 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4370 vid, false);
4371 if (err)
4372 goto err_vid_learning_set;
4373 }
4374
Jiri Pirko2b94e582017-04-18 16:55:37 +02004375 return 0;
4376
Yuval Mintzfccff082017-12-15 08:44:21 +01004377err_vid_learning_set:
4378 for (vid--; vid >= 1; vid--)
4379 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004380err_port_vlan_set:
4381 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004382err_port_stp_set:
4383 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004384 return err;
4385}
4386
4387static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4388{
Yuval Mintzfccff082017-12-15 08:44:21 +01004389 u16 vid;
4390
4391 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4392 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4393 vid, true);
4394
Jiri Pirko2b94e582017-04-18 16:55:37 +02004395 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4396 false, false);
4397 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004398 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004399}
4400
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004401static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4402 struct net_device *dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004403 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004404{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004405 struct netdev_notifier_changeupper_info *info;
4406 struct mlxsw_sp_port *mlxsw_sp_port;
David Aherne58376e2017-10-04 17:48:51 -07004407 struct netlink_ext_ack *extack;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004408 struct net_device *upper_dev;
4409 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004410 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004411
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004412 mlxsw_sp_port = netdev_priv(dev);
4413 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4414 info = ptr;
David Aherne58376e2017-10-04 17:48:51 -07004415 extack = netdev_notifier_info_to_extack(&info->info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004416
4417 switch (event) {
4418 case NETDEV_PRECHANGEUPPER:
4419 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004420 if (!is_vlan_dev(upper_dev) &&
4421 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004422 !netif_is_bridge_master(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004423 !netif_is_ovs_master(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004424 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004425 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004426 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004427 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004428 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004429 if (netdev_has_any_upper_dev(upper_dev) &&
4430 (!netif_is_bridge_master(upper_dev) ||
4431 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4432 upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004433 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004434 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004435 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004436 if (netif_is_lag_master(upper_dev) &&
4437 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
David Aherne58376e2017-10-04 17:48:51 -07004438 info->upper_info, extack))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004439 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004440 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004441 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004442 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004443 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004444 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004445 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004446 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004447 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004448 }
4449 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004450 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004451 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004452 }
4453 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004454 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004455 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004456 }
Petr Machata47bf9df2018-05-27 09:48:41 +03004457 if (is_vlan_dev(upper_dev) &&
4458 vlan_dev_vlan_id(upper_dev) == 1) {
4459 NL_SET_ERR_MSG_MOD(extack, "Creating a VLAN device with VID 1 is unsupported: VLAN 1 carries untagged traffic");
4460 return -EINVAL;
4461 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004462 break;
4463 case NETDEV_CHANGEUPPER:
4464 upper_dev = info->upper_dev;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004465 if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004466 if (info->linking)
4467 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004468 lower_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004469 upper_dev,
4470 extack);
Ido Schimmel7117a572016-06-20 23:04:06 +02004471 else
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004472 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4473 lower_dev,
4474 upper_dev);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004475 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004476 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004477 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4478 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004479 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004480 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4481 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004482 } else if (netif_is_ovs_master(upper_dev)) {
4483 if (info->linking)
4484 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4485 else
4486 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004487 }
4488 break;
4489 }
4490
Ido Schimmel80bedf12016-06-20 23:03:59 +02004491 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004492}
4493
Jiri Pirko74581202015-12-03 12:12:30 +01004494static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4495 unsigned long event, void *ptr)
4496{
4497 struct netdev_notifier_changelowerstate_info *info;
4498 struct mlxsw_sp_port *mlxsw_sp_port;
4499 int err;
4500
4501 mlxsw_sp_port = netdev_priv(dev);
4502 info = ptr;
4503
4504 switch (event) {
4505 case NETDEV_CHANGELOWERSTATE:
4506 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4507 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4508 info->lower_state_info);
4509 if (err)
4510 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4511 }
4512 break;
4513 }
4514
Ido Schimmel80bedf12016-06-20 23:03:59 +02004515 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004516}
4517
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004518static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4519 struct net_device *port_dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004520 unsigned long event, void *ptr)
4521{
4522 switch (event) {
4523 case NETDEV_PRECHANGEUPPER:
4524 case NETDEV_CHANGEUPPER:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004525 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4526 event, ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004527 case NETDEV_CHANGELOWERSTATE:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004528 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4529 ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004530 }
4531
Ido Schimmel80bedf12016-06-20 23:03:59 +02004532 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004533}
4534
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004535static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4536 unsigned long event, void *ptr)
4537{
4538 struct net_device *dev;
4539 struct list_head *iter;
4540 int ret;
4541
4542 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4543 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004544 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4545 ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004546 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004547 return ret;
4548 }
4549 }
4550
Ido Schimmel80bedf12016-06-20 23:03:59 +02004551 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004552}
4553
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004554static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4555 struct net_device *dev,
4556 unsigned long event, void *ptr,
4557 u16 vid)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004558{
4559 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel90045fc2017-12-25 09:05:33 +01004560 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004561 struct netdev_notifier_changeupper_info *info = ptr;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004562 struct netlink_ext_ack *extack;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004563 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004564 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004565
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004566 extack = netdev_notifier_info_to_extack(&info->info);
4567
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004568 switch (event) {
4569 case NETDEV_PRECHANGEUPPER:
4570 upper_dev = info->upper_dev;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004571 if (!netif_is_bridge_master(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004572 NL_SET_ERR_MSG_MOD(extack, "VLAN devices only support bridge and VRF uppers");
Ido Schimmel80bedf12016-06-20 23:03:59 +02004573 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004574 }
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004575 if (!info->linking)
4576 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004577 if (netdev_has_any_upper_dev(upper_dev) &&
4578 (!netif_is_bridge_master(upper_dev) ||
4579 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4580 upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004581 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004582 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004583 }
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004584 break;
4585 case NETDEV_CHANGEUPPER:
4586 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004587 if (netif_is_bridge_master(upper_dev)) {
4588 if (info->linking)
Ido Schimmelc57529e2017-05-26 08:37:31 +02004589 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4590 vlan_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004591 upper_dev,
4592 extack);
Ido Schimmel1f880612017-03-10 08:53:35 +01004593 else
Ido Schimmelc57529e2017-05-26 08:37:31 +02004594 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4595 vlan_dev,
4596 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004597 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004598 err = -EINVAL;
4599 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004600 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004601 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004602 }
4603
Ido Schimmel80bedf12016-06-20 23:03:59 +02004604 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004605}
4606
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004607static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4608 struct net_device *lag_dev,
4609 unsigned long event,
4610 void *ptr, u16 vid)
Ido Schimmel272c4472015-12-15 16:03:47 +01004611{
4612 struct net_device *dev;
4613 struct list_head *iter;
4614 int ret;
4615
4616 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4617 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004618 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4619 event, ptr,
4620 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004621 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004622 return ret;
4623 }
4624 }
4625
Ido Schimmel80bedf12016-06-20 23:03:59 +02004626 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004627}
4628
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004629static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4630 unsigned long event, void *ptr)
4631{
4632 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4633 u16 vid = vlan_dev_vlan_id(vlan_dev);
4634
Ido Schimmel272c4472015-12-15 16:03:47 +01004635 if (mlxsw_sp_port_dev_check(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004636 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4637 event, ptr, vid);
Ido Schimmel272c4472015-12-15 16:03:47 +01004638 else if (netif_is_lag_master(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004639 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4640 real_dev, event,
4641 ptr, vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004642
Ido Schimmel80bedf12016-06-20 23:03:59 +02004643 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004644}
4645
Ido Schimmelb1e45522017-04-30 19:47:14 +03004646static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4647{
4648 struct netdev_notifier_changeupper_info *info = ptr;
4649
4650 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4651 return false;
4652 return netif_is_l3_master(info->upper_dev);
4653}
4654
Petr Machata00635872017-10-16 16:26:37 +02004655static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004656 unsigned long event, void *ptr)
4657{
4658 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Petr Machata079c9f32018-02-27 14:53:44 +01004659 struct mlxsw_sp_span_entry *span_entry;
Petr Machata00635872017-10-16 16:26:37 +02004660 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004661 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004662
Petr Machata00635872017-10-16 16:26:37 +02004663 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
Petr Machata079c9f32018-02-27 14:53:44 +01004664 if (event == NETDEV_UNREGISTER) {
4665 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
4666 if (span_entry)
4667 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
4668 }
Petr Machata803335a2018-02-27 14:53:46 +01004669 mlxsw_sp_span_respin(mlxsw_sp);
Petr Machata079c9f32018-02-27 14:53:44 +01004670
Petr Machata796ec772017-11-03 10:03:29 +01004671 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
4672 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
4673 event, ptr);
Petr Machata61481f22017-11-03 10:03:41 +01004674 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
4675 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
4676 event, ptr);
Petr Machata00635872017-10-16 16:26:37 +02004677 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004678 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03004679 else if (mlxsw_sp_is_vrf_event(event, ptr))
4680 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004681 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004682 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004683 else if (netif_is_lag_master(dev))
4684 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4685 else if (is_vlan_dev(dev))
4686 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004687
Ido Schimmel80bedf12016-06-20 23:03:59 +02004688 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004689}
4690
David Ahern89d5dd22017-10-18 09:56:55 -07004691static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
4692 .notifier_call = mlxsw_sp_inetaddr_valid_event,
4693};
4694
Ido Schimmel99724c12016-07-04 08:23:14 +02004695static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4696 .notifier_call = mlxsw_sp_inetaddr_event,
David Ahern89d5dd22017-10-18 09:56:55 -07004697};
4698
4699static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
4700 .notifier_call = mlxsw_sp_inet6addr_valid_event,
Ido Schimmel99724c12016-07-04 08:23:14 +02004701};
4702
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004703static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
4704 .notifier_call = mlxsw_sp_inet6addr_event,
4705};
4706
Jiri Pirko1d20d232016-10-27 15:12:59 +02004707static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4708 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4709 {0, },
4710};
4711
4712static struct pci_driver mlxsw_sp_pci_driver = {
4713 .name = mlxsw_sp_driver_name,
4714 .id_table = mlxsw_sp_pci_id_table,
4715};
4716
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004717static int __init mlxsw_sp_module_init(void)
4718{
4719 int err;
4720
David Ahern89d5dd22017-10-18 09:56:55 -07004721 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004722 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004723 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004724 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004725
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004726 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4727 if (err)
4728 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02004729
4730 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4731 if (err)
4732 goto err_pci_driver_register;
4733
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004734 return 0;
4735
Jiri Pirko1d20d232016-10-27 15:12:59 +02004736err_pci_driver_register:
4737 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004738err_core_driver_register:
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004739 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004740 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02004741 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004742 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004743 return err;
4744}
4745
4746static void __exit mlxsw_sp_module_exit(void)
4747{
Jiri Pirko1d20d232016-10-27 15:12:59 +02004748 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004749 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004750 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004751 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004752 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004753 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004754}
4755
4756module_init(mlxsw_sp_module_init);
4757module_exit(mlxsw_sp_module_exit);
4758
4759MODULE_LICENSE("Dual BSD/GPL");
4760MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4761MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02004762MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Jiri Pirkoabfd6182018-07-08 23:51:26 +03004763MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);