blob: 9bec940330a450856d2dba23ed7274321cf82059 [file] [log] [blame]
Jiri Pirko9948a062018-08-09 11:59:11 +03001// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2/* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +02007#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02008#include <linux/netdevice.h>
9#include <linux/etherdevice.h>
10#include <linux/ethtool.h>
11#include <linux/slab.h>
12#include <linux/device.h>
13#include <linux/skbuff.h>
14#include <linux/if_vlan.h>
15#include <linux/if_bridge.h>
16#include <linux/workqueue.h>
17#include <linux/jiffies.h>
18#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010019#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020020#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020021#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020022#include <linux/inetdevice.h>
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +020023#include <linux/netlink.h>
Ido Schimmelbeda7f72018-10-11 07:47:57 +000024#include <linux/random.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020025#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020026#include <net/pkt_cls.h>
27#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020028#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010029#include <net/tc_act/tc_sample.h>
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +020030#include <net/addrconf.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020031
32#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020033#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020034#include "core.h"
35#include "reg.h"
36#include "port.h"
37#include "trap.h"
38#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010039#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020040#include "spectrum_dpipe.h"
Yotam Gigid3b939b2017-09-19 10:00:09 +020041#include "spectrum_acl_flex_actions.h"
Petr Machataa629ef22018-02-13 11:27:48 +010042#include "spectrum_span.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020043#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020044
Jiri Pirkoabfd6182018-07-08 23:51:26 +030045#define MLXSW_SP_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
Yotam Gigi6b742192017-05-23 21:56:29 +020046
Jiri Pirkoabfd6182018-07-08 23:51:26 +030047#define MLXSW_SP1_FWREV_MAJOR 13
Petr Machataf9d5b1d2018-09-20 09:31:45 +030048#define MLXSW_SP1_FWREV_MINOR 1703
49#define MLXSW_SP1_FWREV_SUBMINOR 4
Jiri Pirkoc86d62c2018-08-09 11:59:09 +030050#define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
Jiri Pirkoabfd6182018-07-08 23:51:26 +030051
52static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
53 .major = MLXSW_SP1_FWREV_MAJOR,
54 .minor = MLXSW_SP1_FWREV_MINOR,
55 .subminor = MLXSW_SP1_FWREV_SUBMINOR,
Jiri Pirkoc86d62c2018-08-09 11:59:09 +030056 .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
Jiri Pirkoabfd6182018-07-08 23:51:26 +030057};
58
59#define MLXSW_SP1_FW_FILENAME \
60 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
61 "." __stringify(MLXSW_SP1_FWREV_MINOR) \
62 "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2"
Yotam Gigi6b742192017-05-23 21:56:29 +020063
Jiri Pirkoc3ab4352018-07-18 11:14:45 +030064static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
65static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
Jiri Pirko56ade8f2015-10-16 14:01:37 +020066static const char mlxsw_sp_driver_version[] = "1.0";
67
68/* tx_hdr_version
69 * Tx header version.
70 * Must be set to 1.
71 */
72MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
73
74/* tx_hdr_ctl
75 * Packet control type.
76 * 0 - Ethernet control (e.g. EMADs, LACP)
77 * 1 - Ethernet data
78 */
79MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
80
81/* tx_hdr_proto
82 * Packet protocol type. Must be set to 1 (Ethernet).
83 */
84MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
85
86/* tx_hdr_rx_is_router
87 * Packet is sent from the router. Valid for data packets only.
88 */
89MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
90
91/* tx_hdr_fid_valid
92 * Indicates if the 'fid' field is valid and should be used for
93 * forwarding lookup. Valid for data packets only.
94 */
95MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
96
97/* tx_hdr_swid
98 * Switch partition ID. Must be set to 0.
99 */
100MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
101
102/* tx_hdr_control_tclass
103 * Indicates if the packet should use the control TClass and not one
104 * of the data TClasses.
105 */
106MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
107
108/* tx_hdr_etclass
109 * Egress TClass to be used on the egress device on the egress port.
110 */
111MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
112
113/* tx_hdr_port_mid
114 * Destination local port for unicast packets.
115 * Destination multicast ID for multicast packets.
116 *
117 * Control packets are directed to a specific egress port, while data
118 * packets are transmitted through the CPU port (0) into the switch partition,
119 * where forwarding rules are applied.
120 */
121MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
122
123/* tx_hdr_fid
124 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
125 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
126 * Valid for data packets only.
127 */
128MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
129
130/* tx_hdr_type
131 * 0 - Data packets
132 * 6 - Control packets
133 */
134MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
135
Yotam Gigie5e5c882017-05-23 21:56:27 +0200136struct mlxsw_sp_mlxfw_dev {
137 struct mlxfw_dev mlxfw_dev;
138 struct mlxsw_sp *mlxsw_sp;
139};
140
141static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
142 u16 component_index, u32 *p_max_size,
143 u8 *p_align_bits, u16 *p_max_write_size)
144{
145 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
146 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
147 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
148 char mcqi_pl[MLXSW_REG_MCQI_LEN];
149 int err;
150
151 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
152 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
153 if (err)
154 return err;
155 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
156 p_max_write_size);
157
158 *p_align_bits = max_t(u8, *p_align_bits, 2);
159 *p_max_write_size = min_t(u16, *p_max_write_size,
160 MLXSW_REG_MCDA_MAX_DATA_LEN);
161 return 0;
162}
163
164static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
165{
166 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
167 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
168 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
169 char mcc_pl[MLXSW_REG_MCC_LEN];
170 u8 control_state;
171 int err;
172
173 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
174 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
175 if (err)
176 return err;
177
178 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
179 if (control_state != MLXFW_FSM_STATE_IDLE)
180 return -EBUSY;
181
182 mlxsw_reg_mcc_pack(mcc_pl,
183 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
184 0, *fwhandle, 0);
185 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
186}
187
188static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
189 u32 fwhandle, u16 component_index,
190 u32 component_size)
191{
192 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
193 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
194 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
195 char mcc_pl[MLXSW_REG_MCC_LEN];
196
197 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
198 component_index, fwhandle, component_size);
199 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
200}
201
202static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
203 u32 fwhandle, u8 *data, u16 size,
204 u32 offset)
205{
206 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
207 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
208 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
209 char mcda_pl[MLXSW_REG_MCDA_LEN];
210
211 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
212 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
213}
214
215static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
216 u32 fwhandle, u16 component_index)
217{
218 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
219 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
220 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
221 char mcc_pl[MLXSW_REG_MCC_LEN];
222
223 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
224 component_index, fwhandle, 0);
225 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
226}
227
228static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
229{
230 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
231 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
232 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
233 char mcc_pl[MLXSW_REG_MCC_LEN];
234
235 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
236 fwhandle, 0);
237 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
238}
239
240static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
241 enum mlxfw_fsm_state *fsm_state,
242 enum mlxfw_fsm_state_err *fsm_state_err)
243{
244 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
245 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
246 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
247 char mcc_pl[MLXSW_REG_MCC_LEN];
248 u8 control_state;
249 u8 error_code;
250 int err;
251
252 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
253 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
254 if (err)
255 return err;
256
257 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
258 *fsm_state = control_state;
259 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
260 MLXFW_FSM_STATE_ERR_MAX);
261 return 0;
262}
263
264static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
265{
266 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
267 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
268 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
269 char mcc_pl[MLXSW_REG_MCC_LEN];
270
271 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
272 fwhandle, 0);
273 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
274}
275
276static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
277{
278 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
279 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
280 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
281 char mcc_pl[MLXSW_REG_MCC_LEN];
282
283 mlxsw_reg_mcc_pack(mcc_pl,
284 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
285 fwhandle, 0);
286 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
287}
288
289static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
290 .component_query = mlxsw_sp_component_query,
291 .fsm_lock = mlxsw_sp_fsm_lock,
292 .fsm_component_update = mlxsw_sp_fsm_component_update,
293 .fsm_block_download = mlxsw_sp_fsm_block_download,
294 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
295 .fsm_activate = mlxsw_sp_fsm_activate,
296 .fsm_query_state = mlxsw_sp_fsm_query_state,
297 .fsm_cancel = mlxsw_sp_fsm_cancel,
298 .fsm_release = mlxsw_sp_fsm_release
299};
300
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300301static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
302 const struct firmware *firmware)
303{
304 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
305 .mlxfw_dev = {
306 .ops = &mlxsw_sp_mlxfw_dev_ops,
307 .psid = mlxsw_sp->bus_info->psid,
308 .psid_size = strlen(mlxsw_sp->bus_info->psid),
309 },
310 .mlxsw_sp = mlxsw_sp
311 };
312
313 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
314}
315
Yotam Gigi6b742192017-05-23 21:56:29 +0200316static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
317{
318 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
Jiri Pirkoabfd6182018-07-08 23:51:26 +0300319 const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev;
320 const char *fw_filename = mlxsw_sp->fw_filename;
Yotam Gigi6b742192017-05-23 21:56:29 +0200321 const struct firmware *firmware;
322 int err;
323
Jiri Pirkoabfd6182018-07-08 23:51:26 +0300324 /* Don't check if driver does not require it */
325 if (!req_rev || !fw_filename)
326 return 0;
327
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100328 /* Validate driver & FW are compatible */
Jiri Pirkoabfd6182018-07-08 23:51:26 +0300329 if (rev->major != req_rev->major) {
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100330 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
Jiri Pirkoabfd6182018-07-08 23:51:26 +0300331 rev->major, req_rev->major);
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100332 return -EINVAL;
333 }
Jiri Pirkoabfd6182018-07-08 23:51:26 +0300334 if (MLXSW_SP_FWREV_MINOR_TO_BRANCH(rev->minor) ==
Petr Machata12ba7e12018-09-23 17:48:55 +0300335 MLXSW_SP_FWREV_MINOR_TO_BRANCH(req_rev->minor) &&
336 (rev->minor > req_rev->minor ||
337 (rev->minor == req_rev->minor &&
338 rev->subminor >= req_rev->subminor)))
Yotam Gigi6b742192017-05-23 21:56:29 +0200339 return 0;
340
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100341 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200342 rev->major, rev->minor, rev->subminor);
Yuval Mintzfd5204c2018-01-18 12:55:23 +0100343 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
Jiri Pirkoabfd6182018-07-08 23:51:26 +0300344 fw_filename);
Yotam Gigi6b742192017-05-23 21:56:29 +0200345
Jiri Pirkoabfd6182018-07-08 23:51:26 +0300346 err = request_firmware_direct(&firmware, fw_filename,
Yotam Gigi6b742192017-05-23 21:56:29 +0200347 mlxsw_sp->bus_info->dev);
348 if (err) {
349 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
Jiri Pirkoabfd6182018-07-08 23:51:26 +0300350 fw_filename);
Yotam Gigi6b742192017-05-23 21:56:29 +0200351 return err;
352 }
353
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300354 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
Yotam Gigi6b742192017-05-23 21:56:29 +0200355 release_firmware(firmware);
Jiri Pirkoc86d62c2018-08-09 11:59:09 +0300356 if (err)
357 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
358
359 /* On FW flash success, tell the caller FW reset is needed
360 * if current FW supports it.
361 */
362 if (rev->minor >= req_rev->can_reset_minor)
363 return err ? err : -EAGAIN;
364 else
365 return 0;
Yotam Gigi6b742192017-05-23 21:56:29 +0200366}
367
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100368int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
369 unsigned int counter_index, u64 *packets,
370 u64 *bytes)
371{
372 char mgpc_pl[MLXSW_REG_MGPC_LEN];
373 int err;
374
375 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200376 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100377 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
378 if (err)
379 return err;
Arkadi Sharshevsky7cfcbc72017-08-24 08:40:08 +0200380 if (packets)
381 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
382 if (bytes)
383 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100384 return 0;
385}
386
387static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
388 unsigned int counter_index)
389{
390 char mgpc_pl[MLXSW_REG_MGPC_LEN];
391
392 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200393 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100394 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
395}
396
397int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
398 unsigned int *p_counter_index)
399{
400 int err;
401
402 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
403 p_counter_index);
404 if (err)
405 return err;
406 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
407 if (err)
408 goto err_counter_clear;
409 return 0;
410
411err_counter_clear:
412 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
413 *p_counter_index);
414 return err;
415}
416
417void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
418 unsigned int counter_index)
419{
420 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
421 counter_index);
422}
423
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200424static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
425 const struct mlxsw_tx_info *tx_info)
426{
427 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
428
429 memset(txhdr, 0, MLXSW_TXHDR_LEN);
430
431 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
432 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
433 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
434 mlxsw_tx_hdr_swid_set(txhdr, 0);
435 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
436 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
437 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
438}
439
Petr Machata541e1152018-04-29 10:56:09 +0300440enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200441{
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200442 switch (state) {
443 case BR_STATE_FORWARDING:
Petr Machata541e1152018-04-29 10:56:09 +0300444 return MLXSW_REG_SPMS_STATE_FORWARDING;
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200445 case BR_STATE_LEARNING:
Petr Machata541e1152018-04-29 10:56:09 +0300446 return MLXSW_REG_SPMS_STATE_LEARNING;
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200447 case BR_STATE_LISTENING: /* fall-through */
448 case BR_STATE_DISABLED: /* fall-through */
449 case BR_STATE_BLOCKING:
Petr Machata541e1152018-04-29 10:56:09 +0300450 return MLXSW_REG_SPMS_STATE_DISCARDING;
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200451 default:
452 BUG();
453 }
Petr Machata541e1152018-04-29 10:56:09 +0300454}
455
456int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
457 u8 state)
458{
459 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
460 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
461 char *spms_pl;
462 int err;
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200463
464 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
465 if (!spms_pl)
466 return -ENOMEM;
467 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
468 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
469
470 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
471 kfree(spms_pl);
472 return err;
473}
474
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200475static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
476{
Elad Raz5b090742016-10-28 21:35:46 +0200477 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200478 int err;
479
480 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
481 if (err)
482 return err;
483 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
484 return 0;
485}
486
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100487static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
488 bool enable, u32 rate)
489{
490 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
491 char mpsc_pl[MLXSW_REG_MPSC_LEN];
492
493 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
494 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
495}
496
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200497static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
498 bool is_up)
499{
500 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
501 char paos_pl[MLXSW_REG_PAOS_LEN];
502
503 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
504 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
505 MLXSW_PORT_ADMIN_STATUS_DOWN);
506 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
507}
508
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200509static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
510 unsigned char *addr)
511{
512 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
513 char ppad_pl[MLXSW_REG_PPAD_LEN];
514
515 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
516 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
517 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
518}
519
520static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
521{
522 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
523 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
524
525 ether_addr_copy(addr, mlxsw_sp->base_mac);
526 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
527 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
528}
529
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200530static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
531{
532 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
533 char pmtu_pl[MLXSW_REG_PMTU_LEN];
534 int max_mtu;
535 int err;
536
537 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
538 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
539 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
540 if (err)
541 return err;
542 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
543
544 if (mtu > max_mtu)
545 return -EINVAL;
546
547 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
548 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
549}
550
551static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
552{
553 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel5b153852017-06-08 08:47:44 +0200554 char pspa_pl[MLXSW_REG_PSPA_LEN];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200555
Ido Schimmel5b153852017-06-08 08:47:44 +0200556 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
557 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200558}
559
Ido Schimmela1107482017-05-26 08:37:39 +0200560int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200561{
562 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
563 char svpe_pl[MLXSW_REG_SVPE_LEN];
564
565 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
566 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
567}
568
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200569int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
570 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200571{
572 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
573 char *spvmlr_pl;
574 int err;
575
576 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
577 if (!spvmlr_pl)
578 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200579 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
580 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200581 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
582 kfree(spvmlr_pl);
583 return err;
584}
585
Ido Schimmelb02eae92017-05-16 19:38:34 +0200586static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
587 u16 vid)
588{
589 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
590 char spvid_pl[MLXSW_REG_SPVID_LEN];
591
592 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
593 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
594}
595
596static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
597 bool allow)
598{
599 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
600 char spaft_pl[MLXSW_REG_SPAFT_LEN];
601
602 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
603 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
604}
605
606int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
607{
608 int err;
609
610 if (!vid) {
611 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
612 if (err)
613 return err;
614 } else {
615 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
616 if (err)
617 return err;
618 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
619 if (err)
620 goto err_port_allow_untagged_set;
621 }
622
623 mlxsw_sp_port->pvid = vid;
624 return 0;
625
626err_port_allow_untagged_set:
627 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
628 return err;
629}
630
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200631static int
632mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
633{
634 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
635 char sspr_pl[MLXSW_REG_SSPR_LEN];
636
637 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
638 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
639}
640
Ido Schimmeld664b412016-06-09 09:51:40 +0200641static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
642 u8 local_port, u8 *p_module,
643 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200644{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200645 char pmlp_pl[MLXSW_REG_PMLP_LEN];
646 int err;
647
Ido Schimmel558c2d52016-02-26 17:32:29 +0100648 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200649 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
650 if (err)
651 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100652 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
653 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200654 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200655 return 0;
656}
657
Ido Schimmel2e915e02017-06-08 08:47:45 +0200658static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100659 u8 module, u8 width, u8 lane)
660{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200661 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel18f1e702016-02-26 17:32:31 +0100662 char pmlp_pl[MLXSW_REG_PMLP_LEN];
663 int i;
664
Ido Schimmel2e915e02017-06-08 08:47:45 +0200665 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel18f1e702016-02-26 17:32:31 +0100666 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
667 for (i = 0; i < width; i++) {
668 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
669 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
670 }
671
672 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
673}
674
Ido Schimmel2e915e02017-06-08 08:47:45 +0200675static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100676{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200677 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100678 char pmlp_pl[MLXSW_REG_PMLP_LEN];
679
Ido Schimmel2e915e02017-06-08 08:47:45 +0200680 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100681 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
682 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
683}
684
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200685static int mlxsw_sp_port_open(struct net_device *dev)
686{
687 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
688 int err;
689
690 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
691 if (err)
692 return err;
693 netif_start_queue(dev);
694 return 0;
695}
696
697static int mlxsw_sp_port_stop(struct net_device *dev)
698{
699 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
700
701 netif_stop_queue(dev);
702 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
703}
704
705static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
706 struct net_device *dev)
707{
708 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
709 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
710 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
711 const struct mlxsw_tx_info tx_info = {
712 .local_port = mlxsw_sp_port->local_port,
713 .is_emad = false,
714 };
715 u64 len;
716 int err;
717
Jiri Pirko307c2432016-04-08 19:11:22 +0200718 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200719 return NETDEV_TX_BUSY;
720
721 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
722 struct sk_buff *skb_orig = skb;
723
724 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
725 if (!skb) {
726 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
727 dev_kfree_skb_any(skb_orig);
728 return NETDEV_TX_OK;
729 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +0100730 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200731 }
732
733 if (eth_skb_pad(skb)) {
734 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
735 return NETDEV_TX_OK;
736 }
737
738 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +0200739 /* TX header is consumed by HW on the way so we shouldn't count its
740 * bytes as being sent.
741 */
742 len = skb->len - MLXSW_TXHDR_LEN;
743
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200744 /* Due to a race we might fail here because of a full queue. In that
745 * unlikely case we simply drop the packet.
746 */
Jiri Pirko307c2432016-04-08 19:11:22 +0200747 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200748
749 if (!err) {
750 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
751 u64_stats_update_begin(&pcpu_stats->syncp);
752 pcpu_stats->tx_packets++;
753 pcpu_stats->tx_bytes += len;
754 u64_stats_update_end(&pcpu_stats->syncp);
755 } else {
756 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
757 dev_kfree_skb_any(skb);
758 }
759 return NETDEV_TX_OK;
760}
761
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100762static void mlxsw_sp_set_rx_mode(struct net_device *dev)
763{
764}
765
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200766static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
767{
768 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
769 struct sockaddr *addr = p;
770 int err;
771
772 if (!is_valid_ether_addr(addr->sa_data))
773 return -EADDRNOTAVAIL;
774
775 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
776 if (err)
777 return err;
778 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
779 return 0;
780}
781
Ido Schimmel18281f22017-03-24 08:02:51 +0100782static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
783 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200784{
Ido Schimmel18281f22017-03-24 08:02:51 +0100785 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100786}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200787
Ido Schimmelf417f042017-03-24 08:02:50 +0100788#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +0100789
790static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
791 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +0100792{
Ido Schimmel18281f22017-03-24 08:02:51 +0100793 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
794 BITS_PER_BYTE));
795 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
796 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100797}
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200798
Ido Schimmel18281f22017-03-24 08:02:51 +0100799/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +0100800 * Assumes 100m cable and maximum MTU.
801 */
Ido Schimmel18281f22017-03-24 08:02:51 +0100802#define MLXSW_SP_PAUSE_DELAY 58752
803
804static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
805 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +0100806{
807 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +0100808 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +0100809 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +0100810 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200811 else
Ido Schimmelf417f042017-03-24 08:02:50 +0100812 return 0;
813}
814
815static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
816 bool lossy)
817{
818 if (lossy)
819 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
820 else
821 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
822 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200823}
824
825int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200826 u8 *prio_tc, bool pause_en,
827 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +0200828{
829 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200830 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
831 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200832 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200833 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200834
835 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
836 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
837 if (err)
838 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200839
840 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
841 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200842 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +0100843 bool lossy;
844 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200845
846 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
847 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200848 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200849 configure = true;
850 break;
851 }
852 }
853
854 if (!configure)
855 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +0100856
857 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +0100858 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
859 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
860 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +0100861 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200862 }
863
Ido Schimmelff6551e2016-04-06 17:10:03 +0200864 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
865}
866
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200867static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200868 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200869{
870 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
871 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200872 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200873 u8 *prio_tc;
874
875 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200876 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200877
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200878 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200879 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200880}
881
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200882static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
883{
884 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200885 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200886 int err;
887
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200888 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200889 if (err)
890 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200891 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
892 if (err)
893 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200894 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
895 if (err)
896 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200897 dev->mtu = mtu;
898 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200899
900err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +0200901 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
902err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200903 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +0200904 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200905}
906
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +0300907static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200908mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
909 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200910{
911 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
912 struct mlxsw_sp_port_pcpu_stats *p;
913 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
914 u32 tx_dropped = 0;
915 unsigned int start;
916 int i;
917
918 for_each_possible_cpu(i) {
919 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
920 do {
921 start = u64_stats_fetch_begin_irq(&p->syncp);
922 rx_packets = p->rx_packets;
923 rx_bytes = p->rx_bytes;
924 tx_packets = p->tx_packets;
925 tx_bytes = p->tx_bytes;
926 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
927
928 stats->rx_packets += rx_packets;
929 stats->rx_bytes += rx_bytes;
930 stats->tx_packets += tx_packets;
931 stats->tx_bytes += tx_bytes;
932 /* tx_dropped is u32, updated without syncp protection. */
933 tx_dropped += p->tx_dropped;
934 }
935 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200936 return 0;
937}
938
Or Gerlitz3df5b3c2016-11-22 23:09:54 +0200939static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200940{
941 switch (attr_id) {
942 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
943 return true;
944 }
945
946 return false;
947}
948
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +0300949static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
950 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200951{
952 switch (attr_id) {
953 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
954 return mlxsw_sp_port_get_sw_stats64(dev, sp);
955 }
956
957 return -EINVAL;
958}
959
960static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
961 int prio, char *ppcnt_pl)
962{
963 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
964 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
965
966 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
967 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
968}
969
970static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
971 struct rtnl_link_stats64 *stats)
972{
973 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
974 int err;
975
976 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
977 0, ppcnt_pl);
978 if (err)
979 goto out;
980
981 stats->tx_packets =
982 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
983 stats->rx_packets =
984 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
985 stats->tx_bytes =
986 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
987 stats->rx_bytes =
988 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
989 stats->multicast =
990 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
991
992 stats->rx_crc_errors =
993 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
994 stats->rx_frame_errors =
995 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
996
997 stats->rx_length_errors = (
998 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
999 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1000 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1001
1002 stats->rx_errors = (stats->rx_crc_errors +
1003 stats->rx_frame_errors + stats->rx_length_errors);
1004
1005out:
1006 return err;
1007}
1008
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001009static void
1010mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1011 struct mlxsw_sp_port_xstats *xstats)
1012{
1013 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1014 int err, i;
1015
1016 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1017 ppcnt_pl);
1018 if (!err)
1019 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1020
1021 for (i = 0; i < TC_MAX_QUEUE; i++) {
1022 err = mlxsw_sp_port_get_stats_raw(dev,
1023 MLXSW_REG_PPCNT_TC_CONG_TC,
1024 i, ppcnt_pl);
1025 if (!err)
1026 xstats->wred_drop[i] =
1027 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1028
1029 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1030 i, ppcnt_pl);
1031 if (err)
1032 continue;
1033
1034 xstats->backlog[i] =
1035 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1036 xstats->tail_drop[i] =
1037 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1038 }
Nogah Frankel2f880472018-02-28 10:44:59 +01001039
1040 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1041 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
1042 i, ppcnt_pl);
1043 if (err)
1044 continue;
1045
1046 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
1047 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
1048 }
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001049}
1050
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001051static void update_stats_cache(struct work_struct *work)
1052{
1053 struct mlxsw_sp_port *mlxsw_sp_port =
1054 container_of(work, struct mlxsw_sp_port,
Nogah Frankel9deef432017-10-26 10:55:32 +02001055 periodic_hw_stats.update_dw.work);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001056
1057 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1058 goto out;
1059
1060 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
Nogah Frankel9deef432017-10-26 10:55:32 +02001061 &mlxsw_sp_port->periodic_hw_stats.stats);
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001062 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1063 &mlxsw_sp_port->periodic_hw_stats.xstats);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001064
1065out:
Nogah Frankel9deef432017-10-26 10:55:32 +02001066 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001067 MLXSW_HW_STATS_UPDATE_TIME);
1068}
1069
1070/* Return the stats from a cache that is updated periodically,
1071 * as this function might get called in an atomic context.
1072 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001073static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001074mlxsw_sp_port_get_stats64(struct net_device *dev,
1075 struct rtnl_link_stats64 *stats)
1076{
1077 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1078
Nogah Frankel9deef432017-10-26 10:55:32 +02001079 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001080}
1081
Jiri Pirko93cd0812017-04-18 16:55:35 +02001082static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1083 u16 vid_begin, u16 vid_end,
1084 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001085{
1086 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1087 char *spvm_pl;
1088 int err;
1089
1090 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1091 if (!spvm_pl)
1092 return -ENOMEM;
1093
1094 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1095 vid_end, is_member, untagged);
1096 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1097 kfree(spvm_pl);
1098 return err;
1099}
1100
Jiri Pirko93cd0812017-04-18 16:55:35 +02001101int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1102 u16 vid_end, bool is_member, bool untagged)
1103{
1104 u16 vid, vid_e;
1105 int err;
1106
1107 for (vid = vid_begin; vid <= vid_end;
1108 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1109 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1110 vid_end);
1111
1112 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1113 is_member, untagged);
1114 if (err)
1115 return err;
1116 }
1117
1118 return 0;
1119}
1120
Ido Schimmelc57529e2017-05-26 08:37:31 +02001121static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001122{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001123 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001124
Ido Schimmelc57529e2017-05-26 08:37:31 +02001125 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1126 &mlxsw_sp_port->vlans_list, list)
1127 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001128}
1129
Ido Schimmel31a08a52017-05-26 08:37:26 +02001130static struct mlxsw_sp_port_vlan *
1131mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1132{
1133 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001134 bool untagged = vid == 1;
1135 int err;
1136
1137 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1138 if (err)
1139 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001140
1141 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001142 if (!mlxsw_sp_port_vlan) {
1143 err = -ENOMEM;
1144 goto err_port_vlan_alloc;
1145 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02001146
1147 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
Ido Schimmelb3529af2018-02-28 13:12:11 +01001148 mlxsw_sp_port_vlan->ref_count = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02001149 mlxsw_sp_port_vlan->vid = vid;
1150 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1151
1152 return mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001153
1154err_port_vlan_alloc:
1155 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1156 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001157}
1158
1159static void
1160mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1161{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001162 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1163 u16 vid = mlxsw_sp_port_vlan->vid;
Ido Schimmel7cbecf22017-05-26 08:37:28 +02001164
Ido Schimmel31a08a52017-05-26 08:37:26 +02001165 list_del(&mlxsw_sp_port_vlan->list);
1166 kfree(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001167 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1168}
1169
1170struct mlxsw_sp_port_vlan *
1171mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1172{
1173 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1174
1175 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelb3529af2018-02-28 13:12:11 +01001176 if (mlxsw_sp_port_vlan) {
1177 mlxsw_sp_port_vlan->ref_count++;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001178 return mlxsw_sp_port_vlan;
Ido Schimmelb3529af2018-02-28 13:12:11 +01001179 }
Ido Schimmelc57529e2017-05-26 08:37:31 +02001180
1181 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1182}
1183
1184void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1185{
Ido Schimmela1107482017-05-26 08:37:39 +02001186 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1187
Ido Schimmelb3529af2018-02-28 13:12:11 +01001188 if (--mlxsw_sp_port_vlan->ref_count != 0)
1189 return;
1190
Ido Schimmelc57529e2017-05-26 08:37:31 +02001191 if (mlxsw_sp_port_vlan->bridge_port)
1192 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
Ido Schimmela1107482017-05-26 08:37:39 +02001193 else if (fid)
1194 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001195
1196 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001197}
1198
Ido Schimmel05978482016-08-17 16:39:30 +02001199static int mlxsw_sp_port_add_vid(struct net_device *dev,
1200 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001201{
1202 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001203
1204 /* VLAN 0 is added to HW filter when device goes up, but it is
1205 * reserved in our case, so simply return.
1206 */
1207 if (!vid)
1208 return 0;
1209
Ido Schimmelc57529e2017-05-26 08:37:31 +02001210 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001211}
1212
Ido Schimmel32d863f2016-07-02 11:00:10 +02001213static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1214 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001215{
1216 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001217 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001218
1219 /* VLAN 0 is removed from HW filter when device goes down, but
1220 * it is reserved in our case, so simply return.
1221 */
1222 if (!vid)
1223 return 0;
1224
Ido Schimmel31a08a52017-05-26 08:37:26 +02001225 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001226 if (!mlxsw_sp_port_vlan)
Ido Schimmel31a08a52017-05-26 08:37:26 +02001227 return 0;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001228 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001229
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001230 return 0;
1231}
1232
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001233static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1234 size_t len)
1235{
1236 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001237
Jiri Pirkoec932fb2018-05-18 09:29:04 +02001238 return mlxsw_core_port_get_phys_port_name(mlxsw_sp_port->mlxsw_sp->core,
1239 mlxsw_sp_port->local_port,
1240 name, len);
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001241}
1242
Yotam Gigi763b4b72016-07-21 12:03:17 +02001243static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001244mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1245 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001246 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1247
1248 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1249 if (mall_tc_entry->cookie == cookie)
1250 return mall_tc_entry;
1251
1252 return NULL;
1253}
1254
1255static int
1256mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001257 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001258 const struct tc_action *a,
1259 bool ingress)
1260{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001261 enum mlxsw_sp_span_type span_type;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001262 struct net_device *to_dev;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001263
Cong Wang9f8a7392017-12-05 16:17:26 -08001264 to_dev = tcf_mirred_dev(a);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001265 if (!to_dev) {
1266 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1267 return -EINVAL;
1268 }
1269
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001270 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001271 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Petr Machata079c9f32018-02-27 14:53:44 +01001272 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type,
Petr Machata98977082018-02-27 14:53:41 +01001273 true, &mirror->span_id);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001274}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001275
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001276static void
1277mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1278 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1279{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001280 enum mlxsw_sp_span_type span_type;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001281
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001282 span_type = mirror->ingress ?
1283 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Petr Machata98977082018-02-27 14:53:41 +01001284 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
Arkadi Sharshevsky5c8d39c2018-01-19 09:24:50 +01001285 span_type, true);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001286}
1287
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001288static int
1289mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1290 struct tc_cls_matchall_offload *cls,
1291 const struct tc_action *a,
1292 bool ingress)
1293{
1294 int err;
1295
1296 if (!mlxsw_sp_port->sample)
1297 return -EOPNOTSUPP;
1298 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1299 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1300 return -EEXIST;
1301 }
1302 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1303 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1304 return -EOPNOTSUPP;
1305 }
1306
1307 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1308 tcf_sample_psample_group(a));
1309 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1310 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1311 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1312
1313 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1314 if (err)
1315 goto err_port_sample_set;
1316 return 0;
1317
1318err_port_sample_set:
1319 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1320 return err;
1321}
1322
1323static void
1324mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1325{
1326 if (!mlxsw_sp_port->sample)
1327 return;
1328
1329 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1330 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1331}
1332
Yotam Gigi763b4b72016-07-21 12:03:17 +02001333static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001334 struct tc_cls_matchall_offload *f,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001335 bool ingress)
1336{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001337 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001338 __be16 protocol = f->common.protocol;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001339 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001340 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001341 int err;
1342
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001343 if (!tcf_exts_has_one_action(f->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001344 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001345 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001346 }
1347
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001348 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1349 if (!mall_tc_entry)
1350 return -ENOMEM;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001351 mall_tc_entry->cookie = f->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001352
Cong Wang244cd962018-08-19 12:22:09 -07001353 a = tcf_exts_first_action(f->exts);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001354
1355 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1356 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1357
1358 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1359 mirror = &mall_tc_entry->mirror;
1360 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1361 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001362 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1363 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001364 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001365 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001366 } else {
1367 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001368 }
1369
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001370 if (err)
1371 goto err_add_action;
1372
1373 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001374 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001375
1376err_add_action:
1377 kfree(mall_tc_entry);
1378 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001379}
1380
1381static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001382 struct tc_cls_matchall_offload *f)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001383{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001384 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001385
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001386 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001387 f->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001388 if (!mall_tc_entry) {
1389 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1390 return;
1391 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001392 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001393
1394 switch (mall_tc_entry->type) {
1395 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001396 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1397 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001398 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001399 case MLXSW_SP_PORT_MALL_SAMPLE:
1400 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1401 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001402 default:
1403 WARN_ON(1);
1404 }
1405
Yotam Gigi763b4b72016-07-21 12:03:17 +02001406 kfree(mall_tc_entry);
1407}
1408
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001409static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001410 struct tc_cls_matchall_offload *f,
1411 bool ingress)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001412{
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001413 switch (f->command) {
1414 case TC_CLSMATCHALL_REPLACE:
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001415 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001416 ingress);
1417 case TC_CLSMATCHALL_DESTROY:
1418 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1419 return 0;
1420 default:
1421 return -EOPNOTSUPP;
1422 }
1423}
1424
1425static int
Jiri Pirko3aaff322018-01-17 11:46:56 +01001426mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1427 struct tc_cls_flower_offload *f)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001428{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001429 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1430
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001431 switch (f->command) {
1432 case TC_CLSFLOWER_REPLACE:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001433 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001434 case TC_CLSFLOWER_DESTROY:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001435 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001436 return 0;
1437 case TC_CLSFLOWER_STATS:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001438 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
Jiri Pirkoe2f2a1f2018-07-23 09:23:12 +02001439 case TC_CLSFLOWER_TMPLT_CREATE:
1440 return mlxsw_sp_flower_tmplt_create(mlxsw_sp, acl_block, f);
1441 case TC_CLSFLOWER_TMPLT_DESTROY:
1442 mlxsw_sp_flower_tmplt_destroy(mlxsw_sp, acl_block, f);
1443 return 0;
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001444 default:
1445 return -EOPNOTSUPP;
1446 }
1447}
1448
Jiri Pirko3aaff322018-01-17 11:46:56 +01001449static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1450 void *type_data,
1451 void *cb_priv, bool ingress)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001452{
1453 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1454
1455 switch (type) {
1456 case TC_SETUP_CLSMATCHALL:
Jakub Kicinski15f4edb2018-01-25 14:00:51 -08001457 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1458 type_data))
Jiri Pirko3aaff322018-01-17 11:46:56 +01001459 return -EOPNOTSUPP;
1460
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001461 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1462 ingress);
1463 case TC_SETUP_CLSFLOWER:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001464 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001465 default:
1466 return -EOPNOTSUPP;
1467 }
1468}
1469
Jiri Pirko3aaff322018-01-17 11:46:56 +01001470static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1471 void *type_data,
1472 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001473{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001474 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1475 cb_priv, true);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001476}
1477
Jiri Pirko3aaff322018-01-17 11:46:56 +01001478static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1479 void *type_data,
1480 void *cb_priv)
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001481{
Jiri Pirko3aaff322018-01-17 11:46:56 +01001482 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1483 cb_priv, false);
1484}
1485
1486static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1487 void *type_data, void *cb_priv)
1488{
1489 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1490
1491 switch (type) {
1492 case TC_SETUP_CLSMATCHALL:
1493 return 0;
1494 case TC_SETUP_CLSFLOWER:
1495 if (mlxsw_sp_acl_block_disabled(acl_block))
1496 return -EOPNOTSUPP;
1497
1498 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1499 default:
1500 return -EOPNOTSUPP;
1501 }
1502}
1503
1504static int
1505mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
John Hurley60513bd2018-06-25 14:30:04 -07001506 struct tcf_block *block, bool ingress,
1507 struct netlink_ext_ack *extack)
Jiri Pirko3aaff322018-01-17 11:46:56 +01001508{
1509 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1510 struct mlxsw_sp_acl_block *acl_block;
1511 struct tcf_block_cb *block_cb;
1512 int err;
1513
1514 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1515 mlxsw_sp);
1516 if (!block_cb) {
1517 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1518 if (!acl_block)
1519 return -ENOMEM;
1520 block_cb = __tcf_block_cb_register(block,
1521 mlxsw_sp_setup_tc_block_cb_flower,
John Hurley60513bd2018-06-25 14:30:04 -07001522 mlxsw_sp, acl_block, extack);
Jiri Pirko3aaff322018-01-17 11:46:56 +01001523 if (IS_ERR(block_cb)) {
1524 err = PTR_ERR(block_cb);
1525 goto err_cb_register;
1526 }
1527 } else {
1528 acl_block = tcf_block_cb_priv(block_cb);
1529 }
1530 tcf_block_cb_incref(block_cb);
1531 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1532 mlxsw_sp_port, ingress);
1533 if (err)
1534 goto err_block_bind;
1535
1536 if (ingress)
1537 mlxsw_sp_port->ing_acl_block = acl_block;
1538 else
1539 mlxsw_sp_port->eg_acl_block = acl_block;
1540
1541 return 0;
1542
1543err_block_bind:
1544 if (!tcf_block_cb_decref(block_cb)) {
John Hurley32636742018-06-25 14:30:10 -07001545 __tcf_block_cb_unregister(block, block_cb);
Jiri Pirko3aaff322018-01-17 11:46:56 +01001546err_cb_register:
1547 mlxsw_sp_acl_block_destroy(acl_block);
1548 }
1549 return err;
1550}
1551
1552static void
1553mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1554 struct tcf_block *block, bool ingress)
1555{
1556 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1557 struct mlxsw_sp_acl_block *acl_block;
1558 struct tcf_block_cb *block_cb;
1559 int err;
1560
1561 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1562 mlxsw_sp);
1563 if (!block_cb)
1564 return;
1565
1566 if (ingress)
1567 mlxsw_sp_port->ing_acl_block = NULL;
1568 else
1569 mlxsw_sp_port->eg_acl_block = NULL;
1570
1571 acl_block = tcf_block_cb_priv(block_cb);
1572 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1573 mlxsw_sp_port, ingress);
1574 if (!err && !tcf_block_cb_decref(block_cb)) {
John Hurley32636742018-06-25 14:30:10 -07001575 __tcf_block_cb_unregister(block, block_cb);
Jiri Pirko3aaff322018-01-17 11:46:56 +01001576 mlxsw_sp_acl_block_destroy(acl_block);
1577 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001578}
1579
1580static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1581 struct tc_block_offload *f)
1582{
1583 tc_setup_cb_t *cb;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001584 bool ingress;
1585 int err;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001586
Jiri Pirko3aaff322018-01-17 11:46:56 +01001587 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1588 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1589 ingress = true;
1590 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1591 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1592 ingress = false;
1593 } else {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001594 return -EOPNOTSUPP;
Jiri Pirko3aaff322018-01-17 11:46:56 +01001595 }
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001596
1597 switch (f->command) {
1598 case TC_BLOCK_BIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001599 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
John Hurley60513bd2018-06-25 14:30:04 -07001600 mlxsw_sp_port, f->extack);
Jiri Pirko3aaff322018-01-17 11:46:56 +01001601 if (err)
1602 return err;
1603 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
John Hurley60513bd2018-06-25 14:30:04 -07001604 f->block, ingress,
1605 f->extack);
Jiri Pirko3aaff322018-01-17 11:46:56 +01001606 if (err) {
1607 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1608 return err;
1609 }
1610 return 0;
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001611 case TC_BLOCK_UNBIND:
Jiri Pirko3aaff322018-01-17 11:46:56 +01001612 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1613 f->block, ingress);
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001614 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1615 return 0;
1616 default:
1617 return -EOPNOTSUPP;
1618 }
1619}
1620
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001621static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
Jiri Pirkode4784c2017-08-07 10:15:32 +02001622 void *type_data)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001623{
1624 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1625
Jiri Pirko2572ac52017-08-07 10:15:17 +02001626 switch (type) {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001627 case TC_SETUP_BLOCK:
1628 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
Nogah Frankel96f17e02017-11-06 07:23:45 +01001629 case TC_SETUP_QDISC_RED:
1630 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
Nogah Frankel46a36152018-01-14 12:33:16 +01001631 case TC_SETUP_QDISC_PRIO:
1632 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
Jiri Pirko2572ac52017-08-07 10:15:17 +02001633 default:
1634 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001635 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001636}
1637
Jiri Pirko9454d932017-12-06 09:41:12 +01001638
1639static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1640{
1641 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1642
Jiri Pirko3aaff322018-01-17 11:46:56 +01001643 if (!enable) {
1644 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1645 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1646 !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1647 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1648 return -EINVAL;
1649 }
1650 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1651 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1652 } else {
1653 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1654 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
Jiri Pirko9454d932017-12-06 09:41:12 +01001655 }
1656 return 0;
1657}
1658
1659typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1660
1661static int mlxsw_sp_handle_feature(struct net_device *dev,
1662 netdev_features_t wanted_features,
1663 netdev_features_t feature,
1664 mlxsw_sp_feature_handler feature_handler)
1665{
1666 netdev_features_t changes = wanted_features ^ dev->features;
1667 bool enable = !!(wanted_features & feature);
1668 int err;
1669
1670 if (!(changes & feature))
1671 return 0;
1672
1673 err = feature_handler(dev, enable);
1674 if (err) {
1675 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1676 enable ? "Enable" : "Disable", &feature, err);
1677 return err;
1678 }
1679
1680 if (enable)
1681 dev->features |= feature;
1682 else
1683 dev->features &= ~feature;
1684
1685 return 0;
1686}
1687static int mlxsw_sp_set_features(struct net_device *dev,
1688 netdev_features_t features)
1689{
1690 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1691 mlxsw_sp_feature_hw_tc);
1692}
1693
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001694static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1695 .ndo_open = mlxsw_sp_port_open,
1696 .ndo_stop = mlxsw_sp_port_stop,
1697 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001698 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001699 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001700 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1701 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1702 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001703 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1704 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001705 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1706 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001707 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko9454d932017-12-06 09:41:12 +01001708 .ndo_set_features = mlxsw_sp_set_features,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001709};
1710
1711static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1712 struct ethtool_drvinfo *drvinfo)
1713{
1714 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1715 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1716
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03001717 strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind,
1718 sizeof(drvinfo->driver));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001719 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1720 sizeof(drvinfo->version));
1721 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1722 "%d.%d.%d",
1723 mlxsw_sp->bus_info->fw_rev.major,
1724 mlxsw_sp->bus_info->fw_rev.minor,
1725 mlxsw_sp->bus_info->fw_rev.subminor);
1726 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1727 sizeof(drvinfo->bus_info));
1728}
1729
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001730static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1731 struct ethtool_pauseparam *pause)
1732{
1733 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1734
1735 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1736 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1737}
1738
1739static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1740 struct ethtool_pauseparam *pause)
1741{
1742 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1743
1744 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1745 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1746 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1747
1748 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1749 pfcc_pl);
1750}
1751
1752static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1753 struct ethtool_pauseparam *pause)
1754{
1755 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1756 bool pause_en = pause->tx_pause || pause->rx_pause;
1757 int err;
1758
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001759 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1760 netdev_err(dev, "PFC already enabled on port\n");
1761 return -EINVAL;
1762 }
1763
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001764 if (pause->autoneg) {
1765 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1766 return -EINVAL;
1767 }
1768
1769 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1770 if (err) {
1771 netdev_err(dev, "Failed to configure port's headroom\n");
1772 return err;
1773 }
1774
1775 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1776 if (err) {
1777 netdev_err(dev, "Failed to set PAUSE parameters\n");
1778 goto err_port_pause_configure;
1779 }
1780
1781 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1782 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1783
1784 return 0;
1785
1786err_port_pause_configure:
1787 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1788 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1789 return err;
1790}
1791
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001792struct mlxsw_sp_port_hw_stats {
1793 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02001794 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01001795 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001796};
1797
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001798static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001799 {
1800 .str = "a_frames_transmitted_ok",
1801 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1802 },
1803 {
1804 .str = "a_frames_received_ok",
1805 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1806 },
1807 {
1808 .str = "a_frame_check_sequence_errors",
1809 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1810 },
1811 {
1812 .str = "a_alignment_errors",
1813 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1814 },
1815 {
1816 .str = "a_octets_transmitted_ok",
1817 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1818 },
1819 {
1820 .str = "a_octets_received_ok",
1821 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1822 },
1823 {
1824 .str = "a_multicast_frames_xmitted_ok",
1825 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1826 },
1827 {
1828 .str = "a_broadcast_frames_xmitted_ok",
1829 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1830 },
1831 {
1832 .str = "a_multicast_frames_received_ok",
1833 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1834 },
1835 {
1836 .str = "a_broadcast_frames_received_ok",
1837 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1838 },
1839 {
1840 .str = "a_in_range_length_errors",
1841 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1842 },
1843 {
1844 .str = "a_out_of_range_length_field",
1845 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1846 },
1847 {
1848 .str = "a_frame_too_long_errors",
1849 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1850 },
1851 {
1852 .str = "a_symbol_error_during_carrier",
1853 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1854 },
1855 {
1856 .str = "a_mac_control_frames_transmitted",
1857 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1858 },
1859 {
1860 .str = "a_mac_control_frames_received",
1861 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1862 },
1863 {
1864 .str = "a_unsupported_opcodes_received",
1865 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1866 },
1867 {
1868 .str = "a_pause_mac_ctrl_frames_received",
1869 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1870 },
1871 {
1872 .str = "a_pause_mac_ctrl_frames_xmitted",
1873 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1874 },
1875};
1876
1877#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1878
Jiri Pirko1222d152018-07-15 10:45:42 +03001879static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = {
1880 {
1881 .str = "ether_pkts64octets",
1882 .getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get,
1883 },
1884 {
1885 .str = "ether_pkts65to127octets",
1886 .getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get,
1887 },
1888 {
1889 .str = "ether_pkts128to255octets",
1890 .getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get,
1891 },
1892 {
1893 .str = "ether_pkts256to511octets",
1894 .getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get,
1895 },
1896 {
1897 .str = "ether_pkts512to1023octets",
1898 .getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get,
1899 },
1900 {
1901 .str = "ether_pkts1024to1518octets",
1902 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get,
1903 },
1904 {
1905 .str = "ether_pkts1519to2047octets",
1906 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get,
1907 },
1908 {
1909 .str = "ether_pkts2048to4095octets",
1910 .getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get,
1911 },
1912 {
1913 .str = "ether_pkts4096to8191octets",
1914 .getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get,
1915 },
1916 {
1917 .str = "ether_pkts8192to10239octets",
1918 .getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get,
1919 },
1920};
1921
1922#define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \
1923 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats)
1924
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001925static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1926 {
1927 .str = "rx_octets_prio",
1928 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1929 },
1930 {
1931 .str = "rx_frames_prio",
1932 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1933 },
1934 {
1935 .str = "tx_octets_prio",
1936 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1937 },
1938 {
1939 .str = "tx_frames_prio",
1940 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1941 },
1942 {
1943 .str = "rx_pause_prio",
1944 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1945 },
1946 {
1947 .str = "rx_pause_duration_prio",
1948 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1949 },
1950 {
1951 .str = "tx_pause_prio",
1952 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1953 },
1954 {
1955 .str = "tx_pause_duration_prio",
1956 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1957 },
1958};
1959
1960#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1961
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001962static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1963 {
1964 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01001965 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1966 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001967 },
1968 {
1969 .str = "tc_no_buffer_discard_uc_tc",
1970 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1971 },
1972};
1973
1974#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1975
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001976#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Petr Machata9897dce2018-08-09 11:59:12 +03001977 MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \
Petr Machata88cc3182018-08-09 11:59:13 +03001978 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \
1979 IEEE_8021QAZ_MAX_TCS) + \
1980 (MLXSW_SP_PORT_HW_TC_STATS_LEN * \
1981 TC_MAX_QUEUE))
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001982
1983static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1984{
1985 int i;
1986
1987 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1988 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1989 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1990 *p += ETH_GSTRING_LEN;
1991 }
1992}
1993
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001994static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1995{
1996 int i;
1997
1998 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1999 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2000 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2001 *p += ETH_GSTRING_LEN;
2002 }
2003}
2004
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002005static void mlxsw_sp_port_get_strings(struct net_device *dev,
2006 u32 stringset, u8 *data)
2007{
2008 u8 *p = data;
2009 int i;
2010
2011 switch (stringset) {
2012 case ETH_SS_STATS:
2013 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2014 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2015 ETH_GSTRING_LEN);
2016 p += ETH_GSTRING_LEN;
2017 }
Jiri Pirko1222d152018-07-15 10:45:42 +03002018 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) {
2019 memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str,
2020 ETH_GSTRING_LEN);
2021 p += ETH_GSTRING_LEN;
2022 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002023
2024 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2025 mlxsw_sp_port_get_prio_strings(&p, i);
2026
Petr Machata88cc3182018-08-09 11:59:13 +03002027 for (i = 0; i < TC_MAX_QUEUE; i++)
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002028 mlxsw_sp_port_get_tc_strings(&p, i);
2029
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002030 break;
2031 }
2032}
2033
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002034static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2035 enum ethtool_phys_id_state state)
2036{
2037 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2038 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2039 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2040 bool active;
2041
2042 switch (state) {
2043 case ETHTOOL_ID_ACTIVE:
2044 active = true;
2045 break;
2046 case ETHTOOL_ID_INACTIVE:
2047 active = false;
2048 break;
2049 default:
2050 return -EOPNOTSUPP;
2051 }
2052
2053 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2054 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2055}
2056
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002057static int
2058mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2059 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2060{
2061 switch (grp) {
Jiri Pirko1222d152018-07-15 10:45:42 +03002062 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002063 *p_hw_stats = mlxsw_sp_port_hw_stats;
2064 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2065 break;
Jiri Pirko1222d152018-07-15 10:45:42 +03002066 case MLXSW_REG_PPCNT_RFC_2819_CNT:
2067 *p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats;
2068 *p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2069 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002070 case MLXSW_REG_PPCNT_PRIO_CNT:
2071 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2072 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2073 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002074 case MLXSW_REG_PPCNT_TC_CNT:
2075 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2076 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2077 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002078 default:
2079 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002080 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002081 }
2082 return 0;
2083}
2084
2085static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2086 enum mlxsw_reg_ppcnt_grp grp, int prio,
2087 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002088{
Ido Schimmel18281f22017-03-24 08:02:51 +01002089 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2090 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002091 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002092 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002093 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002094 int err;
2095
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002096 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2097 if (err)
2098 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002099 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002100 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002101 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002102 if (!hw_stats[i].cells_bytes)
2103 continue;
2104 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2105 data[data_index + i]);
2106 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002107}
2108
2109static void mlxsw_sp_port_get_stats(struct net_device *dev,
2110 struct ethtool_stats *stats, u64 *data)
2111{
2112 int i, data_index = 0;
2113
2114 /* IEEE 802.3 Counters */
2115 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2116 data, data_index);
2117 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2118
Jiri Pirko1222d152018-07-15 10:45:42 +03002119 /* RFC 2819 Counters */
2120 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0,
2121 data, data_index);
2122 data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2123
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002124 /* Per-Priority Counters */
2125 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2126 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2127 data, data_index);
2128 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2129 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002130
2131 /* Per-TC Counters */
Petr Machata88cc3182018-08-09 11:59:13 +03002132 for (i = 0; i < TC_MAX_QUEUE; i++) {
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002133 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2134 data, data_index);
2135 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2136 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002137}
2138
2139static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2140{
2141 switch (sset) {
2142 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002143 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002144 default:
2145 return -EOPNOTSUPP;
2146 }
2147}
2148
2149struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002150 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002151 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002152 u32 speed;
2153};
2154
2155static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2156 {
2157 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002158 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2159 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002160 },
2161 {
2162 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2163 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002164 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2165 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002166 },
2167 {
2168 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002169 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2170 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002171 },
2172 {
2173 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2174 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002175 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2176 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002177 },
2178 {
2179 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2180 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2181 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2182 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002183 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2184 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002185 },
2186 {
2187 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002188 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2189 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002190 },
2191 {
2192 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002193 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2194 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002195 },
2196 {
2197 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002198 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2199 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002200 },
2201 {
2202 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002203 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2204 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002205 },
2206 {
2207 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002208 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2209 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002210 },
2211 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002212 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2213 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2214 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002215 },
2216 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002217 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2218 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2219 .speed = SPEED_25000,
2220 },
2221 {
2222 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2223 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2224 .speed = SPEED_25000,
2225 },
2226 {
2227 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2228 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2229 .speed = SPEED_25000,
2230 },
2231 {
2232 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2233 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2234 .speed = SPEED_50000,
2235 },
2236 {
2237 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2238 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2239 .speed = SPEED_50000,
2240 },
2241 {
2242 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2243 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2244 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002245 },
2246 {
2247 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002248 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2249 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002250 },
2251 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002252 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2253 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2254 .speed = SPEED_56000,
2255 },
2256 {
2257 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2258 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2259 .speed = SPEED_56000,
2260 },
2261 {
2262 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2263 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2264 .speed = SPEED_56000,
2265 },
2266 {
2267 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2268 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2269 .speed = SPEED_100000,
2270 },
2271 {
2272 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2273 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2274 .speed = SPEED_100000,
2275 },
2276 {
2277 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2278 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2279 .speed = SPEED_100000,
2280 },
2281 {
2282 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2283 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2284 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002285 },
2286};
2287
2288#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2289
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002290static void
2291mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2292 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002293{
2294 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2295 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2296 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2297 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2298 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2299 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002300 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002301
2302 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2303 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2304 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2305 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2306 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002307 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002308}
2309
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002310static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002311{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002312 int i;
2313
2314 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2315 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002316 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2317 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002318 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002319}
2320
2321static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002322 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002323{
2324 u32 speed = SPEED_UNKNOWN;
2325 u8 duplex = DUPLEX_UNKNOWN;
2326 int i;
2327
2328 if (!carrier_ok)
2329 goto out;
2330
2331 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2332 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2333 speed = mlxsw_sp_port_link_mode[i].speed;
2334 duplex = DUPLEX_FULL;
2335 break;
2336 }
2337 }
2338out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002339 cmd->base.speed = speed;
2340 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002341}
2342
2343static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2344{
2345 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2346 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2347 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2348 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2349 return PORT_FIBRE;
2350
2351 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2352 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2353 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2354 return PORT_DA;
2355
2356 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2357 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2358 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2359 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2360 return PORT_NONE;
2361
2362 return PORT_OTHER;
2363}
2364
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002365static u32
2366mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002367{
2368 u32 ptys_proto = 0;
2369 int i;
2370
2371 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002372 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2373 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002374 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2375 }
2376 return ptys_proto;
2377}
2378
2379static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2380{
2381 u32 ptys_proto = 0;
2382 int i;
2383
2384 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2385 if (speed == mlxsw_sp_port_link_mode[i].speed)
2386 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2387 }
2388 return ptys_proto;
2389}
2390
Ido Schimmel18f1e702016-02-26 17:32:31 +01002391static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2392{
2393 u32 ptys_proto = 0;
2394 int i;
2395
2396 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2397 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2398 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2399 }
2400 return ptys_proto;
2401}
2402
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002403static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2404 struct ethtool_link_ksettings *cmd)
2405{
2406 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2407 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2408 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2409
2410 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2411 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2412}
2413
2414static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2415 struct ethtool_link_ksettings *cmd)
2416{
2417 if (!autoneg)
2418 return;
2419
2420 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2421 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2422}
2423
2424static void
2425mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2426 struct ethtool_link_ksettings *cmd)
2427{
2428 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2429 return;
2430
2431 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2432 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2433}
2434
2435static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2436 struct ethtool_link_ksettings *cmd)
2437{
2438 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2439 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2440 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2441 char ptys_pl[MLXSW_REG_PTYS_LEN];
2442 u8 autoneg_status;
2443 bool autoneg;
2444 int err;
2445
2446 autoneg = mlxsw_sp_port->link.autoneg;
Tal Bar8e1ed732018-03-21 09:34:06 +02002447 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002448 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2449 if (err)
2450 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002451 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2452 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002453
2454 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2455
2456 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2457
2458 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2459 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2460 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2461
2462 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2463 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2464 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2465 cmd);
2466
2467 return 0;
2468}
2469
2470static int
2471mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2472 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002473{
2474 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2475 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2476 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002477 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002478 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002479 int err;
2480
Tal Bar8e1ed732018-03-21 09:34:06 +02002481 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002482 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002483 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002484 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002485 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002486
2487 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2488 eth_proto_new = autoneg ?
2489 mlxsw_sp_to_ptys_advert_link(cmd) :
2490 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002491
2492 eth_proto_new = eth_proto_new & eth_proto_cap;
2493 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002494 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002495 return -EINVAL;
2496 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002497
Elad Raz401c8b42016-10-28 21:35:52 +02002498 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
Tal Bar8e1ed732018-03-21 09:34:06 +02002499 eth_proto_new, autoneg);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002500 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002501 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002502 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002503
Ido Schimmel6277d462016-07-15 11:14:58 +02002504 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002505 return 0;
2506
Ido Schimmel0c83f882016-09-12 13:26:23 +02002507 mlxsw_sp_port->link.autoneg = autoneg;
2508
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002509 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2510 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002511
2512 return 0;
2513}
2514
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002515static int mlxsw_sp_flash_device(struct net_device *dev,
2516 struct ethtool_flash *flash)
2517{
2518 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2519 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2520 const struct firmware *firmware;
2521 int err;
2522
2523 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2524 return -EOPNOTSUPP;
2525
2526 dev_hold(dev);
2527 rtnl_unlock();
2528
2529 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2530 if (err)
2531 goto out;
2532 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2533 release_firmware(firmware);
2534out:
2535 rtnl_lock();
2536 dev_put(dev);
2537 return err;
2538}
2539
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002540#define MLXSW_SP_I2C_ADDR_LOW 0x50
2541#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2542#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002543
2544static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2545 u16 offset, u16 size, void *data,
2546 unsigned int *p_read_size)
2547{
2548 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2549 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2550 char mcia_pl[MLXSW_REG_MCIA_LEN];
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002551 u16 i2c_addr;
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002552 int status;
2553 int err;
2554
2555 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002556
2557 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2558 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2559 /* Cross pages read, read until offset 256 in low page */
2560 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2561
2562 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2563 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2564 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2565 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2566 }
2567
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002568 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002569 0, 0, offset, size, i2c_addr);
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002570
2571 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2572 if (err)
2573 return err;
2574
2575 status = mlxsw_reg_mcia_status_get(mcia_pl);
2576 if (status)
2577 return -EIO;
2578
2579 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2580 memcpy(data, eeprom_tmp, size);
2581 *p_read_size = size;
2582
2583 return 0;
2584}
2585
2586enum mlxsw_sp_eeprom_module_info_rev_id {
2587 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2588 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2589 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2590};
2591
2592enum mlxsw_sp_eeprom_module_info_id {
2593 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2594 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2595 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2596 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2597};
2598
2599enum mlxsw_sp_eeprom_module_info {
2600 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2601 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2602 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2603};
2604
2605static int mlxsw_sp_get_module_info(struct net_device *netdev,
2606 struct ethtool_modinfo *modinfo)
2607{
2608 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2609 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2610 u8 module_rev_id, module_id;
2611 unsigned int read_size;
2612 int err;
2613
2614 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2615 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2616 module_info, &read_size);
2617 if (err)
2618 return err;
2619
2620 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2621 return -EIO;
2622
2623 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2624 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2625
2626 switch (module_id) {
2627 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2628 modinfo->type = ETH_MODULE_SFF_8436;
2629 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2630 break;
2631 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2632 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2633 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2634 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2635 modinfo->type = ETH_MODULE_SFF_8636;
2636 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2637 } else {
2638 modinfo->type = ETH_MODULE_SFF_8436;
2639 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2640 }
2641 break;
2642 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2643 modinfo->type = ETH_MODULE_SFF_8472;
2644 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2645 break;
2646 default:
2647 return -EINVAL;
2648 }
2649
2650 return 0;
2651}
2652
2653static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2654 struct ethtool_eeprom *ee,
2655 u8 *data)
2656{
2657 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2658 int offset = ee->offset;
2659 unsigned int read_size;
2660 int i = 0;
2661 int err;
2662
2663 if (!ee->len)
2664 return -EINVAL;
2665
2666 memset(data, 0, ee->len);
2667
2668 while (i < ee->len) {
2669 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2670 ee->len - i, data + i,
2671 &read_size);
2672 if (err) {
2673 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2674 return err;
2675 }
2676
2677 i += read_size;
2678 offset += read_size;
2679 }
2680
2681 return 0;
2682}
2683
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002684static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2685 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2686 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002687 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2688 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002689 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002690 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002691 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2692 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002693 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2694 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002695 .flash_device = mlxsw_sp_flash_device,
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002696 .get_module_info = mlxsw_sp_get_module_info,
2697 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002698};
2699
Ido Schimmel18f1e702016-02-26 17:32:31 +01002700static int
2701mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2702{
2703 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2704 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2705 char ptys_pl[MLXSW_REG_PTYS_LEN];
2706 u32 eth_proto_admin;
2707
2708 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002709 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
Tal Bar8e1ed732018-03-21 09:34:06 +02002710 eth_proto_admin, mlxsw_sp_port->link.autoneg);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002711 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2712}
2713
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002714int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2715 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2716 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002717{
2718 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2719 char qeec_pl[MLXSW_REG_QEEC_LEN];
2720
2721 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2722 next_index);
2723 mlxsw_reg_qeec_de_set(qeec_pl, true);
2724 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2725 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2726 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2727}
2728
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002729int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2730 enum mlxsw_reg_qeec_hr hr, u8 index,
2731 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002732{
2733 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2734 char qeec_pl[MLXSW_REG_QEEC_LEN];
2735
2736 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2737 next_index);
2738 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2739 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2740 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2741}
2742
Petr Machata0fe64022018-10-31 09:56:44 +00002743static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port,
2744 enum mlxsw_reg_qeec_hr hr, u8 index,
2745 u8 next_index, u32 minrate)
2746{
2747 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2748 char qeec_pl[MLXSW_REG_QEEC_LEN];
2749
2750 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2751 next_index);
2752 mlxsw_reg_qeec_mise_set(qeec_pl, true);
2753 mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate);
2754
2755 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2756}
2757
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002758int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2759 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002760{
2761 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2762 char qtct_pl[MLXSW_REG_QTCT_LEN];
2763
2764 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2765 tclass);
2766 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2767}
2768
2769static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2770{
2771 int err, i;
2772
2773 /* Setup the elements hierarcy, so that each TC is linked to
2774 * one subgroup, which are all member in the same group.
2775 */
2776 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2777 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2778 0);
2779 if (err)
2780 return err;
2781 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2782 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2783 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2784 0, false, 0);
2785 if (err)
2786 return err;
2787 }
2788 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2789 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2790 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2791 false, 0);
2792 if (err)
2793 return err;
Petr Machata7b819532018-08-05 09:03:08 +03002794
2795 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2796 MLXSW_REG_QEEC_HIERARCY_TC,
2797 i + 8, i,
2798 false, 0);
2799 if (err)
2800 return err;
Ido Schimmel90183b92016-04-06 17:10:08 +02002801 }
2802
Petr Machatad0a07d62018-08-05 09:03:07 +03002803 /* Make sure the max shaper is disabled in all hierarchies that
Ido Schimmel90183b92016-04-06 17:10:08 +02002804 * support it.
2805 */
2806 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2807 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2808 MLXSW_REG_QEEC_MAS_DIS);
2809 if (err)
2810 return err;
2811 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2812 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2813 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2814 i, 0,
2815 MLXSW_REG_QEEC_MAS_DIS);
2816 if (err)
2817 return err;
2818 }
2819 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2820 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2821 MLXSW_REG_QEEC_HIERARCY_TC,
2822 i, i,
2823 MLXSW_REG_QEEC_MAS_DIS);
2824 if (err)
2825 return err;
Petr Machataa9f36652018-09-20 09:21:24 +03002826
2827 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2828 MLXSW_REG_QEEC_HIERARCY_TC,
2829 i + 8, i,
2830 MLXSW_REG_QEEC_MAS_DIS);
2831 if (err)
2832 return err;
Ido Schimmel90183b92016-04-06 17:10:08 +02002833 }
2834
Petr Machata0fe64022018-10-31 09:56:44 +00002835 /* Configure the min shaper for multicast TCs. */
2836 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2837 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port,
2838 MLXSW_REG_QEEC_HIERARCY_TC,
2839 i + 8, i,
2840 MLXSW_REG_QEEC_MIS_MIN);
2841 if (err)
2842 return err;
2843 }
2844
Ido Schimmel90183b92016-04-06 17:10:08 +02002845 /* Map all priorities to traffic class 0. */
2846 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2847 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2848 if (err)
2849 return err;
2850 }
2851
2852 return 0;
2853}
2854
Petr Machata7b819532018-08-05 09:03:08 +03002855static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
2856 bool enable)
2857{
2858 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2859 char qtctm_pl[MLXSW_REG_QTCTM_LEN];
2860
2861 mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
2862 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
2863}
2864
Ido Schimmel5b153852017-06-08 08:47:44 +02002865static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2866 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002867{
Ido Schimmelc57529e2017-05-26 08:37:31 +02002868 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002869 struct mlxsw_sp_port *mlxsw_sp_port;
2870 struct net_device *dev;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002871 int err;
2872
Ido Schimmel5b153852017-06-08 08:47:44 +02002873 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2874 if (err) {
2875 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2876 local_port);
2877 return err;
2878 }
2879
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002880 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
Ido Schimmel5b153852017-06-08 08:47:44 +02002881 if (!dev) {
2882 err = -ENOMEM;
2883 goto err_alloc_etherdev;
2884 }
Jiri Pirkof20a91f2016-10-27 15:13:00 +02002885 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002886 mlxsw_sp_port = netdev_priv(dev);
2887 mlxsw_sp_port->dev = dev;
2888 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2889 mlxsw_sp_port->local_port = local_port;
Ido Schimmelc57529e2017-05-26 08:37:31 +02002890 mlxsw_sp_port->pvid = 1;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002891 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02002892 mlxsw_sp_port->mapping.module = module;
2893 mlxsw_sp_port->mapping.width = width;
2894 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002895 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02002896 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02002897 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002898
2899 mlxsw_sp_port->pcpu_stats =
2900 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2901 if (!mlxsw_sp_port->pcpu_stats) {
2902 err = -ENOMEM;
2903 goto err_alloc_stats;
2904 }
2905
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002906 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2907 GFP_KERNEL);
2908 if (!mlxsw_sp_port->sample) {
2909 err = -ENOMEM;
2910 goto err_alloc_sample;
2911 }
2912
Nogah Frankel9deef432017-10-26 10:55:32 +02002913 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002914 &update_stats_cache);
2915
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002916 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2917 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2918
Ido Schimmel2e915e02017-06-08 08:47:45 +02002919 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
Ido Schimmel5b153852017-06-08 08:47:44 +02002920 if (err) {
2921 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2922 mlxsw_sp_port->local_port);
2923 goto err_port_module_map;
2924 }
2925
Ido Schimmel3247ff22016-09-08 08:16:02 +02002926 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2927 if (err) {
2928 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2929 mlxsw_sp_port->local_port);
2930 goto err_port_swid_set;
2931 }
2932
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002933 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2934 if (err) {
2935 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2936 mlxsw_sp_port->local_port);
2937 goto err_dev_addr_init;
2938 }
2939
2940 netif_carrier_off(dev);
2941
2942 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02002943 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2944 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002945
Jarod Wilsond894be52016-10-20 13:55:16 -04002946 dev->min_mtu = 0;
2947 dev->max_mtu = ETH_MAX_MTU;
2948
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002949 /* Each packet needs to have a Tx header (metadata) on top all other
2950 * headers.
2951 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02002952 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002953
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002954 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2955 if (err) {
2956 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2957 mlxsw_sp_port->local_port);
2958 goto err_port_system_port_mapping_set;
2959 }
2960
Ido Schimmel18f1e702016-02-26 17:32:31 +01002961 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2962 if (err) {
2963 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2964 mlxsw_sp_port->local_port);
2965 goto err_port_speed_by_width_set;
2966 }
2967
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002968 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2969 if (err) {
2970 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2971 mlxsw_sp_port->local_port);
2972 goto err_port_mtu_set;
2973 }
2974
2975 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2976 if (err)
2977 goto err_port_admin_status_set;
2978
2979 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2980 if (err) {
2981 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2982 mlxsw_sp_port->local_port);
2983 goto err_port_buffers_init;
2984 }
2985
Ido Schimmel90183b92016-04-06 17:10:08 +02002986 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2987 if (err) {
2988 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2989 mlxsw_sp_port->local_port);
2990 goto err_port_ets_init;
2991 }
2992
Petr Machata7b819532018-08-05 09:03:08 +03002993 err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
2994 if (err) {
2995 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
2996 mlxsw_sp_port->local_port);
2997 goto err_port_tc_mc_mode;
2998 }
2999
Ido Schimmelf00817d2016-04-06 17:10:09 +02003000 /* ETS and buffers must be initialized before DCB. */
3001 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
3002 if (err) {
3003 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
3004 mlxsw_sp_port->local_port);
3005 goto err_port_dcb_init;
3006 }
3007
Ido Schimmela1107482017-05-26 08:37:39 +02003008 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
Ido Schimmel45a4a162017-05-16 19:38:35 +02003009 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003010 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
Ido Schimmel45a4a162017-05-16 19:38:35 +02003011 mlxsw_sp_port->local_port);
Ido Schimmela1107482017-05-26 08:37:39 +02003012 goto err_port_fids_init;
Ido Schimmel45a4a162017-05-16 19:38:35 +02003013 }
3014
Nogah Frankel371b4372018-01-10 14:59:57 +01003015 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
3016 if (err) {
3017 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
3018 mlxsw_sp_port->local_port);
3019 goto err_port_qdiscs_init;
3020 }
3021
Ido Schimmel6e6030b2018-10-17 08:53:14 +00003022 err = mlxsw_sp_port_nve_init(mlxsw_sp_port);
3023 if (err) {
3024 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n",
3025 mlxsw_sp_port->local_port);
3026 goto err_port_nve_init;
3027 }
3028
Ido Schimmelc57529e2017-05-26 08:37:31 +02003029 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
3030 if (IS_ERR(mlxsw_sp_port_vlan)) {
3031 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
Ido Schimmel05978482016-08-17 16:39:30 +02003032 mlxsw_sp_port->local_port);
Wei Yongjund86fd112017-11-06 11:11:28 +00003033 err = PTR_ERR(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003034 goto err_port_vlan_get;
Ido Schimmel05978482016-08-17 16:39:30 +02003035 }
3036
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003037 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02003038 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003039 err = register_netdev(dev);
3040 if (err) {
3041 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3042 mlxsw_sp_port->local_port);
3043 goto err_register_netdev;
3044 }
3045
Elad Razd808c7e2016-10-28 21:35:57 +02003046 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
Jiri Pirkob9ffcba2018-05-18 09:29:00 +02003047 mlxsw_sp_port, dev, module + 1,
3048 mlxsw_sp_port->split, lane / width);
Nogah Frankel9deef432017-10-26 10:55:32 +02003049 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003050 return 0;
3051
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003052err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02003053 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02003054 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003055 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
3056err_port_vlan_get:
Ido Schimmel6e6030b2018-10-17 08:53:14 +00003057 mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3058err_port_nve_init:
Nogah Frankel371b4372018-01-10 14:59:57 +01003059 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3060err_port_qdiscs_init:
Ido Schimmela1107482017-05-26 08:37:39 +02003061 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3062err_port_fids_init:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03003063 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02003064err_port_dcb_init:
Petr Machata7b819532018-08-05 09:03:08 +03003065 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3066err_port_tc_mc_mode:
Ido Schimmel90183b92016-04-06 17:10:08 +02003067err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003068err_port_buffers_init:
3069err_port_admin_status_set:
3070err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01003071err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003072err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003073err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02003074 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3075err_port_swid_set:
Ido Schimmel2e915e02017-06-08 08:47:45 +02003076 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Ido Schimmel5b153852017-06-08 08:47:44 +02003077err_port_module_map:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003078 kfree(mlxsw_sp_port->sample);
3079err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003080 free_percpu(mlxsw_sp_port->pcpu_stats);
3081err_alloc_stats:
3082 free_netdev(dev);
Ido Schimmel5b153852017-06-08 08:47:44 +02003083err_alloc_etherdev:
Jiri Pirko67963a32016-10-28 21:35:55 +02003084 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3085 return err;
3086}
3087
Ido Schimmel5b153852017-06-08 08:47:44 +02003088static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003089{
3090 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3091
Nogah Frankel9deef432017-10-26 10:55:32 +02003092 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02003093 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003094 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02003095 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02003096 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003097 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmel6e6030b2018-10-17 08:53:14 +00003098 mlxsw_sp_port_nve_fini(mlxsw_sp_port);
Nogah Frankel371b4372018-01-10 14:59:57 +01003099 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
Ido Schimmela1107482017-05-26 08:37:39 +02003100 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02003101 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Petr Machata7b819532018-08-05 09:03:08 +03003102 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01003103 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
Ido Schimmel2e915e02017-06-08 08:47:45 +02003104 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003105 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01003106 free_percpu(mlxsw_sp_port->pcpu_stats);
Ido Schimmel31a08a52017-05-26 08:37:26 +02003107 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003108 free_netdev(mlxsw_sp_port->dev);
Jiri Pirko67963a32016-10-28 21:35:55 +02003109 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3110}
3111
Jiri Pirkof83e2102016-10-28 21:35:49 +02003112static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3113{
3114 return mlxsw_sp->ports[local_port] != NULL;
3115}
3116
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003117static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3118{
3119 int i;
3120
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003121 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003122 if (mlxsw_sp_port_created(mlxsw_sp, i))
3123 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003124 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003125 kfree(mlxsw_sp->ports);
3126}
3127
3128static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3129{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003130 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02003131 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003132 size_t alloc_size;
3133 int i;
3134 int err;
3135
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003136 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003137 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3138 if (!mlxsw_sp->ports)
3139 return -ENOMEM;
3140
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003141 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3142 GFP_KERNEL);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003143 if (!mlxsw_sp->port_to_module) {
3144 err = -ENOMEM;
3145 goto err_port_to_module_alloc;
3146 }
3147
3148 for (i = 1; i < max_ports; i++) {
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003149 /* Mark as invalid */
3150 mlxsw_sp->port_to_module[i] = -1;
3151
Ido Schimmel558c2d52016-02-26 17:32:29 +01003152 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003153 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01003154 if (err)
3155 goto err_port_module_info_get;
3156 if (!width)
3157 continue;
3158 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02003159 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3160 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003161 if (err)
3162 goto err_port_create;
3163 }
3164 return 0;
3165
3166err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01003167err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003168 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003169 if (mlxsw_sp_port_created(mlxsw_sp, i))
3170 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003171 kfree(mlxsw_sp->port_to_module);
3172err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003173 kfree(mlxsw_sp->ports);
3174 return err;
3175}
3176
Ido Schimmel18f1e702016-02-26 17:32:31 +01003177static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3178{
3179 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3180
3181 return local_port - offset;
3182}
3183
Ido Schimmelbe945352016-06-09 09:51:39 +02003184static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3185 u8 module, unsigned int count)
3186{
3187 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3188 int err, i;
3189
3190 for (i = 0; i < count; i++) {
Ido Schimmelbe945352016-06-09 09:51:39 +02003191 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02003192 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02003193 if (err)
3194 goto err_port_create;
3195 }
3196
3197 return 0;
3198
3199err_port_create:
3200 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003201 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3202 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02003203 return err;
3204}
3205
3206static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3207 u8 base_port, unsigned int count)
3208{
3209 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3210 int i;
3211
3212 /* Split by four means we need to re-create two ports, otherwise
3213 * only one.
3214 */
3215 count = count / 2;
3216
3217 for (i = 0; i < count; i++) {
3218 local_port = base_port + i * 2;
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003219 if (mlxsw_sp->port_to_module[local_port] < 0)
3220 continue;
Ido Schimmelbe945352016-06-09 09:51:39 +02003221 module = mlxsw_sp->port_to_module[local_port];
3222
Ido Schimmelbe945352016-06-09 09:51:39 +02003223 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003224 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003225 }
3226}
3227
Jiri Pirkob2f10572016-04-08 19:11:23 +02003228static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
David Ahern3fcc7732018-06-05 08:14:11 -07003229 unsigned int count,
3230 struct netlink_ext_ack *extack)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003231{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003232 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003233 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003234 u8 module, cur_width, base_port;
3235 int i;
3236 int err;
3237
3238 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3239 if (!mlxsw_sp_port) {
3240 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3241 local_port);
David Ahern3fcc7732018-06-05 08:14:11 -07003242 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003243 return -EINVAL;
3244 }
3245
Ido Schimmeld664b412016-06-09 09:51:40 +02003246 module = mlxsw_sp_port->mapping.module;
3247 cur_width = mlxsw_sp_port->mapping.width;
3248
Ido Schimmel18f1e702016-02-26 17:32:31 +01003249 if (count != 2 && count != 4) {
3250 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
David Ahern3fcc7732018-06-05 08:14:11 -07003251 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003252 return -EINVAL;
3253 }
3254
Ido Schimmel18f1e702016-02-26 17:32:31 +01003255 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3256 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
David Ahern3fcc7732018-06-05 08:14:11 -07003257 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003258 return -EINVAL;
3259 }
3260
3261 /* Make sure we have enough slave (even) ports for the split. */
3262 if (count == 2) {
3263 base_port = local_port;
3264 if (mlxsw_sp->ports[base_port + 1]) {
3265 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
David Ahern3fcc7732018-06-05 08:14:11 -07003266 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003267 return -EINVAL;
3268 }
3269 } else {
3270 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3271 if (mlxsw_sp->ports[base_port + 1] ||
3272 mlxsw_sp->ports[base_port + 3]) {
3273 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
David Ahern3fcc7732018-06-05 08:14:11 -07003274 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003275 return -EINVAL;
3276 }
3277 }
3278
3279 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003280 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3281 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003282
Ido Schimmelbe945352016-06-09 09:51:39 +02003283 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3284 if (err) {
3285 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3286 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003287 }
3288
3289 return 0;
3290
Ido Schimmelbe945352016-06-09 09:51:39 +02003291err_port_split_create:
3292 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003293 return err;
3294}
3295
David Ahern3fcc7732018-06-05 08:14:11 -07003296static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port,
3297 struct netlink_ext_ack *extack)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003298{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003299 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003300 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003301 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003302 unsigned int count;
3303 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003304
3305 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3306 if (!mlxsw_sp_port) {
3307 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3308 local_port);
David Ahern3fcc7732018-06-05 08:14:11 -07003309 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003310 return -EINVAL;
3311 }
3312
3313 if (!mlxsw_sp_port->split) {
David Ahern3fcc7732018-06-05 08:14:11 -07003314 netdev_err(mlxsw_sp_port->dev, "Port was not split\n");
3315 NL_SET_ERR_MSG_MOD(extack, "Port was not split");
Ido Schimmel18f1e702016-02-26 17:32:31 +01003316 return -EINVAL;
3317 }
3318
Ido Schimmeld664b412016-06-09 09:51:40 +02003319 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003320 count = cur_width == 1 ? 4 : 2;
3321
3322 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3323
3324 /* Determine which ports to remove. */
3325 if (count == 2 && local_port >= base_port + 2)
3326 base_port = base_port + 2;
3327
3328 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003329 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3330 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003331
Ido Schimmelbe945352016-06-09 09:51:39 +02003332 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003333
3334 return 0;
3335}
3336
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003337static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3338 char *pude_pl, void *priv)
3339{
3340 struct mlxsw_sp *mlxsw_sp = priv;
3341 struct mlxsw_sp_port *mlxsw_sp_port;
3342 enum mlxsw_reg_pude_oper_status status;
3343 u8 local_port;
3344
3345 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3346 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003347 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003348 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003349
3350 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3351 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3352 netdev_info(mlxsw_sp_port->dev, "link up\n");
3353 netif_carrier_on(mlxsw_sp_port->dev);
3354 } else {
3355 netdev_info(mlxsw_sp_port->dev, "link down\n");
3356 netif_carrier_off(mlxsw_sp_port->dev);
3357 }
3358}
3359
Nogah Frankel14eeda92016-11-25 10:33:32 +01003360static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3361 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003362{
3363 struct mlxsw_sp *mlxsw_sp = priv;
3364 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3365 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3366
3367 if (unlikely(!mlxsw_sp_port)) {
3368 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3369 local_port);
3370 return;
3371 }
3372
3373 skb->dev = mlxsw_sp_port->dev;
3374
3375 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3376 u64_stats_update_begin(&pcpu_stats->syncp);
3377 pcpu_stats->rx_packets++;
3378 pcpu_stats->rx_bytes += skb->len;
3379 u64_stats_update_end(&pcpu_stats->syncp);
3380
3381 skb->protocol = eth_type_trans(skb, skb->dev);
3382 netif_receive_skb(skb);
3383}
3384
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003385static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3386 void *priv)
3387{
3388 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003389 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003390}
3391
Yotam Gigia0040c82017-10-03 09:58:10 +02003392static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3393 u8 local_port, void *priv)
3394{
3395 skb->offload_mr_fwd_mark = 1;
3396 skb->offload_fwd_mark = 1;
3397 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3398}
3399
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003400static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3401 void *priv)
3402{
3403 struct mlxsw_sp *mlxsw_sp = priv;
3404 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3405 struct psample_group *psample_group;
3406 u32 size;
3407
3408 if (unlikely(!mlxsw_sp_port)) {
3409 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3410 local_port);
3411 goto out;
3412 }
3413 if (unlikely(!mlxsw_sp_port->sample)) {
3414 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3415 local_port);
3416 goto out;
3417 }
3418
3419 size = mlxsw_sp_port->sample->truncate ?
3420 mlxsw_sp_port->sample->trunc_size : skb->len;
3421
3422 rcu_read_lock();
3423 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3424 if (!psample_group)
3425 goto out_unlock;
3426 psample_sample_packet(psample_group, skb, size,
3427 mlxsw_sp_port->dev->ifindex, 0,
3428 mlxsw_sp_port->sample->rate);
3429out_unlock:
3430 rcu_read_unlock();
3431out:
3432 consume_skb(skb);
3433}
3434
Nogah Frankel117b0da2016-11-25 10:33:44 +01003435#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003436 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003437 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003438
Nogah Frankel117b0da2016-11-25 10:33:44 +01003439#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003440 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003441 _is_ctrl, SP_##_trap_group, DISCARD)
3442
Yotam Gigia0040c82017-10-03 09:58:10 +02003443#define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3444 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3445 _is_ctrl, SP_##_trap_group, DISCARD)
3446
Nogah Frankel117b0da2016-11-25 10:33:44 +01003447#define MLXSW_SP_EVENTL(_func, _trap_id) \
3448 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003449
Nogah Frankel45449132016-11-25 10:33:35 +01003450static const struct mlxsw_listener mlxsw_sp_listener[] = {
3451 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003452 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003453 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003454 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3455 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3456 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3457 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3458 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3459 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3460 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3461 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3462 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3463 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3464 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003465 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003466 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3467 false),
3468 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3469 false),
3470 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3471 false),
3472 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3473 false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003474 /* L3 traps */
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003475 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3476 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3477 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003478 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003479 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3480 false),
3481 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3482 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3483 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3484 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3485 false),
3486 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3487 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3488 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003489 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003490 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3491 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3492 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3493 false),
3494 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3495 false),
3496 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3497 false),
3498 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3499 false),
3500 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3501 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3502 false),
3503 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3504 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
Ido Schimmel7607dd32017-07-17 14:15:30 +02003505 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003506 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
Petr Machata86484de2017-09-02 23:49:27 +02003507 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Ido Schimmelb02597d2018-10-11 07:48:11 +00003508 MLXSW_SP_RXL_MARK(DECAP_ECN0, TRAP_TO_CPU, ROUTER_EXP, false),
Ido Schimmel11566d32018-07-14 11:39:53 +03003509 MLXSW_SP_RXL_MARK(IPV4_VRRP, TRAP_TO_CPU, ROUTER_EXP, false),
3510 MLXSW_SP_RXL_MARK(IPV6_VRRP, TRAP_TO_CPU, ROUTER_EXP, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003511 /* PKT Sample trap */
3512 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
Jiri Pirko0db7b382017-06-06 14:12:05 +02003513 false, SP_IP2ME, DISCARD),
3514 /* ACL trap */
3515 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
Yotam Gigib48cfc82017-09-19 10:00:20 +02003516 /* Multicast Router Traps */
3517 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
Yuval Mintz6a170d32018-03-26 15:01:45 +03003518 MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false),
Yotam Gigib48cfc82017-09-19 10:00:20 +02003519 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3520 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
Yotam Gigia0040c82017-10-03 09:58:10 +02003521 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
Ido Schimmelb02597d2018-10-11 07:48:11 +00003522 /* NVE traps */
3523 MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, ARP, false),
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003524};
3525
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003526static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3527{
3528 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3529 enum mlxsw_reg_qpcr_ir_units ir_units;
3530 int max_cpu_policers;
3531 bool is_bytes;
3532 u8 burst_size;
3533 u32 rate;
3534 int i, err;
3535
3536 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3537 return -EIO;
3538
3539 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3540
3541 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3542 for (i = 0; i < max_cpu_policers; i++) {
3543 is_bytes = false;
3544 switch (i) {
3545 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3546 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3547 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3548 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003549 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3550 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003551 rate = 128;
3552 burst_size = 7;
3553 break;
3554 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003555 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003556 rate = 16 * 1024;
3557 burst_size = 10;
3558 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003559 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003560 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3561 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003562 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003563 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3564 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003565 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003566 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003567 rate = 1024;
3568 burst_size = 7;
3569 break;
3570 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003571 rate = 4 * 1024;
3572 burst_size = 4;
3573 break;
3574 default:
3575 continue;
3576 }
3577
3578 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3579 burst_size);
3580 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3581 if (err)
3582 return err;
3583 }
3584
3585 return 0;
3586}
3587
Nogah Frankel579c82e2016-11-25 10:33:42 +01003588static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003589{
3590 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003591 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003592 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003593 int max_trap_groups;
3594 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003595 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003596 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003597
3598 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3599 return -EIO;
3600
3601 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003602 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003603
3604 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003605 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003606 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003607 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3608 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3609 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3610 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003611 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003612 priority = 5;
3613 tc = 5;
3614 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003615 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003616 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3617 priority = 4;
3618 tc = 4;
3619 break;
3620 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3621 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003622 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003623 priority = 3;
3624 tc = 3;
3625 break;
3626 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003627 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003628 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003629 priority = 2;
3630 tc = 2;
3631 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003632 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003633 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3634 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003635 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003636 priority = 1;
3637 tc = 1;
3638 break;
3639 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003640 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3641 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003642 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003643 break;
3644 default:
3645 continue;
3646 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003647
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003648 if (max_cpu_policers <= policer_id &&
3649 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3650 return -EIO;
3651
3652 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003653 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3654 if (err)
3655 return err;
3656 }
3657
3658 return 0;
3659}
3660
3661static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3662{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003663 int i;
3664 int err;
3665
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003666 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3667 if (err)
3668 return err;
3669
Nogah Frankel579c82e2016-11-25 10:33:42 +01003670 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003671 if (err)
3672 return err;
3673
Nogah Frankel45449132016-11-25 10:33:35 +01003674 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003675 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003676 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003677 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003678 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003679 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003680
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003681 }
3682 return 0;
3683
Nogah Frankel45449132016-11-25 10:33:35 +01003684err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003685 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003686 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003687 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003688 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003689 }
3690 return err;
3691}
3692
3693static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3694{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003695 int i;
3696
Nogah Frankel45449132016-11-25 10:33:35 +01003697 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003698 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003699 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003700 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003701 }
3702}
3703
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003704static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3705{
3706 char slcr_pl[MLXSW_REG_SLCR_LEN];
Ido Schimmelbeda7f72018-10-11 07:47:57 +00003707 u32 seed;
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003708 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003709
Ido Schimmelbeda7f72018-10-11 07:47:57 +00003710 get_random_bytes(&seed, sizeof(seed));
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003711 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3712 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3713 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3714 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3715 MLXSW_REG_SLCR_LAG_HASH_SIP |
3716 MLXSW_REG_SLCR_LAG_HASH_DIP |
3717 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3718 MLXSW_REG_SLCR_LAG_HASH_DPORT |
Ido Schimmelbeda7f72018-10-11 07:47:57 +00003719 MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003720 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3721 if (err)
3722 return err;
3723
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003724 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3725 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003726 return -EIO;
3727
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003728 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003729 sizeof(struct mlxsw_sp_upper),
3730 GFP_KERNEL);
3731 if (!mlxsw_sp->lags)
3732 return -ENOMEM;
3733
3734 return 0;
3735}
3736
3737static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3738{
3739 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003740}
3741
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003742static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3743{
3744 char htgt_pl[MLXSW_REG_HTGT_LEN];
3745
Nogah Frankel579c82e2016-11-25 10:33:42 +01003746 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3747 MLXSW_REG_HTGT_INVALID_POLICER,
3748 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3749 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003750 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3751}
3752
Petr Machatac30f5d02017-10-16 16:26:35 +02003753static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3754 unsigned long event, void *ptr);
3755
Jiri Pirkob2f10572016-04-08 19:11:23 +02003756static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003757 const struct mlxsw_bus_info *mlxsw_bus_info)
3758{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003759 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003760 int err;
3761
3762 mlxsw_sp->core = mlxsw_core;
3763 mlxsw_sp->bus_info = mlxsw_bus_info;
3764
Yotam Gigi6b742192017-05-23 21:56:29 +02003765 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
Jiri Pirkoc86d62c2018-08-09 11:59:09 +03003766 if (err)
Yotam Gigi6b742192017-05-23 21:56:29 +02003767 return err;
Yotam Gigi6b742192017-05-23 21:56:29 +02003768
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003769 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3770 if (err) {
3771 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3772 return err;
3773 }
3774
Ido Schimmela875a2e2017-10-22 23:11:44 +02003775 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3776 if (err) {
3777 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3778 return err;
3779 }
3780
Ido Schimmela1107482017-05-26 08:37:39 +02003781 err = mlxsw_sp_fids_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003782 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003783 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
Ido Schimmela875a2e2017-10-22 23:11:44 +02003784 goto err_fids_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003785 }
3786
Ido Schimmela1107482017-05-26 08:37:39 +02003787 err = mlxsw_sp_traps_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003788 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003789 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3790 goto err_traps_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003791 }
3792
3793 err = mlxsw_sp_buffers_init(mlxsw_sp);
3794 if (err) {
3795 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3796 goto err_buffers_init;
3797 }
3798
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003799 err = mlxsw_sp_lag_init(mlxsw_sp);
3800 if (err) {
3801 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3802 goto err_lag_init;
3803 }
3804
Petr Machatacda880de2018-04-29 10:56:11 +03003805 /* Initialize SPAN before router and switchdev, so that those components
3806 * can call mlxsw_sp_span_respin().
3807 */
3808 err = mlxsw_sp_span_init(mlxsw_sp);
3809 if (err) {
3810 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3811 goto err_span_init;
3812 }
3813
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003814 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3815 if (err) {
3816 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3817 goto err_switchdev_init;
3818 }
3819
Yotam Gigie2b2d352017-09-19 10:00:08 +02003820 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3821 if (err) {
3822 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3823 goto err_counter_pool_init;
3824 }
3825
Yotam Gigid3b939b2017-09-19 10:00:09 +02003826 err = mlxsw_sp_afa_init(mlxsw_sp);
3827 if (err) {
3828 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3829 goto err_afa_init;
3830 }
3831
Ido Schimmel6e6030b2018-10-17 08:53:14 +00003832 err = mlxsw_sp_nve_init(mlxsw_sp);
3833 if (err) {
3834 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n");
3835 goto err_nve_init;
3836 }
3837
Ido Schimmel464dce12016-07-02 11:00:15 +02003838 err = mlxsw_sp_router_init(mlxsw_sp);
3839 if (err) {
3840 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3841 goto err_router_init;
3842 }
3843
Petr Machata803335a2018-02-27 14:53:46 +01003844 /* Initialize netdevice notifier after router and SPAN is initialized,
3845 * so that the event handler can use router structures and call SPAN
3846 * respin.
Petr Machatac30f5d02017-10-16 16:26:35 +02003847 */
3848 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3849 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3850 if (err) {
3851 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3852 goto err_netdev_notifier;
3853 }
3854
Jiri Pirko22a67762017-02-03 10:29:07 +01003855 err = mlxsw_sp_acl_init(mlxsw_sp);
3856 if (err) {
3857 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3858 goto err_acl_init;
3859 }
3860
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003861 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3862 if (err) {
3863 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3864 goto err_dpipe_init;
3865 }
3866
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003867 err = mlxsw_sp_ports_create(mlxsw_sp);
3868 if (err) {
3869 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3870 goto err_ports_create;
3871 }
3872
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003873 return 0;
3874
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003875err_ports_create:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003876 mlxsw_sp_dpipe_fini(mlxsw_sp);
3877err_dpipe_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01003878 mlxsw_sp_acl_fini(mlxsw_sp);
3879err_acl_init:
Petr Machatac30f5d02017-10-16 16:26:35 +02003880 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3881err_netdev_notifier:
Ido Schimmel464dce12016-07-02 11:00:15 +02003882 mlxsw_sp_router_fini(mlxsw_sp);
3883err_router_init:
Ido Schimmel6e6030b2018-10-17 08:53:14 +00003884 mlxsw_sp_nve_fini(mlxsw_sp);
3885err_nve_init:
Yotam Gigid3b939b2017-09-19 10:00:09 +02003886 mlxsw_sp_afa_fini(mlxsw_sp);
3887err_afa_init:
Yotam Gigie2b2d352017-09-19 10:00:08 +02003888 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3889err_counter_pool_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003890 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003891err_switchdev_init:
Petr Machatacda880de2018-04-29 10:56:11 +03003892 mlxsw_sp_span_fini(mlxsw_sp);
3893err_span_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003894 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003895err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02003896 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003897err_buffers_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003898 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003899err_traps_init:
3900 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003901err_fids_init:
3902 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003903 return err;
3904}
3905
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03003906static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
3907 const struct mlxsw_bus_info *mlxsw_bus_info)
3908{
3909 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3910
3911 mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev;
3912 mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME;
3913 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
3914 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
3915 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
3916 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
3917 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
Ido Schimmel6e6030b2018-10-17 08:53:14 +00003918 mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr;
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03003919
3920 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
3921}
3922
3923static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
3924 const struct mlxsw_bus_info *mlxsw_bus_info)
3925{
3926 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3927
3928 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
3929 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
3930 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
3931 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
3932 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
Ido Schimmel6e6030b2018-10-17 08:53:14 +00003933 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03003934
3935 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
3936}
3937
Jiri Pirkob2f10572016-04-08 19:11:23 +02003938static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003939{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003940 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003941
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003942 mlxsw_sp_ports_remove(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003943 mlxsw_sp_dpipe_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01003944 mlxsw_sp_acl_fini(mlxsw_sp);
Petr Machatac30f5d02017-10-16 16:26:35 +02003945 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
Ido Schimmel464dce12016-07-02 11:00:15 +02003946 mlxsw_sp_router_fini(mlxsw_sp);
Ido Schimmel6e6030b2018-10-17 08:53:14 +00003947 mlxsw_sp_nve_fini(mlxsw_sp);
Yotam Gigid3b939b2017-09-19 10:00:09 +02003948 mlxsw_sp_afa_fini(mlxsw_sp);
Yotam Gigie2b2d352017-09-19 10:00:08 +02003949 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003950 mlxsw_sp_switchdev_fini(mlxsw_sp);
Petr Machatacda880de2018-04-29 10:56:11 +03003951 mlxsw_sp_span_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003952 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02003953 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003954 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003955 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003956 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003957}
3958
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03003959static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003960 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01003961 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003962 .used_flood_tables = 1,
3963 .used_flood_mode = 1,
3964 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003965 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003966 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003967 .max_fid_flood_tables = 3,
Ido Schimmela1107482017-05-26 08:37:39 +02003968 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003969 .used_max_ib_mc = 1,
3970 .max_ib_mc = 0,
3971 .used_max_pkey = 1,
3972 .max_pkey = 0,
Jiri Pirko110d2d22018-04-01 17:34:56 +03003973 .used_kvd_sizes = 1,
Ido Schimmelf11fbaf2017-10-22 23:11:49 +02003974 .kvd_hash_single_parts = 59,
3975 .kvd_hash_double_parts = 41,
Jiri Pirkoc6022422016-07-05 11:27:46 +02003976 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003977 .swid_config = {
3978 {
3979 .used_type = 1,
3980 .type = MLXSW_PORT_SWID_TYPE_ETH,
3981 }
3982 },
3983};
3984
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03003985static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
3986 .used_max_mid = 1,
3987 .max_mid = MLXSW_SP_MID_MAX,
3988 .used_flood_tables = 1,
3989 .used_flood_mode = 1,
3990 .flood_mode = 3,
3991 .max_fid_offset_flood_tables = 3,
3992 .fid_offset_flood_table_size = VLAN_N_VID - 1,
3993 .max_fid_flood_tables = 3,
3994 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
3995 .used_max_ib_mc = 1,
3996 .max_ib_mc = 0,
3997 .used_max_pkey = 1,
3998 .max_pkey = 0,
3999 .swid_config = {
4000 {
4001 .used_type = 1,
4002 .type = MLXSW_PORT_SWID_TYPE_ETH,
4003 }
4004 },
4005};
4006
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004007static void
Jiri Pirko77d27092018-02-28 13:12:09 +01004008mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
4009 struct devlink_resource_size_params *kvd_size_params,
4010 struct devlink_resource_size_params *linear_size_params,
4011 struct devlink_resource_size_params *hash_double_size_params,
4012 struct devlink_resource_size_params *hash_single_size_params)
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004013{
4014 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
4015 KVD_SINGLE_MIN_SIZE);
4016 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
4017 KVD_DOUBLE_MIN_SIZE);
4018 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4019 u32 linear_size_min = 0;
4020
Jiri Pirko77d27092018-02-28 13:12:09 +01004021 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
4022 MLXSW_SP_KVD_GRANULARITY,
4023 DEVLINK_RESOURCE_UNIT_ENTRY);
4024 devlink_resource_size_params_init(linear_size_params, linear_size_min,
4025 kvd_size - single_size_min -
4026 double_size_min,
4027 MLXSW_SP_KVD_GRANULARITY,
4028 DEVLINK_RESOURCE_UNIT_ENTRY);
4029 devlink_resource_size_params_init(hash_double_size_params,
4030 double_size_min,
4031 kvd_size - single_size_min -
4032 linear_size_min,
4033 MLXSW_SP_KVD_GRANULARITY,
4034 DEVLINK_RESOURCE_UNIT_ENTRY);
4035 devlink_resource_size_params_init(hash_single_size_params,
4036 single_size_min,
4037 kvd_size - double_size_min -
4038 linear_size_min,
4039 MLXSW_SP_KVD_GRANULARITY,
4040 DEVLINK_RESOURCE_UNIT_ENTRY);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004041}
4042
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03004043static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004044{
4045 struct devlink *devlink = priv_to_devlink(mlxsw_core);
Jiri Pirko77d27092018-02-28 13:12:09 +01004046 struct devlink_resource_size_params hash_single_size_params;
4047 struct devlink_resource_size_params hash_double_size_params;
4048 struct devlink_resource_size_params linear_size_params;
4049 struct devlink_resource_size_params kvd_size_params;
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004050 u32 kvd_size, single_size, double_size, linear_size;
4051 const struct mlxsw_config_profile *profile;
4052 int err;
4053
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03004054 profile = &mlxsw_sp1_config_profile;
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004055 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
4056 return -EIO;
4057
Jiri Pirko77d27092018-02-28 13:12:09 +01004058 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
4059 &linear_size_params,
4060 &hash_double_size_params,
4061 &hash_single_size_params);
4062
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004063 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4064 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
David Ahern14530742018-03-20 19:31:14 -07004065 kvd_size, MLXSW_SP_RESOURCE_KVD,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004066 DEVLINK_RESOURCE_ID_PARENT_TOP,
Jiri Pirkofc56be42018-04-05 22:13:21 +02004067 &kvd_size_params);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004068 if (err)
4069 return err;
4070
4071 linear_size = profile->kvd_linear_size;
4072 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
David Ahern14530742018-03-20 19:31:14 -07004073 linear_size,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004074 MLXSW_SP_RESOURCE_KVD_LINEAR,
4075 MLXSW_SP_RESOURCE_KVD,
Jiri Pirkofc56be42018-04-05 22:13:21 +02004076 &linear_size_params);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004077 if (err)
4078 return err;
4079
Jiri Pirkoebcff742018-07-08 23:51:16 +03004080 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
Arkadi Sharshevsky51d3c082018-02-20 08:44:22 +01004081 if (err)
4082 return err;
4083
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004084 double_size = kvd_size - linear_size;
4085 double_size *= profile->kvd_hash_double_parts;
4086 double_size /= profile->kvd_hash_double_parts +
4087 profile->kvd_hash_single_parts;
Jiri Pirko72779c92018-04-01 17:34:54 +03004088 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004089 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
David Ahern14530742018-03-20 19:31:14 -07004090 double_size,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004091 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4092 MLXSW_SP_RESOURCE_KVD,
Jiri Pirkofc56be42018-04-05 22:13:21 +02004093 &hash_double_size_params);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004094 if (err)
4095 return err;
4096
4097 single_size = kvd_size - double_size - linear_size;
4098 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
David Ahern14530742018-03-20 19:31:14 -07004099 single_size,
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004100 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4101 MLXSW_SP_RESOURCE_KVD,
Jiri Pirkofc56be42018-04-05 22:13:21 +02004102 &hash_single_size_params);
Arkadi Sharshevskyef3116e2018-01-15 08:59:07 +01004103 if (err)
4104 return err;
4105
4106 return 0;
4107}
4108
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03004109static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
4110{
4111 return mlxsw_sp1_resources_kvd_register(mlxsw_core);
4112}
4113
4114static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
4115{
4116 return 0;
4117}
4118
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01004119static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
4120 const struct mlxsw_config_profile *profile,
4121 u64 *p_single_size, u64 *p_double_size,
4122 u64 *p_linear_size)
4123{
4124 struct devlink *devlink = priv_to_devlink(mlxsw_core);
4125 u32 double_size;
4126 int err;
4127
4128 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
Jiri Pirko110d2d22018-04-01 17:34:56 +03004129 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01004130 return -EIO;
4131
4132 /* The hash part is what left of the kvd without the
4133 * linear part. It is split to the single size and
4134 * double size by the parts ratio from the profile.
4135 * Both sizes must be a multiplications of the
4136 * granularity from the profile. In case the user
4137 * provided the sizes they are obtained via devlink.
4138 */
4139 err = devlink_resource_size_get(devlink,
4140 MLXSW_SP_RESOURCE_KVD_LINEAR,
4141 p_linear_size);
4142 if (err)
4143 *p_linear_size = profile->kvd_linear_size;
4144
4145 err = devlink_resource_size_get(devlink,
4146 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4147 p_double_size);
4148 if (err) {
4149 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4150 *p_linear_size;
4151 double_size *= profile->kvd_hash_double_parts;
4152 double_size /= profile->kvd_hash_double_parts +
4153 profile->kvd_hash_single_parts;
4154 *p_double_size = rounddown(double_size,
Jiri Pirko72779c92018-04-01 17:34:54 +03004155 MLXSW_SP_KVD_GRANULARITY);
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01004156 }
4157
4158 err = devlink_resource_size_get(devlink,
4159 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4160 p_single_size);
4161 if (err)
4162 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4163 *p_double_size - *p_linear_size;
4164
4165 /* Check results are legal. */
4166 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4167 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
4168 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
4169 return -EIO;
4170
4171 return 0;
4172}
4173
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03004174static struct mlxsw_driver mlxsw_sp1_driver = {
4175 .kind = mlxsw_sp1_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02004176 .priv_size = sizeof(struct mlxsw_sp),
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03004177 .init = mlxsw_sp1_init,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02004178 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01004179 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02004180 .port_split = mlxsw_sp_port_split,
4181 .port_unsplit = mlxsw_sp_port_unsplit,
4182 .sb_pool_get = mlxsw_sp_sb_pool_get,
4183 .sb_pool_set = mlxsw_sp_sb_pool_set,
4184 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
4185 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
4186 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
4187 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4188 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4189 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4190 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4191 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4192 .txhdr_construct = mlxsw_sp_txhdr_construct,
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03004193 .resources_register = mlxsw_sp1_resources_register,
Arkadi Sharshevskye21d21c2018-01-15 08:59:10 +01004194 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02004195 .txhdr_len = MLXSW_TXHDR_LEN,
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03004196 .profile = &mlxsw_sp1_config_profile,
4197 .res_query_enabled = true,
4198};
4199
4200static struct mlxsw_driver mlxsw_sp2_driver = {
4201 .kind = mlxsw_sp2_driver_name,
4202 .priv_size = sizeof(struct mlxsw_sp),
4203 .init = mlxsw_sp2_init,
4204 .fini = mlxsw_sp_fini,
4205 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
4206 .port_split = mlxsw_sp_port_split,
4207 .port_unsplit = mlxsw_sp_port_unsplit,
4208 .sb_pool_get = mlxsw_sp_sb_pool_get,
4209 .sb_pool_set = mlxsw_sp_sb_pool_set,
4210 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
4211 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
4212 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
4213 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4214 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4215 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4216 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4217 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4218 .txhdr_construct = mlxsw_sp_txhdr_construct,
4219 .resources_register = mlxsw_sp2_resources_register,
4220 .txhdr_len = MLXSW_TXHDR_LEN,
4221 .profile = &mlxsw_sp2_config_profile,
Jiri Pirkoad3f20b2018-04-01 17:34:57 +03004222 .res_query_enabled = true,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004223};
4224
Jiri Pirko22a67762017-02-03 10:29:07 +01004225bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004226{
4227 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4228}
4229
Jiri Pirko1182e532017-03-06 21:25:20 +01004230static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07004231{
Jiri Pirko1182e532017-03-06 21:25:20 +01004232 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07004233 int ret = 0;
4234
4235 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01004236 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07004237 ret = 1;
4238 }
4239
4240 return ret;
4241}
4242
Ido Schimmelc57529e2017-05-26 08:37:31 +02004243struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004244{
Jiri Pirko1182e532017-03-06 21:25:20 +01004245 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004246
4247 if (mlxsw_sp_port_dev_check(dev))
4248 return netdev_priv(dev);
4249
Jiri Pirko1182e532017-03-06 21:25:20 +01004250 mlxsw_sp_port = NULL;
4251 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004252
Jiri Pirko1182e532017-03-06 21:25:20 +01004253 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004254}
4255
Ido Schimmel4724ba562017-03-10 08:53:39 +01004256struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004257{
4258 struct mlxsw_sp_port *mlxsw_sp_port;
4259
4260 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4261 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4262}
4263
Arkadi Sharshevskyaf0613782017-06-08 08:44:20 +02004264struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004265{
Jiri Pirko1182e532017-03-06 21:25:20 +01004266 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004267
4268 if (mlxsw_sp_port_dev_check(dev))
4269 return netdev_priv(dev);
4270
Jiri Pirko1182e532017-03-06 21:25:20 +01004271 mlxsw_sp_port = NULL;
4272 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4273 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004274
Jiri Pirko1182e532017-03-06 21:25:20 +01004275 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004276}
4277
4278struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4279{
4280 struct mlxsw_sp_port *mlxsw_sp_port;
4281
4282 rcu_read_lock();
4283 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4284 if (mlxsw_sp_port)
4285 dev_hold(mlxsw_sp_port->dev);
4286 rcu_read_unlock();
4287 return mlxsw_sp_port;
4288}
4289
4290void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4291{
4292 dev_put(mlxsw_sp_port->dev);
4293}
4294
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004295static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004296{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004297 char sldr_pl[MLXSW_REG_SLDR_LEN];
4298
4299 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4300 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4301}
4302
4303static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4304{
4305 char sldr_pl[MLXSW_REG_SLDR_LEN];
4306
4307 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4308 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4309}
4310
4311static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4312 u16 lag_id, u8 port_index)
4313{
4314 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4315 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4316
4317 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4318 lag_id, port_index);
4319 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4320}
4321
4322static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4323 u16 lag_id)
4324{
4325 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4326 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4327
4328 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4329 lag_id);
4330 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4331}
4332
4333static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4334 u16 lag_id)
4335{
4336 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4337 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4338
4339 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4340 lag_id);
4341 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4342}
4343
4344static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4345 u16 lag_id)
4346{
4347 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4348 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4349
4350 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4351 lag_id);
4352 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4353}
4354
4355static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4356 struct net_device *lag_dev,
4357 u16 *p_lag_id)
4358{
4359 struct mlxsw_sp_upper *lag;
4360 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004361 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004362 int i;
4363
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004364 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4365 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004366 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4367 if (lag->ref_count) {
4368 if (lag->dev == lag_dev) {
4369 *p_lag_id = i;
4370 return 0;
4371 }
4372 } else if (free_lag_id < 0) {
4373 free_lag_id = i;
4374 }
4375 }
4376 if (free_lag_id < 0)
4377 return -EBUSY;
4378 *p_lag_id = free_lag_id;
4379 return 0;
4380}
4381
4382static bool
4383mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4384 struct net_device *lag_dev,
David Aherne58376e2017-10-04 17:48:51 -07004385 struct netdev_lag_upper_info *lag_upper_info,
4386 struct netlink_ext_ack *extack)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004387{
4388 u16 lag_id;
4389
David Aherne58376e2017-10-04 17:48:51 -07004390 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004391 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004392 return false;
David Aherne58376e2017-10-04 17:48:51 -07004393 }
4394 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004395 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004396 return false;
David Aherne58376e2017-10-04 17:48:51 -07004397 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004398 return true;
4399}
4400
4401static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4402 u16 lag_id, u8 *p_port_index)
4403{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004404 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004405 int i;
4406
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004407 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4408 MAX_LAG_MEMBERS);
4409 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004410 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4411 *p_port_index = i;
4412 return 0;
4413 }
4414 }
4415 return -EBUSY;
4416}
4417
4418static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4419 struct net_device *lag_dev)
4420{
4421 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004422 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004423 struct mlxsw_sp_upper *lag;
4424 u16 lag_id;
4425 u8 port_index;
4426 int err;
4427
4428 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4429 if (err)
4430 return err;
4431 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4432 if (!lag->ref_count) {
4433 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4434 if (err)
4435 return err;
4436 lag->dev = lag_dev;
4437 }
4438
4439 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4440 if (err)
4441 return err;
4442 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4443 if (err)
4444 goto err_col_port_add;
4445 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4446 if (err)
4447 goto err_col_port_enable;
4448
4449 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4450 mlxsw_sp_port->local_port);
4451 mlxsw_sp_port->lag_id = lag_id;
4452 mlxsw_sp_port->lagged = 1;
4453 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004454
Ido Schimmelc57529e2017-05-26 08:37:31 +02004455 /* Port is no longer usable as a router interface */
4456 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4457 if (mlxsw_sp_port_vlan->fid)
Ido Schimmela1107482017-05-26 08:37:39 +02004458 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004459
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004460 return 0;
4461
Ido Schimmel51554db2016-05-06 22:18:39 +02004462err_col_port_enable:
4463 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004464err_col_port_add:
4465 if (!lag->ref_count)
4466 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004467 return err;
4468}
4469
Ido Schimmel82e6db02016-06-20 23:04:04 +02004470static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4471 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004472{
4473 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004474 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004475 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004476
4477 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004478 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004479 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4480 WARN_ON(lag->ref_count == 0);
4481
Ido Schimmel82e6db02016-06-20 23:04:04 +02004482 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4483 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004484
Ido Schimmelc57529e2017-05-26 08:37:31 +02004485 /* Any VLANs configured on the port are no longer valid */
4486 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004487
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004488 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004489 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004490
4491 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4492 mlxsw_sp_port->local_port);
4493 mlxsw_sp_port->lagged = 0;
4494 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004495
Ido Schimmelc57529e2017-05-26 08:37:31 +02004496 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4497 /* Make sure untagged frames are allowed to ingress */
4498 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004499}
4500
Jiri Pirko74581202015-12-03 12:12:30 +01004501static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4502 u16 lag_id)
4503{
4504 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4505 char sldr_pl[MLXSW_REG_SLDR_LEN];
4506
4507 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4508 mlxsw_sp_port->local_port);
4509 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4510}
4511
4512static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4513 u16 lag_id)
4514{
4515 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4516 char sldr_pl[MLXSW_REG_SLDR_LEN];
4517
4518 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4519 mlxsw_sp_port->local_port);
4520 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4521}
4522
4523static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4524 bool lag_tx_enabled)
4525{
4526 if (lag_tx_enabled)
4527 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4528 mlxsw_sp_port->lag_id);
4529 else
4530 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4531 mlxsw_sp_port->lag_id);
4532}
4533
4534static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4535 struct netdev_lag_lower_state_info *info)
4536{
4537 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4538}
4539
Jiri Pirko2b94e582017-04-18 16:55:37 +02004540static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4541 bool enable)
4542{
4543 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4544 enum mlxsw_reg_spms_state spms_state;
4545 char *spms_pl;
4546 u16 vid;
4547 int err;
4548
4549 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4550 MLXSW_REG_SPMS_STATE_DISCARDING;
4551
4552 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4553 if (!spms_pl)
4554 return -ENOMEM;
4555 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4556
4557 for (vid = 0; vid < VLAN_N_VID; vid++)
4558 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4559
4560 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4561 kfree(spms_pl);
4562 return err;
4563}
4564
4565static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4566{
Yuval Mintzfccff082017-12-15 08:44:21 +01004567 u16 vid = 1;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004568 int err;
4569
Ido Schimmel4aafc362017-05-26 08:37:25 +02004570 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004571 if (err)
4572 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02004573 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4574 if (err)
4575 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004576 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4577 true, false);
4578 if (err)
4579 goto err_port_vlan_set;
Yuval Mintzfccff082017-12-15 08:44:21 +01004580
4581 for (; vid <= VLAN_N_VID - 1; vid++) {
4582 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4583 vid, false);
4584 if (err)
4585 goto err_vid_learning_set;
4586 }
4587
Jiri Pirko2b94e582017-04-18 16:55:37 +02004588 return 0;
4589
Yuval Mintzfccff082017-12-15 08:44:21 +01004590err_vid_learning_set:
4591 for (vid--; vid >= 1; vid--)
4592 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004593err_port_vlan_set:
4594 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004595err_port_stp_set:
4596 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004597 return err;
4598}
4599
4600static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4601{
Yuval Mintzfccff082017-12-15 08:44:21 +01004602 u16 vid;
4603
4604 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4605 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4606 vid, true);
4607
Jiri Pirko2b94e582017-04-18 16:55:37 +02004608 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4609 false, false);
4610 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004611 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004612}
4613
Ido Schimmel1c30d182018-10-17 08:53:31 +00004614static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev)
4615{
4616 unsigned int num_vxlans = 0;
4617 struct net_device *dev;
4618 struct list_head *iter;
4619
4620 netdev_for_each_lower_dev(br_dev, dev, iter) {
4621 if (netif_is_vxlan(dev))
4622 num_vxlans++;
4623 }
4624
4625 return num_vxlans > 1;
4626}
4627
4628static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev,
4629 struct netlink_ext_ack *extack)
4630{
4631 if (br_multicast_enabled(br_dev)) {
4632 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device");
4633 return false;
4634 }
4635
4636 if (br_vlan_enabled(br_dev)) {
4637 NL_SET_ERR_MSG_MOD(extack, "VLAN filtering can not be enabled on a bridge with a VxLAN device");
4638 return false;
4639 }
4640
4641 if (mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) {
4642 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge");
4643 return false;
4644 }
4645
4646 return true;
4647}
4648
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004649static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4650 struct net_device *dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004651 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004652{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004653 struct netdev_notifier_changeupper_info *info;
4654 struct mlxsw_sp_port *mlxsw_sp_port;
David Aherne58376e2017-10-04 17:48:51 -07004655 struct netlink_ext_ack *extack;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004656 struct net_device *upper_dev;
4657 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004658 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004659
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004660 mlxsw_sp_port = netdev_priv(dev);
4661 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4662 info = ptr;
David Aherne58376e2017-10-04 17:48:51 -07004663 extack = netdev_notifier_info_to_extack(&info->info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004664
4665 switch (event) {
4666 case NETDEV_PRECHANGEUPPER:
4667 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004668 if (!is_vlan_dev(upper_dev) &&
4669 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004670 !netif_is_bridge_master(upper_dev) &&
Ido Schimmelc5516182018-07-14 11:39:51 +03004671 !netif_is_ovs_master(upper_dev) &&
4672 !netif_is_macvlan(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004673 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004674 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004675 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004676 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004677 break;
Ido Schimmel1c30d182018-10-17 08:53:31 +00004678 if (netif_is_bridge_master(upper_dev) &&
4679 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
4680 mlxsw_sp_bridge_has_vxlan(upper_dev) &&
4681 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
4682 return -EOPNOTSUPP;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004683 if (netdev_has_any_upper_dev(upper_dev) &&
4684 (!netif_is_bridge_master(upper_dev) ||
4685 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4686 upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004687 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004688 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004689 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004690 if (netif_is_lag_master(upper_dev) &&
4691 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
David Aherne58376e2017-10-04 17:48:51 -07004692 info->upper_info, extack))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004693 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004694 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004695 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004696 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004697 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004698 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004699 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004700 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004701 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004702 }
Ido Schimmelc5516182018-07-14 11:39:51 +03004703 if (netif_is_macvlan(upper_dev) &&
4704 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, lower_dev)) {
4705 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4706 return -EOPNOTSUPP;
4707 }
David Aherne58376e2017-10-04 17:48:51 -07004708 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004709 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004710 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004711 }
4712 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004713 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004714 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004715 }
Petr Machata47bf9df2018-05-27 09:48:41 +03004716 if (is_vlan_dev(upper_dev) &&
4717 vlan_dev_vlan_id(upper_dev) == 1) {
4718 NL_SET_ERR_MSG_MOD(extack, "Creating a VLAN device with VID 1 is unsupported: VLAN 1 carries untagged traffic");
4719 return -EINVAL;
4720 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004721 break;
4722 case NETDEV_CHANGEUPPER:
4723 upper_dev = info->upper_dev;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004724 if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004725 if (info->linking)
4726 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004727 lower_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004728 upper_dev,
4729 extack);
Ido Schimmel7117a572016-06-20 23:04:06 +02004730 else
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004731 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4732 lower_dev,
4733 upper_dev);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004734 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004735 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004736 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4737 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004738 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004739 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4740 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004741 } else if (netif_is_ovs_master(upper_dev)) {
4742 if (info->linking)
4743 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4744 else
4745 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Ido Schimmel2db99372018-07-14 11:39:52 +03004746 } else if (netif_is_macvlan(upper_dev)) {
4747 if (!info->linking)
4748 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004749 }
4750 break;
4751 }
4752
Ido Schimmel80bedf12016-06-20 23:03:59 +02004753 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004754}
4755
Jiri Pirko74581202015-12-03 12:12:30 +01004756static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4757 unsigned long event, void *ptr)
4758{
4759 struct netdev_notifier_changelowerstate_info *info;
4760 struct mlxsw_sp_port *mlxsw_sp_port;
4761 int err;
4762
4763 mlxsw_sp_port = netdev_priv(dev);
4764 info = ptr;
4765
4766 switch (event) {
4767 case NETDEV_CHANGELOWERSTATE:
4768 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4769 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4770 info->lower_state_info);
4771 if (err)
4772 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4773 }
4774 break;
4775 }
4776
Ido Schimmel80bedf12016-06-20 23:03:59 +02004777 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004778}
4779
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004780static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4781 struct net_device *port_dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004782 unsigned long event, void *ptr)
4783{
4784 switch (event) {
4785 case NETDEV_PRECHANGEUPPER:
4786 case NETDEV_CHANGEUPPER:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004787 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4788 event, ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004789 case NETDEV_CHANGELOWERSTATE:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004790 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4791 ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004792 }
4793
Ido Schimmel80bedf12016-06-20 23:03:59 +02004794 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004795}
4796
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004797static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4798 unsigned long event, void *ptr)
4799{
4800 struct net_device *dev;
4801 struct list_head *iter;
4802 int ret;
4803
4804 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4805 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004806 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4807 ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004808 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004809 return ret;
4810 }
4811 }
4812
Ido Schimmel80bedf12016-06-20 23:03:59 +02004813 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004814}
4815
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004816static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4817 struct net_device *dev,
4818 unsigned long event, void *ptr,
4819 u16 vid)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004820{
4821 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel90045fc2017-12-25 09:05:33 +01004822 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004823 struct netdev_notifier_changeupper_info *info = ptr;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004824 struct netlink_ext_ack *extack;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004825 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004826 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004827
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004828 extack = netdev_notifier_info_to_extack(&info->info);
4829
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004830 switch (event) {
4831 case NETDEV_PRECHANGEUPPER:
4832 upper_dev = info->upper_dev;
Ido Schimmelc5516182018-07-14 11:39:51 +03004833 if (!netif_is_bridge_master(upper_dev) &&
4834 !netif_is_macvlan(upper_dev)) {
4835 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
Ido Schimmel80bedf12016-06-20 23:03:59 +02004836 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004837 }
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004838 if (!info->linking)
4839 break;
Ido Schimmel1c30d182018-10-17 08:53:31 +00004840 if (netif_is_bridge_master(upper_dev) &&
4841 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
4842 mlxsw_sp_bridge_has_vxlan(upper_dev) &&
4843 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
4844 return -EOPNOTSUPP;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004845 if (netdev_has_any_upper_dev(upper_dev) &&
4846 (!netif_is_bridge_master(upper_dev) ||
4847 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4848 upper_dev))) {
Arkadi Sharshevsky6c677752018-02-13 11:29:05 +01004849 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004850 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004851 }
Ido Schimmelc5516182018-07-14 11:39:51 +03004852 if (netif_is_macvlan(upper_dev) &&
4853 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) {
4854 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4855 return -EOPNOTSUPP;
4856 }
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004857 break;
4858 case NETDEV_CHANGEUPPER:
4859 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004860 if (netif_is_bridge_master(upper_dev)) {
4861 if (info->linking)
Ido Schimmelc57529e2017-05-26 08:37:31 +02004862 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4863 vlan_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004864 upper_dev,
4865 extack);
Ido Schimmel1f880612017-03-10 08:53:35 +01004866 else
Ido Schimmelc57529e2017-05-26 08:37:31 +02004867 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4868 vlan_dev,
4869 upper_dev);
Ido Schimmel2db99372018-07-14 11:39:52 +03004870 } else if (netif_is_macvlan(upper_dev)) {
4871 if (!info->linking)
4872 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004873 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004874 err = -EINVAL;
4875 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004876 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004877 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004878 }
4879
Ido Schimmel80bedf12016-06-20 23:03:59 +02004880 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004881}
4882
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004883static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4884 struct net_device *lag_dev,
4885 unsigned long event,
4886 void *ptr, u16 vid)
Ido Schimmel272c4472015-12-15 16:03:47 +01004887{
4888 struct net_device *dev;
4889 struct list_head *iter;
4890 int ret;
4891
4892 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4893 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004894 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4895 event, ptr,
4896 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004897 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004898 return ret;
4899 }
4900 }
4901
Ido Schimmel80bedf12016-06-20 23:03:59 +02004902 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004903}
4904
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004905static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4906 unsigned long event, void *ptr)
4907{
4908 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4909 u16 vid = vlan_dev_vlan_id(vlan_dev);
4910
Ido Schimmel272c4472015-12-15 16:03:47 +01004911 if (mlxsw_sp_port_dev_check(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004912 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4913 event, ptr, vid);
Ido Schimmel272c4472015-12-15 16:03:47 +01004914 else if (netif_is_lag_master(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004915 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4916 real_dev, event,
4917 ptr, vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004918
Ido Schimmel80bedf12016-06-20 23:03:59 +02004919 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004920}
4921
Ido Schimmelc5516182018-07-14 11:39:51 +03004922static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
4923 unsigned long event, void *ptr)
4924{
4925 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev);
4926 struct netdev_notifier_changeupper_info *info = ptr;
4927 struct netlink_ext_ack *extack;
4928 struct net_device *upper_dev;
4929
4930 if (!mlxsw_sp)
4931 return 0;
4932
4933 extack = netdev_notifier_info_to_extack(&info->info);
4934
4935 switch (event) {
4936 case NETDEV_PRECHANGEUPPER:
4937 upper_dev = info->upper_dev;
4938 if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) {
4939 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4940 return -EOPNOTSUPP;
4941 }
4942 if (!info->linking)
4943 break;
4944 if (netif_is_macvlan(upper_dev) &&
4945 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, br_dev)) {
4946 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4947 return -EOPNOTSUPP;
4948 }
4949 break;
4950 case NETDEV_CHANGEUPPER:
Ido Schimmel2db99372018-07-14 11:39:52 +03004951 upper_dev = info->upper_dev;
4952 if (info->linking)
4953 break;
Ido Schimmelc3608672018-10-04 15:48:03 +00004954 if (is_vlan_dev(upper_dev))
4955 mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
Ido Schimmel2db99372018-07-14 11:39:52 +03004956 if (netif_is_macvlan(upper_dev))
4957 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
Ido Schimmelc5516182018-07-14 11:39:51 +03004958 break;
4959 }
4960
4961 return 0;
4962}
4963
4964static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev,
4965 unsigned long event, void *ptr)
4966{
4967 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
4968 struct netdev_notifier_changeupper_info *info = ptr;
4969 struct netlink_ext_ack *extack;
4970
4971 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
4972 return 0;
4973
4974 extack = netdev_notifier_info_to_extack(&info->info);
4975
4976 /* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */
4977 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4978
4979 return -EOPNOTSUPP;
4980}
4981
Ido Schimmelb1e45522017-04-30 19:47:14 +03004982static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4983{
4984 struct netdev_notifier_changeupper_info *info = ptr;
4985
4986 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4987 return false;
4988 return netif_is_l3_master(info->upper_dev);
4989}
4990
Ido Schimmel1c30d182018-10-17 08:53:31 +00004991static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp,
4992 struct net_device *dev,
4993 unsigned long event, void *ptr)
4994{
4995 struct netdev_notifier_changeupper_info *cu_info;
4996 struct netdev_notifier_info *info = ptr;
4997 struct netlink_ext_ack *extack;
4998 struct net_device *upper_dev;
4999
5000 extack = netdev_notifier_info_to_extack(info);
5001
5002 switch (event) {
5003 case NETDEV_CHANGEUPPER:
5004 cu_info = container_of(info,
5005 struct netdev_notifier_changeupper_info,
5006 info);
5007 upper_dev = cu_info->upper_dev;
5008 if (!netif_is_bridge_master(upper_dev))
5009 return 0;
5010 if (!mlxsw_sp_lower_get(upper_dev))
5011 return 0;
5012 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
5013 return -EOPNOTSUPP;
5014 if (cu_info->linking) {
5015 if (!netif_running(dev))
5016 return 0;
5017 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev,
5018 dev, extack);
5019 } else {
5020 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, upper_dev, dev);
5021 }
5022 break;
5023 case NETDEV_PRE_UP:
5024 upper_dev = netdev_master_upper_dev_get(dev);
5025 if (!upper_dev)
5026 return 0;
5027 if (!netif_is_bridge_master(upper_dev))
5028 return 0;
5029 if (!mlxsw_sp_lower_get(upper_dev))
5030 return 0;
5031 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev,
5032 extack);
5033 case NETDEV_DOWN:
5034 upper_dev = netdev_master_upper_dev_get(dev);
5035 if (!upper_dev)
5036 return 0;
5037 if (!netif_is_bridge_master(upper_dev))
5038 return 0;
5039 if (!mlxsw_sp_lower_get(upper_dev))
5040 return 0;
5041 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, upper_dev, dev);
5042 break;
5043 }
5044
5045 return 0;
5046}
5047
Petr Machata00635872017-10-16 16:26:37 +02005048static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005049 unsigned long event, void *ptr)
5050{
5051 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Petr Machata079c9f32018-02-27 14:53:44 +01005052 struct mlxsw_sp_span_entry *span_entry;
Petr Machata00635872017-10-16 16:26:37 +02005053 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02005054 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005055
Petr Machata00635872017-10-16 16:26:37 +02005056 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
Petr Machata079c9f32018-02-27 14:53:44 +01005057 if (event == NETDEV_UNREGISTER) {
5058 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
5059 if (span_entry)
5060 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
5061 }
Petr Machata803335a2018-02-27 14:53:46 +01005062 mlxsw_sp_span_respin(mlxsw_sp);
Petr Machata079c9f32018-02-27 14:53:44 +01005063
Ido Schimmel1c30d182018-10-17 08:53:31 +00005064 if (netif_is_vxlan(dev))
5065 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr);
Petr Machata796ec772017-11-03 10:03:29 +01005066 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
5067 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
5068 event, ptr);
Petr Machata61481f22017-11-03 10:03:41 +01005069 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
5070 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
5071 event, ptr);
Petr Machata00635872017-10-16 16:26:37 +02005072 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
Ido Schimmel6e095fd2016-07-04 08:23:13 +02005073 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03005074 else if (mlxsw_sp_is_vrf_event(event, ptr))
5075 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02005076 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02005077 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02005078 else if (netif_is_lag_master(dev))
5079 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
5080 else if (is_vlan_dev(dev))
5081 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Ido Schimmelc5516182018-07-14 11:39:51 +03005082 else if (netif_is_bridge_master(dev))
5083 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
5084 else if (netif_is_macvlan(dev))
5085 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005086
Ido Schimmel80bedf12016-06-20 23:03:59 +02005087 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005088}
5089
David Ahern89d5dd22017-10-18 09:56:55 -07005090static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
5091 .notifier_call = mlxsw_sp_inetaddr_valid_event,
5092};
5093
Ido Schimmel99724c12016-07-04 08:23:14 +02005094static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
5095 .notifier_call = mlxsw_sp_inetaddr_event,
David Ahern89d5dd22017-10-18 09:56:55 -07005096};
5097
5098static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
5099 .notifier_call = mlxsw_sp_inet6addr_valid_event,
Ido Schimmel99724c12016-07-04 08:23:14 +02005100};
5101
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005102static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
5103 .notifier_call = mlxsw_sp_inet6addr_event,
5104};
5105
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03005106static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02005107 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
5108 {0, },
5109};
5110
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03005111static struct pci_driver mlxsw_sp1_pci_driver = {
5112 .name = mlxsw_sp1_driver_name,
5113 .id_table = mlxsw_sp1_pci_id_table,
5114};
5115
5116static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
5117 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0},
5118 {0, },
5119};
5120
5121static struct pci_driver mlxsw_sp2_pci_driver = {
5122 .name = mlxsw_sp2_driver_name,
5123 .id_table = mlxsw_sp2_pci_id_table,
Jiri Pirko1d20d232016-10-27 15:12:59 +02005124};
5125
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005126static int __init mlxsw_sp_module_init(void)
5127{
5128 int err;
5129
David Ahern89d5dd22017-10-18 09:56:55 -07005130 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02005131 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005132 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005133 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02005134
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03005135 err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005136 if (err)
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03005137 goto err_sp1_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02005138
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03005139 err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
Jiri Pirko1d20d232016-10-27 15:12:59 +02005140 if (err)
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03005141 goto err_sp2_core_driver_register;
5142
5143 err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
5144 if (err)
5145 goto err_sp1_pci_driver_register;
5146
5147 err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
5148 if (err)
5149 goto err_sp2_pci_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02005150
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005151 return 0;
5152
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03005153err_sp2_pci_driver_register:
5154 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
5155err_sp1_pci_driver_register:
5156 mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
5157err_sp2_core_driver_register:
5158 mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
5159err_sp1_core_driver_register:
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005160 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005161 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02005162 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005163 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005164 return err;
5165}
5166
5167static void __exit mlxsw_sp_module_exit(void)
5168{
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03005169 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
5170 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
5171 mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
5172 mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02005173 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005174 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02005175 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07005176 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005177}
5178
5179module_init(mlxsw_sp_module_init);
5180module_exit(mlxsw_sp_module_exit);
5181
5182MODULE_LICENSE("Dual BSD/GPL");
5183MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
5184MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirkoc3ab4352018-07-18 11:14:45 +03005185MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
5186MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
Jiri Pirkoabfd6182018-07-08 23:51:26 +03005187MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);